diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in index a9eba100f3..a2c5772ee6 100644 --- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in @@ -255,7 +255,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 2 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE int default 64 diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 9e5ace4640..001ed9f471 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -146,9 +146,9 @@ #define SOC_CPU_INTR_NUM 32 #define SOC_CPU_HAS_FPU 1 -#define SOC_CPU_BREAKPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes /*-------------------------- DAC CAPS ----------------------------------------*/ #define SOC_DAC_CHAN_NUM 2 diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 3fbd0ffb7e..fb5fc3781d 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -195,7 +195,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 2 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE hex default 0x80000000 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index 8752196a22..94e4a0a779 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -92,9 +92,9 @@ #define SOC_CPU_INTR_NUM 32 #define SOC_CPU_HAS_FLEXIBLE_INTC 1 -#define SOC_CPU_BREAKPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index a0dbdb144e..62642a88c9 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -283,7 +283,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 8 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE hex default 0x80000000 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index c60f688b7c..519b022cb8 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -124,9 +124,9 @@ #define SOC_CPU_INTR_NUM 32 #define SOC_CPU_HAS_FLEXIBLE_INTC 1 -#define SOC_CPU_BREAKPOINTS_NUM 8 -#define SOC_CPU_WATCHPOINTS_NUM 8 -#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 8 +#define SOC_CPU_WATCHPOINTS_NUM 8 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ /** The maximum length of a Digital Signature in bits. */ diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 3bd19bcd5a..356eb7ac3c 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -339,7 +339,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 4 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE hex default 0x80000000 diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 5081a69a4c..283f07ff09 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -138,9 +138,9 @@ #define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller -#define SOC_CPU_BREAKPOINTS_NUM 4 -#define SOC_CPU_WATCHPOINTS_NUM 4 -#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes #define SOC_CPU_HAS_PMA 1 #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index cc4654abc6..dfaafd809c 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -327,7 +327,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 4 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE hex default 0x80000000 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 2b3b27ac2c..9107c6df52 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -136,9 +136,9 @@ #define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller -#define SOC_CPU_BREAKPOINTS_NUM 4 -#define SOC_CPU_WATCHPOINTS_NUM 4 -#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINTS_NUM 4 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes #define SOC_CPU_HAS_PMA 1 #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index 3857f0efac..d39fdbe123 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -295,7 +295,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 2 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE int default 64 diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 00db84c258..7331ca2b7e 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -133,9 +133,9 @@ #define SOC_CPU_CORES_NUM (1U) #define SOC_CPU_INTR_NUM 32 -#define SOC_CPU_BREAKPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes /*-------------------------- DAC CAPS ----------------------------------------*/ #define SOC_DAC_CHAN_NUM 2 diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index b572636fb6..30cc237866 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -339,7 +339,7 @@ config SOC_CPU_WATCHPOINTS_NUM int default 2 -config SOC_CPU_WATCHPOINT_SIZE +config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE int default 64 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 746e915698..b79d604a9d 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -127,9 +127,9 @@ #define SOC_CPU_INTR_NUM 32 #define SOC_CPU_HAS_FPU 1 -#define SOC_CPU_BREAKPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINTS_NUM 2 -#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes +#define SOC_CPU_BREAKPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64 // bytes /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ /** The maximum length of a Digital Signature in bits. */