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cache_err_int: Modify cache error interrupt panic code format

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This commit is contained in:
Li Shuai
2019-07-31 13:49:21 +08:00
parent ce6c86672b
commit eb4c0ef8b2
1 changed files with 3 additions and 4 deletions
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7
components/esp32s2beta/panic.c
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@@ -197,7 +197,7 @@ static inline void printCacheError(void)
status[0] = REG_READ(DPORT_CACHE_DBG_STATUS0_REG); status[0] = REG_READ(DPORT_CACHE_DBG_STATUS0_REG);
status[1] = REG_READ(DPORT_CACHE_DBG_STATUS1_REG); status[1] = REG_READ(DPORT_CACHE_DBG_STATUS1_REG);
for (int i = 0; i < 32; i++) { for (int i = 0; i < 32; i++) {
switch (status[0] & (1 << (i&0x1f))) switch (status[0] & BIT(i))
{ {
case DPORT_IC_SYNC_SIZE_FAULT_ST: case DPORT_IC_SYNC_SIZE_FAULT_ST:
vaddr = REG_READ(DPORT_PRO_ICACHE_MEM_SYNC0_REG); vaddr = REG_READ(DPORT_PRO_ICACHE_MEM_SYNC0_REG);
@@ -230,7 +230,7 @@ static inline void printCacheError(void)
default: default:
break; break;
} }
switch (status[1] & (1 << (i&0x1f))) switch (status[1] & BIT(i))
{ {
case DPORT_DC_SYNC_SIZE_FAULT_ST: case DPORT_DC_SYNC_SIZE_FAULT_ST:
vaddr = REG_READ(DPORT_PRO_DCACHE_MEM_SYNC0_REG); vaddr = REG_READ(DPORT_PRO_DCACHE_MEM_SYNC0_REG);
@@ -369,8 +369,7 @@ void panicHandler(XtExcFrame *frame)
panicPutStr("DebugIntr "); panicPutStr("DebugIntr ");
} }
panicPutStr("\r\n"); panicPutStr("\r\n");
} } else if (frame->exccause == PANIC_RSN_CACHEERR) {
else if (frame->exccause == PANIC_RSN_CACHEERR) {
panicPutStr(" ^~~~~~~~~~~~~~~\r\n"); panicPutStr(" ^~~~~~~~~~~~~~~\r\n");
printCacheError(); printCacheError();
} }