From ec373b51b864f7522aacedbc86fb924acf1ebac2 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Wed, 19 Mar 2025 22:00:09 +0800 Subject: [PATCH] fix(uart): correct C3/S3 module enable porcedure to avoid undesired line noise --- components/hal/esp32c3/include/hal/uart_ll.h | 2 ++ components/hal/esp32s3/include/hal/uart_ll.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index 3292045bbb..d937792977 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -107,12 +107,14 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) // ESP32C3 requires a workaround: enable core reset before enabling uart module clock to prevent uart output garbage value switch (uart_num) { case 0: + SYSTEM.perip_rst_en0.reg_uart_rst = 0; UART0.clk_conf.rst_core = 1; SYSTEM.perip_rst_en0.reg_uart_rst = 1; SYSTEM.perip_rst_en0.reg_uart_rst = 0; UART0.clk_conf.rst_core = 0; break; case 1: + SYSTEM.perip_rst_en0.reg_uart1_rst = 0; UART1.clk_conf.rst_core = 1; SYSTEM.perip_rst_en0.reg_uart1_rst = 1; SYSTEM.perip_rst_en0.reg_uart1_rst = 0; diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index 0380c7338b..b207815ae1 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -112,18 +112,21 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) // ESP32S3 requires a workaround: enable core reset before enabling uart module clock to prevent uart output garbage value switch (uart_num) { case 0: + SYSTEM.perip_rst_en0.uart_rst = 0; UART0.clk_conf.rst_core = 1; SYSTEM.perip_rst_en0.uart_rst = 1; SYSTEM.perip_rst_en0.uart_rst = 0; UART0.clk_conf.rst_core = 0; break; case 1: + SYSTEM.perip_rst_en0.uart1_rst = 0; UART1.clk_conf.rst_core = 1; SYSTEM.perip_rst_en0.uart1_rst = 1; SYSTEM.perip_rst_en0.uart1_rst = 0; UART1.clk_conf.rst_core = 0; break; case 2: + SYSTEM.perip_rst_en1.uart2_rst = 0; UART2.clk_conf.rst_core = 1; SYSTEM.perip_rst_en1.uart2_rst = 1; SYSTEM.perip_rst_en1.uart2_rst = 0;