espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-10-31 07:01:43 +01:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feature/esp32c5beta3_light_sleep_support_stage_1' into 'master'

Browse Source 
feat(esp_hw_support): esp32c5 sleep support (Stage 2: support basic pmu sleep function)

See merge request espressif/esp-idf!29549
This commit is contained in:
Wu Zheng Hui
2024-04-11 10:38:17 +08:00
parent 4e79288891 2c59c4fbf2
commit ec37cbf157
36 changed files with 1286 additions and 198 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
View File

@@ -99,6 +99,18 @@ config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_PMU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
bool
default y
config SOC_LP_AON_SUPPORTED
bool
default y
config SOC_LP_PERIPHERALS_SUPPORTED
bool
default y
@@ -523,6 +535,14 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
config SOC_LP_TIMER_BIT_WIDTH_HI
int
default 16
config SOC_TIMER_GROUPS
int
default 2
@@ -643,6 +663,22 @@ config SOC_PM_SUPPORT_RTC_PERIPH_PD
bool
default y
config SOC_PM_SUPPORT_PMU_MODEM_STATE
bool
default n
config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
bool
default y
config SOC_PM_CPU_RETENTION_BY_SW
bool
default y
config SOC_PM_PAU_LINK_NUM
int
default 4
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool
default y

77
components/soc/esp32c5/beta3/include/soc/clint_reg.h Normal file
View File

@@ -0,0 +1,77 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/*CLINT MINT*/
#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: .*/
#define CLINT_CPU_MINT_SIP BIT(0)
#define CLINT_CPU_MINT_SIP_M BIT(0)
#define CLINT_CPU_MINT_SIP_V 1
#define CLINT_CPU_MINT_SIP_S 0
#define CLINT_MINT_MTIMECMP_L_REG (DR_REG_CLINT_M_BASE + 0x4000)
/* CLINT_CPU_MINT_MTIMECMP_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIMECMP_L 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_L_M ((CLINT_CPU_MINT_MTIMECMP_L_V)<<(CLINT_CPU_MINT_MTIMECMP_L_S))
#define CLINT_CPU_MINT_MTIMECMP_L_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_L_S 0
#define CLINT_MINT_MTIMECMP_H_REG (DR_REG_CLINT_M_BASE + 0x4004)
/* CLINT_CPU_MINT_MTIMECMP_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIMECMP_H 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_M ((CLINT_CPU_MINT_MTIMECMP_H_V)<<(CLINT_CPU_MINT_MTIMECMP_H_S))
#define CLINT_CPU_MINT_MTIMECMP_H_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIMECMP_H_S 0
#define CLINT_MINT_TIMECTL_REG (DR_REG_CLINT_M_BASE + 0x4010)
/* CLINT_MINT_SAMPLING_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
/*description: .*/
#define CLINT_MINT_SAMPLING_MODE 0x00000003
#define CLINT_MINT_SAMPLING_MODE_M ((CLINT_CPU_MINT_TIMECTL_V)<<(CLINT_CPU_MINT_TIMECTL_S))
#define CLINT_MINT_SAMPLING_MODE_V 0x3
#define CLINT_MINT_SAMPLING_MODE_S 4
/* CLINT_MINT_COUNTER_OVERFLOW : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define CLINT_MINT_COUNTER_OVERFLOW (BIT(3))
#define CLINT_MINT_COUNTER_OVERFLOW_M (BIT(3))
#define CLINT_MINT_COUNTER_OVERFLOW_V 0x1
#define CLINT_MINT_COUNTER_OVERFLOW_S 3
/* CLINT_MINT_COUNTER_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define CLINT_MINT_COUNTER_EN (BIT(0))
#define CLINT_MINT_COUNTER_EN_M (BIT(0))
#define CLINT_MINT_COUNTER_EN_V 0x1
#define CLINT_MINT_COUNTER_EN_S 0
#define CLINT_MINT_MTIME_L_REG (DR_REG_CLINT_M_BASE + 0xBFF8)
/* CLINT_CPU_MINT_MTIME_L : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIME_L 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_M ((CLINT_CPU_MINT_MTIME_L_V)<<(CLINT_CPU_MINT_MTIME_L_S))
#define CLINT_CPU_MINT_MTIME_L_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_L_S 0
#define CLINT_MINT_MTIME_H_REG (DR_REG_CLINT_M_BASE + 0xBFFC)
/* CLINT_CPU_MINT_MTIME_H : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: .*/
#define CLINT_CPU_MINT_MTIME_H 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_H_M ((CLINT_CPU_MINT_MTIME_H_V)<<(CLINT_CPU_MINT_MTIME_H_S))
#define CLINT_CPU_MINT_MTIME_H_V 0xFFFFFFFF
#define CLINT_CPU_MINT_MTIME_H_S 0
#ifdef __cplusplus
}
#endif

4
components/soc/esp32c5/beta3/include/soc/hp_system_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -71,7 +71,7 @@ extern "C" {
* 0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
* the number, the stronger the ability to resist DPA attacks and the higher the
* security level, but it will increase the computational overhead of the hardware
* crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0.
* crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
*/
#define HP_SYS_SEC_DPA_LEVEL 0x00000003U
#define HP_SYS_SEC_DPA_LEVEL_M (HP_SYS_SEC_DPA_LEVEL_V << HP_SYS_SEC_DPA_LEVEL_S)

2
components/soc/esp32c5/beta3/include/soc/periph_defs.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

4
components/soc/esp32c5/beta3/include/soc/pmu_struct.h
View File

@@ -554,7 +554,9 @@ typedef union {
typedef union {
struct {
uint32_t reserved0 : 26;
uint32_t reserved0 : 24;
uint32_t xpd_tc5g_i2c : 1;
uint32_t xpd_rx5g_i2c : 1;
uint32_t perif_i2c_rstb: 1;
uint32_t xpd_perif_i2c : 1;
uint32_t xpd_txrf_i2c : 1;

2
components/soc/esp32c5/beta3/include/soc/reg_base.h
View File

@@ -72,6 +72,7 @@
#define DR_REG_MODEM_PWR_BASE 0x600AD000
#define DR_REG_I2C_ANA_MST_BASE 0x600AF800
#define PWDET_CONF_REG 0x600A0810
/**
* @brief LP System (RTC) Modules
*
@@ -101,3 +102,4 @@
#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000
#define DR_REG_INTPRI_BASE 0x600C5000
#define DR_REG_CACHE_BASE 0x600C8000 // CACHE_CONFIG/EXTMEM
#define DR_REG_CLINT_M_BASE 0x20000000

20
components/soc/esp32c5/beta3/include/soc/soc_caps.h
View File

@@ -59,10 +59,10 @@
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
#define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
#define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
#define SOC_LP_PERIPHERALS_SUPPORTED 1
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634
#define SOC_ULP_SUPPORTED 1
@@ -431,8 +431,8 @@
// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)
@@ -524,17 +524,17 @@
// #define SOC_PM_SUPPORT_MAC_BB_PD (1)
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
// #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
#define SOC_PM_SUPPORT_PMU_MODEM_STATE (0)
/* macro redefine for pass esp_wifi headers md5sum check */
// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
#define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
// #define SOC_PM_CPU_RETENTION_BY_SW (1)
#define SOC_PM_CPU_RETENTION_BY_SW (1)
// #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
// #define SOC_PM_RETENTION_HAS_CLOCK_BUG (1)
// #define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_LINK_NUM (4)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)

10
components/soc/esp32c5/beta3/include/soc/tee_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -670,10 +670,10 @@ extern "C" {
/** TEE_DATE_REG : R/W; bitpos: [27:0]; default: 35725664;
* reg_tee_date
*/
#define TEE_DATE_REG 0x0FFFFFFFU
#define TEE_DATE_REG_M (TEE_DATE_REG_V << TEE_DATE_REG_S)
#define TEE_DATE_REG_V 0x0FFFFFFFU
#define TEE_DATE_REG_S 0
#define TEE_DATE 0x0FFFFFFFU
#define TEE_DATE_M (TEE_DATE_V << TEE_DATE_S)
#define TEE_DATE_V 0x0FFFFFFFU
#define TEE_DATE_S 0
#ifdef __cplusplus
}