diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index 587498bb75..d0ed5f7a0f 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -10,6 +10,7 @@ #include "sdkconfig.h" #include "esp_attr.h" #include "soc/soc.h" +#include "soc/soc_caps.h" #include "freertos/FreeRTOS.h" #include "hal/clk_gate_ll.h" #include "esp_private/esp_modem_clock.h" @@ -19,17 +20,23 @@ // Please define the frequently called modules in the low bit, // which will improve the execution efficiency typedef enum { - MODEM_CLOCK_FE = BIT(0), - MODEM_CLOCK_COEXIST = BIT(1), - MODEM_CLOCK_I2C_MASTER = BIT(2), - MODEM_CLOCK_WIFI_MAC = BIT(3), - MODEM_CLOCK_WIFI_BB = BIT(4), - MODEM_CLOCK_ETM = BIT(5), - MODEM_CLOCK_BLE_MAC = BIT(6), - MODEM_CLOCK_BLE_BB = BIT(7), - MODEM_CLOCK_802154_MAC = BIT(8), - MODEM_CLOCK_DATADUMP = BIT(9), - MODEM_CLOCK_DEVICE_MAX = 10 + MODEM_CLOCK_FE, + MODEM_CLOCK_COEXIST, + MODEM_CLOCK_I2C_MASTER, +#if SOC_WIFI_SUPPORTED + MODEM_CLOCK_WIFI_MAC, + MODEM_CLOCK_WIFI_BB, +#endif + MODEM_CLOCK_ETM, +#if SOC_BT_SUPPORTED + MODEM_CLOCK_BLE_MAC, + MODEM_CLOCK_BLE_BB, +#endif +#if SOC_IEEE802154_SUPPORTED + MODEM_CLOCK_802154_MAC, +#endif + MODEM_CLOCK_DATADUMP, + MODEM_CLOCK_DEVICE_MAX } modem_clock_device_t; @@ -46,6 +53,7 @@ typedef struct modem_clock_context { } modem_clock_context_t; +#if SOC_WIFI_SUPPORTED static void IRAM_ATTR modem_clock_wifi_mac_configure(modem_clock_context_t *ctx, bool enable) { if (enable) { @@ -60,7 +68,9 @@ static void IRAM_ATTR modem_clock_wifi_bb_configure(modem_clock_context_t *ctx, modem_syscon_ll_clk_wifibb_configure(ctx->hal->syscon_dev, enable); } } +#endif // SOC_WIFI_SUPPORTED +#if SOC_BT_SUPPORTED static void IRAM_ATTR modem_clock_ble_mac_configure(modem_clock_context_t *ctx, bool enable) { modem_syscon_ll_enable_etm_clock(ctx->hal->syscon_dev, enable); @@ -74,11 +84,16 @@ static void IRAM_ATTR modem_clock_ble_bb_configure(modem_clock_context_t *ctx, b modem_syscon_ll_enable_bt_clock(ctx->hal->syscon_dev, enable); } +#endif // SOC_BT_SUPPORTED + +#if SOC_IEEE802154_SUPPORTED static void IRAM_ATTR modem_clock_ieee802154_mac_configure(modem_clock_context_t *ctx, bool enable) { + modem_syscon_ll_enable_etm_clock(ctx->hal->syscon_dev, enable); modem_syscon_ll_enable_ieee802154_apb_clock(ctx->hal->syscon_dev, enable); modem_syscon_ll_enable_ieee802154_mac_clock(ctx->hal->syscon_dev, enable); } +#endif // SOC_IEEE802154_SUPPORTED static void IRAM_ATTR modem_clock_coex_configure(modem_clock_context_t *ctx, bool enable) { @@ -87,12 +102,7 @@ static void IRAM_ATTR modem_clock_coex_configure(modem_clock_context_t *ctx, boo static void IRAM_ATTR modem_clock_fe_configure(modem_clock_context_t *ctx, bool enable) { - if (enable) { - modem_syscon_ll_enable_fe_apb_clock(ctx->hal->syscon_dev, enable); - modem_syscon_ll_enable_fe_cal_160m_clock(ctx->hal->syscon_dev, enable); - modem_syscon_ll_enable_fe_160m_clock(ctx->hal->syscon_dev, enable); - modem_syscon_ll_enable_fe_80m_clock(ctx->hal->syscon_dev, enable); - } + modem_clock_hal_enable_fe_clock(ctx->hal, enable); } static void IRAM_ATTR modem_clock_i2c_master_configure(modem_clock_context_t *ctx, bool enable) @@ -118,22 +128,29 @@ modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(voi static DRAM_ATTR modem_clock_context_t modem_clock_context = { .hal = &modem_clock_hal, .lock = portMUX_INITIALIZER_UNLOCKED, .dev = { - { .refs = 0, .configure = modem_clock_fe_configure }, - { .refs = 0, .configure = modem_clock_coex_configure }, - { .refs = 0, .configure = modem_clock_i2c_master_configure }, - { .refs = 0, .configure = modem_clock_wifi_mac_configure }, - { .refs = 0, .configure = modem_clock_wifi_bb_configure }, - { .refs = 0, .configure = modem_clock_etm_configure }, - { .refs = 0, .configure = modem_clock_ble_mac_configure }, - { .refs = 0, .configure = modem_clock_ble_bb_configure }, - { .refs = 0, .configure = modem_clock_ieee802154_mac_configure }, - { .refs = 0, .configure = modem_clock_data_dump_configure } + [MODEM_CLOCK_FE] = { .refs = 0, .configure = modem_clock_fe_configure }, + [MODEM_CLOCK_COEXIST] = { .refs = 0, .configure = modem_clock_coex_configure }, + [MODEM_CLOCK_I2C_MASTER] = { .refs = 0, .configure = modem_clock_i2c_master_configure }, +#if SOC_WIFI_SUPPORTED + [MODEM_CLOCK_WIFI_MAC] = { .refs = 0, .configure = modem_clock_wifi_mac_configure }, + [MODEM_CLOCK_WIFI_BB] = { .refs = 0, .configure = modem_clock_wifi_bb_configure }, +#endif + [MODEM_CLOCK_ETM] = { .refs = 0, .configure = modem_clock_etm_configure }, +#if SOC_BT_SUPPORTED + [MODEM_CLOCK_BLE_MAC] = { .refs = 0, .configure = modem_clock_ble_mac_configure }, + [MODEM_CLOCK_BLE_BB] = { .refs = 0, .configure = modem_clock_ble_bb_configure }, +#endif +#if SOC_IEEE802154_SUPPORTED + [MODEM_CLOCK_802154_MAC] = { .refs = 0, .configure = modem_clock_ieee802154_mac_configure }, +#endif + [MODEM_CLOCK_DATADUMP] = { .refs = 0, .configure = modem_clock_data_dump_configure } }, .lpclk_src = { [0 ... PERIPH_MODEM_MODULE_NUM - 1] = MODEM_CLOCK_LPCLK_SRC_INVALID } }; return &modem_clock_context; } +#if SOC_PM_SUPPORT_PMU_MODEM_STATE static void IRAM_ATTR modem_clock_domain_power_state_icg_map_init(modem_clock_context_t *ctx) { #define ICG_NOGATING_SLEEP (BIT(PMU_HP_ICG_MODEM_CODE_SLEEP)) @@ -159,11 +176,11 @@ static void IRAM_ATTR modem_clock_domain_power_state_icg_map_init(modem_clock_co } } - void modem_clock_domain_pmu_state_icg_map_init(void) { modem_clock_domain_power_state_icg_map_init(MODEM_CLOCK_instance()); } +#endif // #if SOC_PM_SUPPORT_PMU_MODEM_STATE static void IRAM_ATTR modem_clock_device_enable(modem_clock_context_t *ctx, uint32_t dev_map) { @@ -197,33 +214,40 @@ static void IRAM_ATTR modem_clock_device_disable(modem_clock_context_t *ctx, uin assert(refs >= 0); } -#define WIFI_CLOCK_DEPS (MODEM_CLOCK_WIFI_MAC | MODEM_CLOCK_FE | MODEM_CLOCK_WIFI_BB | MODEM_CLOCK_COEXIST) -#define BLE_CLOCK_DEPS (MODEM_CLOCK_BLE_MAC | MODEM_CLOCK_FE | MODEM_CLOCK_BLE_BB | MODEM_CLOCK_ETM | MODEM_CLOCK_COEXIST) -#define IEEE802154_CLOCK_DEPS (MODEM_CLOCK_802154_MAC | MODEM_CLOCK_FE | MODEM_CLOCK_BLE_BB | MODEM_CLOCK_ETM | MODEM_CLOCK_COEXIST) -#define COEXIST_CLOCK_DEPS (MODEM_CLOCK_COEXIST) -#define PHY_CLOCK_DEPS (MODEM_CLOCK_I2C_MASTER | MODEM_CLOCK_FE) +#define WIFI_CLOCK_DEPS (BIT(MODEM_CLOCK_WIFI_MAC) | BIT(MODEM_CLOCK_FE) | BIT(MODEM_CLOCK_WIFI_BB) | BIT(MODEM_CLOCK_COEXIST)) +#define BLE_CLOCK_DEPS (BIT(MODEM_CLOCK_BLE_MAC) | BIT(MODEM_CLOCK_FE) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST)) +#define IEEE802154_CLOCK_DEPS (BIT(MODEM_CLOCK_802154_MAC) | BIT(MODEM_CLOCK_FE) | BIT(MODEM_CLOCK_BLE_BB) | BIT(MODEM_CLOCK_ETM) | BIT(MODEM_CLOCK_COEXIST)) +#define COEXIST_CLOCK_DEPS (BIT(MODEM_CLOCK_COEXIST)) +#define PHY_CLOCK_DEPS (BIT(MODEM_CLOCK_I2C_MASTER) | BIT(MODEM_CLOCK_FE)) + +static inline uint32_t modem_clock_get_module_deps(periph_module_t module) +{ + uint32_t deps = 0; + if (module == PERIPH_PHY_MODULE) {deps = PHY_CLOCK_DEPS;} + else if (module == PERIPH_COEX_MODULE) { deps = COEXIST_CLOCK_DEPS; } +#if SOC_WIFI_SUPPORTED + else if (module == PERIPH_WIFI_MODULE) { deps = WIFI_CLOCK_DEPS; } +#endif +#if SOC_BT_SUPPORTED + else if (module == PERIPH_BT_MODULE) { deps = BLE_CLOCK_DEPS; } +#endif +#if SOC_IEEE802154_SUPPORTED + else if (module == PERIPH_IEEE802154_MODULE) { deps = IEEE802154_CLOCK_DEPS; } +#endif + return deps; +} void IRAM_ATTR modem_clock_module_enable(periph_module_t module) { assert(IS_MODEM_MODULE(module)); - const int deps = (module == PERIPH_WIFI_MODULE) ? WIFI_CLOCK_DEPS \ - : (module == PERIPH_BT_MODULE) ? BLE_CLOCK_DEPS \ - : (module == PERIPH_IEEE802154_MODULE) ? IEEE802154_CLOCK_DEPS \ - : (module == PERIPH_COEX_MODULE) ? COEXIST_CLOCK_DEPS \ - : (module == PERIPH_PHY_MODULE) ? PHY_CLOCK_DEPS \ - : 0; + uint32_t deps = modem_clock_get_module_deps(module); modem_clock_device_enable(MODEM_CLOCK_instance(), deps); } void IRAM_ATTR modem_clock_module_disable(periph_module_t module) { assert(IS_MODEM_MODULE(module)); - const int deps = (module == PERIPH_WIFI_MODULE) ? WIFI_CLOCK_DEPS \ - : (module == PERIPH_BT_MODULE) ? BLE_CLOCK_DEPS \ - : (module == PERIPH_IEEE802154_MODULE) ? IEEE802154_CLOCK_DEPS \ - : (module == PERIPH_COEX_MODULE) ? COEXIST_CLOCK_DEPS \ - : (module == PERIPH_PHY_MODULE) ? PHY_CLOCK_DEPS \ - : 0; + uint32_t deps = modem_clock_get_module_deps(module); modem_clock_device_disable(MODEM_CLOCK_instance(), deps); } @@ -233,18 +257,24 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); switch (module) { +#if SOC_WIFI_SUPPORTED case PERIPH_WIFI_MODULE: modem_clock_hal_deselect_all_wifi_lpclk_source(MODEM_CLOCK_instance()->hal); modem_clock_hal_select_wifi_lpclk_source(MODEM_CLOCK_instance()->hal, src); modem_lpcon_ll_set_wifi_lpclk_divisor_value(MODEM_CLOCK_instance()->hal->lpcon_dev, divider); modem_lpcon_ll_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, true); break; +#endif // SOC_WIFI_SUPPORTED + +#if SOC_BT_SUPPORTED case PERIPH_BT_MODULE: - modem_clock_hal_deselect_all_lp_timer_lpclk_source(MODEM_CLOCK_instance()->hal); - modem_clock_hal_select_lp_timer_lpclk_source(MODEM_CLOCK_instance()->hal, src); - modem_lpcon_ll_set_lp_timer_divisor_value(MODEM_CLOCK_instance()->hal->lpcon_dev, divider); - modem_lpcon_ll_enable_lp_timer_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, true); + modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(MODEM_CLOCK_instance()->hal); + modem_clock_hal_select_ble_rtc_timer_lpclk_source(MODEM_CLOCK_instance()->hal, src); + modem_clock_hal_set_ble_rtc_timer_divisor_value(MODEM_CLOCK_instance()->hal, divider); + modem_clock_hal_enable_ble_rtc_timer_clock(MODEM_CLOCK_instance()->hal, true); break; +#endif // SOC_BT_SUPPORTED + case PERIPH_COEX_MODULE: modem_clock_hal_deselect_all_coex_lpclk_source(MODEM_CLOCK_instance()->hal); modem_clock_hal_select_coex_lpclk_source(MODEM_CLOCK_instance()->hal, src); @@ -258,6 +288,7 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = src; portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); +#if !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6267 /* The power domain of the low-power clock source required by the modem * module remains powered on during sleep */ esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \ @@ -274,6 +305,9 @@ void modem_clock_select_lp_clock_source(periph_module_t module, modem_clock_lpcl : ESP_PD_DOMAIN_MAX); esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF); esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON); +#else + (void)last_src; // Only for bypass compile warning, delete if IDF-6267 resloved +#endif //!CONFIG_IDF_TARGET_ESP32H2 } void modem_clock_deselect_lp_clock_source(periph_module_t module) @@ -282,14 +316,19 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module) portENTER_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); switch (module) { +#if SOC_WIFI_SUPPORTED case PERIPH_WIFI_MODULE: modem_clock_hal_deselect_all_wifi_lpclk_source(MODEM_CLOCK_instance()->hal); modem_lpcon_ll_enable_wifipwr_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, false); break; +#endif // SOC_WIFI_SUPPORTED + +#if SOC_BT_SUPPORTED case PERIPH_BT_MODULE: - modem_clock_hal_deselect_all_lp_timer_lpclk_source(MODEM_CLOCK_instance()->hal); - modem_lpcon_ll_enable_lp_timer_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, false); + modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(MODEM_CLOCK_instance()->hal); + modem_clock_hal_enable_ble_rtc_timer_clock(MODEM_CLOCK_instance()->hal, false); break; +#endif // SOC_BT_SUPPORTED case PERIPH_COEX_MODULE: modem_clock_hal_deselect_all_coex_lpclk_source(MODEM_CLOCK_instance()->hal); // modem_lpcon_ll_enable_coex_clock(MODEM_CLOCK_instance()->hal->lpcon_dev, false); // TODO: IDF-5727 @@ -301,6 +340,7 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module) MODEM_CLOCK_instance()->lpclk_src[module - PERIPH_MODEM_MODULE_MIN] = MODEM_CLOCK_LPCLK_SRC_INVALID; portEXIT_CRITICAL_SAFE(&MODEM_CLOCK_instance()->lock); +#if !CONFIG_IDF_TARGET_ESP32H2 // TODO: IDF-6267 esp_sleep_pd_domain_t pd_domain = (esp_sleep_pd_domain_t) ( \ (last_src == MODEM_CLOCK_LPCLK_SRC_RC_FAST) ? ESP_PD_DOMAIN_RC_FAST \ : (last_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) ? ESP_PD_DOMAIN_XTAL \ @@ -308,4 +348,7 @@ void modem_clock_deselect_lp_clock_source(periph_module_t module) : (last_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) ? ESP_PD_DOMAIN_XTAL32K \ : ESP_PD_DOMAIN_MAX); esp_sleep_pd_config(pd_domain, ESP_PD_OPTION_OFF); +#else + (void)last_src; // Only for bypass compile warning, delete if IDF-6267 resloved +#endif //!CONFIG_IDF_TARGET_ESP32H2 } diff --git a/components/hal/esp32c6/include/hal/modem_lpcon_ll.h b/components/hal/esp32c6/include/hal/modem_lpcon_ll.h index 57ca3bd71c..e6c754005d 100644 --- a/components/hal/esp32c6/include/hal/modem_lpcon_ll.h +++ b/components/hal/esp32c6/include/hal/modem_lpcon_ll.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -// The LL layer for ESP32-C6 MODEM SYSCON register operations +// The LL layer for ESP32-C6 MODEM LPCON register operations #pragma once @@ -25,37 +25,37 @@ static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en } __attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_lp_timer_slow_osc(modem_lpcon_dev_t *hw, bool en) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(modem_lpcon_dev_t *hw, bool en) { hw->lp_timer_conf.clk_lp_timer_sel_osc_slow = en; } __attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_lp_timer_fast_osc(modem_lpcon_dev_t *hw, bool en) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(modem_lpcon_dev_t *hw, bool en) { hw->lp_timer_conf.clk_lp_timer_sel_osc_fast = en; } __attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_lp_timer_main_xtal(modem_lpcon_dev_t *hw, bool en) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(modem_lpcon_dev_t *hw, bool en) { hw->lp_timer_conf.clk_lp_timer_sel_xtal = en; } __attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_lp_timer_32k_xtal(modem_lpcon_dev_t *hw, bool en) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(modem_lpcon_dev_t *hw, bool en) { hw->lp_timer_conf.clk_lp_timer_sel_xtal32k = en; } __attribute__((always_inline)) -static inline void modem_lpcon_ll_set_lp_timer_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +static inline void modem_lpcon_ll_set_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) { hw->lp_timer_conf.clk_lp_timer_div_num = value; } __attribute__((always_inline)) -static inline uint32_t modem_lpcon_ll_get_lp_timer_divisor_value(modem_lpcon_dev_t *hw) +static inline uint32_t modem_lpcon_ll_get_ble_rtc_timer_divisor_value(modem_lpcon_dev_t *hw) { return hw->lp_timer_conf.clk_lp_timer_div_num; } @@ -163,7 +163,7 @@ static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, } __attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_lp_timer_clock(modem_lpcon_dev_t *hw, bool en) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en) { hw->clk_conf.clk_lp_timer_en = en; } @@ -187,7 +187,7 @@ static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_ } __attribute__((always_inline)) -static inline void modem_lpcon_ll_enable_lp_timer_force_clock(modem_lpcon_dev_t *hw, bool en) +static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en) { hw->clk_conf_force_on.clk_lp_timer_fo = en; } diff --git a/components/hal/esp32c6/modem_clock_hal.c b/components/hal/esp32c6/modem_clock_hal.c index 7cbe2bf820..449006b701 100644 --- a/components/hal/esp32c6/modem_clock_hal.c +++ b/components/hal/esp32c6/modem_clock_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -58,39 +58,59 @@ void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, } } -void modem_clock_hal_deselect_all_lp_timer_lpclk_source(modem_clock_hal_context_t *hal) +void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable) { - modem_lpcon_ll_enable_lp_timer_slow_osc(hal->lpcon_dev, false); - modem_lpcon_ll_enable_lp_timer_fast_osc(hal->lpcon_dev, false); - modem_lpcon_ll_enable_lp_timer_32k_xtal(hal->lpcon_dev, false); - modem_lpcon_ll_enable_lp_timer_main_xtal(hal->lpcon_dev, false); + if (enable) { + modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_cal_160m_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_160m_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_80m_clock(hal->syscon_dev, enable); + } } -void modem_clock_hal_select_lp_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) +void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider) +{ + modem_lpcon_ll_set_ble_rtc_timer_divisor_value(hal->lpcon_dev, divider); +} + +void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable) +{ + modem_lpcon_ll_enable_ble_rtc_timer_clock(hal->lpcon_dev, enable); +} + +void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal) +{ + modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, false); + modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(hal->lpcon_dev, false); +} + +void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) { HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); switch (src) { case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: - modem_lpcon_ll_enable_lp_timer_slow_osc(hal->lpcon_dev, true); + modem_lpcon_ll_enable_ble_rtc_timer_slow_osc(hal->lpcon_dev, true); break; case MODEM_CLOCK_LPCLK_SRC_RC_FAST: - modem_lpcon_ll_enable_lp_timer_fast_osc(hal->lpcon_dev, true); + modem_lpcon_ll_enable_ble_rtc_timer_fast_osc(hal->lpcon_dev, true); break; case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: - modem_lpcon_ll_enable_lp_timer_main_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_enable_ble_rtc_timer_main_xtal(hal->lpcon_dev, true); break; case MODEM_CLOCK_LPCLK_SRC_RC32K: - modem_lpcon_ll_enable_lp_timer_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true); modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_RC32K_CODE); break; case MODEM_CLOCK_LPCLK_SRC_XTAL32K: - modem_lpcon_ll_enable_lp_timer_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true); modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_XTAL32K_CODE); break; case MODEM_CLOCK_LPCLK_SRC_EXT32K: - modem_lpcon_ll_enable_lp_timer_32k_xtal(hal->lpcon_dev, true); + modem_lpcon_ll_enable_ble_rtc_timer_32k_xtal(hal->lpcon_dev, true); modem_lpcon_ll_select_modem_32k_clock_source(hal->lpcon_dev, MODEM_CLOCK_EXT32K_CODE); break; default: diff --git a/components/hal/esp32h2/include/hal/lp_clkrst_ll.h b/components/hal/esp32h2/include/hal/lp_clkrst_ll.h new file mode 100644 index 0000000000..fcb46921ec --- /dev/null +++ b/components/hal/esp32h2/include/hal/lp_clkrst_ll.h @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H2 LP CLKRST register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "soc/lp_clkrst_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(lp_clkrst_dev_t *hw, bool en) +{ + hw->lpperi.lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(lp_clkrst_dev_t *hw, bool en) +{ + hw->lpperi.lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(lp_clkrst_dev_t *hw, bool en) +{ + hw->lpperi.lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(lp_clkrst_dev_t *hw, bool en) +{ + hw->lpperi.lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void lp_clkrst_ll_set_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw, uint32_t value) +{ + hw->lpperi.lp_bletimer_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw) +{ + return hw->lpperi.lp_bletimer_div_num; +} + +__attribute__((always_inline)) +static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src) +{ + hw->lpperi.lp_bletimer_32k_sel = src; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/modem_lpcon_ll.h b/components/hal/esp32h2/include/hal/modem_lpcon_ll.h new file mode 100644 index 0000000000..78956cfbb6 --- /dev/null +++ b/components/hal/esp32h2/include/hal/modem_lpcon_ll.h @@ -0,0 +1,114 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H2 MODEM LPCON register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "hal/assert.h" +#include "modem/modem_lpcon_struct.h" +#include "hal/modem_clock_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en) +{ + hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value) +{ + hw->coex_lp_clk_conf.clk_coex_lp_div_num = value; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw) +{ + return hw->coex_lp_clk_conf.clk_coex_lp_div_num; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_coex_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_i2c_mst_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_fe_mem_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_fe_mem_en = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_coex_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_i2c_mst_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_enable_fe_mem_force_clock(modem_lpcon_dev_t *hw, bool en) +{ + hw->clk_conf_force_on.clk_fe_mem_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw) +{ + hw->rst_conf.val = 0xf; + hw->rst_conf.val = 0; +} + +__attribute__((always_inline)) +static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw) +{ + return hw->date.val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/include/hal/modem_syscon_ll.h b/components/hal/esp32h2/include/hal/modem_syscon_ll.h new file mode 100644 index 0000000000..618e88f95d --- /dev/null +++ b/components/hal/esp32h2/include/hal/modem_syscon_ll.h @@ -0,0 +1,276 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-H2 MODEM SYSCON register operations + +#pragma once + +#include +#include "soc/soc.h" +#include "hal/assert.h" +#include "modem/modem_syscon_struct.h" +#include "hal/modem_clock_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en) +{ + hw->test_conf.clk_en = en; +} + + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en) +{ + // ESP32H2 Not Support +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_etm_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zb_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_zb_mac_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_modem_sec_en = en; + hw->clk_conf.clk_modem_sec_ecb_en = en; + hw->clk_conf.clk_modem_sec_ccm_en = en; + hw->clk_conf.clk_modem_sec_bah_en = en; + hw->clk_conf.clk_modem_sec_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_apb(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_ble_timer_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_ble_timer_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf.clk_data_dump_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_etm_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_modem_sec_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_ble_timer_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw) +{ + hw->clk_conf_force_on.clk_data_dump_fo = 1; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_fe = 1; + hw->modem_rst_conf.rst_fe = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac_apb = 1; + hw->modem_rst_conf.rst_btmac_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btmac = 1; + hw->modem_rst_conf.rst_btmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb_apb = 1; + hw->modem_rst_conf.rst_btbb_apb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_btbb = 1; + hw->modem_rst_conf.rst_btbb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_etm = 1; + hw->modem_rst_conf.rst_etm = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_zbmac = 1; + hw->modem_rst_conf.rst_zbmac = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_ecb(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_ecb = 1; + hw->modem_rst_conf.rst_modem_ecb = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_ccm(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_ccm = 1; + hw->modem_rst_conf.rst_modem_ccm = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_bah(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_bah = 1; + hw->modem_rst_conf.rst_modem_bah = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_modem_sec = 1; + hw->modem_rst_conf.rst_modem_sec = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_ble_timer = 1; + hw->modem_rst_conf.rst_ble_timer = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.rst_data_dump = 1; + hw->modem_rst_conf.rst_data_dump = 0; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw) +{ + hw->modem_rst_conf.val = 0xffffffff; + hw->modem_rst_conf.val = 0; +} + + +__attribute__((always_inline)) +static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask) +{ + if(en){ + hw->clk_conf1.val = hw->clk_conf1.val | mask; + } else { + hw->clk_conf1.val = hw->clk_conf1.val & ~mask; + } +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_16m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_16m_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_32m_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_32m_en = en; +} + + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_sdm_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_sdm_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_adc_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_adc_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_fe_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_bt_apb_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1.clk_bt_en = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_fe_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_fe_fo = en; +} + +__attribute__((always_inline)) +static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en) +{ + hw->clk_conf1_force_on.clk_bt_fo = en; +} + +__attribute__((always_inline)) +static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw) +{ + return hw->date.val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32h2/modem_clock_hal.c b/components/hal/esp32h2/modem_clock_hal.c new file mode 100644 index 0000000000..eb77e7b45b --- /dev/null +++ b/components/hal/esp32h2/modem_clock_hal.c @@ -0,0 +1,120 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The HAL layer for MODEM CLOCK (ESP32-H2 specific part) +#include +#include "esp_attr.h" +#include "soc/soc.h" +#include "hal/modem_clock_hal.h" +#include "hal/lp_clkrst_ll.h" +#include "hal/modem_clock_types.h" +#include "hal/assert.h" + +typedef enum { + MODEM_CLOCK_XTAL32K_CODE = 0, + MODEM_CLOCK_RC32K_CODE = 1, + MODEM_CLOCK_EXT32K_CODE = 2 +} modem_clock_32k_clk_src_code_t; + +void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable) +{ + modem_lpcon_ll_enable_fe_mem_clock(hal->lpcon_dev, enable); + modem_syscon_ll_enable_fe_sdm_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable); + modem_syscon_ll_enable_fe_16m_clock(hal->syscon_dev, enable); +} + +void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider) +{ + lp_clkrst_ll_set_ble_rtc_timer_divisor_value(&LP_CLKRST, divider); +} + +void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable) +{ + // No clock gate on ESP32-H2 +} + +void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal) +{ + lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, false); + lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, false); + lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, false); + lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, false); +} + +void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) +{ + HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); + + switch (src) + { + case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: + lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC_FAST: + lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, true); + break; + case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: + lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC32K: + lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true); + lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_XTAL32K: + lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true); + lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_EXT32K: + lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true); + lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE); + break; + default: + break; + } +} + +void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal) +{ + modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, false); + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, false); + modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, false); +} + +void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src) +{ + HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX); + + switch (src) + { + case MODEM_CLOCK_LPCLK_SRC_RC_SLOW: + modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC_FAST: + modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL: + modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, true); + break; + case MODEM_CLOCK_LPCLK_SRC_RC32K: + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true); + lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_XTAL32K: + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true); + lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE); + break; + case MODEM_CLOCK_LPCLK_SRC_EXT32K: + modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true); + lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE); + break; + default: + break; + } +} diff --git a/components/hal/esp32c6/include/hal/modem_clock_hal.h b/components/hal/include/hal/modem_clock_hal.h similarity index 56% rename from components/hal/esp32c6/include/hal/modem_clock_hal.h rename to components/hal/include/hal/modem_clock_hal.h index bbd6866fc8..9912308f5e 100644 --- a/components/hal/esp32c6/include/hal/modem_clock_hal.h +++ b/components/hal/include/hal/modem_clock_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ extern "C" { #endif +#include "soc/soc_caps.h" #include "hal/modem_syscon_ll.h" #include "hal/modem_lpcon_ll.h" #include "hal/modem_clock_types.h" @@ -21,19 +22,26 @@ typedef struct { modem_lpcon_dev_t *lpcon_dev; } modem_clock_hal_context_t; +#if MAC_SUPPORT_PMU_MODEM_STATE void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap); +#endif -void modem_clock_hal_select_lp_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable); -void modem_clock_hal_deselect_all_lp_timer_lpclk_source(modem_clock_hal_context_t *hal); +#if SOC_BT_SUPPORTED +void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider); +void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable); +void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); +void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal); +#endif void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); - void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal); +#if SOC_WIFI_SUPPORTED void modem_clock_hal_select_wifi_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src); - void modem_clock_hal_deselect_all_wifi_lpclk_source(modem_clock_hal_context_t *hal); +#endif #ifdef __cplusplus } diff --git a/components/soc/esp32c6/include/soc/periph_defs.h b/components/soc/esp32c6/include/soc/periph_defs.h index 28bbdb8a46..6ec855cd57 100644 --- a/components/soc/esp32c6/include/soc/periph_defs.h +++ b/components/soc/esp32c6/include/soc/periph_defs.h @@ -42,6 +42,7 @@ typedef enum { PERIPH_SARADC_MODULE, PERIPH_TEMPSENSOR_MODULE, PERIPH_REGDMA_MODULE, +/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ PERIPH_WIFI_MODULE, PERIPH_BT_MODULE, PERIPH_IEEE802154_MODULE, diff --git a/components/soc/esp32h2/include/modem/modem_lpcon_struct.h b/components/soc/esp32h2/include/modem/modem_lpcon_struct.h new file mode 100644 index 0000000000..6e57c6f5f4 --- /dev/null +++ b/components/soc/esp32h2/include/modem/modem_lpcon_struct.h @@ -0,0 +1,124 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef union { + struct { + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} modem_lpcon_test_conf_reg_t; + +typedef union { + struct { + uint32_t clk_coex_lp_sel_osc_slow:1; + uint32_t clk_coex_lp_sel_osc_fast:1; + uint32_t clk_coex_lp_sel_xtal:1; + uint32_t clk_coex_lp_sel_xtal32k:1; + uint32_t clk_coex_lp_div_num:12; + uint32_t reserved_16:16; + }; + uint32_t val; +} modem_lpcon_coex_lp_clk_conf_reg_t; + +typedef union { + struct { + uint32_t reserved_0:1; + uint32_t clk_coex_en:1; + uint32_t clk_i2c_mst_en:1; + uint32_t reserved_3:2; + uint32_t clk_fe_mem_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} modem_lpcon_clk_conf_reg_t; + +typedef union { + struct { + uint32_t reserved_0:1; + uint32_t clk_coex_fo:1; + uint32_t clk_i2c_mst_fo:1; + uint32_t reserved_3:2; + uint32_t clk_fe_mem_fo:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} modem_lpcon_clk_conf_force_on_reg_t; + +typedef union { + struct { + uint32_t pwr_tick_target:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} modem_lpcon_tick_conf_reg_t; + +typedef union { + struct { + uint32_t reserved_0:1; + uint32_t rst_coex:1; + uint32_t rst_i2c_mst:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} modem_lpcon_rst_conf_reg_t; + +typedef union { + struct { + uint32_t reserved_0:2; + uint32_t agc_mem_force_pu:1; + uint32_t agc_mem_force_pd:1; + uint32_t pbus_mem_force_pu:1; + uint32_t pbus_mem_force_pd:1; + uint32_t reserved_6:2; + uint32_t i2c_mst_mem_force_pu:1; + uint32_t i2c_mst_mem_force_pd:1; + uint32_t chan_freq_mem_force_pu:1; + uint32_t chan_freq_mem_force_pd:1; + uint32_t modem_pwr_mem_wp:3; + uint32_t modem_pwr_mem_wa:3; + uint32_t modem_pwr_mem_ra:2; + uint32_t modem_pwr_mem_rm:4; + uint32_t reserved_24:8; + }; + uint32_t val; +} modem_lpcon_mem_conf_reg_t; + +typedef union { + struct { + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} modem_lpcon_date_reg_t; + + +typedef struct { + volatile modem_lpcon_test_conf_reg_t test_conf; + volatile modem_lpcon_coex_lp_clk_conf_reg_t coex_lp_clk_conf; + volatile modem_lpcon_clk_conf_reg_t clk_conf; + volatile modem_lpcon_clk_conf_force_on_reg_t clk_conf_force_on; + volatile modem_lpcon_tick_conf_reg_t tick_conf; + volatile modem_lpcon_rst_conf_reg_t rst_conf; + volatile modem_lpcon_mem_conf_reg_t mem_conf; + volatile modem_lpcon_date_reg_t date; +} modem_lpcon_dev_t; + +extern modem_lpcon_dev_t MODEM_LPCON; + +#ifndef __cplusplus +_Static_assert(sizeof(modem_lpcon_dev_t) == 0x20, "Invalid size of modem_lpcon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/modem/modem_syscon_reg.h b/components/soc/esp32h2/include/modem/modem_syscon_reg.h index aad78ebf38..b44ec31a70 100644 --- a/components/soc/esp32h2/include/modem/modem_syscon_reg.h +++ b/components/soc/esp32h2/include/modem/modem_syscon_reg.h @@ -2,7 +2,7 @@ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 - *//*description: */ + */ #pragma once #include @@ -11,278 +11,278 @@ extern "C" { #endif -#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) -/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) +/* MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; */ +/* description: .*/ #define MODEM_SYSCON_CLK_EN (BIT(0)) -#define MODEM_SYSCON_CLK_EN_M (BIT(0)) -#define MODEM_SYSCON_CLK_EN_V 0x1 +#define MODEM_SYSCON_CLK_EN_M (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S) +#define MODEM_SYSCON_CLK_EN_V 0x00000001U #define MODEM_SYSCON_CLK_EN_S 0 -#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) -/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 -/* MODEM_SYSCON_CLK_BLE_TIMER_APB_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN (BIT(29)) -#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_M (BIT(29)) -#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S 29 -/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 28 -/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 27 -/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 26 -/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 25 -/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(24)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (BIT(24)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 24 -/* MODEM_SYSCON_CLK_ZB_MAC_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_MAC_EN (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_MAC_EN_M (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_MAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZB_MAC_EN_S 23 -/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(22)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(22)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZB_APB_EN_S 22 -/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) +/* MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [21]; default: 0; */ +/* description: .*/ #define MODEM_SYSCON_CLK_ETM_EN (BIT(21)) -#define MODEM_SYSCON_CLK_ETM_EN_M (BIT(21)) -#define MODEM_SYSCON_CLK_ETM_EN_V 0x1 +#define MODEM_SYSCON_CLK_ETM_EN_M (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S) +#define MODEM_SYSCON_CLK_ETM_EN_V 0x00000001U #define MODEM_SYSCON_CLK_ETM_EN_S 21 +/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [22]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(22)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_M (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S) +#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ZB_APB_EN_S 22 +/* MODEM_SYSCON_CLK_ZB_MAC_EN : R/W; bitpos: [23]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_ZB_MAC_EN (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_MAC_EN_M (MODEM_SYSCON_CLK_ZB_MAC_EN_V << MODEM_SYSCON_CLK_ZB_MAC_EN_S) +#define MODEM_SYSCON_CLK_ZB_MAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ZB_MAC_EN_S 23 +/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [24]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(24)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 24 +/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [25]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 25 +/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [26]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 26 +/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [27]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 27 +/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [28]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 28 +/* MODEM_SYSCON_CLK_BLE_TIMER_APB_EN : R/W; bitpos: [29]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN (BIT(29)) +#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S) +#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BLE_TIMER_APB_EN_S 29 +/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 +/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 -#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) -/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 -/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 -/* MODEM_SYSCON_CLK_ZB_FO : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_FO (BIT(24)) -#define MODEM_SYSCON_CLK_ZB_FO_M (BIT(24)) -#define MODEM_SYSCON_CLK_ZB_FO_V 0x1 -#define MODEM_SYSCON_CLK_ZB_FO_S 24 -/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) +/* MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [22]; default: 0; */ +/* description: .*/ #define MODEM_SYSCON_CLK_ETM_FO (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_FO_M (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_FO_V 0x1 +#define MODEM_SYSCON_CLK_ETM_FO_M (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S) +#define MODEM_SYSCON_CLK_ETM_FO_V 0x00000001U #define MODEM_SYSCON_CLK_ETM_FO_S 22 +/* MODEM_SYSCON_CLK_ZB_FO : R/W; bitpos: [24]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_ZB_FO (BIT(24)) +#define MODEM_SYSCON_CLK_ZB_FO_M (MODEM_SYSCON_CLK_ZB_FO_V << MODEM_SYSCON_CLK_ZB_FO_S) +#define MODEM_SYSCON_CLK_ZB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ZB_FO_S 24 +/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 +/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 +/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 -#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0xC) -/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1 -#define MODEM_SYSCON_RST_DATA_DUMP_S 31 -/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_M (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_V 0x1 -#define MODEM_SYSCON_RST_BLE_TIMER_S 30 -/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_M (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_V 0x1 -#define MODEM_SYSCON_RST_MODEM_SEC_S 29 -/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_M (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_V 0x1 -#define MODEM_SYSCON_RST_MODEM_BAH_S 27 -/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1 -#define MODEM_SYSCON_RST_MODEM_CCM_S 26 -/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_M (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_V 0x1 -#define MODEM_SYSCON_RST_MODEM_ECB_S 25 -/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_M (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_V 0x1 -#define MODEM_SYSCON_RST_ZBMAC_S 24 -/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ETM (BIT(22)) -#define MODEM_SYSCON_RST_ETM_M (BIT(22)) -#define MODEM_SYSCON_RST_ETM_V 0x1 -#define MODEM_SYSCON_RST_ETM_S 22 -/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_M (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_S 18 -/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_M (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_APB_S 17 -/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_M (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_S 16 -/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_M (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_APB_S 15 -/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0xc) +/* MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; */ +/* description: .*/ #define MODEM_SYSCON_RST_FE (BIT(14)) -#define MODEM_SYSCON_RST_FE_M (BIT(14)) -#define MODEM_SYSCON_RST_FE_V 0x1 +#define MODEM_SYSCON_RST_FE_M (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S) +#define MODEM_SYSCON_RST_FE_V 0x00000001U #define MODEM_SYSCON_RST_FE_S 14 +/* MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_M (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S) +#define MODEM_SYSCON_RST_BTMAC_APB_V 0x00000001U +#define MODEM_SYSCON_RST_BTMAC_APB_S 15 +/* MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_BTMAC (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_M (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S) +#define MODEM_SYSCON_RST_BTMAC_V 0x00000001U +#define MODEM_SYSCON_RST_BTMAC_S 16 +/* MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_M (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S) +#define MODEM_SYSCON_RST_BTBB_APB_V 0x00000001U +#define MODEM_SYSCON_RST_BTBB_APB_S 17 +/* MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_BTBB (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_M (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S) +#define MODEM_SYSCON_RST_BTBB_V 0x00000001U +#define MODEM_SYSCON_RST_BTBB_S 18 +/* MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_ETM (BIT(22)) +#define MODEM_SYSCON_RST_ETM_M (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S) +#define MODEM_SYSCON_RST_ETM_V 0x00000001U +#define MODEM_SYSCON_RST_ETM_S 22 +/* MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_M (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S) +#define MODEM_SYSCON_RST_ZBMAC_V 0x00000001U +#define MODEM_SYSCON_RST_ZBMAC_S 24 +/* MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_M (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S) +#define MODEM_SYSCON_RST_MODEM_ECB_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_ECB_S 25 +/* MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_M (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S) +#define MODEM_SYSCON_RST_MODEM_CCM_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_CCM_S 26 +/* MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_M (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S) +#define MODEM_SYSCON_RST_MODEM_BAH_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_BAH_S 27 +/* MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_M (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S) +#define MODEM_SYSCON_RST_MODEM_SEC_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_SEC_S 29 +/* MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_M (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S) +#define MODEM_SYSCON_RST_BLE_TIMER_V 0x00000001U +#define MODEM_SYSCON_RST_BLE_TIMER_S 30 +/* MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_M (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S) +#define MODEM_SYSCON_RST_DATA_DUMP_V 0x00000001U +#define MODEM_SYSCON_RST_DATA_DUMP_S 31 -#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) -/* MODEM_SYSCON_CLK_BT_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_EN (BIT(18)) -#define MODEM_SYSCON_CLK_BT_EN_M (BIT(18)) -#define MODEM_SYSCON_CLK_BT_EN_V 0x1 -#define MODEM_SYSCON_CLK_BT_EN_S 18 -/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(17)) -#define MODEM_SYSCON_CLK_BT_APB_EN_M (BIT(17)) -#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BT_APB_EN_S 17 -/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(16)) -#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(16)) -#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_APB_EN_S 16 -/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(15)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_M (BIT(15)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_ADC_EN_S 15 -/* MODEM_SYSCON_CLK_FE_SDM_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_SDM_EN (BIT(14)) -#define MODEM_SYSCON_CLK_FE_SDM_EN_M (BIT(14)) -#define MODEM_SYSCON_CLK_FE_SDM_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_SDM_EN_S 14 -/* MODEM_SYSCON_CLK_FE_32M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_32M_EN (BIT(13)) -#define MODEM_SYSCON_CLK_FE_32M_EN_M (BIT(13)) -#define MODEM_SYSCON_CLK_FE_32M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_32M_EN_S 13 -/* MODEM_SYSCON_CLK_FE_16M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) +/* MODEM_SYSCON_CLK_FE_16M_EN : R/W; bitpos: [12]; default: 0; */ +/* description: .*/ #define MODEM_SYSCON_CLK_FE_16M_EN (BIT(12)) -#define MODEM_SYSCON_CLK_FE_16M_EN_M (BIT(12)) -#define MODEM_SYSCON_CLK_FE_16M_EN_V 0x1 +#define MODEM_SYSCON_CLK_FE_16M_EN_M (MODEM_SYSCON_CLK_FE_16M_EN_V << MODEM_SYSCON_CLK_FE_16M_EN_S) +#define MODEM_SYSCON_CLK_FE_16M_EN_V 0x00000001U #define MODEM_SYSCON_CLK_FE_16M_EN_S 12 +/* MODEM_SYSCON_CLK_FE_32M_EN : R/W; bitpos: [13]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_FE_32M_EN (BIT(13)) +#define MODEM_SYSCON_CLK_FE_32M_EN_M (MODEM_SYSCON_CLK_FE_32M_EN_V << MODEM_SYSCON_CLK_FE_32M_EN_S) +#define MODEM_SYSCON_CLK_FE_32M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_32M_EN_S 13 +/* MODEM_SYSCON_CLK_FE_SDM_EN : R/W; bitpos: [14]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_FE_SDM_EN (BIT(14)) +#define MODEM_SYSCON_CLK_FE_SDM_EN_M (MODEM_SYSCON_CLK_FE_SDM_EN_V << MODEM_SYSCON_CLK_FE_SDM_EN_S) +#define MODEM_SYSCON_CLK_FE_SDM_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_SDM_EN_S 14 +/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W; bitpos: [15]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(15)) +#define MODEM_SYSCON_CLK_FE_ADC_EN_M (MODEM_SYSCON_CLK_FE_ADC_EN_V << MODEM_SYSCON_CLK_FE_ADC_EN_S) +#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_ADC_EN_S 15 +/* MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [16]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(16)) +#define MODEM_SYSCON_CLK_FE_APB_EN_M (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S) +#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_APB_EN_S 16 +/* MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [17]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(17)) +#define MODEM_SYSCON_CLK_BT_APB_EN_M (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S) +#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_APB_EN_S 17 +/* MODEM_SYSCON_CLK_BT_EN : R/W; bitpos: [18]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_BT_EN (BIT(18)) +#define MODEM_SYSCON_CLK_BT_EN_M (MODEM_SYSCON_CLK_BT_EN_V << MODEM_SYSCON_CLK_BT_EN_S) +#define MODEM_SYSCON_CLK_BT_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_EN_S 18 -#define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) -/* MODEM_SYSCON_CLK_BT_FO : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_FO (BIT(18)) -#define MODEM_SYSCON_CLK_BT_FO_M (BIT(18)) -#define MODEM_SYSCON_CLK_BT_FO_V 0x1 -#define MODEM_SYSCON_CLK_BT_FO_S 18 -/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ +#define MODEM_SYSCON_CLK_CONF1_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) +/* MODEM_SYSCON_CLK_FE_FO : R/W; bitpos: [16]; default: 0; */ +/* description: .*/ #define MODEM_SYSCON_CLK_FE_FO (BIT(16)) -#define MODEM_SYSCON_CLK_FE_FO_M (BIT(16)) -#define MODEM_SYSCON_CLK_FE_FO_V 0x1 +#define MODEM_SYSCON_CLK_FE_FO_M (MODEM_SYSCON_CLK_FE_FO_V << MODEM_SYSCON_CLK_FE_FO_S) +#define MODEM_SYSCON_CLK_FE_FO_V 0x00000001U #define MODEM_SYSCON_CLK_FE_FO_S 16 +/* MODEM_SYSCON_CLK_BT_FO : R/W; bitpos: [18]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_CLK_BT_FO (BIT(18)) +#define MODEM_SYSCON_CLK_BT_FO_M (MODEM_SYSCON_CLK_BT_FO_V << MODEM_SYSCON_CLK_BT_FO_S) +#define MODEM_SYSCON_CLK_BT_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_FO_S 18 -#define MODEM_SYSCON_MEM_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) -/* MODEM_SYSCON_MODEM_MEM_RA : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_MEM_RA 0x00000003 -#define MODEM_SYSCON_MODEM_MEM_RA_M ((MODEM_SYSCON_MODEM_MEM_RA_V)<<(MODEM_SYSCON_MODEM_MEM_RA_S)) -#define MODEM_SYSCON_MODEM_MEM_RA_V 0x3 -#define MODEM_SYSCON_MODEM_MEM_RA_S 6 -/* MODEM_SYSCON_MODEM_MEM_WA : R/W ;bitpos:[5:3] ;default: 3'h4 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_MEM_WA 0x00000007 -#define MODEM_SYSCON_MODEM_MEM_WA_M ((MODEM_SYSCON_MODEM_MEM_WA_V)<<(MODEM_SYSCON_MODEM_MEM_WA_S)) -#define MODEM_SYSCON_MODEM_MEM_WA_V 0x7 -#define MODEM_SYSCON_MODEM_MEM_WA_S 3 -/* MODEM_SYSCON_MODEM_MEM_WP : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_MEM_WP 0x00000007 -#define MODEM_SYSCON_MODEM_MEM_WP_M ((MODEM_SYSCON_MODEM_MEM_WP_V)<<(MODEM_SYSCON_MODEM_MEM_WP_S)) -#define MODEM_SYSCON_MODEM_MEM_WP_V 0x7 +#define MODEM_SYSCON_MEM_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) +/* MODEM_SYSCON_MODEM_MEM_WP : R/W; bitpos: [2:0]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_MODEM_MEM_WP 0x00000007U +#define MODEM_SYSCON_MODEM_MEM_WP_M (MODEM_SYSCON_MODEM_MEM_WP_V << MODEM_SYSCON_MODEM_MEM_WP_S) +#define MODEM_SYSCON_MODEM_MEM_WP_V 0x00000007U #define MODEM_SYSCON_MODEM_MEM_WP_S 0 +/* MODEM_SYSCON_MODEM_MEM_WA : R/W; bitpos: [5:3]; default: 4; */ +/* description: .*/ +#define MODEM_SYSCON_MODEM_MEM_WA 0x00000007U +#define MODEM_SYSCON_MODEM_MEM_WA_M (MODEM_SYSCON_MODEM_MEM_WA_V << MODEM_SYSCON_MODEM_MEM_WA_S) +#define MODEM_SYSCON_MODEM_MEM_WA_V 0x00000007U +#define MODEM_SYSCON_MODEM_MEM_WA_S 3 +/* MODEM_SYSCON_MODEM_MEM_RA : R/W; bitpos: [7:6]; default: 0; */ +/* description: .*/ +#define MODEM_SYSCON_MODEM_MEM_RA 0x00000003U +#define MODEM_SYSCON_MODEM_MEM_RA_M (MODEM_SYSCON_MODEM_MEM_RA_V << MODEM_SYSCON_MODEM_MEM_RA_S) +#define MODEM_SYSCON_MODEM_MEM_RA_V 0x00000003U +#define MODEM_SYSCON_MODEM_MEM_RA_S 6 -#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C) -/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2208300 ; */ -/*description: .*/ -#define MODEM_SYSCON_DATE 0x0FFFFFFF -#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S)) -#define MODEM_SYSCON_DATE_V 0xFFFFFFF +#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c) +/* MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 35685120; */ +/* description: .*/ +#define MODEM_SYSCON_DATE 0x0FFFFFFFU +#define MODEM_SYSCON_DATE_M (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S) +#define MODEM_SYSCON_DATE_V 0x0FFFFFFFU #define MODEM_SYSCON_DATE_S 0 #ifdef __cplusplus diff --git a/components/soc/esp32h2/include/modem/modem_syscon_struct.h b/components/soc/esp32h2/include/modem/modem_syscon_struct.h new file mode 100644 index 0000000000..99bd8a5ce6 --- /dev/null +++ b/components/soc/esp32h2/include/modem/modem_syscon_struct.h @@ -0,0 +1,140 @@ +/** + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +typedef union { + struct { + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} modem_syscon_test_conf_reg_t; + +typedef union { + struct { + uint32_t reserved_0:21; + uint32_t clk_etm_en:1; + uint32_t clk_zb_apb_en:1; + uint32_t clk_zb_mac_en:1; + uint32_t clk_modem_sec_ecb_en:1; + uint32_t clk_modem_sec_ccm_en:1; + uint32_t clk_modem_sec_bah_en:1; + uint32_t clk_modem_sec_apb_en:1; + uint32_t clk_modem_sec_en:1; + uint32_t clk_ble_timer_apb_en:1; + uint32_t clk_ble_timer_en:1; + uint32_t clk_data_dump_en:1; + }; + uint32_t val; +} modem_syscon_clk_conf_reg_t; + +typedef union { + struct { + uint32_t reserved_0:22; + uint32_t clk_etm_fo:1; + uint32_t reserved_23:1; + uint32_t clk_zb_fo:1; + uint32_t reserved_25:4; + uint32_t clk_modem_sec_fo:1; + uint32_t clk_ble_timer_fo:1; + uint32_t clk_data_dump_fo:1; + }; + uint32_t val; +} modem_syscon_clk_conf_force_on_reg_t; + +typedef union { + struct { + uint32_t reserved_0:14; + uint32_t rst_fe:1; + uint32_t rst_btmac_apb:1; + uint32_t rst_btmac:1; + uint32_t rst_btbb_apb:1; + uint32_t rst_btbb:1; + uint32_t reserved_19:3; + uint32_t rst_etm:1; + uint32_t reserved_23:1; + uint32_t rst_zbmac:1; + uint32_t rst_modem_ecb:1; + uint32_t rst_modem_ccm:1; + uint32_t rst_modem_bah:1; + uint32_t reserved_28:1; + uint32_t rst_modem_sec:1; + uint32_t rst_ble_timer:1; + uint32_t rst_data_dump:1; + }; + uint32_t val; +} modem_syscon_modem_rst_conf_reg_t; + +typedef union { + struct { + uint32_t reserved_0:12; + uint32_t clk_fe_16m_en:1; + uint32_t clk_fe_32m_en:1; + uint32_t clk_fe_sdm_en:1; + uint32_t clk_fe_adc_en:1; + uint32_t clk_fe_apb_en:1; + uint32_t clk_bt_apb_en:1; + uint32_t clk_bt_en:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} modem_syscon_clk_conf1_reg_t; + +typedef union { + struct { + uint32_t reserved_0:16; + uint32_t clk_fe_fo:1; + uint32_t reserved_17:1; + uint32_t clk_bt_fo:1; + uint32_t reserved_19:13; + }; + uint32_t val; +} modem_syscon_clk_conf1_force_on_reg_t; + +typedef union { + struct { + uint32_t modem_mem_wp:3; + uint32_t modem_mem_wa:3; + uint32_t modem_mem_ra:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} modem_syscon_mem_conf_reg_t; + +typedef union { + struct { + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} modem_syscon_date_reg_t; + + +typedef struct { + volatile modem_syscon_test_conf_reg_t test_conf; + volatile modem_syscon_clk_conf_reg_t clk_conf; + volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on; + volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf; + volatile modem_syscon_clk_conf1_reg_t clk_conf1; + volatile modem_syscon_clk_conf1_force_on_reg_t clk_conf1_force_on; + volatile modem_syscon_mem_conf_reg_t mem_conf; + volatile modem_syscon_date_reg_t date; +} modem_syscon_dev_t; + +extern modem_syscon_dev_t MODEM_SYSCON; + +#ifndef __cplusplus +_Static_assert(sizeof(modem_syscon_dev_t) == 0x20, "Invalid size of modem_syscon_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index cd989e5ae6..47ca4aab63 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -1059,6 +1059,14 @@ config SOC_PM_SUPPORT_BT_PD bool default y +config SOC_PM_SUPPORT_XTAL32K_PD + bool + default y + +config SOC_PM_SUPPORT_RC32K_PD + bool + default y + config SOC_PM_SUPPORT_RC_FAST_PD bool default y @@ -1095,6 +1103,10 @@ config SOC_CLK_LP_FAST_SUPPORT_LP_PLL bool default y +config SOC_MODEM_CLOCK_IS_INDEPENDENT + bool + default y + config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC bool default y diff --git a/components/soc/esp32h2/include/soc/periph_defs.h b/components/soc/esp32h2/include/soc/periph_defs.h index f1b20e2148..5a954b200d 100644 --- a/components/soc/esp32h2/include/soc/periph_defs.h +++ b/components/soc/esp32h2/include/soc/periph_defs.h @@ -27,11 +27,6 @@ typedef enum { PERIPH_SPI2_MODULE, //SPI2 PERIPH_TWAI0_MODULE, PERIPH_RNG_MODULE, - PERIPH_WIFI_MODULE, - PERIPH_BT_MODULE, - PERIPH_WIFI_BT_COMMON_MODULE, - PERIPH_BT_BASEBAND_MODULE, - PERIPH_BT_LC_MODULE, PERIPH_RSA_MODULE, PERIPH_AES_MODULE, PERIPH_SHA_MODULE, @@ -46,9 +41,19 @@ typedef enum { PERIPH_SYSTIMER_MODULE, PERIPH_SARADC_MODULE, PERIPH_TEMPSENSOR_MODULE, +/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */ + PERIPH_BT_MODULE, + PERIPH_IEEE802154_MODULE, + PERIPH_COEX_MODULE, + PERIPH_PHY_MODULE, PERIPH_MODULE_MAX } periph_module_t; +#define PERIPH_MODEM_MODULE_MIN PERIPH_BT_MODULE +#define PERIPH_MODEM_MODULE_MAX PERIPH_PHY_MODULE +#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1) +#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX)) + typedef enum { ETS_PMU_INTR_SOURCE = 0, ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 5cf3b834c1..5f75a8afa1 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -454,6 +454,8 @@ #define SOC_PM_SUPPORT_BT_WAKEUP (1) #define SOC_PM_SUPPORT_CPU_PD (1) #define SOC_PM_SUPPORT_BT_PD (1) +#define SOC_PM_SUPPORT_XTAL32K_PD (1) +#define SOC_PM_SUPPORT_RC32K_PD (1) #define SOC_PM_SUPPORT_RC_FAST_PD (1) #define SOC_PM_SUPPORT_VDDSDIO_PD (1) #define SOC_PM_CPU_RETENTION_BY_RTCCNTL (1) @@ -466,7 +468,8 @@ #define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */ #define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */ -#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL (1) /*!< Support LP_PLL clock as the LP_FAST clock source */ +#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL (1) /*!< Support LP_PLL clock as the LP_FAST clock source */ +#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1) // #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1) // TODO: IDF-6267 diff --git a/components/soc/esp32h2/ld/esp32h2.peripherals.ld b/components/soc/esp32h2/ld/esp32h2.peripherals.ld index 4d24b46d2c..9b88f4b68f 100644 --- a/components/soc/esp32h2/ld/esp32h2.peripherals.ld +++ b/components/soc/esp32h2/ld/esp32h2.peripherals.ld @@ -56,6 +56,10 @@ PROVIDE ( PCR = 0x60096000 ); PROVIDE ( TEE = 0x60098000 ); PROVIDE ( HP_APM = 0x60099000 ); +PROVIDE ( IEEE802154 = 0x600A3000 ); +PROVIDE ( MODEM_SYSCON = 0x600A5400 ); +PROVIDE ( MODEM_LPCON = 0x600AD000 ); + PROVIDE ( PMU = 0x600B0000 ); PROVIDE ( LP_CLKRST = 0x600B0400 ); PROVIDE ( EFUSE = 0x600B0800 ); @@ -67,4 +71,3 @@ PROVIDE ( LP_PERI = 0x600B2800 ); PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); PROVIDE ( LP_APM = 0x600B3800 ); PROVIDE ( OTP_DEBUG = 0x600B3C00 ); -PROVIDE ( IEEE802154 = 0x600A3000 );