From ee6845034270adf4ba5efb498e7a0f2feae53003 Mon Sep 17 00:00:00 2001
From: armando <douyiwen@espressif.com>
Date: Fri, 18 Jul 2025 15:11:55 +0800
Subject: [PATCH] feat(soc): p4 hw ver2 registers

---
 .../register/hw_ver2/soc/adc_eco5_reg.h       |   787 +
 .../register/hw_ver2/soc/adc_eco5_struct.h    |   695 +
 .../esp32p4/register/hw_ver2/soc/adc_reg.h    |   809 +
 .../esp32p4/register/hw_ver2/soc/adc_struct.h |   621 +
 .../register/hw_ver2/soc/aes_eco5_reg.h       |   462 +
 .../esp32p4/register/hw_ver2/soc/aes_reg.h    |   417 +
 .../esp32p4/register/hw_ver2/soc/aes_struct.h |   354 +
 .../hw_ver2/soc/ahb_dma_eco5_struct.h         |  3866 +++++
 .../register/hw_ver2/soc/ahb_dma_reg.h        |  4654 ++++++
 .../register/hw_ver2/soc/ahb_dma_struct.h     |  1411 ++
 .../register/hw_ver2/soc/assist_debug_reg.h   |  1399 ++
 .../hw_ver2/soc/assist_debug_struct.h         |  1318 ++
 .../hw_ver2/soc/axi_dma_eco5_struct.h         |  2021 +++
 .../register/hw_ver2/soc/axi_dma_reg.h        |  5757 ++++++++
 .../register/hw_ver2/soc/axi_dma_struct.h     |  1799 +++
 .../register/hw_ver2/soc/axi_perf_mon_reg.h   |  1858 +++
 .../hw_ver2/soc/axi_perf_mon_struct.h         |  1995 +++
 .../hw_ver2/soc/bitscrambler_eco5_struct.h    |   437 +
 .../register/hw_ver2/soc/bitscrambler_reg.h   |   481 +
 .../hw_ver2/soc/bitscrambler_struct.h         |   612 +
 .../esp32p4/register/hw_ver2/soc/cache_reg.h  |  6343 ++++++++
 .../register/hw_ver2/soc/cache_struct.h       |  5840 ++++++++
 .../register/hw_ver2/soc/dma2d_eco5_reg.h     |  7537 ++++++++++
 .../register/hw_ver2/soc/dma2d_eco5_struct.h  |  2085 +++
 .../esp32p4/register/hw_ver2/soc/dma2d_reg.h  |  5270 +++++++
 .../register/hw_ver2/soc/dma2d_struct.h       |  1827 +++
 .../register/hw_ver2/soc/dma_pms_eco5_reg.h   |  1576 ++
 .../register/hw_ver2/soc/dma_pms_reg.h        |  1740 +++
 .../register/hw_ver2/soc/dma_pms_struct.h     |  1919 +++
 .../soc/esp32p4/register/hw_ver2/soc/ds_reg.h |   176 +
 .../esp32p4/register/hw_ver2/soc/ds_struct.h  |   181 +
 .../hw_ver2/soc/dw_gdma_eco5_struct.h         |  5184 +++++++
 .../register/hw_ver2/soc/dw_gdma_reg.h        |  6880 +++++++++
 .../register/hw_ver2/soc/dw_gdma_struct.h     |  1782 +++
 .../register/hw_ver2/soc/ecc_mult_reg.h       |   210 +
 .../register/hw_ver2/soc/ecc_mult_struct.h    |   192 +
 .../register/hw_ver2/soc/ecdsa_eco5_reg.h     |   359 +
 .../esp32p4/register/hw_ver2/soc/ecdsa_reg.h  |   318 +
 .../register/hw_ver2/soc/ecdsa_struct.h       |   347 +
 .../register/hw_ver2/soc/efuse_eco5_struct.h  |  3689 +++++
 .../esp32p4/register/hw_ver2/soc/efuse_reg.h  |  4655 ++++++
 .../register/hw_ver2/soc/efuse_struct.h       |  4737 ++++++
 .../register/hw_ver2/soc/emac_dma_struct.h    |   154 +
 .../register/hw_ver2/soc/emac_mac_struct.h    |   258 +
 .../register/hw_ver2/soc/emac_ptp_struct.h    |   268 +
 .../hw_ver2/soc/gpio_ext_eco5_struct.h        |   772 +
 .../register/hw_ver2/soc/gpio_ext_reg.h       |  1455 ++
 .../register/hw_ver2/soc/gpio_ext_struct.h    |   194 +
 .../esp32p4/register/hw_ver2/soc/gpio_reg.h   | 12163 ++++++++++++++++
 .../register/hw_ver2/soc/gpio_sig_map.h       |   483 +
 .../register/hw_ver2/soc/gpio_struct.h        |   878 ++
 .../register/hw_ver2/soc/h264_dma_reg.h       |  8118 +++++++++++
 .../register/hw_ver2/soc/h264_dma_struct.h    |  7076 +++++++++
 .../esp32p4/register/hw_ver2/soc/h264_reg.h   |  2488 ++++
 .../register/hw_ver2/soc/h264_struct.h        |  2127 +++
 .../esp32p4/register/hw_ver2/soc/hmac_reg.h   |   282 +
 .../register/hw_ver2/soc/hmac_struct.h        |   344 +
 .../hw_ver2/soc/hp2lp_peri_pms_eco5_reg.h     |   779 +
 .../register/hw_ver2/soc/hp2lp_peri_pms_reg.h |   969 ++
 .../hw_ver2/soc/hp2lp_peri_pms_struct.h       |   530 +
 .../hw_ver2/soc/hp_peri_pms_eco5_reg.h        |  2232 +++
 .../register/hw_ver2/soc/hp_peri_pms_reg.h    |  2840 ++++
 .../register/hw_ver2/soc/hp_peri_pms_struct.h |  1490 ++
 .../register/hw_ver2/soc/hp_sys_clkrst_reg.h  |  4399 ++++++
 .../hw_ver2/soc/hp_sys_clkrst_struct.h        |  3058 ++++
 .../register/hw_ver2/soc/hp_system_reg.h      |  2173 +++
 .../register/hw_ver2/soc/hp_system_struct.h   |  2257 +++
 .../esp32p4/register/hw_ver2/soc/huk_reg.h    |   230 +
 .../esp32p4/register/hw_ver2/soc/huk_struct.h |   247 +
 .../register/hw_ver2/soc/i2c_ana_mst_reg.h    |   301 +
 .../register/hw_ver2/soc/i2c_ana_mst_struct.h |   304 +
 .../register/hw_ver2/soc/i2c_eco5_struct.h    |  1235 ++
 .../esp32p4/register/hw_ver2/soc/i2c_reg.h    |  1478 ++
 .../esp32p4/register/hw_ver2/soc/i2c_struct.h |  1095 ++
 .../register/hw_ver2/soc/i2s_eco5_struct.h    |  1009 ++
 .../esp32p4/register/hw_ver2/soc/i2s_reg.h    |  1268 ++
 .../esp32p4/register/hw_ver2/soc/i2s_struct.h |  1012 ++
 .../hw_ver2/soc/i3c_mst_mem_eco5_struct.h     |  1354 ++
 .../register/hw_ver2/soc/i3c_mst_mem_reg.h    |  1166 ++
 .../register/hw_ver2/soc/i3c_mst_mem_struct.h |   196 +
 .../register/hw_ver2/soc/i3c_mst_reg.h        |  1353 ++
 .../register/hw_ver2/soc/i3c_mst_struct.h     |  1183 ++
 .../register/hw_ver2/soc/i3c_slv_reg.h        |   585 +
 .../register/hw_ver2/soc/i3c_slv_struct.h     |   550 +
 .../register/hw_ver2/soc/icm_sys_qos_reg.h    |   176 +
 .../register/hw_ver2/soc/icm_sys_qos_struct.h |   157 +
 .../register/hw_ver2/soc/icm_sys_reg.h        |   546 +
 .../register/hw_ver2/soc/icm_sys_struct.h     |   521 +
 .../hw_ver2/soc/interrupt_core0_reg.h         |  3592 +++++
 .../hw_ver2/soc/interrupt_core0_struct.h      |  3528 +++++
 90 files changed, 175473 insertions(+)
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/adc_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/adc_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/aes_eco5_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/aes_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/aes_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/assist_debug_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/assist_debug_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/axi_dma_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/axi_dma_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/axi_dma_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/axi_perf_mon_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/axi_perf_mon_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/cache_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/cache_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dma2d_eco5_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dma2d_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dma2d_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dma2d_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dma_pms_eco5_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dma_pms_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dma_pms_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ds_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ds_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ecc_mult_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ecc_mult_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ecdsa_eco5_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ecdsa_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/ecdsa_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/efuse_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/efuse_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/efuse_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/emac_dma_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/emac_mac_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/emac_ptp_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/gpio_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/gpio_sig_map.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/gpio_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/h264_dma_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/h264_dma_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/h264_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/h264_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hmac_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hmac_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_eco5_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_eco5_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp_sys_clkrst_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp_sys_clkrst_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp_system_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/hp_system_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/huk_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/huk_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i2c_ana_mst_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i2c_ana_mst_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i2c_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i2c_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i2c_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i2s_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i2s_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i2s_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_eco5_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i3c_slv_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/i3c_slv_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/icm_sys_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/icm_sys_struct.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/interrupt_core0_reg.h
 create mode 100644 components/soc/esp32p4/register/hw_ver2/soc/interrupt_core0_struct.h

diff --git a/components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_reg.h
new file mode 100644
index 0000000000..2315ba5af2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_reg.h
@@ -0,0 +1,787 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ADC_CTRL_REG_REG register
+ *  Register
+ */
+#define ADC_CTRL_REG_REG (DR_REG_ADC_BASE + 0x0)
+/** ADC_START_FORCE : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_START_FORCE    (BIT(0))
+#define ADC_START_FORCE_M  (ADC_START_FORCE_V << ADC_START_FORCE_S)
+#define ADC_START_FORCE_V  0x00000001U
+#define ADC_START_FORCE_S  0
+/** ADC_START : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_START    (BIT(1))
+#define ADC_START_M  (ADC_START_V << ADC_START_S)
+#define ADC_START_V  0x00000001U
+#define ADC_START_S  1
+/** ADC_WORK_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  0: single mode, 1: double mode, 2: alternate mode
+ */
+#define ADC_WORK_MODE    0x00000003U
+#define ADC_WORK_MODE_M  (ADC_WORK_MODE_V << ADC_WORK_MODE_S)
+#define ADC_WORK_MODE_V  0x00000003U
+#define ADC_WORK_MODE_S  2
+/** ADC_SAR_SEL : R/W; bitpos: [4]; default: 0;
+ *  0: SAR1, 1: SAR2, only work for single SAR mode
+ */
+#define ADC_SAR_SEL    (BIT(4))
+#define ADC_SAR_SEL_M  (ADC_SAR_SEL_V << ADC_SAR_SEL_S)
+#define ADC_SAR_SEL_V  0x00000001U
+#define ADC_SAR_SEL_S  4
+/** ADC_SAR_CLK_GATED : R/W; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define ADC_SAR_CLK_GATED    (BIT(5))
+#define ADC_SAR_CLK_GATED_M  (ADC_SAR_CLK_GATED_V << ADC_SAR_CLK_GATED_S)
+#define ADC_SAR_CLK_GATED_V  0x00000001U
+#define ADC_SAR_CLK_GATED_S  5
+/** ADC_SAR_CLK_DIV : R/W; bitpos: [13:6]; default: 4;
+ *  SAR clock divider
+ */
+#define ADC_SAR_CLK_DIV    0x000000FFU
+#define ADC_SAR_CLK_DIV_M  (ADC_SAR_CLK_DIV_V << ADC_SAR_CLK_DIV_S)
+#define ADC_SAR_CLK_DIV_V  0x000000FFU
+#define ADC_SAR_CLK_DIV_S  6
+/** ADC_SAR1_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR1_PATT_LEN    0x0000000FU
+#define ADC_SAR1_PATT_LEN_M  (ADC_SAR1_PATT_LEN_V << ADC_SAR1_PATT_LEN_S)
+#define ADC_SAR1_PATT_LEN_V  0x0000000FU
+#define ADC_SAR1_PATT_LEN_S  14
+/** ADC_SAR2_PATT_LEN : R/W; bitpos: [21:18]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR2_PATT_LEN    0x0000000FU
+#define ADC_SAR2_PATT_LEN_M  (ADC_SAR2_PATT_LEN_V << ADC_SAR2_PATT_LEN_S)
+#define ADC_SAR2_PATT_LEN_V  0x0000000FU
+#define ADC_SAR2_PATT_LEN_S  18
+/** ADC_SAR1_PATT_P_CLEAR : R/W; bitpos: [22]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC1 CTRL
+ */
+#define ADC_SAR1_PATT_P_CLEAR    (BIT(22))
+#define ADC_SAR1_PATT_P_CLEAR_M  (ADC_SAR1_PATT_P_CLEAR_V << ADC_SAR1_PATT_P_CLEAR_S)
+#define ADC_SAR1_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR1_PATT_P_CLEAR_S  22
+/** ADC_SAR2_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC2 CTRL
+ */
+#define ADC_SAR2_PATT_P_CLEAR    (BIT(23))
+#define ADC_SAR2_PATT_P_CLEAR_M  (ADC_SAR2_PATT_P_CLEAR_V << ADC_SAR2_PATT_P_CLEAR_S)
+#define ADC_SAR2_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR2_PATT_P_CLEAR_S  23
+/** ADC_DATA_SAR_SEL : R/W; bitpos: [24]; default: 0;
+ *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+ *  resolution should not be larger than 11 bits.
+ */
+#define ADC_DATA_SAR_SEL    (BIT(24))
+#define ADC_DATA_SAR_SEL_M  (ADC_DATA_SAR_SEL_V << ADC_DATA_SAR_SEL_S)
+#define ADC_DATA_SAR_SEL_V  0x00000001U
+#define ADC_DATA_SAR_SEL_S  24
+/** ADC_DATA_TO_I2S : R/W; bitpos: [25]; default: 0;
+ *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+ */
+#define ADC_DATA_TO_I2S    (BIT(25))
+#define ADC_DATA_TO_I2S_M  (ADC_DATA_TO_I2S_V << ADC_DATA_TO_I2S_S)
+#define ADC_DATA_TO_I2S_V  0x00000001U
+#define ADC_DATA_TO_I2S_S  25
+/** ADC_XPD_SAR1_FORCE : R/W; bitpos: [27:26]; default: 0;
+ *  force option to xpd sar1 blocks
+ */
+#define ADC_XPD_SAR1_FORCE    0x00000003U
+#define ADC_XPD_SAR1_FORCE_M  (ADC_XPD_SAR1_FORCE_V << ADC_XPD_SAR1_FORCE_S)
+#define ADC_XPD_SAR1_FORCE_V  0x00000003U
+#define ADC_XPD_SAR1_FORCE_S  26
+/** ADC_XPD_SAR2_FORCE : R/W; bitpos: [29:28]; default: 0;
+ *  force option to xpd sar2 blocks
+ */
+#define ADC_XPD_SAR2_FORCE    0x00000003U
+#define ADC_XPD_SAR2_FORCE_M  (ADC_XPD_SAR2_FORCE_V << ADC_XPD_SAR2_FORCE_S)
+#define ADC_XPD_SAR2_FORCE_V  0x00000003U
+#define ADC_XPD_SAR2_FORCE_S  28
+/** ADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
+ *  wait arbit signal stable after sar_done
+ */
+#define ADC_WAIT_ARB_CYCLE    0x00000003U
+#define ADC_WAIT_ARB_CYCLE_M  (ADC_WAIT_ARB_CYCLE_V << ADC_WAIT_ARB_CYCLE_S)
+#define ADC_WAIT_ARB_CYCLE_V  0x00000003U
+#define ADC_WAIT_ARB_CYCLE_S  30
+
+/** ADC_CTRL2_REG register
+ *  Register
+ */
+#define ADC_CTRL2_REG (DR_REG_ADC_BASE + 0x4)
+/** ADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_MEAS_NUM_LIMIT    (BIT(0))
+#define ADC_MEAS_NUM_LIMIT_M  (ADC_MEAS_NUM_LIMIT_V << ADC_MEAS_NUM_LIMIT_S)
+#define ADC_MEAS_NUM_LIMIT_V  0x00000001U
+#define ADC_MEAS_NUM_LIMIT_S  0
+/** ADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
+ *  max conversion number
+ */
+#define ADC_MAX_MEAS_NUM    0x000000FFU
+#define ADC_MAX_MEAS_NUM_M  (ADC_MAX_MEAS_NUM_V << ADC_MAX_MEAS_NUM_S)
+#define ADC_MAX_MEAS_NUM_V  0x000000FFU
+#define ADC_MAX_MEAS_NUM_S  1
+/** ADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
+ *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+ */
+#define ADC_SAR1_INV    (BIT(9))
+#define ADC_SAR1_INV_M  (ADC_SAR1_INV_V << ADC_SAR1_INV_S)
+#define ADC_SAR1_INV_V  0x00000001U
+#define ADC_SAR1_INV_S  9
+/** ADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
+ *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+ */
+#define ADC_SAR2_INV    (BIT(10))
+#define ADC_SAR2_INV_M  (ADC_SAR2_INV_V << ADC_SAR2_INV_S)
+#define ADC_SAR2_INV_V  0x00000001U
+#define ADC_SAR2_INV_S  10
+/** ADC_TIMER_SEL : R/W; bitpos: [11]; default: 0;
+ *  1: select saradc timer 0: i2s_ws trigger
+ */
+#define ADC_TIMER_SEL    (BIT(11))
+#define ADC_TIMER_SEL_M  (ADC_TIMER_SEL_V << ADC_TIMER_SEL_S)
+#define ADC_TIMER_SEL_V  0x00000001U
+#define ADC_TIMER_SEL_S  11
+/** ADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
+ *  to set saradc timer target
+ */
+#define ADC_TIMER_TARGET    0x00000FFFU
+#define ADC_TIMER_TARGET_M  (ADC_TIMER_TARGET_V << ADC_TIMER_TARGET_S)
+#define ADC_TIMER_TARGET_V  0x00000FFFU
+#define ADC_TIMER_TARGET_S  12
+/** ADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
+ *  to enable saradc timer trigger
+ */
+#define ADC_TIMER_EN    (BIT(24))
+#define ADC_TIMER_EN_M  (ADC_TIMER_EN_V << ADC_TIMER_EN_S)
+#define ADC_TIMER_EN_V  0x00000001U
+#define ADC_TIMER_EN_S  24
+
+/** ADC_FILTER_CTRL1_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL1_REG (DR_REG_ADC_BASE + 0x8)
+/** ADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR1    0x00000007U
+#define ADC_FILTER_FACTOR1_M  (ADC_FILTER_FACTOR1_V << ADC_FILTER_FACTOR1_S)
+#define ADC_FILTER_FACTOR1_V  0x00000007U
+#define ADC_FILTER_FACTOR1_S  26
+/** ADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR0    0x00000007U
+#define ADC_FILTER_FACTOR0_M  (ADC_FILTER_FACTOR0_V << ADC_FILTER_FACTOR0_S)
+#define ADC_FILTER_FACTOR0_V  0x00000007U
+#define ADC_FILTER_FACTOR0_S  29
+
+/** ADC_SAR1_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x18)
+/** ADC_SAR1_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
+ *  item 0 ~ 3 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_M  (ADC_SAR1_PATT_TAB1_V << ADC_SAR1_PATT_TAB1_S)
+#define ADC_SAR1_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_S  0
+
+/** ADC_SAR1_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x1c)
+/** ADC_SAR1_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_M  (ADC_SAR1_PATT_TAB2_V << ADC_SAR1_PATT_TAB2_S)
+#define ADC_SAR1_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_S  0
+
+/** ADC_SAR1_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x20)
+/** ADC_SAR1_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_M  (ADC_SAR1_PATT_TAB3_V << ADC_SAR1_PATT_TAB3_S)
+#define ADC_SAR1_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_S  0
+
+/** ADC_SAR1_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x24)
+/** ADC_SAR1_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_M  (ADC_SAR1_PATT_TAB4_V << ADC_SAR1_PATT_TAB4_S)
+#define ADC_SAR1_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_S  0
+
+/** ADC_SAR2_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x28)
+/** ADC_SAR2_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
+ *  item 0 ~ 3 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_M  (ADC_SAR2_PATT_TAB1_V << ADC_SAR2_PATT_TAB1_S)
+#define ADC_SAR2_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_S  0
+
+/** ADC_SAR2_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x2c)
+/** ADC_SAR2_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_M  (ADC_SAR2_PATT_TAB2_V << ADC_SAR2_PATT_TAB2_S)
+#define ADC_SAR2_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_S  0
+
+/** ADC_SAR2_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x30)
+/** ADC_SAR2_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_M  (ADC_SAR2_PATT_TAB3_V << ADC_SAR2_PATT_TAB3_S)
+#define ADC_SAR2_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_S  0
+
+/** ADC_SAR2_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x34)
+/** ADC_SAR2_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_M  (ADC_SAR2_PATT_TAB4_V << ADC_SAR2_PATT_TAB4_S)
+#define ADC_SAR2_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_S  0
+
+/** ADC_ARB_CTRL_REG register
+ *  Register
+ */
+#define ADC_ARB_CTRL_REG (DR_REG_ADC_BASE + 0x38)
+/** ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
+ *  adc2 arbiter force to enableapb controller
+ */
+#define ADC_ARB_APB_FORCE    (BIT(2))
+#define ADC_ARB_APB_FORCE_M  (ADC_ARB_APB_FORCE_V << ADC_ARB_APB_FORCE_S)
+#define ADC_ARB_APB_FORCE_V  0x00000001U
+#define ADC_ARB_APB_FORCE_S  2
+/** ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
+ *  adc2 arbiter force to enable rtc controller
+ */
+#define ADC_ARB_RTC_FORCE    (BIT(3))
+#define ADC_ARB_RTC_FORCE_M  (ADC_ARB_RTC_FORCE_V << ADC_ARB_RTC_FORCE_S)
+#define ADC_ARB_RTC_FORCE_V  0x00000001U
+#define ADC_ARB_RTC_FORCE_S  3
+/** ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
+ *  adc2 arbiter force to enable wifi controller
+ */
+#define ADC_ARB_WIFI_FORCE    (BIT(4))
+#define ADC_ARB_WIFI_FORCE_M  (ADC_ARB_WIFI_FORCE_V << ADC_ARB_WIFI_FORCE_S)
+#define ADC_ARB_WIFI_FORCE_V  0x00000001U
+#define ADC_ARB_WIFI_FORCE_S  4
+/** ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
+ *  adc2 arbiter force grant
+ */
+#define ADC_ARB_GRANT_FORCE    (BIT(5))
+#define ADC_ARB_GRANT_FORCE_M  (ADC_ARB_GRANT_FORCE_V << ADC_ARB_GRANT_FORCE_S)
+#define ADC_ARB_GRANT_FORCE_V  0x00000001U
+#define ADC_ARB_GRANT_FORCE_S  5
+/** ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
+ *  Set adc2 arbiterapb priority
+ */
+#define ADC_ARB_APB_PRIORITY    0x00000003U
+#define ADC_ARB_APB_PRIORITY_M  (ADC_ARB_APB_PRIORITY_V << ADC_ARB_APB_PRIORITY_S)
+#define ADC_ARB_APB_PRIORITY_V  0x00000003U
+#define ADC_ARB_APB_PRIORITY_S  6
+/** ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
+ *  Set adc2 arbiter rtc priority
+ */
+#define ADC_ARB_RTC_PRIORITY    0x00000003U
+#define ADC_ARB_RTC_PRIORITY_M  (ADC_ARB_RTC_PRIORITY_V << ADC_ARB_RTC_PRIORITY_S)
+#define ADC_ARB_RTC_PRIORITY_V  0x00000003U
+#define ADC_ARB_RTC_PRIORITY_S  8
+/** ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
+ *  Set adc2 arbiter wifi priority
+ */
+#define ADC_ARB_WIFI_PRIORITY    0x00000003U
+#define ADC_ARB_WIFI_PRIORITY_M  (ADC_ARB_WIFI_PRIORITY_V << ADC_ARB_WIFI_PRIORITY_S)
+#define ADC_ARB_WIFI_PRIORITY_V  0x00000003U
+#define ADC_ARB_WIFI_PRIORITY_S  10
+/** ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
+ *  adc2 arbiter uses fixed priority
+ */
+#define ADC_ARB_FIX_PRIORITY    (BIT(12))
+#define ADC_ARB_FIX_PRIORITY_M  (ADC_ARB_FIX_PRIORITY_V << ADC_ARB_FIX_PRIORITY_S)
+#define ADC_ARB_FIX_PRIORITY_V  0x00000001U
+#define ADC_ARB_FIX_PRIORITY_S  12
+
+/** ADC_FILTER_CTRL0_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL0_REG (DR_REG_ADC_BASE + 0x3c)
+/** ADC_FILTER_CHANNEL1 : R/W; bitpos: [18:14]; default: 13;
+ *  need_des
+ */
+#define ADC_FILTER_CHANNEL1    0x0000001FU
+#define ADC_FILTER_CHANNEL1_M  (ADC_FILTER_CHANNEL1_V << ADC_FILTER_CHANNEL1_S)
+#define ADC_FILTER_CHANNEL1_V  0x0000001FU
+#define ADC_FILTER_CHANNEL1_S  14
+/** ADC_FILTER_CHANNEL0 : R/W; bitpos: [23:19]; default: 13;
+ *  apb_adc1_filter_factor
+ */
+#define ADC_FILTER_CHANNEL0    0x0000001FU
+#define ADC_FILTER_CHANNEL0_M  (ADC_FILTER_CHANNEL0_V << ADC_FILTER_CHANNEL0_S)
+#define ADC_FILTER_CHANNEL0_V  0x0000001FU
+#define ADC_FILTER_CHANNEL0_S  19
+/** ADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc1_filter
+ */
+#define ADC_FILTER_RESET    (BIT(31))
+#define ADC_FILTER_RESET_M  (ADC_FILTER_RESET_V << ADC_FILTER_RESET_S)
+#define ADC_FILTER_RESET_V  0x00000001U
+#define ADC_FILTER_RESET_S  31
+
+/** ADC_SAR1_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR1_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x40)
+/** ADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DATA    0x0001FFFFU
+#define ADC_APB_SARADC1_DATA_M  (ADC_APB_SARADC1_DATA_V << ADC_APB_SARADC1_DATA_S)
+#define ADC_APB_SARADC1_DATA_V  0x0001FFFFU
+#define ADC_APB_SARADC1_DATA_S  0
+
+/** ADC_THRES0_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES0_CTRL_REG (DR_REG_ADC_BASE + 0x44)
+/** ADC_THRES0_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES0_CHANNEL    0x0000001FU
+#define ADC_THRES0_CHANNEL_M  (ADC_THRES0_CHANNEL_V << ADC_THRES0_CHANNEL_S)
+#define ADC_THRES0_CHANNEL_V  0x0000001FU
+#define ADC_THRES0_CHANNEL_S  0
+/** ADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES0_HIGH    0x00001FFFU
+#define ADC_THRES0_HIGH_M  (ADC_THRES0_HIGH_V << ADC_THRES0_HIGH_S)
+#define ADC_THRES0_HIGH_V  0x00001FFFU
+#define ADC_THRES0_HIGH_S  5
+/** ADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES0_LOW    0x00001FFFU
+#define ADC_THRES0_LOW_M  (ADC_THRES0_LOW_V << ADC_THRES0_LOW_S)
+#define ADC_THRES0_LOW_V  0x00001FFFU
+#define ADC_THRES0_LOW_S  18
+
+/** ADC_THRES1_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES1_CTRL_REG (DR_REG_ADC_BASE + 0x48)
+/** ADC_THRES1_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES1_CHANNEL    0x0000001FU
+#define ADC_THRES1_CHANNEL_M  (ADC_THRES1_CHANNEL_V << ADC_THRES1_CHANNEL_S)
+#define ADC_THRES1_CHANNEL_V  0x0000001FU
+#define ADC_THRES1_CHANNEL_S  0
+/** ADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES1_HIGH    0x00001FFFU
+#define ADC_THRES1_HIGH_M  (ADC_THRES1_HIGH_V << ADC_THRES1_HIGH_S)
+#define ADC_THRES1_HIGH_V  0x00001FFFU
+#define ADC_THRES1_HIGH_S  5
+/** ADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES1_LOW    0x00001FFFU
+#define ADC_THRES1_LOW_M  (ADC_THRES1_LOW_V << ADC_THRES1_LOW_S)
+#define ADC_THRES1_LOW_V  0x00001FFFU
+#define ADC_THRES1_LOW_S  18
+
+/** ADC_THRES_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES_CTRL_REG (DR_REG_ADC_BASE + 0x4c)
+/** ADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES_ALL_EN    (BIT(27))
+#define ADC_THRES_ALL_EN_M  (ADC_THRES_ALL_EN_V << ADC_THRES_ALL_EN_S)
+#define ADC_THRES_ALL_EN_V  0x00000001U
+#define ADC_THRES_ALL_EN_S  27
+/** ADC_THRES3_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES3_EN    (BIT(28))
+#define ADC_THRES3_EN_M  (ADC_THRES3_EN_V << ADC_THRES3_EN_S)
+#define ADC_THRES3_EN_V  0x00000001U
+#define ADC_THRES3_EN_S  28
+/** ADC_THRES2_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES2_EN    (BIT(29))
+#define ADC_THRES2_EN_M  (ADC_THRES2_EN_V << ADC_THRES2_EN_S)
+#define ADC_THRES2_EN_V  0x00000001U
+#define ADC_THRES2_EN_S  29
+/** ADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_EN    (BIT(30))
+#define ADC_THRES1_EN_M  (ADC_THRES1_EN_V << ADC_THRES1_EN_S)
+#define ADC_THRES1_EN_V  0x00000001U
+#define ADC_THRES1_EN_S  30
+/** ADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_EN    (BIT(31))
+#define ADC_THRES0_EN_M  (ADC_THRES0_EN_V << ADC_THRES0_EN_S)
+#define ADC_THRES0_EN_V  0x00000001U
+#define ADC_THRES0_EN_S  31
+
+/** ADC_INT_ENA_REG register
+ *  Register
+ */
+#define ADC_INT_ENA_REG (DR_REG_ADC_BASE + 0x50)
+/** ADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ENA    (BIT(26))
+#define ADC_THRES1_LOW_INT_ENA_M  (ADC_THRES1_LOW_INT_ENA_V << ADC_THRES1_LOW_INT_ENA_S)
+#define ADC_THRES1_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ENA_S  26
+/** ADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ENA    (BIT(27))
+#define ADC_THRES0_LOW_INT_ENA_M  (ADC_THRES0_LOW_INT_ENA_V << ADC_THRES0_LOW_INT_ENA_S)
+#define ADC_THRES0_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ENA_S  27
+/** ADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ENA    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ENA_M  (ADC_THRES1_HIGH_INT_ENA_V << ADC_THRES1_HIGH_INT_ENA_S)
+#define ADC_THRES1_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ENA_S  28
+/** ADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ENA    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ENA_M  (ADC_THRES0_HIGH_INT_ENA_V << ADC_THRES0_HIGH_INT_ENA_S)
+#define ADC_THRES0_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ENA_S  29
+/** ADC_SAR2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_ENA    (BIT(30))
+#define ADC_SAR2_DONE_INT_ENA_M  (ADC_SAR2_DONE_INT_ENA_V << ADC_SAR2_DONE_INT_ENA_S)
+#define ADC_SAR2_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR2_DONE_INT_ENA_S  30
+/** ADC_SAR1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_ENA    (BIT(31))
+#define ADC_SAR1_DONE_INT_ENA_M  (ADC_SAR1_DONE_INT_ENA_V << ADC_SAR1_DONE_INT_ENA_S)
+#define ADC_SAR1_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR1_DONE_INT_ENA_S  31
+
+/** ADC_INT_RAW_REG register
+ *  Register
+ */
+#define ADC_INT_RAW_REG (DR_REG_ADC_BASE + 0x54)
+/** ADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_RAW    (BIT(26))
+#define ADC_THRES1_LOW_INT_RAW_M  (ADC_THRES1_LOW_INT_RAW_V << ADC_THRES1_LOW_INT_RAW_S)
+#define ADC_THRES1_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES1_LOW_INT_RAW_S  26
+/** ADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_RAW    (BIT(27))
+#define ADC_THRES0_LOW_INT_RAW_M  (ADC_THRES0_LOW_INT_RAW_V << ADC_THRES0_LOW_INT_RAW_S)
+#define ADC_THRES0_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES0_LOW_INT_RAW_S  27
+/** ADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_RAW    (BIT(28))
+#define ADC_THRES1_HIGH_INT_RAW_M  (ADC_THRES1_HIGH_INT_RAW_V << ADC_THRES1_HIGH_INT_RAW_S)
+#define ADC_THRES1_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_RAW_S  28
+/** ADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_RAW    (BIT(29))
+#define ADC_THRES0_HIGH_INT_RAW_M  (ADC_THRES0_HIGH_INT_RAW_V << ADC_THRES0_HIGH_INT_RAW_S)
+#define ADC_THRES0_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_RAW_S  29
+/** ADC_SAR2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_RAW    (BIT(30))
+#define ADC_SAR2_DONE_INT_RAW_M  (ADC_SAR2_DONE_INT_RAW_V << ADC_SAR2_DONE_INT_RAW_S)
+#define ADC_SAR2_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR2_DONE_INT_RAW_S  30
+/** ADC_SAR1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_RAW    (BIT(31))
+#define ADC_SAR1_DONE_INT_RAW_M  (ADC_SAR1_DONE_INT_RAW_V << ADC_SAR1_DONE_INT_RAW_S)
+#define ADC_SAR1_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR1_DONE_INT_RAW_S  31
+
+/** ADC_INT_ST_REG register
+ *  Register
+ */
+#define ADC_INT_ST_REG (DR_REG_ADC_BASE + 0x58)
+/** ADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ST    (BIT(26))
+#define ADC_THRES1_LOW_INT_ST_M  (ADC_THRES1_LOW_INT_ST_V << ADC_THRES1_LOW_INT_ST_S)
+#define ADC_THRES1_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ST_S  26
+/** ADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ST    (BIT(27))
+#define ADC_THRES0_LOW_INT_ST_M  (ADC_THRES0_LOW_INT_ST_V << ADC_THRES0_LOW_INT_ST_S)
+#define ADC_THRES0_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ST_S  27
+/** ADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ST    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ST_M  (ADC_THRES1_HIGH_INT_ST_V << ADC_THRES1_HIGH_INT_ST_S)
+#define ADC_THRES1_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ST_S  28
+/** ADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ST    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ST_M  (ADC_THRES0_HIGH_INT_ST_V << ADC_THRES0_HIGH_INT_ST_S)
+#define ADC_THRES0_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ST_S  29
+/** ADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DONE_INT_ST    (BIT(30))
+#define ADC_APB_SARADC2_DONE_INT_ST_M  (ADC_APB_SARADC2_DONE_INT_ST_V << ADC_APB_SARADC2_DONE_INT_ST_S)
+#define ADC_APB_SARADC2_DONE_INT_ST_V  0x00000001U
+#define ADC_APB_SARADC2_DONE_INT_ST_S  30
+/** ADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DONE_INT_ST    (BIT(31))
+#define ADC_APB_SARADC1_DONE_INT_ST_M  (ADC_APB_SARADC1_DONE_INT_ST_V << ADC_APB_SARADC1_DONE_INT_ST_S)
+#define ADC_APB_SARADC1_DONE_INT_ST_V  0x00000001U
+#define ADC_APB_SARADC1_DONE_INT_ST_S  31
+
+/** ADC_INT_CLR_REG register
+ *  Register
+ */
+#define ADC_INT_CLR_REG (DR_REG_ADC_BASE + 0x5c)
+/** ADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_CLR    (BIT(26))
+#define ADC_THRES1_LOW_INT_CLR_M  (ADC_THRES1_LOW_INT_CLR_V << ADC_THRES1_LOW_INT_CLR_S)
+#define ADC_THRES1_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES1_LOW_INT_CLR_S  26
+/** ADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_CLR    (BIT(27))
+#define ADC_THRES0_LOW_INT_CLR_M  (ADC_THRES0_LOW_INT_CLR_V << ADC_THRES0_LOW_INT_CLR_S)
+#define ADC_THRES0_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES0_LOW_INT_CLR_S  27
+/** ADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_CLR    (BIT(28))
+#define ADC_THRES1_HIGH_INT_CLR_M  (ADC_THRES1_HIGH_INT_CLR_V << ADC_THRES1_HIGH_INT_CLR_S)
+#define ADC_THRES1_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_CLR_S  28
+/** ADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_CLR    (BIT(29))
+#define ADC_THRES0_HIGH_INT_CLR_M  (ADC_THRES0_HIGH_INT_CLR_V << ADC_THRES0_HIGH_INT_CLR_S)
+#define ADC_THRES0_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_CLR_S  29
+/** ADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DONE_INT_CLR    (BIT(30))
+#define ADC_APB_SARADC2_DONE_INT_CLR_M  (ADC_APB_SARADC2_DONE_INT_CLR_V << ADC_APB_SARADC2_DONE_INT_CLR_S)
+#define ADC_APB_SARADC2_DONE_INT_CLR_V  0x00000001U
+#define ADC_APB_SARADC2_DONE_INT_CLR_S  30
+/** ADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DONE_INT_CLR    (BIT(31))
+#define ADC_APB_SARADC1_DONE_INT_CLR_M  (ADC_APB_SARADC1_DONE_INT_CLR_V << ADC_APB_SARADC1_DONE_INT_CLR_S)
+#define ADC_APB_SARADC1_DONE_INT_CLR_V  0x00000001U
+#define ADC_APB_SARADC1_DONE_INT_CLR_S  31
+
+/** ADC_DMA_CONF_REG register
+ *  Register
+ */
+#define ADC_DMA_CONF_REG (DR_REG_ADC_BASE + 0x60)
+/** ADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
+ *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+ */
+#define ADC_APB_ADC_EOF_NUM    0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_M  (ADC_APB_ADC_EOF_NUM_V << ADC_APB_ADC_EOF_NUM_S)
+#define ADC_APB_ADC_EOF_NUM_V  0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_S  0
+/** ADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
+ *  reset_apb_adc_state
+ */
+#define ADC_APB_ADC_RESET_FSM    (BIT(30))
+#define ADC_APB_ADC_RESET_FSM_M  (ADC_APB_ADC_RESET_FSM_V << ADC_APB_ADC_RESET_FSM_S)
+#define ADC_APB_ADC_RESET_FSM_V  0x00000001U
+#define ADC_APB_ADC_RESET_FSM_S  30
+/** ADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc use spi_dma
+ */
+#define ADC_APB_ADC_TRANS    (BIT(31))
+#define ADC_APB_ADC_TRANS_M  (ADC_APB_ADC_TRANS_V << ADC_APB_ADC_TRANS_S)
+#define ADC_APB_ADC_TRANS_V  0x00000001U
+#define ADC_APB_ADC_TRANS_S  31
+
+/** ADC_SAR2_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR2_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x64)
+/** ADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DATA    0x0001FFFFU
+#define ADC_APB_SARADC2_DATA_M  (ADC_APB_SARADC2_DATA_V << ADC_APB_SARADC2_DATA_S)
+#define ADC_APB_SARADC2_DATA_V  0x0001FFFFU
+#define ADC_APB_SARADC2_DATA_S  0
+
+/** ADC_CALI_REG register
+ *  Register
+ */
+#define ADC_CALI_REG (DR_REG_ADC_BASE + 0x68)
+/** ADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
+ *  need_des
+ */
+#define ADC_CALI_CFG    0x0001FFFFU
+#define ADC_CALI_CFG_M  (ADC_CALI_CFG_V << ADC_CALI_CFG_S)
+#define ADC_CALI_CFG_V  0x0001FFFFU
+#define ADC_CALI_CFG_S  0
+
+/** ADC_RND_ECO_LOW_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_LOW_REG (DR_REG_ADC_BASE + 0x6c)
+/** ADC_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  rnd eco low
+ */
+#define ADC_RND_ECO_LOW    0xFFFFFFFFU
+#define ADC_RND_ECO_LOW_M  (ADC_RND_ECO_LOW_V << ADC_RND_ECO_LOW_S)
+#define ADC_RND_ECO_LOW_V  0xFFFFFFFFU
+#define ADC_RND_ECO_LOW_S  0
+
+/** ADC_RND_ECO_HIGH_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_HIGH_REG (DR_REG_ADC_BASE + 0x70)
+/** ADC_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  rnd eco high
+ */
+#define ADC_RND_ECO_HIGH    0xFFFFFFFFU
+#define ADC_RND_ECO_HIGH_M  (ADC_RND_ECO_HIGH_V << ADC_RND_ECO_HIGH_S)
+#define ADC_RND_ECO_HIGH_V  0xFFFFFFFFU
+#define ADC_RND_ECO_HIGH_S  0
+
+/** ADC_RND_ECO_CS_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_CS_REG (DR_REG_ADC_BASE + 0x74)
+/** ADC_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_EN    (BIT(0))
+#define ADC_RND_ECO_EN_M  (ADC_RND_ECO_EN_V << ADC_RND_ECO_EN_S)
+#define ADC_RND_ECO_EN_V  0x00000001U
+#define ADC_RND_ECO_EN_S  0
+/** ADC_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_RESULT    (BIT(1))
+#define ADC_RND_ECO_RESULT_M  (ADC_RND_ECO_RESULT_V << ADC_RND_ECO_RESULT_S)
+#define ADC_RND_ECO_RESULT_V  0x00000001U
+#define ADC_RND_ECO_RESULT_S  1
+
+/** ADC_CTRL_DATE_REG register
+ *  Register
+ */
+#define ADC_CTRL_DATE_REG (DR_REG_ADC_BASE + 0x3fc)
+/** ADC_CTRL_DATE : R/W; bitpos: [30:0]; default: 35725920;
+ *  need_des
+ */
+#define ADC_CTRL_DATE    0x7FFFFFFFU
+#define ADC_CTRL_DATE_M  (ADC_CTRL_DATE_V << ADC_CTRL_DATE_S)
+#define ADC_CTRL_DATE_V  0x7FFFFFFFU
+#define ADC_CTRL_DATE_S  0
+/** ADC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_CLK_EN    (BIT(31))
+#define ADC_CLK_EN_M  (ADC_CLK_EN_V << ADC_CLK_EN_S)
+#define ADC_CLK_EN_V  0x00000001U
+#define ADC_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_struct.h
new file mode 100644
index 0000000000..873db7857c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/adc_eco5_struct.h
@@ -0,0 +1,695 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configure Register */
+/** Type of ctrl_reg register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** start_force : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t start_force:1;
+        /** start : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t start:1;
+        /** work_mode : R/W; bitpos: [3:2]; default: 0;
+         *  0: single mode, 1: double mode, 2: alternate mode
+         */
+        uint32_t work_mode:2;
+        /** sar_sel : R/W; bitpos: [4]; default: 0;
+         *  0: SAR1, 1: SAR2, only work for single SAR mode
+         */
+        uint32_t sar_sel:1;
+        /** sar_clk_gated : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t sar_clk_gated:1;
+        /** sar_clk_div : R/W; bitpos: [13:6]; default: 4;
+         *  SAR clock divider
+         */
+        uint32_t sar_clk_div:8;
+        /** sar1_patt_len : R/W; bitpos: [17:14]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar1_patt_len:4;
+        /** sar2_patt_len : R/W; bitpos: [21:18]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar2_patt_len:4;
+        /** sar1_patt_p_clear : R/W; bitpos: [22]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC1 CTRL
+         */
+        uint32_t sar1_patt_p_clear:1;
+        /** sar2_patt_p_clear : R/W; bitpos: [23]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC2 CTRL
+         */
+        uint32_t sar2_patt_p_clear:1;
+        /** data_sar_sel : R/W; bitpos: [24]; default: 0;
+         *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+         *  resolution should not be larger than 11 bits.
+         */
+        uint32_t data_sar_sel:1;
+        /** data_to_i2s : R/W; bitpos: [25]; default: 0;
+         *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+         */
+        uint32_t data_to_i2s:1;
+        /** xpd_sar1_force : R/W; bitpos: [27:26]; default: 0;
+         *  force option to xpd sar1 blocks
+         */
+        uint32_t xpd_sar1_force:2;
+        /** xpd_sar2_force : R/W; bitpos: [29:28]; default: 0;
+         *  force option to xpd sar2 blocks
+         */
+        uint32_t xpd_sar2_force:2;
+        /** wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
+         *  wait arbit signal stable after sar_done
+         */
+        uint32_t wait_arb_cycle:2;
+    };
+    uint32_t val;
+} adc_ctrl_reg_reg_t;
+
+/** Type of ctrl2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** meas_num_limit : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t meas_num_limit:1;
+        /** max_meas_num : R/W; bitpos: [8:1]; default: 255;
+         *  max conversion number
+         */
+        uint32_t max_meas_num:8;
+        /** sar1_inv : R/W; bitpos: [9]; default: 0;
+         *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+         */
+        uint32_t sar1_inv:1;
+        /** sar2_inv : R/W; bitpos: [10]; default: 0;
+         *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+         */
+        uint32_t sar2_inv:1;
+        /** timer_sel : R/W; bitpos: [11]; default: 0;
+         *  1: select saradc timer 0: i2s_ws trigger
+         */
+        uint32_t timer_sel:1;
+        /** timer_target : R/W; bitpos: [23:12]; default: 10;
+         *  to set saradc timer target
+         */
+        uint32_t timer_target:12;
+        /** timer_en : R/W; bitpos: [24]; default: 0;
+         *  to enable saradc timer trigger
+         */
+        uint32_t timer_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} adc_ctrl2_reg_t;
+
+/** Type of filter_ctrl1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** filter_factor1 : R/W; bitpos: [28:26]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor1:3;
+        /** filter_factor0 : R/W; bitpos: [31:29]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor0:3;
+    };
+    uint32_t val;
+} adc_filter_ctrl1_reg_t;
+
+/** Type of sar1_patt_tab1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab1 : R/W; bitpos: [23:0]; default: 0;
+         *  item 0 ~ 3 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab1_reg_t;
+
+/** Type of sar1_patt_tab2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab2:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab2_reg_t;
+
+/** Type of sar1_patt_tab3 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 8 ~ 11 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab3:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab3_reg_t;
+
+/** Type of sar1_patt_tab4 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 12 ~ 15 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab4:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab4_reg_t;
+
+/** Type of sar2_patt_tab1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab1 : R/W; bitpos: [23:0]; default: 0;
+         *  item 0 ~ 3 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab1_reg_t;
+
+/** Type of sar2_patt_tab2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 4 ~ 7 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab2:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab2_reg_t;
+
+/** Type of sar2_patt_tab3 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 8 ~ 11 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab3:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab3_reg_t;
+
+/** Type of sar2_patt_tab4 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 12 ~ 15 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab4:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab4_reg_t;
+
+/** Type of arb_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** arb_apb_force : R/W; bitpos: [2]; default: 0;
+         *  adc2 arbiter force to enableapb controller
+         */
+        uint32_t arb_apb_force:1;
+        /** arb_rtc_force : R/W; bitpos: [3]; default: 0;
+         *  adc2 arbiter force to enable rtc controller
+         */
+        uint32_t arb_rtc_force:1;
+        /** arb_wifi_force : R/W; bitpos: [4]; default: 0;
+         *  adc2 arbiter force to enable wifi controller
+         */
+        uint32_t arb_wifi_force:1;
+        /** arb_grant_force : R/W; bitpos: [5]; default: 0;
+         *  adc2 arbiter force grant
+         */
+        uint32_t arb_grant_force:1;
+        /** arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
+         *  Set adc2 arbiterapb priority
+         */
+        uint32_t arb_apb_priority:2;
+        /** arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
+         *  Set adc2 arbiter rtc priority
+         */
+        uint32_t arb_rtc_priority:2;
+        /** arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
+         *  Set adc2 arbiter wifi priority
+         */
+        uint32_t arb_wifi_priority:2;
+        /** arb_fix_priority : R/W; bitpos: [12]; default: 0;
+         *  adc2 arbiter uses fixed priority
+         */
+        uint32_t arb_fix_priority:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} adc_arb_ctrl_reg_t;
+
+/** Type of filter_ctrl0 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** filter_channel1 : R/W; bitpos: [18:14]; default: 13;
+         *  need_des
+         */
+        uint32_t filter_channel1:5;
+        /** filter_channel0 : R/W; bitpos: [23:19]; default: 13;
+         *  apb_adc1_filter_factor
+         */
+        uint32_t filter_channel0:5;
+        uint32_t reserved_24:7;
+        /** filter_reset : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc1_filter
+         */
+        uint32_t filter_reset:1;
+    };
+    uint32_t val;
+} adc_filter_ctrl0_reg_t;
+
+/** Type of sar1_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_sar1_data_status_reg_t;
+
+/** Type of thres0_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres0_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres0_channel:5;
+        /** thres0_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres0_high:13;
+        /** thres0_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres0_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} adc_thres0_ctrl_reg_t;
+
+/** Type of thres1_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres1_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres1_channel:5;
+        /** thres1_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres1_high:13;
+        /** thres1_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres1_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} adc_thres1_ctrl_reg_t;
+
+/** Type of thres_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** thres_all_en : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres_all_en:1;
+        /** thres3_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres3_en:1;
+        /** thres2_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres2_en:1;
+        /** thres1_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_en:1;
+        /** thres0_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_en:1;
+    };
+    uint32_t val;
+} adc_thres_ctrl_reg_t;
+
+/** Type of int_ena register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_ena:1;
+        /** thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_ena:1;
+        /** thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_ena:1;
+        /** thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_ena:1;
+        /** sar2_done_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_ena:1;
+        /** sar1_done_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_ena:1;
+    };
+    uint32_t val;
+} adc_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_raw:1;
+        /** thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_raw:1;
+        /** thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_raw:1;
+        /** thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_raw:1;
+        /** sar2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_raw:1;
+        /** sar1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_raw:1;
+    };
+    uint32_t val;
+} adc_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_st : RO; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_st:1;
+        /** thres0_low_int_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_st:1;
+        /** thres1_high_int_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_st:1;
+        /** thres0_high_int_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_st:1;
+        /** apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_done_int_st:1;
+        /** apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_done_int_st:1;
+    };
+    uint32_t val;
+} adc_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_clr : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_clr:1;
+        /** thres0_low_int_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_clr:1;
+        /** thres1_high_int_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_clr:1;
+        /** thres0_high_int_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_clr:1;
+        /** apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_done_int_clr:1;
+        /** apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_done_int_clr:1;
+    };
+    uint32_t val;
+} adc_int_clr_reg_t;
+
+/** Type of dma_conf register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
+         *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+         */
+        uint32_t apb_adc_eof_num:16;
+        uint32_t reserved_16:14;
+        /** apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
+         *  reset_apb_adc_state
+         */
+        uint32_t apb_adc_reset_fsm:1;
+        /** apb_adc_trans : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc use spi_dma
+         */
+        uint32_t apb_adc_trans:1;
+    };
+    uint32_t val;
+} adc_dma_conf_reg_t;
+
+/** Type of sar2_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_sar2_data_status_reg_t;
+
+/** Type of cali register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** cali_cfg : R/W; bitpos: [16:0]; default: 32768;
+         *  need_des
+         */
+        uint32_t cali_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_cali_reg_t;
+
+/** Type of rnd_eco_low register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rnd eco low
+         */
+        uint32_t rnd_eco_low:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_low_reg_t;
+
+/** Type of rnd_eco_high register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rnd eco high
+         */
+        uint32_t rnd_eco_high:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_high_reg_t;
+
+/** Type of rnd_eco_cs register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_en:1;
+        /** rnd_eco_result : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} adc_rnd_eco_cs_reg_t;
+
+/** Type of ctrl_date register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** ctrl_date : R/W; bitpos: [30:0]; default: 35725920;
+         *  need_des
+         */
+        uint32_t ctrl_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} adc_ctrl_date_reg_t;
+
+
+typedef struct {
+    volatile adc_ctrl_reg_reg_t ctrl_reg;
+    volatile adc_ctrl2_reg_t ctrl2;
+    volatile adc_filter_ctrl1_reg_t filter_ctrl1;
+    uint32_t reserved_00c[3];
+    volatile adc_sar1_patt_tab1_reg_t sar1_patt_tab1;
+    volatile adc_sar1_patt_tab2_reg_t sar1_patt_tab2;
+    volatile adc_sar1_patt_tab3_reg_t sar1_patt_tab3;
+    volatile adc_sar1_patt_tab4_reg_t sar1_patt_tab4;
+    volatile adc_sar2_patt_tab1_reg_t sar2_patt_tab1;
+    volatile adc_sar2_patt_tab2_reg_t sar2_patt_tab2;
+    volatile adc_sar2_patt_tab3_reg_t sar2_patt_tab3;
+    volatile adc_sar2_patt_tab4_reg_t sar2_patt_tab4;
+    volatile adc_arb_ctrl_reg_t arb_ctrl;
+    volatile adc_filter_ctrl0_reg_t filter_ctrl0;
+    volatile adc_sar1_data_status_reg_t sar1_data_status;
+    volatile adc_thres0_ctrl_reg_t thres0_ctrl;
+    volatile adc_thres1_ctrl_reg_t thres1_ctrl;
+    volatile adc_thres_ctrl_reg_t thres_ctrl;
+    volatile adc_int_ena_reg_t int_ena;
+    volatile adc_int_raw_reg_t int_raw;
+    volatile adc_int_st_reg_t int_st;
+    volatile adc_int_clr_reg_t int_clr;
+    volatile adc_dma_conf_reg_t dma_conf;
+    volatile adc_sar2_data_status_reg_t sar2_data_status;
+    volatile adc_cali_reg_t cali;
+    volatile adc_rnd_eco_low_reg_t rnd_eco_low;
+    volatile adc_rnd_eco_high_reg_t rnd_eco_high;
+    volatile adc_rnd_eco_cs_reg_t rnd_eco_cs;
+    uint32_t reserved_078[225];
+    volatile adc_ctrl_date_reg_t ctrl_date;
+} adc_dev_t;
+
+extern adc_dev_t ADC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/adc_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/adc_reg.h
new file mode 100644
index 0000000000..2e58050bf7
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/adc_reg.h
@@ -0,0 +1,809 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13426
+
+/** ADC_CTRL_REG_REG register
+ *  Register
+ */
+#define ADC_CTRL_REG_REG (DR_REG_ADC_BASE + 0x0)
+/** ADC_START_FORCE : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_START_FORCE    (BIT(0))
+#define ADC_START_FORCE_M  (ADC_START_FORCE_V << ADC_START_FORCE_S)
+#define ADC_START_FORCE_V  0x00000001U
+#define ADC_START_FORCE_S  0
+/** ADC_START : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_START    (BIT(1))
+#define ADC_START_M  (ADC_START_V << ADC_START_S)
+#define ADC_START_V  0x00000001U
+#define ADC_START_S  1
+/** ADC_WORK_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  0: single mode, 1: double mode, 2: alternate mode
+ */
+#define ADC_WORK_MODE    0x00000003U
+#define ADC_WORK_MODE_M  (ADC_WORK_MODE_V << ADC_WORK_MODE_S)
+#define ADC_WORK_MODE_V  0x00000003U
+#define ADC_WORK_MODE_S  2
+/** ADC_SAR_SEL : R/W; bitpos: [4]; default: 0;
+ *  0: SAR1, 1: SAR2, only work for single SAR mode
+ */
+#define ADC_SAR_SEL    (BIT(4))
+#define ADC_SAR_SEL_M  (ADC_SAR_SEL_V << ADC_SAR_SEL_S)
+#define ADC_SAR_SEL_V  0x00000001U
+#define ADC_SAR_SEL_S  4
+/** ADC_SAR_CLK_GATED : R/W; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define ADC_SAR_CLK_GATED    (BIT(5))
+#define ADC_SAR_CLK_GATED_M  (ADC_SAR_CLK_GATED_V << ADC_SAR_CLK_GATED_S)
+#define ADC_SAR_CLK_GATED_V  0x00000001U
+#define ADC_SAR_CLK_GATED_S  5
+/** ADC_SAR_CLK_DIV : R/W; bitpos: [13:6]; default: 4;
+ *  SAR clock divider
+ */
+#define ADC_SAR_CLK_DIV    0x000000FFU
+#define ADC_SAR_CLK_DIV_M  (ADC_SAR_CLK_DIV_V << ADC_SAR_CLK_DIV_S)
+#define ADC_SAR_CLK_DIV_V  0x000000FFU
+#define ADC_SAR_CLK_DIV_S  6
+/** ADC_SAR1_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR1_PATT_LEN    0x0000000FU
+#define ADC_SAR1_PATT_LEN_M  (ADC_SAR1_PATT_LEN_V << ADC_SAR1_PATT_LEN_S)
+#define ADC_SAR1_PATT_LEN_V  0x0000000FU
+#define ADC_SAR1_PATT_LEN_S  14
+/** ADC_SAR2_PATT_LEN : R/W; bitpos: [21:18]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR2_PATT_LEN    0x0000000FU
+#define ADC_SAR2_PATT_LEN_M  (ADC_SAR2_PATT_LEN_V << ADC_SAR2_PATT_LEN_S)
+#define ADC_SAR2_PATT_LEN_V  0x0000000FU
+#define ADC_SAR2_PATT_LEN_S  18
+/** ADC_SAR1_PATT_P_CLEAR : R/W; bitpos: [22]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC1 CTRL
+ */
+#define ADC_SAR1_PATT_P_CLEAR    (BIT(22))
+#define ADC_SAR1_PATT_P_CLEAR_M  (ADC_SAR1_PATT_P_CLEAR_V << ADC_SAR1_PATT_P_CLEAR_S)
+#define ADC_SAR1_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR1_PATT_P_CLEAR_S  22
+/** ADC_SAR2_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC2 CTRL
+ */
+#define ADC_SAR2_PATT_P_CLEAR    (BIT(23))
+#define ADC_SAR2_PATT_P_CLEAR_M  (ADC_SAR2_PATT_P_CLEAR_V << ADC_SAR2_PATT_P_CLEAR_S)
+#define ADC_SAR2_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR2_PATT_P_CLEAR_S  23
+/** ADC_DATA_SAR_SEL : R/W; bitpos: [24]; default: 0;
+ *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+ *  resolution should not be larger than 11 bits.
+ */
+#define ADC_DATA_SAR_SEL    (BIT(24))
+#define ADC_DATA_SAR_SEL_M  (ADC_DATA_SAR_SEL_V << ADC_DATA_SAR_SEL_S)
+#define ADC_DATA_SAR_SEL_V  0x00000001U
+#define ADC_DATA_SAR_SEL_S  24
+/** ADC_DATA_TO_I2S : R/W; bitpos: [25]; default: 0;
+ *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+ */
+#define ADC_DATA_TO_I2S    (BIT(25))
+#define ADC_DATA_TO_I2S_M  (ADC_DATA_TO_I2S_V << ADC_DATA_TO_I2S_S)
+#define ADC_DATA_TO_I2S_V  0x00000001U
+#define ADC_DATA_TO_I2S_S  25
+/** ADC_XPD_SAR1_FORCE : R/W; bitpos: [27:26]; default: 0;
+ *  force option to xpd sar1 blocks
+ */
+#define ADC_XPD_SAR1_FORCE    0x00000003U
+#define ADC_XPD_SAR1_FORCE_M  (ADC_XPD_SAR1_FORCE_V << ADC_XPD_SAR1_FORCE_S)
+#define ADC_XPD_SAR1_FORCE_V  0x00000003U
+#define ADC_XPD_SAR1_FORCE_S  26
+/** ADC_XPD_SAR2_FORCE : R/W; bitpos: [29:28]; default: 0;
+ *  force option to xpd sar2 blocks
+ */
+#define ADC_XPD_SAR2_FORCE    0x00000003U
+#define ADC_XPD_SAR2_FORCE_M  (ADC_XPD_SAR2_FORCE_V << ADC_XPD_SAR2_FORCE_S)
+#define ADC_XPD_SAR2_FORCE_V  0x00000003U
+#define ADC_XPD_SAR2_FORCE_S  28
+/** ADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
+ *  wait arbit signal stable after sar_done
+ */
+#define ADC_WAIT_ARB_CYCLE    0x00000003U
+#define ADC_WAIT_ARB_CYCLE_M  (ADC_WAIT_ARB_CYCLE_V << ADC_WAIT_ARB_CYCLE_S)
+#define ADC_WAIT_ARB_CYCLE_V  0x00000003U
+#define ADC_WAIT_ARB_CYCLE_S  30
+
+/** ADC_CTRL2_REG register
+ *  Register
+ */
+#define ADC_CTRL2_REG (DR_REG_ADC_BASE + 0x4)
+/** ADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_MEAS_NUM_LIMIT    (BIT(0))
+#define ADC_MEAS_NUM_LIMIT_M  (ADC_MEAS_NUM_LIMIT_V << ADC_MEAS_NUM_LIMIT_S)
+#define ADC_MEAS_NUM_LIMIT_V  0x00000001U
+#define ADC_MEAS_NUM_LIMIT_S  0
+/** ADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
+ *  max conversion number
+ */
+#define ADC_MAX_MEAS_NUM    0x000000FFU
+#define ADC_MAX_MEAS_NUM_M  (ADC_MAX_MEAS_NUM_V << ADC_MAX_MEAS_NUM_S)
+#define ADC_MAX_MEAS_NUM_V  0x000000FFU
+#define ADC_MAX_MEAS_NUM_S  1
+/** ADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
+ *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+ */
+#define ADC_SAR1_INV    (BIT(9))
+#define ADC_SAR1_INV_M  (ADC_SAR1_INV_V << ADC_SAR1_INV_S)
+#define ADC_SAR1_INV_V  0x00000001U
+#define ADC_SAR1_INV_S  9
+/** ADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
+ *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+ */
+#define ADC_SAR2_INV    (BIT(10))
+#define ADC_SAR2_INV_M  (ADC_SAR2_INV_V << ADC_SAR2_INV_S)
+#define ADC_SAR2_INV_V  0x00000001U
+#define ADC_SAR2_INV_S  10
+/** ADC_TIMER_SEL : R/W; bitpos: [11]; default: 0;
+ *  1: select saradc timer 0: i2s_ws trigger
+ */
+#define ADC_TIMER_SEL    (BIT(11))
+#define ADC_TIMER_SEL_M  (ADC_TIMER_SEL_V << ADC_TIMER_SEL_S)
+#define ADC_TIMER_SEL_V  0x00000001U
+#define ADC_TIMER_SEL_S  11
+/** ADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
+ *  to set saradc timer target
+ */
+#define ADC_TIMER_TARGET    0x00000FFFU
+#define ADC_TIMER_TARGET_M  (ADC_TIMER_TARGET_V << ADC_TIMER_TARGET_S)
+#define ADC_TIMER_TARGET_V  0x00000FFFU
+#define ADC_TIMER_TARGET_S  12
+/** ADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
+ *  to enable saradc timer trigger
+ */
+#define ADC_TIMER_EN    (BIT(24))
+#define ADC_TIMER_EN_M  (ADC_TIMER_EN_V << ADC_TIMER_EN_S)
+#define ADC_TIMER_EN_V  0x00000001U
+#define ADC_TIMER_EN_S  24
+
+/** ADC_FILTER_CTRL1_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL1_REG (DR_REG_ADC_BASE + 0x8)
+/** ADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR1    0x00000007U
+#define ADC_FILTER_FACTOR1_M  (ADC_FILTER_FACTOR1_V << ADC_FILTER_FACTOR1_S)
+#define ADC_FILTER_FACTOR1_V  0x00000007U
+#define ADC_FILTER_FACTOR1_S  26
+/** ADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR0    0x00000007U
+#define ADC_FILTER_FACTOR0_M  (ADC_FILTER_FACTOR0_V << ADC_FILTER_FACTOR0_S)
+#define ADC_FILTER_FACTOR0_V  0x00000007U
+#define ADC_FILTER_FACTOR0_S  29
+
+#define ADC_FSM_WAIT_REG          (DR_REG_ADC_BASE + 0xC)
+/* ADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
+/*description: need_des.*/
+#define ADC_STANDBY_WAIT    0x000000FF
+#define ADC_STANDBY_WAIT_M  ((ADC_STANDBY_WAIT_V)<<(ADC_STANDBY_WAIT_S))
+#define ADC_STANDBY_WAIT_V  0xFF
+#define ADC_STANDBY_WAIT_S  16
+/* ADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
+/*description: need_des.*/
+#define ADC_RSTB_WAIT    0x000000FF
+#define ADC_RSTB_WAIT_M  ((ADC_RSTB_WAIT_V)<<(ADC_RSTB_WAIT_S))
+#define ADC_RSTB_WAIT_V  0xFF
+#define ADC_RSTB_WAIT_S  8
+/* ADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
+/*description: need_des.*/
+#define ADC_XPD_WAIT    0x000000FF
+#define ADC_XPD_WAIT_M  ((ADC_XPD_WAIT_V)<<(ADC_XPD_WAIT_S))
+#define ADC_XPD_WAIT_V  0xFF
+#define ADC_XPD_WAIT_S  0
+
+/** ADC_SAR1_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x18)
+/** ADC_SAR1_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
+ *  item 0 ~ 3 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_M  (ADC_SAR1_PATT_TAB1_V << ADC_SAR1_PATT_TAB1_S)
+#define ADC_SAR1_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_S  0
+
+/** ADC_SAR1_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x1c)
+/** ADC_SAR1_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_M  (ADC_SAR1_PATT_TAB2_V << ADC_SAR1_PATT_TAB2_S)
+#define ADC_SAR1_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_S  0
+
+/** ADC_SAR1_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x20)
+/** ADC_SAR1_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_M  (ADC_SAR1_PATT_TAB3_V << ADC_SAR1_PATT_TAB3_S)
+#define ADC_SAR1_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_S  0
+
+/** ADC_SAR1_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x24)
+/** ADC_SAR1_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_M  (ADC_SAR1_PATT_TAB4_V << ADC_SAR1_PATT_TAB4_S)
+#define ADC_SAR1_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_S  0
+
+/** ADC_SAR2_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x28)
+/** ADC_SAR2_PATT_TAB1 : R/W; bitpos: [23:0]; default: 0;
+ *  item 0 ~ 3 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_M  (ADC_SAR2_PATT_TAB1_V << ADC_SAR2_PATT_TAB1_S)
+#define ADC_SAR2_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_S  0
+
+/** ADC_SAR2_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x2c)
+/** ADC_SAR2_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_M  (ADC_SAR2_PATT_TAB2_V << ADC_SAR2_PATT_TAB2_S)
+#define ADC_SAR2_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_S  0
+
+/** ADC_SAR2_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x30)
+/** ADC_SAR2_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_M  (ADC_SAR2_PATT_TAB3_V << ADC_SAR2_PATT_TAB3_S)
+#define ADC_SAR2_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_S  0
+
+/** ADC_SAR2_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x34)
+/** ADC_SAR2_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_M  (ADC_SAR2_PATT_TAB4_V << ADC_SAR2_PATT_TAB4_S)
+#define ADC_SAR2_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_S  0
+
+/** ADC_ARB_CTRL_REG register
+ *  Register
+ */
+#define ADC_ARB_CTRL_REG (DR_REG_ADC_BASE + 0x38)
+/** ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
+ *  adc2 arbiter force to enableapb controller
+ */
+#define ADC_ARB_APB_FORCE    (BIT(2))
+#define ADC_ARB_APB_FORCE_M  (ADC_ARB_APB_FORCE_V << ADC_ARB_APB_FORCE_S)
+#define ADC_ARB_APB_FORCE_V  0x00000001U
+#define ADC_ARB_APB_FORCE_S  2
+/** ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
+ *  adc2 arbiter force to enable rtc controller
+ */
+#define ADC_ARB_RTC_FORCE    (BIT(3))
+#define ADC_ARB_RTC_FORCE_M  (ADC_ARB_RTC_FORCE_V << ADC_ARB_RTC_FORCE_S)
+#define ADC_ARB_RTC_FORCE_V  0x00000001U
+#define ADC_ARB_RTC_FORCE_S  3
+/** ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
+ *  adc2 arbiter force to enable wifi controller
+ */
+#define ADC_ARB_WIFI_FORCE    (BIT(4))
+#define ADC_ARB_WIFI_FORCE_M  (ADC_ARB_WIFI_FORCE_V << ADC_ARB_WIFI_FORCE_S)
+#define ADC_ARB_WIFI_FORCE_V  0x00000001U
+#define ADC_ARB_WIFI_FORCE_S  4
+/** ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
+ *  adc2 arbiter force grant
+ */
+#define ADC_ARB_GRANT_FORCE    (BIT(5))
+#define ADC_ARB_GRANT_FORCE_M  (ADC_ARB_GRANT_FORCE_V << ADC_ARB_GRANT_FORCE_S)
+#define ADC_ARB_GRANT_FORCE_V  0x00000001U
+#define ADC_ARB_GRANT_FORCE_S  5
+/** ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
+ *  Set adc2 arbiterapb priority
+ */
+#define ADC_ARB_APB_PRIORITY    0x00000003U
+#define ADC_ARB_APB_PRIORITY_M  (ADC_ARB_APB_PRIORITY_V << ADC_ARB_APB_PRIORITY_S)
+#define ADC_ARB_APB_PRIORITY_V  0x00000003U
+#define ADC_ARB_APB_PRIORITY_S  6
+/** ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
+ *  Set adc2 arbiter rtc priority
+ */
+#define ADC_ARB_RTC_PRIORITY    0x00000003U
+#define ADC_ARB_RTC_PRIORITY_M  (ADC_ARB_RTC_PRIORITY_V << ADC_ARB_RTC_PRIORITY_S)
+#define ADC_ARB_RTC_PRIORITY_V  0x00000003U
+#define ADC_ARB_RTC_PRIORITY_S  8
+/** ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
+ *  Set adc2 arbiter wifi priority
+ */
+#define ADC_ARB_WIFI_PRIORITY    0x00000003U
+#define ADC_ARB_WIFI_PRIORITY_M  (ADC_ARB_WIFI_PRIORITY_V << ADC_ARB_WIFI_PRIORITY_S)
+#define ADC_ARB_WIFI_PRIORITY_V  0x00000003U
+#define ADC_ARB_WIFI_PRIORITY_S  10
+/** ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
+ *  adc2 arbiter uses fixed priority
+ */
+#define ADC_ARB_FIX_PRIORITY    (BIT(12))
+#define ADC_ARB_FIX_PRIORITY_M  (ADC_ARB_FIX_PRIORITY_V << ADC_ARB_FIX_PRIORITY_S)
+#define ADC_ARB_FIX_PRIORITY_V  0x00000001U
+#define ADC_ARB_FIX_PRIORITY_S  12
+
+/** ADC_FILTER_CTRL0_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL0_REG (DR_REG_ADC_BASE + 0x3c)
+/** ADC_FILTER_CHANNEL1 : R/W; bitpos: [18:14]; default: 13;
+ *  need_des
+ */
+#define ADC_FILTER_CHANNEL1    0x0000001FU
+#define ADC_FILTER_CHANNEL1_M  (ADC_FILTER_CHANNEL1_V << ADC_FILTER_CHANNEL1_S)
+#define ADC_FILTER_CHANNEL1_V  0x0000001FU
+#define ADC_FILTER_CHANNEL1_S  14
+/** ADC_FILTER_CHANNEL0 : R/W; bitpos: [23:19]; default: 13;
+ *  apb_adc1_filter_factor
+ */
+#define ADC_FILTER_CHANNEL0    0x0000001FU
+#define ADC_FILTER_CHANNEL0_M  (ADC_FILTER_CHANNEL0_V << ADC_FILTER_CHANNEL0_S)
+#define ADC_FILTER_CHANNEL0_V  0x0000001FU
+#define ADC_FILTER_CHANNEL0_S  19
+/** ADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc1_filter
+ */
+#define ADC_FILTER_RESET    (BIT(31))
+#define ADC_FILTER_RESET_M  (ADC_FILTER_RESET_V << ADC_FILTER_RESET_S)
+#define ADC_FILTER_RESET_V  0x00000001U
+#define ADC_FILTER_RESET_S  31
+
+/** ADC_SAR1_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR1_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x40)
+/** ADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DATA    0x0001FFFFU
+#define ADC_APB_SARADC1_DATA_M  (ADC_APB_SARADC1_DATA_V << ADC_APB_SARADC1_DATA_S)
+#define ADC_APB_SARADC1_DATA_V  0x0001FFFFU
+#define ADC_APB_SARADC1_DATA_S  0
+
+/** ADC_THRES0_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES0_CTRL_REG (DR_REG_ADC_BASE + 0x44)
+/** ADC_THRES0_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES0_CHANNEL    0x0000001FU
+#define ADC_THRES0_CHANNEL_M  (ADC_THRES0_CHANNEL_V << ADC_THRES0_CHANNEL_S)
+#define ADC_THRES0_CHANNEL_V  0x0000001FU
+#define ADC_THRES0_CHANNEL_S  0
+/** ADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES0_HIGH    0x00001FFFU
+#define ADC_THRES0_HIGH_M  (ADC_THRES0_HIGH_V << ADC_THRES0_HIGH_S)
+#define ADC_THRES0_HIGH_V  0x00001FFFU
+#define ADC_THRES0_HIGH_S  5
+/** ADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES0_LOW    0x00001FFFU
+#define ADC_THRES0_LOW_M  (ADC_THRES0_LOW_V << ADC_THRES0_LOW_S)
+#define ADC_THRES0_LOW_V  0x00001FFFU
+#define ADC_THRES0_LOW_S  18
+
+/** ADC_THRES1_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES1_CTRL_REG (DR_REG_ADC_BASE + 0x48)
+/** ADC_THRES1_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES1_CHANNEL    0x0000001FU
+#define ADC_THRES1_CHANNEL_M  (ADC_THRES1_CHANNEL_V << ADC_THRES1_CHANNEL_S)
+#define ADC_THRES1_CHANNEL_V  0x0000001FU
+#define ADC_THRES1_CHANNEL_S  0
+/** ADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES1_HIGH    0x00001FFFU
+#define ADC_THRES1_HIGH_M  (ADC_THRES1_HIGH_V << ADC_THRES1_HIGH_S)
+#define ADC_THRES1_HIGH_V  0x00001FFFU
+#define ADC_THRES1_HIGH_S  5
+/** ADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
+ *  saradc1's thres0 monitor thres
+ */
+#define ADC_THRES1_LOW    0x00001FFFU
+#define ADC_THRES1_LOW_M  (ADC_THRES1_LOW_V << ADC_THRES1_LOW_S)
+#define ADC_THRES1_LOW_V  0x00001FFFU
+#define ADC_THRES1_LOW_S  18
+
+/** ADC_THRES_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES_CTRL_REG (DR_REG_ADC_BASE + 0x4c)
+/** ADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES_ALL_EN    (BIT(27))
+#define ADC_THRES_ALL_EN_M  (ADC_THRES_ALL_EN_V << ADC_THRES_ALL_EN_S)
+#define ADC_THRES_ALL_EN_V  0x00000001U
+#define ADC_THRES_ALL_EN_S  27
+/** ADC_THRES3_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES3_EN    (BIT(28))
+#define ADC_THRES3_EN_M  (ADC_THRES3_EN_V << ADC_THRES3_EN_S)
+#define ADC_THRES3_EN_V  0x00000001U
+#define ADC_THRES3_EN_S  28
+/** ADC_THRES2_EN : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES2_EN    (BIT(29))
+#define ADC_THRES2_EN_M  (ADC_THRES2_EN_V << ADC_THRES2_EN_S)
+#define ADC_THRES2_EN_V  0x00000001U
+#define ADC_THRES2_EN_S  29
+/** ADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_EN    (BIT(30))
+#define ADC_THRES1_EN_M  (ADC_THRES1_EN_V << ADC_THRES1_EN_S)
+#define ADC_THRES1_EN_V  0x00000001U
+#define ADC_THRES1_EN_S  30
+/** ADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_EN    (BIT(31))
+#define ADC_THRES0_EN_M  (ADC_THRES0_EN_V << ADC_THRES0_EN_S)
+#define ADC_THRES0_EN_V  0x00000001U
+#define ADC_THRES0_EN_S  31
+
+/** ADC_INT_ENA_REG register
+ *  Register
+ */
+#define ADC_INT_ENA_REG (DR_REG_ADC_BASE + 0x50)
+/** ADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ENA    (BIT(26))
+#define ADC_THRES1_LOW_INT_ENA_M  (ADC_THRES1_LOW_INT_ENA_V << ADC_THRES1_LOW_INT_ENA_S)
+#define ADC_THRES1_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ENA_S  26
+/** ADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ENA    (BIT(27))
+#define ADC_THRES0_LOW_INT_ENA_M  (ADC_THRES0_LOW_INT_ENA_V << ADC_THRES0_LOW_INT_ENA_S)
+#define ADC_THRES0_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ENA_S  27
+/** ADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ENA    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ENA_M  (ADC_THRES1_HIGH_INT_ENA_V << ADC_THRES1_HIGH_INT_ENA_S)
+#define ADC_THRES1_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ENA_S  28
+/** ADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ENA    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ENA_M  (ADC_THRES0_HIGH_INT_ENA_V << ADC_THRES0_HIGH_INT_ENA_S)
+#define ADC_THRES0_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ENA_S  29
+/** ADC_SAR2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_ENA    (BIT(30))
+#define ADC_SAR2_DONE_INT_ENA_M  (ADC_SAR2_DONE_INT_ENA_V << ADC_SAR2_DONE_INT_ENA_S)
+#define ADC_SAR2_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR2_DONE_INT_ENA_S  30
+/** ADC_SAR1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_ENA    (BIT(31))
+#define ADC_SAR1_DONE_INT_ENA_M  (ADC_SAR1_DONE_INT_ENA_V << ADC_SAR1_DONE_INT_ENA_S)
+#define ADC_SAR1_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR1_DONE_INT_ENA_S  31
+
+/** ADC_INT_RAW_REG register
+ *  Register
+ */
+#define ADC_INT_RAW_REG (DR_REG_ADC_BASE + 0x54)
+/** ADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_RAW    (BIT(26))
+#define ADC_THRES1_LOW_INT_RAW_M  (ADC_THRES1_LOW_INT_RAW_V << ADC_THRES1_LOW_INT_RAW_S)
+#define ADC_THRES1_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES1_LOW_INT_RAW_S  26
+/** ADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_RAW    (BIT(27))
+#define ADC_THRES0_LOW_INT_RAW_M  (ADC_THRES0_LOW_INT_RAW_V << ADC_THRES0_LOW_INT_RAW_S)
+#define ADC_THRES0_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES0_LOW_INT_RAW_S  27
+/** ADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_RAW    (BIT(28))
+#define ADC_THRES1_HIGH_INT_RAW_M  (ADC_THRES1_HIGH_INT_RAW_V << ADC_THRES1_HIGH_INT_RAW_S)
+#define ADC_THRES1_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_RAW_S  28
+/** ADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_RAW    (BIT(29))
+#define ADC_THRES0_HIGH_INT_RAW_M  (ADC_THRES0_HIGH_INT_RAW_V << ADC_THRES0_HIGH_INT_RAW_S)
+#define ADC_THRES0_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_RAW_S  29
+/** ADC_SAR2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_RAW    (BIT(30))
+#define ADC_SAR2_DONE_INT_RAW_M  (ADC_SAR2_DONE_INT_RAW_V << ADC_SAR2_DONE_INT_RAW_S)
+#define ADC_SAR2_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR2_DONE_INT_RAW_S  30
+/** ADC_SAR1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_RAW    (BIT(31))
+#define ADC_SAR1_DONE_INT_RAW_M  (ADC_SAR1_DONE_INT_RAW_V << ADC_SAR1_DONE_INT_RAW_S)
+#define ADC_SAR1_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR1_DONE_INT_RAW_S  31
+
+/** ADC_INT_ST_REG register
+ *  Register
+ */
+#define ADC_INT_ST_REG (DR_REG_ADC_BASE + 0x58)
+/** ADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ST    (BIT(26))
+#define ADC_THRES1_LOW_INT_ST_M  (ADC_THRES1_LOW_INT_ST_V << ADC_THRES1_LOW_INT_ST_S)
+#define ADC_THRES1_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ST_S  26
+/** ADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ST    (BIT(27))
+#define ADC_THRES0_LOW_INT_ST_M  (ADC_THRES0_LOW_INT_ST_V << ADC_THRES0_LOW_INT_ST_S)
+#define ADC_THRES0_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ST_S  27
+/** ADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ST    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ST_M  (ADC_THRES1_HIGH_INT_ST_V << ADC_THRES1_HIGH_INT_ST_S)
+#define ADC_THRES1_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ST_S  28
+/** ADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ST    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ST_M  (ADC_THRES0_HIGH_INT_ST_V << ADC_THRES0_HIGH_INT_ST_S)
+#define ADC_THRES0_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ST_S  29
+/** ADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DONE_INT_ST    (BIT(30))
+#define ADC_APB_SARADC2_DONE_INT_ST_M  (ADC_APB_SARADC2_DONE_INT_ST_V << ADC_APB_SARADC2_DONE_INT_ST_S)
+#define ADC_APB_SARADC2_DONE_INT_ST_V  0x00000001U
+#define ADC_APB_SARADC2_DONE_INT_ST_S  30
+/** ADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DONE_INT_ST    (BIT(31))
+#define ADC_APB_SARADC1_DONE_INT_ST_M  (ADC_APB_SARADC1_DONE_INT_ST_V << ADC_APB_SARADC1_DONE_INT_ST_S)
+#define ADC_APB_SARADC1_DONE_INT_ST_V  0x00000001U
+#define ADC_APB_SARADC1_DONE_INT_ST_S  31
+
+/** ADC_INT_CLR_REG register
+ *  Register
+ */
+#define ADC_INT_CLR_REG (DR_REG_ADC_BASE + 0x5c)
+/** ADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_CLR    (BIT(26))
+#define ADC_THRES1_LOW_INT_CLR_M  (ADC_THRES1_LOW_INT_CLR_V << ADC_THRES1_LOW_INT_CLR_S)
+#define ADC_THRES1_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES1_LOW_INT_CLR_S  26
+/** ADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_CLR    (BIT(27))
+#define ADC_THRES0_LOW_INT_CLR_M  (ADC_THRES0_LOW_INT_CLR_V << ADC_THRES0_LOW_INT_CLR_S)
+#define ADC_THRES0_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES0_LOW_INT_CLR_S  27
+/** ADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_CLR    (BIT(28))
+#define ADC_THRES1_HIGH_INT_CLR_M  (ADC_THRES1_HIGH_INT_CLR_V << ADC_THRES1_HIGH_INT_CLR_S)
+#define ADC_THRES1_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_CLR_S  28
+/** ADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_CLR    (BIT(29))
+#define ADC_THRES0_HIGH_INT_CLR_M  (ADC_THRES0_HIGH_INT_CLR_V << ADC_THRES0_HIGH_INT_CLR_S)
+#define ADC_THRES0_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_CLR_S  29
+/** ADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DONE_INT_CLR    (BIT(30))
+#define ADC_APB_SARADC2_DONE_INT_CLR_M  (ADC_APB_SARADC2_DONE_INT_CLR_V << ADC_APB_SARADC2_DONE_INT_CLR_S)
+#define ADC_APB_SARADC2_DONE_INT_CLR_V  0x00000001U
+#define ADC_APB_SARADC2_DONE_INT_CLR_S  30
+/** ADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DONE_INT_CLR    (BIT(31))
+#define ADC_APB_SARADC1_DONE_INT_CLR_M  (ADC_APB_SARADC1_DONE_INT_CLR_V << ADC_APB_SARADC1_DONE_INT_CLR_S)
+#define ADC_APB_SARADC1_DONE_INT_CLR_V  0x00000001U
+#define ADC_APB_SARADC1_DONE_INT_CLR_S  31
+
+/** ADC_DMA_CONF_REG register
+ *  Register
+ */
+#define ADC_DMA_CONF_REG (DR_REG_ADC_BASE + 0x60)
+/** ADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
+ *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+ */
+#define ADC_APB_ADC_EOF_NUM    0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_M  (ADC_APB_ADC_EOF_NUM_V << ADC_APB_ADC_EOF_NUM_S)
+#define ADC_APB_ADC_EOF_NUM_V  0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_S  0
+/** ADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
+ *  reset_apb_adc_state
+ */
+#define ADC_APB_ADC_RESET_FSM    (BIT(30))
+#define ADC_APB_ADC_RESET_FSM_M  (ADC_APB_ADC_RESET_FSM_V << ADC_APB_ADC_RESET_FSM_S)
+#define ADC_APB_ADC_RESET_FSM_V  0x00000001U
+#define ADC_APB_ADC_RESET_FSM_S  30
+/** ADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc use spi_dma
+ */
+#define ADC_APB_ADC_TRANS    (BIT(31))
+#define ADC_APB_ADC_TRANS_M  (ADC_APB_ADC_TRANS_V << ADC_APB_ADC_TRANS_S)
+#define ADC_APB_ADC_TRANS_V  0x00000001U
+#define ADC_APB_ADC_TRANS_S  31
+
+/** ADC_SAR2_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR2_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x64)
+/** ADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DATA    0x0001FFFFU
+#define ADC_APB_SARADC2_DATA_M  (ADC_APB_SARADC2_DATA_V << ADC_APB_SARADC2_DATA_S)
+#define ADC_APB_SARADC2_DATA_V  0x0001FFFFU
+#define ADC_APB_SARADC2_DATA_S  0
+
+/** ADC_CALI_REG register
+ *  Register
+ */
+#define ADC_CALI_REG (DR_REG_ADC_BASE + 0x68)
+/** ADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
+ *  need_des
+ */
+#define ADC_CALI_CFG    0x0001FFFFU
+#define ADC_CALI_CFG_M  (ADC_CALI_CFG_V << ADC_CALI_CFG_S)
+#define ADC_CALI_CFG_V  0x0001FFFFU
+#define ADC_CALI_CFG_S  0
+
+/** ADC_RND_ECO_LOW_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_LOW_REG (DR_REG_ADC_BASE + 0x6c)
+/** ADC_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  rnd eco low
+ */
+#define ADC_RND_ECO_LOW    0xFFFFFFFFU
+#define ADC_RND_ECO_LOW_M  (ADC_RND_ECO_LOW_V << ADC_RND_ECO_LOW_S)
+#define ADC_RND_ECO_LOW_V  0xFFFFFFFFU
+#define ADC_RND_ECO_LOW_S  0
+
+/** ADC_RND_ECO_HIGH_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_HIGH_REG (DR_REG_ADC_BASE + 0x70)
+/** ADC_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  rnd eco high
+ */
+#define ADC_RND_ECO_HIGH    0xFFFFFFFFU
+#define ADC_RND_ECO_HIGH_M  (ADC_RND_ECO_HIGH_V << ADC_RND_ECO_HIGH_S)
+#define ADC_RND_ECO_HIGH_V  0xFFFFFFFFU
+#define ADC_RND_ECO_HIGH_S  0
+
+/** ADC_RND_ECO_CS_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_CS_REG (DR_REG_ADC_BASE + 0x74)
+/** ADC_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_EN    (BIT(0))
+#define ADC_RND_ECO_EN_M  (ADC_RND_ECO_EN_V << ADC_RND_ECO_EN_S)
+#define ADC_RND_ECO_EN_V  0x00000001U
+#define ADC_RND_ECO_EN_S  0
+/** ADC_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_RESULT    (BIT(1))
+#define ADC_RND_ECO_RESULT_M  (ADC_RND_ECO_RESULT_V << ADC_RND_ECO_RESULT_S)
+#define ADC_RND_ECO_RESULT_V  0x00000001U
+#define ADC_RND_ECO_RESULT_S  1
+
+/** ADC_CTRL_DATE_REG register
+ *  Register
+ */
+#define ADC_CTRL_DATE_REG (DR_REG_ADC_BASE + 0x3fc)
+/** ADC_CTRL_DATE : R/W; bitpos: [30:0]; default: 35725920;
+ *  need_des
+ */
+#define ADC_CTRL_DATE    0x7FFFFFFFU
+#define ADC_CTRL_DATE_M  (ADC_CTRL_DATE_V << ADC_CTRL_DATE_S)
+#define ADC_CTRL_DATE_V  0x7FFFFFFFU
+#define ADC_CTRL_DATE_S  0
+/** ADC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_CLK_EN    (BIT(31))
+#define ADC_CLK_EN_M  (ADC_CLK_EN_V << ADC_CLK_EN_S)
+#define ADC_CLK_EN_V  0x00000001U
+#define ADC_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/adc_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/adc_struct.h
new file mode 100644
index 0000000000..1103ce9498
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/adc_struct.h
@@ -0,0 +1,621 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13426
+
+/** Group: Configure Register */
+/** Type of ctrl_reg register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** start_force : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t start_force:1;
+        /** start : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t start:1;
+        /** work_mode : R/W; bitpos: [3:2]; default: 0;
+         *  0: single mode, 1: double mode, 2: alternate mode
+         */
+        uint32_t work_mode:2;
+        /** sar_sel : R/W; bitpos: [4]; default: 0;
+         *  0: SAR1, 1: SAR2, only work for single SAR mode
+         */
+        uint32_t sar_sel:1;
+        /** sar_clk_gated : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t sar_clk_gated:1;
+        /** sar_clk_div : R/W; bitpos: [13:6]; default: 4;
+         *  SAR clock divider
+         */
+        uint32_t sar_clk_div:8;
+        /** sar1_patt_len : R/W; bitpos: [17:14]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar1_patt_len:4;
+        /** sar2_patt_len : R/W; bitpos: [21:18]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar2_patt_len:4;
+        /** sar1_patt_p_clear : R/W; bitpos: [22]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC1 CTRL
+         */
+        uint32_t sar1_patt_p_clear:1;
+        /** sar2_patt_p_clear : R/W; bitpos: [23]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC2 CTRL
+         */
+        uint32_t sar2_patt_p_clear:1;
+        /** data_sar_sel : R/W; bitpos: [24]; default: 0;
+         *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+         *  resolution should not be larger than 11 bits.
+         */
+        uint32_t data_sar_sel:1;
+        /** data_to_i2s : R/W; bitpos: [25]; default: 0;
+         *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+         */
+        uint32_t data_to_i2s:1;
+        /** xpd_sar1_force : R/W; bitpos: [27:26]; default: 0;
+         *  force option to xpd sar1 blocks
+         */
+        uint32_t xpd_sar1_force:2;
+        /** xpd_sar2_force : R/W; bitpos: [29:28]; default: 0;
+         *  force option to xpd sar2 blocks
+         */
+        uint32_t xpd_sar2_force:2;
+        /** wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
+         *  wait arbit signal stable after sar_done
+         */
+        uint32_t wait_arb_cycle:2;
+    };
+    uint32_t val;
+} adc_ctrl_reg_reg_t;
+
+/** Type of ctrl2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** meas_num_limit : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t meas_num_limit:1;
+        /** max_meas_num : R/W; bitpos: [8:1]; default: 255;
+         *  max conversion number
+         */
+        uint32_t max_meas_num:8;
+        /** sar1_inv : R/W; bitpos: [9]; default: 0;
+         *  1: data to DIG ADC1 CTRL is inverted, otherwise not
+         */
+        uint32_t sar1_inv:1;
+        /** sar2_inv : R/W; bitpos: [10]; default: 0;
+         *  1: data to DIG ADC2 CTRL is inverted, otherwise not
+         */
+        uint32_t sar2_inv:1;
+        /** timer_sel : R/W; bitpos: [11]; default: 0;
+         *  1: select saradc timer 0: i2s_ws trigger
+         */
+        uint32_t timer_sel:1;
+        /** timer_target : R/W; bitpos: [23:12]; default: 10;
+         *  to set saradc timer target
+         */
+        uint32_t timer_target:12;
+        /** timer_en : R/W; bitpos: [24]; default: 0;
+         *  to enable saradc timer trigger
+         */
+        uint32_t timer_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} adc_ctrl2_reg_t;
+
+/** Type of filter_ctrl1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** filter_factor1 : R/W; bitpos: [28:26]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor1:3;
+        /** filter_factor0 : R/W; bitpos: [31:29]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor0:3;
+    };
+    uint32_t val;
+} adc_filter_ctrl1_reg_t;
+
+/** Type of filter_ctrl1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t xpd_wait:8;
+        uint32_t rstb_wait:8;
+        uint32_t standby_wait:8;
+        uint32_t reserved24:8;
+    };
+    uint32_t val;
+} adc_fsm_wait_reg_t;
+
+/** Type of sar1_patt_tab register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab : R/W; bitpos: [23:0]; default: 0;
+         *  item 0 ~ 3 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab_reg_t;
+
+/** Type of sar2_patt_tab1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab : R/W; bitpos: [23:0]; default: 0;
+         *  item 0 ~ 3 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab_reg_t;
+
+/** Type of arb_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** arb_apb_force : R/W; bitpos: [2]; default: 0;
+         *  adc2 arbiter force to enableapb controller
+         */
+        uint32_t arb_apb_force:1;
+        /** arb_rtc_force : R/W; bitpos: [3]; default: 0;
+         *  adc2 arbiter force to enable rtc controller
+         */
+        uint32_t arb_rtc_force:1;
+        /** arb_wifi_force : R/W; bitpos: [4]; default: 0;
+         *  adc2 arbiter force to enable wifi controller
+         */
+        uint32_t arb_wifi_force:1;
+        /** arb_grant_force : R/W; bitpos: [5]; default: 0;
+         *  adc2 arbiter force grant
+         */
+        uint32_t arb_grant_force:1;
+        /** arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
+         *  Set adc2 arbiterapb priority
+         */
+        uint32_t arb_apb_priority:2;
+        /** arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
+         *  Set adc2 arbiter rtc priority
+         */
+        uint32_t arb_rtc_priority:2;
+        /** arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
+         *  Set adc2 arbiter wifi priority
+         */
+        uint32_t arb_wifi_priority:2;
+        /** arb_fix_priority : R/W; bitpos: [12]; default: 0;
+         *  adc2 arbiter uses fixed priority
+         */
+        uint32_t arb_fix_priority:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} adc_arb_ctrl_reg_t;
+
+/** Type of filter_ctrl0 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** filter_channel1 : R/W; bitpos: [18:14]; default: 13;
+         *  need_des
+         */
+        uint32_t filter_channel1:5;
+        /** filter_channel0 : R/W; bitpos: [23:19]; default: 13;
+         *  apb_adc1_filter_factor
+         */
+        uint32_t filter_channel0:5;
+        uint32_t reserved_24:7;
+        /** filter_reset : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc1_filter
+         */
+        uint32_t filter_reset:1;
+    };
+    uint32_t val;
+} adc_filter_ctrl0_reg_t;
+
+/** Type of sar1_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc1_data : RO; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_sar1_data_status_reg_t;
+
+/** Type of thres0_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres0_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres0_channel:5;
+        /** thres0_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres0_high:13;
+        /** thres0_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres0_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} adc_thres0_ctrl_reg_t;
+
+/** Type of thres1_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres1_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres1_channel:5;
+        /** thres1_high : R/W; bitpos: [17:5]; default: 8191;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres1_high:13;
+        /** thres1_low : R/W; bitpos: [30:18]; default: 0;
+         *  saradc1's thres0 monitor thres
+         */
+        uint32_t thres1_low:13;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} adc_thres1_ctrl_reg_t;
+
+/** Type of thres_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** thres_all_en : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres_all_en:1;
+        /** thres3_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres3_en:1;
+        /** thres2_en : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres2_en:1;
+        /** thres1_en : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_en:1;
+        /** thres0_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_en:1;
+    };
+    uint32_t val;
+} adc_thres_ctrl_reg_t;
+
+/** Type of int_ena register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_ena:1;
+        /** thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_ena:1;
+        /** thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_ena:1;
+        /** thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_ena:1;
+        /** sar2_done_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_ena:1;
+        /** sar1_done_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_ena:1;
+    };
+    uint32_t val;
+} adc_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_raw:1;
+        /** thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_raw:1;
+        /** thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_raw:1;
+        /** thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_raw:1;
+        /** sar2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_raw:1;
+        /** sar1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_raw:1;
+    };
+    uint32_t val;
+} adc_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_st : RO; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_st:1;
+        /** thres0_low_int_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_st:1;
+        /** thres1_high_int_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_st:1;
+        /** thres0_high_int_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_st:1;
+        /** apb_saradc2_done_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_done_int_st:1;
+        /** apb_saradc1_done_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_done_int_st:1;
+    };
+    uint32_t val;
+} adc_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** thres1_low_int_clr : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_clr:1;
+        /** thres0_low_int_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_clr:1;
+        /** thres1_high_int_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_clr:1;
+        /** thres0_high_int_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_clr:1;
+        /** apb_saradc2_done_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_done_int_clr:1;
+        /** apb_saradc1_done_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_done_int_clr:1;
+    };
+    uint32_t val;
+} adc_int_clr_reg_t;
+
+/** Type of dma_conf register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
+         *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+         */
+        uint32_t apb_adc_eof_num:16;
+        uint32_t reserved_16:14;
+        /** apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
+         *  reset_apb_adc_state
+         */
+        uint32_t apb_adc_reset_fsm:1;
+        /** apb_adc_trans : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc use spi_dma
+         */
+        uint32_t apb_adc_trans:1;
+    };
+    uint32_t val;
+} adc_dma_conf_reg_t;
+
+/** Type of sar2_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc2_data : RO; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_data:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_sar2_data_status_reg_t;
+
+/** Type of cali register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** cali_cfg : R/W; bitpos: [16:0]; default: 32768;
+         *  need_des
+         */
+        uint32_t cali_cfg:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_cali_reg_t;
+
+/** Type of rnd_eco_low register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rnd eco low
+         */
+        uint32_t rnd_eco_low:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_low_reg_t;
+
+/** Type of rnd_eco_high register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rnd eco high
+         */
+        uint32_t rnd_eco_high:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_high_reg_t;
+
+/** Type of rnd_eco_cs register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_en:1;
+        /** rnd_eco_result : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} adc_rnd_eco_cs_reg_t;
+
+/** Type of ctrl_date register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** ctrl_date : R/W; bitpos: [30:0]; default: 35725920;
+         *  need_des
+         */
+        uint32_t ctrl_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} adc_ctrl_date_reg_t;
+
+
+typedef struct {
+    volatile adc_ctrl_reg_reg_t ctrl_reg;
+    volatile adc_ctrl2_reg_t ctrl2;
+    volatile adc_filter_ctrl1_reg_t filter_ctrl1;
+    volatile adc_fsm_wait_reg_t fsm_wait;
+    uint32_t reserved_00c[2];
+    volatile adc_sar1_patt_tab_reg_t sar1_patt_tab[4];
+    volatile adc_sar2_patt_tab_reg_t sar2_patt_tab[4];
+    volatile adc_arb_ctrl_reg_t arb_ctrl;
+    volatile adc_filter_ctrl0_reg_t filter_ctrl0;
+    volatile adc_sar1_data_status_reg_t sar1_data_status;
+    volatile adc_thres0_ctrl_reg_t thres0_ctrl;
+    volatile adc_thres1_ctrl_reg_t thres1_ctrl;
+    volatile adc_thres_ctrl_reg_t thres_ctrl;
+    volatile adc_int_ena_reg_t int_ena;
+    volatile adc_int_raw_reg_t int_raw;
+    volatile adc_int_st_reg_t int_st;
+    volatile adc_int_clr_reg_t int_clr;
+    volatile adc_dma_conf_reg_t dma_conf;
+    volatile adc_sar2_data_status_reg_t sar2_data_status;
+    volatile adc_cali_reg_t cali;
+    volatile adc_rnd_eco_low_reg_t rnd_eco_low;
+    volatile adc_rnd_eco_high_reg_t rnd_eco_high;
+    volatile adc_rnd_eco_cs_reg_t rnd_eco_cs;
+    uint32_t reserved_078[225];
+    volatile adc_ctrl_date_reg_t ctrl_date;
+} adc_dev_t;
+
+extern adc_dev_t ADC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/aes_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/aes_eco5_reg.h
new file mode 100644
index 0000000000..5d8b0b9a53
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/aes_eco5_reg.h
@@ -0,0 +1,462 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AES_KEY_0_REG register
+ *  AES key data register 0
+ */
+#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_1_REG register
+ *  AES key data register 1
+ */
+#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_2_REG register
+ *  AES key data register 2
+ */
+#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_3_REG register
+ *  AES key data register 3
+ */
+#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_4_REG register
+ *  AES key data register 4
+ */
+#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_5_REG register
+ *  AES key data register 5
+ */
+#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_6_REG register
+ *  AES key data register 6
+ */
+#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_7_REG register
+ *  AES key data register 7
+ */
+#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_TEXT_IN_0_REG register
+ *  Source text data register 0
+ */
+#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_1_REG register
+ *  Source text data register 1
+ */
+#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_2_REG register
+ *  Source text data register 2
+ */
+#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_3_REG register
+ *  Source text data register 3
+ */
+#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_OUT_0_REG register
+ *  Result text data register 0
+ */
+#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_1_REG register
+ *  Result text data register 1
+ */
+#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_2_REG register
+ *  Result text data register 2
+ */
+#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_3_REG register
+ *  Result text data register 3
+ */
+#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_MODE_REG register
+ *  Defines key length and encryption / decryption
+ */
+#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
+/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the key length and encryption / decryption of the AES accelerator.
+ *  0: AES-128 encryption
+ *  1: AES-192 encryption
+ *  2: AES-256 encryption
+ *  3: Reserved
+ *  4: AES-128 decryption
+ *  5: AES-192 decryption
+ *  6: AES-256 decryption
+ *  7: Reserved
+ */
+#define AES_MODE    0x00000007U
+#define AES_MODE_M  (AES_MODE_V << AES_MODE_S)
+#define AES_MODE_V  0x00000007U
+#define AES_MODE_S  0
+
+/** AES_TRIGGER_REG register
+ *  Operation start controlling register
+ */
+#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
+/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to start AES operation.
+ *  0: No effect
+ *  1: Start
+ */
+#define AES_TRIGGER    (BIT(0))
+#define AES_TRIGGER_M  (AES_TRIGGER_V << AES_TRIGGER_S)
+#define AES_TRIGGER_V  0x00000001U
+#define AES_TRIGGER_S  0
+
+/** AES_STATE_REG register
+ *  Operation status register
+ */
+#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
+/** AES_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Represents the working status of the AES accelerator.
+ *  In Typical AES working mode:
+ *  0: IDLE
+ *  1: WORK
+ *  2: No effect
+ *  3: No effect
+ *  In DMA-AES working mode:
+ *  0: IDLE
+ *  1: WORK
+ *  2: DONE
+ *  3: No effect
+ */
+#define AES_STATE    0x00000003U
+#define AES_STATE_M  (AES_STATE_V << AES_STATE_S)
+#define AES_STATE_V  0x00000003U
+#define AES_STATE_S  0
+
+/** AES_IV_MEM register
+ *  The memory that stores initialization vector
+ */
+#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
+#define AES_IV_MEM_SIZE_BYTES 16
+
+/** AES_H_MEM register
+ *  The memory that stores GCM hash subkey
+ */
+#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
+#define AES_H_MEM_SIZE_BYTES 16
+
+/** AES_J0_MEM register
+ *  The memory that stores J0
+ */
+#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
+#define AES_J0_MEM_SIZE_BYTES 16
+
+/** AES_T0_MEM register
+ *  The memory that stores T0
+ */
+#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
+#define AES_T0_MEM_SIZE_BYTES 16
+
+/** AES_DMA_ENABLE_REG register
+ *  Selects the working mode of the AES accelerator
+ */
+#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
+/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Configures the working mode of the AES accelerator.
+ *  0: Typical AES
+ *  1: DMA-AES
+ */
+#define AES_DMA_ENABLE    (BIT(0))
+#define AES_DMA_ENABLE_M  (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
+#define AES_DMA_ENABLE_V  0x00000001U
+#define AES_DMA_ENABLE_S  0
+
+/** AES_BLOCK_MODE_REG register
+ *  Defines the block cipher mode
+ */
+#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
+/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the block cipher mode of the AES accelerator operating under the DMA-AES
+ *  working mode.
+ *  0: ECB (Electronic Code Block)
+ *  1: CBC (Cipher Block Chaining)
+ *  2: OFB (Output FeedBack)
+ *  3: CTR (Counter)
+ *  4: CFB8 (8-bit Cipher FeedBack)
+ *  5: CFB128 (128-bit Cipher FeedBack)
+ *  6: GCM
+ *  7: Reserved
+ */
+#define AES_BLOCK_MODE    0x00000007U
+#define AES_BLOCK_MODE_M  (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
+#define AES_BLOCK_MODE_V  0x00000007U
+#define AES_BLOCK_MODE_S  0
+
+/** AES_BLOCK_NUM_REG register
+ *  Block number configuration register
+ */
+#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
+/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
+ *  Represents the Block Number of plaintext or ciphertext when the AES accelerator
+ *  operates under the DMA-AES working mode. For details, see Section . "
+ */
+#define AES_BLOCK_NUM    0xFFFFFFFFU
+#define AES_BLOCK_NUM_M  (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
+#define AES_BLOCK_NUM_V  0xFFFFFFFFU
+#define AES_BLOCK_NUM_S  0
+
+/** AES_INC_SEL_REG register
+ *  Standard incrementing function register
+ */
+#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
+/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures the Standard Incrementing Function for CTR block operation.
+ *  0: INC_32
+ *  1: INC_128
+ */
+#define AES_INC_SEL    (BIT(0))
+#define AES_INC_SEL_M  (AES_INC_SEL_V << AES_INC_SEL_S)
+#define AES_INC_SEL_V  0x00000001U
+#define AES_INC_SEL_S  0
+
+/** AES_INT_CLEAR_REG register
+ *  DMA-AES interrupt clear register
+ */
+#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
+/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear AES interrupt.
+ *  0: No effect
+ *  1: Clear
+ */
+#define AES_INT_CLEAR    (BIT(0))
+#define AES_INT_CLEAR_M  (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
+#define AES_INT_CLEAR_V  0x00000001U
+#define AES_INT_CLEAR_S  0
+
+/** AES_INT_ENA_REG register
+ *  DMA-AES interrupt enable register
+ */
+#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
+/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable AES interrupt.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AES_INT_ENA    (BIT(0))
+#define AES_INT_ENA_M  (AES_INT_ENA_V << AES_INT_ENA_S)
+#define AES_INT_ENA_V  0x00000001U
+#define AES_INT_ENA_S  0
+
+/** AES_DATE_REG register
+ *  AES version control register
+ */
+#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
+/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000;
+ *  This bits stores the version information of AES.
+ */
+#define AES_DATE    0x0FFFFFFFU
+#define AES_DATE_M  (AES_DATE_V << AES_DATE_S)
+#define AES_DATE_V  0x0FFFFFFFU
+#define AES_DATE_S  0
+
+/** AES_DMA_EXIT_REG register
+ *  Operation exit controlling register
+ */
+#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
+/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to exit AES operation.
+ *  0: No effect
+ *  1: Exit
+ *  Only valid for DMA-AES operation.
+ */
+#define AES_DMA_EXIT    (BIT(0))
+#define AES_DMA_EXIT_M  (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
+#define AES_DMA_EXIT_V  0x00000001U
+#define AES_DMA_EXIT_S  0
+
+/** AES_RX_RESET_REG register
+ *  AES-DMA reset rx-fifo register
+ */
+#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
+/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset rx_fifo under dma_aes working mode.
+ */
+#define AES_RX_RESET    (BIT(0))
+#define AES_RX_RESET_M  (AES_RX_RESET_V << AES_RX_RESET_S)
+#define AES_RX_RESET_V  0x00000001U
+#define AES_RX_RESET_S  0
+
+/** AES_TX_RESET_REG register
+ *  AES-DMA reset tx-fifo register
+ */
+#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
+/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset tx_fifo under dma_aes working mode.
+ */
+#define AES_TX_RESET    (BIT(0))
+#define AES_TX_RESET_M  (AES_TX_RESET_V << AES_TX_RESET_S)
+#define AES_TX_RESET_V  0x00000001U
+#define AES_TX_RESET_S  0
+
+/** AES_PSEUDO_REG register
+ *  AES PSEUDO function configure register
+ */
+#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
+/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
+ *  This bit decides whether the pseudo round function is enable or not.
+ */
+#define AES_PSEUDO_EN    (BIT(0))
+#define AES_PSEUDO_EN_M  (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
+#define AES_PSEUDO_EN_V  0x00000001U
+#define AES_PSEUDO_EN_S  0
+/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
+ *  Those bits decides the basic number of pseudo round number.
+ */
+#define AES_PSEUDO_BASE    0x0000000FU
+#define AES_PSEUDO_BASE_M  (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
+#define AES_PSEUDO_BASE_V  0x0000000FU
+#define AES_PSEUDO_BASE_S  1
+/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
+ *  Those bits decides the increment number of pseudo round number
+ */
+#define AES_PSEUDO_INC    0x00000003U
+#define AES_PSEUDO_INC_M  (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
+#define AES_PSEUDO_INC_V  0x00000003U
+#define AES_PSEUDO_INC_S  5
+/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
+ *  Those bits decides the update frequency of the pseudo-key.
+ */
+#define AES_PSEUDO_RNG_CNT    0x00000007U
+#define AES_PSEUDO_RNG_CNT_M  (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
+#define AES_PSEUDO_RNG_CNT_V  0x00000007U
+#define AES_PSEUDO_RNG_CNT_S  7
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/aes_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/aes_reg.h
new file mode 100644
index 0000000000..741786dbf1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/aes_reg.h
@@ -0,0 +1,417 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AES_KEY_0_REG register
+ *  Key material key_0 configure register
+ */
+#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_1_REG register
+ *  Key material key_1 configure register
+ */
+#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
+/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_1 that is a part of key material.
+ */
+#define AES_KEY_1    0xFFFFFFFFU
+#define AES_KEY_1_M  (AES_KEY_1_V << AES_KEY_1_S)
+#define AES_KEY_1_V  0xFFFFFFFFU
+#define AES_KEY_1_S  0
+
+/** AES_KEY_2_REG register
+ *  Key material key_2 configure register
+ */
+#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
+/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_2 that is a part of key material.
+ */
+#define AES_KEY_2    0xFFFFFFFFU
+#define AES_KEY_2_M  (AES_KEY_2_V << AES_KEY_2_S)
+#define AES_KEY_2_V  0xFFFFFFFFU
+#define AES_KEY_2_S  0
+
+/** AES_KEY_3_REG register
+ *  Key material key_3 configure register
+ */
+#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
+/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_3 that is a part of key material.
+ */
+#define AES_KEY_3    0xFFFFFFFFU
+#define AES_KEY_3_M  (AES_KEY_3_V << AES_KEY_3_S)
+#define AES_KEY_3_V  0xFFFFFFFFU
+#define AES_KEY_3_S  0
+
+/** AES_KEY_4_REG register
+ *  Key material key_4 configure register
+ */
+#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
+/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_4 that is a part of key material.
+ */
+#define AES_KEY_4    0xFFFFFFFFU
+#define AES_KEY_4_M  (AES_KEY_4_V << AES_KEY_4_S)
+#define AES_KEY_4_V  0xFFFFFFFFU
+#define AES_KEY_4_S  0
+
+/** AES_KEY_5_REG register
+ *  Key material key_5 configure register
+ */
+#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
+/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_5 that is a part of key material.
+ */
+#define AES_KEY_5    0xFFFFFFFFU
+#define AES_KEY_5_M  (AES_KEY_5_V << AES_KEY_5_S)
+#define AES_KEY_5_V  0xFFFFFFFFU
+#define AES_KEY_5_S  0
+
+/** AES_KEY_6_REG register
+ *  Key material key_6 configure register
+ */
+#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
+/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_6 that is a part of key material.
+ */
+#define AES_KEY_6    0xFFFFFFFFU
+#define AES_KEY_6_M  (AES_KEY_6_V << AES_KEY_6_S)
+#define AES_KEY_6_V  0xFFFFFFFFU
+#define AES_KEY_6_S  0
+
+/** AES_KEY_7_REG register
+ *  Key material key_7 configure register
+ */
+#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
+/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_7 that is a part of key material.
+ */
+#define AES_KEY_7    0xFFFFFFFFU
+#define AES_KEY_7_M  (AES_KEY_7_V << AES_KEY_7_S)
+#define AES_KEY_7_V  0xFFFFFFFFU
+#define AES_KEY_7_S  0
+
+/** AES_TEXT_IN_0_REG register
+ *  source text material text_in_0 configure register
+ */
+#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_1_REG register
+ *  source text material text_in_1 configure register
+ */
+#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
+/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_1 that is a part of source text material.
+ */
+#define AES_TEXT_IN_1    0xFFFFFFFFU
+#define AES_TEXT_IN_1_M  (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S)
+#define AES_TEXT_IN_1_V  0xFFFFFFFFU
+#define AES_TEXT_IN_1_S  0
+
+/** AES_TEXT_IN_2_REG register
+ *  source text material text_in_2 configure register
+ */
+#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
+/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_2 that is a part of source text material.
+ */
+#define AES_TEXT_IN_2    0xFFFFFFFFU
+#define AES_TEXT_IN_2_M  (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S)
+#define AES_TEXT_IN_2_V  0xFFFFFFFFU
+#define AES_TEXT_IN_2_S  0
+
+/** AES_TEXT_IN_3_REG register
+ *  source text material text_in_3 configure register
+ */
+#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
+/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_3 that is a part of source text material.
+ */
+#define AES_TEXT_IN_3    0xFFFFFFFFU
+#define AES_TEXT_IN_3_M  (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S)
+#define AES_TEXT_IN_3_V  0xFFFFFFFFU
+#define AES_TEXT_IN_3_S  0
+
+/** AES_TEXT_OUT_0_REG register
+ *  result text material text_out_0 configure register
+ */
+#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_1_REG register
+ *  result text material text_out_1 configure register
+ */
+#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
+/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_1 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_1    0xFFFFFFFFU
+#define AES_TEXT_OUT_1_M  (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S)
+#define AES_TEXT_OUT_1_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_1_S  0
+
+/** AES_TEXT_OUT_2_REG register
+ *  result text material text_out_2 configure register
+ */
+#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
+/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_2 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_2    0xFFFFFFFFU
+#define AES_TEXT_OUT_2_M  (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S)
+#define AES_TEXT_OUT_2_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_2_S  0
+
+/** AES_TEXT_OUT_3_REG register
+ *  result text material text_out_3 configure register
+ */
+#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
+/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_3 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_3    0xFFFFFFFFU
+#define AES_TEXT_OUT_3_M  (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S)
+#define AES_TEXT_OUT_3_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_3_S  0
+
+/** AES_MODE_REG register
+ *  AES Mode register
+ */
+#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
+/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
+ *  Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
+ */
+#define AES_MODE    0x00000007U
+#define AES_MODE_M  (AES_MODE_V << AES_MODE_S)
+#define AES_MODE_V  0x00000007U
+#define AES_MODE_S  0
+
+/** AES_ENDIAN_REG register
+ *  AES Endian configure register
+ */
+#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44)
+/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0;
+ *  endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out
+ *  endian or out_stream endian
+ */
+#define AES_ENDIAN    0x0000003FU
+#define AES_ENDIAN_M  (AES_ENDIAN_V << AES_ENDIAN_S)
+#define AES_ENDIAN_V  0x0000003FU
+#define AES_ENDIAN_S  0
+
+/** AES_TRIGGER_REG register
+ *  AES trigger register
+ */
+#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
+/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start AES calculation.
+ */
+#define AES_TRIGGER    (BIT(0))
+#define AES_TRIGGER_M  (AES_TRIGGER_V << AES_TRIGGER_S)
+#define AES_TRIGGER_V  0x00000001U
+#define AES_TRIGGER_S  0
+
+/** AES_STATE_REG register
+ *  AES state register
+ */
+#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
+/** AES_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
+ *  idle, 1: busy, 2: calculation_done.
+ */
+#define AES_STATE    0x00000003U
+#define AES_STATE_M  (AES_STATE_V << AES_STATE_S)
+#define AES_STATE_V  0x00000003U
+#define AES_STATE_S  0
+
+/** AES_IV_MEM register
+ *  The memory that stores initialization vector
+ */
+#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
+#define AES_IV_MEM_SIZE_BYTES 16
+
+/** AES_H_MEM register
+ *  The memory that stores GCM hash subkey
+ */
+#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
+#define AES_H_MEM_SIZE_BYTES 16
+
+/** AES_J0_MEM register
+ *  The memory that stores J0
+ */
+#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
+#define AES_J0_MEM_SIZE_BYTES 16
+
+/** AES_T0_MEM register
+ *  The memory that stores T0
+ */
+#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
+#define AES_T0_MEM_SIZE_BYTES 16
+
+/** AES_DMA_ENABLE_REG register
+ *  DMA-AES working mode register
+ */
+#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
+/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
+ */
+#define AES_DMA_ENABLE    (BIT(0))
+#define AES_DMA_ENABLE_M  (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
+#define AES_DMA_ENABLE_V  0x00000001U
+#define AES_DMA_ENABLE_S  0
+
+/** AES_BLOCK_MODE_REG register
+ *  AES cipher block mode register
+ */
+#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
+/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
+ *  0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
+ */
+#define AES_BLOCK_MODE    0x00000007U
+#define AES_BLOCK_MODE_M  (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
+#define AES_BLOCK_MODE_V  0x00000007U
+#define AES_BLOCK_MODE_S  0
+
+/** AES_BLOCK_NUM_REG register
+ *  AES block number register
+ */
+#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
+/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits stores the number of Plaintext/ciphertext block.
+ */
+#define AES_BLOCK_NUM    0xFFFFFFFFU
+#define AES_BLOCK_NUM_M  (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
+#define AES_BLOCK_NUM_V  0xFFFFFFFFU
+#define AES_BLOCK_NUM_S  0
+
+/** AES_INC_SEL_REG register
+ *  Standard incrementing function configure register
+ */
+#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
+/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
+ *  This bit decides the standard incrementing function. 0: INC32. 1: INC128.
+ */
+#define AES_INC_SEL    (BIT(0))
+#define AES_INC_SEL_M  (AES_INC_SEL_V << AES_INC_SEL_S)
+#define AES_INC_SEL_V  0x00000001U
+#define AES_INC_SEL_S  0
+
+/** AES_AAD_BLOCK_NUM_REG register
+ *  Additional Authential Data block number register
+ */
+#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0)
+/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits stores the number of AAD block.
+ */
+#define AES_AAD_BLOCK_NUM    0xFFFFFFFFU
+#define AES_AAD_BLOCK_NUM_M  (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S)
+#define AES_AAD_BLOCK_NUM_V  0xFFFFFFFFU
+#define AES_AAD_BLOCK_NUM_S  0
+
+/** AES_REMAINDER_BIT_NUM_REG register
+ *  AES remainder bit number register
+ */
+#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4)
+/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0;
+ *  Those bits stores the number of remainder bit.
+ */
+#define AES_REMAINDER_BIT_NUM    0x0000007FU
+#define AES_REMAINDER_BIT_NUM_M  (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S)
+#define AES_REMAINDER_BIT_NUM_V  0x0000007FU
+#define AES_REMAINDER_BIT_NUM_S  0
+
+/** AES_CONTINUE_REG register
+ *  AES continue register
+ */
+#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8)
+/** AES_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to continue GCM operation.
+ */
+#define AES_CONTINUE    (BIT(0))
+#define AES_CONTINUE_M  (AES_CONTINUE_V << AES_CONTINUE_S)
+#define AES_CONTINUE_V  0x00000001U
+#define AES_CONTINUE_S  0
+
+/** AES_INT_CLEAR_REG register
+ *  AES Interrupt clear register
+ */
+#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
+/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the AES interrupt.
+ */
+#define AES_INT_CLEAR    (BIT(0))
+#define AES_INT_CLEAR_M  (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
+#define AES_INT_CLEAR_V  0x00000001U
+#define AES_INT_CLEAR_S  0
+
+/** AES_INT_ENA_REG register
+ *  AES Interrupt enable register
+ */
+#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
+/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
+ */
+#define AES_INT_ENA    (BIT(0))
+#define AES_INT_ENA_M  (AES_INT_ENA_V << AES_INT_ENA_S)
+#define AES_INT_ENA_V  0x00000001U
+#define AES_INT_ENA_S  0
+
+/** AES_DATE_REG register
+ *  AES version control register
+ */
+#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
+/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
+ *  This bits stores the version information of AES.
+ */
+#define AES_DATE    0x3FFFFFFFU
+#define AES_DATE_M  (AES_DATE_V << AES_DATE_S)
+#define AES_DATE_V  0x3FFFFFFFU
+#define AES_DATE_S  0
+
+/** AES_DMA_EXIT_REG register
+ *  AES-DMA exit config
+ */
+#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
+/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
+ *  Set this register to leave calculation done stage. Recommend to use it after
+ *  software finishes reading DMA's output buffer.
+ */
+#define AES_DMA_EXIT    (BIT(0))
+#define AES_DMA_EXIT_M  (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
+#define AES_DMA_EXIT_V  0x00000001U
+#define AES_DMA_EXIT_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/aes_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/aes_struct.h
new file mode 100644
index 0000000000..3065c238f2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/aes_struct.h
@@ -0,0 +1,354 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Key Registers */
+/** Type of key_n register
+ *  AES key data register n
+ */
+typedef union {
+    struct {
+        /** key_0 : R/W; bitpos: [31:0]; default: 0;
+         *  This bits stores key_0 that is a part of key material.
+         */
+        uint32_t key_0:32;
+    };
+    uint32_t val;
+} aes_key_n_reg_t;
+
+
+/** Group: TEXT_IN Registers */
+/** Type of text_in_n register
+ *  Source text data register n
+ */
+typedef union {
+    struct {
+        /** text_in_0 : R/W; bitpos: [31:0]; default: 0;
+         *  This bits stores text_in_0 that is a part of source text material.
+         */
+        uint32_t text_in_0:32;
+    };
+    uint32_t val;
+} aes_text_in_n_reg_t;
+
+
+/** Group: TEXT_OUT Registers */
+/** Type of text_out_n register
+ *  Result text data register n
+ */
+typedef union {
+    struct {
+        /** text_out_0 : R/W; bitpos: [31:0]; default: 0;
+         *  This bits stores text_out_0 that is a part of result text material.
+         */
+        uint32_t text_out_0:32;
+    };
+    uint32_t val;
+} aes_text_out_n_reg_t;
+
+
+/** Group: Control / Configuration Registers */
+/** Type of mode register
+ *  Defines key length and encryption / decryption
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the key length and encryption / decryption of the AES accelerator.
+         *  0: AES-128 encryption
+         *  1: AES-192 encryption
+         *  2: AES-256 encryption
+         *  3: Reserved
+         *  4: AES-128 decryption
+         *  5: AES-192 decryption
+         *  6: AES-256 decryption
+         *  7: Reserved
+         */
+        uint32_t mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} aes_mode_reg_t;
+
+/** Type of trigger register
+ *  Operation start controlling register
+ */
+typedef union {
+    struct {
+        /** trigger : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to start AES operation.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t trigger:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_trigger_reg_t;
+
+/** Type of dma_enable register
+ *  Selects the working mode of the AES accelerator
+ */
+typedef union {
+    struct {
+        /** dma_enable : R/W; bitpos: [0]; default: 0;
+         *  Configures the working mode of the AES accelerator.
+         *  0: Typical AES
+         *  1: DMA-AES
+         */
+        uint32_t dma_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_dma_enable_reg_t;
+
+/** Type of block_mode register
+ *  Defines the block cipher mode
+ */
+typedef union {
+    struct {
+        /** block_mode : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the block cipher mode of the AES accelerator operating under the DMA-AES
+         *  working mode.
+         *  0: ECB (Electronic Code Block)
+         *  1: CBC (Cipher Block Chaining)
+         *  2: OFB (Output FeedBack)
+         *  3: CTR (Counter)
+         *  4: CFB8 (8-bit Cipher FeedBack)
+         *  5: CFB128 (128-bit Cipher FeedBack)
+         *  6: GCM
+         *  7: Reserved
+         */
+        uint32_t block_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} aes_block_mode_reg_t;
+
+/** Type of block_num register
+ *  Block number configuration register
+ */
+typedef union {
+    struct {
+        /** block_num : R/W; bitpos: [31:0]; default: 0;
+         *  Represents the Block Number of plaintext or ciphertext when the AES accelerator
+         *  operates under the DMA-AES working mode. For details, see Section . "
+         */
+        uint32_t block_num:32;
+    };
+    uint32_t val;
+} aes_block_num_reg_t;
+
+/** Type of inc_sel register
+ *  Standard incrementing function register
+ */
+typedef union {
+    struct {
+        /** inc_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures the Standard Incrementing Function for CTR block operation.
+         *  0: INC_32
+         *  1: INC_128
+         */
+        uint32_t inc_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_inc_sel_reg_t;
+
+/** Type of dma_exit register
+ *  Operation exit controlling register
+ */
+typedef union {
+    struct {
+        /** dma_exit : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to exit AES operation.
+         *  0: No effect
+         *  1: Exit
+         *  Only valid for DMA-AES operation.
+         */
+        uint32_t dma_exit:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_dma_exit_reg_t;
+
+/** Type of rx_reset register
+ *  AES-DMA reset rx-fifo register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset rx_fifo under dma_aes working mode.
+         */
+        uint32_t rx_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_rx_reset_reg_t;
+
+/** Type of tx_reset register
+ *  AES-DMA reset tx-fifo register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset tx_fifo under dma_aes working mode.
+         */
+        uint32_t tx_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_tx_reset_reg_t;
+
+
+/** Group: Configuration register */
+/** Type of pseudo register
+ *  AES PSEUDO function configure register
+ */
+typedef union {
+    struct {
+        /** pseudo_en : R/W; bitpos: [0]; default: 0;
+         *  This bit decides whether the pseudo round function is enable or not.
+         */
+        uint32_t pseudo_en:1;
+        /** pseudo_base : R/W; bitpos: [4:1]; default: 2;
+         *  Those bits decides the basic number of pseudo round number.
+         */
+        uint32_t pseudo_base:4;
+        /** pseudo_inc : R/W; bitpos: [6:5]; default: 2;
+         *  Those bits decides the increment number of pseudo round number
+         */
+        uint32_t pseudo_inc:2;
+        /** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7;
+         *  Those bits decides the update frequency of the pseudo-key.
+         */
+        uint32_t pseudo_rng_cnt:3;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} aes_pseudo_reg_t;
+
+
+/** Group: Status Register */
+/** Type of state register
+ *  Operation status register
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [1:0]; default: 0;
+         *  Represents the working status of the AES accelerator.
+         *  In Typical AES working mode:
+         *  0: IDLE
+         *  1: WORK
+         *  2: No effect
+         *  3: No effect
+         *  In DMA-AES working mode:
+         *  0: IDLE
+         *  1: WORK
+         *  2: DONE
+         *  3: No effect
+         */
+        uint32_t state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} aes_state_reg_t;
+
+
+/** Group: memory type */
+
+/** Group: Interrupt Registers */
+/** Type of int_clear register
+ *  DMA-AES interrupt clear register
+ */
+typedef union {
+    struct {
+        /** int_clear : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear AES interrupt.
+         *  0: No effect
+         *  1: Clear
+         */
+        uint32_t int_clear:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_int_clear_reg_t;
+
+/** Type of int_ena register
+ *  DMA-AES interrupt enable register
+ */
+typedef union {
+    struct {
+        /** int_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable AES interrupt.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_int_ena_reg_t;
+
+
+/** Group: Version control register */
+/** Type of date register
+ *  AES version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36774000;
+         *  This bits stores the version information of AES.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} aes_date_reg_t;
+
+
+typedef struct {
+    volatile aes_key_n_reg_t key_n[8];
+    volatile aes_text_in_n_reg_t text_in_n[4];
+    volatile aes_text_out_n_reg_t text_out_n[4];
+    volatile aes_mode_reg_t mode;
+    uint32_t reserved_044;
+    volatile aes_trigger_reg_t trigger;
+    volatile aes_state_reg_t state;
+    volatile uint32_t iv[4];
+    volatile uint32_t h[4];
+    volatile uint32_t j0[4];
+    volatile uint32_t t0[4];
+    volatile aes_dma_enable_reg_t dma_enable;
+    volatile aes_block_mode_reg_t block_mode;
+    volatile aes_block_num_reg_t block_num;
+    volatile aes_inc_sel_reg_t inc_sel;
+    uint32_t reserved_0a0[3];
+    volatile aes_int_clear_reg_t int_clear;
+    volatile aes_int_ena_reg_t int_ena;
+    volatile aes_date_reg_t date;
+    volatile aes_dma_exit_reg_t dma_exit;
+    uint32_t reserved_0bc;
+    volatile aes_rx_reset_reg_t rx_reset;
+    volatile aes_tx_reset_reg_t tx_reset;
+    uint32_t reserved_0c8[2];
+    volatile aes_pseudo_reg_t pseudo;
+} aes_dev_t;
+
+extern aes_dev_t AES;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(aes_dev_t) == 0xd4, "Invalid size of aes_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_eco5_struct.h
new file mode 100644
index 0000000000..43769ae0ee
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_eco5_struct.h
@@ -0,0 +1,3866 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt Registers */
+/** Type of in_int_raw_ch0 register
+ *  Raw interrupt status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT
+         */
+        uint32_t in_done_ch0_int_raw:1;
+        /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT
+         */
+        uint32_t in_suc_eof_ch0_int_raw:1;
+        /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT
+         */
+        uint32_t in_err_eof_ch0_int_raw:1;
+        /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT
+         */
+        uint32_t in_dscr_err_ch0_int_raw:1;
+        /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+         */
+        uint32_t in_dscr_empty_ch0_int_raw:1;
+        /** infifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT
+         */
+        uint32_t infifo_ovf_ch0_int_raw:1;
+        /** infifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT
+         */
+        uint32_t infifo_udf_ch0_int_raw:1;
+        /** in_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch0_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_raw_ch0_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of in_int_st_ch0 register
+ *  Masked interrupt status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT
+         */
+        uint32_t in_done_ch0_int_st:1;
+        /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT
+         */
+        uint32_t in_suc_eof_ch0_int_st:1;
+        /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT
+         */
+        uint32_t in_err_eof_ch0_int_st:1;
+        /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT
+         */
+        uint32_t in_dscr_err_ch0_int_st:1;
+        /** in_dscr_empty_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+         */
+        uint32_t in_dscr_empty_ch0_int_st:1;
+        /** infifo_ovf_ch0_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT
+         */
+        uint32_t infifo_ovf_ch0_int_st:1;
+        /** infifo_udf_ch0_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT
+         */
+        uint32_t infifo_udf_ch0_int_st:1;
+        /** in_ahbinf_resp_err_ch0_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch0_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_st_ch0_reg_t;
+
+/** Type of in_int_ena_ch0 register
+ *  Interrupt enable bits of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DONE_CH0_INT
+         */
+        uint32_t in_done_ch0_int_ena:1;
+        /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT
+         */
+        uint32_t in_suc_eof_ch0_int_ena:1;
+        /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT
+         */
+        uint32_t in_err_eof_ch0_int_ena:1;
+        /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT
+         */
+        uint32_t in_dscr_err_ch0_int_ena:1;
+        /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+         */
+        uint32_t in_dscr_empty_ch0_int_ena:1;
+        /** infifo_ovf_ch0_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT
+         */
+        uint32_t infifo_ovf_ch0_int_ena:1;
+        /** infifo_udf_ch0_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT
+         */
+        uint32_t infifo_udf_ch0_int_ena:1;
+        /** in_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch0_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_ena_ch0_reg_t;
+
+/** Type of in_int_clr_ch0 register
+ *  Interrupt clear bits of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DONE_CH0_INT
+         */
+        uint32_t in_done_ch0_int_clr:1;
+        /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT
+         */
+        uint32_t in_suc_eof_ch0_int_clr:1;
+        /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT
+         */
+        uint32_t in_err_eof_ch0_int_clr:1;
+        /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT
+         */
+        uint32_t in_dscr_err_ch0_int_clr:1;
+        /** in_dscr_empty_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+         */
+        uint32_t in_dscr_empty_ch0_int_clr:1;
+        /** infifo_ovf_ch0_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT
+         */
+        uint32_t infifo_ovf_ch0_int_clr:1;
+        /** infifo_udf_ch0_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT
+         */
+        uint32_t infifo_udf_ch0_int_clr:1;
+        /** in_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch0_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_clr_ch0_reg_t;
+
+/** Type of in_int_raw_ch1 register
+ *  Raw interrupt status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT
+         */
+        uint32_t in_done_ch1_int_raw:1;
+        /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT
+         */
+        uint32_t in_suc_eof_ch1_int_raw:1;
+        /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT
+         */
+        uint32_t in_err_eof_ch1_int_raw:1;
+        /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT
+         */
+        uint32_t in_dscr_err_ch1_int_raw:1;
+        /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+         */
+        uint32_t in_dscr_empty_ch1_int_raw:1;
+        /** infifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT
+         */
+        uint32_t infifo_ovf_ch1_int_raw:1;
+        /** infifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT
+         */
+        uint32_t infifo_udf_ch1_int_raw:1;
+        /** in_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch1_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_raw_ch1_reg_t;
+
+/** Type of in_int_st_ch1 register
+ *  Masked interrupt status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT
+         */
+        uint32_t in_done_ch1_int_st:1;
+        /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT
+         */
+        uint32_t in_suc_eof_ch1_int_st:1;
+        /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT
+         */
+        uint32_t in_err_eof_ch1_int_st:1;
+        /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT
+         */
+        uint32_t in_dscr_err_ch1_int_st:1;
+        /** in_dscr_empty_ch1_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+         */
+        uint32_t in_dscr_empty_ch1_int_st:1;
+        /** infifo_ovf_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT
+         */
+        uint32_t infifo_ovf_ch1_int_st:1;
+        /** infifo_udf_ch1_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT
+         */
+        uint32_t infifo_udf_ch1_int_st:1;
+        /** in_ahbinf_resp_err_ch1_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch1_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_st_ch1_reg_t;
+
+/** Type of in_int_ena_ch1 register
+ *  Interrupt enable bits of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DONE_CH1_INT
+         */
+        uint32_t in_done_ch1_int_ena:1;
+        /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT
+         */
+        uint32_t in_suc_eof_ch1_int_ena:1;
+        /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT
+         */
+        uint32_t in_err_eof_ch1_int_ena:1;
+        /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT
+         */
+        uint32_t in_dscr_err_ch1_int_ena:1;
+        /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+         */
+        uint32_t in_dscr_empty_ch1_int_ena:1;
+        /** infifo_ovf_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT
+         */
+        uint32_t infifo_ovf_ch1_int_ena:1;
+        /** infifo_udf_ch1_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT
+         */
+        uint32_t infifo_udf_ch1_int_ena:1;
+        /** in_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch1_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_ena_ch1_reg_t;
+
+/** Type of in_int_clr_ch1 register
+ *  Interrupt clear bits of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DONE_CH1_INT
+         */
+        uint32_t in_done_ch1_int_clr:1;
+        /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT
+         */
+        uint32_t in_suc_eof_ch1_int_clr:1;
+        /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT
+         */
+        uint32_t in_err_eof_ch1_int_clr:1;
+        /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT
+         */
+        uint32_t in_dscr_err_ch1_int_clr:1;
+        /** in_dscr_empty_ch1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+         */
+        uint32_t in_dscr_empty_ch1_int_clr:1;
+        /** infifo_ovf_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT
+         */
+        uint32_t infifo_ovf_ch1_int_clr:1;
+        /** infifo_udf_ch1_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT
+         */
+        uint32_t infifo_udf_ch1_int_clr:1;
+        /** in_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch1_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_clr_ch1_reg_t;
+
+/** Type of in_int_raw_ch2 register
+ *  Raw interrupt status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT
+         */
+        uint32_t in_done_ch2_int_raw:1;
+        /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT
+         */
+        uint32_t in_suc_eof_ch2_int_raw:1;
+        /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT
+         */
+        uint32_t in_err_eof_ch2_int_raw:1;
+        /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT
+         */
+        uint32_t in_dscr_err_ch2_int_raw:1;
+        /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+         */
+        uint32_t in_dscr_empty_ch2_int_raw:1;
+        /** infifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT
+         */
+        uint32_t infifo_ovf_ch2_int_raw:1;
+        /** infifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT
+         */
+        uint32_t infifo_udf_ch2_int_raw:1;
+        /** in_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch2_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_raw_ch2_reg_t;
+
+/** Type of in_int_st_ch2 register
+ *  Masked interrupt status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT
+         */
+        uint32_t in_done_ch2_int_st:1;
+        /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT
+         */
+        uint32_t in_suc_eof_ch2_int_st:1;
+        /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT
+         */
+        uint32_t in_err_eof_ch2_int_st:1;
+        /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT
+         */
+        uint32_t in_dscr_err_ch2_int_st:1;
+        /** in_dscr_empty_ch2_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+         */
+        uint32_t in_dscr_empty_ch2_int_st:1;
+        /** infifo_ovf_ch2_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT
+         */
+        uint32_t infifo_ovf_ch2_int_st:1;
+        /** infifo_udf_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT
+         */
+        uint32_t infifo_udf_ch2_int_st:1;
+        /** in_ahbinf_resp_err_ch2_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch2_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_st_ch2_reg_t;
+
+/** Type of in_int_ena_ch2 register
+ *  Interrupt enable bits of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DONE_CH2_INT
+         */
+        uint32_t in_done_ch2_int_ena:1;
+        /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT
+         */
+        uint32_t in_suc_eof_ch2_int_ena:1;
+        /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT
+         */
+        uint32_t in_err_eof_ch2_int_ena:1;
+        /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT
+         */
+        uint32_t in_dscr_err_ch2_int_ena:1;
+        /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+         */
+        uint32_t in_dscr_empty_ch2_int_ena:1;
+        /** infifo_ovf_ch2_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT
+         */
+        uint32_t infifo_ovf_ch2_int_ena:1;
+        /** infifo_udf_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT
+         */
+        uint32_t infifo_udf_ch2_int_ena:1;
+        /** in_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch2_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_ena_ch2_reg_t;
+
+/** Type of in_int_clr_ch2 register
+ *  Interrupt clear bits of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DONE_CH2_INT
+         */
+        uint32_t in_done_ch2_int_clr:1;
+        /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT
+         */
+        uint32_t in_suc_eof_ch2_int_clr:1;
+        /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT
+         */
+        uint32_t in_err_eof_ch2_int_clr:1;
+        /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT
+         */
+        uint32_t in_dscr_err_ch2_int_clr:1;
+        /** in_dscr_empty_ch2_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+         */
+        uint32_t in_dscr_empty_ch2_int_clr:1;
+        /** infifo_ovf_ch2_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT
+         */
+        uint32_t infifo_ovf_ch2_int_clr:1;
+        /** infifo_udf_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT
+         */
+        uint32_t infifo_udf_ch2_int_clr:1;
+        /** in_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT
+         */
+        uint32_t in_ahbinf_resp_err_ch2_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_clr_ch2_reg_t;
+
+/** Type of out_int_raw_ch0 register
+ *  //Raw interrupt status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT
+         */
+        uint32_t out_done_ch0_int_raw:1;
+        /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT
+         */
+        uint32_t out_eof_ch0_int_raw:1;
+        /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT
+         */
+        uint32_t out_dscr_err_ch0_int_raw:1;
+        /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+         */
+        uint32_t out_total_eof_ch0_int_raw:1;
+        /** outfifo_ovf_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT
+         */
+        uint32_t outfifo_ovf_ch0_int_raw:1;
+        /** outfifo_udf_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT
+         */
+        uint32_t outfifo_udf_ch0_int_raw:1;
+        /** out_ahbinf_resp_err_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch0_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_raw_ch0_reg_t;
+
+/** Type of out_int_st_ch0 register
+ *  Masked interrupt status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT
+         */
+        uint32_t out_done_ch0_int_st:1;
+        /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT
+         */
+        uint32_t out_eof_ch0_int_st:1;
+        /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT
+         */
+        uint32_t out_dscr_err_ch0_int_st:1;
+        /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+         */
+        uint32_t out_total_eof_ch0_int_st:1;
+        /** outfifo_ovf_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT
+         */
+        uint32_t outfifo_ovf_ch0_int_st:1;
+        /** outfifo_udf_ch0_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT
+         */
+        uint32_t outfifo_udf_ch0_int_st:1;
+        /** out_ahbinf_resp_err_ch0_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch0_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_st_ch0_reg_t;
+
+/** Type of out_int_ena_ch0 register
+ *  Interrupt enable bits of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT
+         */
+        uint32_t out_done_ch0_int_ena:1;
+        /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT
+         */
+        uint32_t out_eof_ch0_int_ena:1;
+        /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT
+         */
+        uint32_t out_dscr_err_ch0_int_ena:1;
+        /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+         */
+        uint32_t out_total_eof_ch0_int_ena:1;
+        /** outfifo_ovf_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT
+         */
+        uint32_t outfifo_ovf_ch0_int_ena:1;
+        /** outfifo_udf_ch0_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT
+         */
+        uint32_t outfifo_udf_ch0_int_ena:1;
+        /** out_ahbinf_resp_err_ch0_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch0_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_ena_ch0_reg_t;
+
+/** Type of out_int_clr_ch0 register
+ *  Interrupt clear bits of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT
+         */
+        uint32_t out_done_ch0_int_clr:1;
+        /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT
+         */
+        uint32_t out_eof_ch0_int_clr:1;
+        /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT
+         */
+        uint32_t out_dscr_err_ch0_int_clr:1;
+        /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+         */
+        uint32_t out_total_eof_ch0_int_clr:1;
+        /** outfifo_ovf_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT
+         */
+        uint32_t outfifo_ovf_ch0_int_clr:1;
+        /** outfifo_udf_ch0_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT
+         */
+        uint32_t outfifo_udf_ch0_int_clr:1;
+        /** out_ahbinf_resp_err_ch0_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch0_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_clr_ch0_reg_t;
+
+/** Type of out_int_raw_ch1 register
+ *  //Raw interrupt status of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT
+         */
+        uint32_t out_done_ch1_int_raw:1;
+        /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT
+         */
+        uint32_t out_eof_ch1_int_raw:1;
+        /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT
+         */
+        uint32_t out_dscr_err_ch1_int_raw:1;
+        /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+         */
+        uint32_t out_total_eof_ch1_int_raw:1;
+        /** outfifo_ovf_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT
+         */
+        uint32_t outfifo_ovf_ch1_int_raw:1;
+        /** outfifo_udf_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT
+         */
+        uint32_t outfifo_udf_ch1_int_raw:1;
+        /** out_ahbinf_resp_err_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch1_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_raw_ch1_reg_t;
+
+/** Type of out_int_st_ch1 register
+ *  Masked interrupt status of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT
+         */
+        uint32_t out_done_ch1_int_st:1;
+        /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT
+         */
+        uint32_t out_eof_ch1_int_st:1;
+        /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT
+         */
+        uint32_t out_dscr_err_ch1_int_st:1;
+        /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+         */
+        uint32_t out_total_eof_ch1_int_st:1;
+        /** outfifo_ovf_ch1_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT
+         */
+        uint32_t outfifo_ovf_ch1_int_st:1;
+        /** outfifo_udf_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT
+         */
+        uint32_t outfifo_udf_ch1_int_st:1;
+        /** out_ahbinf_resp_err_ch1_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch1_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_st_ch1_reg_t;
+
+/** Type of out_int_ena_ch1 register
+ *  Interrupt enable bits of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT
+         */
+        uint32_t out_done_ch1_int_ena:1;
+        /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT
+         */
+        uint32_t out_eof_ch1_int_ena:1;
+        /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT
+         */
+        uint32_t out_dscr_err_ch1_int_ena:1;
+        /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+         */
+        uint32_t out_total_eof_ch1_int_ena:1;
+        /** outfifo_ovf_ch1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT
+         */
+        uint32_t outfifo_ovf_ch1_int_ena:1;
+        /** outfifo_udf_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT
+         */
+        uint32_t outfifo_udf_ch1_int_ena:1;
+        /** out_ahbinf_resp_err_ch1_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch1_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_ena_ch1_reg_t;
+
+/** Type of out_int_clr_ch1 register
+ *  Interrupt clear bits of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT
+         */
+        uint32_t out_done_ch1_int_clr:1;
+        /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT
+         */
+        uint32_t out_eof_ch1_int_clr:1;
+        /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT
+         */
+        uint32_t out_dscr_err_ch1_int_clr:1;
+        /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+         */
+        uint32_t out_total_eof_ch1_int_clr:1;
+        /** outfifo_ovf_ch1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT
+         */
+        uint32_t outfifo_ovf_ch1_int_clr:1;
+        /** outfifo_udf_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT
+         */
+        uint32_t outfifo_udf_ch1_int_clr:1;
+        /** out_ahbinf_resp_err_ch1_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch1_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_clr_ch1_reg_t;
+
+/** Type of out_int_raw_ch2 register
+ *  //Raw interrupt status of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT
+         */
+        uint32_t out_done_ch2_int_raw:1;
+        /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT
+         */
+        uint32_t out_eof_ch2_int_raw:1;
+        /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT
+         */
+        uint32_t out_dscr_err_ch2_int_raw:1;
+        /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+         */
+        uint32_t out_total_eof_ch2_int_raw:1;
+        /** outfifo_ovf_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT
+         */
+        uint32_t outfifo_ovf_ch2_int_raw:1;
+        /** outfifo_udf_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT
+         */
+        uint32_t outfifo_udf_ch2_int_raw:1;
+        /** out_ahbinf_resp_err_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch2_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_raw_ch2_reg_t;
+
+/** Type of out_int_st_ch2 register
+ *  Masked interrupt status of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT
+         */
+        uint32_t out_done_ch2_int_st:1;
+        /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT
+         */
+        uint32_t out_eof_ch2_int_st:1;
+        /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT
+         */
+        uint32_t out_dscr_err_ch2_int_st:1;
+        /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+         */
+        uint32_t out_total_eof_ch2_int_st:1;
+        /** outfifo_ovf_ch2_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT
+         */
+        uint32_t outfifo_ovf_ch2_int_st:1;
+        /** outfifo_udf_ch2_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT
+         */
+        uint32_t outfifo_udf_ch2_int_st:1;
+        /** out_ahbinf_resp_err_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch2_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_st_ch2_reg_t;
+
+/** Type of out_int_ena_ch2 register
+ *  Interrupt enable bits of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT
+         */
+        uint32_t out_done_ch2_int_ena:1;
+        /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT
+         */
+        uint32_t out_eof_ch2_int_ena:1;
+        /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT
+         */
+        uint32_t out_dscr_err_ch2_int_ena:1;
+        /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+         */
+        uint32_t out_total_eof_ch2_int_ena:1;
+        /** outfifo_ovf_ch2_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT
+         */
+        uint32_t outfifo_ovf_ch2_int_ena:1;
+        /** outfifo_udf_ch2_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT
+         */
+        uint32_t outfifo_udf_ch2_int_ena:1;
+        /** out_ahbinf_resp_err_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch2_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_ena_ch2_reg_t;
+
+/** Type of out_int_clr_ch2 register
+ *  Interrupt clear bits of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT
+         */
+        uint32_t out_done_ch2_int_clr:1;
+        /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT
+         */
+        uint32_t out_eof_ch2_int_clr:1;
+        /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT
+         */
+        uint32_t out_dscr_err_ch2_int_clr:1;
+        /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+         */
+        uint32_t out_total_eof_ch2_int_clr:1;
+        /** outfifo_ovf_ch2_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT
+         */
+        uint32_t outfifo_ovf_ch2_int_clr:1;
+        /** outfifo_udf_ch2_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT
+         */
+        uint32_t outfifo_udf_ch2_int_clr:1;
+        /** out_ahbinf_resp_err_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT
+         */
+        uint32_t out_ahbinf_resp_err_ch2_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_clr_ch2_reg_t;
+
+/** Type of ahb_test register
+ *  only for test
+ */
+typedef union {
+    struct {
+        /** ahb_testmode : R/W; bitpos: [2:0]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testmode:3;
+        uint32_t reserved_3:1;
+        /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testaddr:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_ahb_test_reg_t;
+
+/** Type of misc_conf register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset the internal AHB FSM
+         */
+        uint32_t ahbm_rst_inter:1;
+        uint32_t reserved_1:1;
+        /** arb_pri_dis : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to disable the fixed-priority channel arbitration.
+         *  0: Enable
+         *  1: Disable
+         */
+        uint32_t arb_pri_dis:1;
+        /** clk_en : R/W; bitpos: [3]; default: 0;
+         *  Configures clock gating.
+         *  0: Support clock only when the application writes registers.
+         *  1: Always force the clock on for registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_misc_conf_reg_t;
+
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 2425376;
+         *  Version control register
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} ahb_dma_date_reg_t;
+
+/** Type of in_conf0_ch0 register
+ *  Configuration register 0 of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_rst_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+         */
+        uint32_t in_rst_ch0:1;
+        /** in_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_ch0:1;
+        /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable INCR burst transfer for RX channel 0 to read
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t indscr_burst_en_ch0:1;
+        /** in_data_burst_en_ch0 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 0 receiving data
+         *  when accessing internal SRAM.
+         */
+        uint32_t in_data_burst_en_ch0:1;
+        /** mem_trans_en_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable memory-to-memory data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t mem_trans_en_ch0:1;
+        /** in_etm_en_ch0 : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable ETM control for RX channel0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_etm_en_ch0:1;
+        /** in_data_burst_mode_sel_ch0 : R/W; bitpos: [7:6]; default: 1;
+         *  Configures max burst size for Rx channel0.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t in_data_burst_mode_sel_ch0:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_conf0_ch0_reg_t;
+
+/** Type of in_conf1_ch0 register
+ *  Configuration register 1 of RX channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** in_check_owner_ch0 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for RX channel 0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_check_owner_ch0:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_conf1_ch0_reg_t;
+
+/** Type of infifo_status_ch0 register
+ *  Receive FIFO status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_full_ch0 : RO; bitpos: [0]; default: 1;
+         *  Represents whether L1 RX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t infifo_full_ch0:1;
+        /** infifo_empty_ch0 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 RX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t infifo_empty_ch0:1;
+        uint32_t reserved_2:6;
+        /** infifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 RX FIFO for RX channel 0
+         */
+        uint32_t infifo_cnt_ch0:7;
+        uint32_t reserved_15:8;
+        /** in_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_ch0:1;
+        /** in_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_ch0:1;
+        /** in_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_ch0:1;
+        /** in_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_ch0:1;
+        /** in_buf_hungry_ch0 : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_ch0:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ahb_dma_infifo_status_ch0_reg_t;
+
+/** Type of in_pop_ch0 register
+ *  Receive FIFO status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch0 : RO; bitpos: [11:0]; default: 2048;
+         *  Represents the data popped from AHB_DMA FIFO.
+         */
+        uint32_t infifo_rdata_ch0:12;
+        /** infifo_pop_ch0 : WT; bitpos: [12]; default: 0;
+         *  Configures whether to pop data from AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Pop
+         */
+        uint32_t infifo_pop_ch0:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_pop_ch0_reg_t;
+
+/** Type of in_link_ch0 register
+ *  Receive FIFO status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_ch0 : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to return to current receive descriptor's address when there are
+         *  some errors in current receiving data.
+         *  0: Not return
+         *  1: Return
+         *  .
+         */
+        uint32_t inlink_auto_ret_ch0:1;
+        /** inlink_stop_ch0 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to stop AHB_DMA's RX channel 0 from receiving data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t inlink_stop_ch0:1;
+        /** inlink_start_ch0 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to enable AHB_DMA's RX channel 0 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t inlink_start_ch0:1;
+        /** inlink_restart_ch0 : WT; bitpos: [3]; default: 0;
+         *  Configures whether to restart RX channel 0 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t inlink_restart_ch0:1;
+        /** inlink_park_ch0 : RO; bitpos: [4]; default: 1;
+         *  Represents the status of the receive descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t inlink_park_ch0:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} ahb_dma_in_link_ch0_reg_t;
+
+/** Type of in_state_ch0 register
+ *  Receive status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
+         *  reserved
+         */
+        uint32_t inlink_dscr_addr_ch0:18;
+        /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_ch0:2;
+        /** in_state_ch0 : RO; bitpos: [22:20]; default: 0;
+         *  Represents the address of the lower 18 bits of the next receive descriptor to be
+         *  processed.
+         */
+        uint32_t in_state_ch0:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_in_state_ch0_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch0 register
+ *  Receive descriptor address when EOF occurs on RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_suc_eof_des_addr_ch0_reg_t;
+
+/** Type of in_err_eof_des_addr_ch0 register
+ *  Receive descriptor address when errors occur of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when there are some errors in the
+         *  currently received data.
+         */
+        uint32_t in_err_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_err_eof_des_addr_ch0_reg_t;
+
+/** Type of in_dscr_ch0 register
+ *  Current receive descriptor address of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next receive descriptor x+1 pointed by the current
+         *  receive descriptor that has already been fetched.
+         */
+        uint32_t inlink_dscr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_ch0_reg_t;
+
+/** Type of in_dscr_bf0_ch0 register
+ *  The last receive descriptor address of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current receive descriptor x that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf0_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf0_ch0_reg_t;
+
+/** Type of in_dscr_bf1_ch0 register
+ *  The second-to-last receive descriptor address of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous receive descriptor x-1 that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf1_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf1_ch0_reg_t;
+
+/** Type of in_peri_ch0 register
+ *  Priority register of RX channel 0
+ */
+typedef union {
+    struct {
+        /** rx_pri_ch0 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of RX channel 0.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t rx_pri_ch0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_ch0_reg_t;
+
+/** Type of in_peri_sel_ch0 register
+ *  Peripheral selection register of RX channel 0
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_ch0 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to RX channel 0.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_in_sel_ch0:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_sel_ch0_reg_t;
+
+/** Type of out_conf0_ch0 register
+ *  Configuration register 0 of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.
+         *  0: Release reset
+         *  1: Reset
+         */
+        uint32_t out_rst_ch0:1;
+        /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch0:1;
+        /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable automatic outlink write-back when all the data in TX
+         *  FIFO has been transmitted.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_auto_wrback_ch0:1;
+        /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
+         *  Configures when to generate EOF flag.
+         *  0: EOF flag for TX channel 0 is generated when data to be transmitted has been
+         *  pushed into FIFO in AHB_DMA.
+         *  1: EOF flag for TX channel 0 is generated when data to be transmitted has been
+         *  popped from FIFO in AHB_DMA.
+         */
+        uint32_t out_eof_mode_ch0:1;
+        /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable INCR burst transfer for TX channel 0 reading
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outdscr_burst_en_ch0:1;
+        /** out_data_burst_en_ch0 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable INCR4 burst transfer for Tx channel 0 transmitting data
+         *  when accessing internal SRAM.
+         */
+        uint32_t out_data_burst_en_ch0:1;
+        /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to enable ETM control for TX channel 0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_etm_en_ch0:1;
+        uint32_t reserved_7:1;
+        /** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 1;
+         *  Configures max burst size for TX channel0.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t out_data_burst_mode_sel_ch0:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_ch0_reg_t;
+
+/** Type of out_conf1_ch0 register
+ *  Configuration register 1 of TX channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** out_check_owner_ch0 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for TX channel 0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_check_owner_ch0:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_out_conf1_ch0_reg_t;
+
+/** Type of outfifo_status_ch0 register
+ *  Receive FIFO status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_full_ch0 : RO; bitpos: [0]; default: 0;
+         *  Represents whether L1 TX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t outfifo_full_ch0:1;
+        /** outfifo_empty_ch0 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 TX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t outfifo_empty_ch0:1;
+        uint32_t reserved_2:6;
+        /** outfifo_cnt_ch0 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 TX FIFO for TX channel 0
+         */
+        uint32_t outfifo_cnt_ch0:7;
+        uint32_t reserved_15:8;
+        /** out_remain_under_1b_ch0 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_ch0:1;
+        /** out_remain_under_2b_ch0 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_ch0:1;
+        /** out_remain_under_3b_ch0 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_ch0:1;
+        /** out_remain_under_4b_ch0 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_ch0:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} ahb_dma_outfifo_status_ch0_reg_t;
+
+/** Type of out_push_ch0 register
+ *  Push control register of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch0 : R/W; bitpos: [8:0]; default: 0;
+         *  Configures whether to push data into AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Push
+         */
+        uint32_t outfifo_wdata_ch0:9;
+        /** outfifo_push_ch0 : WT; bitpos: [9]; default: 0;
+         *  Configures the data that need to be pushed into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_push_ch0:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_push_ch0_reg_t;
+
+/** Type of out_link_ch0 register
+ *  Push control register of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_stop_ch0 : WT; bitpos: [0]; default: 0;
+         *  Configures whether to stop AHB_DMA's TX channel 0 from transmitting data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t outlink_stop_ch0:1;
+        /** outlink_start_ch0 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to enable AHB_DMA's TX channel 0 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outlink_start_ch0:1;
+        /** outlink_restart_ch0 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to restart TX channel 0 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t outlink_restart_ch0:1;
+        /** outlink_park_ch0 : RO; bitpos: [3]; default: 1;
+         *  Represents the status of the transmit descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t outlink_park_ch0:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_link_ch0_reg_t;
+
+/** Type of out_state_ch0 register
+ *  Transmit status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
+         *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+         *  processed.
+         */
+        uint32_t outlink_dscr_addr_ch0:18;
+        /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_ch0:2;
+        /** out_state_ch0 : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_ch0:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_out_state_ch0_reg_t;
+
+/** Type of out_eof_des_addr_ch0 register
+ *  Transmit descriptor address when EOF occurs on TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_des_addr_ch0_reg_t;
+
+/** Type of out_eof_bfr_des_addr_ch0 register
+ *  The last transmit descriptor address when EOF occurs on TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor before the last transmit
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_bfr_des_addr_ch0_reg_t;
+
+/** Type of out_dscr_ch0 register
+ *  Current transmit descriptor address of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next transmit descriptor y+1 pointed by the current
+         *  transmit descriptor that has already been fetched.
+         */
+        uint32_t outlink_dscr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_ch0_reg_t;
+
+/** Type of out_dscr_bf0_ch0 register
+ *  The last transmit descriptor address of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current transmit descriptor y that has already been
+         *  fetched.
+         */
+        uint32_t outlink_dscr_bf0_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf0_ch0_reg_t;
+
+/** Type of out_dscr_bf1_ch0 register
+ *  The second-to-last transmit descriptor address of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous transmit descriptor y-1 that has already
+         *  been fetched.
+         */
+        uint32_t outlink_dscr_bf1_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf1_ch0_reg_t;
+
+/** Type of out_peri_ch0 register
+ *  Priority register of TX channel 0
+ */
+typedef union {
+    struct {
+        /** tx_pri_ch0 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of TX channel 0.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t tx_pri_ch0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_ch0_reg_t;
+
+/** Type of out_peri_sel_ch0 register
+ *  Peripheral selection register of TX channel 0
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_ch0 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to TX channel 0.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_out_sel_ch0:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_sel_ch0_reg_t;
+
+/** Type of in_conf0_ch1 register
+ *  Configuration register 0 of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_rst_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer.
+         */
+        uint32_t in_rst_ch1:1;
+        /** in_loop_test_ch1 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_ch1:1;
+        /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable INCR burst transfer for RX channel 1 to read
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t indscr_burst_en_ch1:1;
+        /** in_data_burst_en_ch1 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 1 receiving data
+         *  when accessing internal SRAM.
+         */
+        uint32_t in_data_burst_en_ch1:1;
+        /** mem_trans_en_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable memory-to-memory data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t mem_trans_en_ch1:1;
+        /** in_etm_en_ch1 : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable ETM control for RX channel1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_etm_en_ch1:1;
+        /** in_data_burst_mode_sel_ch1 : R/W; bitpos: [7:6]; default: 1;
+         *  Configures max burst size for Rx channel1.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t in_data_burst_mode_sel_ch1:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_conf0_ch1_reg_t;
+
+/** Type of in_conf1_ch1 register
+ *  Configuration register 1 of RX channel 1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** in_check_owner_ch1 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for RX channel 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_check_owner_ch1:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_conf1_ch1_reg_t;
+
+/** Type of infifo_status_ch1 register
+ *  Receive FIFO status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** infifo_full_ch1 : RO; bitpos: [0]; default: 1;
+         *  Represents whether L1 RX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t infifo_full_ch1:1;
+        /** infifo_empty_ch1 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 RX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t infifo_empty_ch1:1;
+        uint32_t reserved_2:6;
+        /** infifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 RX FIFO for RX channel 1
+         */
+        uint32_t infifo_cnt_ch1:7;
+        uint32_t reserved_15:8;
+        /** in_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_ch1:1;
+        /** in_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_ch1:1;
+        /** in_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_ch1:1;
+        /** in_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_ch1:1;
+        /** in_buf_hungry_ch1 : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_ch1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ahb_dma_infifo_status_ch1_reg_t;
+
+/** Type of in_pop_ch1 register
+ *  Receive FIFO status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch1 : RO; bitpos: [11:0]; default: 2048;
+         *  Represents the data popped from AHB_DMA FIFO.
+         */
+        uint32_t infifo_rdata_ch1:12;
+        /** infifo_pop_ch1 : WT; bitpos: [12]; default: 0;
+         *  Configures whether to pop data from AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Pop
+         */
+        uint32_t infifo_pop_ch1:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_pop_ch1_reg_t;
+
+/** Type of in_link_ch1 register
+ *  Receive FIFO status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_ch1 : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to return to current receive descriptor's address when there are
+         *  some errors in current receiving data.
+         *  0: Not return
+         *  1: Return
+         *  .
+         */
+        uint32_t inlink_auto_ret_ch1:1;
+        /** inlink_stop_ch1 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to stop AHB_DMA's RX channel 1 from receiving data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t inlink_stop_ch1:1;
+        /** inlink_start_ch1 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to enable AHB_DMA's RX channel 1 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t inlink_start_ch1:1;
+        /** inlink_restart_ch1 : WT; bitpos: [3]; default: 0;
+         *  Configures whether to restart RX channel 1 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t inlink_restart_ch1:1;
+        /** inlink_park_ch1 : RO; bitpos: [4]; default: 1;
+         *  Represents the status of the receive descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t inlink_park_ch1:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} ahb_dma_in_link_ch1_reg_t;
+
+/** Type of in_state_ch1 register
+ *  Receive status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
+         *  reserved
+         */
+        uint32_t inlink_dscr_addr_ch1:18;
+        /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_ch1:2;
+        /** in_state_ch1 : RO; bitpos: [22:20]; default: 0;
+         *  Represents the address of the lower 18 bits of the next receive descriptor to be
+         *  processed.
+         */
+        uint32_t in_state_ch1:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_in_state_ch1_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch1 register
+ *  Receive descriptor address when EOF occurs on RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_suc_eof_des_addr_ch1_reg_t;
+
+/** Type of in_err_eof_des_addr_ch1 register
+ *  Receive descriptor address when errors occur of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when there are some errors in the
+         *  currently received data.
+         */
+        uint32_t in_err_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_err_eof_des_addr_ch1_reg_t;
+
+/** Type of in_dscr_ch1 register
+ *  Current receive descriptor address of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next receive descriptor x+1 pointed by the current
+         *  receive descriptor that has already been fetched.
+         */
+        uint32_t inlink_dscr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_ch1_reg_t;
+
+/** Type of in_dscr_bf0_ch1 register
+ *  The last receive descriptor address of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current receive descriptor x that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf0_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf0_ch1_reg_t;
+
+/** Type of in_dscr_bf1_ch1 register
+ *  The second-to-last receive descriptor address of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous receive descriptor x-1 that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf1_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf1_ch1_reg_t;
+
+/** Type of in_peri_ch1 register
+ *  Priority register of RX channel 1
+ */
+typedef union {
+    struct {
+        /** rx_pri_ch1 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of RX channel 1.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t rx_pri_ch1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_ch1_reg_t;
+
+/** Type of in_peri_sel_ch1 register
+ *  Peripheral selection register of RX channel 1
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_ch1 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to RX channel 1.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_in_sel_ch1:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_sel_ch1_reg_t;
+
+/** Type of out_conf0_ch1 register
+ *  Configuration register 0 of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_rst_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer.
+         *  0: Release reset
+         *  1: Reset
+         */
+        uint32_t out_rst_ch1:1;
+        /** out_loop_test_ch1 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch1:1;
+        /** out_auto_wrback_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable automatic outlink write-back when all the data in TX
+         *  FIFO has been transmitted.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_auto_wrback_ch1:1;
+        /** out_eof_mode_ch1 : R/W; bitpos: [3]; default: 1;
+         *  Configures when to generate EOF flag.
+         *  0: EOF flag for TX channel 1 is generated when data to be transmitted has been
+         *  pushed into FIFO in AHB_DMA.
+         *  1: EOF flag for TX channel 1 is generated when data to be transmitted has been
+         *  popped from FIFO in AHB_DMA.
+         */
+        uint32_t out_eof_mode_ch1:1;
+        /** outdscr_burst_en_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable INCR burst transfer for TX channel 1 reading
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outdscr_burst_en_ch1:1;
+        /** out_data_burst_en_ch1 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data
+         *  when accessing internal SRAM.
+         */
+        uint32_t out_data_burst_en_ch1:1;
+        /** out_etm_en_ch1 : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to enable ETM control for TX channel 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_etm_en_ch1:1;
+        uint32_t reserved_7:1;
+        /** out_data_burst_mode_sel_ch1 : R/W; bitpos: [9:8]; default: 1;
+         *  Configures max burst size for TX channel1.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t out_data_burst_mode_sel_ch1:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_ch1_reg_t;
+
+/** Type of out_conf1_ch1 register
+ *  Configuration register 1 of TX channel 1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** out_check_owner_ch1 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for TX channel 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_check_owner_ch1:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_out_conf1_ch1_reg_t;
+
+/** Type of outfifo_status_ch1 register
+ *  Receive FIFO status of RX channel 1
+ */
+typedef union {
+    struct {
+        /** outfifo_full_ch1 : RO; bitpos: [0]; default: 0;
+         *  Represents whether L1 TX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t outfifo_full_ch1:1;
+        /** outfifo_empty_ch1 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 TX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t outfifo_empty_ch1:1;
+        uint32_t reserved_2:6;
+        /** outfifo_cnt_ch1 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 TX FIFO for TX channel 1
+         */
+        uint32_t outfifo_cnt_ch1:7;
+        uint32_t reserved_15:8;
+        /** out_remain_under_1b_ch1 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_ch1:1;
+        /** out_remain_under_2b_ch1 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_ch1:1;
+        /** out_remain_under_3b_ch1 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_ch1:1;
+        /** out_remain_under_4b_ch1 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_ch1:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} ahb_dma_outfifo_status_ch1_reg_t;
+
+/** Type of out_push_ch1 register
+ *  Push control register of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch1 : R/W; bitpos: [8:0]; default: 0;
+         *  Configures whether to push data into AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Push
+         */
+        uint32_t outfifo_wdata_ch1:9;
+        /** outfifo_push_ch1 : WT; bitpos: [9]; default: 0;
+         *  Configures the data that need to be pushed into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_push_ch1:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_push_ch1_reg_t;
+
+/** Type of out_link_ch1 register
+ *  Push control register of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_stop_ch1 : WT; bitpos: [0]; default: 0;
+         *  Configures whether to stop AHB_DMA's TX channel 1 from transmitting data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t outlink_stop_ch1:1;
+        /** outlink_start_ch1 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to enable AHB_DMA's TX channel 1 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outlink_start_ch1:1;
+        /** outlink_restart_ch1 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to restart TX channel 1 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t outlink_restart_ch1:1;
+        /** outlink_park_ch1 : RO; bitpos: [3]; default: 1;
+         *  Represents the status of the transmit descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t outlink_park_ch1:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_link_ch1_reg_t;
+
+/** Type of out_state_ch1 register
+ *  Transmit status of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
+         *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+         *  processed.
+         */
+        uint32_t outlink_dscr_addr_ch1:18;
+        /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_ch1:2;
+        /** out_state_ch1 : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_ch1:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_out_state_ch1_reg_t;
+
+/** Type of out_eof_des_addr_ch1 register
+ *  Transmit descriptor address when EOF occurs on TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_des_addr_ch1_reg_t;
+
+/** Type of out_eof_bfr_des_addr_ch1 register
+ *  The last transmit descriptor address when EOF occurs on TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor before the last transmit
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_bfr_des_addr_ch1_reg_t;
+
+/** Type of out_dscr_ch1 register
+ *  Current transmit descriptor address of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next transmit descriptor y+1 pointed by the current
+         *  transmit descriptor that has already been fetched.
+         */
+        uint32_t outlink_dscr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_ch1_reg_t;
+
+/** Type of out_dscr_bf0_ch1 register
+ *  The last transmit descriptor address of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current transmit descriptor y that has already been
+         *  fetched.
+         */
+        uint32_t outlink_dscr_bf0_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf0_ch1_reg_t;
+
+/** Type of out_dscr_bf1_ch1 register
+ *  The second-to-last transmit descriptor address of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous transmit descriptor y-1 that has already
+         *  been fetched.
+         */
+        uint32_t outlink_dscr_bf1_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf1_ch1_reg_t;
+
+/** Type of out_peri_ch1 register
+ *  Priority register of TX channel 1
+ */
+typedef union {
+    struct {
+        /** tx_pri_ch1 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of TX channel 1.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t tx_pri_ch1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_ch1_reg_t;
+
+/** Type of out_peri_sel_ch1 register
+ *  Peripheral selection register of TX channel 1
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_ch1 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to TX channel 1.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_out_sel_ch1:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_sel_ch1_reg_t;
+
+/** Type of in_conf0_ch2 register
+ *  Configuration register 0 of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_rst_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer.
+         */
+        uint32_t in_rst_ch2:1;
+        /** in_loop_test_ch2 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_ch2:1;
+        /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable INCR burst transfer for RX channel 2 to read
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t indscr_burst_en_ch2:1;
+        /** in_data_burst_en_ch2 : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 2 receiving data
+         *  when accessing internal SRAM.
+         */
+        uint32_t in_data_burst_en_ch2:1;
+        /** mem_trans_en_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable memory-to-memory data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t mem_trans_en_ch2:1;
+        /** in_etm_en_ch2 : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable ETM control for RX channel2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_etm_en_ch2:1;
+        /** in_data_burst_mode_sel_ch2 : R/W; bitpos: [7:6]; default: 1;
+         *  Configures max burst size for Rx channel2.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t in_data_burst_mode_sel_ch2:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_conf0_ch2_reg_t;
+
+/** Type of in_conf1_ch2 register
+ *  Configuration register 1 of RX channel 2
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** in_check_owner_ch2 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for RX channel 2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_check_owner_ch2:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_conf1_ch2_reg_t;
+
+/** Type of infifo_status_ch2 register
+ *  Receive FIFO status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** infifo_full_ch2 : RO; bitpos: [0]; default: 1;
+         *  Represents whether L1 RX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t infifo_full_ch2:1;
+        /** infifo_empty_ch2 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 RX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t infifo_empty_ch2:1;
+        uint32_t reserved_2:6;
+        /** infifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 RX FIFO for RX channel 2
+         */
+        uint32_t infifo_cnt_ch2:7;
+        uint32_t reserved_15:8;
+        /** in_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_ch2:1;
+        /** in_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_ch2:1;
+        /** in_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_ch2:1;
+        /** in_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_ch2:1;
+        /** in_buf_hungry_ch2 : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_ch2:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ahb_dma_infifo_status_ch2_reg_t;
+
+/** Type of in_pop_ch2 register
+ *  Receive FIFO status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch2 : RO; bitpos: [11:0]; default: 2048;
+         *  Represents the data popped from AHB_DMA FIFO.
+         */
+        uint32_t infifo_rdata_ch2:12;
+        /** infifo_pop_ch2 : WT; bitpos: [12]; default: 0;
+         *  Configures whether to pop data from AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Pop
+         */
+        uint32_t infifo_pop_ch2:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_pop_ch2_reg_t;
+
+/** Type of in_link_ch2 register
+ *  Receive FIFO status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_ch2 : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to return to current receive descriptor's address when there are
+         *  some errors in current receiving data.
+         *  0: Not return
+         *  1: Return
+         *  .
+         */
+        uint32_t inlink_auto_ret_ch2:1;
+        /** inlink_stop_ch2 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to stop AHB_DMA's RX channel 2 from receiving data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t inlink_stop_ch2:1;
+        /** inlink_start_ch2 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to enable AHB_DMA's RX channel 2 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t inlink_start_ch2:1;
+        /** inlink_restart_ch2 : WT; bitpos: [3]; default: 0;
+         *  Configures whether to restart RX channel 2 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t inlink_restart_ch2:1;
+        /** inlink_park_ch2 : RO; bitpos: [4]; default: 1;
+         *  Represents the status of the receive descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t inlink_park_ch2:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} ahb_dma_in_link_ch2_reg_t;
+
+/** Type of in_state_ch2 register
+ *  Receive status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
+         *  reserved
+         */
+        uint32_t inlink_dscr_addr_ch2:18;
+        /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_ch2:2;
+        /** in_state_ch2 : RO; bitpos: [22:20]; default: 0;
+         *  Represents the address of the lower 18 bits of the next receive descriptor to be
+         *  processed.
+         */
+        uint32_t in_state_ch2:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_in_state_ch2_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch2 register
+ *  Receive descriptor address when EOF occurs on RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_suc_eof_des_addr_ch2_reg_t;
+
+/** Type of in_err_eof_des_addr_ch2 register
+ *  Receive descriptor address when errors occur of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when there are some errors in the
+         *  currently received data.
+         */
+        uint32_t in_err_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_err_eof_des_addr_ch2_reg_t;
+
+/** Type of in_dscr_ch2 register
+ *  Current receive descriptor address of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next receive descriptor x+1 pointed by the current
+         *  receive descriptor that has already been fetched.
+         */
+        uint32_t inlink_dscr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_ch2_reg_t;
+
+/** Type of in_dscr_bf0_ch2 register
+ *  The last receive descriptor address of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current receive descriptor x that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf0_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf0_ch2_reg_t;
+
+/** Type of in_dscr_bf1_ch2 register
+ *  The second-to-last receive descriptor address of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous receive descriptor x-1 that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf1_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf1_ch2_reg_t;
+
+/** Type of in_peri_ch2 register
+ *  Priority register of RX channel 2
+ */
+typedef union {
+    struct {
+        /** rx_pri_ch2 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of RX channel 2.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t rx_pri_ch2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_ch2_reg_t;
+
+/** Type of in_peri_sel_ch2 register
+ *  Peripheral selection register of RX channel 2
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_ch2 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to RX channel 2.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_in_sel_ch2:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_sel_ch2_reg_t;
+
+/** Type of out_conf0_ch2 register
+ *  Configuration register 0 of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_rst_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer.
+         *  0: Release reset
+         *  1: Reset
+         */
+        uint32_t out_rst_ch2:1;
+        /** out_loop_test_ch2 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch2:1;
+        /** out_auto_wrback_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable automatic outlink write-back when all the data in TX
+         *  FIFO has been transmitted.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_auto_wrback_ch2:1;
+        /** out_eof_mode_ch2 : R/W; bitpos: [3]; default: 1;
+         *  Configures when to generate EOF flag.
+         *  0: EOF flag for TX channel 2 is generated when data to be transmitted has been
+         *  pushed into FIFO in AHB_DMA.
+         *  1: EOF flag for TX channel 2 is generated when data to be transmitted has been
+         *  popped from FIFO in AHB_DMA.
+         */
+        uint32_t out_eof_mode_ch2:1;
+        /** outdscr_burst_en_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable INCR burst transfer for TX channel 2 reading
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outdscr_burst_en_ch2:1;
+        /** out_data_burst_en_ch2 : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data
+         *  when accessing internal SRAM.
+         */
+        uint32_t out_data_burst_en_ch2:1;
+        /** out_etm_en_ch2 : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to enable ETM control for TX channel 2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_etm_en_ch2:1;
+        uint32_t reserved_7:1;
+        /** out_data_burst_mode_sel_ch2 : R/W; bitpos: [9:8]; default: 1;
+         *  Configures max burst size for TX channel2.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t out_data_burst_mode_sel_ch2:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_ch2_reg_t;
+
+/** Type of out_conf1_ch2 register
+ *  Configuration register 1 of TX channel 2
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** out_check_owner_ch2 : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for TX channel 2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_check_owner_ch2:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_out_conf1_ch2_reg_t;
+
+/** Type of outfifo_status_ch2 register
+ *  Receive FIFO status of RX channel 2
+ */
+typedef union {
+    struct {
+        /** outfifo_full_ch2 : RO; bitpos: [0]; default: 0;
+         *  Represents whether L1 TX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t outfifo_full_ch2:1;
+        /** outfifo_empty_ch2 : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 TX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t outfifo_empty_ch2:1;
+        uint32_t reserved_2:6;
+        /** outfifo_cnt_ch2 : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 TX FIFO for TX channel 2
+         */
+        uint32_t outfifo_cnt_ch2:7;
+        uint32_t reserved_15:8;
+        /** out_remain_under_1b_ch2 : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_ch2:1;
+        /** out_remain_under_2b_ch2 : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_ch2:1;
+        /** out_remain_under_3b_ch2 : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_ch2:1;
+        /** out_remain_under_4b_ch2 : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_ch2:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} ahb_dma_outfifo_status_ch2_reg_t;
+
+/** Type of out_push_ch2 register
+ *  Push control register of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch2 : R/W; bitpos: [8:0]; default: 0;
+         *  Configures whether to push data into AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Push
+         */
+        uint32_t outfifo_wdata_ch2:9;
+        /** outfifo_push_ch2 : WT; bitpos: [9]; default: 0;
+         *  Configures the data that need to be pushed into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_push_ch2:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_push_ch2_reg_t;
+
+/** Type of out_link_ch2 register
+ *  Push control register of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_stop_ch2 : WT; bitpos: [0]; default: 0;
+         *  Configures whether to stop AHB_DMA's TX channel 2 from transmitting data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t outlink_stop_ch2:1;
+        /** outlink_start_ch2 : WT; bitpos: [1]; default: 0;
+         *  Configures whether to enable AHB_DMA's TX channel 2 for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outlink_start_ch2:1;
+        /** outlink_restart_ch2 : WT; bitpos: [2]; default: 0;
+         *  Configures whether to restart TX channel 2 for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t outlink_restart_ch2:1;
+        /** outlink_park_ch2 : RO; bitpos: [3]; default: 1;
+         *  Represents the status of the transmit descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t outlink_park_ch2:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_link_ch2_reg_t;
+
+/** Type of out_state_ch2 register
+ *  Transmit status of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
+         *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+         *  processed.
+         */
+        uint32_t outlink_dscr_addr_ch2:18;
+        /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_ch2:2;
+        /** out_state_ch2 : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_ch2:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_out_state_ch2_reg_t;
+
+/** Type of out_eof_des_addr_ch2 register
+ *  Transmit descriptor address when EOF occurs on TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_des_addr_ch2_reg_t;
+
+/** Type of out_eof_bfr_des_addr_ch2 register
+ *  The last transmit descriptor address when EOF occurs on TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor before the last transmit
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_bfr_des_addr_ch2_reg_t;
+
+/** Type of out_dscr_ch2 register
+ *  Current transmit descriptor address of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next transmit descriptor y+1 pointed by the current
+         *  transmit descriptor that has already been fetched.
+         */
+        uint32_t outlink_dscr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_ch2_reg_t;
+
+/** Type of out_dscr_bf0_ch2 register
+ *  The last transmit descriptor address of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current transmit descriptor y that has already been
+         *  fetched.
+         */
+        uint32_t outlink_dscr_bf0_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf0_ch2_reg_t;
+
+/** Type of out_dscr_bf1_ch2 register
+ *  The second-to-last transmit descriptor address of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous transmit descriptor y-1 that has already
+         *  been fetched.
+         */
+        uint32_t outlink_dscr_bf1_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf1_ch2_reg_t;
+
+/** Type of out_peri_ch2 register
+ *  Priority register of TX channel 2
+ */
+typedef union {
+    struct {
+        /** tx_pri_ch2 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of TX channel 2.The larger of the value, the higher of the
+         *  priority..
+         */
+        uint32_t tx_pri_ch2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_ch2_reg_t;
+
+/** Type of out_peri_sel_ch2 register
+ *  Peripheral selection register of TX channel 2
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_ch2 : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to TX channel 2.
+         *  0: I3C
+         *  1: Dummy
+         *  2: UHCI0
+         *  3: I2S0
+         *  4: I2S1
+         *  5: I2S2
+         *  6: Dummy
+         *  7: Dummy
+         *  8: ADC_DAC
+         *  9: Dummy
+         *  10: RMT
+         *  11~15: Dummy
+         */
+        uint32_t peri_out_sel_ch2:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_sel_ch2_reg_t;
+
+/** Type of tx_ch_arb_weight_ch0 register
+ *  TX channel 0 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of TX channel0
+         */
+        uint32_t tx_arb_weight_value_ch0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_tx_ch_arb_weight_ch0_reg_t;
+
+/** Type of tx_arb_weight_opt_dir_ch0 register
+ *  TX channel 0 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_arb_weight_opt_dis_ch0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t;
+
+/** Type of tx_ch_arb_weight_ch1 register
+ *  TX channel 1 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of TX channel1
+         */
+        uint32_t tx_arb_weight_value_ch1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_tx_ch_arb_weight_ch1_reg_t;
+
+/** Type of tx_arb_weight_opt_dir_ch1 register
+ *  TX channel 1 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_arb_weight_opt_dis_ch1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t;
+
+/** Type of tx_ch_arb_weight_ch2 register
+ *  TX channel 2 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_value_ch2 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of TX channel2
+         */
+        uint32_t tx_arb_weight_value_ch2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_tx_ch_arb_weight_ch2_reg_t;
+
+/** Type of tx_arb_weight_opt_dir_ch2 register
+ *  TX channel 2 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weight_opt_dis_ch2 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_arb_weight_opt_dis_ch2:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_tx_arb_weight_opt_dir_ch2_reg_t;
+
+/** Type of rx_ch_arb_weight_ch0 register
+ *  RX channel 0 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weight_value_ch0 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of RX channel0
+         */
+        uint32_t rx_arb_weight_value_ch0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_rx_ch_arb_weight_ch0_reg_t;
+
+/** Type of rx_arb_weight_opt_dir_ch0 register
+ *  RX channel 0 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weight_opt_dis_ch0 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_arb_weight_opt_dis_ch0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t;
+
+/** Type of rx_ch_arb_weight_ch1 register
+ *  RX channel 1 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weight_value_ch1 : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of RX channel1
+         */
+        uint32_t rx_arb_weight_value_ch1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_rx_ch_arb_weight_ch1_reg_t;
+
+/** Type of rx_arb_weight_opt_dir_ch1 register
+ *  RX channel 1 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weight_opt_dis_ch1 : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_arb_weight_opt_dis_ch1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t;
+
+/** Type of in_link_addr_ch0 register
+ *  Link list descriptor address configuration of RX channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address
+         */
+        uint32_t inlink_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_link_addr_ch0_reg_t;
+
+/** Type of in_link_addr_ch1 register
+ *  Link list descriptor address configuration of RX channel 1
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address
+         */
+        uint32_t inlink_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_link_addr_ch1_reg_t;
+
+/** Type of in_link_addr_ch2 register
+ *  Link list descriptor address configuration of RX channel 2
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address
+         */
+        uint32_t inlink_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_link_addr_ch2_reg_t;
+
+/** Type of out_link_addr_ch0 register
+ *  Link list descriptor address configuration of TX channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address.
+         */
+        uint32_t outlink_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_link_addr_ch0_reg_t;
+
+/** Type of out_link_addr_ch1 register
+ *  Link list descriptor address configuration of TX channel 1
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address.
+         */
+        uint32_t outlink_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_link_addr_ch1_reg_t;
+
+/** Type of out_link_addr_ch2 register
+ *  Link list descriptor address configuration of TX channel 2
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address.
+         */
+        uint32_t outlink_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_link_addr_ch2_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  Accessible address space start address configuration register
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Accessible address space start address configuration register
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  Accessible address space end address configuration register
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the end address of accessible address space.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_end_addr_reg_t;
+
+/** Type of arb_timeout register
+ *  TX arbitration timeout configuration register
+ */
+typedef union {
+    struct {
+        /** arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the time slot. Measurement unit: AHB bus clock cycle.
+         */
+        uint32_t arb_timeout_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_reg_t;
+
+/** Type of weight_en register
+ *  TX weight arbitration enable register
+ */
+typedef union {
+    struct {
+        /** weight_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable weight arbitration.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t weight_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_reg_t;
+
+/** Type of module_clk_en register
+ *  Module clock force on register
+ */
+typedef union {
+    struct {
+        /** ahb_apb_sync_clk_en : R/W; bitpos: [2:0]; default: 7;
+         *  Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n:
+         *  0 : Not force on ahb_apb_sync n clock
+         *  1 : Force on ahb_apb_sync n clock
+         */
+        uint32_t ahb_apb_sync_clk_en:3;
+        /** out_dscr_clk_en : R/W; bitpos: [5:3]; default: 7;
+         *  Configures whether to force on out_dscr 2~0 module clock. For bit n:
+         *  0 : Not force on out_dscr n clock
+         *  1 : Force on out_dscr n clock
+         */
+        uint32_t out_dscr_clk_en:3;
+        /** out_ctrl_clk_en : R/W; bitpos: [8:6]; default: 7;
+         *  Configures whether to force on out_ctrl 2~0 module clock. For bit n:
+         *  0 : Not force on out_ctrl n clock
+         *  1 : Force on out_ctrl n clock
+         */
+        uint32_t out_ctrl_clk_en:3;
+        /** in_dscr_clk_en : R/W; bitpos: [11:9]; default: 7;
+         *  Configures whether to force on in_dscr 2~0 module clock. For bit n:
+         *  0 : Not force on in_dscr n clock
+         *  1 : Force on in_dscr n clock
+         */
+        uint32_t in_dscr_clk_en:3;
+        /** in_ctrl_clk_en : R/W; bitpos: [14:12]; default: 7;
+         *  Configures whether to force on in_ctrl 2~0 module clock. For bit n:
+         *  0 : Not force on in_ctrl n clock
+         *  1 : Force on in_ctrl n clock
+         */
+        uint32_t in_ctrl_clk_en:3;
+        uint32_t reserved_15:12;
+        /** cmd_arb_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether to force on cmd_arb module clock.
+         *  0 : Not force on cmd_arb clock
+         *  1 : Force on cmd_arb clock
+         */
+        uint32_t cmd_arb_clk_en:1;
+        /** ahbinf_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether to force on ahbinf module clock.
+         *  0 : Not force on ahbinf clock
+         *  1 : Force on ahbinf clock
+         */
+        uint32_t ahbinf_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} ahb_dma_module_clk_en_reg_t;
+
+/** Type of ahbinf_resp_err_status0 register
+ *  AHB response error status 0 register
+ */
+typedef union {
+    struct {
+        /** ahbinf_resp_err_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the AHB response error.
+         */
+        uint32_t ahbinf_resp_err_addr:32;
+    };
+    uint32_t val;
+} ahb_dma_ahbinf_resp_err_status0_reg_t;
+
+/** Type of ahbinf_resp_err_status1 register
+ *  AHB response error status 1 register
+ */
+typedef union {
+    struct {
+        /** ahbinf_resp_err_wr : RO; bitpos: [0]; default: 0;
+         *  Represents the AHB response error is write request.
+         */
+        uint32_t ahbinf_resp_err_wr:1;
+        /** ahbinf_resp_err_id : RO; bitpos: [4:1]; default: 15;
+         *  Represents the AHB response error request id.
+         */
+        uint32_t ahbinf_resp_err_id:4;
+        /** ahbinf_resp_err_ch_id : RO; bitpos: [7:5]; default: 0;
+         *  Represents the AHB response error request channel id.bit[2]=1:TX channel.
+         *  bit[2]=0:RX channel.
+         */
+        uint32_t ahbinf_resp_err_ch_id:3;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_ahbinf_resp_err_status1_reg_t;
+
+/** Type of in_done_des_addr_ch0 register
+ *  RX_done Inlink descriptor address of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the inlink descriptor when  this descriptor is completed .
+         */
+        uint32_t in_done_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_in_done_des_addr_ch0_reg_t;
+
+/** Type of out_done_des_addr_ch0 register
+ *  TX done outlink descriptor address of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the outlink descriptor when this descriptor is completed.
+         */
+        uint32_t out_done_des_addr_ch0:32;
+    };
+    uint32_t val;
+} ahb_dma_out_done_des_addr_ch0_reg_t;
+
+/** Type of in_done_des_addr_ch1 register
+ *  RX_done Inlink descriptor address of RX channel 1
+ */
+typedef union {
+    struct {
+        /** in_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the inlink descriptor when  this descriptor is completed .
+         */
+        uint32_t in_done_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_in_done_des_addr_ch1_reg_t;
+
+/** Type of out_done_des_addr_ch1 register
+ *  TX done outlink descriptor address of TX channel 1
+ */
+typedef union {
+    struct {
+        /** out_done_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the outlink descriptor when this descriptor is completed.
+         */
+        uint32_t out_done_des_addr_ch1:32;
+    };
+    uint32_t val;
+} ahb_dma_out_done_des_addr_ch1_reg_t;
+
+/** Type of in_done_des_addr_ch2 register
+ *  RX_done Inlink descriptor address of RX channel 2
+ */
+typedef union {
+    struct {
+        /** in_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the inlink descriptor when  this descriptor is completed .
+         */
+        uint32_t in_done_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_in_done_des_addr_ch2_reg_t;
+
+/** Type of out_done_des_addr_ch2 register
+ *  TX done outlink descriptor address of TX channel 2
+ */
+typedef union {
+    struct {
+        /** out_done_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the outlink descriptor when this descriptor is completed.
+         */
+        uint32_t out_done_des_addr_ch2:32;
+    };
+    uint32_t val;
+} ahb_dma_out_done_des_addr_ch2_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of out_crc_init_data_chn register
+ *  This register is used to config chn crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of tx crc initial value
+         */
+        uint32_t out_crc_init_data_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_init_data_chn_reg_t;
+
+/** Type of tx_crc_width_chn register
+ *  This register is used to confiig tx chn crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_width_chn:2;
+        /** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_lautch_flga_chn:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_width_chn_reg_t;
+
+/** Type of out_crc_clear_chn register
+ *  This register is used to clear chn crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of tx crc result
+         */
+        uint32_t out_crc_clear_chn_reg:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_clear_chn_reg_t;
+
+/** Type of out_crc_final_result_chn register
+ *  This register is used to store chn crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of tx
+         */
+        uint32_t out_crc_final_result_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_final_result_chn_reg_t;
+
+/** Type of tx_crc_en_wr_data_chn register
+ *  This resister is used to config chn crc en for every bit
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable tx ch0 crc 32bit on/off
+         */
+        uint32_t tx_crc_en_wr_data_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_en_addr_chn register
+ *  This register is used to config chn crc en addr
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_en_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_en_addr_chn_reg_t;
+
+/** Type of tx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_wr_data_chn:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_data_en_addr_chn_reg_t;
+
+/** Type of in_crc_init_data_chn register
+ *  This register is used to config chn crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of rx crc initial value
+         */
+        uint32_t in_crc_init_data_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_init_data_chn_reg_t;
+
+/** Type of rx_crc_width_chn register
+ *  This register is used to confiig rx chn crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_width_chn:2;
+        /** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_lautch_flga_chn:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_width_chn_reg_t;
+
+/** Type of in_crc_clear_chn register
+ *  This register is used to clear chn crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of rx crc result
+         */
+        uint32_t in_crc_clear_chn_reg:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_clear_chn_reg_t;
+
+/** Type of in_crc_final_result_chn register
+ *  This register is used to store chn crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of rx
+         */
+        uint32_t in_crc_final_result_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_final_result_chn_reg_t;
+
+/** Type of rx_crc_en_wr_data_chn register
+ *  This resister is used to config chn crc en for every bit
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable rx ch0 crc 32bit on/off
+         */
+        uint32_t rx_crc_en_wr_data_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_en_addr_chn register
+ *  This register is used to config chn crc en addr
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_en_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_en_addr_chn_reg_t;
+
+/** Type of rx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_wr_data_chn:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_data_en_addr_chn_reg_t;
+
+/** Type of rx_ch_arb_weigh_chn register
+ *  RX channel 2 arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of RX channeln
+         */
+        uint32_t rx_ch_arb_weigh_chn:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_rx_ch_arb_weigh_chn_reg_t;
+
+/** Type of rx_arb_weigh_opt_dir_chn register
+ *  RX channel 2 weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t;
+
+/** Type of arb_timeout_tx register
+ *  TX arbitration timeout configuration register
+ */
+typedef union {
+    struct {
+        /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the time slot for TX. Measurement unit: AHB bus clock cycle.
+         */
+        uint32_t arb_timeout_tx:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_tx_reg_t;
+
+/** Type of arb_timeout_rx register
+ *  RX arbitration timeout configuration register
+ */
+typedef union {
+    struct {
+        /** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the time slot for RX. Measurement unit: AHB bus clock cycle.
+         */
+        uint32_t arb_timeout_rx:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_rx_reg_t;
+
+/** Type of weight_en_tx register
+ *  TX weight arbitration enable register
+ */
+typedef union {
+    struct {
+        /** weight_en_tx : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable weight arbitration for TX.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t weight_en_tx:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_tx_reg_t;
+
+/** Type of weight_en_rx register
+ *  RX weight arbitration enable register
+ */
+typedef union {
+    struct {
+        /** weight_en_rx : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable weight arbitration for RX.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t weight_en_rx:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_rx_reg_t;
+
+
+typedef struct {
+    volatile ahb_dma_in_int_raw_ch0_reg_t in_int_raw_ch0;
+    volatile ahb_dma_in_int_st_ch0_reg_t in_int_st_ch0;
+    volatile ahb_dma_in_int_ena_ch0_reg_t in_int_ena_ch0;
+    volatile ahb_dma_in_int_clr_ch0_reg_t in_int_clr_ch0;
+    volatile ahb_dma_in_int_raw_ch1_reg_t in_int_raw_ch1;
+    volatile ahb_dma_in_int_st_ch1_reg_t in_int_st_ch1;
+    volatile ahb_dma_in_int_ena_ch1_reg_t in_int_ena_ch1;
+    volatile ahb_dma_in_int_clr_ch1_reg_t in_int_clr_ch1;
+    volatile ahb_dma_in_int_raw_ch2_reg_t in_int_raw_ch2;
+    volatile ahb_dma_in_int_st_ch2_reg_t in_int_st_ch2;
+    volatile ahb_dma_in_int_ena_ch2_reg_t in_int_ena_ch2;
+    volatile ahb_dma_in_int_clr_ch2_reg_t in_int_clr_ch2;
+    volatile ahb_dma_out_int_raw_ch0_reg_t out_int_raw_ch0;
+    volatile ahb_dma_out_int_st_ch0_reg_t out_int_st_ch0;
+    volatile ahb_dma_out_int_ena_ch0_reg_t out_int_ena_ch0;
+    volatile ahb_dma_out_int_clr_ch0_reg_t out_int_clr_ch0;
+    volatile ahb_dma_out_int_raw_ch1_reg_t out_int_raw_ch1;
+    volatile ahb_dma_out_int_st_ch1_reg_t out_int_st_ch1;
+    volatile ahb_dma_out_int_ena_ch1_reg_t out_int_ena_ch1;
+    volatile ahb_dma_out_int_clr_ch1_reg_t out_int_clr_ch1;
+    volatile ahb_dma_out_int_raw_ch2_reg_t out_int_raw_ch2;
+    volatile ahb_dma_out_int_st_ch2_reg_t out_int_st_ch2;
+    volatile ahb_dma_out_int_ena_ch2_reg_t out_int_ena_ch2;
+    volatile ahb_dma_out_int_clr_ch2_reg_t out_int_clr_ch2;
+    volatile ahb_dma_ahb_test_reg_t ahb_test;
+    volatile ahb_dma_misc_conf_reg_t misc_conf;
+    volatile ahb_dma_date_reg_t date;
+    uint32_t reserved_06c;
+    volatile ahb_dma_in_conf0_ch0_reg_t in_conf0_ch0;
+    volatile ahb_dma_in_conf1_ch0_reg_t in_conf1_ch0;
+    volatile ahb_dma_infifo_status_ch0_reg_t infifo_status_ch0;
+    volatile ahb_dma_in_pop_ch0_reg_t in_pop_ch0;
+    volatile ahb_dma_in_link_ch0_reg_t in_link_ch0;
+    volatile ahb_dma_in_state_ch0_reg_t in_state_ch0;
+    volatile ahb_dma_in_suc_eof_des_addr_ch0_reg_t in_suc_eof_des_addr_ch0;
+    volatile ahb_dma_in_err_eof_des_addr_ch0_reg_t in_err_eof_des_addr_ch0;
+    volatile ahb_dma_in_dscr_ch0_reg_t in_dscr_ch0;
+    volatile ahb_dma_in_dscr_bf0_ch0_reg_t in_dscr_bf0_ch0;
+    volatile ahb_dma_in_dscr_bf1_ch0_reg_t in_dscr_bf1_ch0;
+    volatile ahb_dma_in_peri_ch0_reg_t in_peri_ch0;
+    volatile ahb_dma_in_peri_sel_ch0_reg_t in_peri_sel_ch0;
+    uint32_t reserved_0a4[11];
+    volatile ahb_dma_out_conf0_ch0_reg_t out_conf0_ch0;
+    volatile ahb_dma_out_conf1_ch0_reg_t out_conf1_ch0;
+    volatile ahb_dma_outfifo_status_ch0_reg_t outfifo_status_ch0;
+    volatile ahb_dma_out_push_ch0_reg_t out_push_ch0;
+    volatile ahb_dma_out_link_ch0_reg_t out_link_ch0;
+    volatile ahb_dma_out_state_ch0_reg_t out_state_ch0;
+    volatile ahb_dma_out_eof_des_addr_ch0_reg_t out_eof_des_addr_ch0;
+    volatile ahb_dma_out_eof_bfr_des_addr_ch0_reg_t out_eof_bfr_des_addr_ch0;
+    volatile ahb_dma_out_dscr_ch0_reg_t out_dscr_ch0;
+    volatile ahb_dma_out_dscr_bf0_ch0_reg_t out_dscr_bf0_ch0;
+    volatile ahb_dma_out_dscr_bf1_ch0_reg_t out_dscr_bf1_ch0;
+    volatile ahb_dma_out_peri_ch0_reg_t out_peri_ch0;
+    volatile ahb_dma_out_peri_sel_ch0_reg_t out_peri_sel_ch0;
+    uint32_t reserved_104[11];
+    volatile ahb_dma_in_conf0_ch1_reg_t in_conf0_ch1;
+    volatile ahb_dma_in_conf1_ch1_reg_t in_conf1_ch1;
+    volatile ahb_dma_infifo_status_ch1_reg_t infifo_status_ch1;
+    volatile ahb_dma_in_pop_ch1_reg_t in_pop_ch1;
+    volatile ahb_dma_in_link_ch1_reg_t in_link_ch1;
+    volatile ahb_dma_in_state_ch1_reg_t in_state_ch1;
+    volatile ahb_dma_in_suc_eof_des_addr_ch1_reg_t in_suc_eof_des_addr_ch1;
+    volatile ahb_dma_in_err_eof_des_addr_ch1_reg_t in_err_eof_des_addr_ch1;
+    volatile ahb_dma_in_dscr_ch1_reg_t in_dscr_ch1;
+    volatile ahb_dma_in_dscr_bf0_ch1_reg_t in_dscr_bf0_ch1;
+    volatile ahb_dma_in_dscr_bf1_ch1_reg_t in_dscr_bf1_ch1;
+    volatile ahb_dma_in_peri_ch1_reg_t in_peri_ch1;
+    volatile ahb_dma_in_peri_sel_ch1_reg_t in_peri_sel_ch1;
+    uint32_t reserved_164[11];
+    volatile ahb_dma_out_conf0_ch1_reg_t out_conf0_ch1;
+    volatile ahb_dma_out_conf1_ch1_reg_t out_conf1_ch1;
+    volatile ahb_dma_outfifo_status_ch1_reg_t outfifo_status_ch1;
+    volatile ahb_dma_out_push_ch1_reg_t out_push_ch1;
+    volatile ahb_dma_out_link_ch1_reg_t out_link_ch1;
+    volatile ahb_dma_out_state_ch1_reg_t out_state_ch1;
+    volatile ahb_dma_out_eof_des_addr_ch1_reg_t out_eof_des_addr_ch1;
+    volatile ahb_dma_out_eof_bfr_des_addr_ch1_reg_t out_eof_bfr_des_addr_ch1;
+    volatile ahb_dma_out_dscr_ch1_reg_t out_dscr_ch1;
+    volatile ahb_dma_out_dscr_bf0_ch1_reg_t out_dscr_bf0_ch1;
+    volatile ahb_dma_out_dscr_bf1_ch1_reg_t out_dscr_bf1_ch1;
+    volatile ahb_dma_out_peri_ch1_reg_t out_peri_ch1;
+    volatile ahb_dma_out_peri_sel_ch1_reg_t out_peri_sel_ch1;
+    uint32_t reserved_1c4[11];
+    volatile ahb_dma_in_conf0_ch2_reg_t in_conf0_ch2;
+    volatile ahb_dma_in_conf1_ch2_reg_t in_conf1_ch2;
+    volatile ahb_dma_infifo_status_ch2_reg_t infifo_status_ch2;
+    volatile ahb_dma_in_pop_ch2_reg_t in_pop_ch2;
+    volatile ahb_dma_in_link_ch2_reg_t in_link_ch2;
+    volatile ahb_dma_in_state_ch2_reg_t in_state_ch2;
+    volatile ahb_dma_in_suc_eof_des_addr_ch2_reg_t in_suc_eof_des_addr_ch2;
+    volatile ahb_dma_in_err_eof_des_addr_ch2_reg_t in_err_eof_des_addr_ch2;
+    volatile ahb_dma_in_dscr_ch2_reg_t in_dscr_ch2;
+    volatile ahb_dma_in_dscr_bf0_ch2_reg_t in_dscr_bf0_ch2;
+    volatile ahb_dma_in_dscr_bf1_ch2_reg_t in_dscr_bf1_ch2;
+    volatile ahb_dma_in_peri_ch2_reg_t in_peri_ch2;
+    volatile ahb_dma_in_peri_sel_ch2_reg_t in_peri_sel_ch2;
+    uint32_t reserved_224[11];
+    volatile ahb_dma_out_conf0_ch2_reg_t out_conf0_ch2;
+    volatile ahb_dma_out_conf1_ch2_reg_t out_conf1_ch2;
+    volatile ahb_dma_outfifo_status_ch2_reg_t outfifo_status_ch2;
+    volatile ahb_dma_out_push_ch2_reg_t out_push_ch2;
+    volatile ahb_dma_out_link_ch2_reg_t out_link_ch2;
+    volatile ahb_dma_out_state_ch2_reg_t out_state_ch2;
+    volatile ahb_dma_out_eof_des_addr_ch2_reg_t out_eof_des_addr_ch2;
+    volatile ahb_dma_out_eof_bfr_des_addr_ch2_reg_t out_eof_bfr_des_addr_ch2;
+    volatile ahb_dma_out_dscr_ch2_reg_t out_dscr_ch2;
+    volatile ahb_dma_out_dscr_bf0_ch2_reg_t out_dscr_bf0_ch2;
+    volatile ahb_dma_out_dscr_bf1_ch2_reg_t out_dscr_bf1_ch2;
+    volatile ahb_dma_out_peri_ch2_reg_t out_peri_ch2;
+    volatile ahb_dma_out_peri_sel_ch2_reg_t out_peri_sel_ch2;
+    uint32_t reserved_284[14];
+    volatile ahb_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch0;
+    volatile ahb_dma_tx_crc_width_chn_reg_t tx_crc_width_ch0;
+    volatile ahb_dma_out_crc_clear_chn_reg_t out_crc_clear_ch0;
+    volatile ahb_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch0;
+    volatile ahb_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch0;
+    volatile ahb_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch0;
+    volatile ahb_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch0;
+    volatile ahb_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch0;
+    volatile ahb_dma_tx_ch_arb_weight_ch0_reg_t tx_ch_arb_weight_ch0;
+    volatile ahb_dma_tx_arb_weight_opt_dir_ch0_reg_t tx_arb_weight_opt_dir_ch0;
+    volatile ahb_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch1;
+    volatile ahb_dma_tx_crc_width_chn_reg_t tx_crc_width_ch1;
+    volatile ahb_dma_out_crc_clear_chn_reg_t out_crc_clear_ch1;
+    volatile ahb_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch1;
+    volatile ahb_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch1;
+    volatile ahb_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch1;
+    volatile ahb_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch1;
+    volatile ahb_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch1;
+    volatile ahb_dma_tx_ch_arb_weight_ch1_reg_t tx_ch_arb_weight_ch1;
+    volatile ahb_dma_tx_arb_weight_opt_dir_ch1_reg_t tx_arb_weight_opt_dir_ch1;
+    volatile ahb_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch2;
+    volatile ahb_dma_tx_crc_width_chn_reg_t tx_crc_width_ch2;
+    volatile ahb_dma_out_crc_clear_chn_reg_t out_crc_clear_ch2;
+    volatile ahb_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch2;
+    volatile ahb_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch2;
+    volatile ahb_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch2;
+    volatile ahb_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch2;
+    volatile ahb_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch2;
+    volatile ahb_dma_tx_ch_arb_weight_ch2_reg_t tx_ch_arb_weight_ch2;
+    volatile ahb_dma_tx_arb_weight_opt_dir_ch2_reg_t tx_arb_weight_opt_dir_ch2;
+    volatile ahb_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch0;
+    volatile ahb_dma_rx_crc_width_chn_reg_t rx_crc_width_ch0;
+    volatile ahb_dma_in_crc_clear_chn_reg_t in_crc_clear_ch0;
+    volatile ahb_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch0;
+    volatile ahb_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch0;
+    volatile ahb_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch0;
+    volatile ahb_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch0;
+    volatile ahb_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch0;
+    volatile ahb_dma_rx_ch_arb_weight_ch0_reg_t rx_ch_arb_weight_ch0;
+    volatile ahb_dma_rx_arb_weight_opt_dir_ch0_reg_t rx_arb_weight_opt_dir_ch0;
+    volatile ahb_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch1;
+    volatile ahb_dma_rx_crc_width_chn_reg_t rx_crc_width_ch1;
+    volatile ahb_dma_in_crc_clear_chn_reg_t in_crc_clear_ch1;
+    volatile ahb_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch1;
+    volatile ahb_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch1;
+    volatile ahb_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch1;
+    volatile ahb_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch1;
+    volatile ahb_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch1;
+    volatile ahb_dma_rx_ch_arb_weight_ch1_reg_t rx_ch_arb_weight_ch1;
+    volatile ahb_dma_rx_arb_weight_opt_dir_ch1_reg_t rx_arb_weight_opt_dir_ch1;
+    volatile ahb_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch2;
+    volatile ahb_dma_rx_crc_width_chn_reg_t rx_crc_width_ch2;
+    volatile ahb_dma_in_crc_clear_chn_reg_t in_crc_clear_ch2;
+    volatile ahb_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch2;
+    volatile ahb_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch2;
+    volatile ahb_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch2;
+    volatile ahb_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch2;
+    volatile ahb_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch2;
+    volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch2;
+    volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch2;
+    volatile ahb_dma_in_link_addr_ch0_reg_t in_link_addr_ch0;
+    volatile ahb_dma_in_link_addr_ch1_reg_t in_link_addr_ch1;
+    volatile ahb_dma_in_link_addr_ch2_reg_t in_link_addr_ch2;
+    volatile ahb_dma_out_link_addr_ch0_reg_t out_link_addr_ch0;
+    volatile ahb_dma_out_link_addr_ch1_reg_t out_link_addr_ch1;
+    volatile ahb_dma_out_link_addr_ch2_reg_t out_link_addr_ch2;
+    volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx;
+    volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx;
+    volatile ahb_dma_weight_en_tx_reg_t weight_en_tx;
+    volatile ahb_dma_weight_en_rx_reg_t weight_en_rx;
+    volatile ahb_dma_arb_timeout_reg_t arb_timeout;
+    uint32_t reserved_3e0[8];
+    volatile ahb_dma_weight_en_reg_t weight_en;
+    volatile ahb_dma_module_clk_en_reg_t module_clk_en;
+    volatile ahb_dma_ahbinf_resp_err_status0_reg_t ahbinf_resp_err_status0;
+    volatile ahb_dma_ahbinf_resp_err_status1_reg_t ahbinf_resp_err_status1;
+    volatile ahb_dma_in_done_des_addr_ch0_reg_t in_done_des_addr_ch0;
+    volatile ahb_dma_out_done_des_addr_ch0_reg_t out_done_des_addr_ch0;
+    volatile ahb_dma_in_done_des_addr_ch1_reg_t in_done_des_addr_ch1;
+    volatile ahb_dma_out_done_des_addr_ch1_reg_t out_done_des_addr_ch1;
+    volatile ahb_dma_in_done_des_addr_ch2_reg_t in_done_des_addr_ch2;
+    volatile ahb_dma_out_done_des_addr_ch2_reg_t out_done_des_addr_ch2;
+} ahb_dma_dev_t;
+
+extern ahb_dma_dev_t AHB_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ahb_dma_dev_t) == 0x428, "Invalid size of ahb_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_reg.h
new file mode 100644
index 0000000000..8fcba6d907
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_reg.h
@@ -0,0 +1,4654 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AHB_DMA_IN_INT_RAW_CH0_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define AHB_DMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x0)
+/** AHB_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_RAW_M  (AHB_DMA_IN_DONE_CH0_INT_RAW_V << AHB_DMA_IN_DONE_CH0_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH0_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define AHB_DMA_IN_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x4)
+/** AHB_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_ST_M  (AHB_DMA_IN_DONE_CH0_INT_ST_V << AHB_DMA_IN_DONE_CH0_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH0_INT_ST_V << AHB_DMA_INFIFO_OVF_CH0_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH0_INT_ST_V << AHB_DMA_INFIFO_UDF_CH0_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define AHB_DMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8)
+/** AHB_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH0_INT
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_ENA_M  (AHB_DMA_IN_DONE_CH0_INT_ENA_V << AHB_DMA_IN_DONE_CH0_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define AHB_DMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xc)
+/** AHB_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH0_INT
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_CLR_M  (AHB_DMA_IN_DONE_CH0_INT_CLR_V << AHB_DMA_IN_DONE_CH0_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S  7
+
+/** AHB_DMA_IN_INT_RAW_CH1_REG register
+ *  Raw interrupt status of RX channel 1
+ */
+#define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10)
+/** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_RAW_M  (AHB_DMA_IN_DONE_CH1_INT_RAW_V << AHB_DMA_IN_DONE_CH1_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH1_REG register
+ *  Masked interrupt status of RX channel 1
+ */
+#define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14)
+/** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_ST_M  (AHB_DMA_IN_DONE_CH1_INT_ST_V << AHB_DMA_IN_DONE_CH1_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH1_INT_ST_V << AHB_DMA_INFIFO_OVF_CH1_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH1_INT_ST_V << AHB_DMA_INFIFO_UDF_CH1_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of RX channel 1
+ */
+#define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18)
+/** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH1_INT
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_ENA_M  (AHB_DMA_IN_DONE_CH1_INT_ENA_V << AHB_DMA_IN_DONE_CH1_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of RX channel 1
+ */
+#define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c)
+/** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH1_INT
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_CLR_M  (AHB_DMA_IN_DONE_CH1_INT_CLR_V << AHB_DMA_IN_DONE_CH1_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S  7
+
+/** AHB_DMA_IN_INT_RAW_CH2_REG register
+ *  Raw interrupt status of RX channel 2
+ */
+#define AHB_DMA_IN_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20)
+/** AHB_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_RAW_M  (AHB_DMA_IN_DONE_CH2_INT_RAW_V << AHB_DMA_IN_DONE_CH2_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH2_REG register
+ *  Masked interrupt status of RX channel 2
+ */
+#define AHB_DMA_IN_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x24)
+/** AHB_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_ST_M  (AHB_DMA_IN_DONE_CH2_INT_ST_V << AHB_DMA_IN_DONE_CH2_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH2_INT_ST_V << AHB_DMA_INFIFO_OVF_CH2_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH2_INT_ST_V << AHB_DMA_INFIFO_UDF_CH2_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of RX channel 2
+ */
+#define AHB_DMA_IN_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x28)
+/** AHB_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH2_INT
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_ENA_M  (AHB_DMA_IN_DONE_CH2_INT_ENA_V << AHB_DMA_IN_DONE_CH2_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of RX channel 2
+ */
+#define AHB_DMA_IN_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x2c)
+/** AHB_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH2_INT
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_CLR_M  (AHB_DMA_IN_DONE_CH2_INT_CLR_V << AHB_DMA_IN_DONE_CH2_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S  7
+
+/** AHB_DMA_OUT_INT_RAW_CH0_REG register
+ *  //Raw interrupt status of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x30)
+/** AHB_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW_M  (AHB_DMA_OUT_DONE_CH0_INT_RAW_V << AHB_DMA_OUT_DONE_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW_M  (AHB_DMA_OUT_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34)
+/** AHB_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_ST_M  (AHB_DMA_OUT_DONE_CH0_INT_ST_V << AHB_DMA_OUT_DONE_CH0_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_ST_M  (AHB_DMA_OUT_EOF_CH0_INT_ST_V << AHB_DMA_OUT_EOF_CH0_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x38)
+/** AHB_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA_M  (AHB_DMA_OUT_DONE_CH0_INT_ENA_V << AHB_DMA_OUT_DONE_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA_M  (AHB_DMA_OUT_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3c)
+/** AHB_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR_M  (AHB_DMA_OUT_DONE_CH0_INT_CLR_V << AHB_DMA_OUT_DONE_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR_M  (AHB_DMA_OUT_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S  6
+
+/** AHB_DMA_OUT_INT_RAW_CH1_REG register
+ *  //Raw interrupt status of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x40)
+/** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW_M  (AHB_DMA_OUT_DONE_CH1_INT_RAW_V << AHB_DMA_OUT_DONE_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW_M  (AHB_DMA_OUT_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt status of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x44)
+/** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_ST_M  (AHB_DMA_OUT_DONE_CH1_INT_ST_V << AHB_DMA_OUT_DONE_CH1_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_ST_M  (AHB_DMA_OUT_EOF_CH1_INT_ST_V << AHB_DMA_OUT_EOF_CH1_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x48)
+/** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA_M  (AHB_DMA_OUT_DONE_CH1_INT_ENA_V << AHB_DMA_OUT_DONE_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA_M  (AHB_DMA_OUT_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x4c)
+/** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR_M  (AHB_DMA_OUT_DONE_CH1_INT_CLR_V << AHB_DMA_OUT_DONE_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR_M  (AHB_DMA_OUT_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S  6
+
+/** AHB_DMA_OUT_INT_RAW_CH2_REG register
+ *  //Raw interrupt status of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x50)
+/** AHB_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW_M  (AHB_DMA_OUT_DONE_CH2_INT_RAW_V << AHB_DMA_OUT_DONE_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW_M  (AHB_DMA_OUT_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt status of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x54)
+/** AHB_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_ST_M  (AHB_DMA_OUT_DONE_CH2_INT_ST_V << AHB_DMA_OUT_DONE_CH2_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_ST_M  (AHB_DMA_OUT_EOF_CH2_INT_ST_V << AHB_DMA_OUT_EOF_CH2_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x58)
+/** AHB_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA_M  (AHB_DMA_OUT_DONE_CH2_INT_ENA_V << AHB_DMA_OUT_DONE_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA_M  (AHB_DMA_OUT_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x5c)
+/** AHB_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR_M  (AHB_DMA_OUT_DONE_CH2_INT_CLR_V << AHB_DMA_OUT_DONE_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR_M  (AHB_DMA_OUT_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S  6
+
+/** AHB_DMA_AHB_TEST_REG register
+ *  only for test
+ */
+#define AHB_DMA_AHB_TEST_REG (DR_REG_AHB_DMA_BASE + 0x60)
+/** AHB_DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_AHB_TESTMODE    0x00000007U
+#define AHB_DMA_AHB_TESTMODE_M  (AHB_DMA_AHB_TESTMODE_V << AHB_DMA_AHB_TESTMODE_S)
+#define AHB_DMA_AHB_TESTMODE_V  0x00000007U
+#define AHB_DMA_AHB_TESTMODE_S  0
+/** AHB_DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_AHB_TESTADDR    0x00000003U
+#define AHB_DMA_AHB_TESTADDR_M  (AHB_DMA_AHB_TESTADDR_V << AHB_DMA_AHB_TESTADDR_S)
+#define AHB_DMA_AHB_TESTADDR_V  0x00000003U
+#define AHB_DMA_AHB_TESTADDR_S  4
+
+/** AHB_DMA_MISC_CONF_REG register
+ *  reserved
+ */
+#define AHB_DMA_MISC_CONF_REG (DR_REG_AHB_DMA_BASE + 0x64)
+/** AHB_DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset the internal AHB FSM
+ */
+#define AHB_DMA_AHBM_RST_INTER    (BIT(0))
+#define AHB_DMA_AHBM_RST_INTER_M  (AHB_DMA_AHBM_RST_INTER_V << AHB_DMA_AHBM_RST_INTER_S)
+#define AHB_DMA_AHBM_RST_INTER_V  0x00000001U
+#define AHB_DMA_AHBM_RST_INTER_S  0
+/** AHB_DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to disable the fixed-priority channel arbitration.
+ *  0: Enable
+ *  1: Disable
+ */
+#define AHB_DMA_ARB_PRI_DIS    (BIT(2))
+#define AHB_DMA_ARB_PRI_DIS_M  (AHB_DMA_ARB_PRI_DIS_V << AHB_DMA_ARB_PRI_DIS_S)
+#define AHB_DMA_ARB_PRI_DIS_V  0x00000001U
+#define AHB_DMA_ARB_PRI_DIS_S  2
+/** AHB_DMA_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures clock gating.
+ *  0: Support clock only when the application writes registers.
+ *  1: Always force the clock on for registers.
+ */
+#define AHB_DMA_CLK_EN    (BIT(3))
+#define AHB_DMA_CLK_EN_M  (AHB_DMA_CLK_EN_V << AHB_DMA_CLK_EN_S)
+#define AHB_DMA_CLK_EN_V  0x00000001U
+#define AHB_DMA_CLK_EN_S  3
+
+/** AHB_DMA_DATE_REG register
+ *  Version control register
+ */
+#define AHB_DMA_DATE_REG (DR_REG_AHB_DMA_BASE + 0x68)
+/** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 2425376;
+ *  Version control register
+ */
+#define AHB_DMA_DATE    0xFFFFFFFFU
+#define AHB_DMA_DATE_M  (AHB_DMA_DATE_V << AHB_DMA_DATE_S)
+#define AHB_DMA_DATE_V  0xFFFFFFFFU
+#define AHB_DMA_DATE_S  0
+
+/** AHB_DMA_IN_CONF0_CH0_REG register
+ *  Configuration register 0 of RX channel 0
+ */
+#define AHB_DMA_IN_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x70)
+/** AHB_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH0    (BIT(0))
+#define AHB_DMA_IN_RST_CH0_M  (AHB_DMA_IN_RST_CH0_V << AHB_DMA_IN_RST_CH0_S)
+#define AHB_DMA_IN_RST_CH0_V  0x00000001U
+#define AHB_DMA_IN_RST_CH0_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH0    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH0_M  (AHB_DMA_IN_LOOP_TEST_CH0_V << AHB_DMA_IN_LOOP_TEST_CH0_S)
+#define AHB_DMA_IN_LOOP_TEST_CH0_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH0_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 0 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH0    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH0_M  (AHB_DMA_INDSCR_BURST_EN_CH0_V << AHB_DMA_INDSCR_BURST_EN_CH0_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH0_S  2
+/** AHB_DMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 0 receiving data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_IN_DATA_BURST_EN_CH0    (BIT(3))
+#define AHB_DMA_IN_DATA_BURST_EN_CH0_M  (AHB_DMA_IN_DATA_BURST_EN_CH0_V << AHB_DMA_IN_DATA_BURST_EN_CH0_S)
+#define AHB_DMA_IN_DATA_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_IN_DATA_BURST_EN_CH0_S  3
+/** AHB_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH0    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH0_M  (AHB_DMA_MEM_TRANS_EN_CH0_V << AHB_DMA_MEM_TRANS_EN_CH0_S)
+#define AHB_DMA_MEM_TRANS_EN_CH0_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH0_S  4
+/** AHB_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH0    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH0_M  (AHB_DMA_IN_ETM_EN_CH0_V << AHB_DMA_IN_ETM_EN_CH0_S)
+#define AHB_DMA_IN_ETM_EN_CH0_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH0_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 1;
+ *  Configures max burst size for Rx channel0.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S  6
+
+/** AHB_DMA_IN_CONF1_CH0_REG register
+ *  Configuration register 1 of RX channel 0
+ */
+#define AHB_DMA_IN_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x74)
+/** AHB_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH0    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH0_M  (AHB_DMA_IN_CHECK_OWNER_CH0_V << AHB_DMA_IN_CHECK_OWNER_CH0_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH0_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH0_REG register
+ *  Receive FIFO status of RX channel 0
+ */
+#define AHB_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x78)
+/** AHB_DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH0    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH0_M  (AHB_DMA_INFIFO_FULL_CH0_V << AHB_DMA_INFIFO_FULL_CH0_S)
+#define AHB_DMA_INFIFO_FULL_CH0_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH0_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH0    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH0_M  (AHB_DMA_INFIFO_EMPTY_CH0_V << AHB_DMA_INFIFO_EMPTY_CH0_S)
+#define AHB_DMA_INFIFO_EMPTY_CH0_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH0_S  1
+/** AHB_DMA_INFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 0
+ */
+#define AHB_DMA_INFIFO_CNT_CH0    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH0_M  (AHB_DMA_INFIFO_CNT_CH0_V << AHB_DMA_INFIFO_CNT_CH0_S)
+#define AHB_DMA_INFIFO_CNT_CH0_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH0_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH0    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH0_M  (AHB_DMA_IN_BUF_HUNGRY_CH0_V << AHB_DMA_IN_BUF_HUNGRY_CH0_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH0_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH0_S  27
+
+/** AHB_DMA_IN_POP_CH0_REG register
+ *  Receive FIFO status of RX channel 0
+ */
+#define AHB_DMA_IN_POP_CH0_REG (DR_REG_AHB_DMA_BASE + 0x7c)
+/** AHB_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH0    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH0_M  (AHB_DMA_INFIFO_RDATA_CH0_V << AHB_DMA_INFIFO_RDATA_CH0_S)
+#define AHB_DMA_INFIFO_RDATA_CH0_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH0_S  0
+/** AHB_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH0    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH0_M  (AHB_DMA_INFIFO_POP_CH0_V << AHB_DMA_INFIFO_POP_CH0_S)
+#define AHB_DMA_INFIFO_POP_CH0_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH0_S  12
+
+/** AHB_DMA_IN_LINK_CH0_REG register
+ *  Receive FIFO status of RX channel 0
+ */
+#define AHB_DMA_IN_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x80)
+/** AHB_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ *  .
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH0    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH0_M  (AHB_DMA_INLINK_AUTO_RET_CH0_V << AHB_DMA_INLINK_AUTO_RET_CH0_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH0_S  0
+/** AHB_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 0 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH0    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH0_M  (AHB_DMA_INLINK_STOP_CH0_V << AHB_DMA_INLINK_STOP_CH0_S)
+#define AHB_DMA_INLINK_STOP_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH0_S  1
+/** AHB_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 0 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH0    (BIT(2))
+#define AHB_DMA_INLINK_START_CH0_M  (AHB_DMA_INLINK_START_CH0_V << AHB_DMA_INLINK_START_CH0_S)
+#define AHB_DMA_INLINK_START_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH0_S  2
+/** AHB_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 0 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH0    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH0_M  (AHB_DMA_INLINK_RESTART_CH0_V << AHB_DMA_INLINK_RESTART_CH0_S)
+#define AHB_DMA_INLINK_RESTART_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH0_S  3
+/** AHB_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH0    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH0_M  (AHB_DMA_INLINK_PARK_CH0_V << AHB_DMA_INLINK_PARK_CH0_S)
+#define AHB_DMA_INLINK_PARK_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH0_S  4
+
+/** AHB_DMA_IN_STATE_CH0_REG register
+ *  Receive status of RX channel 0
+ */
+#define AHB_DMA_IN_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x84)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0_M  (AHB_DMA_INLINK_DSCR_ADDR_CH0_V << AHB_DMA_INLINK_DSCR_ADDR_CH0_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH0    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH0_M  (AHB_DMA_IN_DSCR_STATE_CH0_V << AHB_DMA_IN_DSCR_STATE_CH0_S)
+#define AHB_DMA_IN_DSCR_STATE_CH0_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH0_S  18
+/** AHB_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_IN_STATE_CH0    0x00000007U
+#define AHB_DMA_IN_STATE_CH0_M  (AHB_DMA_IN_STATE_CH0_V << AHB_DMA_IN_STATE_CH0_S)
+#define AHB_DMA_IN_STATE_CH0_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH0_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 0
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x88)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Receive descriptor address when errors occur of RX channel 0
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8c)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_DSCR_CH0_REG register
+ *  Current receive descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x90)
+/** AHB_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH0_M  (AHB_DMA_INLINK_DSCR_CH0_V << AHB_DMA_INLINK_DSCR_CH0_S)
+#define AHB_DMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH0_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH0_REG register
+ *  The last receive descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x94)
+/** AHB_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH0_M  (AHB_DMA_INLINK_DSCR_BF0_CH0_V << AHB_DMA_INLINK_DSCR_BF0_CH0_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH0_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH0_REG register
+ *  The second-to-last receive descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x98)
+/** AHB_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH0_M  (AHB_DMA_INLINK_DSCR_BF1_CH0_V << AHB_DMA_INLINK_DSCR_BF1_CH0_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH0_S  0
+
+/** AHB_DMA_IN_PRI_CH0_REG register
+ *  Priority register of RX channel 0
+ */
+#define AHB_DMA_IN_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x9c)
+/** AHB_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 0.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_RX_PRI_CH0    0x0000000FU
+#define AHB_DMA_RX_PRI_CH0_M  (AHB_DMA_RX_PRI_CH0_V << AHB_DMA_RX_PRI_CH0_S)
+#define AHB_DMA_RX_PRI_CH0_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH0_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH0_REG register
+ *  Peripheral selection register of RX channel 0
+ */
+#define AHB_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0xa0)
+/** AHB_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 0.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_IN_SEL_CH0    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH0_M  (AHB_DMA_PERI_IN_SEL_CH0_V << AHB_DMA_PERI_IN_SEL_CH0_S)
+#define AHB_DMA_PERI_IN_SEL_CH0_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH0_S  0
+
+/** AHB_DMA_OUT_CONF0_CH0_REG register
+ *  Configuration register 0 of TX channel 0
+ */
+#define AHB_DMA_OUT_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd0)
+/** AHB_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH0    (BIT(0))
+#define AHB_DMA_OUT_RST_CH0_M  (AHB_DMA_OUT_RST_CH0_V << AHB_DMA_OUT_RST_CH0_S)
+#define AHB_DMA_OUT_RST_CH0_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH0_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH0    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH0_M  (AHB_DMA_OUT_LOOP_TEST_CH0_V << AHB_DMA_OUT_LOOP_TEST_CH0_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH0_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0_M  (AHB_DMA_OUT_AUTO_WRBACK_CH0_V << AHB_DMA_OUT_AUTO_WRBACK_CH0_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 0 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 0 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH0    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH0_M  (AHB_DMA_OUT_EOF_MODE_CH0_V << AHB_DMA_OUT_EOF_MODE_CH0_S)
+#define AHB_DMA_OUT_EOF_MODE_CH0_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH0_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 0 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0_M  (AHB_DMA_OUTDSCR_BURST_EN_CH0_V << AHB_DMA_OUTDSCR_BURST_EN_CH0_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0_S  4
+/** AHB_DMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to 1 to enable INCR4 burst transfer for Tx channel 0 transmitting data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_OUT_DATA_BURST_EN_CH0    (BIT(5))
+#define AHB_DMA_OUT_DATA_BURST_EN_CH0_M  (AHB_DMA_OUT_DATA_BURST_EN_CH0_V << AHB_DMA_OUT_DATA_BURST_EN_CH0_S)
+#define AHB_DMA_OUT_DATA_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_OUT_DATA_BURST_EN_CH0_S  5
+/** AHB_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH0    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH0_M  (AHB_DMA_OUT_ETM_EN_CH0_V << AHB_DMA_OUT_ETM_EN_CH0_S)
+#define AHB_DMA_OUT_ETM_EN_CH0_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH0_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 1;
+ *  Configures max burst size for TX channel0.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S  8
+
+/** AHB_DMA_OUT_CONF1_CH0_REG register
+ *  Configuration register 1 of TX channel 0
+ */
+#define AHB_DMA_OUT_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd4)
+/** AHB_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH0    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH0_M  (AHB_DMA_OUT_CHECK_OWNER_CH0_V << AHB_DMA_OUT_CHECK_OWNER_CH0_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH0_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH0_REG register
+ *  Receive FIFO status of RX channel 0
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0xd8)
+/** AHB_DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH0    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH0_M  (AHB_DMA_OUTFIFO_FULL_CH0_V << AHB_DMA_OUTFIFO_FULL_CH0_S)
+#define AHB_DMA_OUTFIFO_FULL_CH0_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH0_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH0    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH0_M  (AHB_DMA_OUTFIFO_EMPTY_CH0_V << AHB_DMA_OUTFIFO_EMPTY_CH0_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH0_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH0_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 0
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH0    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH0_M  (AHB_DMA_OUTFIFO_CNT_CH0_V << AHB_DMA_OUTFIFO_CNT_CH0_S)
+#define AHB_DMA_OUTFIFO_CNT_CH0_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH0_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S  26
+
+/** AHB_DMA_OUT_PUSH_CH0_REG register
+ *  Push control register of TX channel 0
+ */
+#define AHB_DMA_OUT_PUSH_CH0_REG (DR_REG_AHB_DMA_BASE + 0xdc)
+/** AHB_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH0    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH0_M  (AHB_DMA_OUTFIFO_WDATA_CH0_V << AHB_DMA_OUTFIFO_WDATA_CH0_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH0_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH0_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH0    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH0_M  (AHB_DMA_OUTFIFO_PUSH_CH0_V << AHB_DMA_OUTFIFO_PUSH_CH0_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH0_S  9
+
+/** AHB_DMA_OUT_LINK_CH0_REG register
+ *  Push control register of TX channel 0
+ */
+#define AHB_DMA_OUT_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe0)
+/** AHB_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 0 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH0    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH0_M  (AHB_DMA_OUTLINK_STOP_CH0_V << AHB_DMA_OUTLINK_STOP_CH0_S)
+#define AHB_DMA_OUTLINK_STOP_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH0_S  0
+/** AHB_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 0 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH0    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH0_M  (AHB_DMA_OUTLINK_START_CH0_V << AHB_DMA_OUTLINK_START_CH0_S)
+#define AHB_DMA_OUTLINK_START_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH0_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 0 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH0    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH0_M  (AHB_DMA_OUTLINK_RESTART_CH0_V << AHB_DMA_OUTLINK_RESTART_CH0_S)
+#define AHB_DMA_OUTLINK_RESTART_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH0_S  2
+/** AHB_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH0    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH0_M  (AHB_DMA_OUTLINK_PARK_CH0_V << AHB_DMA_OUTLINK_PARK_CH0_S)
+#define AHB_DMA_OUTLINK_PARK_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH0_S  3
+
+/** AHB_DMA_OUT_STATE_CH0_REG register
+ *  Transmit status of TX channel 0
+ */
+#define AHB_DMA_OUT_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe4)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH0    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH0_M  (AHB_DMA_OUT_DSCR_STATE_CH0_V << AHB_DMA_OUT_DSCR_STATE_CH0_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH0_S  18
+/** AHB_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH0    0x00000007U
+#define AHB_DMA_OUT_STATE_CH0_M  (AHB_DMA_OUT_STATE_CH0_V << AHB_DMA_OUT_STATE_CH0_S)
+#define AHB_DMA_OUT_STATE_CH0_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH0_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 0
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xe8)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_DES_ADDR_CH0_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 0
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xec)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_DSCR_CH0_REG register
+ *  Current transmit descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf0)
+/** AHB_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH0_M  (AHB_DMA_OUTLINK_DSCR_CH0_V << AHB_DMA_OUTLINK_DSCR_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH0_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH0_REG register
+ *  The last transmit descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf4)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH0_V << AHB_DMA_OUTLINK_DSCR_BF0_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH0_REG register
+ *  The second-to-last transmit descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0xf8)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH0_V << AHB_DMA_OUTLINK_DSCR_BF1_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** AHB_DMA_OUT_PRI_CH0_REG register
+ *  Priority register of TX channel 0
+ */
+#define AHB_DMA_OUT_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0xfc)
+/** AHB_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 0.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_TX_PRI_CH0    0x0000000FU
+#define AHB_DMA_TX_PRI_CH0_M  (AHB_DMA_TX_PRI_CH0_V << AHB_DMA_TX_PRI_CH0_S)
+#define AHB_DMA_TX_PRI_CH0_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH0_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH0_REG register
+ *  Peripheral selection register of TX channel 0
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0x100)
+/** AHB_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 0.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH0    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH0_M  (AHB_DMA_PERI_OUT_SEL_CH0_V << AHB_DMA_PERI_OUT_SEL_CH0_S)
+#define AHB_DMA_PERI_OUT_SEL_CH0_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH0_S  0
+
+/** AHB_DMA_IN_CONF0_CH1_REG register
+ *  Configuration register 0 of RX channel 1
+ */
+#define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x130)
+/** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 1 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH1    (BIT(0))
+#define AHB_DMA_IN_RST_CH1_M  (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S)
+#define AHB_DMA_IN_RST_CH1_V  0x00000001U
+#define AHB_DMA_IN_RST_CH1_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH1    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH1_M  (AHB_DMA_IN_LOOP_TEST_CH1_V << AHB_DMA_IN_LOOP_TEST_CH1_S)
+#define AHB_DMA_IN_LOOP_TEST_CH1_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH1_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 1 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH1    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH1_M  (AHB_DMA_INDSCR_BURST_EN_CH1_V << AHB_DMA_INDSCR_BURST_EN_CH1_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH1_S  2
+/** AHB_DMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 1 receiving data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_IN_DATA_BURST_EN_CH1    (BIT(3))
+#define AHB_DMA_IN_DATA_BURST_EN_CH1_M  (AHB_DMA_IN_DATA_BURST_EN_CH1_V << AHB_DMA_IN_DATA_BURST_EN_CH1_S)
+#define AHB_DMA_IN_DATA_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_IN_DATA_BURST_EN_CH1_S  3
+/** AHB_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH1    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH1_M  (AHB_DMA_MEM_TRANS_EN_CH1_V << AHB_DMA_MEM_TRANS_EN_CH1_S)
+#define AHB_DMA_MEM_TRANS_EN_CH1_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH1_S  4
+/** AHB_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH1    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH1_M  (AHB_DMA_IN_ETM_EN_CH1_V << AHB_DMA_IN_ETM_EN_CH1_S)
+#define AHB_DMA_IN_ETM_EN_CH1_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH1_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 1;
+ *  Configures max burst size for Rx channel1.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S  6
+
+/** AHB_DMA_IN_CONF1_CH1_REG register
+ *  Configuration register 1 of RX channel 1
+ */
+#define AHB_DMA_IN_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x134)
+/** AHB_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH1    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH1_M  (AHB_DMA_IN_CHECK_OWNER_CH1_V << AHB_DMA_IN_CHECK_OWNER_CH1_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH1_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH1_REG register
+ *  Receive FIFO status of RX channel 1
+ */
+#define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x138)
+/** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH1    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH1_M  (AHB_DMA_INFIFO_FULL_CH1_V << AHB_DMA_INFIFO_FULL_CH1_S)
+#define AHB_DMA_INFIFO_FULL_CH1_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH1_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH1    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH1_M  (AHB_DMA_INFIFO_EMPTY_CH1_V << AHB_DMA_INFIFO_EMPTY_CH1_S)
+#define AHB_DMA_INFIFO_EMPTY_CH1_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH1_S  1
+/** AHB_DMA_INFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 1
+ */
+#define AHB_DMA_INFIFO_CNT_CH1    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH1_M  (AHB_DMA_INFIFO_CNT_CH1_V << AHB_DMA_INFIFO_CNT_CH1_S)
+#define AHB_DMA_INFIFO_CNT_CH1_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH1_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH1    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH1_M  (AHB_DMA_IN_BUF_HUNGRY_CH1_V << AHB_DMA_IN_BUF_HUNGRY_CH1_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH1_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH1_S  27
+
+/** AHB_DMA_IN_POP_CH1_REG register
+ *  Receive FIFO status of RX channel 1
+ */
+#define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x13c)
+/** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH1    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH1_M  (AHB_DMA_INFIFO_RDATA_CH1_V << AHB_DMA_INFIFO_RDATA_CH1_S)
+#define AHB_DMA_INFIFO_RDATA_CH1_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH1_S  0
+/** AHB_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH1    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH1_M  (AHB_DMA_INFIFO_POP_CH1_V << AHB_DMA_INFIFO_POP_CH1_S)
+#define AHB_DMA_INFIFO_POP_CH1_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH1_S  12
+
+/** AHB_DMA_IN_LINK_CH1_REG register
+ *  Receive FIFO status of RX channel 1
+ */
+#define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x140)
+/** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ *  .
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH1    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH1_M  (AHB_DMA_INLINK_AUTO_RET_CH1_V << AHB_DMA_INLINK_AUTO_RET_CH1_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH1_S  0
+/** AHB_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 1 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH1    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH1_M  (AHB_DMA_INLINK_STOP_CH1_V << AHB_DMA_INLINK_STOP_CH1_S)
+#define AHB_DMA_INLINK_STOP_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH1_S  1
+/** AHB_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 1 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH1    (BIT(2))
+#define AHB_DMA_INLINK_START_CH1_M  (AHB_DMA_INLINK_START_CH1_V << AHB_DMA_INLINK_START_CH1_S)
+#define AHB_DMA_INLINK_START_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH1_S  2
+/** AHB_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 1 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH1    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH1_M  (AHB_DMA_INLINK_RESTART_CH1_V << AHB_DMA_INLINK_RESTART_CH1_S)
+#define AHB_DMA_INLINK_RESTART_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH1_S  3
+/** AHB_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH1    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH1_M  (AHB_DMA_INLINK_PARK_CH1_V << AHB_DMA_INLINK_PARK_CH1_S)
+#define AHB_DMA_INLINK_PARK_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH1_S  4
+
+/** AHB_DMA_IN_STATE_CH1_REG register
+ *  Receive status of RX channel 1
+ */
+#define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x144)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1_M  (AHB_DMA_INLINK_DSCR_ADDR_CH1_V << AHB_DMA_INLINK_DSCR_ADDR_CH1_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH1    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH1_M  (AHB_DMA_IN_DSCR_STATE_CH1_V << AHB_DMA_IN_DSCR_STATE_CH1_S)
+#define AHB_DMA_IN_DSCR_STATE_CH1_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH1_S  18
+/** AHB_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_IN_STATE_CH1    0x00000007U
+#define AHB_DMA_IN_STATE_CH1_M  (AHB_DMA_IN_STATE_CH1_V << AHB_DMA_IN_STATE_CH1_S)
+#define AHB_DMA_IN_STATE_CH1_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH1_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 1
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x148)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Receive descriptor address when errors occur of RX channel 1
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14c)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_DSCR_CH1_REG register
+ *  Current receive descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x150)
+/** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH1_M  (AHB_DMA_INLINK_DSCR_CH1_V << AHB_DMA_INLINK_DSCR_CH1_S)
+#define AHB_DMA_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH1_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH1_REG register
+ *  The last receive descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x154)
+/** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH1_M  (AHB_DMA_INLINK_DSCR_BF0_CH1_V << AHB_DMA_INLINK_DSCR_BF0_CH1_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH1_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH1_REG register
+ *  The second-to-last receive descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x158)
+/** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH1_M  (AHB_DMA_INLINK_DSCR_BF1_CH1_V << AHB_DMA_INLINK_DSCR_BF1_CH1_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH1_S  0
+
+/** AHB_DMA_IN_PRI_CH1_REG register
+ *  Priority register of RX channel 1
+ */
+#define AHB_DMA_IN_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x15c)
+/** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 1.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_RX_PRI_CH1    0x0000000FU
+#define AHB_DMA_RX_PRI_CH1_M  (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S)
+#define AHB_DMA_RX_PRI_CH1_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH1_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH1_REG register
+ *  Peripheral selection register of RX channel 1
+ */
+#define AHB_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x160)
+/** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 1.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_IN_SEL_CH1    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH1_M  (AHB_DMA_PERI_IN_SEL_CH1_V << AHB_DMA_PERI_IN_SEL_CH1_S)
+#define AHB_DMA_PERI_IN_SEL_CH1_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH1_S  0
+
+/** AHB_DMA_OUT_CONF0_CH1_REG register
+ *  Configuration register 0 of TX channel 1
+ */
+#define AHB_DMA_OUT_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x190)
+/** AHB_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH1    (BIT(0))
+#define AHB_DMA_OUT_RST_CH1_M  (AHB_DMA_OUT_RST_CH1_V << AHB_DMA_OUT_RST_CH1_S)
+#define AHB_DMA_OUT_RST_CH1_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH1_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH1    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH1_M  (AHB_DMA_OUT_LOOP_TEST_CH1_V << AHB_DMA_OUT_LOOP_TEST_CH1_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH1_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1_M  (AHB_DMA_OUT_AUTO_WRBACK_CH1_V << AHB_DMA_OUT_AUTO_WRBACK_CH1_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 1 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 1 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH1    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH1_M  (AHB_DMA_OUT_EOF_MODE_CH1_V << AHB_DMA_OUT_EOF_MODE_CH1_S)
+#define AHB_DMA_OUT_EOF_MODE_CH1_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH1_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 1 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1_M  (AHB_DMA_OUTDSCR_BURST_EN_CH1_V << AHB_DMA_OUTDSCR_BURST_EN_CH1_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1_S  4
+/** AHB_DMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_OUT_DATA_BURST_EN_CH1    (BIT(5))
+#define AHB_DMA_OUT_DATA_BURST_EN_CH1_M  (AHB_DMA_OUT_DATA_BURST_EN_CH1_V << AHB_DMA_OUT_DATA_BURST_EN_CH1_S)
+#define AHB_DMA_OUT_DATA_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_OUT_DATA_BURST_EN_CH1_S  5
+/** AHB_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH1    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH1_M  (AHB_DMA_OUT_ETM_EN_CH1_V << AHB_DMA_OUT_ETM_EN_CH1_S)
+#define AHB_DMA_OUT_ETM_EN_CH1_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH1_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 1;
+ *  Configures max burst size for TX channel1.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S  8
+
+/** AHB_DMA_OUT_CONF1_CH1_REG register
+ *  Configuration register 1 of TX channel 1
+ */
+#define AHB_DMA_OUT_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x194)
+/** AHB_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH1    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH1_M  (AHB_DMA_OUT_CHECK_OWNER_CH1_V << AHB_DMA_OUT_CHECK_OWNER_CH1_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH1_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH1_REG register
+ *  Receive FIFO status of RX channel 1
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x198)
+/** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH1    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH1_M  (AHB_DMA_OUTFIFO_FULL_CH1_V << AHB_DMA_OUTFIFO_FULL_CH1_S)
+#define AHB_DMA_OUTFIFO_FULL_CH1_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH1_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH1    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH1_M  (AHB_DMA_OUTFIFO_EMPTY_CH1_V << AHB_DMA_OUTFIFO_EMPTY_CH1_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH1_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH1_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 1
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH1    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH1_M  (AHB_DMA_OUTFIFO_CNT_CH1_V << AHB_DMA_OUTFIFO_CNT_CH1_S)
+#define AHB_DMA_OUTFIFO_CNT_CH1_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH1_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S  26
+
+/** AHB_DMA_OUT_PUSH_CH1_REG register
+ *  Push control register of TX channel 1
+ */
+#define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x19c)
+/** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH1    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH1_M  (AHB_DMA_OUTFIFO_WDATA_CH1_V << AHB_DMA_OUTFIFO_WDATA_CH1_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH1_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH1_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH1    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH1_M  (AHB_DMA_OUTFIFO_PUSH_CH1_V << AHB_DMA_OUTFIFO_PUSH_CH1_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH1_S  9
+
+/** AHB_DMA_OUT_LINK_CH1_REG register
+ *  Push control register of TX channel 1
+ */
+#define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a0)
+/** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 1 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH1    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH1_M  (AHB_DMA_OUTLINK_STOP_CH1_V << AHB_DMA_OUTLINK_STOP_CH1_S)
+#define AHB_DMA_OUTLINK_STOP_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH1_S  0
+/** AHB_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 1 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH1    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH1_M  (AHB_DMA_OUTLINK_START_CH1_V << AHB_DMA_OUTLINK_START_CH1_S)
+#define AHB_DMA_OUTLINK_START_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH1_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 1 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH1    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH1_M  (AHB_DMA_OUTLINK_RESTART_CH1_V << AHB_DMA_OUTLINK_RESTART_CH1_S)
+#define AHB_DMA_OUTLINK_RESTART_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH1_S  2
+/** AHB_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH1    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH1_M  (AHB_DMA_OUTLINK_PARK_CH1_V << AHB_DMA_OUTLINK_PARK_CH1_S)
+#define AHB_DMA_OUTLINK_PARK_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH1_S  3
+
+/** AHB_DMA_OUT_STATE_CH1_REG register
+ *  Transmit status of TX channel 1
+ */
+#define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a4)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH1    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH1_M  (AHB_DMA_OUT_DSCR_STATE_CH1_V << AHB_DMA_OUT_DSCR_STATE_CH1_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH1_S  18
+/** AHB_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH1    0x00000007U
+#define AHB_DMA_OUT_STATE_CH1_M  (AHB_DMA_OUT_STATE_CH1_V << AHB_DMA_OUT_STATE_CH1_S)
+#define AHB_DMA_OUT_STATE_CH1_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH1_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 1
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1a8)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_DES_ADDR_CH1_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 1
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1ac)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_DSCR_CH1_REG register
+ *  Current transmit descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b0)
+/** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH1_M  (AHB_DMA_OUTLINK_DSCR_CH1_V << AHB_DMA_OUTLINK_DSCR_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH1_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH1_REG register
+ *  The last transmit descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b4)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH1_V << AHB_DMA_OUTLINK_DSCR_BF0_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH1_REG register
+ *  The second-to-last transmit descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1b8)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH1_V << AHB_DMA_OUTLINK_DSCR_BF1_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** AHB_DMA_OUT_PRI_CH1_REG register
+ *  Priority register of TX channel 1
+ */
+#define AHB_DMA_OUT_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1bc)
+/** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 1.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_TX_PRI_CH1    0x0000000FU
+#define AHB_DMA_TX_PRI_CH1_M  (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S)
+#define AHB_DMA_TX_PRI_CH1_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH1_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH1_REG register
+ *  Peripheral selection register of TX channel 1
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c0)
+/** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 1.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH1    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH1_M  (AHB_DMA_PERI_OUT_SEL_CH1_V << AHB_DMA_PERI_OUT_SEL_CH1_S)
+#define AHB_DMA_PERI_OUT_SEL_CH1_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH1_S  0
+
+/** AHB_DMA_IN_CONF0_CH2_REG register
+ *  Configuration register 0 of RX channel 2
+ */
+#define AHB_DMA_IN_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f0)
+/** AHB_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 2 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH2    (BIT(0))
+#define AHB_DMA_IN_RST_CH2_M  (AHB_DMA_IN_RST_CH2_V << AHB_DMA_IN_RST_CH2_S)
+#define AHB_DMA_IN_RST_CH2_V  0x00000001U
+#define AHB_DMA_IN_RST_CH2_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH2    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH2_M  (AHB_DMA_IN_LOOP_TEST_CH2_V << AHB_DMA_IN_LOOP_TEST_CH2_S)
+#define AHB_DMA_IN_LOOP_TEST_CH2_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH2_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 2 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH2    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH2_M  (AHB_DMA_INDSCR_BURST_EN_CH2_V << AHB_DMA_INDSCR_BURST_EN_CH2_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH2_S  2
+/** AHB_DMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable INCR4 burst transfer for Rx channel 2 receiving data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_IN_DATA_BURST_EN_CH2    (BIT(3))
+#define AHB_DMA_IN_DATA_BURST_EN_CH2_M  (AHB_DMA_IN_DATA_BURST_EN_CH2_V << AHB_DMA_IN_DATA_BURST_EN_CH2_S)
+#define AHB_DMA_IN_DATA_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_IN_DATA_BURST_EN_CH2_S  3
+/** AHB_DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH2    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH2_M  (AHB_DMA_MEM_TRANS_EN_CH2_V << AHB_DMA_MEM_TRANS_EN_CH2_S)
+#define AHB_DMA_MEM_TRANS_EN_CH2_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH2_S  4
+/** AHB_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH2    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH2_M  (AHB_DMA_IN_ETM_EN_CH2_V << AHB_DMA_IN_ETM_EN_CH2_S)
+#define AHB_DMA_IN_ETM_EN_CH2_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH2_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [7:6]; default: 1;
+ *  Configures max burst size for Rx channel2.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S  6
+
+/** AHB_DMA_IN_CONF1_CH2_REG register
+ *  Configuration register 1 of RX channel 2
+ */
+#define AHB_DMA_IN_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f4)
+/** AHB_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH2    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH2_M  (AHB_DMA_IN_CHECK_OWNER_CH2_V << AHB_DMA_IN_CHECK_OWNER_CH2_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH2_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH2_REG register
+ *  Receive FIFO status of RX channel 2
+ */
+#define AHB_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1f8)
+/** AHB_DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH2    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH2_M  (AHB_DMA_INFIFO_FULL_CH2_V << AHB_DMA_INFIFO_FULL_CH2_S)
+#define AHB_DMA_INFIFO_FULL_CH2_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH2_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH2    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH2_M  (AHB_DMA_INFIFO_EMPTY_CH2_V << AHB_DMA_INFIFO_EMPTY_CH2_S)
+#define AHB_DMA_INFIFO_EMPTY_CH2_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH2_S  1
+/** AHB_DMA_INFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 2
+ */
+#define AHB_DMA_INFIFO_CNT_CH2    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH2_M  (AHB_DMA_INFIFO_CNT_CH2_V << AHB_DMA_INFIFO_CNT_CH2_S)
+#define AHB_DMA_INFIFO_CNT_CH2_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH2_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH2    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH2_M  (AHB_DMA_IN_BUF_HUNGRY_CH2_V << AHB_DMA_IN_BUF_HUNGRY_CH2_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH2_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH2_S  27
+
+/** AHB_DMA_IN_POP_CH2_REG register
+ *  Receive FIFO status of RX channel 2
+ */
+#define AHB_DMA_IN_POP_CH2_REG (DR_REG_AHB_DMA_BASE + 0x1fc)
+/** AHB_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH2    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH2_M  (AHB_DMA_INFIFO_RDATA_CH2_V << AHB_DMA_INFIFO_RDATA_CH2_S)
+#define AHB_DMA_INFIFO_RDATA_CH2_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH2_S  0
+/** AHB_DMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH2    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH2_M  (AHB_DMA_INFIFO_POP_CH2_V << AHB_DMA_INFIFO_POP_CH2_S)
+#define AHB_DMA_INFIFO_POP_CH2_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH2_S  12
+
+/** AHB_DMA_IN_LINK_CH2_REG register
+ *  Receive FIFO status of RX channel 2
+ */
+#define AHB_DMA_IN_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x200)
+/** AHB_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ *  .
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH2    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH2_M  (AHB_DMA_INLINK_AUTO_RET_CH2_V << AHB_DMA_INLINK_AUTO_RET_CH2_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH2_S  0
+/** AHB_DMA_INLINK_STOP_CH2 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 2 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH2    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH2_M  (AHB_DMA_INLINK_STOP_CH2_V << AHB_DMA_INLINK_STOP_CH2_S)
+#define AHB_DMA_INLINK_STOP_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH2_S  1
+/** AHB_DMA_INLINK_START_CH2 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 2 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH2    (BIT(2))
+#define AHB_DMA_INLINK_START_CH2_M  (AHB_DMA_INLINK_START_CH2_V << AHB_DMA_INLINK_START_CH2_S)
+#define AHB_DMA_INLINK_START_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH2_S  2
+/** AHB_DMA_INLINK_RESTART_CH2 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 2 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH2    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH2_M  (AHB_DMA_INLINK_RESTART_CH2_V << AHB_DMA_INLINK_RESTART_CH2_S)
+#define AHB_DMA_INLINK_RESTART_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH2_S  3
+/** AHB_DMA_INLINK_PARK_CH2 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH2    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH2_M  (AHB_DMA_INLINK_PARK_CH2_V << AHB_DMA_INLINK_PARK_CH2_S)
+#define AHB_DMA_INLINK_PARK_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH2_S  4
+
+/** AHB_DMA_IN_STATE_CH2_REG register
+ *  Receive status of RX channel 2
+ */
+#define AHB_DMA_IN_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x204)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2_M  (AHB_DMA_INLINK_DSCR_ADDR_CH2_V << AHB_DMA_INLINK_DSCR_ADDR_CH2_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH2    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH2_M  (AHB_DMA_IN_DSCR_STATE_CH2_V << AHB_DMA_IN_DSCR_STATE_CH2_S)
+#define AHB_DMA_IN_DSCR_STATE_CH2_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH2_S  18
+/** AHB_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_IN_STATE_CH2    0x00000007U
+#define AHB_DMA_IN_STATE_CH2_M  (AHB_DMA_IN_STATE_CH2_V << AHB_DMA_IN_STATE_CH2_S)
+#define AHB_DMA_IN_STATE_CH2_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH2_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 2
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x208)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  Receive descriptor address when errors occur of RX channel 2
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20c)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_IN_DSCR_CH2_REG register
+ *  Current receive descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x210)
+/** AHB_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH2_M  (AHB_DMA_INLINK_DSCR_CH2_V << AHB_DMA_INLINK_DSCR_CH2_S)
+#define AHB_DMA_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH2_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH2_REG register
+ *  The last receive descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x214)
+/** AHB_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH2_M  (AHB_DMA_INLINK_DSCR_BF0_CH2_V << AHB_DMA_INLINK_DSCR_BF0_CH2_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH2_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH2_REG register
+ *  The second-to-last receive descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x218)
+/** AHB_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH2_M  (AHB_DMA_INLINK_DSCR_BF1_CH2_V << AHB_DMA_INLINK_DSCR_BF1_CH2_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH2_S  0
+
+/** AHB_DMA_IN_PRI_CH2_REG register
+ *  Priority register of RX channel 2
+ */
+#define AHB_DMA_IN_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x21c)
+/** AHB_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 2.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_RX_PRI_CH2    0x0000000FU
+#define AHB_DMA_RX_PRI_CH2_M  (AHB_DMA_RX_PRI_CH2_V << AHB_DMA_RX_PRI_CH2_S)
+#define AHB_DMA_RX_PRI_CH2_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH2_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH2_REG register
+ *  Peripheral selection register of RX channel 2
+ */
+#define AHB_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x220)
+/** AHB_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 2.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_IN_SEL_CH2    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH2_M  (AHB_DMA_PERI_IN_SEL_CH2_V << AHB_DMA_PERI_IN_SEL_CH2_S)
+#define AHB_DMA_PERI_IN_SEL_CH2_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH2_S  0
+
+/** AHB_DMA_OUT_CONF0_CH2_REG register
+ *  Configuration register 0 of TX channel 2
+ */
+#define AHB_DMA_OUT_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x250)
+/** AHB_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH2    (BIT(0))
+#define AHB_DMA_OUT_RST_CH2_M  (AHB_DMA_OUT_RST_CH2_V << AHB_DMA_OUT_RST_CH2_S)
+#define AHB_DMA_OUT_RST_CH2_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH2_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH2    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH2_M  (AHB_DMA_OUT_LOOP_TEST_CH2_V << AHB_DMA_OUT_LOOP_TEST_CH2_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH2_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2_M  (AHB_DMA_OUT_AUTO_WRBACK_CH2_V << AHB_DMA_OUT_AUTO_WRBACK_CH2_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 2 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 2 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH2    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH2_M  (AHB_DMA_OUT_EOF_MODE_CH2_V << AHB_DMA_OUT_EOF_MODE_CH2_S)
+#define AHB_DMA_OUT_EOF_MODE_CH2_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH2_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 2 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2_M  (AHB_DMA_OUTDSCR_BURST_EN_CH2_V << AHB_DMA_OUTDSCR_BURST_EN_CH2_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2_S  4
+/** AHB_DMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data
+ *  when accessing internal SRAM.
+ */
+#define AHB_DMA_OUT_DATA_BURST_EN_CH2    (BIT(5))
+#define AHB_DMA_OUT_DATA_BURST_EN_CH2_M  (AHB_DMA_OUT_DATA_BURST_EN_CH2_V << AHB_DMA_OUT_DATA_BURST_EN_CH2_S)
+#define AHB_DMA_OUT_DATA_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_OUT_DATA_BURST_EN_CH2_S  5
+/** AHB_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH2    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH2_M  (AHB_DMA_OUT_ETM_EN_CH2_V << AHB_DMA_OUT_ETM_EN_CH2_S)
+#define AHB_DMA_OUT_ETM_EN_CH2_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH2_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [9:8]; default: 1;
+ *  Configures max burst size for TX channel2.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S  8
+
+/** AHB_DMA_OUT_CONF1_CH2_REG register
+ *  Configuration register 1 of TX channel 2
+ */
+#define AHB_DMA_OUT_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x254)
+/** AHB_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH2    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH2_M  (AHB_DMA_OUT_CHECK_OWNER_CH2_V << AHB_DMA_OUT_CHECK_OWNER_CH2_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH2_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH2_REG register
+ *  Receive FIFO status of RX channel 2
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x258)
+/** AHB_DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH2    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH2_M  (AHB_DMA_OUTFIFO_FULL_CH2_V << AHB_DMA_OUTFIFO_FULL_CH2_S)
+#define AHB_DMA_OUTFIFO_FULL_CH2_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH2_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH2    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH2_M  (AHB_DMA_OUTFIFO_EMPTY_CH2_V << AHB_DMA_OUTFIFO_EMPTY_CH2_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH2_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH2_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 2
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH2    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH2_M  (AHB_DMA_OUTFIFO_CNT_CH2_V << AHB_DMA_OUTFIFO_CNT_CH2_S)
+#define AHB_DMA_OUTFIFO_CNT_CH2_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH2_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S  26
+
+/** AHB_DMA_OUT_PUSH_CH2_REG register
+ *  Push control register of TX channel 2
+ */
+#define AHB_DMA_OUT_PUSH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x25c)
+/** AHB_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH2    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH2_M  (AHB_DMA_OUTFIFO_WDATA_CH2_V << AHB_DMA_OUTFIFO_WDATA_CH2_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH2_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH2_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH2    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH2_M  (AHB_DMA_OUTFIFO_PUSH_CH2_V << AHB_DMA_OUTFIFO_PUSH_CH2_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH2_S  9
+
+/** AHB_DMA_OUT_LINK_CH2_REG register
+ *  Push control register of TX channel 2
+ */
+#define AHB_DMA_OUT_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x260)
+/** AHB_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 2 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH2    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH2_M  (AHB_DMA_OUTLINK_STOP_CH2_V << AHB_DMA_OUTLINK_STOP_CH2_S)
+#define AHB_DMA_OUTLINK_STOP_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH2_S  0
+/** AHB_DMA_OUTLINK_START_CH2 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 2 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH2    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH2_M  (AHB_DMA_OUTLINK_START_CH2_V << AHB_DMA_OUTLINK_START_CH2_S)
+#define AHB_DMA_OUTLINK_START_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH2_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH2 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 2 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH2    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH2_M  (AHB_DMA_OUTLINK_RESTART_CH2_V << AHB_DMA_OUTLINK_RESTART_CH2_S)
+#define AHB_DMA_OUTLINK_RESTART_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH2_S  2
+/** AHB_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH2    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH2_M  (AHB_DMA_OUTLINK_PARK_CH2_V << AHB_DMA_OUTLINK_PARK_CH2_S)
+#define AHB_DMA_OUTLINK_PARK_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH2_S  3
+
+/** AHB_DMA_OUT_STATE_CH2_REG register
+ *  Transmit status of TX channel 2
+ */
+#define AHB_DMA_OUT_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x264)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH2    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH2_M  (AHB_DMA_OUT_DSCR_STATE_CH2_V << AHB_DMA_OUT_DSCR_STATE_CH2_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH2_S  18
+/** AHB_DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH2    0x00000007U
+#define AHB_DMA_OUT_STATE_CH2_M  (AHB_DMA_OUT_STATE_CH2_V << AHB_DMA_OUT_STATE_CH2_S)
+#define AHB_DMA_OUT_STATE_CH2_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH2_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 2
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x268)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_DES_ADDR_CH2_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 2
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x26c)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_DSCR_CH2_REG register
+ *  Current transmit descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x270)
+/** AHB_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH2_M  (AHB_DMA_OUTLINK_DSCR_CH2_V << AHB_DMA_OUTLINK_DSCR_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH2_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH2_REG register
+ *  The last transmit descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x274)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH2_V << AHB_DMA_OUTLINK_DSCR_BF0_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH2_REG register
+ *  The second-to-last transmit descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x278)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH2_V << AHB_DMA_OUTLINK_DSCR_BF1_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** AHB_DMA_OUT_PRI_CH2_REG register
+ *  Priority register of TX channel 2
+ */
+#define AHB_DMA_OUT_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x27c)
+/** AHB_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 2.The larger of the value, the higher of the
+ *  priority..
+ */
+#define AHB_DMA_TX_PRI_CH2    0x0000000FU
+#define AHB_DMA_TX_PRI_CH2_M  (AHB_DMA_TX_PRI_CH2_V << AHB_DMA_TX_PRI_CH2_S)
+#define AHB_DMA_TX_PRI_CH2_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH2_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH2_REG register
+ *  Peripheral selection register of TX channel 2
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x280)
+/** AHB_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 2.
+ *  0: I3C
+ *  1: Dummy
+ *  2: UHCI0
+ *  3: I2S0
+ *  4: I2S1
+ *  5: I2S2
+ *  6: Dummy
+ *  7: Dummy
+ *  8: ADC_DAC
+ *  9: Dummy
+ *  10: RMT
+ *  11~15: Dummy
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH2    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH2_M  (AHB_DMA_PERI_OUT_SEL_CH2_V << AHB_DMA_PERI_OUT_SEL_CH2_S)
+#define AHB_DMA_PERI_OUT_SEL_CH2_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH2_S  0
+
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2bc)
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_M  (AHB_DMA_OUT_CRC_INIT_DATA_CH0_V << AHB_DMA_OUT_CRC_INIT_DATA_CH0_S)
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH0_S  0
+
+/** AHB_DMA_TX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2c0)
+/** AHB_DMA_TX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH0    0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH0_M  (AHB_DMA_TX_CRC_WIDTH_CH0_V << AHB_DMA_TX_CRC_WIDTH_CH0_S)
+#define AHB_DMA_TX_CRC_WIDTH_CH0_V  0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH0_S  0
+/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_M  (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_S)
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AHB_DMA_OUT_CRC_CLEAR_CH0_REG register
+ *  This register is used to clear ch0 crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2c4)
+/** AHB_DMA_OUT_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH0    (BIT(0))
+#define AHB_DMA_OUT_CRC_CLEAR_CH0_M  (AHB_DMA_OUT_CRC_CLEAR_CH0_V << AHB_DMA_OUT_CRC_CLEAR_CH0_S)
+#define AHB_DMA_OUT_CRC_CLEAR_CH0_V  0x00000001U
+#define AHB_DMA_OUT_CRC_CLEAR_CH0_S  0
+
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2c8)
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_M  (AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_V << AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_S)
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH0_S  0
+
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2cc)
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0_M  (AHB_DMA_TX_CRC_EN_WR_DATA_CH0_V << AHB_DMA_TX_CRC_EN_WR_DATA_CH0_S)
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AHB_DMA_TX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2d0)
+/** AHB_DMA_TX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0_M  (AHB_DMA_TX_CRC_EN_ADDR_CH0_V << AHB_DMA_TX_CRC_EN_ADDR_CH0_S)
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH0_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2d4)
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0    0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_M  (AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V << AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V  0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2d8)
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_M  (AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_V << AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_S)
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG register
+ *  TX channel 0 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2dc)
+/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel0
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0    0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_M  (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S)
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_V  0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH0_S  0
+
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG register
+ *  TX channel 0 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x2e0)
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_M  (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH0_S  0
+
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2e4)
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_M  (AHB_DMA_OUT_CRC_INIT_DATA_CH1_V << AHB_DMA_OUT_CRC_INIT_DATA_CH1_S)
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH1_S  0
+
+/** AHB_DMA_TX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2e8)
+/** AHB_DMA_TX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH1    0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH1_M  (AHB_DMA_TX_CRC_WIDTH_CH1_V << AHB_DMA_TX_CRC_WIDTH_CH1_S)
+#define AHB_DMA_TX_CRC_WIDTH_CH1_V  0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH1_S  0
+/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_M  (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_S)
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AHB_DMA_OUT_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2ec)
+/** AHB_DMA_OUT_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH1    (BIT(0))
+#define AHB_DMA_OUT_CRC_CLEAR_CH1_M  (AHB_DMA_OUT_CRC_CLEAR_CH1_V << AHB_DMA_OUT_CRC_CLEAR_CH1_S)
+#define AHB_DMA_OUT_CRC_CLEAR_CH1_V  0x00000001U
+#define AHB_DMA_OUT_CRC_CLEAR_CH1_S  0
+
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2f0)
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_M  (AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_V << AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_S)
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH1_S  0
+
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2f4)
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1_M  (AHB_DMA_TX_CRC_EN_WR_DATA_CH1_V << AHB_DMA_TX_CRC_EN_WR_DATA_CH1_S)
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AHB_DMA_TX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2f8)
+/** AHB_DMA_TX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1_M  (AHB_DMA_TX_CRC_EN_ADDR_CH1_V << AHB_DMA_TX_CRC_EN_ADDR_CH1_S)
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH1_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2fc)
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1    0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_M  (AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V << AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V  0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x300)
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_M  (AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_V << AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_S)
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG register
+ *  TX channel 1 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x304)
+/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel1
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1    0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_M  (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S)
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_V  0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH1_S  0
+
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG register
+ *  TX channel 1 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x308)
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_M  (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH1_S  0
+
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x30c)
+/** AHB_DMA_OUT_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_M  (AHB_DMA_OUT_CRC_INIT_DATA_CH2_V << AHB_DMA_OUT_CRC_INIT_DATA_CH2_S)
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_INIT_DATA_CH2_S  0
+
+/** AHB_DMA_TX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig tx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x310)
+/** AHB_DMA_TX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_WIDTH_CH2    0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH2_M  (AHB_DMA_TX_CRC_WIDTH_CH2_V << AHB_DMA_TX_CRC_WIDTH_CH2_S)
+#define AHB_DMA_TX_CRC_WIDTH_CH2_V  0x00000003U
+#define AHB_DMA_TX_CRC_WIDTH_CH2_S  0
+/** AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_M  (AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_V << AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_S)
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AHB_DMA_TX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AHB_DMA_OUT_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x314)
+/** AHB_DMA_OUT_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AHB_DMA_OUT_CRC_CLEAR_CH2    (BIT(0))
+#define AHB_DMA_OUT_CRC_CLEAR_CH2_M  (AHB_DMA_OUT_CRC_CLEAR_CH2_V << AHB_DMA_OUT_CRC_CLEAR_CH2_S)
+#define AHB_DMA_OUT_CRC_CLEAR_CH2_V  0x00000001U
+#define AHB_DMA_OUT_CRC_CLEAR_CH2_S  0
+
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_REG (DR_REG_AHB_DMA_BASE + 0x318)
+/** AHB_DMA_OUT_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_M  (AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_V << AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_S)
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_CRC_FINAL_RESULT_CH2_S  0
+
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x31c)
+/** AHB_DMA_TX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2_M  (AHB_DMA_TX_CRC_EN_WR_DATA_CH2_V << AHB_DMA_TX_CRC_EN_WR_DATA_CH2_S)
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AHB_DMA_TX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x320)
+/** AHB_DMA_TX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2_M  (AHB_DMA_TX_CRC_EN_ADDR_CH2_V << AHB_DMA_TX_CRC_EN_ADDR_CH2_S)
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_EN_ADDR_CH2_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x324)
+/** AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2    0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_M  (AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V << AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V  0x000000FFU
+#define AHB_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x328)
+/** AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_M  (AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_V << AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_S)
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_TX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG register
+ *  TX channel 2 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x32c)
+/** AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel2
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2    0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_M  (AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V << AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S)
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_V  0x0000000FU
+#define AHB_DMA_TX_ARB_WEIGHT_VALUE_CH2_S  0
+
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH2_REG register
+ *  TX channel 2 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x330)
+/** AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_M  (AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V << AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGHT_OPT_DIS_CH2_S  0
+
+/** AHB_DMA_IN_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x334)
+/** AHB_DMA_IN_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0_M  (AHB_DMA_IN_CRC_INIT_DATA_CH0_V << AHB_DMA_IN_CRC_INIT_DATA_CH0_S)
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH0_S  0
+
+/** AHB_DMA_RX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x338)
+/** AHB_DMA_RX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH0    0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH0_M  (AHB_DMA_RX_CRC_WIDTH_CH0_V << AHB_DMA_RX_CRC_WIDTH_CH0_S)
+#define AHB_DMA_RX_CRC_WIDTH_CH0_V  0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH0_S  0
+/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_M  (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_S)
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AHB_DMA_IN_CRC_CLEAR_CH0_REG register
+ *  This register is used to clear ch0 crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x33c)
+/** AHB_DMA_IN_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH0    (BIT(0))
+#define AHB_DMA_IN_CRC_CLEAR_CH0_M  (AHB_DMA_IN_CRC_CLEAR_CH0_V << AHB_DMA_IN_CRC_CLEAR_CH0_S)
+#define AHB_DMA_IN_CRC_CLEAR_CH0_V  0x00000001U
+#define AHB_DMA_IN_CRC_CLEAR_CH0_S  0
+
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0_REG (DR_REG_AHB_DMA_BASE + 0x340)
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0_M  (AHB_DMA_IN_CRC_FINAL_RESULT_CH0_V << AHB_DMA_IN_CRC_FINAL_RESULT_CH0_S)
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH0_S  0
+
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x344)
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0_M  (AHB_DMA_RX_CRC_EN_WR_DATA_CH0_V << AHB_DMA_RX_CRC_EN_WR_DATA_CH0_S)
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AHB_DMA_RX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x348)
+/** AHB_DMA_RX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0_M  (AHB_DMA_RX_CRC_EN_ADDR_CH0_V << AHB_DMA_RX_CRC_EN_ADDR_CH0_S)
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH0_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x34c)
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0    0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_M  (AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V << AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V  0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x350)
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_M  (AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_V << AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_S)
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG register
+ *  RX channel 0 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x354)
+/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel0
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0    0x0000000FU
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_M  (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S)
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_V  0x0000000FU
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH0_S  0
+
+/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG register
+ *  RX channel 0 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x358)
+/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_M  (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH0_S  0
+
+/** AHB_DMA_IN_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x35c)
+/** AHB_DMA_IN_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1_M  (AHB_DMA_IN_CRC_INIT_DATA_CH1_V << AHB_DMA_IN_CRC_INIT_DATA_CH1_S)
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH1_S  0
+
+/** AHB_DMA_RX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig rx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x360)
+/** AHB_DMA_RX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH1    0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH1_M  (AHB_DMA_RX_CRC_WIDTH_CH1_V << AHB_DMA_RX_CRC_WIDTH_CH1_S)
+#define AHB_DMA_RX_CRC_WIDTH_CH1_V  0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH1_S  0
+/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_M  (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_S)
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AHB_DMA_IN_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x364)
+/** AHB_DMA_IN_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH1    (BIT(0))
+#define AHB_DMA_IN_CRC_CLEAR_CH1_M  (AHB_DMA_IN_CRC_CLEAR_CH1_V << AHB_DMA_IN_CRC_CLEAR_CH1_S)
+#define AHB_DMA_IN_CRC_CLEAR_CH1_V  0x00000001U
+#define AHB_DMA_IN_CRC_CLEAR_CH1_S  0
+
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1_REG (DR_REG_AHB_DMA_BASE + 0x368)
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1_M  (AHB_DMA_IN_CRC_FINAL_RESULT_CH1_V << AHB_DMA_IN_CRC_FINAL_RESULT_CH1_S)
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH1_S  0
+
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x36c)
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1_M  (AHB_DMA_RX_CRC_EN_WR_DATA_CH1_V << AHB_DMA_RX_CRC_EN_WR_DATA_CH1_S)
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AHB_DMA_RX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x370)
+/** AHB_DMA_RX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1_M  (AHB_DMA_RX_CRC_EN_ADDR_CH1_V << AHB_DMA_RX_CRC_EN_ADDR_CH1_S)
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH1_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x374)
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1    0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_M  (AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V << AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V  0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x378)
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_M  (AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_V << AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_S)
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG register
+ *  RX channel 1 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x37c)
+/** AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel1
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1    0x0000000FU
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_M  (AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V << AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S)
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_V  0x0000000FU
+#define AHB_DMA_RX_ARB_WEIGHT_VALUE_CH1_S  0
+
+/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG register
+ *  RX channel 1 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x380)
+/** AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_M  (AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V << AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGHT_OPT_DIS_CH1_S  0
+
+/** AHB_DMA_IN_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x384)
+/** AHB_DMA_IN_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2_M  (AHB_DMA_IN_CRC_INIT_DATA_CH2_V << AHB_DMA_IN_CRC_INIT_DATA_CH2_S)
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_INIT_DATA_CH2_S  0
+
+/** AHB_DMA_RX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig rx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x388)
+/** AHB_DMA_RX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_WIDTH_CH2    0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH2_M  (AHB_DMA_RX_CRC_WIDTH_CH2_V << AHB_DMA_RX_CRC_WIDTH_CH2_S)
+#define AHB_DMA_RX_CRC_WIDTH_CH2_V  0x00000003U
+#define AHB_DMA_RX_CRC_WIDTH_CH2_S  0
+/** AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_M  (AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_V << AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_S)
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AHB_DMA_RX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AHB_DMA_IN_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x38c)
+/** AHB_DMA_IN_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AHB_DMA_IN_CRC_CLEAR_CH2    (BIT(0))
+#define AHB_DMA_IN_CRC_CLEAR_CH2_M  (AHB_DMA_IN_CRC_CLEAR_CH2_V << AHB_DMA_IN_CRC_CLEAR_CH2_S)
+#define AHB_DMA_IN_CRC_CLEAR_CH2_V  0x00000001U
+#define AHB_DMA_IN_CRC_CLEAR_CH2_S  0
+
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2_REG (DR_REG_AHB_DMA_BASE + 0x390)
+/** AHB_DMA_IN_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2_M  (AHB_DMA_IN_CRC_FINAL_RESULT_CH2_V << AHB_DMA_IN_CRC_FINAL_RESULT_CH2_S)
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_CRC_FINAL_RESULT_CH2_S  0
+
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x394)
+/** AHB_DMA_RX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2_M  (AHB_DMA_RX_CRC_EN_WR_DATA_CH2_V << AHB_DMA_RX_CRC_EN_WR_DATA_CH2_S)
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AHB_DMA_RX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x398)
+/** AHB_DMA_RX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2_M  (AHB_DMA_RX_CRC_EN_ADDR_CH2_V << AHB_DMA_RX_CRC_EN_ADDR_CH2_S)
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_EN_ADDR_CH2_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x39c)
+/** AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2    0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_M  (AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V << AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V  0x000000FFU
+#define AHB_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a0)
+/** AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_M  (AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_V << AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_S)
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_RX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG register
+ *  RX channel 2 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a4)
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel2
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_M  (AHB_DMA_RX_CH_ARB_WEIGH_CH2_V << AHB_DMA_RX_CH_ARB_WEIGH_CH2_S)
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_S  0
+
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG register
+ *  RX channel 2 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a8)
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M  (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S  0
+
+/** AHB_DMA_IN_LINK_ADDR_CH0_REG register
+ *  Link list descriptor address configuration of RX channel 0
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3ac)
+/** AHB_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address
+ */
+#define AHB_DMA_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH0_M  (AHB_DMA_INLINK_ADDR_CH0_V << AHB_DMA_INLINK_ADDR_CH0_S)
+#define AHB_DMA_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_LINK_ADDR_CH1_REG register
+ *  Link list descriptor address configuration of RX channel 1
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3b0)
+/** AHB_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address
+ */
+#define AHB_DMA_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH1_M  (AHB_DMA_INLINK_ADDR_CH1_V << AHB_DMA_INLINK_ADDR_CH1_S)
+#define AHB_DMA_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_LINK_ADDR_CH2_REG register
+ *  Link list descriptor address configuration of RX channel 2
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3b4)
+/** AHB_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address
+ */
+#define AHB_DMA_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH2_M  (AHB_DMA_INLINK_ADDR_CH2_V << AHB_DMA_INLINK_ADDR_CH2_S)
+#define AHB_DMA_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_LINK_ADDR_CH0_REG register
+ *  Link list descriptor address configuration of TX channel 0
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x3b8)
+/** AHB_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH0_M  (AHB_DMA_OUTLINK_ADDR_CH0_V << AHB_DMA_OUTLINK_ADDR_CH0_S)
+#define AHB_DMA_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_LINK_ADDR_CH1_REG register
+ *  Link list descriptor address configuration of TX channel 1
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x3bc)
+/** AHB_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH1_M  (AHB_DMA_OUTLINK_ADDR_CH1_V << AHB_DMA_OUTLINK_ADDR_CH1_S)
+#define AHB_DMA_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_LINK_ADDR_CH2_REG register
+ *  Link list descriptor address configuration of TX channel 2
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3c0)
+/** AHB_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH2_M  (AHB_DMA_OUTLINK_ADDR_CH2_V << AHB_DMA_OUTLINK_ADDR_CH2_S)
+#define AHB_DMA_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH2_S  0
+
+/** AHB_DMA_INTR_MEM_START_ADDR_REG register
+ *  Accessible address space start address configuration register
+ */
+#define AHB_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c4)
+/** AHB_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Accessible address space start address configuration register
+ */
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_M  (AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S)
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** AHB_DMA_INTR_MEM_END_ADDR_REG register
+ *  Accessible address space end address configuration register
+ */
+#define AHB_DMA_INTR_MEM_END_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x3c8)
+/** AHB_DMA_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the end address of accessible address space.
+ */
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_M  (AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S)
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** AHB_DMA_ARB_TIMEOUT_TX_REG register
+ *  TX arbitration timeout configuration register
+ */
+#define AHB_DMA_ARB_TIMEOUT_TX_REG (DR_REG_AHB_DMA_BASE + 0x3cc)
+/** AHB_DMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the time slot for TX. Measurement unit: AHB bus clock cycle.
+ */
+#define AHB_DMA_ARB_TIMEOUT_TX    0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_TX_M  (AHB_DMA_ARB_TIMEOUT_TX_V << AHB_DMA_ARB_TIMEOUT_TX_S)
+#define AHB_DMA_ARB_TIMEOUT_TX_V  0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_TX_S  0
+
+/** AHB_DMA_ARB_TIMEOUT_RX_REG register
+ *  RX arbitration timeout configuration register
+ */
+#define AHB_DMA_ARB_TIMEOUT_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d0)
+/** AHB_DMA_ARB_TIMEOUT_RX : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the time slot for RX. Measurement unit: AHB bus clock cycle.
+ */
+#define AHB_DMA_ARB_TIMEOUT_RX    0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_RX_M  (AHB_DMA_ARB_TIMEOUT_RX_V << AHB_DMA_ARB_TIMEOUT_RX_S)
+#define AHB_DMA_ARB_TIMEOUT_RX_V  0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_RX_S  0
+
+/** AHB_DMA_WEIGHT_EN_TX_REG register
+ *  TX weight arbitration enable register
+ */
+#define AHB_DMA_WEIGHT_EN_TX_REG (DR_REG_AHB_DMA_BASE + 0x3d4)
+/** AHB_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable weight arbitration for TX.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_WEIGHT_EN_TX    (BIT(0))
+#define AHB_DMA_WEIGHT_EN_TX_M  (AHB_DMA_WEIGHT_EN_TX_V << AHB_DMA_WEIGHT_EN_TX_S)
+#define AHB_DMA_WEIGHT_EN_TX_V  0x00000001U
+#define AHB_DMA_WEIGHT_EN_TX_S  0
+
+/** AHB_DMA_WEIGHT_EN_RX_REG register
+ *  RX weight arbitration enable register
+ */
+#define AHB_DMA_WEIGHT_EN_RX_REG (DR_REG_AHB_DMA_BASE + 0x3d8)
+/** AHB_DMA_WEIGHT_EN_RX : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable weight arbitration for RX.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_WEIGHT_EN_RX    (BIT(0))
+#define AHB_DMA_WEIGHT_EN_RX_M  (AHB_DMA_WEIGHT_EN_RX_V << AHB_DMA_WEIGHT_EN_RX_S)
+#define AHB_DMA_WEIGHT_EN_RX_V  0x00000001U
+#define AHB_DMA_WEIGHT_EN_RX_S  0
+
+/** AHB_DMA_ARB_TIMEOUT_REG register
+ *  TX arbitration timeout configuration register
+ */
+#define AHB_DMA_ARB_TIMEOUT_REG (DR_REG_AHB_DMA_BASE + 0x3dc)
+/** AHB_DMA_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the time slot. Measurement unit: AHB bus clock cycle.
+ */
+#define AHB_DMA_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_NUM_M  (AHB_DMA_ARB_TIMEOUT_NUM_V << AHB_DMA_ARB_TIMEOUT_NUM_S)
+#define AHB_DMA_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_NUM_S  0
+
+/** AHB_DMA_WEIGHT_EN_REG register
+ *  TX weight arbitration enable register
+ */
+#define AHB_DMA_WEIGHT_EN_REG (DR_REG_AHB_DMA_BASE + 0x400)
+/** AHB_DMA_WEIGHT_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable weight arbitration.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_WEIGHT_EN    (BIT(0))
+#define AHB_DMA_WEIGHT_EN_M  (AHB_DMA_WEIGHT_EN_V << AHB_DMA_WEIGHT_EN_S)
+#define AHB_DMA_WEIGHT_EN_V  0x00000001U
+#define AHB_DMA_WEIGHT_EN_S  0
+
+/** AHB_DMA_MODULE_CLK_EN_REG register
+ *  Module clock force on register
+ */
+#define AHB_DMA_MODULE_CLK_EN_REG (DR_REG_AHB_DMA_BASE + 0x404)
+/** AHB_DMA_AHB_APB_SYNC_CLK_EN : R/W; bitpos: [2:0]; default: 7;
+ *  Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n:
+ *  0 : Not force on ahb_apb_sync n clock
+ *  1 : Force on ahb_apb_sync n clock
+ */
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN    0x00000007U
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN_M  (AHB_DMA_AHB_APB_SYNC_CLK_EN_V << AHB_DMA_AHB_APB_SYNC_CLK_EN_S)
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN_V  0x00000007U
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN_S  0
+/** AHB_DMA_OUT_DSCR_CLK_EN : R/W; bitpos: [5:3]; default: 7;
+ *  Configures whether to force on out_dscr 2~0 module clock. For bit n:
+ *  0 : Not force on out_dscr n clock
+ *  1 : Force on out_dscr n clock
+ */
+#define AHB_DMA_OUT_DSCR_CLK_EN    0x00000007U
+#define AHB_DMA_OUT_DSCR_CLK_EN_M  (AHB_DMA_OUT_DSCR_CLK_EN_V << AHB_DMA_OUT_DSCR_CLK_EN_S)
+#define AHB_DMA_OUT_DSCR_CLK_EN_V  0x00000007U
+#define AHB_DMA_OUT_DSCR_CLK_EN_S  3
+/** AHB_DMA_OUT_CTRL_CLK_EN : R/W; bitpos: [8:6]; default: 7;
+ *  Configures whether to force on out_ctrl 2~0 module clock. For bit n:
+ *  0 : Not force on out_ctrl n clock
+ *  1 : Force on out_ctrl n clock
+ */
+#define AHB_DMA_OUT_CTRL_CLK_EN    0x00000007U
+#define AHB_DMA_OUT_CTRL_CLK_EN_M  (AHB_DMA_OUT_CTRL_CLK_EN_V << AHB_DMA_OUT_CTRL_CLK_EN_S)
+#define AHB_DMA_OUT_CTRL_CLK_EN_V  0x00000007U
+#define AHB_DMA_OUT_CTRL_CLK_EN_S  6
+/** AHB_DMA_IN_DSCR_CLK_EN : R/W; bitpos: [11:9]; default: 7;
+ *  Configures whether to force on in_dscr 2~0 module clock. For bit n:
+ *  0 : Not force on in_dscr n clock
+ *  1 : Force on in_dscr n clock
+ */
+#define AHB_DMA_IN_DSCR_CLK_EN    0x00000007U
+#define AHB_DMA_IN_DSCR_CLK_EN_M  (AHB_DMA_IN_DSCR_CLK_EN_V << AHB_DMA_IN_DSCR_CLK_EN_S)
+#define AHB_DMA_IN_DSCR_CLK_EN_V  0x00000007U
+#define AHB_DMA_IN_DSCR_CLK_EN_S  9
+/** AHB_DMA_IN_CTRL_CLK_EN : R/W; bitpos: [14:12]; default: 7;
+ *  Configures whether to force on in_ctrl 2~0 module clock. For bit n:
+ *  0 : Not force on in_ctrl n clock
+ *  1 : Force on in_ctrl n clock
+ */
+#define AHB_DMA_IN_CTRL_CLK_EN    0x00000007U
+#define AHB_DMA_IN_CTRL_CLK_EN_M  (AHB_DMA_IN_CTRL_CLK_EN_V << AHB_DMA_IN_CTRL_CLK_EN_S)
+#define AHB_DMA_IN_CTRL_CLK_EN_V  0x00000007U
+#define AHB_DMA_IN_CTRL_CLK_EN_S  12
+/** AHB_DMA_CMD_ARB_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether to force on cmd_arb module clock.
+ *  0 : Not force on cmd_arb clock
+ *  1 : Force on cmd_arb clock
+ */
+#define AHB_DMA_CMD_ARB_CLK_EN    (BIT(27))
+#define AHB_DMA_CMD_ARB_CLK_EN_M  (AHB_DMA_CMD_ARB_CLK_EN_V << AHB_DMA_CMD_ARB_CLK_EN_S)
+#define AHB_DMA_CMD_ARB_CLK_EN_V  0x00000001U
+#define AHB_DMA_CMD_ARB_CLK_EN_S  27
+/** AHB_DMA_AHBINF_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether to force on ahbinf module clock.
+ *  0 : Not force on ahbinf clock
+ *  1 : Force on ahbinf clock
+ */
+#define AHB_DMA_AHBINF_CLK_EN    (BIT(28))
+#define AHB_DMA_AHBINF_CLK_EN_M  (AHB_DMA_AHBINF_CLK_EN_V << AHB_DMA_AHBINF_CLK_EN_S)
+#define AHB_DMA_AHBINF_CLK_EN_V  0x00000001U
+#define AHB_DMA_AHBINF_CLK_EN_S  28
+
+/** AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG register
+ *  AHB response error status 0 register
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG (DR_REG_AHB_DMA_BASE + 0x408)
+/** AHB_DMA_AHBINF_RESP_ERR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the AHB response error.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR    0xFFFFFFFFU
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR_M  (AHB_DMA_AHBINF_RESP_ERR_ADDR_V << AHB_DMA_AHBINF_RESP_ERR_ADDR_S)
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR_V  0xFFFFFFFFU
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR_S  0
+
+/** AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG register
+ *  AHB response error status 1 register
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG (DR_REG_AHB_DMA_BASE + 0x40c)
+/** AHB_DMA_AHBINF_RESP_ERR_WR : RO; bitpos: [0]; default: 0;
+ *  Represents the AHB response error is write request.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_WR    (BIT(0))
+#define AHB_DMA_AHBINF_RESP_ERR_WR_M  (AHB_DMA_AHBINF_RESP_ERR_WR_V << AHB_DMA_AHBINF_RESP_ERR_WR_S)
+#define AHB_DMA_AHBINF_RESP_ERR_WR_V  0x00000001U
+#define AHB_DMA_AHBINF_RESP_ERR_WR_S  0
+/** AHB_DMA_AHBINF_RESP_ERR_ID : RO; bitpos: [4:1]; default: 15;
+ *  Represents the AHB response error request id.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_ID    0x0000000FU
+#define AHB_DMA_AHBINF_RESP_ERR_ID_M  (AHB_DMA_AHBINF_RESP_ERR_ID_V << AHB_DMA_AHBINF_RESP_ERR_ID_S)
+#define AHB_DMA_AHBINF_RESP_ERR_ID_V  0x0000000FU
+#define AHB_DMA_AHBINF_RESP_ERR_ID_S  1
+/** AHB_DMA_AHBINF_RESP_ERR_CH_ID : RO; bitpos: [7:5]; default: 0;
+ *  Represents the AHB response error request channel id.bit[2]=1:TX channel.
+ *  bit[2]=0:RX channel.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID    0x00000007U
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_M  (AHB_DMA_AHBINF_RESP_ERR_CH_ID_V << AHB_DMA_AHBINF_RESP_ERR_CH_ID_S)
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_V  0x00000007U
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_S  5
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH0_REG register
+ *  RX_done Inlink descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x410)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_M  (AHB_DMA_IN_DONE_DES_ADDR_CH0_V << AHB_DMA_IN_DONE_DES_ADDR_CH0_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG register
+ *  TX done outlink descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x414)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH0_V << AHB_DMA_OUT_DONE_DES_ADDR_CH0_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH1_REG register
+ *  RX_done Inlink descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x418)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_M  (AHB_DMA_IN_DONE_DES_ADDR_CH1_V << AHB_DMA_IN_DONE_DES_ADDR_CH1_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG register
+ *  TX done outlink descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x41c)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH1_V << AHB_DMA_OUT_DONE_DES_ADDR_CH1_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH2_REG register
+ *  RX_done Inlink descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x420)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_M  (AHB_DMA_IN_DONE_DES_ADDR_CH2_V << AHB_DMA_IN_DONE_DES_ADDR_CH2_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG register
+ *  TX done outlink descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x424)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH2_V << AHB_DMA_OUT_DONE_DES_ADDR_CH2_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_struct.h
new file mode 100644
index 0000000000..eb66f78455
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ahb_dma_struct.h
@@ -0,0 +1,1411 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt Registers */
+/** Type of in_int_raw_chn register
+ *  Raw status interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw: 1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+         *  turns to high level when the last data pointed by one inlink descriptor has been
+         *  received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw: 1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when data error is detected only in the
+         *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+         *  interrupt is reserved.
+         */
+        uint32_t in_err_eof_chn_int_raw: 1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+         *  including owner error and the second and third word error of inlink descriptor for
+         *  Rx channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw: 1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+         *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+         */
+        uint32_t in_dscr_empty_chn_int_raw: 1;
+        /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_ovf_chn_int_raw: 1;
+        /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_udf_chn_int_raw: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_in_int_raw_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st: 1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st: 1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st: 1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st: 1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st: 1;
+        /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_chn_int_st: 1;
+        /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_chn_int_st: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_in_int_st_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena: 1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena: 1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena: 1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena: 1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena: 1;
+        /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_chn_int_ena: 1;
+        /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_chn_int_ena: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_in_int_ena_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr: 1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr: 1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr: 1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr: 1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr: 1;
+        /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_chn_int_clr: 1;
+        /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_chn_int_clr: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_in_int_clr_chn_reg_t;
+
+/** Type of out_int_raw_chn register
+ *  Raw status interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_chn_int_raw: 1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_chn_int_raw: 1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+         *  including owner error and the second and third word error of outlink descriptor for
+         *  Tx channel 0.
+         */
+        uint32_t out_dscr_err_chn_int_raw: 1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_chn_int_raw: 1;
+        /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+         *  overflow.
+         */
+        uint32_t outfifo_ovf_chn_int_raw: 1;
+        /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+         *  underflow.
+         */
+        uint32_t outfifo_udf_chn_int_raw: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_int_raw_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st: 1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st: 1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st: 1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st: 1;
+        /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_chn_int_st: 1;
+        /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_chn_int_st: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_int_st_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena: 1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena: 1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena: 1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena: 1;
+        /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_chn_int_ena: 1;
+        /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_chn_int_ena: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_int_ena_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr: 1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr: 1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr: 1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr: 1;
+        /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_chn_int_clr: 1;
+        /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_chn_int_clr: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_int_clr_chn_reg_t;
+
+/** Group: Debug Registers */
+/** Type of ahb_test register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** ahb_testmode : R/W; bitpos: [2:0]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testmode: 3;
+        uint32_t reserved_3: 1;
+        /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testaddr: 2;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_ahb_test_reg_t;
+
+/** Group: Configuration Registers */
+/** Type of misc_conf register
+ *  MISC register
+ */
+typedef union {
+    struct {
+        /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0;
+         *  Set this bit then clear this bit to reset the internal ahb FSM.
+         */
+        uint32_t ahbm_rst_inter: 1;
+        uint32_t reserved_1: 1;
+        /** arb_pri_dis : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to disable priority arbitration function.
+         */
+        uint32_t arb_pri_dis: 1;
+        /** clk_en : R/W; bitpos: [3]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_misc_conf_reg_t;
+
+/** Type of in_conf0_chn register
+ *  Configure 0 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer.
+         */
+        uint32_t in_rst_chn: 1;
+        /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn: 1;
+        /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t indscr_burst_en_chn: 1;
+        /** in_data_burst_en_chn : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
+         *  when accessing internal SRAM.
+         */
+        uint32_t in_data_burst_en_chn: 1;
+        /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+         *  AHB_DMA.
+         */
+        uint32_t mem_trans_en_chn: 1;
+        /** in_etm_en_chn : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+         *  task.
+         */
+        uint32_t in_etm_en_chn: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_in_conf0_chn_reg_t;
+
+/** Type of in_conf1_chn register
+ *  Configure 1 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} ahb_dma_in_conf1_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Pop control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
+         *  This register stores the data popping from AHB_DMA FIFO.
+         */
+        uint32_t infifo_rdata_chn: 12;
+        /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
+         *  Set this bit to pop data from AHB_DMA FIFO.
+         */
+        uint32_t infifo_pop_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} ahb_dma_in_pop_chn_reg_t;
+
+/** Type of in_link_chn register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn: 1;
+        /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn: 1;
+        /** inlink_start_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn: 1;
+        /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn: 1;
+        /** inlink_park_chn : RO; bitpos: [4]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} ahb_dma_in_link_chn_reg_t;
+
+/** Type of out_conf1_chn register
+ *  Configure 1 register of Tx channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} ahb_dma_out_conf1_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Push control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
+         *  This register stores the data that need to be pushed into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_wdata_chn: 9;
+        /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
+         *  Set this bit to push data into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_push_chn: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} ahb_dma_out_push_chn_reg_t;
+
+/** Type of out_link_chn register
+ *  Link descriptor configure and control register of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn: 1;
+        /** outlink_start_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn: 1;
+        /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn: 1;
+        /** outlink_park_chn : RO; bitpos: [3]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_out_link_chn_reg_t;
+
+/** Type of out_conf0_chn register
+ *  Configure 0 register of Tx channel 1
+ */
+typedef union {
+    struct {
+        /** out_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_chn: 1;
+        /** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn: 1;
+        /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_chn: 1;
+        /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is
+         *  generated when data need to transmit has been popped from FIFO in AHB_DMA
+         */
+        uint32_t out_eof_mode_chn: 1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn: 1;
+        /** out_data_burst_en_chn : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data
+         *  when accessing internal SRAM.
+         */
+        uint32_t out_data_burst_en_chn: 1;
+        /** out_etm_en_chn : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_chn: 1;
+        uint32_t reserved_7: 25;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_chn_reg_t;
+
+/** Type of out_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of tx crc initial value
+         */
+        uint32_t out_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_init_data_chn_reg_t;
+
+/** Type of tx_crc_width_chn register
+ *  This register is used to config tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_width_chn: 2;
+        /** tx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_width_chn_reg_t;
+
+/** Type of out_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of tx crc result
+         */
+        uint32_t out_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_clear_chn_reg_t;
+
+/** Type of out_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of tx
+         */
+        uint32_t out_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_crc_final_result_chn_reg_t;
+
+/** Type of tx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable tx ch0 crc 32bit on/off
+         */
+        uint32_t tx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_en_addr_chn_reg_t;
+
+/** Type of tx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_wr_data_chn: 8;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_tx_crc_data_en_addr_chn_reg_t;
+
+/** Type of tx_ch_arb_weigh_chn register
+ *  This register is used to config ch0 arbiter weigh
+ */
+typedef union {
+    struct {
+        /** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_ch_arb_weigh_chn: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_tx_ch_arb_weigh_chn_reg_t;
+
+/** Type of tx_arb_weigh_opt_dir_chn register
+ *  This register is used to config off or on weigh optimization
+ */
+typedef union {
+    struct {
+        /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t;
+
+/** Type of in_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of rx crc initial value
+         */
+        uint32_t in_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_init_data_chn_reg_t;
+
+/** Type of rx_crc_width_chn register
+ *  This register is used to config rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_width_chn: 2;
+        /** rx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_width_chn_reg_t;
+
+/** Type of in_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of rx crc result
+         */
+        uint32_t in_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_clear_chn_reg_t;
+
+/** Type of in_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of rx
+         */
+        uint32_t in_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_crc_final_result_chn_reg_t;
+
+/** Type of rx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable rx ch0 crc 32bit on/off
+         */
+        uint32_t rx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_en_addr_chn_reg_t;
+
+/** Type of rx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_wr_data_chn: 8;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_rx_crc_data_en_addr_chn_reg_t;
+
+/** Type of rx_ch_arb_weigh_chn register
+ *  This register is used to config ch0 arbiter weigh
+ */
+typedef union {
+    struct {
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_ch_arb_weigh_chn: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_rx_ch_arb_weigh_chn_reg_t;
+
+/** Type of rx_arb_weigh_opt_dir_chn register
+ *  This register is used to config off or on weigh optimization
+ */
+typedef union {
+    struct {
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t;
+
+/** Type of in_link_addr_chn register
+ *  Link descriptor configure of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 32 least significant bits of the first inlink descriptor's
+         *  address.
+         */
+        uint32_t inlink_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_link_addr_chn_reg_t;
+
+/** Type of out_link_addr_chn register
+ *  Link descriptor configure of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 32 least significant bits of the first outlink
+         *  descriptor's address.
+         */
+        uint32_t outlink_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_link_addr_chn_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr: 32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr: 32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_end_addr_reg_t;
+
+/** Type of arb_timeout_tx register
+ *  This retister is used to config arbiter time slice for tx dir
+ */
+typedef union {
+    struct {
+        /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to config arbiter time out value
+         */
+        uint32_t arb_timeout_tx: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_tx_reg_t;
+
+/** Type of arb_timeout_rx register
+ *  This retister is used to config arbiter time slice for rx dir
+ */
+typedef union {
+    struct {
+        /** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to config arbiter time out value
+         */
+        uint32_t arb_timeout_rx: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_rx_reg_t;
+
+/** Type of weight_en_tx register
+ *  This register is used to config arbiter weigh function to on or off for tx dir
+ */
+typedef union {
+    struct {
+        /** weight_en_tx : R/W; bitpos: [0]; default: 0;
+         *  This register is used to config arbiter weight function  off/on
+         */
+        uint32_t weight_en_tx: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_tx_reg_t;
+
+/** Type of weight_en_rx register
+ *  This register is used to config arbiter weigh function to on or off for rx dir
+ */
+typedef union {
+    struct {
+        /** weight_en_rx : R/W; bitpos: [0]; default: 0;
+         *  This register is used to config arbiter weight function  off/on
+         */
+        uint32_t weight_en_rx: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_rx_reg_t;
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36712768;
+         *  register version.
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} ahb_dma_date_reg_t;
+
+/** Group: Status Registers */
+/** Type of infifo_status_chn register
+ *  Receive FIFO status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_full_chn : RO; bitpos: [0]; default: 1;
+         *  L1 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_full_chn: 1;
+        /** infifo_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L1 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_empty_chn: 1;
+        /** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_cnt_chn: 6;
+        uint32_t reserved_8: 15;
+        /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn: 1;
+        /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn: 1;
+        /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn: 1;
+        /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn: 1;
+        /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_chn: 1;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} ahb_dma_infifo_status_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Receive status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn: 18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn: 2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} ahb_dma_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Inlink descriptor address when EOF occurs of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Inlink descriptor address when errors occur of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data. Only used when peripheral is UHCI0.
+         */
+        uint32_t in_err_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Current inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current inlink descriptor x.
+         */
+        uint32_t inlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  The last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  The second-to-last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf1_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Transmit FIFO status of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_full_chn : RO; bitpos: [0]; default: 0;
+         *  L1 Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_chn: 1;
+        /** outfifo_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L1 Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_chn: 1;
+        /** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_chn: 6;
+        uint32_t reserved_8: 15;
+        /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn: 1;
+        /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn: 1;
+        /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn: 1;
+        /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn: 1;
+        uint32_t reserved_27: 5;
+    };
+    uint32_t val;
+} ahb_dma_outfifo_status_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Transmit status of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn: 18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_chn: 2;
+        /** out_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} ahb_dma_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Outlink descriptor address when EOF occurs of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_eof_bfr_des_addr_chn register
+ *  The last outlink descriptor address when EOF occurs of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor before the last outlink
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_bfr_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Current inlink descriptor address of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current outlink descriptor y.
+         */
+        uint32_t outlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  The last inlink descriptor address of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  The second-to-last inlink descriptor address of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor x-2.
+         */
+        uint32_t outlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf1_chn_reg_t;
+
+/** Group: Priority Registers */
+/** Type of in_pri_chn register
+ *  Priority register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+         */
+        uint32_t rx_pri_chn: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_in_pri_chn_reg_t;
+
+/** Type of out_pri_chn register
+ *  Priority register of Tx channel 0.
+ */
+typedef union {
+    struct {
+        /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Tx channel 0. The larger of the value the higher of the priority.
+         */
+        uint32_t tx_pri_chn: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} ahb_dma_out_pri_chn_reg_t;
+
+/** Group: Peripheral Select Registers */
+/** Type of in_peri_sel_chn register
+ *  Peripheral selection of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2:
+         *  UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10:
+         *  RMT,11~15: Dummy
+         */
+        uint32_t peri_in_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_sel_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Peripheral selection of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2:
+         *  UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10:
+         *  RMT,11~15: Dummy
+         */
+        uint32_t peri_out_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_sel_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_in_int_raw_chn_reg_t raw;
+    volatile ahb_dma_in_int_st_chn_reg_t st;
+    volatile ahb_dma_in_int_ena_chn_reg_t ena;
+    volatile ahb_dma_in_int_clr_chn_reg_t clr;
+} ahb_dma_in_int_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_out_int_raw_chn_reg_t raw;
+    volatile ahb_dma_out_int_st_chn_reg_t st;
+    volatile ahb_dma_out_int_ena_chn_reg_t ena;
+    volatile ahb_dma_out_int_clr_chn_reg_t clr;
+} ahb_dma_out_int_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_in_conf0_chn_reg_t in_conf0;
+    volatile ahb_dma_in_conf1_chn_reg_t in_conf1;
+    volatile ahb_dma_infifo_status_chn_reg_t infifo_status;
+    volatile ahb_dma_in_pop_chn_reg_t in_pop;
+    volatile ahb_dma_in_link_chn_reg_t in_link;
+    volatile ahb_dma_in_state_chn_reg_t in_state;
+    volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
+    volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
+    volatile ahb_dma_in_dscr_chn_reg_t in_dscr;
+    volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
+    volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
+    volatile ahb_dma_in_pri_chn_reg_t in_pri;
+    volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel;
+} ahb_dma_in_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_out_conf0_chn_reg_t out_conf0;
+    volatile ahb_dma_out_conf1_chn_reg_t out_conf1;
+    volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status;
+    volatile ahb_dma_out_push_chn_reg_t out_push;
+    volatile ahb_dma_out_link_chn_reg_t out_link;
+    volatile ahb_dma_out_state_chn_reg_t out_state;
+    volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
+    volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
+    volatile ahb_dma_out_dscr_chn_reg_t out_dscr;
+    volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
+    volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
+    volatile ahb_dma_out_pri_chn_reg_t out_pri;
+    volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel;
+} ahb_dma_out_chn_reg_t;
+
+typedef struct {
+    ahb_dma_in_crc_init_data_chn_reg_t crc_init_data;
+    ahb_dma_rx_crc_width_chn_reg_t crc_width;
+    ahb_dma_in_crc_clear_chn_reg_t crc_clear;
+    ahb_dma_in_crc_final_result_chn_reg_t crc_final_result;
+    ahb_dma_rx_crc_en_wr_data_chn_reg_t crc_en_wr_data;
+    ahb_dma_rx_crc_en_addr_chn_reg_t crc_en_addr;
+    ahb_dma_rx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
+    ahb_dma_rx_crc_data_en_addr_chn_reg_t crc_data_en_addr;
+    ahb_dma_rx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
+    ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
+} ahb_dma_in_crc_arb_chn_reg_t;
+
+typedef struct {
+    ahb_dma_out_crc_init_data_chn_reg_t crc_init_data;
+    ahb_dma_tx_crc_width_chn_reg_t crc_width;
+    ahb_dma_out_crc_clear_chn_reg_t crc_clear;
+    ahb_dma_out_crc_final_result_chn_reg_t crc_final_result;
+    ahb_dma_tx_crc_en_wr_data_chn_reg_t crc_en_wr_data;
+    ahb_dma_tx_crc_en_addr_chn_reg_t crc_en_addr;
+    ahb_dma_tx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
+    ahb_dma_tx_crc_data_en_addr_chn_reg_t crc_data_en_addr;
+    ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
+    ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
+} ahb_dma_out_crc_arb_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_in_chn_reg_t in;
+    uint32_t reserved_in[11];
+    volatile ahb_dma_out_chn_reg_t out;
+    uint32_t reserved_out[11];
+} ahb_dma_chn_reg_t;
+
+typedef struct {
+    volatile ahb_dma_in_int_chn_reg_t in_intr[3];
+    volatile ahb_dma_out_int_chn_reg_t out_intr[3];
+    volatile ahb_dma_ahb_test_reg_t ahb_test;
+    volatile ahb_dma_misc_conf_reg_t misc_conf;
+    volatile ahb_dma_date_reg_t date;
+    uint32_t reserved_06c;
+    volatile ahb_dma_chn_reg_t channel[3];
+    uint32_t reserved_2b0[3];
+    volatile ahb_dma_out_crc_arb_chn_reg_t out_crc_arb[3];
+    volatile ahb_dma_in_crc_arb_chn_reg_t in_crc_arb[3];
+    volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr[3];
+    volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr[3];
+    volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx;
+    volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx;
+    volatile ahb_dma_weight_en_tx_reg_t weight_en_tx;
+    volatile ahb_dma_weight_en_rx_reg_t weight_en_rx;
+} ahb_dma_dev_t;
+
+extern ahb_dma_dev_t AHB_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ahb_dma_dev_t) == 0x3DC, "Invalid size of ahb_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/assist_debug_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/assist_debug_reg.h
new file mode 100644
index 0000000000..3cbd5c7c89
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/assist_debug_reg.h
@@ -0,0 +1,1399 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
+ *  core0 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+
+/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
+ *  core0 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+
+/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
+ *  core0 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
+
+/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
+ *  core0 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
+ *  core0 area pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  the stackpointer when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
+ *  core0 area sp status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
+/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  the PC when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
+/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core0 sp region configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
+/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core0 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
+/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
+/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register2
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
+ *  reg_core_0_dram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  1
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register3
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  exception monitor status register4
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  exception monitor status register5
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
+ *  reg_core_0_dram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  1
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CORE_1_INTR_ENA_REG register
+ *  core1 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S  9
+
+/** ASSIST_DEBUG_CORE_1_INTR_RAW_REG register
+ *  core1 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S  9
+
+/** ASSIST_DEBUG_CORE_1_INTR_RLS_REG register
+ *  core1 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S  9
+
+/** ASSIST_DEBUG_CORE_1_INTR_CLR_REG register
+ *  core1 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8c)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S  9
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG register
+ *  core1 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 dram0 region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG register
+ *  core1 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 dram0 region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG register
+ *  core1 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 dram0 region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG register
+ *  core1 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x9c)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 dram0 region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG register
+ *  core1 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa0)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 PIF region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG register
+ *  core1 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa4)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 PIF region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG register
+ *  core1 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa8)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 PIF region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG register
+ *  core1 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xac)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 PIF region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PC_REG register
+ *  core1 area pc status register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb0)
+/** ASSIST_DEBUG_CORE_1_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  the stackpointer when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PC_M  (ASSIST_DEBUG_CORE_1_AREA_PC_V << ASSIST_DEBUG_CORE_1_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PC_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_SP_REG register
+ *  core1 area sp status register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb4)
+/** ASSIST_DEBUG_CORE_1_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  the PC when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_SP_M  (ASSIST_DEBUG_CORE_1_AREA_SP_V << ASSIST_DEBUG_CORE_1_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_1_AREA_SP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_SP_S  0
+
+/** ASSIST_DEBUG_CORE_1_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb8)
+/** ASSIST_DEBUG_CORE_1_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core1 sp region configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MIN_M  (ASSIST_DEBUG_CORE_1_SP_MIN_V << ASSIST_DEBUG_CORE_1_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_1_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xbc)
+/** ASSIST_DEBUG_CORE_1_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core1 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MAX_M  (ASSIST_DEBUG_CORE_1_SP_MAX_V << ASSIST_DEBUG_CORE_1_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_1_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_1_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc0)
+/** ASSIST_DEBUG_CORE_1_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_1_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_PC_M  (ASSIST_DEBUG_CORE_1_SP_PC_V << ASSIST_DEBUG_CORE_1_SP_PC_S)
+#define ASSIST_DEBUG_CORE_1_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_1_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc4)
+/** ASSIST_DEBUG_CORE_1_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_1_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_1_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc8)
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xcc)
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd0)
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_iram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_1_iram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
+ *  reg_core_1_iram0_recording_loadstore_0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S  25
+
+/** ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd4)
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_iram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_1_iram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
+ *  reg_core_1_iram0_recording_loadstore_1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S  25
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register2
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd8)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
+ *  reg_core_1_dram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S  0
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_1_dram0_recording_byteen_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S  1
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register3
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0xdc)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_dram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S  0
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  exception monitor status register4
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe0)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_1_dram0_recording_pc_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S  0
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  exception monitor status register5
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe4)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
+ *  reg_core_1_dram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S  0
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_1_dram0_recording_byteen_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S  1
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe8)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_dram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S  0
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0xec)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_1_dram0_recording_pc_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S  0
+
+/** ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0xf0)
+/** ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0xf4)
+/** ASSIST_DEBUG_CORE_1_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_1_DEBUG_MODE_V << ASSIST_DEBUG_CORE_1_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_0
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_1
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
+
+/** ASSIST_DEBUG_CLOCK_GATE_REG register
+ *  clock register
+ */
+#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108)
+/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 force on the clock gate
+ */
+#define ASSIST_DEBUG_CLK_EN    (BIT(0))
+#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
+#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
+#define ASSIST_DEBUG_CLK_EN_S  0
+
+/** ASSIST_DEBUG_DATE_REG register
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
+/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
+ *  version register
+ */
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE    0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/assist_debug_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/assist_debug_struct.h
new file mode 100644
index 0000000000..3f040390f7
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/assist_debug_struct.h
@@ -0,0 +1,1318 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: monitor configuration registers */
+/** Type of core_0_intr_ena register
+ *  core0 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor enable
+         */
+        uint32_t core_0_area_dram0_0_rd_ena:1;
+        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor enable
+         */
+        uint32_t core_0_area_dram0_0_wr_ena:1;
+        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor enable
+         */
+        uint32_t core_0_area_dram0_1_rd_ena:1;
+        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor enable
+         */
+        uint32_t core_0_area_dram0_1_wr_ena:1;
+        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor enable
+         */
+        uint32_t core_0_area_pif_0_rd_ena:1;
+        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor enable
+         */
+        uint32_t core_0_area_pif_0_wr_ena:1;
+        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor enable
+         */
+        uint32_t core_0_area_pif_1_rd_ena:1;
+        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor enable
+         */
+        uint32_t core_0_area_pif_1_wr_ena:1;
+        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor enable
+         */
+        uint32_t core_0_sp_spill_min_ena:1;
+        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor enable
+         */
+        uint32_t core_0_sp_spill_max_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_ena_reg_t;
+
+/** Type of core_0_area_dram0_0_min register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region0 start addr
+         */
+        uint32_t core_0_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_min_reg_t;
+
+/** Type of core_0_area_dram0_0_max register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region0 end addr
+         */
+        uint32_t core_0_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_max_reg_t;
+
+/** Type of core_0_area_dram0_1_min register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region1 start addr
+         */
+        uint32_t core_0_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_min_reg_t;
+
+/** Type of core_0_area_dram0_1_max register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region1 end addr
+         */
+        uint32_t core_0_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_max_reg_t;
+
+/** Type of core_0_area_pif_0_min register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region0 start addr
+         */
+        uint32_t core_0_area_pif_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_min_reg_t;
+
+/** Type of core_0_area_pif_0_max register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region0 end addr
+         */
+        uint32_t core_0_area_pif_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_max_reg_t;
+
+/** Type of core_0_area_pif_1_min register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region1 start addr
+         */
+        uint32_t core_0_area_pif_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_min_reg_t;
+
+/** Type of core_0_area_pif_1_max register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region1 end addr
+         */
+        uint32_t core_0_area_pif_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_max_reg_t;
+
+/** Type of core_0_area_pc register
+ *  core0 area pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  the stackpointer when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pc_reg_t;
+
+/** Type of core_0_area_sp register
+ *  core0 area sp status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  the PC when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_sp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_sp_reg_t;
+
+/** Type of core_0_sp_min register
+ *  stack min value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  core0 sp region configuration register
+         */
+        uint32_t core_0_sp_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_min_reg_t;
+
+/** Type of core_0_sp_max register
+ *  stack max value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  core0 sp pc status register
+         */
+        uint32_t core_0_sp_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_max_reg_t;
+
+/** Type of core_0_sp_pc register
+ *  stack monitor pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the PC when trigger stack monitor.
+         */
+        uint32_t core_0_sp_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_pc_reg_t;
+
+/** Type of core_1_intr_ena register
+ *  core1 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor enable
+         */
+        uint32_t core_1_area_dram0_0_rd_ena:1;
+        /** core_1_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor enable
+         */
+        uint32_t core_1_area_dram0_0_wr_ena:1;
+        /** core_1_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor enable
+         */
+        uint32_t core_1_area_dram0_1_rd_ena:1;
+        /** core_1_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor enable
+         */
+        uint32_t core_1_area_dram0_1_wr_ena:1;
+        /** core_1_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor enable
+         */
+        uint32_t core_1_area_pif_0_rd_ena:1;
+        /** core_1_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor enable
+         */
+        uint32_t core_1_area_pif_0_wr_ena:1;
+        /** core_1_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor enable
+         */
+        uint32_t core_1_area_pif_1_rd_ena:1;
+        /** core_1_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor enable
+         */
+        uint32_t core_1_area_pif_1_wr_ena:1;
+        /** core_1_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor enable
+         */
+        uint32_t core_1_sp_spill_min_ena:1;
+        /** core_1_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor enable
+         */
+        uint32_t core_1_sp_spill_max_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_ena_reg_t;
+
+/** Type of core_1_area_dram0_0_min register
+ *  core1 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 dram0 region0 start addr
+         */
+        uint32_t core_1_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_0_min_reg_t;
+
+/** Type of core_1_area_dram0_0_max register
+ *  core1 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 dram0 region0 end addr
+         */
+        uint32_t core_1_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_0_max_reg_t;
+
+/** Type of core_1_area_dram0_1_min register
+ *  core1 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 dram0 region1 start addr
+         */
+        uint32_t core_1_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_1_min_reg_t;
+
+/** Type of core_1_area_dram0_1_max register
+ *  core1 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 dram0 region1 end addr
+         */
+        uint32_t core_1_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_1_max_reg_t;
+
+/** Type of core_1_area_pif_0_min register
+ *  core1 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 PIF region0 start addr
+         */
+        uint32_t core_1_area_pif_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_0_min_reg_t;
+
+/** Type of core_1_area_pif_0_max register
+ *  core1 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 PIF region0 end addr
+         */
+        uint32_t core_1_area_pif_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_0_max_reg_t;
+
+/** Type of core_1_area_pif_1_min register
+ *  core1 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 PIF region1 start addr
+         */
+        uint32_t core_1_area_pif_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_1_min_reg_t;
+
+/** Type of core_1_area_pif_1_max register
+ *  core1 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 PIF region1 end addr
+         */
+        uint32_t core_1_area_pif_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_1_max_reg_t;
+
+/** Type of core_1_area_pc register
+ *  core1 area pc status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  the stackpointer when first touch region monitor interrupt
+         */
+        uint32_t core_1_area_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pc_reg_t;
+
+/** Type of core_1_area_sp register
+ *  core1 area sp status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  the PC when first touch region monitor interrupt
+         */
+        uint32_t core_1_area_sp:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_sp_reg_t;
+
+/** Type of core_1_sp_min register
+ *  stack min value
+ */
+typedef union {
+    struct {
+        /** core_1_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  core1 sp region configuration register
+         */
+        uint32_t core_1_sp_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_sp_min_reg_t;
+
+/** Type of core_1_sp_max register
+ *  stack max value
+ */
+typedef union {
+    struct {
+        /** core_1_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  core1 sp pc status register
+         */
+        uint32_t core_1_sp_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_sp_max_reg_t;
+
+/** Type of core_1_sp_pc register
+ *  stack monitor pc status register
+ */
+typedef union {
+    struct {
+        /** core_1_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the PC when trigger stack monitor.
+         */
+        uint32_t core_1_sp_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_sp_pc_reg_t;
+
+
+/** Group: interrupt configuration register */
+/** Type of core_0_intr_raw register
+ *  core0 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_rd_raw:1;
+        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_wr_raw:1;
+        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_rd_raw:1;
+        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_wr_raw:1;
+        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_rd_raw:1;
+        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_wr_raw:1;
+        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_rd_raw:1;
+        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_wr_raw:1;
+        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_min_raw:1;
+        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_max_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_raw_reg_t;
+
+/** Type of core_0_intr_rls register
+ *  core0 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_rd_rls:1;
+        /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_wr_rls:1;
+        /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_rd_rls:1;
+        /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_wr_rls:1;
+        /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_rd_rls:1;
+        /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_wr_rls:1;
+        /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_rd_rls:1;
+        /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_wr_rls:1;
+        /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_min_rls:1;
+        /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_max_rls:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_rls_reg_t;
+
+/** Type of core_0_intr_clr register
+ *  core0 monitor interrupt clr register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_rd_clr:1;
+        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_wr_clr:1;
+        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_rd_clr:1;
+        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_wr_clr:1;
+        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_rd_clr:1;
+        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_wr_clr:1;
+        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_rd_clr:1;
+        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_wr_clr:1;
+        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_min_clr:1;
+        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_max_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_clr_reg_t;
+
+/** Type of core_1_intr_raw register
+ *  core1 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_0_rd_raw:1;
+        /** core_1_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_0_wr_raw:1;
+        /** core_1_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_1_rd_raw:1;
+        /** core_1_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_1_wr_raw:1;
+        /** core_1_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt status
+         */
+        uint32_t core_1_area_pif_0_rd_raw:1;
+        /** core_1_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt status
+         */
+        uint32_t core_1_area_pif_0_wr_raw:1;
+        /** core_1_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt status
+         */
+        uint32_t core_1_area_pif_1_rd_raw:1;
+        /** core_1_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt status
+         */
+        uint32_t core_1_area_pif_1_wr_raw:1;
+        /** core_1_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt status
+         */
+        uint32_t core_1_sp_spill_min_raw:1;
+        /** core_1_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt status
+         */
+        uint32_t core_1_sp_spill_max_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_raw_reg_t;
+
+/** Type of core_1_intr_rls register
+ *  core1 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_0_rd_rls:1;
+        /** core_1_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_0_wr_rls:1;
+        /** core_1_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_1_rd_rls:1;
+        /** core_1_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_1_wr_rls:1;
+        /** core_1_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_0_rd_rls:1;
+        /** core_1_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_0_wr_rls:1;
+        /** core_1_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_1_rd_rls:1;
+        /** core_1_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_1_wr_rls:1;
+        /** core_1_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_1_sp_spill_min_rls:1;
+        /** core_1_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_1_sp_spill_max_rls:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_rls_reg_t;
+
+/** Type of core_1_intr_clr register
+ *  core1 monitor interrupt clr register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_0_rd_clr:1;
+        /** core_1_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_0_wr_clr:1;
+        /** core_1_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_1_rd_clr:1;
+        /** core_1_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_1_wr_clr:1;
+        /** core_1_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_0_rd_clr:1;
+        /** core_1_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_0_wr_clr:1;
+        /** core_1_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_1_rd_clr:1;
+        /** core_1_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_1_wr_clr:1;
+        /** core_1_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt clr
+         */
+        uint32_t core_1_sp_spill_min_clr:1;
+        /** core_1_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt clr
+         */
+        uint32_t core_1_sp_spill_max_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_clr_reg_t;
+
+
+/** Group: pc recording configuration register */
+/** Type of core_0_rcd_en register
+ *  record enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable record PC
+         */
+        uint32_t core_0_rcd_recorden:1;
+        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+         */
+        uint32_t core_0_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_en_reg_t;
+
+/** Type of core_1_rcd_en register
+ *  record enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable record PC
+         */
+        uint32_t core_1_rcd_recorden:1;
+        /** core_1_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+         */
+        uint32_t core_1_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_1_rcd_en_reg_t;
+
+
+/** Group: pc recording status register */
+/** Type of core_0_rcd_pdebugpc register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  recorded PC
+         */
+        uint32_t core_0_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugpc_reg_t;
+
+/** Type of core_0_rcd_pdebugsp register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  recorded sp
+         */
+        uint32_t core_0_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugsp_reg_t;
+
+/** Type of core_1_rcd_pdebugpc register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  recorded PC
+         */
+        uint32_t core_1_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_rcd_pdebugpc_reg_t;
+
+/** Type of core_1_rcd_pdebugsp register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  recorded sp
+         */
+        uint32_t core_1_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_rcd_pdebugsp_reg_t;
+
+
+/** Group: exception monitor register */
+/** Type of core_0_iram0_exception_monitor_0 register
+ *  exception monitor status register0
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_0
+         */
+        uint32_t core_0_iram0_recording_addr_0:24;
+        /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_0
+         */
+        uint32_t core_0_iram0_recording_wr_0:1;
+        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_0
+         */
+        uint32_t core_0_iram0_recording_loadstore_0:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_iram0_exception_monitor_1 register
+ *  exception monitor status register1
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_1
+         */
+        uint32_t core_0_iram0_recording_addr_1:24;
+        /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_1
+         */
+        uint32_t core_0_iram0_recording_wr_1:1;
+        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_1
+         */
+        uint32_t core_0_iram0_recording_loadstore_1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_0 register
+ *  exception monitor status register2
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
+         *  reg_core_0_dram0_recording_wr_0
+         */
+        uint32_t core_0_dram0_recording_wr_0:1;
+        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_0
+         */
+        uint32_t core_0_dram0_recording_byteen_0:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_1 register
+ *  exception monitor status register3
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_0
+         */
+        uint32_t core_0_dram0_recording_addr_0:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_2 register
+ *  exception monitor status register4
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_0
+         */
+        uint32_t core_0_dram0_recording_pc_0:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_3 register
+ *  exception monitor status register5
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
+         *  reg_core_0_dram0_recording_wr_1
+         */
+        uint32_t core_0_dram0_recording_wr_1:1;
+        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_1
+         */
+        uint32_t core_0_dram0_recording_byteen_1:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_4 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_1
+         */
+        uint32_t core_0_dram0_recording_addr_1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_5 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_1
+         */
+        uint32_t core_0_dram0_recording_pc_1:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
+
+/** Type of core_1_iram0_exception_monitor_0 register
+ *  exception monitor status register0
+ */
+typedef union {
+    struct {
+        /** core_1_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_iram0_recording_addr_0
+         */
+        uint32_t core_1_iram0_recording_addr_0:24;
+        /** core_1_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_1_iram0_recording_wr_0
+         */
+        uint32_t core_1_iram0_recording_wr_0:1;
+        /** core_1_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
+         *  reg_core_1_iram0_recording_loadstore_0
+         */
+        uint32_t core_1_iram0_recording_loadstore_0:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_1_iram0_exception_monitor_0_reg_t;
+
+/** Type of core_1_iram0_exception_monitor_1 register
+ *  exception monitor status register1
+ */
+typedef union {
+    struct {
+        /** core_1_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_iram0_recording_addr_1
+         */
+        uint32_t core_1_iram0_recording_addr_1:24;
+        /** core_1_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_1_iram0_recording_wr_1
+         */
+        uint32_t core_1_iram0_recording_wr_1:1;
+        /** core_1_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
+         *  reg_core_1_iram0_recording_loadstore_1
+         */
+        uint32_t core_1_iram0_recording_loadstore_1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_1_iram0_exception_monitor_1_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_0 register
+ *  exception monitor status register2
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
+         *  reg_core_1_dram0_recording_wr_0
+         */
+        uint32_t core_1_dram0_recording_wr_0:1;
+        /** core_1_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_1_dram0_recording_byteen_0
+         */
+        uint32_t core_1_dram0_recording_byteen_0:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_1 register
+ *  exception monitor status register3
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_dram0_recording_addr_0
+         */
+        uint32_t core_1_dram0_recording_addr_0:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_1_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_2 register
+ *  exception monitor status register4
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_1_dram0_recording_pc_0
+         */
+        uint32_t core_1_dram0_recording_pc_0:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_2_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_3 register
+ *  exception monitor status register5
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
+         *  reg_core_1_dram0_recording_wr_1
+         */
+        uint32_t core_1_dram0_recording_wr_1:1;
+        /** core_1_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_1_dram0_recording_byteen_1
+         */
+        uint32_t core_1_dram0_recording_byteen_1:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_3_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_4 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_dram0_recording_addr_1
+         */
+        uint32_t core_1_dram0_recording_addr_1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_4_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_5 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_1_dram0_recording_pc_1
+         */
+        uint32_t core_1_dram0_recording_pc_1:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_5_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_0 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_0
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_1 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_1
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
+
+
+/** Group: cpu status registers */
+/** Type of core_0_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  cpu's lastpc before exception
+         */
+        uint32_t core_0_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_lastpc_before_exception_reg_t;
+
+/** Type of core_0_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
+         *  cpu debug mode status, 1 means cpu enter debug mode.
+         */
+        uint32_t core_0_debug_mode:1;
+        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  cpu debug_module active status
+         */
+        uint32_t core_0_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_debug_mode_reg_t;
+
+/** Type of core_1_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_1_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  cpu's lastpc before exception
+         */
+        uint32_t core_1_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_lastpc_before_exception_reg_t;
+
+/** Type of core_1_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_1_debug_mode : RO; bitpos: [0]; default: 0;
+         *  cpu debug mode status, 1 means cpu enter debug mode.
+         */
+        uint32_t core_1_debug_mode:1;
+        /** core_1_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  cpu debug_module active status
+         */
+        uint32_t core_1_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_1_debug_mode_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of clock_gate register
+ *  clock register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 force on the clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} assist_debug_clock_gate_reg_t;
+
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
+         *  version register
+         */
+        uint32_t assist_debug_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} assist_debug_date_reg_t;
+
+
+typedef struct {
+    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
+    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
+    volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
+    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
+    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
+    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
+    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
+    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
+    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
+    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
+    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
+    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
+    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
+    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
+    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
+    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
+    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
+    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
+    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
+    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
+    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
+    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
+    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
+    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
+    volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
+    volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
+    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
+    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
+    uint32_t reserved_078[2];
+    volatile assist_debug_core_1_intr_ena_reg_t core_1_intr_ena;
+    volatile assist_debug_core_1_intr_raw_reg_t core_1_intr_raw;
+    volatile assist_debug_core_1_intr_rls_reg_t core_1_intr_rls;
+    volatile assist_debug_core_1_intr_clr_reg_t core_1_intr_clr;
+    volatile assist_debug_core_1_area_dram0_0_min_reg_t core_1_area_dram0_0_min;
+    volatile assist_debug_core_1_area_dram0_0_max_reg_t core_1_area_dram0_0_max;
+    volatile assist_debug_core_1_area_dram0_1_min_reg_t core_1_area_dram0_1_min;
+    volatile assist_debug_core_1_area_dram0_1_max_reg_t core_1_area_dram0_1_max;
+    volatile assist_debug_core_1_area_pif_0_min_reg_t core_1_area_pif_0_min;
+    volatile assist_debug_core_1_area_pif_0_max_reg_t core_1_area_pif_0_max;
+    volatile assist_debug_core_1_area_pif_1_min_reg_t core_1_area_pif_1_min;
+    volatile assist_debug_core_1_area_pif_1_max_reg_t core_1_area_pif_1_max;
+    volatile assist_debug_core_1_area_pc_reg_t core_1_area_pc;
+    volatile assist_debug_core_1_area_sp_reg_t core_1_area_sp;
+    volatile assist_debug_core_1_sp_min_reg_t core_1_sp_min;
+    volatile assist_debug_core_1_sp_max_reg_t core_1_sp_max;
+    volatile assist_debug_core_1_sp_pc_reg_t core_1_sp_pc;
+    volatile assist_debug_core_1_rcd_en_reg_t core_1_rcd_en;
+    volatile assist_debug_core_1_rcd_pdebugpc_reg_t core_1_rcd_pdebugpc;
+    volatile assist_debug_core_1_rcd_pdebugsp_reg_t core_1_rcd_pdebugsp;
+    volatile assist_debug_core_1_iram0_exception_monitor_0_reg_t core_1_iram0_exception_monitor_0;
+    volatile assist_debug_core_1_iram0_exception_monitor_1_reg_t core_1_iram0_exception_monitor_1;
+    volatile assist_debug_core_1_dram0_exception_monitor_0_reg_t core_1_dram0_exception_monitor_0;
+    volatile assist_debug_core_1_dram0_exception_monitor_1_reg_t core_1_dram0_exception_monitor_1;
+    volatile assist_debug_core_1_dram0_exception_monitor_2_reg_t core_1_dram0_exception_monitor_2;
+    volatile assist_debug_core_1_dram0_exception_monitor_3_reg_t core_1_dram0_exception_monitor_3;
+    volatile assist_debug_core_1_dram0_exception_monitor_4_reg_t core_1_dram0_exception_monitor_4;
+    volatile assist_debug_core_1_dram0_exception_monitor_5_reg_t core_1_dram0_exception_monitor_5;
+    volatile assist_debug_core_1_lastpc_before_exception_reg_t core_1_lastpc_before_exception;
+    volatile assist_debug_core_1_debug_mode_reg_t core_1_debug_mode;
+    uint32_t reserved_0f8[2];
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
+    volatile assist_debug_clock_gate_reg_t clock_gate;
+    uint32_t reserved_10c[188];
+    volatile assist_debug_date_reg_t date;
+} assist_debug_dev_t;
+
+extern assist_debug_dev_t ASSIST_DEBUG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/axi_dma_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/axi_dma_eco5_struct.h
new file mode 100644
index 0000000000..0abf169209
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/axi_dma_eco5_struct.h
@@ -0,0 +1,2021 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt Registers */
+/** Type of in_int_raw_chn register
+ *  Raw status interrupt of channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw:1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+         *  turns to high level when the last data pointed by one inlink descriptor has been
+         *  received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw:1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when data error is detected only in the
+         *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+         *  interrupt is reserved.
+         */
+        uint32_t in_err_eof_chn_int_raw:1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+         *  including owner error and the second and third word error of inlink descriptor for
+         *  Rx channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw:1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+         *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+         */
+        uint32_t in_dscr_empty_chn_int_raw:1;
+        /** infifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l1_ovf_chn_int_raw:1;
+        /** infifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l1_udf_chn_int_raw:1;
+        /** infifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l2_ovf_chn_int_raw:1;
+        /** infifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l2_udf_chn_int_raw:1;
+        /** infifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l3_ovf_chn_int_raw:1;
+        /** infifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l3_udf_chn_int_raw:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_in_int_raw_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt of channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st:1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st:1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st:1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st:1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st:1;
+        /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_chn_int_st:1;
+        /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_chn_int_st:1;
+        /** infifo_l1_ovf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_st:1;
+        /** infifo_l1_udf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_st:1;
+        /** infifo_l3_ovf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_st:1;
+        /** infifo_l3_udf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_st:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_in_int_st_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena:1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena:1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena:1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena:1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena:1;
+        /** infifo_l1_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_ena:1;
+        /** infifo_l1_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_ena:1;
+        /** infifo_l2_ovf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_ena:1;
+        /** infifo_l2_udf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_ena:1;
+        /** infifo_l3_ovf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_ena:1;
+        /** infifo_l3_udf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_ena:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_in_int_ena_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr:1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr:1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr:1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr:1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr:1;
+        /** infifo_l1_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_clr:1;
+        /** infifo_l1_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_clr:1;
+        /** infifo_l2_ovf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_clr:1;
+        /** infifo_l2_udf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_clr:1;
+        /** infifo_l3_ovf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_clr:1;
+        /** infifo_l3_udf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_clr:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_in_int_clr_chn_reg_t;
+
+/** Type of out_int_raw_chn register
+ *  Raw status interrupt of channeln
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel0.
+         */
+        uint32_t out_done_chn_int_raw:1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel0.
+         */
+        uint32_t out_eof_chn_int_raw:1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+         *  including owner error and the second and third word error of outlink descriptor for
+         *  Tx channel0.
+         */
+        uint32_t out_dscr_err_chn_int_raw:1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel0.
+         */
+        uint32_t out_total_eof_chn_int_raw:1;
+        /** outfifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_raw:1;
+        /** outfifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l1_udf_chn_int_raw:1;
+        /** outfifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_raw:1;
+        /** outfifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l2_udf_chn_int_raw:1;
+        /** outfifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_raw:1;
+        /** outfifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l3_udf_chn_int_raw:1;
+        /** out_link_switch_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+         *  channel0.
+         */
+        uint32_t out_link_switch_chn_int_raw:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_int_raw_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt of channeln
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st:1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st:1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st:1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st:1;
+        /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_chn_int_st:1;
+        /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_chn_int_st:1;
+        /** outfifo_l1_ovf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_st:1;
+        /** outfifo_l1_udf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_st:1;
+        /** outfifo_l3_ovf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_st:1;
+        /** outfifo_l3_udf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_st:1;
+        /** out_link_switch_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+         */
+        uint32_t out_link_switch_chn_int_st:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_int_st_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of channeln
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena:1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena:1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena:1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena:1;
+        /** outfifo_l1_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_ena:1;
+        /** outfifo_l1_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_ena:1;
+        /** outfifo_l2_ovf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_ena:1;
+        /** outfifo_l2_udf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_ena:1;
+        /** outfifo_l3_ovf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_ena:1;
+        /** outfifo_l3_udf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_ena:1;
+        /** out_link_switch_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+         */
+        uint32_t out_link_switch_chn_int_ena:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_int_ena_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of channeln
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr:1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr:1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr:1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr:1;
+        /** outfifo_l1_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_clr:1;
+        /** outfifo_l1_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_clr:1;
+        /** outfifo_l2_ovf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_clr:1;
+        /** outfifo_l2_udf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_clr:1;
+        /** outfifo_l3_ovf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_clr:1;
+        /** outfifo_l3_udf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_clr:1;
+        /** out_link_switch_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+         */
+        uint32_t out_link_switch_chn_int_clr:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_int_clr_chn_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of in_conf0_chn register
+ *  Configure 0 register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** in_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+         */
+        uint32_t in_rst_chn:1;
+        /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn:1;
+        /** mem_trans_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+         *  AXI_DMA.
+         */
+        uint32_t mem_trans_en_chn:1;
+        /** in_etm_en_chn : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+         *  task.
+         */
+        uint32_t in_etm_en_chn:1;
+        /** in_burst_size_sel_chn : R/W; bitpos: [6:4]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t in_burst_size_sel_chn:3;
+        /** in_cmd_disable_chn : R/W; bitpos: [7]; default: 0;
+         *  1:mean disable cmd of this ch0
+         */
+        uint32_t in_cmd_disable_chn:1;
+        /** in_ecc_aec_en_chn : R/W; bitpos: [8]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t in_ecc_aec_en_chn:1;
+        /** indscr_burst_en_chn : R/W; bitpos: [9]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t indscr_burst_en_chn:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_dma_in_conf0_chn_reg_t;
+
+/** Type of in_conf1_chn register
+ *  Configure 1 register of Rx channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_dma_in_conf1_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Pop control register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
+         *  This register stores the data popping from AXI_DMA FIFO.
+         */
+        uint32_t infifo_rdata_chn:12;
+        /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
+         *  Set this bit to pop data from AXI_DMA FIFO.
+         */
+        uint32_t infifo_pop_chn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_dma_in_pop_chn_reg_t;
+
+/** Type of in_link1_chn register
+ *  Link descriptor configure and control register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn:1;
+        /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn:1;
+        /** inlink_start_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn:1;
+        /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn:1;
+        /** inlink_park_chn : RO; bitpos: [4]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} axi_dma_in_link1_chn_reg_t;
+
+/** Type of in_link2_chn register
+ *  Link descriptor configure and control register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 20 least significant bits of the first inlink descriptor's
+         *  address.
+         */
+        uint32_t inlink_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_link2_chn_reg_t;
+
+/** Type of in_crc_init_data_chn register
+ *  This register is used to config chn crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of rx crc initial value
+         */
+        uint32_t in_crc_init_data_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_init_data_chn_reg_t;
+
+/** Type of rx_crc_width_chn register
+ *  This register is used to confiig rx chn crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_width_chn:2;
+        /** rx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_lautch_flga_chn:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_width_chn_reg_t;
+
+/** Type of in_crc_clear_chn register
+ *  This register is used to clear chn crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of rx crc result
+         */
+        uint32_t in_crc_clear_chn_reg:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_dma_in_crc_clear_chn_reg_t;
+
+/** Type of in_crc_final_result_chn register
+ *  This register is used to store chn crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of rx
+         */
+        uint32_t in_crc_final_result_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_final_result_chn_reg_t;
+
+/** Type of rx_crc_en_addr_chn register
+ *  This register is used to config chn crc en addr
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_en_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_addr_chn_reg_t;
+
+/** Type of rx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_wr_data_chn:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_addr_chn_reg_t;
+
+/** Type of out_conf0_ch0 register
+ *  Configure 0 register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_ch0:1;
+        /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch0:1;
+        /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_ch0:1;
+        /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is
+         *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+         */
+        uint32_t out_eof_mode_ch0:1;
+        /** out_etm_en_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_ch0:1;
+        /** out_burst_size_sel_ch0 : R/W; bitpos: [7:5]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t out_burst_size_sel_ch0:3;
+        /** out_cmd_disable_ch0 : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this ch0
+         */
+        uint32_t out_cmd_disable_ch0:1;
+        /** out_ecc_aec_en_ch0 : R/W; bitpos: [9]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t out_ecc_aec_en_ch0:1;
+        /** outdscr_burst_en_ch0 : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch0:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_conf0_ch0_reg_t;
+
+/** Type of out_conf1_chn register
+ *  Configure 1 register of Tx channeln
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_dma_out_conf1_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Push control register of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
+         *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_wdata_chn:9;
+        /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
+         *  Set this bit to push data into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_push_chn:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_dma_out_push_chn_reg_t;
+
+/** Type of out_link1_chn register
+ *  Link descriptor configure and control register of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn:1;
+        /** outlink_start_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn:1;
+        /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn:1;
+        /** outlink_park_chn : RO; bitpos: [3]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_dma_out_link1_chn_reg_t;
+
+/** Type of out_link2_chn register
+ *  Link descriptor configure and control register of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 32 least significant bits of the first outlink
+         *  descriptor's address.
+         */
+        uint32_t outlink_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_link2_chn_reg_t;
+
+/** Type of out_crc_init_data_chn register
+ *  This register is used to config chn crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of tx crc initial value
+         */
+        uint32_t out_crc_init_data_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_init_data_chn_reg_t;
+
+/** Type of tx_crc_width_chn register
+ *  This register is used to confiig tx chn crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_width_chn:2;
+        /** tx_crc_lautch_flga_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_lautch_flga_chn:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_width_chn_reg_t;
+
+/** Type of out_crc_clear_chn register
+ *  This register is used to clear chn crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of tx crc result
+         */
+        uint32_t out_crc_clear_chn_reg:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_dma_out_crc_clear_chn_reg_t;
+
+/** Type of out_crc_final_result_chn register
+ *  This register is used to store chn crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of tx
+         */
+        uint32_t out_crc_final_result_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_final_result_chn_reg_t;
+
+/** Type of tx_crc_en_wr_data_chn register
+ *  This resister is used to config chn crc en for every bit
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable tx ch0 crc 32bit on/off
+         */
+        uint32_t tx_crc_en_wr_data_chn:32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_en_addr_chn register
+ *  This register is used to config chn crc en addr
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_en_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_addr_chn_reg_t;
+
+/** Type of tx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_wr_data_chn:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_addr_chn_reg_t;
+
+/** Type of out_conf0_ch1 register
+ *  Configure 0 register of Tx channel1
+ */
+typedef union {
+    struct {
+        /** out_rst_ch1 : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_ch1:1;
+        /** out_loop_test_ch1 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch1:1;
+        /** out_auto_wrback_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_ch1:1;
+        /** out_eof_mode_ch1 : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is
+         *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+         */
+        uint32_t out_eof_mode_ch1:1;
+        /** out_etm_en_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_ch1:1;
+        /** out_burst_size_sel_ch1 : R/W; bitpos: [7:5]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t out_burst_size_sel_ch1:3;
+        /** out_cmd_disable_ch1 : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this ch1
+         */
+        uint32_t out_cmd_disable_ch1:1;
+        /** out_ecc_aec_en_ch1 : R/W; bitpos: [9]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t out_ecc_aec_en_ch1:1;
+        /** outdscr_burst_en_ch1 : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch1:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_conf0_ch1_reg_t;
+
+/** Type of out_conf0_ch2 register
+ *  Configure 0 register of Tx channel2
+ */
+typedef union {
+    struct {
+        /** out_rst_ch2 : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_ch2:1;
+        /** out_loop_test_ch2 : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_ch2:1;
+        /** out_auto_wrback_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_ch2:1;
+        /** out_eof_mode_ch2 : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is
+         *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+         */
+        uint32_t out_eof_mode_ch2:1;
+        /** out_etm_en_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_ch2:1;
+        /** out_burst_size_sel_ch2 : R/W; bitpos: [7:5]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t out_burst_size_sel_ch2:3;
+        /** out_cmd_disable_ch2 : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this ch2
+         */
+        uint32_t out_cmd_disable_ch2:1;
+        /** out_ecc_aec_en_ch2 : R/W; bitpos: [9]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t out_ecc_aec_en_ch2:1;
+        /** outdscr_burst_en_ch2 : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch2:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_dma_out_conf0_ch2_reg_t;
+
+/** Type of arb_timeout register
+ *  This retister is used to config arbiter time slice
+ */
+typedef union {
+    struct {
+        /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to config tx arbiter time out value
+         */
+        uint32_t arb_timeout_tx:16;
+        /** arb_timeout_rx : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to config rx arbiter time out value
+         */
+        uint32_t arb_timeout_rx:16;
+    };
+    uint32_t val;
+} axi_dma_arb_timeout_reg_t;
+
+/** Type of weight_en register
+ *  This register is used to config arbiter weight function to on or off
+ */
+typedef union {
+    struct {
+        /** weight_en_tx : R/W; bitpos: [0]; default: 0;
+         *  This register is used to config tx arbiter weight function  off/on
+         */
+        uint32_t weight_en_tx:1;
+        /** weight_en_rx : R/W; bitpos: [1]; default: 0;
+         *  This register is used to config rx arbiter weight function  off/on
+         */
+        uint32_t weight_en_rx:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_dma_weight_en_reg_t;
+
+/** Type of in_mem_conf register
+ *  Mem power configure register of Rx channel
+ */
+typedef union {
+    struct {
+        /** in_mem_clk_force_en : R/W; bitpos: [0]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t in_mem_clk_force_en:1;
+        /** in_mem_force_pu : R/W; bitpos: [1]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t in_mem_force_pu:1;
+        /** in_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t in_mem_force_pd:1;
+        /** out_mem_clk_force_en : R/W; bitpos: [3]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t out_mem_clk_force_en:1;
+        /** out_mem_force_pu : R/W; bitpos: [4]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t out_mem_force_pu:1;
+        /** out_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t out_mem_force_pd:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_dma_in_mem_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr:32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr:32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_end_addr_reg_t;
+
+/** Type of in_reset_avail_chn register
+ *  The rx channel n reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** in_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  rx chan0 reset valid reg.
+         */
+        uint32_t in_reset_avail_chn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_dma_in_reset_avail_chn_reg_t;
+
+/** Type of out_reset_avail_chn register
+ *  The tx channel n reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** out_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  tx chan0 reset valid reg.
+         */
+        uint32_t out_reset_avail_chn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_dma_out_reset_avail_chn_reg_t;
+
+/** Type of misc_conf register
+ *  MISC register
+ */
+typedef union {
+    struct {
+        /** axim_rst_wr_inter : R/W; bitpos: [0]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_wr FSM.
+         */
+        uint32_t axim_rst_wr_inter:1;
+        /** axim_rst_rd_inter : R/W; bitpos: [1]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_rd FSM.
+         */
+        uint32_t axim_rst_rd_inter:1;
+        uint32_t reserved_2:1;
+        /** arb_pri_dis : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to disable priority arbitration function.
+         */
+        uint32_t arb_pri_dis:1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} axi_dma_misc_conf_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of infifo_status_chn register
+ *  Receive FIFO status of Rx channel n
+ */
+typedef union {
+    struct {
+        /** infifo_l3_full_chn : RO; bitpos: [0]; default: 1;
+         *  L3 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_full_chn:1;
+        /** infifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_empty_chn:1;
+        /** infifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_l3_cnt_chn:6;
+        /** infifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_udf_chn:1;
+        /** infifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_ovf_chn:1;
+        /** infifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_full_chn:1;
+        /** infifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_empty_chn:1;
+        /** infifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_udf_chn:1;
+        /** infifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_ovf_chn:1;
+        /** infifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Rx RAM full signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_full_chn:1;
+        /** infifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Rx RAM empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_empty_chn:1;
+        /** infifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_udf_chn:1;
+        /** infifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_ovf_chn:1;
+        uint32_t reserved_18:5;
+        /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn:1;
+        /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn:1;
+        /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn:1;
+        /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn:1;
+        /** in_remain_under_5b_chn : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn:1;
+        /** in_remain_under_6b_chn : RO; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn:1;
+        /** in_remain_under_7b_chn : RO; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn:1;
+        /** in_remain_under_8b_chn : RO; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn:1;
+        /** in_buf_hungry_chn : RO; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_chn:1;
+    };
+    uint32_t val;
+} axi_dma_infifo_status_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Receive status of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn:18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn:2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} axi_dma_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Inlink descriptor address when EOF occurs of Rx channel n
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Inlink descriptor address when errors occur of Rx channel n
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data. Only used when peripheral is UHCI0.
+         */
+        uint32_t in_err_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Current inlink descriptor address of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current inlink descriptor x.
+         */
+        uint32_t inlink_dscr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  The last inlink descriptor address of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  The second-to-last inlink descriptor address of Rx channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf1_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Transmit FIFO status of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outfifo_l3_full_chn : RO; bitpos: [0]; default: 0;
+         *  L3 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_full_chn:1;
+        /** outfifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_empty_chn:1;
+        /** outfifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+         */
+        uint32_t outfifo_l3_cnt_chn:6;
+        /** outfifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_udf_chn:1;
+        /** outfifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_ovf_chn:1;
+        /** outfifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_full_chn:1;
+        /** outfifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_empty_chn:1;
+        /** outfifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_udf_chn:1;
+        /** outfifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_ovf_chn:1;
+        /** outfifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Tx RAM full signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_full_chn:1;
+        /** outfifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Tx RAM empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_empty_chn:1;
+        /** outfifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_udf_chn:1;
+        /** outfifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_ovf_chn:1;
+        uint32_t reserved_18:5;
+        /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn:1;
+        /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn:1;
+        /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn:1;
+        /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn:1;
+        /** out_remain_under_5b_chn : RO; bitpos: [27]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn:1;
+        /** out_remain_under_6b_chn : RO; bitpos: [28]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn:1;
+        /** out_remain_under_7b_chn : RO; bitpos: [29]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn:1;
+        /** out_remain_under_8b_chn : RO; bitpos: [30]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Transmit status of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn:18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_chn:2;
+        /** out_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_chn:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} axi_dma_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Outlink descriptor address when EOF occurs of Tx channeln
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_eof_bfr_des_addr_chn register
+ *  The last outlink descriptor address when EOF occurs of Tx channeln
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor before the last outlink
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_bfr_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Current outlink descriptor address of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current outlink descriptor y.
+         */
+        uint32_t outlink_dscr_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  The last outlink descriptor address of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  The second-to-last outlink descriptor address of Tx channeln
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor x-2.
+         */
+        uint32_t outlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf1_chn_reg_t;
+
+/** Type of wresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** wresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi wr response cnt reg.
+         */
+        uint32_t wresp_cnt:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_dma_wresp_cnt_reg_t;
+
+/** Type of rresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** rresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi rd response cnt reg.
+         */
+        uint32_t rresp_cnt:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_dma_rresp_cnt_reg_t;
+
+/** Type of infifo_status1_chn register
+ *  Receive FIFO status of Rx channel n
+ */
+typedef union {
+    struct {
+        /** l1infifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l1infifo_cnt_chn:6;
+        /** l2infifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l2infifo_cnt_chn:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_dma_infifo_status1_chn_reg_t;
+
+/** Type of outfifo_status1_chn register
+ *  Receive FIFO status of Tx channel n
+ */
+typedef union {
+    struct {
+        /** l1outfifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l1outfifo_cnt_chn:6;
+        /** l2outfifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l2outfifo_cnt_chn:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status1_chn_reg_t;
+
+/** Type of link_switch_state register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** link_switch_state_ch0 : R/W; bitpos: [0]; default: 0;
+         *  The register that confirm ch dscr switch success
+         */
+        uint32_t link_switch_state_ch0:1;
+        /** link_switch_state_ch1 : R/W; bitpos: [1]; default: 0;
+         *  The register that confirm ch dscr switch success
+         */
+        uint32_t link_switch_state_ch1:1;
+        /** link_switch_state_ch2 : R/W; bitpos: [2]; default: 0;
+         *  The register that confirm ch dscr switch success
+         */
+        uint32_t link_switch_state_ch2:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_dma_link_switch_state_reg_t;
+
+
+/** Group: Priority Registers */
+/** Type of in_pri_chn register
+ *  Priority register of Rx channel n
+ */
+typedef union {
+    struct {
+        /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+         */
+        uint32_t rx_pri_chn:4;
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Rx channel 0
+         */
+        uint32_t rx_ch_arb_weigh_chn:4;
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} axi_dma_in_pri_chn_reg_t;
+
+/** Type of out_pri_chn register
+ *  Priority register of Tx channeln.
+ */
+typedef union {
+    struct {
+        /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Tx channel0. The larger of the value the higher of the priority.
+         */
+        uint32_t tx_pri_chn:4;
+        /** tx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Tx channel0
+         */
+        uint32_t tx_ch_arb_weigh_chn:4;
+        /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t tx_arb_weigh_opt_dir_chn:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} axi_dma_out_pri_chn_reg_t;
+
+
+/** Group: Peripheral Select Registers */
+/** Type of in_peri_sel_chn register
+ *  Peripheral selection of Rx channel n
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_in_sel_chn:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_dma_in_peri_sel_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Peripheral selection of Tx channeln
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_out_sel_chn:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_dma_out_peri_sel_chn_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of rx_crc_en_wr_data_chn register
+ *  This resister is used to config chn crc en for every bit
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable rx ch0 crc 32bit on/off
+         */
+        uint32_t rx_crc_en_wr_data_chn:32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_wr_data_chn_reg_t;
+
+
+/** Group: Debug Registers */
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_dma_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_low_reg_t;
+
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36712768;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} axi_dma_date_reg_t;
+
+
+typedef struct {
+    volatile axi_dma_in_int_raw_chn_reg_t in_int_raw_ch0;
+    volatile axi_dma_in_int_st_chn_reg_t in_int_st_ch0;
+    volatile axi_dma_in_int_ena_chn_reg_t in_int_ena_ch0;
+    volatile axi_dma_in_int_clr_chn_reg_t in_int_clr_ch0;
+    volatile axi_dma_in_conf0_chn_reg_t in_conf0_ch0;
+    volatile axi_dma_in_conf1_chn_reg_t in_conf1_ch0;
+    volatile axi_dma_infifo_status_chn_reg_t infifo_status_ch0;
+    volatile axi_dma_in_pop_chn_reg_t in_pop_ch0;
+    volatile axi_dma_in_link1_chn_reg_t in_link1_ch0;
+    volatile axi_dma_in_link2_chn_reg_t in_link2_ch0;
+    volatile axi_dma_in_state_chn_reg_t in_state_ch0;
+    volatile axi_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
+    volatile axi_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
+    volatile axi_dma_in_dscr_chn_reg_t in_dscr_ch0;
+    volatile axi_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
+    volatile axi_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
+    volatile axi_dma_in_pri_chn_reg_t in_pri_ch0;
+    volatile axi_dma_in_peri_sel_chn_reg_t in_peri_sel_ch0;
+    volatile axi_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch0;
+    volatile axi_dma_rx_crc_width_chn_reg_t rx_crc_width_ch0;
+    volatile axi_dma_in_crc_clear_chn_reg_t in_crc_clear_ch0;
+    volatile axi_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch0;
+    volatile axi_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch0;
+    volatile axi_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch0;
+    volatile axi_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch0;
+    volatile axi_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch0;
+    volatile axi_dma_in_int_raw_chn_reg_t in_int_raw_ch1;
+    volatile axi_dma_in_int_st_chn_reg_t in_int_st_ch1;
+    volatile axi_dma_in_int_ena_chn_reg_t in_int_ena_ch1;
+    volatile axi_dma_in_int_clr_chn_reg_t in_int_clr_ch1;
+    volatile axi_dma_in_conf0_chn_reg_t in_conf0_ch1;
+    volatile axi_dma_in_conf1_chn_reg_t in_conf1_ch1;
+    volatile axi_dma_infifo_status_chn_reg_t infifo_status_ch1;
+    volatile axi_dma_in_pop_chn_reg_t in_pop_ch1;
+    volatile axi_dma_in_link1_chn_reg_t in_link1_ch1;
+    volatile axi_dma_in_link2_chn_reg_t in_link2_ch1;
+    volatile axi_dma_in_state_chn_reg_t in_state_ch1;
+    volatile axi_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
+    volatile axi_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
+    volatile axi_dma_in_dscr_chn_reg_t in_dscr_ch1;
+    volatile axi_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
+    volatile axi_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
+    volatile axi_dma_in_pri_chn_reg_t in_pri_ch1;
+    volatile axi_dma_in_peri_sel_chn_reg_t in_peri_sel_ch1;
+    volatile axi_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch1;
+    volatile axi_dma_rx_crc_width_chn_reg_t rx_crc_width_ch1;
+    volatile axi_dma_in_crc_clear_chn_reg_t in_crc_clear_ch1;
+    volatile axi_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch1;
+    volatile axi_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch1;
+    volatile axi_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch1;
+    volatile axi_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch1;
+    volatile axi_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch1;
+    volatile axi_dma_in_int_raw_chn_reg_t in_int_raw_ch2;
+    volatile axi_dma_in_int_st_chn_reg_t in_int_st_ch2;
+    volatile axi_dma_in_int_ena_chn_reg_t in_int_ena_ch2;
+    volatile axi_dma_in_int_clr_chn_reg_t in_int_clr_ch2;
+    volatile axi_dma_in_conf0_chn_reg_t in_conf0_ch2;
+    volatile axi_dma_in_conf1_chn_reg_t in_conf1_ch2;
+    volatile axi_dma_infifo_status_chn_reg_t infifo_status_ch2;
+    volatile axi_dma_in_pop_chn_reg_t in_pop_ch2;
+    volatile axi_dma_in_link1_chn_reg_t in_link1_ch2;
+    volatile axi_dma_in_link2_chn_reg_t in_link2_ch2;
+    volatile axi_dma_in_state_chn_reg_t in_state_ch2;
+    volatile axi_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2;
+    volatile axi_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2;
+    volatile axi_dma_in_dscr_chn_reg_t in_dscr_ch2;
+    volatile axi_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2;
+    volatile axi_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2;
+    volatile axi_dma_in_pri_chn_reg_t in_pri_ch2;
+    volatile axi_dma_in_peri_sel_chn_reg_t in_peri_sel_ch2;
+    volatile axi_dma_in_crc_init_data_chn_reg_t in_crc_init_data_ch2;
+    volatile axi_dma_rx_crc_width_chn_reg_t rx_crc_width_ch2;
+    volatile axi_dma_in_crc_clear_chn_reg_t in_crc_clear_ch2;
+    volatile axi_dma_in_crc_final_result_chn_reg_t in_crc_final_result_ch2;
+    volatile axi_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data_ch2;
+    volatile axi_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr_ch2;
+    volatile axi_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data_ch2;
+    volatile axi_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr_ch2;
+    volatile axi_dma_out_int_raw_chn_reg_t out_int_raw_ch0;
+    volatile axi_dma_out_int_st_chn_reg_t out_int_st_ch0;
+    volatile axi_dma_out_int_ena_chn_reg_t out_int_ena_ch0;
+    volatile axi_dma_out_int_clr_chn_reg_t out_int_clr_ch0;
+    volatile axi_dma_out_conf0_ch0_reg_t out_conf0_ch0;
+    volatile axi_dma_out_conf1_chn_reg_t out_conf1_ch0;
+    volatile axi_dma_outfifo_status_chn_reg_t outfifo_status_ch0;
+    volatile axi_dma_out_push_chn_reg_t out_push_ch0;
+    volatile axi_dma_out_link1_chn_reg_t out_link1_ch0;
+    volatile axi_dma_out_link2_chn_reg_t out_link2_ch0;
+    volatile axi_dma_out_state_chn_reg_t out_state_ch0;
+    volatile axi_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
+    volatile axi_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0;
+    volatile axi_dma_out_dscr_chn_reg_t out_dscr_ch0;
+    volatile axi_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
+    volatile axi_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
+    volatile axi_dma_out_pri_chn_reg_t out_pri_ch0;
+    volatile axi_dma_out_peri_sel_chn_reg_t out_peri_sel_ch0;
+    volatile axi_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch0;
+    volatile axi_dma_tx_crc_width_chn_reg_t tx_crc_width_ch0;
+    volatile axi_dma_out_crc_clear_chn_reg_t out_crc_clear_ch0;
+    volatile axi_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch0;
+    volatile axi_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch0;
+    volatile axi_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch0;
+    volatile axi_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch0;
+    volatile axi_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch0;
+    volatile axi_dma_out_int_raw_chn_reg_t out_int_raw_ch1;
+    volatile axi_dma_out_int_st_chn_reg_t out_int_st_ch1;
+    volatile axi_dma_out_int_ena_chn_reg_t out_int_ena_ch1;
+    volatile axi_dma_out_int_clr_chn_reg_t out_int_clr_ch1;
+    volatile axi_dma_out_conf0_ch1_reg_t out_conf0_ch1;
+    volatile axi_dma_out_conf1_chn_reg_t out_conf1_ch1;
+    volatile axi_dma_outfifo_status_chn_reg_t outfifo_status_ch1;
+    volatile axi_dma_out_push_chn_reg_t out_push_ch1;
+    volatile axi_dma_out_link1_chn_reg_t out_link1_ch1;
+    volatile axi_dma_out_link2_chn_reg_t out_link2_ch1;
+    volatile axi_dma_out_state_chn_reg_t out_state_ch1;
+    volatile axi_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
+    volatile axi_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1;
+    volatile axi_dma_out_dscr_chn_reg_t out_dscr_ch1;
+    volatile axi_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
+    volatile axi_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
+    volatile axi_dma_out_pri_chn_reg_t out_pri_ch1;
+    volatile axi_dma_out_peri_sel_chn_reg_t out_peri_sel_ch1;
+    volatile axi_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch1;
+    volatile axi_dma_tx_crc_width_chn_reg_t tx_crc_width_ch1;
+    volatile axi_dma_out_crc_clear_chn_reg_t out_crc_clear_ch1;
+    volatile axi_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch1;
+    volatile axi_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch1;
+    volatile axi_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch1;
+    volatile axi_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch1;
+    volatile axi_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch1;
+    volatile axi_dma_out_int_raw_chn_reg_t out_int_raw_ch2;
+    volatile axi_dma_out_int_st_chn_reg_t out_int_st_ch2;
+    volatile axi_dma_out_int_ena_chn_reg_t out_int_ena_ch2;
+    volatile axi_dma_out_int_clr_chn_reg_t out_int_clr_ch2;
+    volatile axi_dma_out_conf0_ch2_reg_t out_conf0_ch2;
+    volatile axi_dma_out_conf1_chn_reg_t out_conf1_ch2;
+    volatile axi_dma_outfifo_status_chn_reg_t outfifo_status_ch2;
+    volatile axi_dma_out_push_chn_reg_t out_push_ch2;
+    volatile axi_dma_out_link1_chn_reg_t out_link1_ch2;
+    volatile axi_dma_out_link2_chn_reg_t out_link2_ch2;
+    volatile axi_dma_out_state_chn_reg_t out_state_ch2;
+    volatile axi_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2;
+    volatile axi_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2;
+    volatile axi_dma_out_dscr_chn_reg_t out_dscr_ch2;
+    volatile axi_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2;
+    volatile axi_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2;
+    volatile axi_dma_out_pri_chn_reg_t out_pri_ch2;
+    volatile axi_dma_out_peri_sel_chn_reg_t out_peri_sel_ch2;
+    volatile axi_dma_out_crc_init_data_chn_reg_t out_crc_init_data_ch2;
+    volatile axi_dma_tx_crc_width_chn_reg_t tx_crc_width_ch2;
+    volatile axi_dma_out_crc_clear_chn_reg_t out_crc_clear_ch2;
+    volatile axi_dma_out_crc_final_result_chn_reg_t out_crc_final_result_ch2;
+    volatile axi_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data_ch2;
+    volatile axi_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr_ch2;
+    volatile axi_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data_ch2;
+    volatile axi_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr_ch2;
+    volatile axi_dma_arb_timeout_reg_t arb_timeout;
+    volatile axi_dma_weight_en_reg_t weight_en;
+    volatile axi_dma_in_mem_conf_reg_t in_mem_conf;
+    volatile axi_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile axi_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile axi_dma_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile axi_dma_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile axi_dma_in_reset_avail_chn_reg_t in_reset_avail_chn[3];
+    volatile axi_dma_out_reset_avail_chn_reg_t out_reset_avail_chn[3];
+    uint32_t reserved_2a4;
+    volatile axi_dma_misc_conf_reg_t misc_conf;
+    volatile axi_dma_rdn_result_reg_t rdn_result;
+    volatile axi_dma_rdn_eco_high_reg_t rdn_eco_high;
+    volatile axi_dma_rdn_eco_low_reg_t rdn_eco_low;
+    volatile axi_dma_wresp_cnt_reg_t wresp_cnt;
+    volatile axi_dma_rresp_cnt_reg_t rresp_cnt;
+    volatile axi_dma_infifo_status1_chn_reg_t infifo_status1_chn[3];
+    volatile axi_dma_outfifo_status1_chn_reg_t outfifo_status1_chn[3];
+    volatile axi_dma_date_reg_t date;
+    volatile axi_dma_link_switch_state_reg_t link_switch_state;
+} axi_dma_dev_t;
+
+extern axi_dma_dev_t AXI_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(axi_dma_dev_t) == 0x2e0, "Invalid size of axi_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/axi_dma_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/axi_dma_reg.h
new file mode 100644
index 0000000000..5d0e1fb808
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/axi_dma_reg.h
@@ -0,0 +1,5757 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AXI_DMA_IN_INT_RAW_CH0_REG register
+ *  Raw status interrupt of channel 0
+ */
+#define AXI_DMA_IN_INT_RAW_CH0_REG (DR_REG_AXI_DMA_BASE + 0x0)
+/** AXI_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_RAW_M  (AXI_DMA_IN_DONE_CH0_INT_RAW_V << AXI_DMA_IN_DONE_CH0_INT_RAW_S)
+#define AXI_DMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_RAW_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+ *  interrupt is reserved.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+ *  including owner error and the second and third word error of inlink descriptor for
+ *  Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_S  10
+
+/** AXI_DMA_IN_INT_ST_CH0_REG register
+ *  Masked interrupt of channel 0
+ */
+#define AXI_DMA_IN_INT_ST_CH0_REG (DR_REG_AXI_DMA_BASE + 0x4)
+/** AXI_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_ST    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_ST_M  (AXI_DMA_IN_DONE_CH0_INT_ST_V << AXI_DMA_IN_DONE_CH0_INT_ST_S)
+#define AXI_DMA_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_ST_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_ST_V << AXI_DMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_ST_V << AXI_DMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S  4
+/** AXI_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST    (BIT(5))
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST_M  (AXI_DMA_INFIFO_OVF_CH0_INT_ST_V << AXI_DMA_INFIFO_OVF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST_S  5
+/** AXI_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST    (BIT(6))
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST_M  (AXI_DMA_INFIFO_UDF_CH0_INT_ST_V << AXI_DMA_INFIFO_UDF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST_S  6
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST    (BIT(7))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_S  7
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST    (BIT(8))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_S  10
+
+/** AXI_DMA_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of channel 0
+ */
+#define AXI_DMA_IN_INT_ENA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x8)
+/** AXI_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_ENA_M  (AXI_DMA_IN_DONE_CH0_INT_ENA_V << AXI_DMA_IN_DONE_CH0_INT_ENA_S)
+#define AXI_DMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_ENA_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_S  10
+
+/** AXI_DMA_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of channel 0
+ */
+#define AXI_DMA_IN_INT_CLR_CH0_REG (DR_REG_AXI_DMA_BASE + 0xc)
+/** AXI_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_CLR_M  (AXI_DMA_IN_DONE_CH0_INT_CLR_V << AXI_DMA_IN_DONE_CH0_INT_CLR_S)
+#define AXI_DMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_CLR_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_S  10
+
+/** AXI_DMA_IN_CONF0_CH0_REG register
+ *  Configure 0 register of Rx channel 0
+ */
+#define AXI_DMA_IN_CONF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x10)
+/** AXI_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define AXI_DMA_IN_RST_CH0    (BIT(0))
+#define AXI_DMA_IN_RST_CH0_M  (AXI_DMA_IN_RST_CH0_V << AXI_DMA_IN_RST_CH0_S)
+#define AXI_DMA_IN_RST_CH0_V  0x00000001U
+#define AXI_DMA_IN_RST_CH0_S  0
+/** AXI_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_LOOP_TEST_CH0    (BIT(1))
+#define AXI_DMA_IN_LOOP_TEST_CH0_M  (AXI_DMA_IN_LOOP_TEST_CH0_V << AXI_DMA_IN_LOOP_TEST_CH0_S)
+#define AXI_DMA_IN_LOOP_TEST_CH0_V  0x00000001U
+#define AXI_DMA_IN_LOOP_TEST_CH0_S  1
+/** AXI_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+ *  AXI_DMA.
+ */
+#define AXI_DMA_MEM_TRANS_EN_CH0    (BIT(2))
+#define AXI_DMA_MEM_TRANS_EN_CH0_M  (AXI_DMA_MEM_TRANS_EN_CH0_V << AXI_DMA_MEM_TRANS_EN_CH0_S)
+#define AXI_DMA_MEM_TRANS_EN_CH0_V  0x00000001U
+#define AXI_DMA_MEM_TRANS_EN_CH0_S  2
+/** AXI_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_IN_ETM_EN_CH0    (BIT(3))
+#define AXI_DMA_IN_ETM_EN_CH0_M  (AXI_DMA_IN_ETM_EN_CH0_V << AXI_DMA_IN_ETM_EN_CH0_S)
+#define AXI_DMA_IN_ETM_EN_CH0_V  0x00000001U
+#define AXI_DMA_IN_ETM_EN_CH0_S  3
+/** AXI_DMA_IN_BURST_SIZE_SEL_CH0 : R/W; bitpos: [6:4]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0    0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0_M  (AXI_DMA_IN_BURST_SIZE_SEL_CH0_V << AXI_DMA_IN_BURST_SIZE_SEL_CH0_S)
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0_V  0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0_S  4
+/** AXI_DMA_IN_CMD_DISABLE_CH0 : R/W; bitpos: [7]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_IN_CMD_DISABLE_CH0    (BIT(7))
+#define AXI_DMA_IN_CMD_DISABLE_CH0_M  (AXI_DMA_IN_CMD_DISABLE_CH0_V << AXI_DMA_IN_CMD_DISABLE_CH0_S)
+#define AXI_DMA_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define AXI_DMA_IN_CMD_DISABLE_CH0_S  7
+/** AXI_DMA_IN_ECC_AEC_EN_CH0 : R/W; bitpos: [8]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_IN_ECC_AEC_EN_CH0    (BIT(8))
+#define AXI_DMA_IN_ECC_AEC_EN_CH0_M  (AXI_DMA_IN_ECC_AEC_EN_CH0_V << AXI_DMA_IN_ECC_AEC_EN_CH0_S)
+#define AXI_DMA_IN_ECC_AEC_EN_CH0_V  0x00000001U
+#define AXI_DMA_IN_ECC_AEC_EN_CH0_S  8
+/** AXI_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_INDSCR_BURST_EN_CH0    (BIT(9))
+#define AXI_DMA_INDSCR_BURST_EN_CH0_M  (AXI_DMA_INDSCR_BURST_EN_CH0_V << AXI_DMA_INDSCR_BURST_EN_CH0_S)
+#define AXI_DMA_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define AXI_DMA_INDSCR_BURST_EN_CH0_S  9
+
+/** AXI_DMA_IN_CONF1_CH0_REG register
+ *  Configure 1 register of Rx channel 0
+ */
+#define AXI_DMA_IN_CONF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x14)
+/** AXI_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_IN_CHECK_OWNER_CH0    (BIT(12))
+#define AXI_DMA_IN_CHECK_OWNER_CH0_M  (AXI_DMA_IN_CHECK_OWNER_CH0_V << AXI_DMA_IN_CHECK_OWNER_CH0_S)
+#define AXI_DMA_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define AXI_DMA_IN_CHECK_OWNER_CH0_S  12
+
+/** AXI_DMA_INFIFO_STATUS_CH0_REG register
+ *  Receive FIFO status of Rx channel 0
+ */
+#define AXI_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AXI_DMA_BASE + 0x18)
+/** AXI_DMA_INFIFO_L3_FULL_CH0 : RO; bitpos: [0]; default: 1;
+ *  L3 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_FULL_CH0    (BIT(0))
+#define AXI_DMA_INFIFO_L3_FULL_CH0_M  (AXI_DMA_INFIFO_L3_FULL_CH0_V << AXI_DMA_INFIFO_L3_FULL_CH0_S)
+#define AXI_DMA_INFIFO_L3_FULL_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_FULL_CH0_S  0
+/** AXI_DMA_INFIFO_L3_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  L3 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0    (BIT(1))
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0_M  (AXI_DMA_INFIFO_L3_EMPTY_CH0_V << AXI_DMA_INFIFO_L3_EMPTY_CH0_S)
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0_S  1
+/** AXI_DMA_INFIFO_L3_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_CNT_CH0    0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH0_M  (AXI_DMA_INFIFO_L3_CNT_CH0_V << AXI_DMA_INFIFO_L3_CNT_CH0_S)
+#define AXI_DMA_INFIFO_L3_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH0_S  2
+/** AXI_DMA_INFIFO_L3_UDF_CH0 : RO; bitpos: [8]; default: 0;
+ *  L3 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0    (BIT(8))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_M  (AXI_DMA_INFIFO_L3_UDF_CH0_V << AXI_DMA_INFIFO_L3_UDF_CH0_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0 : RO; bitpos: [9]; default: 0;
+ *  L3 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_M  (AXI_DMA_INFIFO_L3_OVF_CH0_V << AXI_DMA_INFIFO_L3_OVF_CH0_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_S  9
+/** AXI_DMA_INFIFO_L1_FULL_CH0 : RO; bitpos: [10]; default: 0;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_FULL_CH0    (BIT(10))
+#define AXI_DMA_INFIFO_L1_FULL_CH0_M  (AXI_DMA_INFIFO_L1_FULL_CH0_V << AXI_DMA_INFIFO_L1_FULL_CH0_S)
+#define AXI_DMA_INFIFO_L1_FULL_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_FULL_CH0_S  10
+/** AXI_DMA_INFIFO_L1_EMPTY_CH0 : RO; bitpos: [11]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0    (BIT(11))
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0_M  (AXI_DMA_INFIFO_L1_EMPTY_CH0_V << AXI_DMA_INFIFO_L1_EMPTY_CH0_S)
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0_S  11
+/** AXI_DMA_INFIFO_L1_UDF_CH0 : RO; bitpos: [12]; default: 0;
+ *  L1 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0    (BIT(12))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_M  (AXI_DMA_INFIFO_L1_UDF_CH0_V << AXI_DMA_INFIFO_L1_UDF_CH0_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_S  12
+/** AXI_DMA_INFIFO_L1_OVF_CH0 : RO; bitpos: [13]; default: 0;
+ *  L1 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0    (BIT(13))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_M  (AXI_DMA_INFIFO_L1_OVF_CH0_V << AXI_DMA_INFIFO_L1_OVF_CH0_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_S  13
+/** AXI_DMA_INFIFO_L2_FULL_CH0 : RO; bitpos: [14]; default: 0;
+ *  L2 Rx RAM full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_FULL_CH0    (BIT(14))
+#define AXI_DMA_INFIFO_L2_FULL_CH0_M  (AXI_DMA_INFIFO_L2_FULL_CH0_V << AXI_DMA_INFIFO_L2_FULL_CH0_S)
+#define AXI_DMA_INFIFO_L2_FULL_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_FULL_CH0_S  14
+/** AXI_DMA_INFIFO_L2_EMPTY_CH0 : RO; bitpos: [15]; default: 1;
+ *  L2 Rx RAM empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0    (BIT(15))
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0_M  (AXI_DMA_INFIFO_L2_EMPTY_CH0_V << AXI_DMA_INFIFO_L2_EMPTY_CH0_S)
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0_S  15
+/** AXI_DMA_INFIFO_L2_UDF_CH0 : RO; bitpos: [16]; default: 0;
+ *  L2 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0    (BIT(16))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_M  (AXI_DMA_INFIFO_L2_UDF_CH0_V << AXI_DMA_INFIFO_L2_UDF_CH0_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_S  16
+/** AXI_DMA_INFIFO_L2_OVF_CH0 : RO; bitpos: [17]; default: 0;
+ *  L2 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0    (BIT(17))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_M  (AXI_DMA_INFIFO_L2_OVF_CH0_V << AXI_DMA_INFIFO_L2_OVF_CH0_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_S  17
+/** AXI_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_1B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_1B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0_S  23
+/** AXI_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_2B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_2B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0_S  24
+/** AXI_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_3B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_3B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0_S  25
+/** AXI_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_4B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_4B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0_S  26
+/** AXI_DMA_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0    (BIT(27))
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_5B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_5B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0_S  27
+/** AXI_DMA_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0    (BIT(28))
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_6B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_6B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0_S  28
+/** AXI_DMA_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0    (BIT(29))
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_7B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_7B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0_S  29
+/** AXI_DMA_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0    (BIT(30))
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_8B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_8B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0_S  30
+/** AXI_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_BUF_HUNGRY_CH0    (BIT(31))
+#define AXI_DMA_IN_BUF_HUNGRY_CH0_M  (AXI_DMA_IN_BUF_HUNGRY_CH0_V << AXI_DMA_IN_BUF_HUNGRY_CH0_S)
+#define AXI_DMA_IN_BUF_HUNGRY_CH0_V  0x00000001U
+#define AXI_DMA_IN_BUF_HUNGRY_CH0_S  31
+
+/** AXI_DMA_IN_POP_CH0_REG register
+ *  Pop control register of Rx channel 0
+ */
+#define AXI_DMA_IN_POP_CH0_REG (DR_REG_AXI_DMA_BASE + 0x1c)
+/** AXI_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_RDATA_CH0    0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH0_M  (AXI_DMA_INFIFO_RDATA_CH0_V << AXI_DMA_INFIFO_RDATA_CH0_S)
+#define AXI_DMA_INFIFO_RDATA_CH0_V  0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH0_S  0
+/** AXI_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_POP_CH0    (BIT(12))
+#define AXI_DMA_INFIFO_POP_CH0_M  (AXI_DMA_INFIFO_POP_CH0_V << AXI_DMA_INFIFO_POP_CH0_S)
+#define AXI_DMA_INFIFO_POP_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_POP_CH0_S  12
+
+/** AXI_DMA_IN_LINK1_CH0_REG register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+#define AXI_DMA_IN_LINK1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x20)
+/** AXI_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address when there are some
+ *  errors in current receiving data.
+ */
+#define AXI_DMA_INLINK_AUTO_RET_CH0    (BIT(0))
+#define AXI_DMA_INLINK_AUTO_RET_CH0_M  (AXI_DMA_INLINK_AUTO_RET_CH0_V << AXI_DMA_INLINK_AUTO_RET_CH0_S)
+#define AXI_DMA_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_AUTO_RET_CH0_S  0
+/** AXI_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_STOP_CH0    (BIT(1))
+#define AXI_DMA_INLINK_STOP_CH0_M  (AXI_DMA_INLINK_STOP_CH0_V << AXI_DMA_INLINK_STOP_CH0_S)
+#define AXI_DMA_INLINK_STOP_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_STOP_CH0_S  1
+/** AXI_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_START_CH0    (BIT(2))
+#define AXI_DMA_INLINK_START_CH0_M  (AXI_DMA_INLINK_START_CH0_V << AXI_DMA_INLINK_START_CH0_S)
+#define AXI_DMA_INLINK_START_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_START_CH0_S  2
+/** AXI_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define AXI_DMA_INLINK_RESTART_CH0    (BIT(3))
+#define AXI_DMA_INLINK_RESTART_CH0_M  (AXI_DMA_INLINK_RESTART_CH0_V << AXI_DMA_INLINK_RESTART_CH0_S)
+#define AXI_DMA_INLINK_RESTART_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_RESTART_CH0_S  3
+/** AXI_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define AXI_DMA_INLINK_PARK_CH0    (BIT(4))
+#define AXI_DMA_INLINK_PARK_CH0_M  (AXI_DMA_INLINK_PARK_CH0_V << AXI_DMA_INLINK_PARK_CH0_S)
+#define AXI_DMA_INLINK_PARK_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_PARK_CH0_S  4
+
+/** AXI_DMA_IN_LINK2_CH0_REG register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+#define AXI_DMA_IN_LINK2_CH0_REG (DR_REG_AXI_DMA_BASE + 0x24)
+/** AXI_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define AXI_DMA_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH0_M  (AXI_DMA_INLINK_ADDR_CH0_V << AXI_DMA_INLINK_ADDR_CH0_S)
+#define AXI_DMA_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_STATE_CH0_REG register
+ *  Receive status of Rx channel 0
+ */
+#define AXI_DMA_IN_STATE_CH0_REG (DR_REG_AXI_DMA_BASE + 0x28)
+/** AXI_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0_M  (AXI_DMA_INLINK_DSCR_ADDR_CH0_V << AXI_DMA_INLINK_DSCR_ADDR_CH0_S)
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0_S  0
+/** AXI_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_DSCR_STATE_CH0    0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH0_M  (AXI_DMA_IN_DSCR_STATE_CH0_V << AXI_DMA_IN_DSCR_STATE_CH0_S)
+#define AXI_DMA_IN_DSCR_STATE_CH0_V  0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH0_S  18
+/** AXI_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_STATE_CH0    0x00000007U
+#define AXI_DMA_IN_STATE_CH0_M  (AXI_DMA_IN_STATE_CH0_V << AXI_DMA_IN_STATE_CH0_S)
+#define AXI_DMA_IN_STATE_CH0_V  0x00000007U
+#define AXI_DMA_IN_STATE_CH0_S  20
+
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Inlink descriptor address when EOF occurs of Rx channel 0
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x2c)
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_M  (AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Inlink descriptor address when errors occur of Rx channel 0
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x30)
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_M  (AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_DSCR_CH0_REG register
+ *  Current inlink descriptor address of Rx channel 0
+ */
+#define AXI_DMA_IN_DSCR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x34)
+/** AXI_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define AXI_DMA_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH0_M  (AXI_DMA_INLINK_DSCR_CH0_V << AXI_DMA_INLINK_DSCR_CH0_S)
+#define AXI_DMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH0_S  0
+
+/** AXI_DMA_IN_DSCR_BF0_CH0_REG register
+ *  The last inlink descriptor address of Rx channel 0
+ */
+#define AXI_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x38)
+/** AXI_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define AXI_DMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH0_M  (AXI_DMA_INLINK_DSCR_BF0_CH0_V << AXI_DMA_INLINK_DSCR_BF0_CH0_S)
+#define AXI_DMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH0_S  0
+
+/** AXI_DMA_IN_DSCR_BF1_CH0_REG register
+ *  The second-to-last inlink descriptor address of Rx channel 0
+ */
+#define AXI_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x3c)
+/** AXI_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define AXI_DMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH0_M  (AXI_DMA_INLINK_DSCR_BF1_CH0_V << AXI_DMA_INLINK_DSCR_BF1_CH0_S)
+#define AXI_DMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH0_S  0
+
+/** AXI_DMA_IN_PRI_CH0_REG register
+ *  Priority register of Rx channel 0
+ */
+#define AXI_DMA_IN_PRI_CH0_REG (DR_REG_AXI_DMA_BASE + 0x40)
+/** AXI_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_RX_PRI_CH0    0x0000000FU
+#define AXI_DMA_RX_PRI_CH0_M  (AXI_DMA_RX_PRI_CH0_V << AXI_DMA_RX_PRI_CH0_S)
+#define AXI_DMA_RX_PRI_CH0_V  0x0000000FU
+#define AXI_DMA_RX_PRI_CH0_S  0
+/** AXI_DMA_RX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Rx channel 0
+ */
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0    0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0_M  (AXI_DMA_RX_CH_ARB_WEIGH_CH0_V << AXI_DMA_RX_CH_ARB_WEIGH_CH0_S)
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0_V  0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0_S  4
+/** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S)
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V  0x00000001U
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S  8
+
+/** AXI_DMA_IN_PERI_SEL_CH0_REG register
+ *  Peripheral selection of Rx channel 0
+ */
+#define AXI_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x44)
+/** AXI_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_IN_SEL_CH0    0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH0_M  (AXI_DMA_PERI_IN_SEL_CH0_V << AXI_DMA_PERI_IN_SEL_CH0_S)
+#define AXI_DMA_PERI_IN_SEL_CH0_V  0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH0_S  0
+
+/** AXI_DMA_IN_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x48)
+/** AXI_DMA_IN_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_M  (AXI_DMA_IN_CRC_INIT_DATA_CH0_V << AXI_DMA_IN_CRC_INIT_DATA_CH0_S)
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_S  0
+
+/** AXI_DMA_RX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH0_REG (DR_REG_AXI_DMA_BASE + 0x4c)
+/** AXI_DMA_RX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH0    0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH0_M  (AXI_DMA_RX_CRC_WIDTH_CH0_V << AXI_DMA_RX_CRC_WIDTH_CH0_S)
+#define AXI_DMA_RX_CRC_WIDTH_CH0_V  0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH0_S  0
+/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_M  (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S)
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AXI_DMA_IN_CRC_CLEAR_CH0_REG register
+ *  This register is used to clear ch0 crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x50)
+/** AXI_DMA_IN_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH0    (BIT(0))
+#define AXI_DMA_IN_CRC_CLEAR_CH0_M  (AXI_DMA_IN_CRC_CLEAR_CH0_V << AXI_DMA_IN_CRC_CLEAR_CH0_S)
+#define AXI_DMA_IN_CRC_CLEAR_CH0_V  0x00000001U
+#define AXI_DMA_IN_CRC_CLEAR_CH0_S  0
+
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_REG (DR_REG_AXI_DMA_BASE + 0x54)
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_M  (AXI_DMA_IN_CRC_FINAL_RESULT_CH0_V << AXI_DMA_IN_CRC_FINAL_RESULT_CH0_S)
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_S  0
+
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x58)
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_M  (AXI_DMA_RX_CRC_EN_WR_DATA_CH0_V << AXI_DMA_RX_CRC_EN_WR_DATA_CH0_S)
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_RX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x5c)
+/** AXI_DMA_RX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_M  (AXI_DMA_RX_CRC_EN_ADDR_CH0_V << AXI_DMA_RX_CRC_EN_ADDR_CH0_S)
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x60)
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0    0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_M  (AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V << AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V  0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x64)
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_M  (AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_V << AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_S)
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_INT_RAW_CH1_REG register
+ *  Raw status interrupt of channel 1
+ */
+#define AXI_DMA_IN_INT_RAW_CH1_REG (DR_REG_AXI_DMA_BASE + 0x68)
+/** AXI_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_RAW_M  (AXI_DMA_IN_DONE_CH1_INT_RAW_V << AXI_DMA_IN_DONE_CH1_INT_RAW_S)
+#define AXI_DMA_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_RAW_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+ *  interrupt is reserved.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+ *  including owner error and the second and third word error of inlink descriptor for
+ *  Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_S  10
+
+/** AXI_DMA_IN_INT_ST_CH1_REG register
+ *  Masked interrupt of channel 1
+ */
+#define AXI_DMA_IN_INT_ST_CH1_REG (DR_REG_AXI_DMA_BASE + 0x6c)
+/** AXI_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_ST    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_ST_M  (AXI_DMA_IN_DONE_CH1_INT_ST_V << AXI_DMA_IN_DONE_CH1_INT_ST_S)
+#define AXI_DMA_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_ST_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_ST_V << AXI_DMA_IN_SUC_EOF_CH1_INT_ST_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_ST_V << AXI_DMA_IN_ERR_EOF_CH1_INT_ST_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S  4
+/** AXI_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST    (BIT(5))
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST_M  (AXI_DMA_INFIFO_OVF_CH1_INT_ST_V << AXI_DMA_INFIFO_OVF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST_S  5
+/** AXI_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST    (BIT(6))
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST_M  (AXI_DMA_INFIFO_UDF_CH1_INT_ST_V << AXI_DMA_INFIFO_UDF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST_S  6
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST    (BIT(7))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_S  7
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST    (BIT(8))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_S  10
+
+/** AXI_DMA_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of channel 1
+ */
+#define AXI_DMA_IN_INT_ENA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x70)
+/** AXI_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_ENA_M  (AXI_DMA_IN_DONE_CH1_INT_ENA_V << AXI_DMA_IN_DONE_CH1_INT_ENA_S)
+#define AXI_DMA_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_ENA_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_S  10
+
+/** AXI_DMA_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of channel 1
+ */
+#define AXI_DMA_IN_INT_CLR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x74)
+/** AXI_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_CLR_M  (AXI_DMA_IN_DONE_CH1_INT_CLR_V << AXI_DMA_IN_DONE_CH1_INT_CLR_S)
+#define AXI_DMA_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_CLR_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_S  10
+
+/** AXI_DMA_IN_CONF0_CH1_REG register
+ *  Configure 0 register of Rx channel 1
+ */
+#define AXI_DMA_IN_CONF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0x78)
+/** AXI_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define AXI_DMA_IN_RST_CH1    (BIT(0))
+#define AXI_DMA_IN_RST_CH1_M  (AXI_DMA_IN_RST_CH1_V << AXI_DMA_IN_RST_CH1_S)
+#define AXI_DMA_IN_RST_CH1_V  0x00000001U
+#define AXI_DMA_IN_RST_CH1_S  0
+/** AXI_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_LOOP_TEST_CH1    (BIT(1))
+#define AXI_DMA_IN_LOOP_TEST_CH1_M  (AXI_DMA_IN_LOOP_TEST_CH1_V << AXI_DMA_IN_LOOP_TEST_CH1_S)
+#define AXI_DMA_IN_LOOP_TEST_CH1_V  0x00000001U
+#define AXI_DMA_IN_LOOP_TEST_CH1_S  1
+/** AXI_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+ *  AXI_DMA.
+ */
+#define AXI_DMA_MEM_TRANS_EN_CH1    (BIT(2))
+#define AXI_DMA_MEM_TRANS_EN_CH1_M  (AXI_DMA_MEM_TRANS_EN_CH1_V << AXI_DMA_MEM_TRANS_EN_CH1_S)
+#define AXI_DMA_MEM_TRANS_EN_CH1_V  0x00000001U
+#define AXI_DMA_MEM_TRANS_EN_CH1_S  2
+/** AXI_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_IN_ETM_EN_CH1    (BIT(3))
+#define AXI_DMA_IN_ETM_EN_CH1_M  (AXI_DMA_IN_ETM_EN_CH1_V << AXI_DMA_IN_ETM_EN_CH1_S)
+#define AXI_DMA_IN_ETM_EN_CH1_V  0x00000001U
+#define AXI_DMA_IN_ETM_EN_CH1_S  3
+/** AXI_DMA_IN_BURST_SIZE_SEL_CH1 : R/W; bitpos: [6:4]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1    0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1_M  (AXI_DMA_IN_BURST_SIZE_SEL_CH1_V << AXI_DMA_IN_BURST_SIZE_SEL_CH1_S)
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1_V  0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1_S  4
+/** AXI_DMA_IN_CMD_DISABLE_CH1 : R/W; bitpos: [7]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_IN_CMD_DISABLE_CH1    (BIT(7))
+#define AXI_DMA_IN_CMD_DISABLE_CH1_M  (AXI_DMA_IN_CMD_DISABLE_CH1_V << AXI_DMA_IN_CMD_DISABLE_CH1_S)
+#define AXI_DMA_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define AXI_DMA_IN_CMD_DISABLE_CH1_S  7
+/** AXI_DMA_IN_ECC_AEC_EN_CH1 : R/W; bitpos: [8]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_IN_ECC_AEC_EN_CH1    (BIT(8))
+#define AXI_DMA_IN_ECC_AEC_EN_CH1_M  (AXI_DMA_IN_ECC_AEC_EN_CH1_V << AXI_DMA_IN_ECC_AEC_EN_CH1_S)
+#define AXI_DMA_IN_ECC_AEC_EN_CH1_V  0x00000001U
+#define AXI_DMA_IN_ECC_AEC_EN_CH1_S  8
+/** AXI_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_INDSCR_BURST_EN_CH1    (BIT(9))
+#define AXI_DMA_INDSCR_BURST_EN_CH1_M  (AXI_DMA_INDSCR_BURST_EN_CH1_V << AXI_DMA_INDSCR_BURST_EN_CH1_S)
+#define AXI_DMA_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define AXI_DMA_INDSCR_BURST_EN_CH1_S  9
+
+/** AXI_DMA_IN_CONF1_CH1_REG register
+ *  Configure 1 register of Rx channel 1
+ */
+#define AXI_DMA_IN_CONF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x7c)
+/** AXI_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_IN_CHECK_OWNER_CH1    (BIT(12))
+#define AXI_DMA_IN_CHECK_OWNER_CH1_M  (AXI_DMA_IN_CHECK_OWNER_CH1_V << AXI_DMA_IN_CHECK_OWNER_CH1_S)
+#define AXI_DMA_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define AXI_DMA_IN_CHECK_OWNER_CH1_S  12
+
+/** AXI_DMA_INFIFO_STATUS_CH1_REG register
+ *  Receive FIFO status of Rx channel 1
+ */
+#define AXI_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AXI_DMA_BASE + 0x80)
+/** AXI_DMA_INFIFO_L3_FULL_CH1 : RO; bitpos: [0]; default: 1;
+ *  L3 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_FULL_CH1    (BIT(0))
+#define AXI_DMA_INFIFO_L3_FULL_CH1_M  (AXI_DMA_INFIFO_L3_FULL_CH1_V << AXI_DMA_INFIFO_L3_FULL_CH1_S)
+#define AXI_DMA_INFIFO_L3_FULL_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_FULL_CH1_S  0
+/** AXI_DMA_INFIFO_L3_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  L3 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1    (BIT(1))
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1_M  (AXI_DMA_INFIFO_L3_EMPTY_CH1_V << AXI_DMA_INFIFO_L3_EMPTY_CH1_S)
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1_S  1
+/** AXI_DMA_INFIFO_L3_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_CNT_CH1    0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH1_M  (AXI_DMA_INFIFO_L3_CNT_CH1_V << AXI_DMA_INFIFO_L3_CNT_CH1_S)
+#define AXI_DMA_INFIFO_L3_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH1_S  2
+/** AXI_DMA_INFIFO_L3_UDF_CH1 : RO; bitpos: [8]; default: 0;
+ *  L3 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1    (BIT(8))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_M  (AXI_DMA_INFIFO_L3_UDF_CH1_V << AXI_DMA_INFIFO_L3_UDF_CH1_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1 : RO; bitpos: [9]; default: 0;
+ *  L3 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_M  (AXI_DMA_INFIFO_L3_OVF_CH1_V << AXI_DMA_INFIFO_L3_OVF_CH1_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_S  9
+/** AXI_DMA_INFIFO_L1_FULL_CH1 : RO; bitpos: [10]; default: 0;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_FULL_CH1    (BIT(10))
+#define AXI_DMA_INFIFO_L1_FULL_CH1_M  (AXI_DMA_INFIFO_L1_FULL_CH1_V << AXI_DMA_INFIFO_L1_FULL_CH1_S)
+#define AXI_DMA_INFIFO_L1_FULL_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_FULL_CH1_S  10
+/** AXI_DMA_INFIFO_L1_EMPTY_CH1 : RO; bitpos: [11]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1    (BIT(11))
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1_M  (AXI_DMA_INFIFO_L1_EMPTY_CH1_V << AXI_DMA_INFIFO_L1_EMPTY_CH1_S)
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1_S  11
+/** AXI_DMA_INFIFO_L1_UDF_CH1 : RO; bitpos: [12]; default: 0;
+ *  L1 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1    (BIT(12))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_M  (AXI_DMA_INFIFO_L1_UDF_CH1_V << AXI_DMA_INFIFO_L1_UDF_CH1_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_S  12
+/** AXI_DMA_INFIFO_L1_OVF_CH1 : RO; bitpos: [13]; default: 0;
+ *  L1 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1    (BIT(13))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_M  (AXI_DMA_INFIFO_L1_OVF_CH1_V << AXI_DMA_INFIFO_L1_OVF_CH1_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_S  13
+/** AXI_DMA_INFIFO_L2_FULL_CH1 : RO; bitpos: [14]; default: 0;
+ *  L2 Rx RAM full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_FULL_CH1    (BIT(14))
+#define AXI_DMA_INFIFO_L2_FULL_CH1_M  (AXI_DMA_INFIFO_L2_FULL_CH1_V << AXI_DMA_INFIFO_L2_FULL_CH1_S)
+#define AXI_DMA_INFIFO_L2_FULL_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_FULL_CH1_S  14
+/** AXI_DMA_INFIFO_L2_EMPTY_CH1 : RO; bitpos: [15]; default: 1;
+ *  L2 Rx RAM empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1    (BIT(15))
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1_M  (AXI_DMA_INFIFO_L2_EMPTY_CH1_V << AXI_DMA_INFIFO_L2_EMPTY_CH1_S)
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1_S  15
+/** AXI_DMA_INFIFO_L2_UDF_CH1 : RO; bitpos: [16]; default: 0;
+ *  L2 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1    (BIT(16))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_M  (AXI_DMA_INFIFO_L2_UDF_CH1_V << AXI_DMA_INFIFO_L2_UDF_CH1_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_S  16
+/** AXI_DMA_INFIFO_L2_OVF_CH1 : RO; bitpos: [17]; default: 0;
+ *  L2 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1    (BIT(17))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_M  (AXI_DMA_INFIFO_L2_OVF_CH1_V << AXI_DMA_INFIFO_L2_OVF_CH1_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_S  17
+/** AXI_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_1B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_1B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1_S  23
+/** AXI_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_2B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_2B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1_S  24
+/** AXI_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_3B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_3B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1_S  25
+/** AXI_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_4B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_4B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1_S  26
+/** AXI_DMA_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1    (BIT(27))
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_5B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_5B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1_S  27
+/** AXI_DMA_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1    (BIT(28))
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_6B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_6B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1_S  28
+/** AXI_DMA_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1    (BIT(29))
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_7B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_7B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1_S  29
+/** AXI_DMA_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1    (BIT(30))
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_8B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_8B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1_S  30
+/** AXI_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_BUF_HUNGRY_CH1    (BIT(31))
+#define AXI_DMA_IN_BUF_HUNGRY_CH1_M  (AXI_DMA_IN_BUF_HUNGRY_CH1_V << AXI_DMA_IN_BUF_HUNGRY_CH1_S)
+#define AXI_DMA_IN_BUF_HUNGRY_CH1_V  0x00000001U
+#define AXI_DMA_IN_BUF_HUNGRY_CH1_S  31
+
+/** AXI_DMA_IN_POP_CH1_REG register
+ *  Pop control register of Rx channel 1
+ */
+#define AXI_DMA_IN_POP_CH1_REG (DR_REG_AXI_DMA_BASE + 0x84)
+/** AXI_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_RDATA_CH1    0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH1_M  (AXI_DMA_INFIFO_RDATA_CH1_V << AXI_DMA_INFIFO_RDATA_CH1_S)
+#define AXI_DMA_INFIFO_RDATA_CH1_V  0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH1_S  0
+/** AXI_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_POP_CH1    (BIT(12))
+#define AXI_DMA_INFIFO_POP_CH1_M  (AXI_DMA_INFIFO_POP_CH1_V << AXI_DMA_INFIFO_POP_CH1_S)
+#define AXI_DMA_INFIFO_POP_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_POP_CH1_S  12
+
+/** AXI_DMA_IN_LINK1_CH1_REG register
+ *  Link descriptor configure and control register of Rx channel 1
+ */
+#define AXI_DMA_IN_LINK1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x88)
+/** AXI_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address when there are some
+ *  errors in current receiving data.
+ */
+#define AXI_DMA_INLINK_AUTO_RET_CH1    (BIT(0))
+#define AXI_DMA_INLINK_AUTO_RET_CH1_M  (AXI_DMA_INLINK_AUTO_RET_CH1_V << AXI_DMA_INLINK_AUTO_RET_CH1_S)
+#define AXI_DMA_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_AUTO_RET_CH1_S  0
+/** AXI_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_STOP_CH1    (BIT(1))
+#define AXI_DMA_INLINK_STOP_CH1_M  (AXI_DMA_INLINK_STOP_CH1_V << AXI_DMA_INLINK_STOP_CH1_S)
+#define AXI_DMA_INLINK_STOP_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_STOP_CH1_S  1
+/** AXI_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_START_CH1    (BIT(2))
+#define AXI_DMA_INLINK_START_CH1_M  (AXI_DMA_INLINK_START_CH1_V << AXI_DMA_INLINK_START_CH1_S)
+#define AXI_DMA_INLINK_START_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_START_CH1_S  2
+/** AXI_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define AXI_DMA_INLINK_RESTART_CH1    (BIT(3))
+#define AXI_DMA_INLINK_RESTART_CH1_M  (AXI_DMA_INLINK_RESTART_CH1_V << AXI_DMA_INLINK_RESTART_CH1_S)
+#define AXI_DMA_INLINK_RESTART_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_RESTART_CH1_S  3
+/** AXI_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define AXI_DMA_INLINK_PARK_CH1    (BIT(4))
+#define AXI_DMA_INLINK_PARK_CH1_M  (AXI_DMA_INLINK_PARK_CH1_V << AXI_DMA_INLINK_PARK_CH1_S)
+#define AXI_DMA_INLINK_PARK_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_PARK_CH1_S  4
+
+/** AXI_DMA_IN_LINK2_CH1_REG register
+ *  Link descriptor configure and control register of Rx channel 1
+ */
+#define AXI_DMA_IN_LINK2_CH1_REG (DR_REG_AXI_DMA_BASE + 0x8c)
+/** AXI_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define AXI_DMA_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH1_M  (AXI_DMA_INLINK_ADDR_CH1_V << AXI_DMA_INLINK_ADDR_CH1_S)
+#define AXI_DMA_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_STATE_CH1_REG register
+ *  Receive status of Rx channel 1
+ */
+#define AXI_DMA_IN_STATE_CH1_REG (DR_REG_AXI_DMA_BASE + 0x90)
+/** AXI_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1_M  (AXI_DMA_INLINK_DSCR_ADDR_CH1_V << AXI_DMA_INLINK_DSCR_ADDR_CH1_S)
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1_S  0
+/** AXI_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_DSCR_STATE_CH1    0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH1_M  (AXI_DMA_IN_DSCR_STATE_CH1_V << AXI_DMA_IN_DSCR_STATE_CH1_S)
+#define AXI_DMA_IN_DSCR_STATE_CH1_V  0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH1_S  18
+/** AXI_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_STATE_CH1    0x00000007U
+#define AXI_DMA_IN_STATE_CH1_M  (AXI_DMA_IN_STATE_CH1_V << AXI_DMA_IN_STATE_CH1_S)
+#define AXI_DMA_IN_STATE_CH1_V  0x00000007U
+#define AXI_DMA_IN_STATE_CH1_S  20
+
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Inlink descriptor address when EOF occurs of Rx channel 1
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x94)
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_M  (AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Inlink descriptor address when errors occur of Rx channel 1
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x98)
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_M  (AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_DSCR_CH1_REG register
+ *  Current inlink descriptor address of Rx channel 1
+ */
+#define AXI_DMA_IN_DSCR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x9c)
+/** AXI_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define AXI_DMA_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH1_M  (AXI_DMA_INLINK_DSCR_CH1_V << AXI_DMA_INLINK_DSCR_CH1_S)
+#define AXI_DMA_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH1_S  0
+
+/** AXI_DMA_IN_DSCR_BF0_CH1_REG register
+ *  The last inlink descriptor address of Rx channel 1
+ */
+#define AXI_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0xa0)
+/** AXI_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define AXI_DMA_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH1_M  (AXI_DMA_INLINK_DSCR_BF0_CH1_V << AXI_DMA_INLINK_DSCR_BF0_CH1_S)
+#define AXI_DMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH1_S  0
+
+/** AXI_DMA_IN_DSCR_BF1_CH1_REG register
+ *  The second-to-last inlink descriptor address of Rx channel 1
+ */
+#define AXI_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0xa4)
+/** AXI_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define AXI_DMA_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH1_M  (AXI_DMA_INLINK_DSCR_BF1_CH1_V << AXI_DMA_INLINK_DSCR_BF1_CH1_S)
+#define AXI_DMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH1_S  0
+
+/** AXI_DMA_IN_PRI_CH1_REG register
+ *  Priority register of Rx channel 1
+ */
+#define AXI_DMA_IN_PRI_CH1_REG (DR_REG_AXI_DMA_BASE + 0xa8)
+/** AXI_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_RX_PRI_CH1    0x0000000FU
+#define AXI_DMA_RX_PRI_CH1_M  (AXI_DMA_RX_PRI_CH1_V << AXI_DMA_RX_PRI_CH1_S)
+#define AXI_DMA_RX_PRI_CH1_V  0x0000000FU
+#define AXI_DMA_RX_PRI_CH1_S  0
+/** AXI_DMA_RX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Rx channel 0
+ */
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1    0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1_M  (AXI_DMA_RX_CH_ARB_WEIGH_CH1_V << AXI_DMA_RX_CH_ARB_WEIGH_CH1_S)
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1_V  0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1_S  4
+/** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S)
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V  0x00000001U
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S  8
+
+/** AXI_DMA_IN_PERI_SEL_CH1_REG register
+ *  Peripheral selection of Rx channel 1
+ */
+#define AXI_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AXI_DMA_BASE + 0xac)
+/** AXI_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_IN_SEL_CH1    0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH1_M  (AXI_DMA_PERI_IN_SEL_CH1_V << AXI_DMA_PERI_IN_SEL_CH1_S)
+#define AXI_DMA_PERI_IN_SEL_CH1_V  0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH1_S  0
+
+/** AXI_DMA_IN_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb0)
+/** AXI_DMA_IN_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_M  (AXI_DMA_IN_CRC_INIT_DATA_CH1_V << AXI_DMA_IN_CRC_INIT_DATA_CH1_S)
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_S  0
+
+/** AXI_DMA_RX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig rx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb4)
+/** AXI_DMA_RX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH1    0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH1_M  (AXI_DMA_RX_CRC_WIDTH_CH1_V << AXI_DMA_RX_CRC_WIDTH_CH1_S)
+#define AXI_DMA_RX_CRC_WIDTH_CH1_V  0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH1_S  0
+/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_M  (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S)
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AXI_DMA_IN_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb8)
+/** AXI_DMA_IN_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH1    (BIT(0))
+#define AXI_DMA_IN_CRC_CLEAR_CH1_M  (AXI_DMA_IN_CRC_CLEAR_CH1_V << AXI_DMA_IN_CRC_CLEAR_CH1_S)
+#define AXI_DMA_IN_CRC_CLEAR_CH1_V  0x00000001U
+#define AXI_DMA_IN_CRC_CLEAR_CH1_S  0
+
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_REG (DR_REG_AXI_DMA_BASE + 0xbc)
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_M  (AXI_DMA_IN_CRC_FINAL_RESULT_CH1_V << AXI_DMA_IN_CRC_FINAL_RESULT_CH1_S)
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_S  0
+
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0xc0)
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_M  (AXI_DMA_RX_CRC_EN_WR_DATA_CH1_V << AXI_DMA_RX_CRC_EN_WR_DATA_CH1_S)
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_RX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xc4)
+/** AXI_DMA_RX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_M  (AXI_DMA_RX_CRC_EN_ADDR_CH1_V << AXI_DMA_RX_CRC_EN_ADDR_CH1_S)
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0xc8)
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1    0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_M  (AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V << AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V  0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xcc)
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_M  (AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_V << AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_S)
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_INT_RAW_CH2_REG register
+ *  Raw status interrupt of channel 2
+ */
+#define AXI_DMA_IN_INT_RAW_CH2_REG (DR_REG_AXI_DMA_BASE + 0xd0)
+/** AXI_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_RAW_M  (AXI_DMA_IN_DONE_CH2_INT_RAW_V << AXI_DMA_IN_DONE_CH2_INT_RAW_S)
+#define AXI_DMA_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_RAW_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+ *  interrupt is reserved.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_V << AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+ *  including owner error and the second and third word error of inlink descriptor for
+ *  Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_S  10
+
+/** AXI_DMA_IN_INT_ST_CH2_REG register
+ *  Masked interrupt of channel 2
+ */
+#define AXI_DMA_IN_INT_ST_CH2_REG (DR_REG_AXI_DMA_BASE + 0xd4)
+/** AXI_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_ST    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_ST_M  (AXI_DMA_IN_DONE_CH2_INT_ST_V << AXI_DMA_IN_DONE_CH2_INT_ST_S)
+#define AXI_DMA_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_ST_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_ST_V << AXI_DMA_IN_SUC_EOF_CH2_INT_ST_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_ST_V << AXI_DMA_IN_ERR_EOF_CH2_INT_ST_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S  4
+/** AXI_DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST    (BIT(5))
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST_M  (AXI_DMA_INFIFO_OVF_CH2_INT_ST_V << AXI_DMA_INFIFO_OVF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST_S  5
+/** AXI_DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST    (BIT(6))
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST_M  (AXI_DMA_INFIFO_UDF_CH2_INT_ST_V << AXI_DMA_INFIFO_UDF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST_S  6
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST    (BIT(7))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_S  7
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST    (BIT(8))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_S  10
+
+/** AXI_DMA_IN_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of channel 2
+ */
+#define AXI_DMA_IN_INT_ENA_CH2_REG (DR_REG_AXI_DMA_BASE + 0xd8)
+/** AXI_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_ENA_M  (AXI_DMA_IN_DONE_CH2_INT_ENA_V << AXI_DMA_IN_DONE_CH2_INT_ENA_S)
+#define AXI_DMA_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_ENA_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_V << AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_V << AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_S  10
+
+/** AXI_DMA_IN_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of channel 2
+ */
+#define AXI_DMA_IN_INT_CLR_CH2_REG (DR_REG_AXI_DMA_BASE + 0xdc)
+/** AXI_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_CLR_M  (AXI_DMA_IN_DONE_CH2_INT_CLR_V << AXI_DMA_IN_DONE_CH2_INT_CLR_S)
+#define AXI_DMA_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_CLR_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_V << AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_V << AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_S  10
+
+/** AXI_DMA_IN_CONF0_CH2_REG register
+ *  Configure 0 register of Rx channel 2
+ */
+#define AXI_DMA_IN_CONF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0xe0)
+/** AXI_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define AXI_DMA_IN_RST_CH2    (BIT(0))
+#define AXI_DMA_IN_RST_CH2_M  (AXI_DMA_IN_RST_CH2_V << AXI_DMA_IN_RST_CH2_S)
+#define AXI_DMA_IN_RST_CH2_V  0x00000001U
+#define AXI_DMA_IN_RST_CH2_S  0
+/** AXI_DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_LOOP_TEST_CH2    (BIT(1))
+#define AXI_DMA_IN_LOOP_TEST_CH2_M  (AXI_DMA_IN_LOOP_TEST_CH2_V << AXI_DMA_IN_LOOP_TEST_CH2_S)
+#define AXI_DMA_IN_LOOP_TEST_CH2_V  0x00000001U
+#define AXI_DMA_IN_LOOP_TEST_CH2_S  1
+/** AXI_DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+ *  AXI_DMA.
+ */
+#define AXI_DMA_MEM_TRANS_EN_CH2    (BIT(2))
+#define AXI_DMA_MEM_TRANS_EN_CH2_M  (AXI_DMA_MEM_TRANS_EN_CH2_V << AXI_DMA_MEM_TRANS_EN_CH2_S)
+#define AXI_DMA_MEM_TRANS_EN_CH2_V  0x00000001U
+#define AXI_DMA_MEM_TRANS_EN_CH2_S  2
+/** AXI_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_IN_ETM_EN_CH2    (BIT(3))
+#define AXI_DMA_IN_ETM_EN_CH2_M  (AXI_DMA_IN_ETM_EN_CH2_V << AXI_DMA_IN_ETM_EN_CH2_S)
+#define AXI_DMA_IN_ETM_EN_CH2_V  0x00000001U
+#define AXI_DMA_IN_ETM_EN_CH2_S  3
+/** AXI_DMA_IN_BURST_SIZE_SEL_CH2 : R/W; bitpos: [6:4]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2    0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2_M  (AXI_DMA_IN_BURST_SIZE_SEL_CH2_V << AXI_DMA_IN_BURST_SIZE_SEL_CH2_S)
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2_V  0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2_S  4
+/** AXI_DMA_IN_CMD_DISABLE_CH2 : R/W; bitpos: [7]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_IN_CMD_DISABLE_CH2    (BIT(7))
+#define AXI_DMA_IN_CMD_DISABLE_CH2_M  (AXI_DMA_IN_CMD_DISABLE_CH2_V << AXI_DMA_IN_CMD_DISABLE_CH2_S)
+#define AXI_DMA_IN_CMD_DISABLE_CH2_V  0x00000001U
+#define AXI_DMA_IN_CMD_DISABLE_CH2_S  7
+/** AXI_DMA_IN_ECC_AEC_EN_CH2 : R/W; bitpos: [8]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_IN_ECC_AEC_EN_CH2    (BIT(8))
+#define AXI_DMA_IN_ECC_AEC_EN_CH2_M  (AXI_DMA_IN_ECC_AEC_EN_CH2_V << AXI_DMA_IN_ECC_AEC_EN_CH2_S)
+#define AXI_DMA_IN_ECC_AEC_EN_CH2_V  0x00000001U
+#define AXI_DMA_IN_ECC_AEC_EN_CH2_S  8
+/** AXI_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_INDSCR_BURST_EN_CH2    (BIT(9))
+#define AXI_DMA_INDSCR_BURST_EN_CH2_M  (AXI_DMA_INDSCR_BURST_EN_CH2_V << AXI_DMA_INDSCR_BURST_EN_CH2_S)
+#define AXI_DMA_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define AXI_DMA_INDSCR_BURST_EN_CH2_S  9
+
+/** AXI_DMA_IN_CONF1_CH2_REG register
+ *  Configure 1 register of Rx channel 2
+ */
+#define AXI_DMA_IN_CONF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0xe4)
+/** AXI_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_IN_CHECK_OWNER_CH2    (BIT(12))
+#define AXI_DMA_IN_CHECK_OWNER_CH2_M  (AXI_DMA_IN_CHECK_OWNER_CH2_V << AXI_DMA_IN_CHECK_OWNER_CH2_S)
+#define AXI_DMA_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define AXI_DMA_IN_CHECK_OWNER_CH2_S  12
+
+/** AXI_DMA_INFIFO_STATUS_CH2_REG register
+ *  Receive FIFO status of Rx channel 2
+ */
+#define AXI_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AXI_DMA_BASE + 0xe8)
+/** AXI_DMA_INFIFO_L3_FULL_CH2 : RO; bitpos: [0]; default: 1;
+ *  L3 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_FULL_CH2    (BIT(0))
+#define AXI_DMA_INFIFO_L3_FULL_CH2_M  (AXI_DMA_INFIFO_L3_FULL_CH2_V << AXI_DMA_INFIFO_L3_FULL_CH2_S)
+#define AXI_DMA_INFIFO_L3_FULL_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_FULL_CH2_S  0
+/** AXI_DMA_INFIFO_L3_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  L3 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2    (BIT(1))
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2_M  (AXI_DMA_INFIFO_L3_EMPTY_CH2_V << AXI_DMA_INFIFO_L3_EMPTY_CH2_S)
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2_S  1
+/** AXI_DMA_INFIFO_L3_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_CNT_CH2    0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH2_M  (AXI_DMA_INFIFO_L3_CNT_CH2_V << AXI_DMA_INFIFO_L3_CNT_CH2_S)
+#define AXI_DMA_INFIFO_L3_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH2_S  2
+/** AXI_DMA_INFIFO_L3_UDF_CH2 : RO; bitpos: [8]; default: 0;
+ *  L3 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2    (BIT(8))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_M  (AXI_DMA_INFIFO_L3_UDF_CH2_V << AXI_DMA_INFIFO_L3_UDF_CH2_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2 : RO; bitpos: [9]; default: 0;
+ *  L3 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_M  (AXI_DMA_INFIFO_L3_OVF_CH2_V << AXI_DMA_INFIFO_L3_OVF_CH2_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_S  9
+/** AXI_DMA_INFIFO_L1_FULL_CH2 : RO; bitpos: [10]; default: 0;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_FULL_CH2    (BIT(10))
+#define AXI_DMA_INFIFO_L1_FULL_CH2_M  (AXI_DMA_INFIFO_L1_FULL_CH2_V << AXI_DMA_INFIFO_L1_FULL_CH2_S)
+#define AXI_DMA_INFIFO_L1_FULL_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_FULL_CH2_S  10
+/** AXI_DMA_INFIFO_L1_EMPTY_CH2 : RO; bitpos: [11]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2    (BIT(11))
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2_M  (AXI_DMA_INFIFO_L1_EMPTY_CH2_V << AXI_DMA_INFIFO_L1_EMPTY_CH2_S)
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2_S  11
+/** AXI_DMA_INFIFO_L1_UDF_CH2 : RO; bitpos: [12]; default: 0;
+ *  L1 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2    (BIT(12))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_M  (AXI_DMA_INFIFO_L1_UDF_CH2_V << AXI_DMA_INFIFO_L1_UDF_CH2_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_S  12
+/** AXI_DMA_INFIFO_L1_OVF_CH2 : RO; bitpos: [13]; default: 0;
+ *  L1 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2    (BIT(13))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_M  (AXI_DMA_INFIFO_L1_OVF_CH2_V << AXI_DMA_INFIFO_L1_OVF_CH2_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_S  13
+/** AXI_DMA_INFIFO_L2_FULL_CH2 : RO; bitpos: [14]; default: 0;
+ *  L2 Rx RAM full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_FULL_CH2    (BIT(14))
+#define AXI_DMA_INFIFO_L2_FULL_CH2_M  (AXI_DMA_INFIFO_L2_FULL_CH2_V << AXI_DMA_INFIFO_L2_FULL_CH2_S)
+#define AXI_DMA_INFIFO_L2_FULL_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_FULL_CH2_S  14
+/** AXI_DMA_INFIFO_L2_EMPTY_CH2 : RO; bitpos: [15]; default: 1;
+ *  L2 Rx RAM empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2    (BIT(15))
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2_M  (AXI_DMA_INFIFO_L2_EMPTY_CH2_V << AXI_DMA_INFIFO_L2_EMPTY_CH2_S)
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2_S  15
+/** AXI_DMA_INFIFO_L2_UDF_CH2 : RO; bitpos: [16]; default: 0;
+ *  L2 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2    (BIT(16))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_M  (AXI_DMA_INFIFO_L2_UDF_CH2_V << AXI_DMA_INFIFO_L2_UDF_CH2_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_S  16
+/** AXI_DMA_INFIFO_L2_OVF_CH2 : RO; bitpos: [17]; default: 0;
+ *  L2 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2    (BIT(17))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_M  (AXI_DMA_INFIFO_L2_OVF_CH2_V << AXI_DMA_INFIFO_L2_OVF_CH2_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_S  17
+/** AXI_DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_1B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_1B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2_S  23
+/** AXI_DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_2B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_2B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2_S  24
+/** AXI_DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_3B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_3B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2_S  25
+/** AXI_DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_4B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_4B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2_S  26
+/** AXI_DMA_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2    (BIT(27))
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_5B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_5B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2_S  27
+/** AXI_DMA_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2    (BIT(28))
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_6B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_6B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2_S  28
+/** AXI_DMA_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2    (BIT(29))
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_7B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_7B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2_S  29
+/** AXI_DMA_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2    (BIT(30))
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_8B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_8B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2_S  30
+/** AXI_DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_BUF_HUNGRY_CH2    (BIT(31))
+#define AXI_DMA_IN_BUF_HUNGRY_CH2_M  (AXI_DMA_IN_BUF_HUNGRY_CH2_V << AXI_DMA_IN_BUF_HUNGRY_CH2_S)
+#define AXI_DMA_IN_BUF_HUNGRY_CH2_V  0x00000001U
+#define AXI_DMA_IN_BUF_HUNGRY_CH2_S  31
+
+/** AXI_DMA_IN_POP_CH2_REG register
+ *  Pop control register of Rx channel 2
+ */
+#define AXI_DMA_IN_POP_CH2_REG (DR_REG_AXI_DMA_BASE + 0xec)
+/** AXI_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_RDATA_CH2    0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH2_M  (AXI_DMA_INFIFO_RDATA_CH2_V << AXI_DMA_INFIFO_RDATA_CH2_S)
+#define AXI_DMA_INFIFO_RDATA_CH2_V  0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH2_S  0
+/** AXI_DMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_POP_CH2    (BIT(12))
+#define AXI_DMA_INFIFO_POP_CH2_M  (AXI_DMA_INFIFO_POP_CH2_V << AXI_DMA_INFIFO_POP_CH2_S)
+#define AXI_DMA_INFIFO_POP_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_POP_CH2_S  12
+
+/** AXI_DMA_IN_LINK1_CH2_REG register
+ *  Link descriptor configure and control register of Rx channel 2
+ */
+#define AXI_DMA_IN_LINK1_CH2_REG (DR_REG_AXI_DMA_BASE + 0xf0)
+/** AXI_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address when there are some
+ *  errors in current receiving data.
+ */
+#define AXI_DMA_INLINK_AUTO_RET_CH2    (BIT(0))
+#define AXI_DMA_INLINK_AUTO_RET_CH2_M  (AXI_DMA_INLINK_AUTO_RET_CH2_V << AXI_DMA_INLINK_AUTO_RET_CH2_S)
+#define AXI_DMA_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_AUTO_RET_CH2_S  0
+/** AXI_DMA_INLINK_STOP_CH2 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_STOP_CH2    (BIT(1))
+#define AXI_DMA_INLINK_STOP_CH2_M  (AXI_DMA_INLINK_STOP_CH2_V << AXI_DMA_INLINK_STOP_CH2_S)
+#define AXI_DMA_INLINK_STOP_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_STOP_CH2_S  1
+/** AXI_DMA_INLINK_START_CH2 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_START_CH2    (BIT(2))
+#define AXI_DMA_INLINK_START_CH2_M  (AXI_DMA_INLINK_START_CH2_V << AXI_DMA_INLINK_START_CH2_S)
+#define AXI_DMA_INLINK_START_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_START_CH2_S  2
+/** AXI_DMA_INLINK_RESTART_CH2 : WT; bitpos: [3]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define AXI_DMA_INLINK_RESTART_CH2    (BIT(3))
+#define AXI_DMA_INLINK_RESTART_CH2_M  (AXI_DMA_INLINK_RESTART_CH2_V << AXI_DMA_INLINK_RESTART_CH2_S)
+#define AXI_DMA_INLINK_RESTART_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_RESTART_CH2_S  3
+/** AXI_DMA_INLINK_PARK_CH2 : RO; bitpos: [4]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define AXI_DMA_INLINK_PARK_CH2    (BIT(4))
+#define AXI_DMA_INLINK_PARK_CH2_M  (AXI_DMA_INLINK_PARK_CH2_V << AXI_DMA_INLINK_PARK_CH2_S)
+#define AXI_DMA_INLINK_PARK_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_PARK_CH2_S  4
+
+/** AXI_DMA_IN_LINK2_CH2_REG register
+ *  Link descriptor configure and control register of Rx channel 2
+ */
+#define AXI_DMA_IN_LINK2_CH2_REG (DR_REG_AXI_DMA_BASE + 0xf4)
+/** AXI_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define AXI_DMA_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH2_M  (AXI_DMA_INLINK_ADDR_CH2_V << AXI_DMA_INLINK_ADDR_CH2_S)
+#define AXI_DMA_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH2_S  0
+
+/** AXI_DMA_IN_STATE_CH2_REG register
+ *  Receive status of Rx channel 2
+ */
+#define AXI_DMA_IN_STATE_CH2_REG (DR_REG_AXI_DMA_BASE + 0xf8)
+/** AXI_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2_M  (AXI_DMA_INLINK_DSCR_ADDR_CH2_V << AXI_DMA_INLINK_DSCR_ADDR_CH2_S)
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2_S  0
+/** AXI_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_DSCR_STATE_CH2    0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH2_M  (AXI_DMA_IN_DSCR_STATE_CH2_V << AXI_DMA_IN_DSCR_STATE_CH2_S)
+#define AXI_DMA_IN_DSCR_STATE_CH2_V  0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH2_S  18
+/** AXI_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_STATE_CH2    0x00000007U
+#define AXI_DMA_IN_STATE_CH2_M  (AXI_DMA_IN_STATE_CH2_V << AXI_DMA_IN_STATE_CH2_S)
+#define AXI_DMA_IN_STATE_CH2_V  0x00000007U
+#define AXI_DMA_IN_STATE_CH2_S  20
+
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  Inlink descriptor address when EOF occurs of Rx channel 2
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0xfc)
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_M  (AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  Inlink descriptor address when errors occur of Rx channel 2
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x100)
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_M  (AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_IN_DSCR_CH2_REG register
+ *  Current inlink descriptor address of Rx channel 2
+ */
+#define AXI_DMA_IN_DSCR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x104)
+/** AXI_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define AXI_DMA_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH2_M  (AXI_DMA_INLINK_DSCR_CH2_V << AXI_DMA_INLINK_DSCR_CH2_S)
+#define AXI_DMA_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH2_S  0
+
+/** AXI_DMA_IN_DSCR_BF0_CH2_REG register
+ *  The last inlink descriptor address of Rx channel 2
+ */
+#define AXI_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0x108)
+/** AXI_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define AXI_DMA_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH2_M  (AXI_DMA_INLINK_DSCR_BF0_CH2_V << AXI_DMA_INLINK_DSCR_BF0_CH2_S)
+#define AXI_DMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH2_S  0
+
+/** AXI_DMA_IN_DSCR_BF1_CH2_REG register
+ *  The second-to-last inlink descriptor address of Rx channel 2
+ */
+#define AXI_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x10c)
+/** AXI_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define AXI_DMA_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH2_M  (AXI_DMA_INLINK_DSCR_BF1_CH2_V << AXI_DMA_INLINK_DSCR_BF1_CH2_S)
+#define AXI_DMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH2_S  0
+
+/** AXI_DMA_IN_PRI_CH2_REG register
+ *  Priority register of Rx channel 2
+ */
+#define AXI_DMA_IN_PRI_CH2_REG (DR_REG_AXI_DMA_BASE + 0x110)
+/** AXI_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_RX_PRI_CH2    0x0000000FU
+#define AXI_DMA_RX_PRI_CH2_M  (AXI_DMA_RX_PRI_CH2_V << AXI_DMA_RX_PRI_CH2_S)
+#define AXI_DMA_RX_PRI_CH2_V  0x0000000FU
+#define AXI_DMA_RX_PRI_CH2_S  0
+/** AXI_DMA_RX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Rx channel 0
+ */
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2_M  (AXI_DMA_RX_CH_ARB_WEIGH_CH2_V << AXI_DMA_RX_CH_ARB_WEIGH_CH2_S)
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2_S  4
+/** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S  8
+
+/** AXI_DMA_IN_PERI_SEL_CH2_REG register
+ *  Peripheral selection of Rx channel 2
+ */
+#define AXI_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x114)
+/** AXI_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_IN_SEL_CH2    0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH2_M  (AXI_DMA_PERI_IN_SEL_CH2_V << AXI_DMA_PERI_IN_SEL_CH2_S)
+#define AXI_DMA_PERI_IN_SEL_CH2_V  0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH2_S  0
+
+/** AXI_DMA_IN_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x118)
+/** AXI_DMA_IN_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_M  (AXI_DMA_IN_CRC_INIT_DATA_CH2_V << AXI_DMA_IN_CRC_INIT_DATA_CH2_S)
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_S  0
+
+/** AXI_DMA_RX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig rx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH2_REG (DR_REG_AXI_DMA_BASE + 0x11c)
+/** AXI_DMA_RX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH2    0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH2_M  (AXI_DMA_RX_CRC_WIDTH_CH2_V << AXI_DMA_RX_CRC_WIDTH_CH2_S)
+#define AXI_DMA_RX_CRC_WIDTH_CH2_V  0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH2_S  0
+/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_M  (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S)
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AXI_DMA_IN_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x120)
+/** AXI_DMA_IN_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH2    (BIT(0))
+#define AXI_DMA_IN_CRC_CLEAR_CH2_M  (AXI_DMA_IN_CRC_CLEAR_CH2_V << AXI_DMA_IN_CRC_CLEAR_CH2_S)
+#define AXI_DMA_IN_CRC_CLEAR_CH2_V  0x00000001U
+#define AXI_DMA_IN_CRC_CLEAR_CH2_S  0
+
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_REG (DR_REG_AXI_DMA_BASE + 0x124)
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_M  (AXI_DMA_IN_CRC_FINAL_RESULT_CH2_V << AXI_DMA_IN_CRC_FINAL_RESULT_CH2_S)
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_S  0
+
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x128)
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_M  (AXI_DMA_RX_CRC_EN_WR_DATA_CH2_V << AXI_DMA_RX_CRC_EN_WR_DATA_CH2_S)
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_RX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x12c)
+/** AXI_DMA_RX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_M  (AXI_DMA_RX_CRC_EN_ADDR_CH2_V << AXI_DMA_RX_CRC_EN_ADDR_CH2_S)
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x130)
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2    0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_M  (AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V << AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V  0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x134)
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_M  (AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_V << AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_S)
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_INT_RAW_CH0_REG register
+ *  Raw status interrupt of channel0
+ */
+#define AXI_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AXI_DMA_BASE + 0x138)
+/** AXI_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel0.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW_M  (AXI_DMA_OUT_DONE_CH0_INT_RAW_V << AXI_DMA_OUT_DONE_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel0.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW_M  (AXI_DMA_OUT_EOF_CH0_INT_RAW_V << AXI_DMA_OUT_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+ *  including owner error and the second and third word error of outlink descriptor for
+ *  Tx channel0.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_S  10
+
+/** AXI_DMA_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt of channel0
+ */
+#define AXI_DMA_OUT_INT_ST_CH0_REG (DR_REG_AXI_DMA_BASE + 0x13c)
+/** AXI_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_ST_M  (AXI_DMA_OUT_DONE_CH0_INT_ST_V << AXI_DMA_OUT_DONE_CH0_INT_ST_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_ST_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_ST_M  (AXI_DMA_OUT_EOF_CH0_INT_ST_V << AXI_DMA_OUT_EOF_CH0_INT_ST_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_ST_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** AXI_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST    (BIT(4))
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_S  4
+/** AXI_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST    (BIT(5))
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_S  5
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST    (BIT(6))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_S  6
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST    (BIT(7))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_S  10
+
+/** AXI_DMA_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of channel0
+ */
+#define AXI_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x140)
+/** AXI_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA_M  (AXI_DMA_OUT_DONE_CH0_INT_ENA_V << AXI_DMA_OUT_DONE_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA_M  (AXI_DMA_OUT_EOF_CH0_INT_ENA_V << AXI_DMA_OUT_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_S  10
+
+/** AXI_DMA_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of channel0
+ */
+#define AXI_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x144)
+/** AXI_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR_M  (AXI_DMA_OUT_DONE_CH0_INT_CLR_V << AXI_DMA_OUT_DONE_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR_M  (AXI_DMA_OUT_EOF_CH0_INT_CLR_V << AXI_DMA_OUT_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_S  10
+
+/** AXI_DMA_OUT_CONF0_CH0_REG register
+ *  Configure 0 register of Tx channel0
+ */
+#define AXI_DMA_OUT_CONF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x148)
+/** AXI_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer.
+ */
+#define AXI_DMA_OUT_RST_CH0    (BIT(0))
+#define AXI_DMA_OUT_RST_CH0_M  (AXI_DMA_OUT_RST_CH0_V << AXI_DMA_OUT_RST_CH0_S)
+#define AXI_DMA_OUT_RST_CH0_V  0x00000001U
+#define AXI_DMA_OUT_RST_CH0_S  0
+/** AXI_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_LOOP_TEST_CH0    (BIT(1))
+#define AXI_DMA_OUT_LOOP_TEST_CH0_M  (AXI_DMA_OUT_LOOP_TEST_CH0_V << AXI_DMA_OUT_LOOP_TEST_CH0_S)
+#define AXI_DMA_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define AXI_DMA_OUT_LOOP_TEST_CH0_S  1
+/** AXI_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0    (BIT(2))
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0_M  (AXI_DMA_OUT_AUTO_WRBACK_CH0_V << AXI_DMA_OUT_AUTO_WRBACK_CH0_S)
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0_S  2
+/** AXI_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is
+ *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+ */
+#define AXI_DMA_OUT_EOF_MODE_CH0    (BIT(3))
+#define AXI_DMA_OUT_EOF_MODE_CH0_M  (AXI_DMA_OUT_EOF_MODE_CH0_V << AXI_DMA_OUT_EOF_MODE_CH0_S)
+#define AXI_DMA_OUT_EOF_MODE_CH0_V  0x00000001U
+#define AXI_DMA_OUT_EOF_MODE_CH0_S  3
+/** AXI_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_OUT_ETM_EN_CH0    (BIT(4))
+#define AXI_DMA_OUT_ETM_EN_CH0_M  (AXI_DMA_OUT_ETM_EN_CH0_V << AXI_DMA_OUT_ETM_EN_CH0_S)
+#define AXI_DMA_OUT_ETM_EN_CH0_V  0x00000001U
+#define AXI_DMA_OUT_ETM_EN_CH0_S  4
+/** AXI_DMA_OUT_BURST_SIZE_SEL_CH0 : R/W; bitpos: [7:5]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0    0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0_M  (AXI_DMA_OUT_BURST_SIZE_SEL_CH0_V << AXI_DMA_OUT_BURST_SIZE_SEL_CH0_S)
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0_V  0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0_S  5
+/** AXI_DMA_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [8]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_OUT_CMD_DISABLE_CH0    (BIT(8))
+#define AXI_DMA_OUT_CMD_DISABLE_CH0_M  (AXI_DMA_OUT_CMD_DISABLE_CH0_V << AXI_DMA_OUT_CMD_DISABLE_CH0_S)
+#define AXI_DMA_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define AXI_DMA_OUT_CMD_DISABLE_CH0_S  8
+/** AXI_DMA_OUT_ECC_AEC_EN_CH0 : R/W; bitpos: [9]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0    (BIT(9))
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0_M  (AXI_DMA_OUT_ECC_AEC_EN_CH0_V << AXI_DMA_OUT_ECC_AEC_EN_CH0_S)
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0_V  0x00000001U
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0_S  9
+/** AXI_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0    (BIT(10))
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0_M  (AXI_DMA_OUTDSCR_BURST_EN_CH0_V << AXI_DMA_OUTDSCR_BURST_EN_CH0_S)
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0_S  10
+
+/** AXI_DMA_OUT_CONF1_CH0_REG register
+ *  Configure 1 register of Tx channel0
+ */
+#define AXI_DMA_OUT_CONF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x14c)
+/** AXI_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_OUT_CHECK_OWNER_CH0    (BIT(12))
+#define AXI_DMA_OUT_CHECK_OWNER_CH0_M  (AXI_DMA_OUT_CHECK_OWNER_CH0_V << AXI_DMA_OUT_CHECK_OWNER_CH0_S)
+#define AXI_DMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define AXI_DMA_OUT_CHECK_OWNER_CH0_S  12
+
+/** AXI_DMA_OUTFIFO_STATUS_CH0_REG register
+ *  Transmit FIFO status of Tx channel0
+ */
+#define AXI_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AXI_DMA_BASE + 0x150)
+/** AXI_DMA_OUTFIFO_L3_FULL_CH0 : RO; bitpos: [0]; default: 0;
+ *  L3 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0    (BIT(0))
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0_M  (AXI_DMA_OUTFIFO_L3_FULL_CH0_V << AXI_DMA_OUTFIFO_L3_FULL_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0_S  0
+/** AXI_DMA_OUTFIFO_L3_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  L3 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0    (BIT(1))
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0_M  (AXI_DMA_OUTFIFO_L3_EMPTY_CH0_V << AXI_DMA_OUTFIFO_L3_EMPTY_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0_S  1
+/** AXI_DMA_OUTFIFO_L3_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0    0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0_M  (AXI_DMA_OUTFIFO_L3_CNT_CH0_V << AXI_DMA_OUTFIFO_L3_CNT_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0_S  2
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0 : RO; bitpos: [8]; default: 0;
+ *  L3 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_S  8
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0 : RO; bitpos: [9]; default: 0;
+ *  L3 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_S  9
+/** AXI_DMA_OUTFIFO_L1_FULL_CH0 : RO; bitpos: [10]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0    (BIT(10))
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0_M  (AXI_DMA_OUTFIFO_L1_FULL_CH0_V << AXI_DMA_OUTFIFO_L1_FULL_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0_S  10
+/** AXI_DMA_OUTFIFO_L1_EMPTY_CH0 : RO; bitpos: [11]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0    (BIT(11))
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0_M  (AXI_DMA_OUTFIFO_L1_EMPTY_CH0_V << AXI_DMA_OUTFIFO_L1_EMPTY_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0_S  11
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0 : RO; bitpos: [12]; default: 0;
+ *  L1 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0    (BIT(12))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_S  12
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0 : RO; bitpos: [13]; default: 0;
+ *  L1 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0    (BIT(13))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_S  13
+/** AXI_DMA_OUTFIFO_L2_FULL_CH0 : RO; bitpos: [14]; default: 0;
+ *  L2 Tx RAM full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0    (BIT(14))
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0_M  (AXI_DMA_OUTFIFO_L2_FULL_CH0_V << AXI_DMA_OUTFIFO_L2_FULL_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0_S  14
+/** AXI_DMA_OUTFIFO_L2_EMPTY_CH0 : RO; bitpos: [15]; default: 1;
+ *  L2 Tx RAM empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0    (BIT(15))
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0_M  (AXI_DMA_OUTFIFO_L2_EMPTY_CH0_V << AXI_DMA_OUTFIFO_L2_EMPTY_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0_S  15
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0 : RO; bitpos: [16]; default: 0;
+ *  L2 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0    (BIT(16))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_S  16
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0 : RO; bitpos: [17]; default: 0;
+ *  L2 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0    (BIT(17))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_S  17
+/** AXI_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_S  23
+/** AXI_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_S  24
+/** AXI_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_S  25
+/** AXI_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_S  26
+/** AXI_DMA_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [27]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0    (BIT(27))
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_S  27
+/** AXI_DMA_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0    (BIT(28))
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_S  28
+/** AXI_DMA_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0    (BIT(29))
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_S  29
+/** AXI_DMA_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0    (BIT(30))
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_S  30
+
+/** AXI_DMA_OUT_PUSH_CH0_REG register
+ *  Push control register of Tx channel0
+ */
+#define AXI_DMA_OUT_PUSH_CH0_REG (DR_REG_AXI_DMA_BASE + 0x154)
+/** AXI_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_WDATA_CH0    0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH0_M  (AXI_DMA_OUTFIFO_WDATA_CH0_V << AXI_DMA_OUTFIFO_WDATA_CH0_S)
+#define AXI_DMA_OUTFIFO_WDATA_CH0_V  0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH0_S  0
+/** AXI_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0;
+ *  Set this bit to push data into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_PUSH_CH0    (BIT(9))
+#define AXI_DMA_OUTFIFO_PUSH_CH0_M  (AXI_DMA_OUTFIFO_PUSH_CH0_V << AXI_DMA_OUTFIFO_PUSH_CH0_S)
+#define AXI_DMA_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_PUSH_CH0_S  9
+
+/** AXI_DMA_OUT_LINK1_CH0_REG register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+#define AXI_DMA_OUT_LINK1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x158)
+/** AXI_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_STOP_CH0    (BIT(0))
+#define AXI_DMA_OUTLINK_STOP_CH0_M  (AXI_DMA_OUTLINK_STOP_CH0_V << AXI_DMA_OUTLINK_STOP_CH0_S)
+#define AXI_DMA_OUTLINK_STOP_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_STOP_CH0_S  0
+/** AXI_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_START_CH0    (BIT(1))
+#define AXI_DMA_OUTLINK_START_CH0_M  (AXI_DMA_OUTLINK_START_CH0_V << AXI_DMA_OUTLINK_START_CH0_S)
+#define AXI_DMA_OUTLINK_START_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_START_CH0_S  1
+/** AXI_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define AXI_DMA_OUTLINK_RESTART_CH0    (BIT(2))
+#define AXI_DMA_OUTLINK_RESTART_CH0_M  (AXI_DMA_OUTLINK_RESTART_CH0_V << AXI_DMA_OUTLINK_RESTART_CH0_S)
+#define AXI_DMA_OUTLINK_RESTART_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_RESTART_CH0_S  2
+/** AXI_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define AXI_DMA_OUTLINK_PARK_CH0    (BIT(3))
+#define AXI_DMA_OUTLINK_PARK_CH0_M  (AXI_DMA_OUTLINK_PARK_CH0_V << AXI_DMA_OUTLINK_PARK_CH0_S)
+#define AXI_DMA_OUTLINK_PARK_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_PARK_CH0_S  3
+
+/** AXI_DMA_OUT_LINK2_CH0_REG register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+#define AXI_DMA_OUT_LINK2_CH0_REG (DR_REG_AXI_DMA_BASE + 0x15c)
+/** AXI_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 32 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH0_M  (AXI_DMA_OUTLINK_ADDR_CH0_V << AXI_DMA_OUTLINK_ADDR_CH0_S)
+#define AXI_DMA_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_STATE_CH0_REG register
+ *  Transmit status of Tx channel0
+ */
+#define AXI_DMA_OUT_STATE_CH0_REG (DR_REG_AXI_DMA_BASE + 0x160)
+/** AXI_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0_M  (AXI_DMA_OUTLINK_DSCR_ADDR_CH0_V << AXI_DMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0_S  0
+/** AXI_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_DSCR_STATE_CH0    0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH0_M  (AXI_DMA_OUT_DSCR_STATE_CH0_V << AXI_DMA_OUT_DSCR_STATE_CH0_S)
+#define AXI_DMA_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH0_S  18
+/** AXI_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_STATE_CH0    0x00000007U
+#define AXI_DMA_OUT_STATE_CH0_M  (AXI_DMA_OUT_STATE_CH0_V << AXI_DMA_OUT_STATE_CH0_S)
+#define AXI_DMA_OUT_STATE_CH0_V  0x00000007U
+#define AXI_DMA_OUT_STATE_CH0_S  20
+
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Outlink descriptor address when EOF occurs of Tx channel0
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x164)
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_M  (AXI_DMA_OUT_EOF_DES_ADDR_CH0_V << AXI_DMA_OUT_EOF_DES_ADDR_CH0_S)
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register
+ *  The last outlink descriptor address when EOF occurs of Tx channel0
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x168)
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_M  (AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_DSCR_CH0_REG register
+ *  Current outlink descriptor address of Tx channel0
+ */
+#define AXI_DMA_OUT_DSCR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x16c)
+/** AXI_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define AXI_DMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH0_M  (AXI_DMA_OUTLINK_DSCR_CH0_V << AXI_DMA_OUTLINK_DSCR_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH0_S  0
+
+/** AXI_DMA_OUT_DSCR_BF0_CH0_REG register
+ *  The last outlink descriptor address of Tx channel0
+ */
+#define AXI_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x170)
+/** AXI_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0_M  (AXI_DMA_OUTLINK_DSCR_BF0_CH0_V << AXI_DMA_OUTLINK_DSCR_BF0_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** AXI_DMA_OUT_DSCR_BF1_CH0_REG register
+ *  The second-to-last outlink descriptor address of Tx channel0
+ */
+#define AXI_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x174)
+/** AXI_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor x-2.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0_M  (AXI_DMA_OUTLINK_DSCR_BF1_CH0_V << AXI_DMA_OUTLINK_DSCR_BF1_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** AXI_DMA_OUT_PRI_CH0_REG register
+ *  Priority register of Tx channel0.
+ */
+#define AXI_DMA_OUT_PRI_CH0_REG (DR_REG_AXI_DMA_BASE + 0x178)
+/** AXI_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_TX_PRI_CH0    0x0000000FU
+#define AXI_DMA_TX_PRI_CH0_M  (AXI_DMA_TX_PRI_CH0_V << AXI_DMA_TX_PRI_CH0_S)
+#define AXI_DMA_TX_PRI_CH0_V  0x0000000FU
+#define AXI_DMA_TX_PRI_CH0_S  0
+/** AXI_DMA_TX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Tx channel0
+ */
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0    0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0_M  (AXI_DMA_TX_CH_ARB_WEIGH_CH0_V << AXI_DMA_TX_CH_ARB_WEIGH_CH0_S)
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0_V  0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0_S  4
+/** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S)
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V  0x00000001U
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S  8
+
+/** AXI_DMA_OUT_PERI_SEL_CH0_REG register
+ *  Peripheral selection of Tx channel0
+ */
+#define AXI_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x17c)
+/** AXI_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_OUT_SEL_CH0    0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH0_M  (AXI_DMA_PERI_OUT_SEL_CH0_V << AXI_DMA_PERI_OUT_SEL_CH0_S)
+#define AXI_DMA_PERI_OUT_SEL_CH0_V  0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH0_S  0
+
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x180)
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_M  (AXI_DMA_OUT_CRC_INIT_DATA_CH0_V << AXI_DMA_OUT_CRC_INIT_DATA_CH0_S)
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_S  0
+
+/** AXI_DMA_TX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH0_REG (DR_REG_AXI_DMA_BASE + 0x184)
+/** AXI_DMA_TX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH0    0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH0_M  (AXI_DMA_TX_CRC_WIDTH_CH0_V << AXI_DMA_TX_CRC_WIDTH_CH0_S)
+#define AXI_DMA_TX_CRC_WIDTH_CH0_V  0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH0_S  0
+/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_M  (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S)
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AXI_DMA_OUT_CRC_CLEAR_CH0_REG register
+ *  This register is used to clear ch0 crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x188)
+/** AXI_DMA_OUT_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH0    (BIT(0))
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_M  (AXI_DMA_OUT_CRC_CLEAR_CH0_V << AXI_DMA_OUT_CRC_CLEAR_CH0_S)
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_V  0x00000001U
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_S  0
+
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_REG (DR_REG_AXI_DMA_BASE + 0x18c)
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_M  (AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_V << AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_S)
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_S  0
+
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x190)
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_M  (AXI_DMA_TX_CRC_EN_WR_DATA_CH0_V << AXI_DMA_TX_CRC_EN_WR_DATA_CH0_S)
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_TX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x194)
+/** AXI_DMA_TX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_M  (AXI_DMA_TX_CRC_EN_ADDR_CH0_V << AXI_DMA_TX_CRC_EN_ADDR_CH0_S)
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x198)
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0    0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_M  (AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V << AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V  0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x19c)
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_M  (AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_V << AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_S)
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_INT_RAW_CH1_REG register
+ *  Raw status interrupt of channel1
+ */
+#define AXI_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1a0)
+/** AXI_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel0.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW_M  (AXI_DMA_OUT_DONE_CH1_INT_RAW_V << AXI_DMA_OUT_DONE_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel0.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW_M  (AXI_DMA_OUT_EOF_CH1_INT_RAW_V << AXI_DMA_OUT_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+ *  including owner error and the second and third word error of outlink descriptor for
+ *  Tx channel0.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_S  10
+
+/** AXI_DMA_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt of channel1
+ */
+#define AXI_DMA_OUT_INT_ST_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1a4)
+/** AXI_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_ST_M  (AXI_DMA_OUT_DONE_CH1_INT_ST_V << AXI_DMA_OUT_DONE_CH1_INT_ST_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_ST_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_ST_M  (AXI_DMA_OUT_EOF_CH1_INT_ST_V << AXI_DMA_OUT_EOF_CH1_INT_ST_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_ST_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** AXI_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST    (BIT(4))
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_S  4
+/** AXI_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST    (BIT(5))
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_S  5
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST    (BIT(6))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_S  6
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST    (BIT(7))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_S  10
+
+/** AXI_DMA_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of channel1
+ */
+#define AXI_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1a8)
+/** AXI_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA_M  (AXI_DMA_OUT_DONE_CH1_INT_ENA_V << AXI_DMA_OUT_DONE_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA_M  (AXI_DMA_OUT_EOF_CH1_INT_ENA_V << AXI_DMA_OUT_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_S  10
+
+/** AXI_DMA_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of channel1
+ */
+#define AXI_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1ac)
+/** AXI_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR_M  (AXI_DMA_OUT_DONE_CH1_INT_CLR_V << AXI_DMA_OUT_DONE_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR_M  (AXI_DMA_OUT_EOF_CH1_INT_CLR_V << AXI_DMA_OUT_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_S  10
+
+/** AXI_DMA_OUT_CONF0_CH1_REG register
+ *  Configure 0 register of Tx channel1
+ */
+#define AXI_DMA_OUT_CONF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1b0)
+/** AXI_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer.
+ */
+#define AXI_DMA_OUT_RST_CH1    (BIT(0))
+#define AXI_DMA_OUT_RST_CH1_M  (AXI_DMA_OUT_RST_CH1_V << AXI_DMA_OUT_RST_CH1_S)
+#define AXI_DMA_OUT_RST_CH1_V  0x00000001U
+#define AXI_DMA_OUT_RST_CH1_S  0
+/** AXI_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_LOOP_TEST_CH1    (BIT(1))
+#define AXI_DMA_OUT_LOOP_TEST_CH1_M  (AXI_DMA_OUT_LOOP_TEST_CH1_V << AXI_DMA_OUT_LOOP_TEST_CH1_S)
+#define AXI_DMA_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define AXI_DMA_OUT_LOOP_TEST_CH1_S  1
+/** AXI_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1    (BIT(2))
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1_M  (AXI_DMA_OUT_AUTO_WRBACK_CH1_V << AXI_DMA_OUT_AUTO_WRBACK_CH1_S)
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1_S  2
+/** AXI_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is
+ *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+ */
+#define AXI_DMA_OUT_EOF_MODE_CH1    (BIT(3))
+#define AXI_DMA_OUT_EOF_MODE_CH1_M  (AXI_DMA_OUT_EOF_MODE_CH1_V << AXI_DMA_OUT_EOF_MODE_CH1_S)
+#define AXI_DMA_OUT_EOF_MODE_CH1_V  0x00000001U
+#define AXI_DMA_OUT_EOF_MODE_CH1_S  3
+/** AXI_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_OUT_ETM_EN_CH1    (BIT(4))
+#define AXI_DMA_OUT_ETM_EN_CH1_M  (AXI_DMA_OUT_ETM_EN_CH1_V << AXI_DMA_OUT_ETM_EN_CH1_S)
+#define AXI_DMA_OUT_ETM_EN_CH1_V  0x00000001U
+#define AXI_DMA_OUT_ETM_EN_CH1_S  4
+/** AXI_DMA_OUT_BURST_SIZE_SEL_CH1 : R/W; bitpos: [7:5]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1    0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1_M  (AXI_DMA_OUT_BURST_SIZE_SEL_CH1_V << AXI_DMA_OUT_BURST_SIZE_SEL_CH1_S)
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1_V  0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1_S  5
+/** AXI_DMA_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [8]; default: 0;
+ *  1:mean disable cmd of this ch1
+ */
+#define AXI_DMA_OUT_CMD_DISABLE_CH1    (BIT(8))
+#define AXI_DMA_OUT_CMD_DISABLE_CH1_M  (AXI_DMA_OUT_CMD_DISABLE_CH1_V << AXI_DMA_OUT_CMD_DISABLE_CH1_S)
+#define AXI_DMA_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define AXI_DMA_OUT_CMD_DISABLE_CH1_S  8
+/** AXI_DMA_OUT_ECC_AEC_EN_CH1 : R/W; bitpos: [9]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1    (BIT(9))
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1_M  (AXI_DMA_OUT_ECC_AEC_EN_CH1_V << AXI_DMA_OUT_ECC_AEC_EN_CH1_S)
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1_V  0x00000001U
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1_S  9
+/** AXI_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1    (BIT(10))
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1_M  (AXI_DMA_OUTDSCR_BURST_EN_CH1_V << AXI_DMA_OUTDSCR_BURST_EN_CH1_S)
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1_S  10
+
+/** AXI_DMA_OUT_CONF1_CH1_REG register
+ *  Configure 1 register of Tx channel1
+ */
+#define AXI_DMA_OUT_CONF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1b4)
+/** AXI_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_OUT_CHECK_OWNER_CH1    (BIT(12))
+#define AXI_DMA_OUT_CHECK_OWNER_CH1_M  (AXI_DMA_OUT_CHECK_OWNER_CH1_V << AXI_DMA_OUT_CHECK_OWNER_CH1_S)
+#define AXI_DMA_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define AXI_DMA_OUT_CHECK_OWNER_CH1_S  12
+
+/** AXI_DMA_OUTFIFO_STATUS_CH1_REG register
+ *  Transmit FIFO status of Tx channel1
+ */
+#define AXI_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1b8)
+/** AXI_DMA_OUTFIFO_L3_FULL_CH1 : RO; bitpos: [0]; default: 0;
+ *  L3 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1    (BIT(0))
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1_M  (AXI_DMA_OUTFIFO_L3_FULL_CH1_V << AXI_DMA_OUTFIFO_L3_FULL_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1_S  0
+/** AXI_DMA_OUTFIFO_L3_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  L3 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1    (BIT(1))
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1_M  (AXI_DMA_OUTFIFO_L3_EMPTY_CH1_V << AXI_DMA_OUTFIFO_L3_EMPTY_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1_S  1
+/** AXI_DMA_OUTFIFO_L3_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1    0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1_M  (AXI_DMA_OUTFIFO_L3_CNT_CH1_V << AXI_DMA_OUTFIFO_L3_CNT_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1_S  2
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1 : RO; bitpos: [8]; default: 0;
+ *  L3 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_S  8
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1 : RO; bitpos: [9]; default: 0;
+ *  L3 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_S  9
+/** AXI_DMA_OUTFIFO_L1_FULL_CH1 : RO; bitpos: [10]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1    (BIT(10))
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1_M  (AXI_DMA_OUTFIFO_L1_FULL_CH1_V << AXI_DMA_OUTFIFO_L1_FULL_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1_S  10
+/** AXI_DMA_OUTFIFO_L1_EMPTY_CH1 : RO; bitpos: [11]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1    (BIT(11))
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1_M  (AXI_DMA_OUTFIFO_L1_EMPTY_CH1_V << AXI_DMA_OUTFIFO_L1_EMPTY_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1_S  11
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1 : RO; bitpos: [12]; default: 0;
+ *  L1 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1    (BIT(12))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_S  12
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1 : RO; bitpos: [13]; default: 0;
+ *  L1 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1    (BIT(13))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_S  13
+/** AXI_DMA_OUTFIFO_L2_FULL_CH1 : RO; bitpos: [14]; default: 0;
+ *  L2 Tx RAM full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1    (BIT(14))
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1_M  (AXI_DMA_OUTFIFO_L2_FULL_CH1_V << AXI_DMA_OUTFIFO_L2_FULL_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1_S  14
+/** AXI_DMA_OUTFIFO_L2_EMPTY_CH1 : RO; bitpos: [15]; default: 1;
+ *  L2 Tx RAM empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1    (BIT(15))
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1_M  (AXI_DMA_OUTFIFO_L2_EMPTY_CH1_V << AXI_DMA_OUTFIFO_L2_EMPTY_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1_S  15
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1 : RO; bitpos: [16]; default: 0;
+ *  L2 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1    (BIT(16))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_S  16
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1 : RO; bitpos: [17]; default: 0;
+ *  L2 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1    (BIT(17))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_S  17
+/** AXI_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_S  23
+/** AXI_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_S  24
+/** AXI_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_S  25
+/** AXI_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_S  26
+/** AXI_DMA_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [27]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1    (BIT(27))
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_S  27
+/** AXI_DMA_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1    (BIT(28))
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_S  28
+/** AXI_DMA_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1    (BIT(29))
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_S  29
+/** AXI_DMA_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1    (BIT(30))
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_S  30
+
+/** AXI_DMA_OUT_PUSH_CH1_REG register
+ *  Push control register of Tx channel1
+ */
+#define AXI_DMA_OUT_PUSH_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1bc)
+/** AXI_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_WDATA_CH1    0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH1_M  (AXI_DMA_OUTFIFO_WDATA_CH1_V << AXI_DMA_OUTFIFO_WDATA_CH1_S)
+#define AXI_DMA_OUTFIFO_WDATA_CH1_V  0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH1_S  0
+/** AXI_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0;
+ *  Set this bit to push data into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_PUSH_CH1    (BIT(9))
+#define AXI_DMA_OUTFIFO_PUSH_CH1_M  (AXI_DMA_OUTFIFO_PUSH_CH1_V << AXI_DMA_OUTFIFO_PUSH_CH1_S)
+#define AXI_DMA_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_PUSH_CH1_S  9
+
+/** AXI_DMA_OUT_LINK1_CH1_REG register
+ *  Link descriptor configure and control register of Tx channel1
+ */
+#define AXI_DMA_OUT_LINK1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1c0)
+/** AXI_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_STOP_CH1    (BIT(0))
+#define AXI_DMA_OUTLINK_STOP_CH1_M  (AXI_DMA_OUTLINK_STOP_CH1_V << AXI_DMA_OUTLINK_STOP_CH1_S)
+#define AXI_DMA_OUTLINK_STOP_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_STOP_CH1_S  0
+/** AXI_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_START_CH1    (BIT(1))
+#define AXI_DMA_OUTLINK_START_CH1_M  (AXI_DMA_OUTLINK_START_CH1_V << AXI_DMA_OUTLINK_START_CH1_S)
+#define AXI_DMA_OUTLINK_START_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_START_CH1_S  1
+/** AXI_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define AXI_DMA_OUTLINK_RESTART_CH1    (BIT(2))
+#define AXI_DMA_OUTLINK_RESTART_CH1_M  (AXI_DMA_OUTLINK_RESTART_CH1_V << AXI_DMA_OUTLINK_RESTART_CH1_S)
+#define AXI_DMA_OUTLINK_RESTART_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_RESTART_CH1_S  2
+/** AXI_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define AXI_DMA_OUTLINK_PARK_CH1    (BIT(3))
+#define AXI_DMA_OUTLINK_PARK_CH1_M  (AXI_DMA_OUTLINK_PARK_CH1_V << AXI_DMA_OUTLINK_PARK_CH1_S)
+#define AXI_DMA_OUTLINK_PARK_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_PARK_CH1_S  3
+
+/** AXI_DMA_OUT_LINK2_CH1_REG register
+ *  Link descriptor configure and control register of Tx channel1
+ */
+#define AXI_DMA_OUT_LINK2_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1c4)
+/** AXI_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 32 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH1_M  (AXI_DMA_OUTLINK_ADDR_CH1_V << AXI_DMA_OUTLINK_ADDR_CH1_S)
+#define AXI_DMA_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_STATE_CH1_REG register
+ *  Transmit status of Tx channel1
+ */
+#define AXI_DMA_OUT_STATE_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1c8)
+/** AXI_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1_M  (AXI_DMA_OUTLINK_DSCR_ADDR_CH1_V << AXI_DMA_OUTLINK_DSCR_ADDR_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1_S  0
+/** AXI_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_DSCR_STATE_CH1    0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH1_M  (AXI_DMA_OUT_DSCR_STATE_CH1_V << AXI_DMA_OUT_DSCR_STATE_CH1_S)
+#define AXI_DMA_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH1_S  18
+/** AXI_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_STATE_CH1    0x00000007U
+#define AXI_DMA_OUT_STATE_CH1_M  (AXI_DMA_OUT_STATE_CH1_V << AXI_DMA_OUT_STATE_CH1_S)
+#define AXI_DMA_OUT_STATE_CH1_V  0x00000007U
+#define AXI_DMA_OUT_STATE_CH1_S  20
+
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Outlink descriptor address when EOF occurs of Tx channel1
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1cc)
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_M  (AXI_DMA_OUT_EOF_DES_ADDR_CH1_V << AXI_DMA_OUT_EOF_DES_ADDR_CH1_S)
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register
+ *  The last outlink descriptor address when EOF occurs of Tx channel1
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1d0)
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_M  (AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_DSCR_CH1_REG register
+ *  Current outlink descriptor address of Tx channel1
+ */
+#define AXI_DMA_OUT_DSCR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1d4)
+/** AXI_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define AXI_DMA_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH1_M  (AXI_DMA_OUTLINK_DSCR_CH1_V << AXI_DMA_OUTLINK_DSCR_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH1_S  0
+
+/** AXI_DMA_OUT_DSCR_BF0_CH1_REG register
+ *  The last outlink descriptor address of Tx channel1
+ */
+#define AXI_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1d8)
+/** AXI_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1_M  (AXI_DMA_OUTLINK_DSCR_BF0_CH1_V << AXI_DMA_OUTLINK_DSCR_BF0_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** AXI_DMA_OUT_DSCR_BF1_CH1_REG register
+ *  The second-to-last outlink descriptor address of Tx channel1
+ */
+#define AXI_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1dc)
+/** AXI_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor x-2.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1_M  (AXI_DMA_OUTLINK_DSCR_BF1_CH1_V << AXI_DMA_OUTLINK_DSCR_BF1_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** AXI_DMA_OUT_PRI_CH1_REG register
+ *  Priority register of Tx channel1.
+ */
+#define AXI_DMA_OUT_PRI_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1e0)
+/** AXI_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_TX_PRI_CH1    0x0000000FU
+#define AXI_DMA_TX_PRI_CH1_M  (AXI_DMA_TX_PRI_CH1_V << AXI_DMA_TX_PRI_CH1_S)
+#define AXI_DMA_TX_PRI_CH1_V  0x0000000FU
+#define AXI_DMA_TX_PRI_CH1_S  0
+/** AXI_DMA_TX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Tx channel0
+ */
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1    0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1_M  (AXI_DMA_TX_CH_ARB_WEIGH_CH1_V << AXI_DMA_TX_CH_ARB_WEIGH_CH1_S)
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1_V  0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1_S  4
+/** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S)
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V  0x00000001U
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S  8
+
+/** AXI_DMA_OUT_PERI_SEL_CH1_REG register
+ *  Peripheral selection of Tx channel1
+ */
+#define AXI_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1e4)
+/** AXI_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_OUT_SEL_CH1    0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH1_M  (AXI_DMA_PERI_OUT_SEL_CH1_V << AXI_DMA_PERI_OUT_SEL_CH1_S)
+#define AXI_DMA_PERI_OUT_SEL_CH1_V  0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH1_S  0
+
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1e8)
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_M  (AXI_DMA_OUT_CRC_INIT_DATA_CH1_V << AXI_DMA_OUT_CRC_INIT_DATA_CH1_S)
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_S  0
+
+/** AXI_DMA_TX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1ec)
+/** AXI_DMA_TX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH1    0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH1_M  (AXI_DMA_TX_CRC_WIDTH_CH1_V << AXI_DMA_TX_CRC_WIDTH_CH1_S)
+#define AXI_DMA_TX_CRC_WIDTH_CH1_V  0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH1_S  0
+/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_M  (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S)
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AXI_DMA_OUT_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f0)
+/** AXI_DMA_OUT_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH1    (BIT(0))
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_M  (AXI_DMA_OUT_CRC_CLEAR_CH1_V << AXI_DMA_OUT_CRC_CLEAR_CH1_S)
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_V  0x00000001U
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_S  0
+
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f4)
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_M  (AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_V << AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_S)
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_S  0
+
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f8)
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_M  (AXI_DMA_TX_CRC_EN_WR_DATA_CH1_V << AXI_DMA_TX_CRC_EN_WR_DATA_CH1_S)
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_TX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1fc)
+/** AXI_DMA_TX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_M  (AXI_DMA_TX_CRC_EN_ADDR_CH1_V << AXI_DMA_TX_CRC_EN_ADDR_CH1_S)
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x200)
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1    0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_M  (AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V << AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V  0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x204)
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_M  (AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_V << AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_S)
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_INT_RAW_CH2_REG register
+ *  Raw status interrupt of channel2
+ */
+#define AXI_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AXI_DMA_BASE + 0x208)
+/** AXI_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel0.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW_M  (AXI_DMA_OUT_DONE_CH2_INT_RAW_V << AXI_DMA_OUT_DONE_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel0.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW_M  (AXI_DMA_OUT_EOF_CH2_INT_RAW_V << AXI_DMA_OUT_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+ *  including owner error and the second and third word error of outlink descriptor for
+ *  Tx channel0.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_S  10
+
+/** AXI_DMA_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt of channel2
+ */
+#define AXI_DMA_OUT_INT_ST_CH2_REG (DR_REG_AXI_DMA_BASE + 0x20c)
+/** AXI_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_ST_M  (AXI_DMA_OUT_DONE_CH2_INT_ST_V << AXI_DMA_OUT_DONE_CH2_INT_ST_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_ST_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_ST_M  (AXI_DMA_OUT_EOF_CH2_INT_ST_V << AXI_DMA_OUT_EOF_CH2_INT_ST_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_ST_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** AXI_DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST    (BIT(4))
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_S  4
+/** AXI_DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST    (BIT(5))
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_S  5
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST    (BIT(6))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_S  6
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST    (BIT(7))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_S  10
+
+/** AXI_DMA_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of channel2
+ */
+#define AXI_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x210)
+/** AXI_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA_M  (AXI_DMA_OUT_DONE_CH2_INT_ENA_V << AXI_DMA_OUT_DONE_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA_M  (AXI_DMA_OUT_EOF_CH2_INT_ENA_V << AXI_DMA_OUT_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_S  10
+
+/** AXI_DMA_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of channel2
+ */
+#define AXI_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x214)
+/** AXI_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR_M  (AXI_DMA_OUT_DONE_CH2_INT_CLR_V << AXI_DMA_OUT_DONE_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR_M  (AXI_DMA_OUT_EOF_CH2_INT_CLR_V << AXI_DMA_OUT_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_S  10
+
+/** AXI_DMA_OUT_CONF0_CH2_REG register
+ *  Configure 0 register of Tx channel2
+ */
+#define AXI_DMA_OUT_CONF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0x218)
+/** AXI_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer.
+ */
+#define AXI_DMA_OUT_RST_CH2    (BIT(0))
+#define AXI_DMA_OUT_RST_CH2_M  (AXI_DMA_OUT_RST_CH2_V << AXI_DMA_OUT_RST_CH2_S)
+#define AXI_DMA_OUT_RST_CH2_V  0x00000001U
+#define AXI_DMA_OUT_RST_CH2_S  0
+/** AXI_DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_LOOP_TEST_CH2    (BIT(1))
+#define AXI_DMA_OUT_LOOP_TEST_CH2_M  (AXI_DMA_OUT_LOOP_TEST_CH2_V << AXI_DMA_OUT_LOOP_TEST_CH2_S)
+#define AXI_DMA_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define AXI_DMA_OUT_LOOP_TEST_CH2_S  1
+/** AXI_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2    (BIT(2))
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2_M  (AXI_DMA_OUT_AUTO_WRBACK_CH2_V << AXI_DMA_OUT_AUTO_WRBACK_CH2_S)
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2_S  2
+/** AXI_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is
+ *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+ */
+#define AXI_DMA_OUT_EOF_MODE_CH2    (BIT(3))
+#define AXI_DMA_OUT_EOF_MODE_CH2_M  (AXI_DMA_OUT_EOF_MODE_CH2_V << AXI_DMA_OUT_EOF_MODE_CH2_S)
+#define AXI_DMA_OUT_EOF_MODE_CH2_V  0x00000001U
+#define AXI_DMA_OUT_EOF_MODE_CH2_S  3
+/** AXI_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_OUT_ETM_EN_CH2    (BIT(4))
+#define AXI_DMA_OUT_ETM_EN_CH2_M  (AXI_DMA_OUT_ETM_EN_CH2_V << AXI_DMA_OUT_ETM_EN_CH2_S)
+#define AXI_DMA_OUT_ETM_EN_CH2_V  0x00000001U
+#define AXI_DMA_OUT_ETM_EN_CH2_S  4
+/** AXI_DMA_OUT_BURST_SIZE_SEL_CH2 : R/W; bitpos: [7:5]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2    0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2_M  (AXI_DMA_OUT_BURST_SIZE_SEL_CH2_V << AXI_DMA_OUT_BURST_SIZE_SEL_CH2_S)
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2_V  0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2_S  5
+/** AXI_DMA_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [8]; default: 0;
+ *  1:mean disable cmd of this ch2
+ */
+#define AXI_DMA_OUT_CMD_DISABLE_CH2    (BIT(8))
+#define AXI_DMA_OUT_CMD_DISABLE_CH2_M  (AXI_DMA_OUT_CMD_DISABLE_CH2_V << AXI_DMA_OUT_CMD_DISABLE_CH2_S)
+#define AXI_DMA_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define AXI_DMA_OUT_CMD_DISABLE_CH2_S  8
+/** AXI_DMA_OUT_ECC_AEC_EN_CH2 : R/W; bitpos: [9]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2    (BIT(9))
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2_M  (AXI_DMA_OUT_ECC_AEC_EN_CH2_V << AXI_DMA_OUT_ECC_AEC_EN_CH2_S)
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2_V  0x00000001U
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2_S  9
+/** AXI_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2    (BIT(10))
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2_M  (AXI_DMA_OUTDSCR_BURST_EN_CH2_V << AXI_DMA_OUTDSCR_BURST_EN_CH2_S)
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2_S  10
+
+/** AXI_DMA_OUT_CONF1_CH2_REG register
+ *  Configure 1 register of Tx channel2
+ */
+#define AXI_DMA_OUT_CONF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x21c)
+/** AXI_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_OUT_CHECK_OWNER_CH2    (BIT(12))
+#define AXI_DMA_OUT_CHECK_OWNER_CH2_M  (AXI_DMA_OUT_CHECK_OWNER_CH2_V << AXI_DMA_OUT_CHECK_OWNER_CH2_S)
+#define AXI_DMA_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define AXI_DMA_OUT_CHECK_OWNER_CH2_S  12
+
+/** AXI_DMA_OUTFIFO_STATUS_CH2_REG register
+ *  Transmit FIFO status of Tx channel2
+ */
+#define AXI_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AXI_DMA_BASE + 0x220)
+/** AXI_DMA_OUTFIFO_L3_FULL_CH2 : RO; bitpos: [0]; default: 0;
+ *  L3 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2    (BIT(0))
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2_M  (AXI_DMA_OUTFIFO_L3_FULL_CH2_V << AXI_DMA_OUTFIFO_L3_FULL_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2_S  0
+/** AXI_DMA_OUTFIFO_L3_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  L3 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2    (BIT(1))
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2_M  (AXI_DMA_OUTFIFO_L3_EMPTY_CH2_V << AXI_DMA_OUTFIFO_L3_EMPTY_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2_S  1
+/** AXI_DMA_OUTFIFO_L3_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2    0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2_M  (AXI_DMA_OUTFIFO_L3_CNT_CH2_V << AXI_DMA_OUTFIFO_L3_CNT_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2_S  2
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2 : RO; bitpos: [8]; default: 0;
+ *  L3 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_S  8
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2 : RO; bitpos: [9]; default: 0;
+ *  L3 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_S  9
+/** AXI_DMA_OUTFIFO_L1_FULL_CH2 : RO; bitpos: [10]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2    (BIT(10))
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2_M  (AXI_DMA_OUTFIFO_L1_FULL_CH2_V << AXI_DMA_OUTFIFO_L1_FULL_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2_S  10
+/** AXI_DMA_OUTFIFO_L1_EMPTY_CH2 : RO; bitpos: [11]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2    (BIT(11))
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2_M  (AXI_DMA_OUTFIFO_L1_EMPTY_CH2_V << AXI_DMA_OUTFIFO_L1_EMPTY_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2_S  11
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2 : RO; bitpos: [12]; default: 0;
+ *  L1 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2    (BIT(12))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_S  12
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2 : RO; bitpos: [13]; default: 0;
+ *  L1 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2    (BIT(13))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_S  13
+/** AXI_DMA_OUTFIFO_L2_FULL_CH2 : RO; bitpos: [14]; default: 0;
+ *  L2 Tx RAM full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2    (BIT(14))
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2_M  (AXI_DMA_OUTFIFO_L2_FULL_CH2_V << AXI_DMA_OUTFIFO_L2_FULL_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2_S  14
+/** AXI_DMA_OUTFIFO_L2_EMPTY_CH2 : RO; bitpos: [15]; default: 1;
+ *  L2 Tx RAM empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2    (BIT(15))
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2_M  (AXI_DMA_OUTFIFO_L2_EMPTY_CH2_V << AXI_DMA_OUTFIFO_L2_EMPTY_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2_S  15
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2 : RO; bitpos: [16]; default: 0;
+ *  L2 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2    (BIT(16))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_S  16
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2 : RO; bitpos: [17]; default: 0;
+ *  L2 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2    (BIT(17))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_S  17
+/** AXI_DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_S  23
+/** AXI_DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_S  24
+/** AXI_DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_S  25
+/** AXI_DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_S  26
+/** AXI_DMA_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [27]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2    (BIT(27))
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_S  27
+/** AXI_DMA_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2    (BIT(28))
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_S  28
+/** AXI_DMA_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2    (BIT(29))
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_S  29
+/** AXI_DMA_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2    (BIT(30))
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_S  30
+
+/** AXI_DMA_OUT_PUSH_CH2_REG register
+ *  Push control register of Tx channel2
+ */
+#define AXI_DMA_OUT_PUSH_CH2_REG (DR_REG_AXI_DMA_BASE + 0x224)
+/** AXI_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_WDATA_CH2    0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH2_M  (AXI_DMA_OUTFIFO_WDATA_CH2_V << AXI_DMA_OUTFIFO_WDATA_CH2_S)
+#define AXI_DMA_OUTFIFO_WDATA_CH2_V  0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH2_S  0
+/** AXI_DMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0;
+ *  Set this bit to push data into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_PUSH_CH2    (BIT(9))
+#define AXI_DMA_OUTFIFO_PUSH_CH2_M  (AXI_DMA_OUTFIFO_PUSH_CH2_V << AXI_DMA_OUTFIFO_PUSH_CH2_S)
+#define AXI_DMA_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_PUSH_CH2_S  9
+
+/** AXI_DMA_OUT_LINK1_CH2_REG register
+ *  Link descriptor configure and control register of Tx channel2
+ */
+#define AXI_DMA_OUT_LINK1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x228)
+/** AXI_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_STOP_CH2    (BIT(0))
+#define AXI_DMA_OUTLINK_STOP_CH2_M  (AXI_DMA_OUTLINK_STOP_CH2_V << AXI_DMA_OUTLINK_STOP_CH2_S)
+#define AXI_DMA_OUTLINK_STOP_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_STOP_CH2_S  0
+/** AXI_DMA_OUTLINK_START_CH2 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_START_CH2    (BIT(1))
+#define AXI_DMA_OUTLINK_START_CH2_M  (AXI_DMA_OUTLINK_START_CH2_V << AXI_DMA_OUTLINK_START_CH2_S)
+#define AXI_DMA_OUTLINK_START_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_START_CH2_S  1
+/** AXI_DMA_OUTLINK_RESTART_CH2 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define AXI_DMA_OUTLINK_RESTART_CH2    (BIT(2))
+#define AXI_DMA_OUTLINK_RESTART_CH2_M  (AXI_DMA_OUTLINK_RESTART_CH2_V << AXI_DMA_OUTLINK_RESTART_CH2_S)
+#define AXI_DMA_OUTLINK_RESTART_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_RESTART_CH2_S  2
+/** AXI_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [3]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define AXI_DMA_OUTLINK_PARK_CH2    (BIT(3))
+#define AXI_DMA_OUTLINK_PARK_CH2_M  (AXI_DMA_OUTLINK_PARK_CH2_V << AXI_DMA_OUTLINK_PARK_CH2_S)
+#define AXI_DMA_OUTLINK_PARK_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_PARK_CH2_S  3
+
+/** AXI_DMA_OUT_LINK2_CH2_REG register
+ *  Link descriptor configure and control register of Tx channel2
+ */
+#define AXI_DMA_OUT_LINK2_CH2_REG (DR_REG_AXI_DMA_BASE + 0x22c)
+/** AXI_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 32 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH2_M  (AXI_DMA_OUTLINK_ADDR_CH2_V << AXI_DMA_OUTLINK_ADDR_CH2_S)
+#define AXI_DMA_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_STATE_CH2_REG register
+ *  Transmit status of Tx channel2
+ */
+#define AXI_DMA_OUT_STATE_CH2_REG (DR_REG_AXI_DMA_BASE + 0x230)
+/** AXI_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2_M  (AXI_DMA_OUTLINK_DSCR_ADDR_CH2_V << AXI_DMA_OUTLINK_DSCR_ADDR_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2_S  0
+/** AXI_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_DSCR_STATE_CH2    0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH2_M  (AXI_DMA_OUT_DSCR_STATE_CH2_V << AXI_DMA_OUT_DSCR_STATE_CH2_S)
+#define AXI_DMA_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH2_S  18
+/** AXI_DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_STATE_CH2    0x00000007U
+#define AXI_DMA_OUT_STATE_CH2_M  (AXI_DMA_OUT_STATE_CH2_V << AXI_DMA_OUT_STATE_CH2_S)
+#define AXI_DMA_OUT_STATE_CH2_V  0x00000007U
+#define AXI_DMA_OUT_STATE_CH2_S  20
+
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Outlink descriptor address when EOF occurs of Tx channel2
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x234)
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_M  (AXI_DMA_OUT_EOF_DES_ADDR_CH2_V << AXI_DMA_OUT_EOF_DES_ADDR_CH2_S)
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register
+ *  The last outlink descriptor address when EOF occurs of Tx channel2
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x238)
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_M  (AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_DSCR_CH2_REG register
+ *  Current outlink descriptor address of Tx channel2
+ */
+#define AXI_DMA_OUT_DSCR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x23c)
+/** AXI_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define AXI_DMA_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH2_M  (AXI_DMA_OUTLINK_DSCR_CH2_V << AXI_DMA_OUTLINK_DSCR_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH2_S  0
+
+/** AXI_DMA_OUT_DSCR_BF0_CH2_REG register
+ *  The last outlink descriptor address of Tx channel2
+ */
+#define AXI_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0x240)
+/** AXI_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2_M  (AXI_DMA_OUTLINK_DSCR_BF0_CH2_V << AXI_DMA_OUTLINK_DSCR_BF0_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** AXI_DMA_OUT_DSCR_BF1_CH2_REG register
+ *  The second-to-last outlink descriptor address of Tx channel2
+ */
+#define AXI_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x244)
+/** AXI_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor x-2.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2_M  (AXI_DMA_OUTLINK_DSCR_BF1_CH2_V << AXI_DMA_OUTLINK_DSCR_BF1_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** AXI_DMA_OUT_PRI_CH2_REG register
+ *  Priority register of Tx channel2.
+ */
+#define AXI_DMA_OUT_PRI_CH2_REG (DR_REG_AXI_DMA_BASE + 0x248)
+/** AXI_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_TX_PRI_CH2    0x0000000FU
+#define AXI_DMA_TX_PRI_CH2_M  (AXI_DMA_TX_PRI_CH2_V << AXI_DMA_TX_PRI_CH2_S)
+#define AXI_DMA_TX_PRI_CH2_V  0x0000000FU
+#define AXI_DMA_TX_PRI_CH2_S  0
+/** AXI_DMA_TX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Tx channel0
+ */
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2_M  (AXI_DMA_TX_CH_ARB_WEIGH_CH2_V << AXI_DMA_TX_CH_ARB_WEIGH_CH2_S)
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2_S  4
+/** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S  8
+
+/** AXI_DMA_OUT_PERI_SEL_CH2_REG register
+ *  Peripheral selection of Tx channel2
+ */
+#define AXI_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x24c)
+/** AXI_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_OUT_SEL_CH2    0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH2_M  (AXI_DMA_PERI_OUT_SEL_CH2_V << AXI_DMA_PERI_OUT_SEL_CH2_S)
+#define AXI_DMA_PERI_OUT_SEL_CH2_V  0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH2_S  0
+
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x250)
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_M  (AXI_DMA_OUT_CRC_INIT_DATA_CH2_V << AXI_DMA_OUT_CRC_INIT_DATA_CH2_S)
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_S  0
+
+/** AXI_DMA_TX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig tx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH2_REG (DR_REG_AXI_DMA_BASE + 0x254)
+/** AXI_DMA_TX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH2    0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH2_M  (AXI_DMA_TX_CRC_WIDTH_CH2_V << AXI_DMA_TX_CRC_WIDTH_CH2_S)
+#define AXI_DMA_TX_CRC_WIDTH_CH2_V  0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH2_S  0
+/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_M  (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S)
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AXI_DMA_OUT_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x258)
+/** AXI_DMA_OUT_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH2    (BIT(0))
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_M  (AXI_DMA_OUT_CRC_CLEAR_CH2_V << AXI_DMA_OUT_CRC_CLEAR_CH2_S)
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_V  0x00000001U
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_S  0
+
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_REG (DR_REG_AXI_DMA_BASE + 0x25c)
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_M  (AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_V << AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_S)
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_S  0
+
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x260)
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_M  (AXI_DMA_TX_CRC_EN_WR_DATA_CH2_V << AXI_DMA_TX_CRC_EN_WR_DATA_CH2_S)
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_TX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x264)
+/** AXI_DMA_TX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_M  (AXI_DMA_TX_CRC_EN_ADDR_CH2_V << AXI_DMA_TX_CRC_EN_ADDR_CH2_S)
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x268)
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2    0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_M  (AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V << AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V  0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x26c)
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_M  (AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_V << AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_S)
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_ARB_TIMEOUT_REG register
+ *  This retister is used to config arbiter time slice
+ */
+#define AXI_DMA_ARB_TIMEOUT_REG (DR_REG_AXI_DMA_BASE + 0x270)
+/** AXI_DMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to config tx arbiter time out value
+ */
+#define AXI_DMA_ARB_TIMEOUT_TX    0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_TX_M  (AXI_DMA_ARB_TIMEOUT_TX_V << AXI_DMA_ARB_TIMEOUT_TX_S)
+#define AXI_DMA_ARB_TIMEOUT_TX_V  0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_TX_S  0
+/** AXI_DMA_ARB_TIMEOUT_RX : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to config rx arbiter time out value
+ */
+#define AXI_DMA_ARB_TIMEOUT_RX    0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_RX_M  (AXI_DMA_ARB_TIMEOUT_RX_V << AXI_DMA_ARB_TIMEOUT_RX_S)
+#define AXI_DMA_ARB_TIMEOUT_RX_V  0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_RX_S  16
+
+/** AXI_DMA_WEIGHT_EN_REG register
+ *  This register is used to config arbiter weight function to on or off
+ */
+#define AXI_DMA_WEIGHT_EN_REG (DR_REG_AXI_DMA_BASE + 0x274)
+/** AXI_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0;
+ *  This register is used to config tx arbiter weight function  off/on
+ */
+#define AXI_DMA_WEIGHT_EN_TX    (BIT(0))
+#define AXI_DMA_WEIGHT_EN_TX_M  (AXI_DMA_WEIGHT_EN_TX_V << AXI_DMA_WEIGHT_EN_TX_S)
+#define AXI_DMA_WEIGHT_EN_TX_V  0x00000001U
+#define AXI_DMA_WEIGHT_EN_TX_S  0
+/** AXI_DMA_WEIGHT_EN_RX : R/W; bitpos: [1]; default: 0;
+ *  This register is used to config rx arbiter weight function  off/on
+ */
+#define AXI_DMA_WEIGHT_EN_RX    (BIT(1))
+#define AXI_DMA_WEIGHT_EN_RX_M  (AXI_DMA_WEIGHT_EN_RX_V << AXI_DMA_WEIGHT_EN_RX_S)
+#define AXI_DMA_WEIGHT_EN_RX_V  0x00000001U
+#define AXI_DMA_WEIGHT_EN_RX_S  1
+
+/** AXI_DMA_IN_MEM_CONF_REG register
+ *  Mem power configure register of Rx channel
+ */
+#define AXI_DMA_IN_MEM_CONF_REG (DR_REG_AXI_DMA_BASE + 0x278)
+/** AXI_DMA_IN_MEM_CLK_FORCE_EN : R/W; bitpos: [0]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+ *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+ */
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN    (BIT(0))
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN_M  (AXI_DMA_IN_MEM_CLK_FORCE_EN_V << AXI_DMA_IN_MEM_CLK_FORCE_EN_S)
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN_V  0x00000001U
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN_S  0
+/** AXI_DMA_IN_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0;
+ *  Force power up ram
+ */
+#define AXI_DMA_IN_MEM_FORCE_PU    (BIT(1))
+#define AXI_DMA_IN_MEM_FORCE_PU_M  (AXI_DMA_IN_MEM_FORCE_PU_V << AXI_DMA_IN_MEM_FORCE_PU_S)
+#define AXI_DMA_IN_MEM_FORCE_PU_V  0x00000001U
+#define AXI_DMA_IN_MEM_FORCE_PU_S  1
+/** AXI_DMA_IN_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Force power down ram
+ */
+#define AXI_DMA_IN_MEM_FORCE_PD    (BIT(2))
+#define AXI_DMA_IN_MEM_FORCE_PD_M  (AXI_DMA_IN_MEM_FORCE_PD_V << AXI_DMA_IN_MEM_FORCE_PD_S)
+#define AXI_DMA_IN_MEM_FORCE_PD_V  0x00000001U
+#define AXI_DMA_IN_MEM_FORCE_PD_S  2
+/** AXI_DMA_OUT_MEM_CLK_FORCE_EN : R/W; bitpos: [3]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+ *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+ */
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN    (BIT(3))
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN_M  (AXI_DMA_OUT_MEM_CLK_FORCE_EN_V << AXI_DMA_OUT_MEM_CLK_FORCE_EN_S)
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN_V  0x00000001U
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN_S  3
+/** AXI_DMA_OUT_MEM_FORCE_PU : R/W; bitpos: [4]; default: 0;
+ *  Force power up ram
+ */
+#define AXI_DMA_OUT_MEM_FORCE_PU    (BIT(4))
+#define AXI_DMA_OUT_MEM_FORCE_PU_M  (AXI_DMA_OUT_MEM_FORCE_PU_V << AXI_DMA_OUT_MEM_FORCE_PU_S)
+#define AXI_DMA_OUT_MEM_FORCE_PU_V  0x00000001U
+#define AXI_DMA_OUT_MEM_FORCE_PU_S  4
+/** AXI_DMA_OUT_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  Force power down ram
+ */
+#define AXI_DMA_OUT_MEM_FORCE_PD    (BIT(5))
+#define AXI_DMA_OUT_MEM_FORCE_PD_M  (AXI_DMA_OUT_MEM_FORCE_PD_V << AXI_DMA_OUT_MEM_FORCE_PD_S)
+#define AXI_DMA_OUT_MEM_FORCE_PD_V  0x00000001U
+#define AXI_DMA_OUT_MEM_FORCE_PD_S  5
+
+/** AXI_DMA_INTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x27c)
+/** AXI_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR_M  (AXI_DMA_ACCESS_INTR_MEM_START_ADDR_V << AXI_DMA_ACCESS_INTR_MEM_START_ADDR_S)
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** AXI_DMA_INTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_INTR_MEM_END_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x280)
+/** AXI_DMA_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR_M  (AXI_DMA_ACCESS_INTR_MEM_END_ADDR_V << AXI_DMA_ACCESS_INTR_MEM_END_ADDR_S)
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** AXI_DMA_EXTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_EXTR_MEM_START_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x284)
+/** AXI_DMA_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_M  (AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_V << AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_S)
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_S  0
+
+/** AXI_DMA_EXTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_EXTR_MEM_END_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x288)
+/** AXI_DMA_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_M  (AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_V << AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_S)
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_S  0
+
+/** AXI_DMA_IN_RESET_AVAIL_CH0_REG register
+ *  The rx channel 0 reset valid_flag register.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x28c)
+/** AXI_DMA_IN_RESET_AVAIL_CH0 : RO; bitpos: [0]; default: 1;
+ *  rx chan0 reset valid reg.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH0    (BIT(0))
+#define AXI_DMA_IN_RESET_AVAIL_CH0_M  (AXI_DMA_IN_RESET_AVAIL_CH0_V << AXI_DMA_IN_RESET_AVAIL_CH0_S)
+#define AXI_DMA_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define AXI_DMA_IN_RESET_AVAIL_CH0_S  0
+
+/** AXI_DMA_IN_RESET_AVAIL_CH1_REG register
+ *  The rx channel 1 reset valid_flag register.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH1_REG (DR_REG_AXI_DMA_BASE + 0x290)
+/** AXI_DMA_IN_RESET_AVAIL_CH1 : RO; bitpos: [0]; default: 1;
+ *  rx chan0 reset valid reg.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH1    (BIT(0))
+#define AXI_DMA_IN_RESET_AVAIL_CH1_M  (AXI_DMA_IN_RESET_AVAIL_CH1_V << AXI_DMA_IN_RESET_AVAIL_CH1_S)
+#define AXI_DMA_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define AXI_DMA_IN_RESET_AVAIL_CH1_S  0
+
+/** AXI_DMA_IN_RESET_AVAIL_CH2_REG register
+ *  The rx channel 2 reset valid_flag register.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x294)
+/** AXI_DMA_IN_RESET_AVAIL_CH2 : RO; bitpos: [0]; default: 1;
+ *  rx chan0 reset valid reg.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH2    (BIT(0))
+#define AXI_DMA_IN_RESET_AVAIL_CH2_M  (AXI_DMA_IN_RESET_AVAIL_CH2_V << AXI_DMA_IN_RESET_AVAIL_CH2_S)
+#define AXI_DMA_IN_RESET_AVAIL_CH2_V  0x00000001U
+#define AXI_DMA_IN_RESET_AVAIL_CH2_S  0
+
+/** AXI_DMA_OUT_RESET_AVAIL_CH0_REG register
+ *  The tx channel 0 reset valid_flag register.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x298)
+/** AXI_DMA_OUT_RESET_AVAIL_CH0 : RO; bitpos: [0]; default: 1;
+ *  tx chan0 reset valid reg.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH0    (BIT(0))
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_M  (AXI_DMA_OUT_RESET_AVAIL_CH0_V << AXI_DMA_OUT_RESET_AVAIL_CH0_S)
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_S  0
+
+/** AXI_DMA_OUT_RESET_AVAIL_CH1_REG register
+ *  The tx channel 1 reset valid_flag register.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_REG (DR_REG_AXI_DMA_BASE + 0x29c)
+/** AXI_DMA_OUT_RESET_AVAIL_CH1 : RO; bitpos: [0]; default: 1;
+ *  tx chan0 reset valid reg.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH1    (BIT(0))
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_M  (AXI_DMA_OUT_RESET_AVAIL_CH1_V << AXI_DMA_OUT_RESET_AVAIL_CH1_S)
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_S  0
+
+/** AXI_DMA_OUT_RESET_AVAIL_CH2_REG register
+ *  The tx channel 2 reset valid_flag register.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x2a0)
+/** AXI_DMA_OUT_RESET_AVAIL_CH2 : RO; bitpos: [0]; default: 1;
+ *  tx chan0 reset valid reg.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH2    (BIT(0))
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_M  (AXI_DMA_OUT_RESET_AVAIL_CH2_V << AXI_DMA_OUT_RESET_AVAIL_CH2_S)
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_S  0
+
+/** AXI_DMA_MISC_CONF_REG register
+ *  MISC register
+ */
+#define AXI_DMA_MISC_CONF_REG (DR_REG_AXI_DMA_BASE + 0x2a8)
+/** AXI_DMA_AXIM_RST_WR_INTER : R/W; bitpos: [0]; default: 0;
+ *  Set this bit then clear this bit to reset the internal axi_wr FSM.
+ */
+#define AXI_DMA_AXIM_RST_WR_INTER    (BIT(0))
+#define AXI_DMA_AXIM_RST_WR_INTER_M  (AXI_DMA_AXIM_RST_WR_INTER_V << AXI_DMA_AXIM_RST_WR_INTER_S)
+#define AXI_DMA_AXIM_RST_WR_INTER_V  0x00000001U
+#define AXI_DMA_AXIM_RST_WR_INTER_S  0
+/** AXI_DMA_AXIM_RST_RD_INTER : R/W; bitpos: [1]; default: 0;
+ *  Set this bit then clear this bit to reset the internal axi_rd FSM.
+ */
+#define AXI_DMA_AXIM_RST_RD_INTER    (BIT(1))
+#define AXI_DMA_AXIM_RST_RD_INTER_M  (AXI_DMA_AXIM_RST_RD_INTER_V << AXI_DMA_AXIM_RST_RD_INTER_S)
+#define AXI_DMA_AXIM_RST_RD_INTER_V  0x00000001U
+#define AXI_DMA_AXIM_RST_RD_INTER_S  1
+/** AXI_DMA_ARB_PRI_DIS : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to disable priority arbitration function.
+ */
+#define AXI_DMA_ARB_PRI_DIS    (BIT(3))
+#define AXI_DMA_ARB_PRI_DIS_M  (AXI_DMA_ARB_PRI_DIS_V << AXI_DMA_ARB_PRI_DIS_S)
+#define AXI_DMA_ARB_PRI_DIS_V  0x00000001U
+#define AXI_DMA_ARB_PRI_DIS_S  3
+/** AXI_DMA_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define AXI_DMA_CLK_EN    (BIT(4))
+#define AXI_DMA_CLK_EN_M  (AXI_DMA_CLK_EN_V << AXI_DMA_CLK_EN_S)
+#define AXI_DMA_CLK_EN_V  0x00000001U
+#define AXI_DMA_CLK_EN_S  4
+
+/** AXI_DMA_RDN_RESULT_REG register
+ *  reserved
+ */
+#define AXI_DMA_RDN_RESULT_REG (DR_REG_AXI_DMA_BASE + 0x2ac)
+/** AXI_DMA_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RDN_ENA    (BIT(0))
+#define AXI_DMA_RDN_ENA_M  (AXI_DMA_RDN_ENA_V << AXI_DMA_RDN_ENA_S)
+#define AXI_DMA_RDN_ENA_V  0x00000001U
+#define AXI_DMA_RDN_ENA_S  0
+/** AXI_DMA_RDN_RESULT : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RDN_RESULT    (BIT(1))
+#define AXI_DMA_RDN_RESULT_M  (AXI_DMA_RDN_RESULT_V << AXI_DMA_RDN_RESULT_S)
+#define AXI_DMA_RDN_RESULT_V  0x00000001U
+#define AXI_DMA_RDN_RESULT_S  1
+
+/** AXI_DMA_RDN_ECO_HIGH_REG register
+ *  reserved
+ */
+#define AXI_DMA_RDN_ECO_HIGH_REG (DR_REG_AXI_DMA_BASE + 0x2b0)
+/** AXI_DMA_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_RDN_ECO_HIGH    0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_HIGH_M  (AXI_DMA_RDN_ECO_HIGH_V << AXI_DMA_RDN_ECO_HIGH_S)
+#define AXI_DMA_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_HIGH_S  0
+
+/** AXI_DMA_RDN_ECO_LOW_REG register
+ *  reserved
+ */
+#define AXI_DMA_RDN_ECO_LOW_REG (DR_REG_AXI_DMA_BASE + 0x2b4)
+/** AXI_DMA_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_RDN_ECO_LOW    0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_LOW_M  (AXI_DMA_RDN_ECO_LOW_V << AXI_DMA_RDN_ECO_LOW_S)
+#define AXI_DMA_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_LOW_S  0
+
+/** AXI_DMA_WRESP_CNT_REG register
+ *  AXI wr response cnt register.
+ */
+#define AXI_DMA_WRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2b8)
+/** AXI_DMA_WRESP_CNT : RO; bitpos: [3:0]; default: 0;
+ *  axi wr response cnt reg.
+ */
+#define AXI_DMA_WRESP_CNT    0x0000000FU
+#define AXI_DMA_WRESP_CNT_M  (AXI_DMA_WRESP_CNT_V << AXI_DMA_WRESP_CNT_S)
+#define AXI_DMA_WRESP_CNT_V  0x0000000FU
+#define AXI_DMA_WRESP_CNT_S  0
+
+/** AXI_DMA_RRESP_CNT_REG register
+ *  AXI wr response cnt register.
+ */
+#define AXI_DMA_RRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2bc)
+/** AXI_DMA_RRESP_CNT : RO; bitpos: [3:0]; default: 0;
+ *  axi rd response cnt reg.
+ */
+#define AXI_DMA_RRESP_CNT    0x0000000FU
+#define AXI_DMA_RRESP_CNT_M  (AXI_DMA_RRESP_CNT_V << AXI_DMA_RRESP_CNT_S)
+#define AXI_DMA_RRESP_CNT_V  0x0000000FU
+#define AXI_DMA_RRESP_CNT_S  0
+
+/** AXI_DMA_INFIFO_STATUS1_CH0_REG register
+ *  Receive FIFO status of Rx channel 0
+ */
+#define AXI_DMA_INFIFO_STATUS1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x2c0)
+/** AXI_DMA_L1INFIFO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L1INFIFO_CNT_CH0    0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH0_M  (AXI_DMA_L1INFIFO_CNT_CH0_V << AXI_DMA_L1INFIFO_CNT_CH0_S)
+#define AXI_DMA_L1INFIFO_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH0_S  0
+/** AXI_DMA_L2INFIFO_CNT_CH0 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L2INFIFO_CNT_CH0    0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH0_M  (AXI_DMA_L2INFIFO_CNT_CH0_V << AXI_DMA_L2INFIFO_CNT_CH0_S)
+#define AXI_DMA_L2INFIFO_CNT_CH0_V  0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH0_S  6
+
+/** AXI_DMA_INFIFO_STATUS1_CH1_REG register
+ *  Receive FIFO status of Rx channel 1
+ */
+#define AXI_DMA_INFIFO_STATUS1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x2c4)
+/** AXI_DMA_L1INFIFO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L1INFIFO_CNT_CH1    0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH1_M  (AXI_DMA_L1INFIFO_CNT_CH1_V << AXI_DMA_L1INFIFO_CNT_CH1_S)
+#define AXI_DMA_L1INFIFO_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH1_S  0
+/** AXI_DMA_L2INFIFO_CNT_CH1 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L2INFIFO_CNT_CH1    0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH1_M  (AXI_DMA_L2INFIFO_CNT_CH1_V << AXI_DMA_L2INFIFO_CNT_CH1_S)
+#define AXI_DMA_L2INFIFO_CNT_CH1_V  0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH1_S  6
+
+/** AXI_DMA_INFIFO_STATUS1_CH2_REG register
+ *  Receive FIFO status of Rx channel 2
+ */
+#define AXI_DMA_INFIFO_STATUS1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x2c8)
+/** AXI_DMA_L1INFIFO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L1INFIFO_CNT_CH2    0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH2_M  (AXI_DMA_L1INFIFO_CNT_CH2_V << AXI_DMA_L1INFIFO_CNT_CH2_S)
+#define AXI_DMA_L1INFIFO_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH2_S  0
+/** AXI_DMA_L2INFIFO_CNT_CH2 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L2INFIFO_CNT_CH2    0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH2_M  (AXI_DMA_L2INFIFO_CNT_CH2_V << AXI_DMA_L2INFIFO_CNT_CH2_S)
+#define AXI_DMA_L2INFIFO_CNT_CH2_V  0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH2_S  6
+
+/** AXI_DMA_OUTFIFO_STATUS1_CH0_REG register
+ *  Receive FIFO status of Tx channel 0
+ */
+#define AXI_DMA_OUTFIFO_STATUS1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x2cc)
+/** AXI_DMA_L1OUTFIFO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L1OUTFIFO_CNT_CH0    0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH0_M  (AXI_DMA_L1OUTFIFO_CNT_CH0_V << AXI_DMA_L1OUTFIFO_CNT_CH0_S)
+#define AXI_DMA_L1OUTFIFO_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH0_S  0
+/** AXI_DMA_L2OUTFIFO_CNT_CH0 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L2OUTFIFO_CNT_CH0    0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH0_M  (AXI_DMA_L2OUTFIFO_CNT_CH0_V << AXI_DMA_L2OUTFIFO_CNT_CH0_S)
+#define AXI_DMA_L2OUTFIFO_CNT_CH0_V  0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH0_S  6
+
+/** AXI_DMA_OUTFIFO_STATUS1_CH1_REG register
+ *  Receive FIFO status of Tx channel 1
+ */
+#define AXI_DMA_OUTFIFO_STATUS1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x2d0)
+/** AXI_DMA_L1OUTFIFO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L1OUTFIFO_CNT_CH1    0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH1_M  (AXI_DMA_L1OUTFIFO_CNT_CH1_V << AXI_DMA_L1OUTFIFO_CNT_CH1_S)
+#define AXI_DMA_L1OUTFIFO_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH1_S  0
+/** AXI_DMA_L2OUTFIFO_CNT_CH1 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L2OUTFIFO_CNT_CH1    0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH1_M  (AXI_DMA_L2OUTFIFO_CNT_CH1_V << AXI_DMA_L2OUTFIFO_CNT_CH1_S)
+#define AXI_DMA_L2OUTFIFO_CNT_CH1_V  0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH1_S  6
+
+/** AXI_DMA_OUTFIFO_STATUS1_CH2_REG register
+ *  Receive FIFO status of Tx channel 2
+ */
+#define AXI_DMA_OUTFIFO_STATUS1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x2d4)
+/** AXI_DMA_L1OUTFIFO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L1OUTFIFO_CNT_CH2    0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH2_M  (AXI_DMA_L1OUTFIFO_CNT_CH2_V << AXI_DMA_L1OUTFIFO_CNT_CH2_S)
+#define AXI_DMA_L1OUTFIFO_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH2_S  0
+/** AXI_DMA_L2OUTFIFO_CNT_CH2 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L2OUTFIFO_CNT_CH2    0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH2_M  (AXI_DMA_L2OUTFIFO_CNT_CH2_V << AXI_DMA_L2OUTFIFO_CNT_CH2_S)
+#define AXI_DMA_L2OUTFIFO_CNT_CH2_V  0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH2_S  6
+
+/** AXI_DMA_DATE_REG register
+ *  Version control register
+ */
+#define AXI_DMA_DATE_REG (DR_REG_AXI_DMA_BASE + 0x2d8)
+/** AXI_DMA_DATE : R/W; bitpos: [31:0]; default: 36712768;
+ *  register version.
+ */
+#define AXI_DMA_DATE    0xFFFFFFFFU
+#define AXI_DMA_DATE_M  (AXI_DMA_DATE_V << AXI_DMA_DATE_S)
+#define AXI_DMA_DATE_V  0xFFFFFFFFU
+#define AXI_DMA_DATE_S  0
+
+/** AXI_DMA_LINK_SWITCH_STATE_REG register
+ *  Version control register
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_REG (DR_REG_AXI_DMA_BASE + 0x2dc)
+/** AXI_DMA_LINK_SWITCH_STATE_CH0 : R/W; bitpos: [0]; default: 0;
+ *  The register that confirm ch dscr switch success
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_CH0    (BIT(0))
+#define AXI_DMA_LINK_SWITCH_STATE_CH0_M  (AXI_DMA_LINK_SWITCH_STATE_CH0_V << AXI_DMA_LINK_SWITCH_STATE_CH0_S)
+#define AXI_DMA_LINK_SWITCH_STATE_CH0_V  0x00000001U
+#define AXI_DMA_LINK_SWITCH_STATE_CH0_S  0
+/** AXI_DMA_LINK_SWITCH_STATE_CH1 : R/W; bitpos: [1]; default: 0;
+ *  The register that confirm ch dscr switch success
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_CH1    (BIT(1))
+#define AXI_DMA_LINK_SWITCH_STATE_CH1_M  (AXI_DMA_LINK_SWITCH_STATE_CH1_V << AXI_DMA_LINK_SWITCH_STATE_CH1_S)
+#define AXI_DMA_LINK_SWITCH_STATE_CH1_V  0x00000001U
+#define AXI_DMA_LINK_SWITCH_STATE_CH1_S  1
+/** AXI_DMA_LINK_SWITCH_STATE_CH2 : R/W; bitpos: [2]; default: 0;
+ *  The register that confirm ch dscr switch success
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_CH2    (BIT(2))
+#define AXI_DMA_LINK_SWITCH_STATE_CH2_M  (AXI_DMA_LINK_SWITCH_STATE_CH2_V << AXI_DMA_LINK_SWITCH_STATE_CH2_S)
+#define AXI_DMA_LINK_SWITCH_STATE_CH2_V  0x00000001U
+#define AXI_DMA_LINK_SWITCH_STATE_CH2_S  2
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/axi_dma_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/axi_dma_struct.h
new file mode 100644
index 0000000000..fed3f3ed39
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/axi_dma_struct.h
@@ -0,0 +1,1799 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: in */
+/** Type of in_int_raw_chn register
+ *  Raw status interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw: 1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+         *  turns to high level when the last data pointed by one inlink descriptor has been
+         *  received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw: 1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when data error is detected only in the
+         *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+         *  interrupt is reserved.
+         */
+        uint32_t in_err_eof_chn_int_raw: 1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+         *  including owner error and the second and third word error of inlink descriptor for
+         *  Rx channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw: 1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+         *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+         */
+        uint32_t in_dscr_empty_chn_int_raw: 1;
+        /** infifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l1_ovf_chn_int_raw: 1;
+        /** infifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l1_udf_chn_int_raw: 1;
+        /** infifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l2_ovf_chn_int_raw: 1;
+        /** infifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l2_udf_chn_int_raw: 1;
+        /** infifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l3_ovf_chn_int_raw: 1;
+        /** infifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l3_udf_chn_int_raw: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_raw_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st: 1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st: 1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st: 1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st: 1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st: 1;
+        /** infifo_l1_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_st: 1;
+        /** infifo_l1_udf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_st: 1;
+        /** infifo_l2_ovf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_st: 1;
+        /** infifo_l2_udf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_st: 1;
+        /** infifo_l3_ovf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_st: 1;
+        /** infifo_l3_udf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_st: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_st_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena: 1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena: 1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena: 1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena: 1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena: 1;
+        /** infifo_l1_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_ena: 1;
+        /** infifo_l1_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_ena: 1;
+        /** infifo_l2_ovf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_ena: 1;
+        /** infifo_l2_udf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_ena: 1;
+        /** infifo_l3_ovf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_ena: 1;
+        /** infifo_l3_udf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_ena: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_ena_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr: 1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr: 1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr: 1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr: 1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr: 1;
+        /** infifo_l1_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_clr: 1;
+        /** infifo_l1_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_clr: 1;
+        /** infifo_l2_ovf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_clr: 1;
+        /** infifo_l2_udf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_clr: 1;
+        /** infifo_l3_ovf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_clr: 1;
+        /** infifo_l3_udf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_clr: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_clr_chn_reg_t;
+
+/** Type of in_conf0_chn register
+ *  Configure 0 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+         */
+        uint32_t in_rst_chn: 1;
+        /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn: 1;
+        /** mem_trans_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+         *  AXI_DMA.
+         */
+        uint32_t mem_trans_en_chn: 1;
+        /** in_etm_en_chn : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+         *  task.
+         */
+        uint32_t in_etm_en_chn: 1;
+        /** in_burst_size_sel_chn : R/W; bitpos: [6:4]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t in_burst_size_sel_chn: 3;
+        /** in_cmd_disable_chn : R/W; bitpos: [7]; default: 0;
+         *  1:mean disable cmd of this ch0
+         */
+        uint32_t in_cmd_disable_chn: 1;
+        /** in_ecc_aes_en_chn : R/W; bitpos: [8]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t in_ecc_aes_en_chn: 1;
+        /** indscr_burst_en_chn : R/W; bitpos: [9]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t indscr_burst_en_chn: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_in_conf0_chn_reg_t;
+
+/** Type of in_conf1_chn register
+ *  Configure 1 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} axi_dma_in_conf1_chn_reg_t;
+
+/** Type of infifo_status_chn register
+ *  Receive FIFO status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_l3_full_chn : RO; bitpos: [0]; default: 1;
+         *  L3 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_full_chn: 1;
+        /** infifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_empty_chn: 1;
+        /** infifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_l3_cnt_chn: 6;
+        /** infifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_udf_chn: 1;
+        /** infifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_ovf_chn: 1;
+        /** infifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_full_chn: 1;
+        /** infifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_empty_chn: 1;
+        /** infifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_udf_chn: 1;
+        /** infifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_ovf_chn: 1;
+        /** infifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Rx RAM full signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_full_chn: 1;
+        /** infifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Rx RAM empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_empty_chn: 1;
+        /** infifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_udf_chn: 1;
+        /** infifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_ovf_chn: 1;
+        uint32_t reserved_18: 5;
+        /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn: 1;
+        /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn: 1;
+        /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn: 1;
+        /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn: 1;
+        /** in_remain_under_5b_chn : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn: 1;
+        /** in_remain_under_6b_chn : RO; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn: 1;
+        /** in_remain_under_7b_chn : RO; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn: 1;
+        /** in_remain_under_8b_chn : RO; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn: 1;
+        /** in_buf_hungry_chn : RO; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_chn: 1;
+    };
+    uint32_t val;
+} axi_dma_infifo_status_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Pop control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
+         *  This register stores the data popping from AXI_DMA FIFO.
+         */
+        uint32_t infifo_rdata_chn: 12;
+        /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
+         *  Set this bit to pop data from AXI_DMA FIFO.
+         */
+        uint32_t infifo_pop_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} axi_dma_in_pop_chn_reg_t;
+
+/** Type of in_link1_chn register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn: 1;
+        /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn: 1;
+        /** inlink_start_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn: 1;
+        /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn: 1;
+        /** inlink_park_chn : RO; bitpos: [4]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} axi_dma_in_link1_chn_reg_t;
+
+/** Type of in_link2_chn register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 20 least significant bits of the first inlink descriptor's
+         *  address.
+         */
+        uint32_t inlink_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_link2_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Receive status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn: 18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn: 2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} axi_dma_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Inlink descriptor address when EOF occurs of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Inlink descriptor address when errors occur of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data. Only used when peripheral is UHCI0.
+         */
+        uint32_t in_err_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Current inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current inlink descriptor x.
+         */
+        uint32_t inlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  The last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  The second-to-last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf1_chn_reg_t;
+
+/** Type of in_pri_chn register
+ *  Priority register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+         */
+        uint32_t rx_pri_chn: 4;
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Rx channel 0
+         */
+        uint32_t rx_ch_arb_weigh_chn: 4;
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_9: 23;
+    };
+    uint32_t val;
+} axi_dma_in_pri_chn_reg_t;
+
+/** Type of in_peri_sel_chn register
+ *  Peripheral selection of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_in_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} axi_dma_in_peri_sel_chn_reg_t;
+
+/** Type of in_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of rx crc initial value
+         */
+        uint32_t in_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_init_data_chn_reg_t;
+
+/** Type of rx_crc_width_chn register
+ *  This register is used to config rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_width_chn: 2;
+        /** rx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_width_chn_reg_t;
+
+/** Type of in_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of rx crc result
+         */
+        uint32_t in_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_in_crc_clear_chn_reg_t;
+
+/** Type of in_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of rx
+         */
+        uint32_t in_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_final_result_chn_reg_t;
+
+/** Type of rx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable rx ch0 crc 32bit on/off
+         */
+        uint32_t rx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_addr_chn_reg_t;
+
+/** Type of rx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_wr_data_chn: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_addr_chn_reg_t;
+
+/** Group: out */
+/** Type of out_int_raw_chn register
+ *  Raw status interrupt of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel0.
+         */
+        uint32_t out_done_chn_int_raw: 1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel0.
+         */
+        uint32_t out_eof_chn_int_raw: 1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+         *  including owner error and the second and third word error of outlink descriptor for
+         *  Tx channel0.
+         */
+        uint32_t out_dscr_err_chn_int_raw: 1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel0.
+         */
+        uint32_t out_total_eof_chn_int_raw: 1;
+        /** outfifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_raw: 1;
+        /** outfifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l1_udf_chn_int_raw: 1;
+        /** outfifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_raw: 1;
+        /** outfifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l2_udf_chn_int_raw: 1;
+        /** outfifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_raw: 1;
+        /** outfifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l3_udf_chn_int_raw: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_raw_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st: 1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st: 1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st: 1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st: 1;
+        /** outfifo_l1_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_st: 1;
+        /** outfifo_l1_udf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_st: 1;
+        /** outfifo_l2_ovf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_st: 1;
+        /** outfifo_l2_udf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_st: 1;
+        /** outfifo_l3_ovf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_st: 1;
+        /** outfifo_l3_udf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_st: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_st_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena: 1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena: 1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena: 1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena: 1;
+        /** outfifo_l1_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_ena: 1;
+        /** outfifo_l1_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_ena: 1;
+        /** outfifo_l2_ovf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_ena: 1;
+        /** outfifo_l2_udf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_ena: 1;
+        /** outfifo_l3_ovf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_ena: 1;
+        /** outfifo_l3_udf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_ena: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_ena_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr: 1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr: 1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr: 1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr: 1;
+        /** outfifo_l1_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_clr: 1;
+        /** outfifo_l1_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_clr: 1;
+        /** outfifo_l2_ovf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_clr: 1;
+        /** outfifo_l2_udf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_clr: 1;
+        /** outfifo_l3_ovf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_clr: 1;
+        /** outfifo_l3_udf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_clr: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_clr_chn_reg_t;
+
+/** Type of out_conf0_chn register
+ *  Configure 0 register of Tx channelN
+ */
+typedef union {
+    struct {
+        /** out_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_chn: 1;
+        /** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn: 1;
+        /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_chn: 1;
+        /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is
+         *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+         */
+        uint32_t out_eof_mode_chn: 1;
+        /** out_etm_en_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_chn: 1;
+        /** out_burst_size_sel_chn : R/W; bitpos: [7:5]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t out_burst_size_sel_chn: 3;
+        /** out_cmd_disable_chn : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this chn
+         */
+        uint32_t out_cmd_disable_chn: 1;
+        /** out_ecc_aes_en_chn : R/W; bitpos: [9]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t out_ecc_aes_en_chn: 1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_out_conf0_chn_reg_t;
+
+/** Type of out_conf1_chn register
+ *  Configure 1 register of Tx channel0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} axi_dma_out_conf1_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Transmit FIFO status of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outfifo_l3_full_chn : RO; bitpos: [0]; default: 0;
+         *  L3 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_full_chn: 1;
+        /** outfifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_empty_chn: 1;
+        /** outfifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+         */
+        uint32_t outfifo_l3_cnt_chn: 6;
+        /** outfifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_udf_chn: 1;
+        /** outfifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_ovf_chn: 1;
+        /** outfifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_full_chn: 1;
+        /** outfifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_empty_chn: 1;
+        /** outfifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_udf_chn: 1;
+        /** outfifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_ovf_chn: 1;
+        /** outfifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Tx RAM full signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_full_chn: 1;
+        /** outfifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Tx RAM empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_empty_chn: 1;
+        /** outfifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_udf_chn: 1;
+        /** outfifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_ovf_chn: 1;
+        uint32_t reserved_18: 5;
+        /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn: 1;
+        /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn: 1;
+        /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn: 1;
+        /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn: 1;
+        /** out_remain_under_5b_chn : RO; bitpos: [27]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn: 1;
+        /** out_remain_under_6b_chn : RO; bitpos: [28]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn: 1;
+        /** out_remain_under_7b_chn : RO; bitpos: [29]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn: 1;
+        /** out_remain_under_8b_chn : RO; bitpos: [30]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn: 1;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Push control register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
+         *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_wdata_chn: 9;
+        /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
+         *  Set this bit to push data into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_push_chn: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_push_chn_reg_t;
+
+/** Type of out_link1_chn register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn: 1;
+        /** outlink_start_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn: 1;
+        /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn: 1;
+        /** outlink_park_chn : RO; bitpos: [3]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} axi_dma_out_link1_chn_reg_t;
+
+/** Type of out_link2_chn register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 32 least significant bits of the first outlink
+         *  descriptor's address.
+         */
+        uint32_t outlink_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_link2_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Transmit status of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn: 18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_chn: 2;
+        /** out_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} axi_dma_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Outlink descriptor address when EOF occurs of Tx channel0
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_eof_bfr_des_addr_chn register
+ *  The last outlink descriptor address when EOF occurs of Tx channel0
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor before the last outlink
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_bfr_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Current outlink descriptor address of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current outlink descriptor y.
+         */
+        uint32_t outlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  The last outlink descriptor address of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  The second-to-last outlink descriptor address of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor x-2.
+         */
+        uint32_t outlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf1_chn_reg_t;
+
+/** Type of out_pri_chn register
+ *  Priority register of Tx channel0.
+ */
+typedef union {
+    struct {
+        /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Tx channel0. The larger of the value the higher of the priority.
+         */
+        uint32_t tx_pri_chn: 4;
+        /** tx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Tx channel0
+         */
+        uint32_t tx_ch_arb_weigh_chn: 4;
+        /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t tx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_9: 23;
+    };
+    uint32_t val;
+} axi_dma_out_pri_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Peripheral selection of Tx channel0
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_out_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} axi_dma_out_peri_sel_chn_reg_t;
+
+/** Type of out_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of tx crc initial value
+         */
+        uint32_t out_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_init_data_chn_reg_t;
+
+/** Type of tx_crc_width_chn register
+ *  This register is used to config tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_width_chn: 2;
+        /** tx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_width_chn_reg_t;
+
+/** Type of out_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of tx crc result
+         */
+        uint32_t out_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_out_crc_clear_chn_reg_t;
+
+/** Type of out_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of tx
+         */
+        uint32_t out_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_final_result_chn_reg_t;
+
+/** Type of tx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable tx ch0 crc 32bit on/off
+         */
+        uint32_t tx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_addr_chn_reg_t;
+
+/** Type of tx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_wr_data_chn: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_addr_chn_reg_t;
+
+/** Group: Configuration Registers */
+/** Type of arb_timeout register
+ *  This retister is used to config arbiter time slice
+ */
+typedef union {
+    struct {
+        /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to config tx arbiter time out value
+         */
+        uint32_t arb_timeout_tx: 16;
+        /** arb_timeout_rx : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to config rx arbiter time out value
+         */
+        uint32_t arb_timeout_rx: 16;
+    };
+    uint32_t val;
+} axi_dma_arb_timeout_reg_t;
+
+/** Type of weight_en register
+ *  This register is used to config arbiter weight function to on or off
+ */
+typedef union {
+    struct {
+        /** weight_en_tx : R/W; bitpos: [0]; default: 0;
+         *  This register is used to config tx arbiter weight function  off/on
+         */
+        uint32_t weight_en_tx: 1;
+        /** weight_en_rx : R/W; bitpos: [1]; default: 0;
+         *  This register is used to config rx arbiter weight function  off/on
+         */
+        uint32_t weight_en_rx: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} axi_dma_weight_en_reg_t;
+
+/** Type of in_mem_conf register
+ *  Mem power configure register of Rx channel
+ */
+typedef union {
+    struct {
+        /** in_mem_clk_force_en : R/W; bitpos: [0]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t in_mem_clk_force_en: 1;
+        /** in_mem_force_pu : R/W; bitpos: [1]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t in_mem_force_pu: 1;
+        /** in_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t in_mem_force_pd: 1;
+        /** out_mem_clk_force_en : R/W; bitpos: [3]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t out_mem_clk_force_en: 1;
+        /** out_mem_force_pu : R/W; bitpos: [4]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t out_mem_force_pu: 1;
+        /** out_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t out_mem_force_pd: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} axi_dma_in_mem_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_end_addr_reg_t;
+
+/** Type of in_reset_avail_chn register
+ *  The rx channel 0 reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** in_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  rx chan0 reset valid reg.
+         */
+        uint32_t in_reset_avail_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_in_reset_avail_chn_reg_t;
+
+/** Type of out_reset_avail_chn register
+ *  The tx channel 0 reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** out_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  tx chan0 reset valid reg.
+         */
+        uint32_t out_reset_avail_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_out_reset_avail_chn_reg_t;
+
+/** Type of misc_conf register
+ *  MISC register
+ */
+typedef union {
+    struct {
+        /** axim_rst_wr_inter : R/W; bitpos: [0]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_wr FSM.
+         */
+        uint32_t axim_rst_wr_inter: 1;
+        /** axim_rst_rd_inter : R/W; bitpos: [1]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_rd FSM.
+         */
+        uint32_t axim_rst_rd_inter: 1;
+        uint32_t reserved_2: 1;
+        /** arb_pri_dis : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to disable priority arbitration function.
+         */
+        uint32_t arb_pri_dis: 1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} axi_dma_misc_conf_reg_t;
+
+/** Group: Debug Registers */
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena: 1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} axi_dma_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high: 32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low: 32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_low_reg_t;
+
+/** Group: Status Registers */
+/** Type of wresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** wresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi wr response cnt reg.
+         */
+        uint32_t wresp_cnt: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} axi_dma_wresp_cnt_reg_t;
+
+/** Type of rresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** rresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi rd response cnt reg.
+         */
+        uint32_t rresp_cnt: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} axi_dma_rresp_cnt_reg_t;
+
+/** Type of infifo_status1_chn register
+ *  Receive FIFO status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** l1infifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l1infifo_cnt_chn: 6;
+        /** l2infifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l2infifo_cnt_chn: 4;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_infifo_status1_chn_reg_t;
+
+/** Type of outfifo_status1_chn register
+ *  Receive FIFO status of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** l1outfifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l1outfifo_cnt_chn: 6;
+        /** l2outfifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l2outfifo_cnt_chn: 4;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status1_chn_reg_t;
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36712768;
+         *  register version.
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} axi_dma_date_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_int_raw_chn_reg_t raw;
+    volatile axi_dma_in_int_st_chn_reg_t st;
+    volatile axi_dma_in_int_ena_chn_reg_t ena;
+    volatile axi_dma_in_int_clr_chn_reg_t clr;
+} axi_dma_in_int_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_conf0_chn_reg_t in_conf0;
+    volatile axi_dma_in_conf1_chn_reg_t in_conf1;
+    volatile axi_dma_infifo_status_chn_reg_t infifo_status;
+    volatile axi_dma_in_pop_chn_reg_t in_pop;
+    volatile axi_dma_in_link1_chn_reg_t in_link1;
+    volatile axi_dma_in_link2_chn_reg_t in_link2;
+    volatile axi_dma_in_state_chn_reg_t in_state;
+    volatile axi_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
+    volatile axi_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
+    volatile axi_dma_in_dscr_chn_reg_t in_dscr;
+    volatile axi_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
+    volatile axi_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
+    volatile axi_dma_in_pri_chn_reg_t in_pri;
+    volatile axi_dma_in_peri_sel_chn_reg_t in_peri_sel;
+} axi_dma_in_conf_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_crc_init_data_chn_reg_t in_crc_init_data;
+    volatile axi_dma_rx_crc_width_chn_reg_t rx_crc_width;
+    volatile axi_dma_in_crc_clear_chn_reg_t in_crc_clear;
+    volatile axi_dma_in_crc_final_result_chn_reg_t in_crc_final_result;
+    volatile axi_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data;
+    volatile axi_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr;
+    volatile axi_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data;
+    volatile axi_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr;
+} axi_dma_in_crc_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_int_chn_reg_t intr;
+    volatile axi_dma_in_conf_chn_reg_t conf;
+    volatile axi_dma_in_crc_chn_reg_t crc;
+} axi_dma_in_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_int_raw_chn_reg_t raw;
+    volatile axi_dma_out_int_st_chn_reg_t st;
+    volatile axi_dma_out_int_ena_chn_reg_t ena;
+    volatile axi_dma_out_int_clr_chn_reg_t clr;
+} axi_dma_out_int_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_conf0_chn_reg_t out_conf0;
+    volatile axi_dma_out_conf1_chn_reg_t out_conf1;
+    volatile axi_dma_outfifo_status_chn_reg_t outfifo_status;
+    volatile axi_dma_out_push_chn_reg_t out_push;
+    volatile axi_dma_out_link1_chn_reg_t out_link1;
+    volatile axi_dma_out_link2_chn_reg_t out_link2;
+    volatile axi_dma_out_state_chn_reg_t out_state;
+    volatile axi_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
+    volatile axi_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
+    volatile axi_dma_out_dscr_chn_reg_t out_dscr;
+    volatile axi_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
+    volatile axi_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
+    volatile axi_dma_out_pri_chn_reg_t out_pri;
+    volatile axi_dma_out_peri_sel_chn_reg_t out_peri_sel;
+} axi_dma_out_conf_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_crc_init_data_chn_reg_t out_crc_init_data;
+    volatile axi_dma_tx_crc_width_chn_reg_t tx_crc_width;
+    volatile axi_dma_out_crc_clear_chn_reg_t out_crc_clear;
+    volatile axi_dma_out_crc_final_result_chn_reg_t out_crc_final_result;
+    volatile axi_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data;
+    volatile axi_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr;
+    volatile axi_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data;
+    volatile axi_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr;
+} axi_dma_out_crc_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_int_chn_reg_t intr;
+    volatile axi_dma_out_conf_chn_reg_t conf;
+    volatile axi_dma_out_crc_chn_reg_t crc;
+} axi_dma_out_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_reg_t in[3];
+    volatile axi_dma_out_reg_t out[3];
+    volatile axi_dma_arb_timeout_reg_t arb_timeout;
+    volatile axi_dma_weight_en_reg_t weight_en;
+    volatile axi_dma_in_mem_conf_reg_t in_mem_conf;
+    volatile axi_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile axi_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile axi_dma_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile axi_dma_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile axi_dma_in_reset_avail_chn_reg_t in_reset_avail_chn[3];
+    volatile axi_dma_out_reset_avail_chn_reg_t out_reset_avail_chn[3];
+    uint32_t reserved_2a4;
+    volatile axi_dma_misc_conf_reg_t misc_conf;
+    volatile axi_dma_rdn_result_reg_t rdn_result;
+    volatile axi_dma_rdn_eco_high_reg_t rdn_eco_high;
+    volatile axi_dma_rdn_eco_low_reg_t rdn_eco_low;
+    volatile axi_dma_wresp_cnt_reg_t wresp_cnt;
+    volatile axi_dma_rresp_cnt_reg_t rresp_cnt;
+    volatile axi_dma_infifo_status1_chn_reg_t infifo_status1_chn[3];
+    volatile axi_dma_outfifo_status1_chn_reg_t outfifo_status1_chn[3];
+    volatile axi_dma_date_reg_t date;
+} axi_dma_dev_t;
+
+extern axi_dma_dev_t AXI_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(axi_dma_dev_t) == 0x2dc, "Invalid size of axi_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/axi_perf_mon_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/axi_perf_mon_reg.h
new file mode 100644
index 0000000000..bc1ebf8a28
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/axi_perf_mon_reg.h
@@ -0,0 +1,1858 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AXI_PERF_MON_CLK_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_CLK_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x0)
+/** AXI_PERF_MON_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  reserved
+ */
+#define AXI_PERF_MON_CLK_EN    (BIT(0))
+#define AXI_PERF_MON_CLK_EN_M  (AXI_PERF_MON_CLK_EN_V << AXI_PERF_MON_CLK_EN_S)
+#define AXI_PERF_MON_CLK_EN_V  0x00000001U
+#define AXI_PERF_MON_CLK_EN_S  0
+
+/** AXI_PERF_MON_AGENT_SELECT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_AGENT_SELECT_REG (DR_REG_AXI_PERF_MON_BASE + 0x4)
+/** AXI_PERF_MON_AGENT_SELECT : R/W; bitpos: [31:0]; default: 0;
+ *  Select Agent in slot to be monitored, 4 bits means one agent number
+ */
+#define AXI_PERF_MON_AGENT_SELECT    0xFFFFFFFFU
+#define AXI_PERF_MON_AGENT_SELECT_M  (AXI_PERF_MON_AGENT_SELECT_V << AXI_PERF_MON_AGENT_SELECT_S)
+#define AXI_PERF_MON_AGENT_SELECT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_AGENT_SELECT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x8)
+/** AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0xc)
+/** AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x10)
+/** AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x14)
+/** AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x18)
+/** AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c)
+/** AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x20)
+/** AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x24)
+/** AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x28)
+/** AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x2c)
+/** AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0x30)
+/** AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0x34)
+/** AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x38)
+/** AXI_PERF_MON_SEL_AG0_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x3c)
+/** AXI_PERF_MON_SEL_AG1_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x40)
+/** AXI_PERF_MON_SEL_AG0_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x44)
+/** AXI_PERF_MON_SEL_AG1_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x48)
+/** AXI_PERF_MON_SEL_AG0_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4c)
+/** AXI_PERF_MON_SEL_AG1_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x50)
+/** AXI_PERF_MON_SEL_AG0_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x54)
+/** AXI_PERF_MON_SEL_AG1_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x58)
+/** AXI_PERF_MON_SEL_AG0_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x5c)
+/** AXI_PERF_MON_SEL_AG1_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x60)
+/** AXI_PERF_MON_SEL_AG0_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x64)
+/** AXI_PERF_MON_SEL_AG1_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x68)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x6c)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x70)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x74)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x78)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x7c)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x80)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x84)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x88)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x8c)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x90)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x94)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x98)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x9c)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0xa0)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0xa4)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0xa8)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0xac)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0xb0)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0xb4)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0xb8)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0xbc)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0xc0)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0xc4)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xc8)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xcc)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0xd0)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0xd4)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0xd8)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0xdc)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0xe0)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0xe4)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0xe8)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0xec)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0xf0)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0xf4)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0xf8)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0xfc)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x100)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x104)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x108)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x10c)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x110)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x114)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x118)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x11c)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x120)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x124)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x128)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x12c)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x130)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x134)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x138)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x13c)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x140)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x144)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x148)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x14c)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x150)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x154)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x158)
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x15c)
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x160)
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x164)
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG_RD_ADDR_REGION_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_RD_ADDR_REGION_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x168)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL : R/W; bitpos: [5:3]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_S  3
+
+/** AXI_PERF_MON_SEL_AG_WR_ADDR_REGION_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_WR_ADDR_REGION_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x16c)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL : R/W; bitpos: [5:3]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_S  3
+
+/** AXI_PERF_MON_SEL_AG_ADDR_FILTER_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_ADDR_FILTER_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x170)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN : R/W; bitpos: [1]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_S  1
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN : R/W; bitpos: [2]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN : R/W; bitpos: [3]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_S  3
+
+/** AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x174)
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN : WT; bitpos: [0]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_S  0
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN : WT; bitpos: [1]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_S  1
+
+/** AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_CLR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_CLR_REG (DR_REG_AXI_PERF_MON_BASE + 0x178)
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR : WT; bitpos: [0]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_S  0
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR : WT; bitpos: [1]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_S  1
+
+/** AXI_PERF_MON_SEL_AG_INS_BANDW_TEST_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INS_BANDW_TEST_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x17c)
+/** AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN : R/W; bitpos: [1]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_S  1
+/** AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN : R/W; bitpos: [2]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN : R/W; bitpos: [3]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_S  3
+
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x180)
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x184)
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG0_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x188)
+/** AXI_PERF_MON_SEL_AG0_RD_ID_MASK : R/W; bitpos: [7:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG0_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG0_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_ID_MASK : R/W; bitpos: [15:8]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG0_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG0_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK_S  8
+
+/** AXI_PERF_MON_SEL_AG1_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x18c)
+/** AXI_PERF_MON_SEL_AG1_RD_ID_MASK : R/W; bitpos: [7:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG1_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG1_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_ID_MASK : R/W; bitpos: [15:8]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG1_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG1_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK_S  8
+
+/** AXI_PERF_MON_SEL_AG0_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x190)
+/** AXI_PERF_MON_SEL_AG0_RD_ID_FILTER : R/W; bitpos: [7:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_ID_FILTER : R/W; bitpos: [15:8]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_S  8
+
+/** AXI_PERF_MON_SEL_AG1_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x194)
+/** AXI_PERF_MON_SEL_AG1_RD_ID_FILTER : R/W; bitpos: [7:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_ID_FILTER : R/W; bitpos: [15:8]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_S  8
+
+/** AXI_PERF_MON_SEL_AG_BANDW_TEST_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_BANDW_TEST_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x198)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN : R/W; bitpos: [1]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_S  1
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN : R/W; bitpos: [3]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_S  3
+
+/** AXI_PERF_MON_SEL_AG_BANDW_TEST_STOP_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_BANDW_TEST_STOP_REG (DR_REG_AXI_PERF_MON_BASE + 0x19c)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP : R/W; bitpos: [1]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP    (BIT(1))
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_S  1
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP    (BIT(2))
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP : R/W; bitpos: [3]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_S  3
+
+/** AXI_PERF_MON_SEL_AG0_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x1a0)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG1_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x1a4)
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x1a8)
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x1ac)
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x1b0)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x1b4)
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x1b8)
+/** AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x1bc)
+/** AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG_INT_RAW_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_RAW_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c0)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [0];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [1];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  1
+
+/** AXI_PERF_MON_SEL_AG_INT_ST_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_ST_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c4)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_S  1
+
+/** AXI_PERF_MON_SEL_AG_INT_ENA_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_ENA_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c8)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  1
+
+/** AXI_PERF_MON_SEL_AG_INT_CLR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_CLR_REG (DR_REG_AXI_PERF_MON_BASE + 0x1cc)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/axi_perf_mon_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/axi_perf_mon_struct.h
new file mode 100644
index 0000000000..eceee2b302
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/axi_perf_mon_struct.h
@@ -0,0 +1,1995 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of clk_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  reserved
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_perf_mon_clk_en_reg_t;
+
+/** Type of sel_ag0_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range0_cnt_high:16;
+        /** sel_ag0_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range0_reg_t;
+
+/** Type of sel_ag1_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range0_cnt_high:16;
+        /** sel_ag1_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range0_reg_t;
+
+/** Type of sel_ag0_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range1_cnt_high:16;
+        /** sel_ag0_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range1_reg_t;
+
+/** Type of sel_ag1_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range1_cnt_high:16;
+        /** sel_ag1_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range1_reg_t;
+
+/** Type of sel_ag0_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range2_cnt_high:16;
+        /** sel_ag0_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range2_reg_t;
+
+/** Type of sel_ag1_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range2_cnt_high:16;
+        /** sel_ag1_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range2_reg_t;
+
+/** Type of sel_ag0_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range3_cnt_high:16;
+        /** sel_ag0_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range3_reg_t;
+
+/** Type of sel_ag1_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range3_cnt_high:16;
+        /** sel_ag1_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range3_reg_t;
+
+/** Type of sel_ag0_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range4_cnt_high:16;
+        /** sel_ag0_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range4_reg_t;
+
+/** Type of sel_ag1_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range4_cnt_high:16;
+        /** sel_ag1_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range4_reg_t;
+
+/** Type of sel_ag0_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range5_cnt_high:16;
+        /** sel_ag0_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range5_reg_t;
+
+/** Type of sel_ag1_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range5_cnt_high:16;
+        /** sel_ag1_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range5_reg_t;
+
+/** Type of sel_ag0_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag1_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag0_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag1_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag0_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag1_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag0_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag1_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag0_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag1_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag0_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag1_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag0_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag1_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag0_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag1_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag0_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag1_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag0_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag1_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag0_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag1_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag0_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag1_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag0_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag0_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_select1_reg_t;
+
+/** Type of sel_ag1_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag1_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_select1_reg_t;
+
+/** Type of sel_ag0_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag0_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_select2_reg_t;
+
+/** Type of sel_ag1_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag1_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_select2_reg_t;
+
+/** Type of sel_ag_rd_addr_region_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_region_sel : R/W; bitpos: [2:0]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag0_rd_addr_region_sel:3;
+        /** sel_ag1_rd_addr_region_sel : R/W; bitpos: [5:3]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag1_rd_addr_region_sel:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_rd_addr_region_sel_reg_t;
+
+/** Type of sel_ag_wr_addr_region_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_region_sel : R/W; bitpos: [2:0]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag0_wr_addr_region_sel:3;
+        /** sel_ag1_wr_addr_region_sel : R/W; bitpos: [5:3]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag1_wr_addr_region_sel:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_wr_addr_region_sel_reg_t;
+
+/** Type of sel_ag_addr_filter_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter_en : R/W; bitpos: [0]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag0_rd_addr_filter_en:1;
+        /** sel_ag1_rd_addr_filter_en : R/W; bitpos: [1]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag1_rd_addr_filter_en:1;
+        /** sel_ag0_wr_addr_filter_en : R/W; bitpos: [2]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag0_wr_addr_filter_en:1;
+        /** sel_ag1_wr_addr_filter_en : R/W; bitpos: [3]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag1_wr_addr_filter_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_addr_filter_en_reg_t;
+
+/** Type of sel_ag_sw_record_stop_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_sw_record_stop_en : WT; bitpos: [0]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag0_sw_record_stop_en:1;
+        /** sel_ag1_sw_record_stop_en : WT; bitpos: [1]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag1_sw_record_stop_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_sw_record_stop_en_reg_t;
+
+/** Type of sel_ag_sw_record_stop_clr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_sw_record_stop_clr : WT; bitpos: [0]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag0_sw_record_stop_clr:1;
+        /** sel_ag1_sw_record_stop_clr : WT; bitpos: [1]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag1_sw_record_stop_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_sw_record_stop_clr_reg_t;
+
+/** Type of sel_ag_ins_bandw_test_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_ins_bandw_test_en : R/W; bitpos: [0]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_rd_ins_bandw_test_en:1;
+        /** sel_ag0_wr_ins_bandw_test_en : R/W; bitpos: [1]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_wr_ins_bandw_test_en:1;
+        /** sel_ag1_rd_ins_bandw_test_en : R/W; bitpos: [2]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_rd_ins_bandw_test_en:1;
+        /** sel_ag1_wr_ins_bandw_test_en : R/W; bitpos: [3]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_wr_ins_bandw_test_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_ins_bandw_test_en_reg_t;
+
+/** Type of sel_ag0_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag0_sw_record_stop_rd_data_limit:16;
+        /** sel_ag0_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag0_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag1_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag1_sw_record_stop_rd_data_limit:16;
+        /** sel_ag1_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag1_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag0_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_id_mask : R/W; bitpos: [7:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag0_rd_id_mask:8;
+        /** sel_ag0_wr_id_mask : R/W; bitpos: [15:8]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag0_wr_id_mask:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_id_mask_reg_t;
+
+/** Type of sel_ag1_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_id_mask : R/W; bitpos: [7:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag1_rd_id_mask:8;
+        /** sel_ag1_wr_id_mask : R/W; bitpos: [15:8]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag1_wr_id_mask:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_id_mask_reg_t;
+
+/** Type of sel_ag0_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_id_filter : R/W; bitpos: [7:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag0_rd_id_filter:8;
+        /** sel_ag0_wr_id_filter : R/W; bitpos: [15:8]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag0_wr_id_filter:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_id_filter_reg_t;
+
+/** Type of sel_ag1_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_id_filter : R/W; bitpos: [7:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag1_rd_id_filter:8;
+        /** sel_ag1_wr_id_filter : R/W; bitpos: [15:8]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag1_wr_id_filter:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_id_filter_reg_t;
+
+/** Type of sel_ag_bandw_test_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_test_en : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag0_rd_bandw_test_en:1;
+        /** sel_ag0_wr_bandw_test_en : R/W; bitpos: [1]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_wr_bandw_test_en:1;
+        /** sel_ag1_rd_bandw_test_en : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag1_rd_bandw_test_en:1;
+        /** sel_ag1_wr_bandw_test_en : R/W; bitpos: [3]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_wr_bandw_test_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_bandw_test_en_reg_t;
+
+/** Type of sel_ag_bandw_test_stop register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_test_stop : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag0_rd_bandw_test_stop:1;
+        /** sel_ag0_wr_bandw_test_stop : R/W; bitpos: [1]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_wr_bandw_test_stop:1;
+        /** sel_ag1_rd_bandw_test_stop : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag1_rd_bandw_test_stop:1;
+        /** sel_ag1_wr_bandw_test_stop : R/W; bitpos: [3]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_wr_bandw_test_stop:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_bandw_test_stop_reg_t;
+
+/** Type of sel_ag0_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag0_rd_bandw_trigger_en_sel:4;
+        /** sel_ag0_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag0_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag0_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag0_wr_bandw_trigger_en_sel:4;
+        /** sel_ag0_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag0_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag1_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag1_rd_bandw_trigger_en_sel:4;
+        /** sel_ag1_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag1_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag1_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag1_wr_bandw_trigger_en_sel:4;
+        /** sel_ag1_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag1_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag0_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag0_rd_ins_bandw_time_thr:16;
+        /** sel_ag0_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag0_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_time_thr_reg_t;
+
+/** Type of sel_ag1_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag1_rd_ins_bandw_time_thr:16;
+        /** sel_ag1_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag1_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_time_thr_reg_t;
+
+
+/** Group: Peripheral Select Registers */
+/** Type of agent_select register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** agent_select : R/W; bitpos: [31:0]; default: 0;
+         *  Select Agent in slot to be monitored, 4 bits means one agent number
+         */
+        uint32_t agent_select:32;
+    };
+    uint32_t val;
+} axi_perf_mon_agent_select_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of sel_ag0_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter0_reg_t;
+
+/** Type of sel_ag1_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter0_reg_t;
+
+/** Type of sel_ag0_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter1_reg_t;
+
+/** Type of sel_ag1_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter1_reg_t;
+
+/** Type of sel_ag0_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter2_reg_t;
+
+/** Type of sel_ag1_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter2_reg_t;
+
+/** Type of sel_ag0_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter3_reg_t;
+
+/** Type of sel_ag1_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter3_reg_t;
+
+/** Type of sel_ag0_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter4_reg_t;
+
+/** Type of sel_ag1_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter4_reg_t;
+
+/** Type of sel_ag0_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter5_reg_t;
+
+/** Type of sel_ag1_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter5_reg_t;
+
+/** Type of sel_ag0_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range0_reg_t;
+
+/** Type of sel_ag1_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range0_reg_t;
+
+/** Type of sel_ag0_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range1_reg_t;
+
+/** Type of sel_ag1_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range1_reg_t;
+
+/** Type of sel_ag0_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range2_reg_t;
+
+/** Type of sel_ag1_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range2_reg_t;
+
+/** Type of sel_ag0_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range3_reg_t;
+
+/** Type of sel_ag1_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range3_reg_t;
+
+/** Type of sel_ag0_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range4_reg_t;
+
+/** Type of sel_ag1_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range4_reg_t;
+
+/** Type of sel_ag0_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range5_reg_t;
+
+/** Type of sel_ag1_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range5_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag0_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag0_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag0_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag0_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag1_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag1_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag1_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag1_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag0_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag0_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag0_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag0_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag1_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag1_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag1_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag1_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of sel_ag_int_raw register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_raw:1;
+        /** sel_ag1_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_raw_reg_t;
+
+/** Type of sel_ag_int_st register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_st:1;
+        /** sel_ag1_record_cnt_under_limit_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_st_reg_t;
+
+/** Type of sel_ag_int_ena register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_ena:1;
+        /** sel_ag1_record_cnt_under_limit_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_ena_reg_t;
+
+/** Type of sel_ag_int_clr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_clr:1;
+        /** sel_ag1_record_cnt_under_limit_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_clr_reg_t;
+
+
+typedef struct {
+    volatile axi_perf_mon_clk_en_reg_t clk_en;
+    volatile axi_perf_mon_agent_select_reg_t agent_select;
+    volatile axi_perf_mon_sel_ag0_counter0_reg_t sel_ag0_counter0;
+    volatile axi_perf_mon_sel_ag1_counter0_reg_t sel_ag1_counter0;
+    volatile axi_perf_mon_sel_ag0_counter1_reg_t sel_ag0_counter1;
+    volatile axi_perf_mon_sel_ag1_counter1_reg_t sel_ag1_counter1;
+    volatile axi_perf_mon_sel_ag0_counter2_reg_t sel_ag0_counter2;
+    volatile axi_perf_mon_sel_ag1_counter2_reg_t sel_ag1_counter2;
+    volatile axi_perf_mon_sel_ag0_counter3_reg_t sel_ag0_counter3;
+    volatile axi_perf_mon_sel_ag1_counter3_reg_t sel_ag1_counter3;
+    volatile axi_perf_mon_sel_ag0_counter4_reg_t sel_ag0_counter4;
+    volatile axi_perf_mon_sel_ag1_counter4_reg_t sel_ag1_counter4;
+    volatile axi_perf_mon_sel_ag0_counter5_reg_t sel_ag0_counter5;
+    volatile axi_perf_mon_sel_ag1_counter5_reg_t sel_ag1_counter5;
+    volatile axi_perf_mon_sel_ag0_range0_reg_t sel_ag0_range0;
+    volatile axi_perf_mon_sel_ag1_range0_reg_t sel_ag1_range0;
+    volatile axi_perf_mon_sel_ag0_range1_reg_t sel_ag0_range1;
+    volatile axi_perf_mon_sel_ag1_range1_reg_t sel_ag1_range1;
+    volatile axi_perf_mon_sel_ag0_range2_reg_t sel_ag0_range2;
+    volatile axi_perf_mon_sel_ag1_range2_reg_t sel_ag1_range2;
+    volatile axi_perf_mon_sel_ag0_range3_reg_t sel_ag0_range3;
+    volatile axi_perf_mon_sel_ag1_range3_reg_t sel_ag1_range3;
+    volatile axi_perf_mon_sel_ag0_range4_reg_t sel_ag0_range4;
+    volatile axi_perf_mon_sel_ag1_range4_reg_t sel_ag1_range4;
+    volatile axi_perf_mon_sel_ag0_range5_reg_t sel_ag0_range5;
+    volatile axi_perf_mon_sel_ag1_range5_reg_t sel_ag1_range5;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record0_reg_t sel_ag0_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record0_reg_t sel_ag1_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record1_reg_t sel_ag0_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record1_reg_t sel_ag1_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record2_reg_t sel_ag0_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record2_reg_t sel_ag1_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record3_reg_t sel_ag0_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record3_reg_t sel_ag1_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record0_reg_t sel_ag0_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record0_reg_t sel_ag1_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record1_reg_t sel_ag0_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record1_reg_t sel_ag1_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record2_reg_t sel_ag0_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record2_reg_t sel_ag1_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record3_reg_t sel_ag0_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record3_reg_t sel_ag1_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data0_reg_t sel_ag0_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data0_reg_t sel_ag1_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data1_reg_t sel_ag0_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data1_reg_t sel_ag1_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data2_reg_t sel_ag0_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data2_reg_t sel_ag1_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data3_reg_t sel_ag0_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data3_reg_t sel_ag1_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag0_metric_range0_reg_t sel_ag0_metric_range0;
+    volatile axi_perf_mon_sel_ag1_metric_range0_reg_t sel_ag1_metric_range0;
+    volatile axi_perf_mon_sel_ag0_metric_range1_reg_t sel_ag0_metric_range1;
+    volatile axi_perf_mon_sel_ag1_metric_range1_reg_t sel_ag1_metric_range1;
+    volatile axi_perf_mon_sel_ag0_metric_range2_reg_t sel_ag0_metric_range2;
+    volatile axi_perf_mon_sel_ag1_metric_range2_reg_t sel_ag1_metric_range2;
+    volatile axi_perf_mon_sel_ag0_metric_range3_reg_t sel_ag0_metric_range3;
+    volatile axi_perf_mon_sel_ag1_metric_range3_reg_t sel_ag1_metric_range3;
+    volatile axi_perf_mon_sel_ag0_metric_range4_reg_t sel_ag0_metric_range4;
+    volatile axi_perf_mon_sel_ag1_metric_range4_reg_t sel_ag1_metric_range4;
+    volatile axi_perf_mon_sel_ag0_metric_range5_reg_t sel_ag0_metric_range5;
+    volatile axi_perf_mon_sel_ag1_metric_range5_reg_t sel_ag1_metric_range5;
+    volatile axi_perf_mon_sel_ag0_rd_addr_mask0_reg_t sel_ag0_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag1_rd_addr_mask0_reg_t sel_ag1_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag0_rd_addr_mask1_reg_t sel_ag0_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag1_rd_addr_mask1_reg_t sel_ag1_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag0_rd_addr_mask2_reg_t sel_ag0_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag1_rd_addr_mask2_reg_t sel_ag1_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag0_wr_addr_mask0_reg_t sel_ag0_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag1_wr_addr_mask0_reg_t sel_ag1_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag0_wr_addr_mask1_reg_t sel_ag0_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag1_wr_addr_mask1_reg_t sel_ag1_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag0_wr_addr_mask2_reg_t sel_ag0_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag1_wr_addr_mask2_reg_t sel_ag1_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag0_rd_addr_filter0_reg_t sel_ag0_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag1_rd_addr_filter0_reg_t sel_ag1_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag0_rd_addr_filter1_reg_t sel_ag0_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag1_rd_addr_filter1_reg_t sel_ag1_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag0_rd_addr_filter2_reg_t sel_ag0_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag1_rd_addr_filter2_reg_t sel_ag1_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag0_wr_addr_filter0_reg_t sel_ag0_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag1_wr_addr_filter0_reg_t sel_ag1_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag0_wr_addr_filter1_reg_t sel_ag0_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag1_wr_addr_filter1_reg_t sel_ag1_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag0_wr_addr_filter2_reg_t sel_ag0_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag1_wr_addr_filter2_reg_t sel_ag1_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag0_metric_select1_reg_t sel_ag0_metric_select1;
+    volatile axi_perf_mon_sel_ag1_metric_select1_reg_t sel_ag1_metric_select1;
+    volatile axi_perf_mon_sel_ag0_metric_select2_reg_t sel_ag0_metric_select2;
+    volatile axi_perf_mon_sel_ag1_metric_select2_reg_t sel_ag1_metric_select2;
+    volatile axi_perf_mon_sel_ag_rd_addr_region_sel_reg_t sel_ag_rd_addr_region_sel;
+    volatile axi_perf_mon_sel_ag_wr_addr_region_sel_reg_t sel_ag_wr_addr_region_sel;
+    volatile axi_perf_mon_sel_ag_addr_filter_en_reg_t sel_ag_addr_filter_en;
+    volatile axi_perf_mon_sel_ag_sw_record_stop_en_reg_t sel_ag_sw_record_stop_en;
+    volatile axi_perf_mon_sel_ag_sw_record_stop_clr_reg_t sel_ag_sw_record_stop_clr;
+    volatile axi_perf_mon_sel_ag_ins_bandw_test_en_reg_t sel_ag_ins_bandw_test_en;
+    volatile axi_perf_mon_sel_ag0_sw_record_stop_data_limit_reg_t sel_ag0_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag1_sw_record_stop_data_limit_reg_t sel_ag1_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag0_id_mask_reg_t sel_ag0_id_mask;
+    volatile axi_perf_mon_sel_ag1_id_mask_reg_t sel_ag1_id_mask;
+    volatile axi_perf_mon_sel_ag0_id_filter_reg_t sel_ag0_id_filter;
+    volatile axi_perf_mon_sel_ag1_id_filter_reg_t sel_ag1_id_filter;
+    volatile axi_perf_mon_sel_ag_bandw_test_en_reg_t sel_ag_bandw_test_en;
+    volatile axi_perf_mon_sel_ag_bandw_test_stop_reg_t sel_ag_bandw_test_stop;
+    volatile axi_perf_mon_sel_ag0_bandw_trigger_in_sel_reg_t sel_ag0_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag1_bandw_trigger_in_sel_reg_t sel_ag1_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag0_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag0_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag1_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag1_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag0_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag0_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag1_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag1_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_time_thr_reg_t sel_ag0_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_time_thr_reg_t sel_ag1_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag_int_raw_reg_t sel_ag_int_raw;
+    volatile axi_perf_mon_sel_ag_int_st_reg_t sel_ag_int_st;
+    volatile axi_perf_mon_sel_ag_int_ena_reg_t sel_ag_int_ena;
+    volatile axi_perf_mon_sel_ag_int_clr_reg_t sel_ag_int_clr;
+} axi_perf_mon_dev_t;
+
+extern axi_perf_mon_dev_t AXI_PERF_MON;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(axi_perf_mon_dev_t) == 0x1d0, "Invalid size of axi_perf_mon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_eco5_struct.h
new file mode 100644
index 0000000000..904de77a89
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_eco5_struct.h
@@ -0,0 +1,437 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of tx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t tx_inst_idx:3;
+        /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t tx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg0_reg_t;
+
+/** Type of tx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst : R/W; bitpos: [31:0]; default: 4;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG
+         */
+        uint32_t tx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg1_reg_t;
+
+/** Type of rx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t rx_inst_idx:3;
+        /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t rx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg0_reg_t;
+
+/** Type of rx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst : R/W; bitpos: [31:0]; default: 12;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG
+         */
+        uint32_t rx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg1_reg_t;
+
+/** Type of tx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_tx_lut_mode
+         */
+        uint32_t tx_lut_idx:11;
+        /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t tx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg0_reg_t;
+
+/** Type of tx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut : R/W; bitpos: [31:0]; default: 20;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
+         */
+        uint32_t tx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg1_reg_t;
+
+/** Type of rx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_rx_lut_mode
+         */
+        uint32_t rx_lut_idx:11;
+        /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t rx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg0_reg_t;
+
+/** Type of rx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut : R/W; bitpos: [31:0]; default: 28;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
+         */
+        uint32_t rx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg1_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of tx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t tx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_tx_tailing_bits_reg_t;
+
+/** Type of rx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t rx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_rx_tailing_bits_reg_t;
+
+/** Type of tx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler tx
+         */
+        uint32_t tx_ena:1;
+        /** tx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler tx core
+         */
+        uint32_t tx_pause:1;
+        /** tx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler tx core
+         */
+        uint32_t tx_halt:1;
+        /** tx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
+         *  counter by write peripheral buffer
+         */
+        uint32_t tx_eof_mode:1;
+        /** tx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t tx_cond_mode:1;
+        /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t tx_fetch_mode:1;
+        /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t tx_halt_mode:1;
+        /** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t tx_rd_dummy:1;
+        /** tx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler tx fifo
+         */
+        uint32_t tx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_tx_ctrl_reg_t;
+
+/** Type of rx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler rx
+         */
+        uint32_t rx_ena:1;
+        /** rx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler rx core
+         */
+        uint32_t rx_pause:1;
+        /** rx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler rx core
+         */
+        uint32_t rx_halt:1;
+        /** rx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
+         *  buffer, 0 counter by write dma fifo
+         */
+        uint32_t rx_eof_mode:1;
+        /** rx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t rx_cond_mode:1;
+        /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t rx_fetch_mode:1;
+        /** rx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t rx_halt_mode:1;
+        /** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t rx_rd_dummy:1;
+        /** rx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler rx fifo
+         */
+        uint32_t rx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_rx_ctrl_reg_t;
+
+/** Type of sys register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** loop_mode : R/W; bitpos: [0]; default: 0;
+         *  write this bit to set the bitscrambler tx loop back to DMA rx
+         */
+        uint32_t loop_mode:1;
+        uint32_t reserved_1:30;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} bitscrambler_sys_reg_t;
+
+
+/** Group: Status registers */
+/** Type of tx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** tx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler tx core in halt mode
+         */
+        uint32_t tx_in_idle:1;
+        /** tx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler tx core in run mode
+         */
+        uint32_t tx_in_run:1;
+        /** tx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler tx core in wait mode to wait write back done
+         */
+        uint32_t tx_in_wait:1;
+        /** tx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler tx core in pause mode
+         */
+        uint32_t tx_in_pause:1;
+        /** tx_fifo_empty : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler tx fifo in empty state
+         */
+        uint32_t tx_fifo_empty:1;
+        uint32_t reserved_5:11;
+        /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler tx core when get EOF
+         */
+        uint32_t tx_eof_get_cnt:14;
+        /** tx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler tx core
+         */
+        uint32_t tx_eof_overload:1;
+        /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_tx_eof_overload and
+         *  reg_bitscrambler_tx_eof_get_cnt registers
+         */
+        uint32_t tx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_tx_state_reg_t;
+
+/** Type of rx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** rx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler rx core in halt mode
+         */
+        uint32_t rx_in_idle:1;
+        /** rx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler rx core in run mode
+         */
+        uint32_t rx_in_run:1;
+        /** rx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler rx core in wait mode to wait write back done
+         */
+        uint32_t rx_in_wait:1;
+        /** rx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler rx core in pause mode
+         */
+        uint32_t rx_in_pause:1;
+        /** rx_fifo_full : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler rx fifo in full state
+         */
+        uint32_t rx_fifo_full:1;
+        uint32_t reserved_5:11;
+        /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler rx core when get EOF
+         */
+        uint32_t rx_eof_get_cnt:14;
+        /** rx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler rx core
+         */
+        uint32_t rx_eof_overload:1;
+        /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_rx_eof_overload and
+         *  reg_bitscrambler_rx_eof_get_cnt registers
+         */
+        uint32_t rx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_rx_state_reg_t;
+
+
+/** Group: Version register */
+/** Type of version register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
+         *  Reserved
+         */
+        uint32_t bitscrambler_ver:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} bitscrambler_version_reg_t;
+
+
+typedef struct {
+    volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
+    volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
+    volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
+    volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
+    volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
+    volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
+    volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
+    volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
+    volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
+    volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
+    volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
+    volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
+    volatile bitscrambler_tx_state_reg_t tx_state;
+    volatile bitscrambler_rx_state_reg_t rx_state;
+    uint32_t reserved_038[48];
+    volatile bitscrambler_sys_reg_t sys;
+    volatile bitscrambler_version_reg_t version;
+} bitscrambler_dev_t;
+
+extern bitscrambler_dev_t BITSCRAMBLER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_reg.h
new file mode 100644
index 0000000000..5bee86a8b5
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_reg.h
@@ -0,0 +1,481 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** BITSCRAMBLER_TX_INST_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
+/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
+ *  write this bits to specify the one of 8 instruction
+ */
+#define BITSCRAMBLER_TX_INST_IDX    0x00000007U
+#define BITSCRAMBLER_TX_INST_IDX_M  (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
+#define BITSCRAMBLER_TX_INST_IDX_V  0x00000007U
+#define BITSCRAMBLER_TX_INST_IDX_S  0
+/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
+ *  write this bits to specify the bit position of 257 bit instruction which in units
+ *  of 32 bits
+ */
+#define BITSCRAMBLER_TX_INST_POS    0x0000000FU
+#define BITSCRAMBLER_TX_INST_POS_M  (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
+#define BITSCRAMBLER_TX_INST_POS_V  0x0000000FU
+#define BITSCRAMBLER_TX_INST_POS_S  3
+
+/** BITSCRAMBLER_TX_INST_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
+/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
+ *  write this bits to update instruction which specified by
+ *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
+ *  BITSCRAMBLER_TX_INST_CFG0_REG
+ */
+#define BITSCRAMBLER_TX_INST    0xFFFFFFFFU
+#define BITSCRAMBLER_TX_INST_M  (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
+#define BITSCRAMBLER_TX_INST_V  0xFFFFFFFFU
+#define BITSCRAMBLER_TX_INST_S  0
+
+/** BITSCRAMBLER_RX_INST_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
+/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
+ *  write this bits to specify the one of 8 instruction
+ */
+#define BITSCRAMBLER_RX_INST_IDX    0x00000007U
+#define BITSCRAMBLER_RX_INST_IDX_M  (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
+#define BITSCRAMBLER_RX_INST_IDX_V  0x00000007U
+#define BITSCRAMBLER_RX_INST_IDX_S  0
+/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
+ *  write this bits to specify the bit position of 257 bit instruction which in units
+ *  of 32 bits
+ */
+#define BITSCRAMBLER_RX_INST_POS    0x0000000FU
+#define BITSCRAMBLER_RX_INST_POS_M  (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
+#define BITSCRAMBLER_RX_INST_POS_V  0x0000000FU
+#define BITSCRAMBLER_RX_INST_POS_S  3
+
+/** BITSCRAMBLER_RX_INST_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
+/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
+ *  write this bits to update instruction which specified by
+ *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
+ *  BITSCRAMBLER_RX_INST_CFG0_REG
+ */
+#define BITSCRAMBLER_RX_INST    0xFFFFFFFFU
+#define BITSCRAMBLER_RX_INST_M  (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
+#define BITSCRAMBLER_RX_INST_V  0xFFFFFFFFU
+#define BITSCRAMBLER_RX_INST_S  0
+
+/** BITSCRAMBLER_TX_LUT_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
+/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
+ *  write this bits to specify the bytes position of LUT RAM based on
+ *  reg_bitscrambler_tx_lut_mode
+ */
+#define BITSCRAMBLER_TX_LUT_IDX    0x000007FFU
+#define BITSCRAMBLER_TX_LUT_IDX_M  (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
+#define BITSCRAMBLER_TX_LUT_IDX_V  0x000007FFU
+#define BITSCRAMBLER_TX_LUT_IDX_S  0
+/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+ *  bytes
+ */
+#define BITSCRAMBLER_TX_LUT_MODE    0x00000003U
+#define BITSCRAMBLER_TX_LUT_MODE_M  (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
+#define BITSCRAMBLER_TX_LUT_MODE_V  0x00000003U
+#define BITSCRAMBLER_TX_LUT_MODE_S  11
+
+/** BITSCRAMBLER_TX_LUT_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
+/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
+ *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
+ *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
+ */
+#define BITSCRAMBLER_TX_LUT    0xFFFFFFFFU
+#define BITSCRAMBLER_TX_LUT_M  (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
+#define BITSCRAMBLER_TX_LUT_V  0xFFFFFFFFU
+#define BITSCRAMBLER_TX_LUT_S  0
+
+/** BITSCRAMBLER_RX_LUT_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
+/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
+ *  write this bits to specify the bytes position of LUT RAM based on
+ *  reg_bitscrambler_rx_lut_mode
+ */
+#define BITSCRAMBLER_RX_LUT_IDX    0x000007FFU
+#define BITSCRAMBLER_RX_LUT_IDX_M  (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
+#define BITSCRAMBLER_RX_LUT_IDX_V  0x000007FFU
+#define BITSCRAMBLER_RX_LUT_IDX_S  0
+/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+ *  bytes
+ */
+#define BITSCRAMBLER_RX_LUT_MODE    0x00000003U
+#define BITSCRAMBLER_RX_LUT_MODE_M  (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
+#define BITSCRAMBLER_RX_LUT_MODE_V  0x00000003U
+#define BITSCRAMBLER_RX_LUT_MODE_S  11
+
+/** BITSCRAMBLER_RX_LUT_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
+/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
+ *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
+ *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
+ */
+#define BITSCRAMBLER_RX_LUT    0xFFFFFFFFU
+#define BITSCRAMBLER_RX_LUT_M  (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
+#define BITSCRAMBLER_RX_LUT_V  0xFFFFFFFFU
+#define BITSCRAMBLER_RX_LUT_S  0
+
+/** BITSCRAMBLER_TX_TAILING_BITS_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
+/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
+ *  write this bits to specify the extra data bit length after getting EOF
+ */
+#define BITSCRAMBLER_TX_TAILING_BITS    0x0000FFFFU
+#define BITSCRAMBLER_TX_TAILING_BITS_M  (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
+#define BITSCRAMBLER_TX_TAILING_BITS_V  0x0000FFFFU
+#define BITSCRAMBLER_TX_TAILING_BITS_S  0
+
+/** BITSCRAMBLER_RX_TAILING_BITS_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
+/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
+ *  write this bits to specify the extra data bit length after getting EOF
+ */
+#define BITSCRAMBLER_RX_TAILING_BITS    0x0000FFFFU
+#define BITSCRAMBLER_RX_TAILING_BITS_M  (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
+#define BITSCRAMBLER_RX_TAILING_BITS_V  0x0000FFFFU
+#define BITSCRAMBLER_RX_TAILING_BITS_S  0
+
+/** BITSCRAMBLER_TX_CTRL_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
+/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
+ *  write this bit to enable the bitscrambler tx
+ */
+#define BITSCRAMBLER_TX_ENA    (BIT(0))
+#define BITSCRAMBLER_TX_ENA_M  (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
+#define BITSCRAMBLER_TX_ENA_V  0x00000001U
+#define BITSCRAMBLER_TX_ENA_S  0
+/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
+ *  write this bit to pause the bitscrambler tx core
+ */
+#define BITSCRAMBLER_TX_PAUSE    (BIT(1))
+#define BITSCRAMBLER_TX_PAUSE_M  (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
+#define BITSCRAMBLER_TX_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_TX_PAUSE_S  1
+/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
+ *  write this bit to halt the bitscrambler tx core
+ */
+#define BITSCRAMBLER_TX_HALT    (BIT(2))
+#define BITSCRAMBLER_TX_HALT_M  (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
+#define BITSCRAMBLER_TX_HALT_V  0x00000001U
+#define BITSCRAMBLER_TX_HALT_S  2
+/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
+ *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+ *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
+ *  counter by write peripheral buffer
+ */
+#define BITSCRAMBLER_TX_EOF_MODE    (BIT(3))
+#define BITSCRAMBLER_TX_EOF_MODE_M  (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
+#define BITSCRAMBLER_TX_EOF_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_EOF_MODE_S  3
+/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
+ *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+ *  core, 0: use the little than operator to get the condition, 1: use not equal
+ *  operator to get the condition
+ */
+#define BITSCRAMBLER_TX_COND_MODE    (BIT(4))
+#define BITSCRAMBLER_TX_COND_MODE_M  (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
+#define BITSCRAMBLER_TX_COND_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_COND_MODE_S  4
+/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
+ *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+ *  by reset, 1: fetch by instructions
+ */
+#define BITSCRAMBLER_TX_FETCH_MODE    (BIT(5))
+#define BITSCRAMBLER_TX_FETCH_MODE_M  (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
+#define BITSCRAMBLER_TX_FETCH_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_FETCH_MODE_S  5
+/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
+ *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
+ *  wait write data back done, , 1: ignore write data back
+ */
+#define BITSCRAMBLER_TX_HALT_MODE    (BIT(6))
+#define BITSCRAMBLER_TX_HALT_MODE_M  (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
+#define BITSCRAMBLER_TX_HALT_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_HALT_MODE_S  6
+/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
+ *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+ *  wait read data, 1: ignore read data
+ */
+#define BITSCRAMBLER_TX_RD_DUMMY    (BIT(7))
+#define BITSCRAMBLER_TX_RD_DUMMY_M  (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
+#define BITSCRAMBLER_TX_RD_DUMMY_V  0x00000001U
+#define BITSCRAMBLER_TX_RD_DUMMY_S  7
+/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
+ *  write this bit to reset the bitscrambler tx fifo
+ */
+#define BITSCRAMBLER_TX_FIFO_RST    (BIT(8))
+#define BITSCRAMBLER_TX_FIFO_RST_M  (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
+#define BITSCRAMBLER_TX_FIFO_RST_V  0x00000001U
+#define BITSCRAMBLER_TX_FIFO_RST_S  8
+
+/** BITSCRAMBLER_RX_CTRL_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
+/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
+ *  write this bit to enable the bitscrambler rx
+ */
+#define BITSCRAMBLER_RX_ENA    (BIT(0))
+#define BITSCRAMBLER_RX_ENA_M  (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
+#define BITSCRAMBLER_RX_ENA_V  0x00000001U
+#define BITSCRAMBLER_RX_ENA_S  0
+/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
+ *  write this bit to pause the bitscrambler rx core
+ */
+#define BITSCRAMBLER_RX_PAUSE    (BIT(1))
+#define BITSCRAMBLER_RX_PAUSE_M  (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
+#define BITSCRAMBLER_RX_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_RX_PAUSE_S  1
+/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
+ *  write this bit to halt the bitscrambler rx core
+ */
+#define BITSCRAMBLER_RX_HALT    (BIT(2))
+#define BITSCRAMBLER_RX_HALT_M  (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
+#define BITSCRAMBLER_RX_HALT_V  0x00000001U
+#define BITSCRAMBLER_RX_HALT_S  2
+/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
+ *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
+ *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
+ *  buffer, 0 counter by write dma fifo
+ */
+#define BITSCRAMBLER_RX_EOF_MODE    (BIT(3))
+#define BITSCRAMBLER_RX_EOF_MODE_M  (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
+#define BITSCRAMBLER_RX_EOF_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_EOF_MODE_S  3
+/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
+ *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
+ *  core, 0: use the little than operator to get the condition, 1: use not equal
+ *  operator to get the condition
+ */
+#define BITSCRAMBLER_RX_COND_MODE    (BIT(4))
+#define BITSCRAMBLER_RX_COND_MODE_M  (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
+#define BITSCRAMBLER_RX_COND_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_COND_MODE_S  4
+/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
+ *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
+ *  by reset, 1: fetch by instructions
+ */
+#define BITSCRAMBLER_RX_FETCH_MODE    (BIT(5))
+#define BITSCRAMBLER_RX_FETCH_MODE_M  (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
+#define BITSCRAMBLER_RX_FETCH_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_FETCH_MODE_S  5
+/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
+ *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
+ *  wait write data back done, , 1: ignore write data back
+ */
+#define BITSCRAMBLER_RX_HALT_MODE    (BIT(6))
+#define BITSCRAMBLER_RX_HALT_MODE_M  (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
+#define BITSCRAMBLER_RX_HALT_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_HALT_MODE_S  6
+/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
+ *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
+ *  wait read data, 1: ignore read data
+ */
+#define BITSCRAMBLER_RX_RD_DUMMY    (BIT(7))
+#define BITSCRAMBLER_RX_RD_DUMMY_M  (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
+#define BITSCRAMBLER_RX_RD_DUMMY_V  0x00000001U
+#define BITSCRAMBLER_RX_RD_DUMMY_S  7
+/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
+ *  write this bit to reset the bitscrambler rx fifo
+ */
+#define BITSCRAMBLER_RX_FIFO_RST    (BIT(8))
+#define BITSCRAMBLER_RX_FIFO_RST_M  (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
+#define BITSCRAMBLER_RX_FIFO_RST_V  0x00000001U
+#define BITSCRAMBLER_RX_FIFO_RST_S  8
+
+/** BITSCRAMBLER_TX_STATE_REG register
+ *  Status registers
+ */
+#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
+/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
+ *  represents the bitscrambler tx core in halt mode
+ */
+#define BITSCRAMBLER_TX_IN_IDLE    (BIT(0))
+#define BITSCRAMBLER_TX_IN_IDLE_M  (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
+#define BITSCRAMBLER_TX_IN_IDLE_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_IDLE_S  0
+/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
+ *  represents the bitscrambler tx core in run mode
+ */
+#define BITSCRAMBLER_TX_IN_RUN    (BIT(1))
+#define BITSCRAMBLER_TX_IN_RUN_M  (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
+#define BITSCRAMBLER_TX_IN_RUN_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_RUN_S  1
+/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
+ *  represents the bitscrambler tx core in wait mode to wait write back done
+ */
+#define BITSCRAMBLER_TX_IN_WAIT    (BIT(2))
+#define BITSCRAMBLER_TX_IN_WAIT_M  (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
+#define BITSCRAMBLER_TX_IN_WAIT_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_WAIT_S  2
+/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
+ *  represents the bitscrambler tx core in pause mode
+ */
+#define BITSCRAMBLER_TX_IN_PAUSE    (BIT(3))
+#define BITSCRAMBLER_TX_IN_PAUSE_M  (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
+#define BITSCRAMBLER_TX_IN_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_PAUSE_S  3
+/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 0;
+ *  represents the bitscrambler tx fifo in empty state
+ */
+#define BITSCRAMBLER_TX_FIFO_EMPTY    (BIT(4))
+#define BITSCRAMBLER_TX_FIFO_EMPTY_M  (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
+#define BITSCRAMBLER_TX_FIFO_EMPTY_V  0x00000001U
+#define BITSCRAMBLER_TX_FIFO_EMPTY_S  4
+/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
+ *  represents the bytes numbers of bitscrambler tx core when get EOF
+ */
+#define BITSCRAMBLER_TX_EOF_GET_CNT    0x00003FFFU
+#define BITSCRAMBLER_TX_EOF_GET_CNT_M  (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
+#define BITSCRAMBLER_TX_EOF_GET_CNT_V  0x00003FFFU
+#define BITSCRAMBLER_TX_EOF_GET_CNT_S  16
+/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
+ *  represents the some EOFs will be lost for bitscrambler tx core
+ */
+#define BITSCRAMBLER_TX_EOF_OVERLOAD    (BIT(30))
+#define BITSCRAMBLER_TX_EOF_OVERLOAD_M  (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
+#define BITSCRAMBLER_TX_EOF_OVERLOAD_V  0x00000001U
+#define BITSCRAMBLER_TX_EOF_OVERLOAD_S  30
+/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
+ *  write this bit to clear reg_bitscrambler_tx_eof_overload and
+ *  reg_bitscrambler_tx_eof_get_cnt registers
+ */
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR    (BIT(31))
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M  (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V  0x00000001U
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S  31
+
+/** BITSCRAMBLER_RX_STATE_REG register
+ *  Status registers
+ */
+#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
+/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
+ *  represents the bitscrambler rx core in halt mode
+ */
+#define BITSCRAMBLER_RX_IN_IDLE    (BIT(0))
+#define BITSCRAMBLER_RX_IN_IDLE_M  (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
+#define BITSCRAMBLER_RX_IN_IDLE_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_IDLE_S  0
+/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
+ *  represents the bitscrambler rx core in run mode
+ */
+#define BITSCRAMBLER_RX_IN_RUN    (BIT(1))
+#define BITSCRAMBLER_RX_IN_RUN_M  (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
+#define BITSCRAMBLER_RX_IN_RUN_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_RUN_S  1
+/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
+ *  represents the bitscrambler rx core in wait mode to wait write back done
+ */
+#define BITSCRAMBLER_RX_IN_WAIT    (BIT(2))
+#define BITSCRAMBLER_RX_IN_WAIT_M  (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
+#define BITSCRAMBLER_RX_IN_WAIT_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_WAIT_S  2
+/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
+ *  represents the bitscrambler rx core in pause mode
+ */
+#define BITSCRAMBLER_RX_IN_PAUSE    (BIT(3))
+#define BITSCRAMBLER_RX_IN_PAUSE_M  (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
+#define BITSCRAMBLER_RX_IN_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_PAUSE_S  3
+/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
+ *  represents the bitscrambler rx fifo in full state
+ */
+#define BITSCRAMBLER_RX_FIFO_FULL    (BIT(4))
+#define BITSCRAMBLER_RX_FIFO_FULL_M  (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
+#define BITSCRAMBLER_RX_FIFO_FULL_V  0x00000001U
+#define BITSCRAMBLER_RX_FIFO_FULL_S  4
+/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
+ *  represents the bytes numbers of bitscrambler rx core when get EOF
+ */
+#define BITSCRAMBLER_RX_EOF_GET_CNT    0x00003FFFU
+#define BITSCRAMBLER_RX_EOF_GET_CNT_M  (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
+#define BITSCRAMBLER_RX_EOF_GET_CNT_V  0x00003FFFU
+#define BITSCRAMBLER_RX_EOF_GET_CNT_S  16
+/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
+ *  represents the some EOFs will be lost for bitscrambler rx core
+ */
+#define BITSCRAMBLER_RX_EOF_OVERLOAD    (BIT(30))
+#define BITSCRAMBLER_RX_EOF_OVERLOAD_M  (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
+#define BITSCRAMBLER_RX_EOF_OVERLOAD_V  0x00000001U
+#define BITSCRAMBLER_RX_EOF_OVERLOAD_S  30
+/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
+ *  write this bit to clear reg_bitscrambler_rx_eof_overload and
+ *  reg_bitscrambler_rx_eof_get_cnt registers
+ */
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR    (BIT(31))
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M  (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V  0x00000001U
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S  31
+
+/** BITSCRAMBLER_SYS_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
+/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
+ *  write this bit to set the bitscrambler tx loop back to DMA rx
+ */
+#define BITSCRAMBLER_LOOP_MODE    (BIT(0))
+#define BITSCRAMBLER_LOOP_MODE_M  (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
+#define BITSCRAMBLER_LOOP_MODE_V  0x00000001U
+#define BITSCRAMBLER_LOOP_MODE_S  0
+/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define BITSCRAMBLER_CLK_EN    (BIT(31))
+#define BITSCRAMBLER_CLK_EN_M  (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
+#define BITSCRAMBLER_CLK_EN_V  0x00000001U
+#define BITSCRAMBLER_CLK_EN_S  31
+
+/** BITSCRAMBLER_VERSION_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
+/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 36713024;
+ *  Reserved
+ */
+#define BITSCRAMBLER_BITSCRAMBLER_VER    0x0FFFFFFFU
+#define BITSCRAMBLER_BITSCRAMBLER_VER_M  (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
+#define BITSCRAMBLER_BITSCRAMBLER_VER_V  0x0FFFFFFFU
+#define BITSCRAMBLER_BITSCRAMBLER_VER_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_struct.h
new file mode 100644
index 0000000000..4701ecccf0
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/bitscrambler_struct.h
@@ -0,0 +1,612 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of tx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t tx_inst_idx:3;
+        /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t tx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg0_reg_t;
+
+/** Type of tx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst : R/W; bitpos: [31:0]; default: 4;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG
+         */
+        uint32_t tx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg1_reg_t;
+
+/** Type of rx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t rx_inst_idx:3;
+        /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t rx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg0_reg_t;
+
+/** Type of rx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst : R/W; bitpos: [31:0]; default: 12;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG
+         */
+        uint32_t rx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg1_reg_t;
+
+/** Type of tx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_tx_lut_mode
+         */
+        uint32_t tx_lut_idx:11;
+        /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t tx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg0_reg_t;
+
+/** Type of tx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut : R/W; bitpos: [31:0]; default: 20;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
+         */
+        uint32_t tx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg1_reg_t;
+
+/** Type of rx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_rx_lut_mode
+         */
+        uint32_t rx_lut_idx:11;
+        /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t rx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg0_reg_t;
+
+/** Type of rx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut : R/W; bitpos: [31:0]; default: 28;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
+         */
+        uint32_t rx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg1_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of tx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t tx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_tx_tailing_bits_reg_t;
+
+/** Type of rx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t rx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_rx_tailing_bits_reg_t;
+
+/** Type of tx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler tx
+         */
+        uint32_t tx_ena:1;
+        /** tx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler tx core
+         */
+        uint32_t tx_pause:1;
+        /** tx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler tx core
+         */
+        uint32_t tx_halt:1;
+        /** tx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
+         *  counter by write peripheral buffer
+         */
+        uint32_t tx_eof_mode:1;
+        /** tx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t tx_cond_mode:1;
+        /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t tx_fetch_mode:1;
+        /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t tx_halt_mode:1;
+        /** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t tx_rd_dummy:1;
+        /** tx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler tx fifo
+         */
+        uint32_t tx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_tx_ctrl_reg_t;
+
+/** Type of rx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler rx
+         */
+        uint32_t rx_ena:1;
+        /** rx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler rx core
+         */
+        uint32_t rx_pause:1;
+        /** rx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler rx core
+         */
+        uint32_t rx_halt:1;
+        /** rx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
+         *  buffer, 0 counter by write dma fifo
+         */
+        uint32_t rx_eof_mode:1;
+        /** rx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t rx_cond_mode:1;
+        /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t rx_fetch_mode:1;
+        /** rx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t rx_halt_mode:1;
+        /** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t rx_rd_dummy:1;
+        /** rx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler rx fifo
+         */
+        uint32_t rx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_rx_ctrl_reg_t;
+
+/** Type of sys register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** loop_mode : R/W; bitpos: [0]; default: 0;
+         *  write this bit to set the bitscrambler tx loop back to DMA rx
+         */
+        uint32_t loop_mode:1;
+        uint32_t reserved_1:30;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} bitscrambler_sys_reg_t;
+
+
+/** Group: Status registers */
+/** Type of tx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** tx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler tx core in halt mode
+         */
+        uint32_t tx_in_idle:1;
+        /** tx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler tx core in run mode
+         */
+        uint32_t tx_in_run:1;
+        /** tx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler tx core in wait mode to wait write back done
+         */
+        uint32_t tx_in_wait:1;
+        /** tx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler tx core in pause mode
+         */
+        uint32_t tx_in_pause:1;
+        /** tx_fifo_empty : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler tx fifo in empty state
+         */
+        uint32_t tx_fifo_empty:1;
+        uint32_t reserved_5:11;
+        /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler tx core when get EOF
+         */
+        uint32_t tx_eof_get_cnt:14;
+        /** tx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler tx core
+         */
+        uint32_t tx_eof_overload:1;
+        /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_tx_eof_overload and
+         *  reg_bitscrambler_tx_eof_get_cnt registers
+         */
+        uint32_t tx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_tx_state_reg_t;
+
+/** Type of rx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** rx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler rx core in halt mode
+         */
+        uint32_t rx_in_idle:1;
+        /** rx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler rx core in run mode
+         */
+        uint32_t rx_in_run:1;
+        /** rx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler rx core in wait mode to wait write back done
+         */
+        uint32_t rx_in_wait:1;
+        /** rx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler rx core in pause mode
+         */
+        uint32_t rx_in_pause:1;
+        /** rx_fifo_full : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler rx fifo in full state
+         */
+        uint32_t rx_fifo_full:1;
+        uint32_t reserved_5:11;
+        /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler rx core when get EOF
+         */
+        uint32_t rx_eof_get_cnt:14;
+        /** rx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler rx core
+         */
+        uint32_t rx_eof_overload:1;
+        /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_rx_eof_overload and
+         *  reg_bitscrambler_rx_eof_get_cnt registers
+         */
+        uint32_t rx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_rx_state_reg_t;
+
+
+/** Group: Version register */
+/** Type of version register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
+         *  Reserved
+         */
+        uint32_t bitscrambler_ver:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} bitscrambler_version_reg_t;
+
+///////////////////// TX and RX registers are exactly the same //////////////////////////////////
+// The following registers are used for both TX and RX, so we can use the same struct for both //
+/////////////////////////////////////////////////////////////////////////////////////////////////
+
+/** Type of inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t inst_idx:3;
+        /** inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_inst_cfg0_reg_t;
+
+/** Type of inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** inst : R/W; bitpos: [31:0]; default: 4;
+         *  write this bits to update instruction, Read this bits to get instruction.
+         */
+        uint32_t inst:32;
+    };
+    uint32_t val;
+} bitscrambler_inst_cfg1_reg_t;
+
+/** Type of lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on lut_mode
+         */
+        uint32_t lut_idx:11;
+        /** lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_lut_cfg0_reg_t;
+
+/** Type of lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** lut : R/W; bitpos: [31:0]; default: 20;
+         *  write this bits to update LUT, Read this bits to get LUT
+         */
+        uint32_t lut:32;
+    };
+    uint32_t val;
+} bitscrambler_lut_cfg1_reg_t;
+
+/** Type of tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_tailing_bits_reg_t;
+
+/** Type of ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler tx
+         */
+        uint32_t ena:1;
+        /** pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler tx core
+         */
+        uint32_t pause:1;
+        /** halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler tx core
+         */
+        uint32_t halt:1;
+        /** eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_tailing_bits, 0: counter by read dma fifo, 0
+         *  counter by write peripheral buffer
+         */
+        uint32_t eof_mode:1;
+        /** cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t cond_mode:1;
+        /** fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t fetch_mode:1;
+        /** halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler tx core halt mode when halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t halt_mode:1;
+        /** rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t rd_dummy:1;
+        /** fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler tx fifo
+         */
+        uint32_t fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_ctrl_reg_t;
+
+/** Group: Status registers */
+/** Type of state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler tx core in halt mode
+         */
+        uint32_t in_idle:1;
+        /** in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler tx core in run mode
+         */
+        uint32_t in_run:1;
+        /** in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler tx core in wait mode to wait write back done
+         */
+        uint32_t in_wait:1;
+        /** in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler tx core in pause mode
+         */
+        uint32_t in_pause:1;
+        /** fifo_empty : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler tx fifo in empty state
+         */
+        uint32_t fifo_empty:1;
+        uint32_t reserved_5:11;
+        /** eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler tx core when get EOF
+         */
+        uint32_t eof_get_cnt:14;
+        /** eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler tx core
+         */
+        uint32_t eof_overload:1;
+        /** eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_eof_overload and
+         *  reg_bitscrambler_eof_get_cnt registers
+         */
+        uint32_t eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_state_reg_t;
+
+typedef struct {
+    volatile struct {
+        bitscrambler_inst_cfg0_reg_t cfg0;
+        bitscrambler_inst_cfg1_reg_t cfg1;
+    } inst_cfg[2];
+    volatile struct {
+        bitscrambler_lut_cfg0_reg_t cfg0;
+        bitscrambler_lut_cfg1_reg_t cfg1;
+    } lut_cfg[2];
+    volatile bitscrambler_tailing_bits_reg_t tail_bits[2];
+    volatile bitscrambler_ctrl_reg_t ctrl[2];
+    volatile bitscrambler_state_reg_t state[2];
+    uint32_t reserved_038[48];
+    volatile bitscrambler_sys_reg_t sys;
+    volatile bitscrambler_version_reg_t version;
+} bitscrambler_dev_t;
+
+extern bitscrambler_dev_t BITSCRAMBLER;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/cache_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/cache_reg.h
new file mode 100644
index 0000000000..a99a74bbcb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/cache_reg.h
@@ -0,0 +1,6343 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CACHE_L1_ICACHE_CTRL_REG register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0)
+/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS0    (BIT(0))
+#define CACHE_L1_ICACHE_SHUT_IBUS0_M  (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS0_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS0_S  0
+/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS1    (BIT(1))
+#define CACHE_L1_ICACHE_SHUT_IBUS1_M  (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS1_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS1_S  1
+/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS2    (BIT(2))
+#define CACHE_L1_ICACHE_SHUT_IBUS2_M  (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS2_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS2_S  2
+/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS3    (BIT(3))
+#define CACHE_L1_ICACHE_SHUT_IBUS3_M  (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS3_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS3_S  3
+
+/** CACHE_L1_DCACHE_CTRL_REG register
+ *  L1 data Cache(L1-DCache) control register
+ */
+#define CACHE_L1_DCACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
+/** CACHE_L1_DCACHE_SHUT_DBUS0 : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS0    (BIT(0))
+#define CACHE_L1_DCACHE_SHUT_DBUS0_M  (CACHE_L1_DCACHE_SHUT_DBUS0_V << CACHE_L1_DCACHE_SHUT_DBUS0_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS0_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS0_S  0
+/** CACHE_L1_DCACHE_SHUT_DBUS1 : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS1    (BIT(1))
+#define CACHE_L1_DCACHE_SHUT_DBUS1_M  (CACHE_L1_DCACHE_SHUT_DBUS1_V << CACHE_L1_DCACHE_SHUT_DBUS1_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS1_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS1_S  1
+/** CACHE_L1_DCACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS2    (BIT(2))
+#define CACHE_L1_DCACHE_SHUT_DBUS2_M  (CACHE_L1_DCACHE_SHUT_DBUS2_V << CACHE_L1_DCACHE_SHUT_DBUS2_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS2_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS2_S  2
+/** CACHE_L1_DCACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS3    (BIT(3))
+#define CACHE_L1_DCACHE_SHUT_DBUS3_M  (CACHE_L1_DCACHE_SHUT_DBUS3_V << CACHE_L1_DCACHE_SHUT_DBUS3_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS3_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS3_S  3
+/** CACHE_L1_DCACHE_SHUT_DMA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L1_DCACHE_SHUT_DMA_M  (CACHE_L1_DCACHE_SHUT_DMA_V << CACHE_L1_DCACHE_SHUT_DMA_S)
+#define CACHE_L1_DCACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DMA_S  4
+
+/** CACHE_L1_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8)
+/** CACHE_BYPASS_L1_ICACHE0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE0_EN    (BIT(0))
+#define CACHE_BYPASS_L1_ICACHE0_EN_M  (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S)
+#define CACHE_BYPASS_L1_ICACHE0_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE0_EN_S  0
+/** CACHE_BYPASS_L1_ICACHE1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE1_EN    (BIT(1))
+#define CACHE_BYPASS_L1_ICACHE1_EN_M  (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S)
+#define CACHE_BYPASS_L1_ICACHE1_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE1_EN_S  1
+/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE2_EN    (BIT(2))
+#define CACHE_BYPASS_L1_ICACHE2_EN_M  (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S)
+#define CACHE_BYPASS_L1_ICACHE2_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE2_EN_S  2
+/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE3_EN    (BIT(3))
+#define CACHE_BYPASS_L1_ICACHE3_EN_M  (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S)
+#define CACHE_BYPASS_L1_ICACHE3_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE3_EN_S  3
+/** CACHE_BYPASS_L1_DCACHE_EN : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_DCACHE_EN    (BIT(4))
+#define CACHE_BYPASS_L1_DCACHE_EN_M  (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S)
+#define CACHE_BYPASS_L1_DCACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_DCACHE_EN_S  4
+
+/** CACHE_L1_CACHE_ATOMIC_CONF_REG register
+ *  L1 Cache atomic feature configure register
+ */
+#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc)
+/** CACHE_L1_DCACHE_ATOMIC_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable atomic feature on L1-DCache when multiple cores access
+ *  L1-DCache.  1: disable, 1: enable.
+ */
+#define CACHE_L1_DCACHE_ATOMIC_EN    (BIT(0))
+#define CACHE_L1_DCACHE_ATOMIC_EN_M  (CACHE_L1_DCACHE_ATOMIC_EN_V << CACHE_L1_DCACHE_ATOMIC_EN_S)
+#define CACHE_L1_DCACHE_ATOMIC_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_ATOMIC_EN_S  0
+
+/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10)
+/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_ICACHE_CACHESIZE_256_M  (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256_S  0
+/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_ICACHE_CACHESIZE_512_M  (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512_S  1
+/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_ICACHE_CACHESIZE_1K_M  (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_ICACHE_CACHESIZE_2K_M  (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_ICACHE_CACHESIZE_4K_M  (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_ICACHE_CACHESIZE_8K_M  (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 1;
+ *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_ICACHE_CACHESIZE_16K_M  (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_ICACHE_CACHESIZE_32K_M  (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_ICACHE_CACHESIZE_64K_M  (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_ICACHE_CACHESIZE_128K_M  (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_ICACHE_CACHESIZE_256K_M  (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_ICACHE_CACHESIZE_512K_M  (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_M  (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14)
+/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_M  (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_M  (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_M  (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_M  (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_M  (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_M  (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_DCACHE_CACHESIZE_CONF_REG register
+ *  L1 data Cache CacheSize mode configure register
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18)
+/** CACHE_L1_DCACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_DCACHE_CACHESIZE_256_M  (CACHE_L1_DCACHE_CACHESIZE_256_V << CACHE_L1_DCACHE_CACHESIZE_256_S)
+#define CACHE_L1_DCACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_256_S  0
+/** CACHE_L1_DCACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_DCACHE_CACHESIZE_512_M  (CACHE_L1_DCACHE_CACHESIZE_512_V << CACHE_L1_DCACHE_CACHESIZE_512_S)
+#define CACHE_L1_DCACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_512_S  1
+/** CACHE_L1_DCACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_DCACHE_CACHESIZE_1K_M  (CACHE_L1_DCACHE_CACHESIZE_1K_V << CACHE_L1_DCACHE_CACHESIZE_1K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_DCACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_DCACHE_CACHESIZE_2K_M  (CACHE_L1_DCACHE_CACHESIZE_2K_V << CACHE_L1_DCACHE_CACHESIZE_2K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_DCACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_DCACHE_CACHESIZE_4K_M  (CACHE_L1_DCACHE_CACHESIZE_4K_V << CACHE_L1_DCACHE_CACHESIZE_4K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_DCACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_DCACHE_CACHESIZE_8K_M  (CACHE_L1_DCACHE_CACHESIZE_8K_V << CACHE_L1_DCACHE_CACHESIZE_8K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_DCACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_DCACHE_CACHESIZE_16K_M  (CACHE_L1_DCACHE_CACHESIZE_16K_V << CACHE_L1_DCACHE_CACHESIZE_16K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_DCACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_DCACHE_CACHESIZE_32K_M  (CACHE_L1_DCACHE_CACHESIZE_32K_V << CACHE_L1_DCACHE_CACHESIZE_32K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_DCACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 1;
+ *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_DCACHE_CACHESIZE_64K_M  (CACHE_L1_DCACHE_CACHESIZE_64K_V << CACHE_L1_DCACHE_CACHESIZE_64K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_DCACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_DCACHE_CACHESIZE_128K_M  (CACHE_L1_DCACHE_CACHESIZE_128K_V << CACHE_L1_DCACHE_CACHESIZE_128K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_DCACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_DCACHE_CACHESIZE_256K_M  (CACHE_L1_DCACHE_CACHESIZE_256K_V << CACHE_L1_DCACHE_CACHESIZE_256K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_DCACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_DCACHE_CACHESIZE_512K_M  (CACHE_L1_DCACHE_CACHESIZE_512K_V << CACHE_L1_DCACHE_CACHESIZE_512K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_DCACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_M  (CACHE_L1_DCACHE_CACHESIZE_1024K_V << CACHE_L1_DCACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG register
+ *  L1 data Cache BlockSize mode configure register
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c)
+/** CACHE_L1_DCACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_M  (CACHE_L1_DCACHE_BLOCKSIZE_8_V << CACHE_L1_DCACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_DCACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_M  (CACHE_L1_DCACHE_BLOCKSIZE_16_V << CACHE_L1_DCACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_DCACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_M  (CACHE_L1_DCACHE_BLOCKSIZE_32_V << CACHE_L1_DCACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_DCACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_M  (CACHE_L1_DCACHE_BLOCKSIZE_64_V << CACHE_L1_DCACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_DCACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_M  (CACHE_L1_DCACHE_BLOCKSIZE_128_V << CACHE_L1_DCACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_DCACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_M  (CACHE_L1_DCACHE_BLOCKSIZE_256_V << CACHE_L1_DCACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20)
+/** CACHE_L1_ICACHE0_WRAP : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+ */
+#define CACHE_L1_ICACHE0_WRAP    (BIT(0))
+#define CACHE_L1_ICACHE0_WRAP_M  (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S)
+#define CACHE_L1_ICACHE0_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE0_WRAP_S  0
+/** CACHE_L1_ICACHE1_WRAP : R/W; bitpos: [1]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+ */
+#define CACHE_L1_ICACHE1_WRAP    (BIT(1))
+#define CACHE_L1_ICACHE1_WRAP_M  (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S)
+#define CACHE_L1_ICACHE1_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE1_WRAP_S  1
+/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_WRAP    (BIT(2))
+#define CACHE_L1_ICACHE2_WRAP_M  (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S)
+#define CACHE_L1_ICACHE2_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE2_WRAP_S  2
+/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_WRAP    (BIT(3))
+#define CACHE_L1_ICACHE3_WRAP_M  (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S)
+#define CACHE_L1_ICACHE3_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE3_WRAP_S  3
+/** CACHE_L1_DCACHE_WRAP : R/W; bitpos: [4]; default: 0;
+ *  Set this bit as 1 to enable L1-DCache wrap around mode.
+ */
+#define CACHE_L1_DCACHE_WRAP    (BIT(4))
+#define CACHE_L1_DCACHE_WRAP_M  (CACHE_L1_DCACHE_WRAP_V << CACHE_L1_DCACHE_WRAP_S)
+#define CACHE_L1_DCACHE_WRAP_V  0x00000001U
+#define CACHE_L1_DCACHE_WRAP_S  4
+
+/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register
+ *  Cache tag memory power control register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S  1
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU    (BIT(2))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S  2
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S  5
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU : R/W; bitpos: [6]; default: 1;
+ *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU    (BIT(6))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S  6
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S  9
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU    (BIT(10))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S  10
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S  13
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU    (BIT(14))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S  14
+/** CACHE_L1_DCACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to close clock gating of  L1-DCache tag memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_S  16
+/** CACHE_L1_DCACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_S  17
+/** CACHE_L1_DCACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register
+ *  Cache data memory power control register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S  1
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU    (BIT(2))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S  2
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S  5
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU : R/W; bitpos: [6]; default: 1;
+ *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU    (BIT(6))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S  6
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S  9
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU    (BIT(10))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S  10
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S  13
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU    (BIT(14))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S  14
+/** CACHE_L1_DCACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to close clock gating of  L1-DCache data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_S  16
+/** CACHE_L1_DCACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_S  17
+/** CACHE_L1_DCACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_S  18
+
+/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c)
+/** CACHE_L1_ICACHE0_FREEZE_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_FREEZE_EN_M  (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S)
+#define CACHE_L1_ICACHE0_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_EN_S  0
+/** CACHE_L1_ICACHE0_FREEZE_MODE : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_MODE    (BIT(1))
+#define CACHE_L1_ICACHE0_FREEZE_MODE_M  (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE0_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_MODE_S  1
+/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_DONE    (BIT(2))
+#define CACHE_L1_ICACHE0_FREEZE_DONE_M  (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE0_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_DONE_S  2
+/** CACHE_L1_ICACHE1_FREEZE_EN : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_FREEZE_EN_M  (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S)
+#define CACHE_L1_ICACHE1_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_EN_S  4
+/** CACHE_L1_ICACHE1_FREEZE_MODE : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_MODE    (BIT(5))
+#define CACHE_L1_ICACHE1_FREEZE_MODE_M  (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE1_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_MODE_S  5
+/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_DONE    (BIT(6))
+#define CACHE_L1_ICACHE1_FREEZE_DONE_M  (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE1_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_DONE_S  6
+/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_FREEZE_EN_M  (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S)
+#define CACHE_L1_ICACHE2_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_EN_S  8
+/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_MODE    (BIT(9))
+#define CACHE_L1_ICACHE2_FREEZE_MODE_M  (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE2_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_MODE_S  9
+/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_DONE    (BIT(10))
+#define CACHE_L1_ICACHE2_FREEZE_DONE_M  (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE2_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_DONE_S  10
+/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_FREEZE_EN_M  (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S)
+#define CACHE_L1_ICACHE3_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_EN_S  12
+/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_MODE    (BIT(13))
+#define CACHE_L1_ICACHE3_FREEZE_MODE_M  (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE3_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_MODE_S  13
+/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_DONE    (BIT(14))
+#define CACHE_L1_ICACHE3_FREEZE_DONE_M  (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE3_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_DONE_S  14
+/** CACHE_L1_DCACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
+ *  The bit is used to enable freeze operation on L1-DCache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_DCACHE_FREEZE_EN    (BIT(16))
+#define CACHE_L1_DCACHE_FREEZE_EN_M  (CACHE_L1_DCACHE_FREEZE_EN_V << CACHE_L1_DCACHE_FREEZE_EN_S)
+#define CACHE_L1_DCACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_EN_S  16
+/** CACHE_L1_DCACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_DCACHE_FREEZE_MODE    (BIT(17))
+#define CACHE_L1_DCACHE_FREEZE_MODE_M  (CACHE_L1_DCACHE_FREEZE_MODE_V << CACHE_L1_DCACHE_FREEZE_MODE_S)
+#define CACHE_L1_DCACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_MODE_S  17
+/** CACHE_L1_DCACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-DCache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_DCACHE_FREEZE_DONE    (BIT(18))
+#define CACHE_L1_DCACHE_FREEZE_DONE_M  (CACHE_L1_DCACHE_FREEZE_DONE_V << CACHE_L1_DCACHE_FREEZE_DONE_S)
+#define CACHE_L1_DCACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_DONE_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
+/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : R/W; bitpos: [1]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : R/W; bitpos: [5]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S  13
+/** CACHE_L1_DCACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_M  (CACHE_L1_DCACHE_DATA_MEM_RD_EN_V << CACHE_L1_DCACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_S  16
+/** CACHE_L1_DCACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
+ *  The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_M  (CACHE_L1_DCACHE_DATA_MEM_WR_EN_V << CACHE_L1_DCACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_S  17
+
+/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34)
+/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : R/W; bitpos: [1]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : R/W; bitpos: [5]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S  13
+/** CACHE_L1_DCACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_M  (CACHE_L1_DCACHE_TAG_MEM_RD_EN_V << CACHE_L1_DCACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_S  16
+/** CACHE_L1_DCACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
+ *  The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_M  (CACHE_L1_DCACHE_TAG_MEM_WR_EN_V << CACHE_L1_DCACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_S  17
+
+/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x38)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE0_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 prelock.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_M  (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x3c)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache0, which should be used together with
+ *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x40)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache0, which should be used together with
+ *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x44)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x48)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE1_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 prelock.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_M  (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x4c)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache1, which should be used together with
+ *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x50)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache1, which should be used together with
+ *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x54)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x58)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 prelock.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_M  (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x5c)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache2, which should be used together with
+ *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x60)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache2, which should be used together with
+ *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x64)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x68)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 prelock.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_M  (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x6c)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache3, which should be used together with
+ *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x70)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache3, which should be used together with
+ *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x74)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_DCACHE_PRELOCK_CONF_REG register
+ *  L1 data Cache prelock configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_DCACHE_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 dcache prelock.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_PRELOCK_RGID_M  (CACHE_L1_DCACHE_PRELOCK_RGID_V << CACHE_L1_DCACHE_PRELOCK_RGID_S)
+#define CACHE_L1_DCACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L1 data Cache prelock section0 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-DCache, which should be used together with
+ *  L1_DCACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L1 data Cache prelock section1 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80)
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-DCache, which should be used together with
+ *  L1_DCACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
+ *  L1 data Cache prelock section size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_LOCK_CTRL_REG register
+ *  Lock-class (manual lock) operation control register
+ */
+#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88)
+/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+ *  operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive,
+ *  that is, those bits can not be set to 1 at the same time. (2) lock operation can be
+ *  applied on LL1-ICache, L1-DCache and L2-Cache.
+ */
+#define CACHE_LOCK_ENA    (BIT(0))
+#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
+#define CACHE_LOCK_ENA_V  0x00000001U
+#define CACHE_LOCK_ENA_S  0
+/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable unlock operation. It will be cleared by hardware after
+ *  unlock operation done. Note that (1) this bit and lock_ena bit are mutually
+ *  exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock
+ *  operation can be applied on L1-ICache, L1-DCache and L2-Cache.
+ */
+#define CACHE_UNLOCK_ENA    (BIT(1))
+#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
+#define CACHE_UNLOCK_ENA_V  0x00000001U
+#define CACHE_UNLOCK_ENA_S  1
+/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
+ *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+ *  not finished. 1: finished.
+ */
+#define CACHE_LOCK_DONE    (BIT(2))
+#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
+#define CACHE_LOCK_DONE_V  0x00000001U
+#define CACHE_LOCK_DONE_S  2
+/** CACHE_LOCK_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of cache lock/unlock.
+ */
+#define CACHE_LOCK_RGID    0x0000000FU
+#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
+#define CACHE_LOCK_RGID_V  0x0000000FU
+#define CACHE_LOCK_RGID_S  3
+
+/** CACHE_LOCK_MAP_REG register
+ *  Lock (manual lock) map configure register
+ */
+#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c)
+/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]:
+ *  L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+ */
+#define CACHE_LOCK_MAP    0x0000003FU
+#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
+#define CACHE_LOCK_MAP_V  0x0000003FU
+#define CACHE_LOCK_MAP_S  0
+
+/** CACHE_LOCK_ADDR_REG register
+ *  Lock (manual lock) address configure register
+ */
+#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90)
+/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the lock/unlock
+ *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+ */
+#define CACHE_LOCK_ADDR    0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
+#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_S  0
+
+/** CACHE_LOCK_SIZE_REG register
+ *  Lock (manual lock) size configure register
+ */
+#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94)
+/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the lock/unlock operation, which
+ *  should be used together with CACHE_LOCK_ADDR_REG
+ */
+#define CACHE_LOCK_SIZE    0x0000FFFFU
+#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
+#define CACHE_LOCK_SIZE_V  0x0000FFFFU
+#define CACHE_LOCK_SIZE_S  0
+
+/** CACHE_SYNC_CTRL_REG register
+ *  Sync-class operation control register
+ */
+#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98)
+/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
+ *  The bit is used to enable invalidate operation. It will be cleared by hardware
+ *  after invalidate operation done. Note that this bit and the other sync-bits
+ *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_INVALIDATE_ENA    (BIT(0))
+#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
+#define CACHE_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_INVALIDATE_ENA_S  0
+/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable clean operation. It will be cleared by hardware after
+ *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+ *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+ *  bits can not be set to 1 at the same time.
+ */
+#define CACHE_CLEAN_ENA    (BIT(1))
+#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
+#define CACHE_CLEAN_ENA_V  0x00000001U
+#define CACHE_CLEAN_ENA_S  1
+/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
+ *  The bit is used to enable writeback operation. It will be cleared by hardware after
+ *  writeback operation done. Note that this bit and the other sync-bits
+ *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_ENA    (BIT(2))
+#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
+#define CACHE_WRITEBACK_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_ENA_S  2
+/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
+ *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+ *  hardware after writeback-invalidate operation done. Note that this bit and the
+ *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+ *  that is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
+#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
+#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
+/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
+ *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+ *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+ */
+#define CACHE_SYNC_DONE    (BIT(4))
+#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
+#define CACHE_SYNC_DONE_V  0x00000001U
+#define CACHE_SYNC_DONE_S  4
+/** CACHE_SYNC_RGID : R/W; bitpos: [8:5]; default: 0;
+ *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+ *  writeback, writeback_invalidate)
+ */
+#define CACHE_SYNC_RGID    0x0000000FU
+#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
+#define CACHE_SYNC_RGID_V  0x0000000FU
+#define CACHE_SYNC_RGID_S  5
+
+/** CACHE_SYNC_MAP_REG register
+ *  Sync map configure register
+ */
+#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c)
+/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 31;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]:
+ *  L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+ */
+#define CACHE_SYNC_MAP    0x0000003FU
+#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
+#define CACHE_SYNC_MAP_V  0x0000003FU
+#define CACHE_SYNC_MAP_S  0
+
+/** CACHE_SYNC_ADDR_REG register
+ *  Sync address configure register
+ */
+#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0)
+/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the sync operation,
+ *  which should be used together with CACHE_SYNC_SIZE_REG
+ */
+#define CACHE_SYNC_ADDR    0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
+#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_S  0
+
+/** CACHE_SYNC_SIZE_REG register
+ *  Sync size configure register
+ */
+#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4)
+/** CACHE_SYNC_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the sync operation, which should be
+ *  used together with CACHE_SYNC_ADDR_REG
+ */
+#define CACHE_SYNC_SIZE    0x0FFFFFFFU
+#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
+#define CACHE_SYNC_SIZE_V  0x0FFFFFFFU
+#define CACHE_SYNC_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa8)
+/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_M  (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_M  (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M  (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 preload.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_M  (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE0_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 icache0 preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE0_PRELOAD_MODE_M  (CACHE_L1_ICACHE0_PRELOAD_MODE_V << CACHE_L1_ICACHE0_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xac)
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M  (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb0)
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M  (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb4)
+/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_M  (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_M  (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M  (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 preload.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_M  (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE1_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 icache1 preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE1_PRELOAD_MODE_M  (CACHE_L1_ICACHE1_PRELOAD_MODE_V << CACHE_L1_ICACHE1_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb8)
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M  (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xbc)
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M  (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc0)
+/** CACHE_L1_ICACHE2_PRELOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_M  (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_M  (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M  (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 preload.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_M  (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE2_PRELOAD_MODE : HRO; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 icache2 preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE2_PRELOAD_MODE_M  (CACHE_L1_ICACHE2_PRELOAD_MODE_V << CACHE_L1_ICACHE2_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc4)
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M  (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc8)
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M  (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xcc)
+/** CACHE_L1_ICACHE3_PRELOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_M  (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_M  (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M  (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 preload.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_M  (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE3_PRELOAD_MODE : HRO; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 icache3 preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE3_PRELOAD_MODE_M  (CACHE_L1_ICACHE3_PRELOAD_MODE_V << CACHE_L1_ICACHE3_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd0)
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M  (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd4)
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M  (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_CTRL_REG register
+ *  L1 data Cache  preload-operation control register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8)
+/** CACHE_L1_DCACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-DCache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_DCACHE_PRELOAD_ENA_M  (CACHE_L1_DCACHE_PRELOAD_ENA_V << CACHE_L1_DCACHE_PRELOAD_ENA_S)
+#define CACHE_L1_DCACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_ENA_S  0
+/** CACHE_L1_DCACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_DCACHE_PRELOAD_DONE_M  (CACHE_L1_DCACHE_PRELOAD_DONE_V << CACHE_L1_DCACHE_PRELOAD_DONE_S)
+#define CACHE_L1_DCACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_DONE_S  1
+/** CACHE_L1_DCACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_M  (CACHE_L1_DCACHE_PRELOAD_ORDER_V << CACHE_L1_DCACHE_PRELOAD_ORDER_S)
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_S  2
+/** CACHE_L1_DCACHE_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 dcache preload.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_PRELOAD_RGID_M  (CACHE_L1_DCACHE_PRELOAD_RGID_V << CACHE_L1_DCACHE_PRELOAD_RGID_S)
+#define CACHE_L1_DCACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_PRELOAD_RGID_S  3
+/** CACHE_L1_DCACHE_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l1 dcache preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_DCACHE_PRELOAD_MODE_M  (CACHE_L1_DCACHE_PRELOAD_MODE_V << CACHE_L1_DCACHE_PRELOAD_MODE_S)
+#define CACHE_L1_DCACHE_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_MODE_S  7
+
+/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
+ *  L1 data Cache  preload address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc)
+/** CACHE_L1_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on L1-DCache,
+ *  which should be used together with L1_DCACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_M  (CACHE_L1_DCACHE_PRELOAD_ADDR_V << CACHE_L1_DCACHE_PRELOAD_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
+ *  L1 data Cache  preload size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0)
+/** CACHE_L1_DCACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_M  (CACHE_L1_DCACHE_PRELOAD_SIZE_V << CACHE_L1_DCACHE_PRELOAD_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 autoload.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe8)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xec)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xf0)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf8)
+/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 autoload.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xfc)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x100)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x104)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x108)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x10c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 autoload.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x110)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x114)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x118)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x11c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x120)
+/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 autoload.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x124)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x128)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x12c)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x130)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG register
+ *  L1 data Cache autoload-operation control register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134)
+/** CACHE_L1_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-DCache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L1_DCACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-DCache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_M  (CACHE_L1_DCACHE_AUTOLOAD_DONE_V << CACHE_L1_DCACHE_AUTOLOAD_DONE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L1_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-DCache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_M  (CACHE_L1_DCACHE_AUTOLOAD_ORDER_V << CACHE_L1_DCACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-DCache.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA : R/W; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L1_DCACHE_AUTOLOAD_RGID : R/W; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l1 dcache autoload.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_M  (CACHE_L1_DCACHE_AUTOLOAD_RGID_V << CACHE_L1_DCACHE_AUTOLOAD_RGID_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 data Cache autoload section 0 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 data Cache autoload section 0 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L1 data Cache autoload section 2 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x148)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the third section for
+ *  autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L1 data Cache autoload section 2 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x14c)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x150)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the fourth section
+ *  for autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x154)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158)
+/** CACHE_L1_IBUS0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ENA_M  (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ENA_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ENA_M  (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ENA_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ENA_M  (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ENA_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ENA_M  (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ENA_S  3
+/** CACHE_L1_DBUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_ENA    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_ENA_M  (CACHE_L1_DBUS0_OVF_INT_ENA_V << CACHE_L1_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_ENA_S  4
+/** CACHE_L1_DBUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_ENA    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_ENA_M  (CACHE_L1_DBUS1_OVF_INT_ENA_V << CACHE_L1_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_ENA_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ENA_M  (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ENA_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ENA_M  (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ENA_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c)
+/** CACHE_L1_IBUS0_OVF_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+ *  to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_CLR    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_CLR_M  (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_CLR_S  0
+/** CACHE_L1_IBUS1_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+ *  to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_CLR    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_CLR_M  (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_CLR_S  1
+/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_CLR    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_CLR_M  (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_CLR_S  2
+/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_CLR    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_CLR_M  (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_CLR_S  3
+/** CACHE_L1_DBUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_CLR    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_CLR_M  (CACHE_L1_DBUS0_OVF_INT_CLR_V << CACHE_L1_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_CLR_S  4
+/** CACHE_L1_DBUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_CLR    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_CLR_M  (CACHE_L1_DBUS1_OVF_INT_CLR_V << CACHE_L1_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_CLR_S  5
+/** CACHE_L1_DBUS2_OVF_INT_CLR : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_CLR    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_CLR_M  (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_CLR_S  6
+/** CACHE_L1_DBUS3_OVF_INT_CLR : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_CLR    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_CLR_M  (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_CLR_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160)
+/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+ *  due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_RAW    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_RAW_M  (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_RAW_S  0
+/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+ *  due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_RAW    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_RAW_M  (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_RAW_S  1
+/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+ *  due to bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_OVF_INT_RAW    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_RAW_M  (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_RAW_S  2
+/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+ *  due to bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_OVF_INT_RAW    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_RAW_M  (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_RAW_S  3
+/** CACHE_L1_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_RAW    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_RAW_M  (CACHE_L1_DBUS0_OVF_INT_RAW_V << CACHE_L1_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_RAW_S  4
+/** CACHE_L1_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_RAW    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_RAW_M  (CACHE_L1_DBUS1_OVF_INT_RAW_V << CACHE_L1_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_RAW_S  5
+/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_OVF_INT_RAW    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_RAW_M  (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_RAW_S  6
+/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_OVF_INT_RAW    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_RAW_M  (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_RAW_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164)
+/** CACHE_L1_IBUS0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ST    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ST_M  (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S)
+#define CACHE_L1_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ST_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ST    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ST_M  (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S)
+#define CACHE_L1_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ST_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ST    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ST_M  (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S)
+#define CACHE_L1_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ST_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ST    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ST_M  (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S)
+#define CACHE_L1_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ST_S  3
+/** CACHE_L1_DBUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_ST    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_ST_M  (CACHE_L1_DBUS0_OVF_INT_ST_V << CACHE_L1_DBUS0_OVF_INT_ST_S)
+#define CACHE_L1_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_ST_S  4
+/** CACHE_L1_DBUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_ST    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_ST_M  (CACHE_L1_DBUS1_OVF_INT_ST_V << CACHE_L1_DBUS1_OVF_INT_ST_S)
+#define CACHE_L1_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_ST_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ST : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ST    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ST_M  (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S)
+#define CACHE_L1_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ST_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ST : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ST    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ST_M  (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S)
+#define CACHE_L1_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ST_S  7
+
+/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x168)
+/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S  0
+/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE    (BIT(1))
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S  1
+/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE    (BIT(2))
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S  2
+/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : R/W; bitpos: [3]; default: 0;
+ *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE    (BIT(3))
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S  3
+/** CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to configure l1 dcache access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE    (BIT(4))
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x16c)
+/** CACHE_L1_ICACHE0_FAIL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M  (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M  (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M  (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M  (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_ENA    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_M  (CACHE_L1_DCACHE_FAIL_INT_ENA_V << CACHE_L1_DCACHE_FAIL_INT_ENA_S)
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x170)
+/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M  (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M  (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M  (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M  (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_M  (CACHE_L1_DCACHE_FAIL_INT_CLR_V << CACHE_L1_DCACHE_FAIL_INT_CLR_S)
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x174)
+/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M  (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M  (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M  (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M  (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_RAW    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_M  (CACHE_L1_DCACHE_FAIL_INT_RAW_V << CACHE_L1_DCACHE_FAIL_INT_RAW_S)
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x178)
+/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_M  (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_M  (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_M  (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_M  (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+ *  to cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_ST    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_ST_M  (CACHE_L1_DCACHE_FAIL_INT_ST_V << CACHE_L1_DCACHE_FAIL_INT_ST_S)
+#define CACHE_L1_DCACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_ST_S  4
+
+/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x17c)
+/** CACHE_L1_IBUS0_CNT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_CNT_ENA_M  (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S)
+#define CACHE_L1_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_ENA_S  0
+/** CACHE_L1_IBUS1_CNT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_CNT_ENA_M  (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S)
+#define CACHE_L1_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_ENA_S  1
+/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_CNT_ENA_M  (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S)
+#define CACHE_L1_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_ENA_S  2
+/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_CNT_ENA_M  (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S)
+#define CACHE_L1_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_ENA_S  3
+/** CACHE_L1_DBUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CNT_ENA    (BIT(4))
+#define CACHE_L1_DBUS0_CNT_ENA_M  (CACHE_L1_DBUS0_CNT_ENA_V << CACHE_L1_DBUS0_CNT_ENA_S)
+#define CACHE_L1_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS0_CNT_ENA_S  4
+/** CACHE_L1_DBUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CNT_ENA    (BIT(5))
+#define CACHE_L1_DBUS1_CNT_ENA_M  (CACHE_L1_DBUS1_CNT_ENA_V << CACHE_L1_DBUS1_CNT_ENA_S)
+#define CACHE_L1_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS1_CNT_ENA_S  5
+/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_CNT_ENA_M  (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S)
+#define CACHE_L1_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_ENA_S  6
+/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_CNT_ENA_M  (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S)
+#define CACHE_L1_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_ENA_S  7
+/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0;
+ *  The bit is used to clear ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_CLR    (BIT(16))
+#define CACHE_L1_IBUS0_CNT_CLR_M  (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S)
+#define CACHE_L1_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_CLR_S  16
+/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0;
+ *  The bit is used to clear ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_CLR    (BIT(17))
+#define CACHE_L1_IBUS1_CNT_CLR_M  (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S)
+#define CACHE_L1_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_CLR_S  17
+/** CACHE_L1_IBUS2_CNT_CLR : HRO; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_CLR    (BIT(18))
+#define CACHE_L1_IBUS2_CNT_CLR_M  (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S)
+#define CACHE_L1_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_CLR_S  18
+/** CACHE_L1_IBUS3_CNT_CLR : HRO; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_CLR    (BIT(19))
+#define CACHE_L1_IBUS3_CNT_CLR_M  (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S)
+#define CACHE_L1_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_CLR_S  19
+/** CACHE_L1_DBUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
+ *  The bit is used to clear dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CNT_CLR    (BIT(20))
+#define CACHE_L1_DBUS0_CNT_CLR_M  (CACHE_L1_DBUS0_CNT_CLR_V << CACHE_L1_DBUS0_CNT_CLR_S)
+#define CACHE_L1_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS0_CNT_CLR_S  20
+/** CACHE_L1_DBUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
+ *  The bit is used to clear dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CNT_CLR    (BIT(21))
+#define CACHE_L1_DBUS1_CNT_CLR_M  (CACHE_L1_DBUS1_CNT_CLR_V << CACHE_L1_DBUS1_CNT_CLR_S)
+#define CACHE_L1_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS1_CNT_CLR_S  21
+/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_CLR    (BIT(22))
+#define CACHE_L1_DBUS2_CNT_CLR_M  (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S)
+#define CACHE_L1_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_CLR_S  22
+/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_CLR    (BIT(23))
+#define CACHE_L1_DBUS3_CNT_CLR_M  (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S)
+#define CACHE_L1_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_CLR_S  23
+
+/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x180)
+/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_M  (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S)
+#define CACHE_L1_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x184)
+/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_M  (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S)
+#define CACHE_L1_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x188)
+/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_M  (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x18c)
+/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x190)
+/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_M  (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S)
+#define CACHE_L1_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x194)
+/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_M  (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S)
+#define CACHE_L1_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x198)
+/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_M  (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x19c)
+/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1a0)
+/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_M  (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S)
+#define CACHE_L1_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a4)
+/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_M  (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S)
+#define CACHE_L1_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a8)
+/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_M  (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1ac)
+/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1b0)
+/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_M  (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S)
+#define CACHE_L1_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b4)
+/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_M  (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S)
+#define CACHE_L1_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b8)
+/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_M  (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1bc)
+/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_HIT_CNT_REG register
+ *  L1-DCache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
+/** CACHE_L1_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_HIT_CNT_M  (CACHE_L1_DBUS0_HIT_CNT_V << CACHE_L1_DBUS0_HIT_CNT_S)
+#define CACHE_L1_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_MISS_CNT_REG register
+ *  L1-DCache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
+/** CACHE_L1_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_MISS_CNT_M  (CACHE_L1_DBUS0_MISS_CNT_V << CACHE_L1_DBUS0_MISS_CNT_S)
+#define CACHE_L1_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
+/** CACHE_L1_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_CONFLICT_CNT_M  (CACHE_L1_DBUS0_CONFLICT_CNT_V << CACHE_L1_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
+/** CACHE_L1_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS0_NXTLVL_RD_CNT_V << CACHE_L1_DBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus0 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
+/** CACHE_L1_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS0_NXTLVL_WR_CNT_V << CACHE_L1_DBUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_HIT_CNT_REG register
+ *  L1-DCache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
+/** CACHE_L1_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_HIT_CNT_M  (CACHE_L1_DBUS1_HIT_CNT_V << CACHE_L1_DBUS1_HIT_CNT_S)
+#define CACHE_L1_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_MISS_CNT_REG register
+ *  L1-DCache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
+/** CACHE_L1_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_MISS_CNT_M  (CACHE_L1_DBUS1_MISS_CNT_V << CACHE_L1_DBUS1_MISS_CNT_S)
+#define CACHE_L1_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
+/** CACHE_L1_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_CONFLICT_CNT_M  (CACHE_L1_DBUS1_CONFLICT_CNT_V << CACHE_L1_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
+/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus1 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
+/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1e8)
+/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_M  (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S)
+#define CACHE_L1_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1ec)
+/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_M  (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S)
+#define CACHE_L1_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1f0)
+/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_M  (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f4)
+/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus2 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1f8)
+/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1fc)
+/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_M  (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S)
+#define CACHE_L1_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x200)
+/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_M  (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S)
+#define CACHE_L1_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x204)
+/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_M  (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x208)
+/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus3 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x20c)
+/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x210)
+/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
+#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_S  0
+/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x214)
+/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x218)
+/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
+#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_S  0
+/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x21c)
+/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x220)
+/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_M  (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S)
+#define CACHE_L1_ICACHE2_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_S  0
+/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_M  (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE2_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x224)
+/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_M  (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE2_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x228)
+/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_M  (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S)
+#define CACHE_L1_ICACHE3_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_S  0
+/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_M  (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE3_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x22c)
+/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_M  (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE3_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_S  0
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L1-DCache Access Fail ID/attribution information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x230)
+/** CACHE_L1_DCACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ID_M  (CACHE_L1_DCACHE_FAIL_ID_V << CACHE_L1_DCACHE_FAIL_ID_S)
+#define CACHE_L1_DCACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ID_S  0
+/** CACHE_L1_DCACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ATTR_M  (CACHE_L1_DCACHE_FAIL_ATTR_V << CACHE_L1_DCACHE_FAIL_ATTR_S)
+#define CACHE_L1_DCACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ATTR_S  16
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
+ *  L1-DCache Access Fail Address information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x234)
+/** CACHE_L1_DCACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_FAIL_ADDR_M  (CACHE_L1_DCACHE_FAIL_ADDR_V << CACHE_L1_DCACHE_FAIL_ADDR_S)
+#define CACHE_L1_DCACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_FAIL_ADDR_S  0
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x238)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of L1-DCache preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V << CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S  4
+/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation done.
+ */
+#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
+#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ENA_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V << CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S  11
+/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
+#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ENA_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x23c)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-DCache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V << CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S  4
+/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+ *  done.
+ */
+#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
+#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
+#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_CLR_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The bit is used to clear interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V << CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S  11
+/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
+#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
+#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_CLR_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x240)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation is
+ *  done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V << CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S  4
+/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
+#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
+#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_RAW_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V << CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S  11
+/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+ *  occurs.
+ */
+#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
+#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
+#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_RAW_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x244)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-DCache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ST_V << CACHE_L1_DCACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_S  4
+/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when Cache
+ *  sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
+#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ST_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : RO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ST_V << CACHE_L1_DCACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_S  11
+/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the status of the interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
+#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ST_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x248)
+/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M  (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S  0
+/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M  (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S  2
+/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M  (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S  4
+/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M  (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S  6
+/** CACHE_L1_DCACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_M  (CACHE_L1_DCACHE_PLD_ERR_CODE_V << CACHE_L1_DCACHE_PLD_ERR_CODE_S)
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_S  8
+/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
+ *  The values 0-2 are available which means sync map, command conflict and size are
+ *  error in Cache System.
+ */
+#define CACHE_SYNC_ERR_CODE    0x00000003U
+#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
+#define CACHE_SYNC_ERR_CODE_V  0x00000003U
+#define CACHE_SYNC_ERR_CODE_S  12
+
+/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c)
+/** CACHE_L1_ICACHE0_SYNC_RST : R/W; bitpos: [0]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE0_SYNC_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_SYNC_RST_M  (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S)
+#define CACHE_L1_ICACHE0_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_SYNC_RST_S  0
+/** CACHE_L1_ICACHE1_SYNC_RST : R/W; bitpos: [1]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE1_SYNC_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_SYNC_RST_M  (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S)
+#define CACHE_L1_ICACHE1_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_SYNC_RST_S  1
+/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_SYNC_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_SYNC_RST_M  (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S)
+#define CACHE_L1_ICACHE2_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_SYNC_RST_S  2
+/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_SYNC_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_SYNC_RST_M  (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S)
+#define CACHE_L1_ICACHE3_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_SYNC_RST_S  3
+/** CACHE_L1_DCACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset sync-logic inside L1-DCache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_DCACHE_SYNC_RST    (BIT(4))
+#define CACHE_L1_DCACHE_SYNC_RST_M  (CACHE_L1_DCACHE_SYNC_RST_V << CACHE_L1_DCACHE_SYNC_RST_S)
+#define CACHE_L1_DCACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L1_DCACHE_SYNC_RST_S  4
+
+/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x250)
+/** CACHE_L1_ICACHE0_PLD_RST : R/W; bitpos: [0]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_RST_M  (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S)
+#define CACHE_L1_ICACHE0_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_RST_S  0
+/** CACHE_L1_ICACHE1_PLD_RST : R/W; bitpos: [1]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_RST_M  (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S)
+#define CACHE_L1_ICACHE1_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_RST_S  1
+/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_RST_M  (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S)
+#define CACHE_L1_ICACHE2_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_RST_S  2
+/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_RST_M  (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S)
+#define CACHE_L1_ICACHE3_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_RST_S  3
+/** CACHE_L1_DCACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset preload-logic inside L1-DCache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_RST    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_RST_M  (CACHE_L1_DCACHE_PLD_RST_V << CACHE_L1_DCACHE_PLD_RST_S)
+#define CACHE_L1_DCACHE_PLD_RST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_RST_S  4
+
+/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x254)
+/** CACHE_L1_ICACHE0_ALD_BUF_CLR : R/W; bitpos: [0]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+ *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+ *  works in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M  (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S  0
+/** CACHE_L1_ICACHE1_ALD_BUF_CLR : R/W; bitpos: [1]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+ *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+ *  works in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M  (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S  1
+/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M  (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S  2
+/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M  (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S  3
+/** CACHE_L1_DCACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-DCache. If this bit is active,
+ *  autoload will not work in L1-DCache. This bit should not be active when autoload
+ *  works in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_ALD_BUF_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_M  (CACHE_L1_DCACHE_ALD_BUF_CLR_V << CACHE_L1_DCACHE_ALD_BUF_CLR_S)
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_S  4
+
+/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x258)
+/** CACHE_L1_ICACHE0_UNALLOC_CLR : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
+/** CACHE_L1_ICACHE1_UNALLOC_CLR : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_S  1
+/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_UNALLOC_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_M  (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_S  2
+/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_UNALLOC_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_M  (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
+/** CACHE_L1_DCACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 dcache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_DCACHE_UNALLOC_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_UNALLOC_CLR_M  (CACHE_L1_DCACHE_UNALLOC_CLR_V << CACHE_L1_DCACHE_UNALLOC_CLR_S)
+#define CACHE_L1_DCACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_UNALLOC_CLR_S  4
+
+/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x25c)
+/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_TAG_OBJECT    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_OBJECT_M  (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE0_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_OBJECT_S  0
+/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_TAG_OBJECT    (BIT(1))
+#define CACHE_L1_ICACHE1_TAG_OBJECT_M  (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE1_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_OBJECT_S  1
+/** CACHE_L1_ICACHE2_TAG_OBJECT : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_OBJECT    (BIT(2))
+#define CACHE_L1_ICACHE2_TAG_OBJECT_M  (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE2_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_OBJECT_S  2
+/** CACHE_L1_ICACHE3_TAG_OBJECT : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_OBJECT    (BIT(3))
+#define CACHE_L1_ICACHE3_TAG_OBJECT_M  (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE3_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_OBJECT_S  3
+/** CACHE_L1_DCACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to set L1-DCache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_DCACHE_TAG_OBJECT    (BIT(4))
+#define CACHE_L1_DCACHE_TAG_OBJECT_M  (CACHE_L1_DCACHE_TAG_OBJECT_V << CACHE_L1_DCACHE_TAG_OBJECT_S)
+#define CACHE_L1_DCACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_OBJECT_S  4
+/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_MEM_OBJECT    (BIT(6))
+#define CACHE_L1_ICACHE0_MEM_OBJECT_M  (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE0_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_MEM_OBJECT_S  6
+/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_MEM_OBJECT    (BIT(7))
+#define CACHE_L1_ICACHE1_MEM_OBJECT_M  (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE1_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_MEM_OBJECT_S  7
+/** CACHE_L1_ICACHE2_MEM_OBJECT : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_MEM_OBJECT    (BIT(8))
+#define CACHE_L1_ICACHE2_MEM_OBJECT_M  (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE2_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_MEM_OBJECT_S  8
+/** CACHE_L1_ICACHE3_MEM_OBJECT : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_MEM_OBJECT    (BIT(9))
+#define CACHE_L1_ICACHE3_MEM_OBJECT_M  (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE3_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_MEM_OBJECT_S  9
+/** CACHE_L1_DCACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to set L1-DCache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_DCACHE_MEM_OBJECT    (BIT(10))
+#define CACHE_L1_DCACHE_MEM_OBJECT_M  (CACHE_L1_DCACHE_MEM_OBJECT_V << CACHE_L1_DCACHE_MEM_OBJECT_S)
+#define CACHE_L1_DCACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_DCACHE_MEM_OBJECT_S  10
+
+/** CACHE_L1_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x260)
+/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
+#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L1_CACHE_VADDR_REG register
+ *  Cache Vaddr register
+ */
+#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x264)
+/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the virtual address which will decide where inside the specified
+ *  tag memory object will be accessed.
+ */
+#define CACHE_L1_CACHE_VADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_VADDR_M  (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S)
+#define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_VADDR_S  0
+
+/** CACHE_L1_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x268)
+/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 616;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
+#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_L2_CACHE_CTRL_REG register
+ *  L2 Cache(L2-Cache) control register
+ */
+#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x270)
+/** CACHE_L2_CACHE_SHUT_DMA : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L2_CACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L2_CACHE_SHUT_DMA_M  (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S)
+#define CACHE_L2_CACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L2_CACHE_SHUT_DMA_S  4
+
+/** CACHE_L2_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x274)
+/** CACHE_BYPASS_L2_CACHE_EN : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L2_CACHE_EN    (BIT(5))
+#define CACHE_BYPASS_L2_CACHE_EN_M  (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S)
+#define CACHE_BYPASS_L2_CACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L2_CACHE_EN_S  5
+
+/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register
+ *  L2 Cache CacheSize mode configure register
+ */
+#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x278)
+/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L2_CACHE_CACHESIZE_256_M  (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S)
+#define CACHE_L2_CACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256_S  0
+/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L2_CACHE_CACHESIZE_512_M  (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S)
+#define CACHE_L2_CACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512_S  1
+/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L2_CACHE_CACHESIZE_1K_M  (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1K_S  2
+/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L2_CACHE_CACHESIZE_2K_M  (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S)
+#define CACHE_L2_CACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_2K_S  3
+/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L2_CACHE_CACHESIZE_4K_M  (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S)
+#define CACHE_L2_CACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_4K_S  4
+/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L2_CACHE_CACHESIZE_8K_M  (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S)
+#define CACHE_L2_CACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_8K_S  5
+/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L2_CACHE_CACHESIZE_16K_M  (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S)
+#define CACHE_L2_CACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_16K_S  6
+/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L2_CACHE_CACHESIZE_32K_M  (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S)
+#define CACHE_L2_CACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_32K_S  7
+/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L2_CACHE_CACHESIZE_64K_M  (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S)
+#define CACHE_L2_CACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_64K_S  8
+/** CACHE_L2_CACHE_CACHESIZE_128K : R/W; bitpos: [9]; default: 1;
+ *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L2_CACHE_CACHESIZE_128K_M  (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S)
+#define CACHE_L2_CACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_128K_S  9
+/** CACHE_L2_CACHE_CACHESIZE_256K : R/W; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L2_CACHE_CACHESIZE_256K_M  (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S)
+#define CACHE_L2_CACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256K_S  10
+/** CACHE_L2_CACHE_CACHESIZE_512K : R/W; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L2_CACHE_CACHESIZE_512K_M  (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S)
+#define CACHE_L2_CACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512K_S  11
+/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L2_CACHE_CACHESIZE_1024K_M  (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register
+ *  L2 Cache BlockSize mode configure register
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x27c)
+/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L2_CACHE_BLOCKSIZE_8_M  (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_8_S  0
+/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L2_CACHE_BLOCKSIZE_16_M  (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_16_S  1
+/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L2_CACHE_BLOCKSIZE_32_M  (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_32_S  2
+/** CACHE_L2_CACHE_BLOCKSIZE_64 : R/W; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L2_CACHE_BLOCKSIZE_64_M  (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_64_S  3
+/** CACHE_L2_CACHE_BLOCKSIZE_128 : R/W; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L2_CACHE_BLOCKSIZE_128_M  (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_128_S  4
+/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L2_CACHE_BLOCKSIZE_256_M  (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x280)
+/** CACHE_L2_CACHE_WRAP : R/W; bitpos: [5]; default: 0;
+ *  Set this bit as 1 to enable L2-Cache wrap around mode.
+ */
+#define CACHE_L2_CACHE_WRAP    (BIT(5))
+#define CACHE_L2_CACHE_WRAP_M  (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S)
+#define CACHE_L2_CACHE_WRAP_V  0x00000001U
+#define CACHE_L2_CACHE_WRAP_S  5
+
+/** CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG register
+ *  Cache tag memory power control register
+ */
+#define CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x284)
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S  20
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [21]; default: 0;
+ *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S  21
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [22]; default: 1;
+ *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU    (BIT(22))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG register
+ *  Cache data memory power control register
+ */
+#define CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x288)
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S  20
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [21]; default: 0;
+ *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S  21
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [22]; default: 1;
+ *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU    (BIT(22))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S  22
+
+/** CACHE_L2_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28c)
+/** CACHE_L2_CACHE_FREEZE_EN : R/W; bitpos: [20]; default: 0;
+ *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L2_CACHE_FREEZE_EN    (BIT(20))
+#define CACHE_L2_CACHE_FREEZE_EN_M  (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S)
+#define CACHE_L2_CACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_EN_S  20
+/** CACHE_L2_CACHE_FREEZE_MODE : R/W; bitpos: [21]; default: 0;
+ *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L2_CACHE_FREEZE_MODE    (BIT(21))
+#define CACHE_L2_CACHE_FREEZE_MODE_M  (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S)
+#define CACHE_L2_CACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_MODE_S  21
+/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_FREEZE_DONE    (BIT(22))
+#define CACHE_L2_CACHE_FREEZE_DONE_M  (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S)
+#define CACHE_L2_CACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_DONE_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x290)
+/** CACHE_L2_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M  (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [21]; default: 1;
+ *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M  (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x294)
+/** CACHE_L2_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M  (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [21]; default: 1;
+ *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M  (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_PRELOCK_CONF_REG register
+ *  L2 Cache prelock configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x298)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L2_CACHE_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l2 cache prelock.
+ */
+#define CACHE_L2_CACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_M  (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S)
+#define CACHE_L2_CACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L2 Cache prelock section0 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x29c)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L2-Cache, which should be used together with
+ *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L2 Cache prelock section1 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2a0)
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L2-Cache, which should be used together with
+ *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register
+ *  L2 Cache prelock section size configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x2a4)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [15:0]; default: 65535;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [31:16]; default: 65535;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register
+ *  L2 Cache preload-operation control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a8)
+/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_PRELOAD_ENA_M  (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S)
+#define CACHE_L2_CACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ENA_S  0
+/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_PRELOAD_DONE_M  (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S)
+#define CACHE_L2_CACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_DONE_S  1
+/** CACHE_L2_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_PRELOAD_ORDER_M  (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S)
+#define CACHE_L2_CACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ORDER_S  2
+/** CACHE_L2_CACHE_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l2 cache preload.
+ */
+#define CACHE_L2_CACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_M  (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S)
+#define CACHE_L2_CACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_S  3
+/** CACHE_L2_CACHE_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to configure the mode of l2 cache preload, 0: load data from next
+ *  level memory, 1: not load data from next level memory.
+ */
+#define CACHE_L2_CACHE_PRELOAD_MODE    (BIT(7))
+#define CACHE_L2_CACHE_PRELOAD_MODE_M  (CACHE_L2_CACHE_PRELOAD_MODE_V << CACHE_L2_CACHE_PRELOAD_MODE_S)
+#define CACHE_L2_CACHE_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_MODE_S  7
+
+/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register
+ *  L2 Cache preload address configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2ac)
+/** CACHE_L2_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+ *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_M  (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S)
+#define CACHE_L2_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register
+ *  L2 Cache preload size configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2b0)
+/** CACHE_L2_CACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_M  (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S)
+#define CACHE_L2_CACHE_PRELOAD_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register
+ *  L2 Cache autoload-operation control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2b4)
+/** CACHE_L2_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_M  (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L2_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M  (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+ *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : R/W; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L2_CACHE_AUTOLOAD_RGID : R/W; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l2 cache autoload.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_M  (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S)
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L2 Cache autoload section 0 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L2 Cache autoload section 0 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L2 Cache autoload section 1 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L2 Cache autoload section 1 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L2 Cache autoload section 2 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the third section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L2 Cache autoload section 2 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L2 Cache autoload section 3 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2d0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the fourth section
+ *  for autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L2 Cache autoload section 3 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2d4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d8)
+/** CACHE_L2_IBUS0_OVF_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ENA_M  (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ENA_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ENA_M  (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ENA_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ENA_M  (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ENA_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ENA_M  (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ENA_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ENA_M  (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ENA_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ENA_M  (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ENA_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ENA_M  (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ENA_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ENA_M  (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ENA_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2dc)
+/** CACHE_L2_IBUS0_OVF_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_CLR    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_CLR_M  (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_CLR_S  8
+/** CACHE_L2_IBUS1_OVF_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_CLR    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_CLR_M  (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_CLR_S  9
+/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_CLR    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_CLR_M  (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_CLR_S  10
+/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_CLR    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_CLR_M  (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_CLR_S  11
+/** CACHE_L2_DBUS0_OVF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_CLR    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_CLR_M  (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_CLR_S  12
+/** CACHE_L2_DBUS1_OVF_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_CLR    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_CLR_M  (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_CLR_S  13
+/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_CLR    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_CLR_M  (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_CLR_S  14
+/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_CLR    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_CLR_M  (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_CLR_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2e0)
+/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-ICache0.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_RAW    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_RAW_M  (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_RAW_S  8
+/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-ICache1.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_RAW    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_RAW_M  (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_RAW_S  9
+/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-ICache2.
+ */
+#define CACHE_L2_IBUS2_OVF_INT_RAW    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_RAW_M  (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_RAW_S  10
+/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-ICache3.
+ */
+#define CACHE_L2_IBUS3_OVF_INT_RAW    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_RAW_M  (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_RAW_S  11
+/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_RAW    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_RAW_M  (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_RAW_S  12
+/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_RAW    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_RAW_M  (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_RAW_S  13
+/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS2_OVF_INT_RAW    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_RAW_M  (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_RAW_S  14
+/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS3_OVF_INT_RAW    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_RAW_M  (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_RAW_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2e4)
+/** CACHE_L2_IBUS0_OVF_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ST    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ST_M  (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S)
+#define CACHE_L2_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ST_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ST    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ST_M  (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S)
+#define CACHE_L2_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ST_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ST    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ST_M  (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S)
+#define CACHE_L2_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ST_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ST    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ST_M  (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S)
+#define CACHE_L2_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ST_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ST    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ST_M  (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S)
+#define CACHE_L2_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ST_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ST    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ST_M  (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S)
+#define CACHE_L2_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ST_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ST    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ST_M  (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S)
+#define CACHE_L2_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ST_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ST    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ST_M  (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S)
+#define CACHE_L2_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ST_S  15
+
+/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e8)
+/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
+ *  not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2ec)
+/** CACHE_L2_CACHE_FAIL_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+ *  l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ENA_M  (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S)
+#define CACHE_L2_CACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ENA_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2f0)
+/** CACHE_L2_CACHE_FAIL_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+ *  cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_CLR_M  (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S)
+#define CACHE_L2_CACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_CLR_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2f4)
+/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_RAW_M  (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S)
+#define CACHE_L2_CACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_RAW_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f8)
+/** CACHE_L2_CACHE_FAIL_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+ *  to l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ST_M  (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S)
+#define CACHE_L2_CACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ST_S  5
+
+/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2fc)
+/** CACHE_L2_IBUS0_CNT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_CNT_ENA_M  (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S)
+#define CACHE_L2_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_ENA_S  8
+/** CACHE_L2_IBUS1_CNT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_CNT_ENA_M  (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S)
+#define CACHE_L2_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_ENA_S  9
+/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_CNT_ENA_M  (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S)
+#define CACHE_L2_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_ENA_S  10
+/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_CNT_ENA_M  (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S)
+#define CACHE_L2_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_ENA_S  11
+/** CACHE_L2_DBUS0_CNT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The bit is used to enable dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_CNT_ENA_M  (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S)
+#define CACHE_L2_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_ENA_S  12
+/** CACHE_L2_DBUS1_CNT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_CNT_ENA_M  (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S)
+#define CACHE_L2_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_ENA_S  13
+/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_CNT_ENA_M  (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S)
+#define CACHE_L2_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_ENA_S  14
+/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_CNT_ENA_M  (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S)
+#define CACHE_L2_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_ENA_S  15
+/** CACHE_L2_IBUS0_CNT_CLR : WT; bitpos: [24]; default: 0;
+ *  The bit is used to clear ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_CLR    (BIT(24))
+#define CACHE_L2_IBUS0_CNT_CLR_M  (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S)
+#define CACHE_L2_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_CLR_S  24
+/** CACHE_L2_IBUS1_CNT_CLR : WT; bitpos: [25]; default: 0;
+ *  The bit is used to clear ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_CLR    (BIT(25))
+#define CACHE_L2_IBUS1_CNT_CLR_M  (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S)
+#define CACHE_L2_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_CLR_S  25
+/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_CLR    (BIT(26))
+#define CACHE_L2_IBUS2_CNT_CLR_M  (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S)
+#define CACHE_L2_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_CLR_S  26
+/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_CLR    (BIT(27))
+#define CACHE_L2_IBUS3_CNT_CLR_M  (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S)
+#define CACHE_L2_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_CLR_S  27
+/** CACHE_L2_DBUS0_CNT_CLR : WT; bitpos: [28]; default: 0;
+ *  The bit is used to clear dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_CLR    (BIT(28))
+#define CACHE_L2_DBUS0_CNT_CLR_M  (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S)
+#define CACHE_L2_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_CLR_S  28
+/** CACHE_L2_DBUS1_CNT_CLR : WT; bitpos: [29]; default: 0;
+ *  The bit is used to clear dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_CLR    (BIT(29))
+#define CACHE_L2_DBUS1_CNT_CLR_M  (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S)
+#define CACHE_L2_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_CLR_S  29
+/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_CLR    (BIT(30))
+#define CACHE_L2_DBUS2_CNT_CLR_M  (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S)
+#define CACHE_L2_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_CLR_S  30
+/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_CLR    (BIT(31))
+#define CACHE_L2_DBUS3_CNT_CLR_M  (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S)
+#define CACHE_L2_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_CLR_S  31
+
+/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x300)
+/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_M  (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S)
+#define CACHE_L2_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x304)
+/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_M  (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S)
+#define CACHE_L2_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x308)
+/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache0 accesses
+ *  L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_M  (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x30c)
+/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x310)
+/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_M  (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S)
+#define CACHE_L2_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x314)
+/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_M  (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S)
+#define CACHE_L2_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x318)
+/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache1 accesses
+ *  L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_M  (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x31c)
+/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x320)
+/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_M  (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S)
+#define CACHE_L2_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x324)
+/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_M  (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S)
+#define CACHE_L2_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x328)
+/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache2 accesses
+ *  L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_M  (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x32c)
+/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x330)
+/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_M  (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S)
+#define CACHE_L2_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x334)
+/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_M  (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S)
+#define CACHE_L2_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x338)
+/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache3 accesses
+ *  L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_M  (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x33c)
+/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x340)
+/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_M  (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S)
+#define CACHE_L2_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x344)
+/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_M  (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S)
+#define CACHE_L2_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x348)
+/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_M  (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x34c)
+/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus0 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x350)
+/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x354)
+/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_M  (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S)
+#define CACHE_L2_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x358)
+/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_M  (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S)
+#define CACHE_L2_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x35c)
+/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_M  (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x360)
+/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus1 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x364)
+/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x368)
+/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_M  (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S)
+#define CACHE_L2_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x36c)
+/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_M  (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S)
+#define CACHE_L2_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x370)
+/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_M  (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x374)
+/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus2 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x378)
+/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x37c)
+/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_M  (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S)
+#define CACHE_L2_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x380)
+/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_M  (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S)
+#define CACHE_L2_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x384)
+/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_M  (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x388)
+/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus3 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x38c)
+/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x390)
+/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_M  (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S)
+#define CACHE_L2_CACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_S  0
+/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+ *  due to cache accessing L1-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_M  (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S)
+#define CACHE_L2_CACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_S  16
+
+/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register
+ *  L2-Cache Access Fail Address information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x394)
+/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_M  (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S)
+#define CACHE_L2_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_S  0
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x398)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x39c)
+/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+ *  is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x3a0)
+/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+ *  done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x3a4)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+ *  preload-operation is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M  (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M  (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a8)
+/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L2-Cache.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_M  (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S)
+#define CACHE_L2_CACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_S  10
+
+/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac)
+/** CACHE_L2_CACHE_SYNC_RST : R/W; bitpos: [5]; default: 0;
+ *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L2_CACHE_SYNC_RST    (BIT(5))
+#define CACHE_L2_CACHE_SYNC_RST_M  (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S)
+#define CACHE_L2_CACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L2_CACHE_SYNC_RST_S  5
+
+/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3b0)
+/** CACHE_L2_CACHE_PLD_RST : R/W; bitpos: [5]; default: 0;
+ *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_RST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_RST_M  (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S)
+#define CACHE_L2_CACHE_PLD_RST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_RST_S  5
+
+/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4)
+/** CACHE_L2_CACHE_ALD_BUF_CLR : R/W; bitpos: [5]; default: 0;
+ *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+ *  autoload will not work in L2-Cache. This bit should not be active when autoload
+ *  works in L2-Cache.
+ */
+#define CACHE_L2_CACHE_ALD_BUF_CLR    (BIT(5))
+#define CACHE_L2_CACHE_ALD_BUF_CLR_M  (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S)
+#define CACHE_L2_CACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_ALD_BUF_CLR_S  5
+
+/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b8)
+/** CACHE_L2_CACHE_UNALLOC_CLR : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l2 icache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
+#define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
+#define CACHE_L2_CACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_UNALLOC_CLR_S  5
+
+/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register
+ *  L2 cache access attribute control register
+ */
+#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3bc)
+/** CACHE_L2_CACHE_ACCESS_FORCE_CC : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+ *  non-cacheable.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC    (BIT(0))
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M  (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S  0
+/** CACHE_L2_CACHE_ACCESS_FORCE_WB : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+ *  write-through.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB    (BIT(1))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M  (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S  1
+/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  write-miss-allocate and write-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA    (BIT(2))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S  2
+/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : R/W; bitpos: [3]; default: 1;
+ *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  read-miss-allocate and read-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA    (BIT(3))
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S  3
+
+/** CACHE_L2_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3c0)
+/** CACHE_L2_CACHE_TAG_OBJECT : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_TAG_OBJECT    (BIT(5))
+#define CACHE_L2_CACHE_TAG_OBJECT_M  (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S)
+#define CACHE_L2_CACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_OBJECT_S  5
+/** CACHE_L2_CACHE_MEM_OBJECT : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_MEM_OBJECT    (BIT(11))
+#define CACHE_L2_CACHE_MEM_OBJECT_M  (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S)
+#define CACHE_L2_CACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_MEM_OBJECT_S  11
+
+/** CACHE_L2_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3c4)
+/** CACHE_L2_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_M  (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S)
+#define CACHE_L2_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L2_CACHE_VADDR_REG register
+ *  Cache Vaddr register
+ */
+#define CACHE_L2_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x3c8)
+/** CACHE_L2_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the virtual address which will decide where inside the specified
+ *  tag memory object will be accessed.
+ */
+#define CACHE_L2_CACHE_VADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_VADDR_M  (CACHE_L2_CACHE_VADDR_V << CACHE_L2_CACHE_VADDR_S)
+#define CACHE_L2_CACHE_VADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_VADDR_S  0
+
+/** CACHE_L2_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3cc)
+/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 972;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_M  (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S)
+#define CACHE_L2_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3d4)
+/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define CACHE_CLK_EN    (BIT(0))
+#define CACHE_CLK_EN_M  (CACHE_CLK_EN_V << CACHE_CLK_EN_S)
+#define CACHE_CLK_EN_V  0x00000001U
+#define CACHE_CLK_EN_S  0
+
+/** CACHE_DATE_REG register
+ *  Version control register
+ */
+#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
+/** CACHE_DATE : R/W; bitpos: [27:0]; default: 38810192;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define CACHE_DATE    0x0FFFFFFFU
+#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
+#define CACHE_DATE_V  0x0FFFFFFFU
+#define CACHE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/cache_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/cache_struct.h
new file mode 100644
index 0000000000..771b04eeee
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/cache_struct.h
@@ -0,0 +1,5840 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of l1_icache_ctrl register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+typedef union {
+    struct {
+        /** l1_icache_shut_ibus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus0:1;
+        /** l1_icache_shut_ibus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus1:1;
+        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus2:1;
+        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus3:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_l1_icache_ctrl_reg_t;
+
+/** Type of l1_dcache_ctrl register
+ *  L1 data Cache(L1-DCache) control register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_shut_dbus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable
+         */
+        uint32_t l1_dcache_shut_dbus0:1;
+        /** l1_dcache_shut_dbus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable
+         */
+        uint32_t l1_dcache_shut_dbus1:1;
+        /** l1_dcache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dcache_shut_dbus2:1;
+        /** l1_dcache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dcache_shut_dbus3:1;
+        /** l1_dcache_shut_dma : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable
+         */
+        uint32_t l1_dcache_shut_dma:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_dcache_ctrl_reg_t;
+
+/** Type of l2_cache_ctrl register
+ *  L2 Cache(L2-Cache) control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** l2_cache_shut_dma : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+         */
+        uint32_t l2_cache_shut_dma:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l2_cache_ctrl_reg_t;
+
+
+/** Group: Bypass Cache Control and configuration registers */
+/** Type of l1_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        /** bypass_l1_icache0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache0_en:1;
+        /** bypass_l1_icache1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache1_en:1;
+        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache2_en:1;
+        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache3_en:1;
+        /** bypass_l1_dcache_en : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_dcache_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_bypass_cache_conf_reg_t;
+
+/** Type of l2_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** bypass_l2_cache_en : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l2_cache_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_bypass_cache_conf_reg_t;
+
+
+/** Group: Cache Atomic Control and configuration registers */
+/** Type of l1_cache_atomic_conf register
+ *  L1 Cache atomic feature configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_atomic_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable atomic feature on L1-DCache when multiple cores access
+         *  L1-DCache.  1: disable, 1: enable.
+         */
+        uint32_t l1_dcache_atomic_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_l1_cache_atomic_conf_reg_t;
+
+
+/** Group: Cache Mode Control and configuration registers */
+/** Type of l1_icache_cachesize_conf register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256:1;
+        /** l1_icache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512:1;
+        /** l1_icache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1k:1;
+        /** l1_icache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2k:1;
+        /** l1_icache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4k:1;
+        /** l1_icache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_8k:1;
+        /** l1_icache_cachesize_16k : HRO; bitpos: [6]; default: 1;
+         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_16k:1;
+        /** l1_icache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_32k:1;
+        /** l1_icache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_64k:1;
+        /** l1_icache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_128k:1;
+        /** l1_icache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256k:1;
+        /** l1_icache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512k:1;
+        /** l1_icache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_icache_cachesize_conf_reg_t;
+
+/** Type of l1_icache_blocksize_conf register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_8:1;
+        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_16:1;
+        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_32:1;
+        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_64:1;
+        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_128:1;
+        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache_blocksize_conf_reg_t;
+
+/** Type of l1_dcache_cachesize_conf register
+ *  L1 data Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_256:1;
+        /** l1_dcache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_512:1;
+        /** l1_dcache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_1k:1;
+        /** l1_dcache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_2k:1;
+        /** l1_dcache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_4k:1;
+        /** l1_dcache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_8k:1;
+        /** l1_dcache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_16k:1;
+        /** l1_dcache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_32k:1;
+        /** l1_dcache_cachesize_64k : HRO; bitpos: [8]; default: 1;
+         *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_64k:1;
+        /** l1_dcache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_128k:1;
+        /** l1_dcache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_256k:1;
+        /** l1_dcache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_512k:1;
+        /** l1_dcache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_dcache_cachesize_conf_reg_t;
+
+/** Type of l1_dcache_blocksize_conf register
+ *  L1 data Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_8:1;
+        /** l1_dcache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_16:1;
+        /** l1_dcache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_32:1;
+        /** l1_dcache_blocksize_64 : HRO; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_64:1;
+        /** l1_dcache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_128:1;
+        /** l1_dcache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_dcache_blocksize_conf_reg_t;
+
+/** Type of l2_cache_cachesize_conf register
+ *  L2 Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256:1;
+        /** l2_cache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512:1;
+        /** l2_cache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1k:1;
+        /** l2_cache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2k:1;
+        /** l2_cache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4k:1;
+        /** l2_cache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_8k:1;
+        /** l2_cache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_16k:1;
+        /** l2_cache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_32k:1;
+        /** l2_cache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_64k:1;
+        /** l2_cache_cachesize_128k : R/W; bitpos: [9]; default: 1;
+         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_128k:1;
+        /** l2_cache_cachesize_256k : R/W; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256k:1;
+        /** l2_cache_cachesize_512k : R/W; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512k:1;
+        /** l2_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_cachesize_conf_reg_t;
+
+/** Type of l2_cache_blocksize_conf register
+ *  L2 Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_8:1;
+        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_16:1;
+        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_32:1;
+        /** l2_cache_blocksize_64 : R/W; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_64:1;
+        /** l2_cache_blocksize_128 : R/W; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_128:1;
+        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_blocksize_conf_reg_t;
+
+
+/** Group: Wrap Mode Control and configuration registers */
+/** Type of l1_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_wrap : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+         */
+        uint32_t l1_icache0_wrap:1;
+        /** l1_icache1_wrap : R/W; bitpos: [1]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+         */
+        uint32_t l1_icache1_wrap:1;
+        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_wrap:1;
+        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_wrap:1;
+        /** l1_dcache_wrap : R/W; bitpos: [4]; default: 0;
+         *  Set this bit as 1 to enable L1-DCache wrap around mode.
+         */
+        uint32_t l1_dcache_wrap:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_wrap_around_ctrl_reg_t;
+
+/** Type of l2_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_wrap : R/W; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to enable L2-Cache wrap around mode.
+         */
+        uint32_t l2_cache_wrap:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_wrap_around_ctrl_reg_t;
+
+
+/** Group: Cache Tag Memory Power Control registers */
+/** Type of l1_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_force_on : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_tag_mem_force_on:1;
+        /** l1_icache0_tag_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_tag_mem_force_pd:1;
+        /** l1_icache0_tag_mem_force_pu : R/W; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_tag_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_tag_mem_force_on : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_tag_mem_force_on:1;
+        /** l1_icache1_tag_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_tag_mem_force_pd:1;
+        /** l1_icache1_tag_mem_force_pu : R/W; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_tag_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_on:1;
+        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pd:1;
+        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_on:1;
+        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pd:1;
+        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_dcache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-DCache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_dcache_tag_mem_force_on:1;
+        /** l1_dcache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_dcache_tag_mem_force_pd:1;
+        /** l1_dcache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_dcache_tag_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_tag_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_force_on : R/W; bitpos: [20]; default: 1;
+         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_tag_mem_force_on:1;
+        /** l2_cache_tag_mem_force_pd : R/W; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l2_cache_tag_mem_force_pd:1;
+        /** l2_cache_tag_mem_force_pu : R/W; bitpos: [22]; default: 1;
+         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_tag_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_tag_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Power Control registers */
+/** Type of l1_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_force_on : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_data_mem_force_on:1;
+        /** l1_icache0_data_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_data_mem_force_pd:1;
+        /** l1_icache0_data_mem_force_pu : R/W; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_data_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_data_mem_force_on : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_data_mem_force_on:1;
+        /** l1_icache1_data_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_data_mem_force_pd:1;
+        /** l1_icache1_data_mem_force_pu : R/W; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_data_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_on:1;
+        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pd:1;
+        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_on:1;
+        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pd:1;
+        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_dcache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-DCache data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_dcache_data_mem_force_on:1;
+        /** l1_dcache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_dcache_data_mem_force_pd:1;
+        /** l1_dcache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_dcache_data_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_data_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_force_on : R/W; bitpos: [20]; default: 1;
+         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_data_mem_force_on:1;
+        /** l2_cache_data_mem_force_pd : R/W; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l2_cache_data_mem_force_pd:1;
+        /** l2_cache_data_mem_force_pu : R/W; bitpos: [22]; default: 1;
+         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_data_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_data_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Freeze Control registers */
+/** Type of l1_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_freeze_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache0_freeze_en:1;
+        /** l1_icache0_freeze_mode : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache0_freeze_mode:1;
+        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_freeze_done:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_freeze_en : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache1_freeze_en:1;
+        /** l1_icache1_freeze_mode : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache1_freeze_mode:1;
+        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_freeze_done:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_en:1;
+        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_mode:1;
+        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_done:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_en:1;
+        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_mode:1;
+        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_done:1;
+        uint32_t reserved_15:1;
+        /** l1_dcache_freeze_en : R/W; bitpos: [16]; default: 0;
+         *  The bit is used to enable freeze operation on L1-DCache. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_dcache_freeze_en:1;
+        /** l1_dcache_freeze_mode : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_dcache_freeze_mode:1;
+        /** l1_dcache_freeze_done : RO; bitpos: [18]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-DCache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_dcache_freeze_done:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_freeze_ctrl_reg_t;
+
+/** Type of l2_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_freeze_en : R/W; bitpos: [20]; default: 0;
+         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l2_cache_freeze_en:1;
+        /** l2_cache_freeze_mode : R/W; bitpos: [21]; default: 0;
+         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l2_cache_freeze_mode:1;
+        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_freeze_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_freeze_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Access Control and Configuration registers */
+/** Type of l1_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_rd_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_data_mem_rd_en:1;
+        /** l1_icache0_data_mem_wr_en : R/W; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache0_data_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_data_mem_rd_en : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_data_mem_rd_en:1;
+        /** l1_icache1_data_mem_wr_en : R/W; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache1_data_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_rd_en:1;
+        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_rd_en:1;
+        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_dcache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_dcache_data_mem_rd_en:1;
+        /** l1_dcache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_dcache_data_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_data_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_rd_en : R/W; bitpos: [20]; default: 1;
+         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_rd_en:1;
+        /** l2_cache_data_mem_wr_en : R/W; bitpos: [21]; default: 1;
+         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_data_mem_acs_conf_reg_t;
+
+
+/** Group: Cache Tag Memory Access Control and Configuration registers */
+/** Type of l1_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_rd_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_rd_en:1;
+        /** l1_icache0_tag_mem_wr_en : R/W; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_tag_mem_rd_en : R/W; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_rd_en:1;
+        /** l1_icache1_tag_mem_wr_en : R/W; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_rd_en:1;
+        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_rd_en:1;
+        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_dcache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_dcache_tag_mem_rd_en:1;
+        /** l1_dcache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_dcache_tag_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_tag_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_rd_en : R/W; bitpos: [20]; default: 1;
+         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_rd_en:1;
+        /** l2_cache_tag_mem_wr_en : R/W; bitpos: [21]; default: 1;
+         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_tag_mem_acs_conf_reg_t;
+
+
+/** Group: Prelock Control and configuration registers */
+/** Type of l1_icache0_prelock_conf register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct0_en:1;
+        /** l1_icache0_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct1_en:1;
+        /** l1_icache0_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 prelock.
+         */
+        uint32_t l1_icache0_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_conf_reg_t;
+
+/** Type of l1_icache0_prelock_sct0_addr register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct1_addr register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct_size register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache0_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct_size_reg_t;
+
+/** Type of l1_icache1_prelock_conf register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct0_en:1;
+        /** l1_icache1_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct1_en:1;
+        /** l1_icache1_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 prelock.
+         */
+        uint32_t l1_icache1_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_conf_reg_t;
+
+/** Type of l1_icache1_prelock_sct0_addr register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct1_addr register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct_size register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache1_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct_size_reg_t;
+
+/** Type of l1_icache2_prelock_conf register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct0_en:1;
+        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct1_en:1;
+        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 prelock.
+         */
+        uint32_t l1_icache2_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_conf_reg_t;
+
+/** Type of l1_icache2_prelock_sct0_addr register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct1_addr register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct_size register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct_size_reg_t;
+
+/** Type of l1_icache3_prelock_conf register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct0_en:1;
+        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct1_en:1;
+        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 prelock.
+         */
+        uint32_t l1_icache3_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_conf_reg_t;
+
+/** Type of l1_icache3_prelock_sct0_addr register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct1_addr register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct_size register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct_size_reg_t;
+
+/** Type of l1_dcache_prelock_conf register
+ *  L1 data Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-DCache.
+         */
+        uint32_t l1_dcache_prelock_sct0_en:1;
+        /** l1_dcache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-DCache.
+         */
+        uint32_t l1_dcache_prelock_sct1_en:1;
+        /** l1_dcache_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 dcache prelock.
+         */
+        uint32_t l1_dcache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_conf_reg_t;
+
+/** Type of l1_dcache_prelock_sct0_addr register
+ *  L1 data Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-DCache, which should be used together with
+         *  L1_DCACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_dcache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct0_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct1_addr register
+ *  L1 data Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-DCache, which should be used together with
+         *  L1_DCACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_dcache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct1_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct_size register
+ *  L1 data Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_dcache_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_dcache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_dcache_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct_size_reg_t;
+
+/** Type of l2_cache_prelock_conf register
+ *  L2 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct0_en:1;
+        /** l2_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct1_en:1;
+        /** l2_cache_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l2 cache prelock.
+         */
+        uint32_t l2_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_conf_reg_t;
+
+/** Type of l2_cache_prelock_sct0_addr register
+ *  L2 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct1_addr register
+ *  L2 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct1_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct_size register
+ *  L2 Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_size : R/W; bitpos: [15:0]; default: 65535;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct0_size:16;
+        /** l2_cache_prelock_sct1_size : R/W; bitpos: [31:16]; default: 65535;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct1_size:16;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct_size_reg_t;
+
+
+/** Group: Lock Control and configuration registers */
+/** Type of lock_ctrl register
+ *  Lock-class (manual lock) operation control register
+ */
+typedef union {
+    struct {
+        /** lock_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+         *  operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive,
+         *  that is, those bits can not be set to 1 at the same time. (2) lock operation can be
+         *  applied on LL1-ICache, L1-DCache and L2-Cache.
+         */
+        uint32_t lock_ena:1;
+        /** unlock_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable unlock operation. It will be cleared by hardware after
+         *  unlock operation done. Note that (1) this bit and lock_ena bit are mutually
+         *  exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock
+         *  operation can be applied on L1-ICache, L1-DCache and L2-Cache.
+         */
+        uint32_t unlock_ena:1;
+        /** lock_done : RO; bitpos: [2]; default: 1;
+         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+         *  not finished. 1: finished.
+         */
+        uint32_t lock_done:1;
+        /** lock_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of cache lock/unlock.
+         */
+        uint32_t lock_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_lock_ctrl_reg_t;
+
+/** Type of lock_map register
+ *  Lock (manual lock) map configure register
+ */
+typedef union {
+    struct {
+        /** lock_map : R/W; bitpos: [5:0]; default: 0;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]:
+         *  L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+         */
+        uint32_t lock_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_lock_map_reg_t;
+
+/** Type of lock_addr register
+ *  Lock (manual lock) address configure register
+ */
+typedef union {
+    struct {
+        /** lock_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the lock/unlock
+         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+         */
+        uint32_t lock_addr:32;
+    };
+    uint32_t val;
+} cache_lock_addr_reg_t;
+
+/** Type of lock_size register
+ *  Lock (manual lock) size configure register
+ */
+typedef union {
+    struct {
+        /** lock_size : R/W; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the lock/unlock operation, which
+         *  should be used together with CACHE_LOCK_ADDR_REG
+         */
+        uint32_t lock_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_lock_size_reg_t;
+
+
+/** Group: Sync Control and configuration registers */
+/** Type of sync_ctrl register
+ *  Sync-class operation control register
+ */
+typedef union {
+    struct {
+        /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
+         *  The bit is used to enable invalidate operation. It will be cleared by hardware
+         *  after invalidate operation done. Note that this bit and the other sync-bits
+         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t invalidate_ena:1;
+        /** clean_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable clean operation. It will be cleared by hardware after
+         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+         *  bits can not be set to 1 at the same time.
+         */
+        uint32_t clean_ena:1;
+        /** writeback_ena : R/W/SC; bitpos: [2]; default: 0;
+         *  The bit is used to enable writeback operation. It will be cleared by hardware after
+         *  writeback operation done. Note that this bit and the other sync-bits
+         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t writeback_ena:1;
+        /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
+         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+         *  hardware after writeback-invalidate operation done. Note that this bit and the
+         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+         *  that is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t writeback_invalidate_ena:1;
+        /** sync_done : RO; bitpos: [4]; default: 0;
+         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+         */
+        uint32_t sync_done:1;
+        /** sync_rgid : R/W; bitpos: [8:5]; default: 0;
+         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+         *  writeback, writeback_invalidate)
+         */
+        uint32_t sync_rgid:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} cache_sync_ctrl_reg_t;
+
+/** Type of sync_map register
+ *  Sync map configure register
+ */
+typedef union {
+    struct {
+        /** sync_map : R/W; bitpos: [5:0]; default: 31;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]:
+         *  L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+         */
+        uint32_t sync_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_sync_map_reg_t;
+
+/** Type of sync_addr register
+ *  Sync address configure register
+ */
+typedef union {
+    struct {
+        /** sync_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the sync operation,
+         *  which should be used together with CACHE_SYNC_SIZE_REG
+         */
+        uint32_t sync_addr:32;
+    };
+    uint32_t val;
+} cache_sync_addr_reg_t;
+
+/** Type of sync_size register
+ *  Sync size configure register
+ */
+typedef union {
+    struct {
+        /** sync_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the sync operation, which should be
+         *  used together with CACHE_SYNC_ADDR_REG
+         */
+        uint32_t sync_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_sync_size_reg_t;
+
+
+/** Group: Preload Control and configuration registers */
+/** Type of l1_icache0_preload_ctrl register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache0_preload_ena:1;
+        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache0_preload_done:1;
+        /** l1_icache0_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache0_preload_order:1;
+        /** l1_icache0_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 preload.
+         */
+        uint32_t l1_icache0_preload_rgid:4;
+        /** l1_icache0_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 icache0 preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_icache0_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_ctrl_reg_t;
+
+/** Type of l1_icache0_preload_addr register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache0_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_addr_reg_t;
+
+/** Type of l1_icache0_preload_size register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache0_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_size_reg_t;
+
+/** Type of l1_icache1_preload_ctrl register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache1_preload_ena:1;
+        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache1_preload_done:1;
+        /** l1_icache1_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache1_preload_order:1;
+        /** l1_icache1_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 preload.
+         */
+        uint32_t l1_icache1_preload_rgid:4;
+        /** l1_icache1_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 icache1 preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_icache1_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_ctrl_reg_t;
+
+/** Type of l1_icache1_preload_addr register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache1_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_addr_reg_t;
+
+/** Type of l1_icache1_preload_size register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache1_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_size_reg_t;
+
+/** Type of l1_icache2_preload_ctrl register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache2_preload_ena:1;
+        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache2_preload_done:1;
+        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache2_preload_order:1;
+        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 preload.
+         */
+        uint32_t l1_icache2_preload_rgid:4;
+        /** l1_icache2_preload_mode : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 icache2 preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_icache2_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_ctrl_reg_t;
+
+/** Type of l1_icache2_preload_addr register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache2_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_addr_reg_t;
+
+/** Type of l1_icache2_preload_size register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache2_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_size_reg_t;
+
+/** Type of l1_icache3_preload_ctrl register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache3_preload_ena:1;
+        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache3_preload_done:1;
+        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache3_preload_order:1;
+        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 preload.
+         */
+        uint32_t l1_icache3_preload_rgid:4;
+        /** l1_icache3_preload_mode : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 icache3 preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_icache3_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_ctrl_reg_t;
+
+/** Type of l1_icache3_preload_addr register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache3_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_addr_reg_t;
+
+/** Type of l1_icache3_preload_size register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache3_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_size_reg_t;
+
+/** Type of l1_dcache_preload_ctrl register
+ *  L1 data Cache  preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-DCache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_dcache_preload_ena:1;
+        /** l1_dcache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_dcache_preload_done:1;
+        /** l1_dcache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_dcache_preload_order:1;
+        /** l1_dcache_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 dcache preload.
+         */
+        uint32_t l1_dcache_preload_rgid:4;
+        /** l1_dcache_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l1 dcache preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l1_dcache_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_ctrl_reg_t;
+
+/** Type of l1_dcache_preload_addr register
+ *  L1 data Cache  preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L1-DCache,
+         *  which should be used together with L1_DCACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_dcache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_addr_reg_t;
+
+/** Type of l1_dcache_preload_size register
+ *  L1 data Cache  preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_dcache_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_size_reg_t;
+
+/** Type of l2_cache_preload_ctrl register
+ *  L2 Cache preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l2_cache_preload_ena:1;
+        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l2_cache_preload_done:1;
+        /** l2_cache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l2_cache_preload_order:1;
+        /** l2_cache_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l2 cache preload.
+         */
+        uint32_t l2_cache_preload_rgid:4;
+        /** l2_cache_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to configure the mode of l2 cache preload, 0: load data from next
+         *  level memory, 1: not load data from next level memory.
+         */
+        uint32_t l2_cache_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_ctrl_reg_t;
+
+/** Type of l2_cache_preload_addr register
+ *  L2 Cache preload address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l2_cache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_addr_reg_t;
+
+/** Type of l2_cache_preload_size register
+ *  L2 Cache preload size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_size : R/W; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l2_cache_preload_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_size_reg_t;
+
+
+/** Group: Autoload Control and configuration registers */
+/** Type of l1_icache0_autoload_ctrl register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache0_autoload_ena:1;
+        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_autoload_done:1;
+        /** l1_icache0_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache0_autoload_order:1;
+        /** l1_icache0_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache0_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache0_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct0_ena:1;
+        /** l1_icache0_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct1_ena:1;
+        /** l1_icache0_autoload_rgid : R/W; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 autoload.
+         */
+        uint32_t l1_icache0_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_ctrl_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_addr register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_size register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_addr register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_size register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache1_autoload_ctrl register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache1_autoload_ena:1;
+        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_autoload_done:1;
+        /** l1_icache1_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache1_autoload_order:1;
+        /** l1_icache1_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache1_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache1_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct0_ena:1;
+        /** l1_icache1_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct1_ena:1;
+        /** l1_icache1_autoload_rgid : R/W; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 autoload.
+         */
+        uint32_t l1_icache1_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_ctrl_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_addr register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_size register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_addr register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_size register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache2_autoload_ctrl register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache2_autoload_ena:1;
+        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache2_autoload_done:1;
+        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache2_autoload_order:1;
+        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache2_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct0_ena:1;
+        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct1_ena:1;
+        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 autoload.
+         */
+        uint32_t l1_icache2_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_ctrl_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_addr register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_size register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_addr register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_size register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache3_autoload_ctrl register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache3_autoload_ena:1;
+        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache3_autoload_done:1;
+        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache3_autoload_order:1;
+        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache3_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct0_ena:1;
+        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct1_ena:1;
+        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 autoload.
+         */
+        uint32_t l1_icache3_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_ctrl_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_addr register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_size register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_addr register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_size register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_size_reg_t;
+
+/** Type of l1_dcache_autoload_ctrl register
+ *  L1 data Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-DCache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_dcache_autoload_ena:1;
+        /** l1_dcache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-DCache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_dcache_autoload_done:1;
+        /** l1_dcache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-DCache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_dcache_autoload_order:1;
+        /** l1_dcache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-DCache.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_dcache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_dcache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-DCache.
+         */
+        uint32_t l1_dcache_autoload_sct0_ena:1;
+        /** l1_dcache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-DCache.
+         */
+        uint32_t l1_dcache_autoload_sct1_ena:1;
+        /** l1_dcache_autoload_sct2_ena : R/W; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L1-DCache.
+         */
+        uint32_t l1_dcache_autoload_sct2_ena:1;
+        /** l1_dcache_autoload_sct3_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L1-DCache.
+         */
+        uint32_t l1_dcache_autoload_sct3_ena:1;
+        /** l1_dcache_autoload_rgid : R/W; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l1 dcache autoload.
+         */
+        uint32_t l1_dcache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_ctrl_reg_t;
+
+/** Type of l1_dcache_autoload_sct0_addr register
+ *  L1 data Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct0_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct0_size register
+ *  L1 data Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct0_size_reg_t;
+
+/** Type of l1_dcache_autoload_sct1_addr register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct1_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct1_size register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct1_size_reg_t;
+
+/** Type of l1_dcache_autoload_sct2_addr register
+ *  L1 data Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct2_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct2_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct2_size register
+ *  L1 data Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct2_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct2_size_reg_t;
+
+/** Type of l1_dcache_autoload_sct3_addr register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct3_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct3_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct3_size register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct3_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L1-DCache. Note that it should be used together with
+         *  L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct3_size_reg_t;
+
+/** Type of l2_cache_autoload_ctrl register
+ *  L2 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l2_cache_autoload_ena:1;
+        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_autoload_done:1;
+        /** l2_cache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l2_cache_autoload_order:1;
+        /** l2_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l2_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l2_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct0_ena:1;
+        /** l2_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct1_ena:1;
+        /** l2_cache_autoload_sct2_ena : R/W; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct2_ena:1;
+        /** l2_cache_autoload_sct3_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct3_ena:1;
+        /** l2_cache_autoload_rgid : R/W; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l2 cache autoload.
+         */
+        uint32_t l2_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_sct0_addr register
+ *  L2 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct0_size register
+ *  L2 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_size_reg_t;
+
+/** Type of l2_cache_autoload_sct1_addr register
+ *  L2 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct1_size register
+ *  L2 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_size_reg_t;
+
+/** Type of l2_cache_autoload_sct2_addr register
+ *  L2 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct2_size register
+ *  L2 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_size_reg_t;
+
+/** Type of l2_cache_autoload_sct3_addr register
+ *  L2 Cache autoload section 3 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct3_size register
+ *  L2 Cache autoload section 3 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_size_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of l1_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_ena:1;
+        /** l1_ibus1_ovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_ena:1;
+        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_ena:1;
+        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_ena:1;
+        /** l1_dbus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_ena:1;
+        /** l1_dbus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_ena:1;
+        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_ena:1;
+        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+         *  to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_clr:1;
+        /** l1_ibus1_ovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+         *  to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_clr:1;
+        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_clr:1;
+        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_clr:1;
+        /** l1_dbus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_clr:1;
+        /** l1_dbus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_clr:1;
+        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_clr:1;
+        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+         *  due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_raw:1;
+        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+         *  due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_raw:1;
+        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+         *  due to bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_ovf_int_raw:1;
+        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+         *  due to bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_ovf_int_raw:1;
+        /** l1_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_raw:1;
+        /** l1_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_raw:1;
+        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_ovf_int_raw:1;
+        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_ovf_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_st:1;
+        /** l1_ibus1_ovf_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_st:1;
+        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_st:1;
+        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_st:1;
+        /** l1_dbus0_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_st:1;
+        /** l1_dbus1_ovf_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_st:1;
+        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_st:1;
+        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l1_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_ena:1;
+        /** l1_icache1_fail_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_ena:1;
+        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_ena:1;
+        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_ena:1;
+        /** l1_dcache_fail_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l1_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_clr:1;
+        /** l1_icache1_fail_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_clr:1;
+        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_clr:1;
+        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_clr:1;
+        /** l1_dcache_fail_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l1_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_raw:1;
+        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_raw:1;
+        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+         */
+        uint32_t l1_icache2_fail_int_raw:1;
+        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+         */
+        uint32_t l1_icache3_fail_int_raw:1;
+        /** l1_dcache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l1_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_int_st:1;
+        /** l1_icache1_fail_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_int_st:1;
+        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_st:1;
+        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_st:1;
+        /** l1_dcache_fail_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+         *  to cpu accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_st_reg_t;
+
+/** Type of sync_l1_cache_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache0_pld_done_int_ena:1;
+        /** l1_icache1_pld_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache1_pld_done_int_ena:1;
+        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_ena:1;
+        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_ena:1;
+        /** l1_dcache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of L1-DCache preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_dcache_pld_done_int_ena:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation done.
+         */
+        uint32_t sync_done_int_ena:1;
+        /** l1_icache0_pld_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_ena:1;
+        /** l1_icache1_pld_err_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_ena:1;
+        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_ena:1;
+        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_ena:1;
+        /** l1_dcache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable interrupt of L1-DCache preload-operation error.
+         */
+        uint32_t l1_dcache_pld_err_int_ena:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_int_ena_reg_t;
+
+/** Type of sync_l1_cache_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_clr:1;
+        /** l1_icache1_pld_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_clr:1;
+        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_clr:1;
+        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_clr:1;
+        /** l1_dcache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-DCache
+         *  preload-operation is done.
+         */
+        uint32_t l1_dcache_pld_done_int_clr:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+         *  done.
+         */
+        uint32_t sync_done_int_clr:1;
+        /** l1_icache0_pld_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_clr:1;
+        /** l1_icache1_pld_err_int_clr : WT; bitpos: [8]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_clr:1;
+        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_clr:1;
+        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_clr:1;
+        /** l1_dcache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
+         *  The bit is used to clear interrupt of L1-DCache preload-operation error.
+         */
+        uint32_t l1_dcache_pld_err_int_clr:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_int_clr_reg_t;
+
+/** Type of sync_l1_cache_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache0_pld_done_int_raw:1;
+        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache1_pld_done_int_raw:1;
+        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_raw:1;
+        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_raw:1;
+        /** l1_dcache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation is
+         *  done.
+         */
+        uint32_t l1_dcache_pld_done_int_raw:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+         */
+        uint32_t sync_done_int_raw:1;
+        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache0_pld_err_int_raw:1;
+        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache1_pld_err_int_raw:1;
+        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_raw:1;
+        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_raw:1;
+        /** l1_dcache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_dcache_pld_err_int_raw:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+         *  occurs.
+         */
+        uint32_t sync_err_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_int_raw_reg_t;
+
+/** Type of sync_l1_cache_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_st:1;
+        /** l1_icache1_pld_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_st:1;
+        /** l1_icache2_pld_done_int_st : RO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_st:1;
+        /** l1_icache3_pld_done_int_st : RO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_st:1;
+        /** l1_dcache_pld_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-DCache
+         *  preload-operation is done.
+         */
+        uint32_t l1_dcache_pld_done_int_st:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_st : RO; bitpos: [6]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when Cache
+         *  sync-operation is done.
+         */
+        uint32_t sync_done_int_st:1;
+        /** l1_icache0_pld_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_st:1;
+        /** l1_icache1_pld_err_int_st : RO; bitpos: [8]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_st:1;
+        /** l1_icache2_pld_err_int_st : RO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_st:1;
+        /** l1_icache3_pld_err_int_st : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_st:1;
+        /** l1_dcache_pld_err_int_st : RO; bitpos: [11]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-DCache preload-operation error.
+         */
+        uint32_t l1_dcache_pld_err_int_st:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the status of the interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_int_st_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_ena:1;
+        /** l2_ibus1_ovf_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_ena:1;
+        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_ena:1;
+        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_ena:1;
+        /** l2_dbus0_ovf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_ena:1;
+        /** l2_dbus1_ovf_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_ena:1;
+        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_ena:1;
+        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_clr : WT; bitpos: [8]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_clr:1;
+        /** l2_ibus1_ovf_int_clr : WT; bitpos: [9]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_clr:1;
+        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_clr:1;
+        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_clr:1;
+        /** l2_dbus0_ovf_int_clr : WT; bitpos: [12]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_clr:1;
+        /** l2_dbus1_ovf_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_clr:1;
+        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_clr:1;
+        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-ICache0.
+         */
+        uint32_t l2_ibus0_ovf_int_raw:1;
+        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-ICache1.
+         */
+        uint32_t l2_ibus1_ovf_int_raw:1;
+        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-ICache2.
+         */
+        uint32_t l2_ibus2_ovf_int_raw:1;
+        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-ICache3.
+         */
+        uint32_t l2_ibus3_ovf_int_raw:1;
+        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-DCache.
+         */
+        uint32_t l2_dbus0_ovf_int_raw:1;
+        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-DCache.
+         */
+        uint32_t l2_dbus1_ovf_int_raw:1;
+        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-DCache.
+         */
+        uint32_t l2_dbus2_ovf_int_raw:1;
+        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-DCache.
+         */
+        uint32_t l2_dbus3_ovf_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_st : RO; bitpos: [8]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_st:1;
+        /** l2_ibus1_ovf_int_st : RO; bitpos: [9]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_st:1;
+        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_st:1;
+        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_st:1;
+        /** l2_dbus0_ovf_int_st : RO; bitpos: [12]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_st:1;
+        /** l2_dbus1_ovf_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_st:1;
+        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_st:1;
+        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l2_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+         *  l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l2_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+         *  cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l2_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l2_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+         *  to l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_st_reg_t;
+
+/** Type of l2_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+         */
+        uint32_t l2_cache_pld_done_int_ena:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l2_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l2_cache_pld_done_int_clr:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_clr : WT; bitpos: [12]; default: 0;
+         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l2_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l2_cache_pld_done_int_raw:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_err_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l2_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l2_cache_pld_done_int_st:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_st : RO; bitpos: [12]; default: 0;
+         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_st_reg_t;
+
+
+/** Group: Cache Access Fail Configuration register */
+/** Type of l1_cache_acs_fail_ctrl register
+ *  Cache Access Fail Configuration register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_acs_fail_check_mode : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache0_acs_fail_check_mode:1;
+        /** l1_icache1_acs_fail_check_mode : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache1_acs_fail_check_mode:1;
+        /** l1_icache2_acs_fail_check_mode : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache2_acs_fail_check_mode:1;
+        /** l1_icache3_acs_fail_check_mode : R/W; bitpos: [3]; default: 0;
+         *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache3_acs_fail_check_mode:1;
+        /** l1_dcache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to configure l1 dcache access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_dcache_acs_fail_check_mode:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_ctrl_reg_t;
+
+/** Type of l2_cache_acs_fail_ctrl register
+ *  Cache Access Fail Configuration register
+ */
+typedef union {
+    struct {
+        /** l2_cache_acs_fail_check_mode : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
+         *  not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l2_cache_acs_fail_check_mode:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_ctrl_reg_t;
+
+
+/** Group: Access Statistics registers */
+/** Type of l1_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_cnt_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_ena:1;
+        /** l1_ibus1_cnt_ena : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_ena:1;
+        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_ena:1;
+        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_ena:1;
+        /** l1_dbus0_cnt_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_dbus0_cnt_ena:1;
+        /** l1_dbus1_cnt_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_dbus1_cnt_ena:1;
+        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_ena:1;
+        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_ena:1;
+        uint32_t reserved_8:8;
+        /** l1_ibus0_cnt_clr : WT; bitpos: [16]; default: 0;
+         *  The bit is used to clear ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_clr:1;
+        /** l1_ibus1_cnt_clr : WT; bitpos: [17]; default: 0;
+         *  The bit is used to clear ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_clr:1;
+        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_clr:1;
+        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_clr:1;
+        /** l1_dbus0_cnt_clr : WT; bitpos: [20]; default: 0;
+         *  The bit is used to clear dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_dbus0_cnt_clr:1;
+        /** l1_dbus1_cnt_clr : WT; bitpos: [21]; default: 0;
+         *  The bit is used to clear dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_dbus1_cnt_clr:1;
+        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_clr:1;
+        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_clr:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l1_ibus0_acs_hit_cnt register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_miss_cnt register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_conflict_cnt register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l1_ibus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_hit_cnt register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_miss_cnt register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_conflict_cnt register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l1_ibus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_hit_cnt register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_miss_cnt register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_conflict_cnt register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l1_ibus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_hit_cnt register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_miss_cnt register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_conflict_cnt register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l1_ibus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_hit_cnt register
+ *  L1-DCache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_miss_cnt register
+ *  L1-DCache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_conflict_cnt register
+ *  L1-DCache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l1_dbus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus0 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_hit_cnt register
+ *  L1-DCache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_miss_cnt register
+ *  L1-DCache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_conflict_cnt register
+ *  L1-DCache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l1_dbus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus1 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_hit_cnt register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_miss_cnt register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_conflict_cnt register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus2 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_hit_cnt register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_miss_cnt register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_conflict_cnt register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus3 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_cnt_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_ena:1;
+        /** l2_ibus1_cnt_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_ena:1;
+        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_ena:1;
+        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_ena:1;
+        /** l2_dbus0_cnt_ena : R/W; bitpos: [12]; default: 0;
+         *  The bit is used to enable dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_ena:1;
+        /** l2_dbus1_cnt_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_ena:1;
+        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_ena:1;
+        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_ena:1;
+        uint32_t reserved_16:8;
+        /** l2_ibus0_cnt_clr : WT; bitpos: [24]; default: 0;
+         *  The bit is used to clear ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_clr:1;
+        /** l2_ibus1_cnt_clr : WT; bitpos: [25]; default: 0;
+         *  The bit is used to clear ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_clr:1;
+        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_clr:1;
+        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_clr:1;
+        /** l2_dbus0_cnt_clr : WT; bitpos: [28]; default: 0;
+         *  The bit is used to clear dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_clr:1;
+        /** l2_dbus1_cnt_clr : WT; bitpos: [29]; default: 0;
+         *  The bit is used to clear dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_clr:1;
+        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_clr:1;
+        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_clr:1;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l2_ibus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache0 accesses
+         *  L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache1 accesses
+         *  L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache2 accesses
+         *  L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache3 accesses
+         *  L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus0 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus1 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus2 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus3 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t;
+
+
+/** Group: Access Fail Debug registers */
+/** Type of l1_icache0_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_id:16;
+        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache0_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_addr_reg_t;
+
+/** Type of l1_icache1_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_id:16;
+        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache1_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_addr_reg_t;
+
+/** Type of l1_icache2_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_id:16;
+        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache2_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_addr_reg_t;
+
+/** Type of l1_icache3_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_id:16;
+        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache3_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_addr_reg_t;
+
+/** Type of l1_dcache_acs_fail_id_attr register
+ *  L1-DCache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_id:16;
+        /** l1_dcache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_dcache_acs_fail_id_attr_reg_t;
+
+/** Type of l1_dcache_acs_fail_addr register
+ *  L1-DCache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_acs_fail_addr_reg_t;
+
+/** Type of l2_cache_acs_fail_id_attr register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_id:16;
+        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+         *  due to cache accessing L1-Cache.
+         */
+        uint32_t l2_cache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l2_cache_acs_fail_addr register
+ *  L2-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_addr_reg_t;
+
+
+/** Group: Operation Exception registers */
+/** Type of sync_l1_cache_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache0.
+         */
+        uint32_t l1_icache0_pld_err_code:2;
+        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache1.
+         */
+        uint32_t l1_icache1_pld_err_code:2;
+        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_code:2;
+        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_code:2;
+        /** l1_dcache_pld_err_code : RO; bitpos: [9:8]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-DCache.
+         */
+        uint32_t l1_dcache_pld_err_code:2;
+        uint32_t reserved_10:2;
+        /** sync_err_code : RO; bitpos: [13:12]; default: 0;
+         *  The values 0-2 are available which means sync map, command conflict and size are
+         *  error in Cache System.
+         */
+        uint32_t sync_err_code:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_sync_l1_cache_preload_exception_reg_t;
+
+/** Type of l2_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L2-Cache.
+         */
+        uint32_t l2_cache_pld_err_code:2;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_exception_reg_t;
+
+
+/** Group: Sync Reset control and configuration registers */
+/** Type of l1_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_sync_rst : R/W; bitpos: [0]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache0_sync_rst:1;
+        /** l1_icache1_sync_rst : R/W; bitpos: [1]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache1_sync_rst:1;
+        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_sync_rst:1;
+        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_sync_rst:1;
+        /** l1_dcache_sync_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset sync-logic inside L1-DCache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_dcache_sync_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_rst_ctrl_reg_t;
+
+/** Type of l2_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_sync_rst : R/W; bitpos: [5]; default: 0;
+         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l2_cache_sync_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_rst_ctrl_reg_t;
+
+
+/** Group: Preload Reset control and configuration registers */
+/** Type of l1_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_rst : R/W; bitpos: [0]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache0_pld_rst:1;
+        /** l1_icache1_pld_rst : R/W; bitpos: [1]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache1_pld_rst:1;
+        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_rst:1;
+        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_rst:1;
+        /** l1_dcache_pld_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset preload-logic inside L1-DCache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_dcache_pld_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_preload_rst_ctrl_reg_t;
+
+/** Type of l2_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_rst : R/W; bitpos: [5]; default: 0;
+         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_rst_ctrl_reg_t;
+
+
+/** Group: Autoload buffer clear control and configuration registers */
+/** Type of l1_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_ald_buf_clr : R/W; bitpos: [0]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+         *  works in L1-ICache0.
+         */
+        uint32_t l1_icache0_ald_buf_clr:1;
+        /** l1_icache1_ald_buf_clr : R/W; bitpos: [1]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+         *  works in L1-ICache1.
+         */
+        uint32_t l1_icache1_ald_buf_clr:1;
+        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_ald_buf_clr:1;
+        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_ald_buf_clr:1;
+        /** l1_dcache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-DCache. If this bit is active,
+         *  autoload will not work in L1-DCache. This bit should not be active when autoload
+         *  works in L1-DCache.
+         */
+        uint32_t l1_dcache_ald_buf_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_buf_clr_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_ald_buf_clr : R/W; bitpos: [5]; default: 0;
+         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+         *  autoload will not work in L2-Cache. This bit should not be active when autoload
+         *  works in L2-Cache.
+         */
+        uint32_t l2_cache_ald_buf_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_buf_clr_ctrl_reg_t;
+
+
+/** Group: Unallocate request buffer clear registers */
+/** Type of l1_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        /** l1_icache0_unalloc_clr : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache0_unalloc_clr:1;
+        /** l1_icache1_unalloc_clr : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache1_unalloc_clr:1;
+        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_unalloc_clr:1;
+        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_unalloc_clr:1;
+        /** l1_dcache_unalloc_clr : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 dcache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_dcache_unalloc_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_unallocate_buffer_clear_reg_t;
+
+/** Type of l2_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_unalloc_clr : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l2 icache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l2_cache_unalloc_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_unallocate_buffer_clear_reg_t;
+
+
+/** Group: Tag and Data Memory Access Control and configuration register */
+/** Type of l1_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_object : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache0_tag_object:1;
+        /** l1_icache1_tag_object : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache1_tag_object:1;
+        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_object:1;
+        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_object:1;
+        /** l1_dcache_tag_object : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to set L1-DCache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_dcache_tag_object:1;
+        uint32_t reserved_5:1;
+        /** l1_icache0_mem_object : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache0_mem_object:1;
+        /** l1_icache1_mem_object : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache1_mem_object:1;
+        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_mem_object:1;
+        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_mem_object:1;
+        /** l1_dcache_mem_object : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to set L1-DCache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_dcache_mem_object:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} cache_l1_cache_object_ctrl_reg_t;
+
+/** Type of l1_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l1_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l1_cache_way_object_reg_t;
+
+/** Type of l1_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l1_cache_vaddr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_vaddr_reg_t;
+
+/** Type of l1_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 616;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l1_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l1_cache_debug_bus_reg_t;
+
+/** Type of l2_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_tag_object : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_tag_object:1;
+        uint32_t reserved_6:5;
+        /** l2_cache_mem_object : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_mem_object:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_object_ctrl_reg_t;
+
+/** Type of l2_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l2_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l2_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l2_cache_way_object_reg_t;
+
+/** Type of l2_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l2_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l2_cache_vaddr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_vaddr_reg_t;
+
+/** Type of l2_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l2_cache_debug_bus : R/W; bitpos: [31:0]; default: 972;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l2_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l2_cache_debug_bus_reg_t;
+
+
+/** Group: L2 cache access attribute control register */
+/** Type of l2_cache_access_attr_ctrl register
+ *  L2 cache access attribute control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_access_force_cc : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+         *  non-cacheable.
+         */
+        uint32_t l2_cache_access_force_cc:1;
+        /** l2_cache_access_force_wb : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+         *  write-through.
+         */
+        uint32_t l2_cache_access_force_wb:1;
+        /** l2_cache_access_force_wma : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  write-miss-allocate and write-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_wma:1;
+        /** l2_cache_access_force_rma : R/W; bitpos: [3]; default: 1;
+         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  read-miss-allocate and read-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_rma:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_l2_cache_access_attr_ctrl_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38810192;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_date_reg_t;
+
+
+typedef struct {
+    volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl;
+    volatile cache_l1_dcache_ctrl_reg_t l1_dcache_ctrl;
+    volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
+    volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
+    volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
+    volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
+    volatile cache_l1_dcache_cachesize_conf_reg_t l1_dcache_cachesize_conf;
+    volatile cache_l1_dcache_blocksize_conf_reg_t l1_dcache_blocksize_conf;
+    volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
+    volatile cache_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
+    volatile cache_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
+    volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
+    volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
+    volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
+    volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
+    volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
+    volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
+    volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
+    volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
+    volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
+    volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
+    volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
+    volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
+    volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
+    volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
+    volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
+    volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
+    volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
+    volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
+    volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
+    volatile cache_l1_dcache_prelock_conf_reg_t l1_dcache_prelock_conf;
+    volatile cache_l1_dcache_prelock_sct0_addr_reg_t l1_dcache_prelock_sct0_addr;
+    volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
+    volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
+    volatile cache_lock_ctrl_reg_t lock_ctrl;
+    volatile cache_lock_map_reg_t lock_map;
+    volatile cache_lock_addr_reg_t lock_addr;
+    volatile cache_lock_size_reg_t lock_size;
+    volatile cache_sync_ctrl_reg_t sync_ctrl;
+    volatile cache_sync_map_reg_t sync_map;
+    volatile cache_sync_addr_reg_t sync_addr;
+    volatile cache_sync_size_reg_t sync_size;
+    volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
+    volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
+    volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
+    volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
+    volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
+    volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
+    volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
+    volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
+    volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
+    volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
+    volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
+    volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
+    volatile cache_l1_dcache_preload_ctrl_reg_t l1_dcache_preload_ctrl;
+    volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
+    volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
+    volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
+    volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
+    volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
+    volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
+    volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
+    volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
+    volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
+    volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
+    volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
+    volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
+    volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
+    volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
+    volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
+    volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
+    volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
+    volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
+    volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
+    volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
+    volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
+    volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
+    volatile cache_l1_dcache_autoload_ctrl_reg_t l1_dcache_autoload_ctrl;
+    volatile cache_l1_dcache_autoload_sct0_addr_reg_t l1_dcache_autoload_sct0_addr;
+    volatile cache_l1_dcache_autoload_sct0_size_reg_t l1_dcache_autoload_sct0_size;
+    volatile cache_l1_dcache_autoload_sct1_addr_reg_t l1_dcache_autoload_sct1_addr;
+    volatile cache_l1_dcache_autoload_sct1_size_reg_t l1_dcache_autoload_sct1_size;
+    volatile cache_l1_dcache_autoload_sct2_addr_reg_t l1_dcache_autoload_sct2_addr;
+    volatile cache_l1_dcache_autoload_sct2_size_reg_t l1_dcache_autoload_sct2_size;
+    volatile cache_l1_dcache_autoload_sct3_addr_reg_t l1_dcache_autoload_sct3_addr;
+    volatile cache_l1_dcache_autoload_sct3_size_reg_t l1_dcache_autoload_sct3_size;
+    volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
+    volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
+    volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
+    volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
+    volatile cache_l1_cache_acs_fail_ctrl_reg_t l1_cache_acs_fail_ctrl;
+    volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
+    volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
+    volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
+    volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
+    volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
+    volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
+    volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
+    volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
+    volatile cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t l1_ibus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
+    volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
+    volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
+    volatile cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t l1_ibus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
+    volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
+    volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
+    volatile cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t l1_ibus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
+    volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
+    volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
+    volatile cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t l1_ibus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus0_acs_hit_cnt_reg_t l1_dbus0_acs_hit_cnt;
+    volatile cache_l1_dbus0_acs_miss_cnt_reg_t l1_dbus0_acs_miss_cnt;
+    volatile cache_l1_dbus0_acs_conflict_cnt_reg_t l1_dbus0_acs_conflict_cnt;
+    volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus1_acs_hit_cnt_reg_t l1_dbus1_acs_hit_cnt;
+    volatile cache_l1_dbus1_acs_miss_cnt_reg_t l1_dbus1_acs_miss_cnt;
+    volatile cache_l1_dbus1_acs_conflict_cnt_reg_t l1_dbus1_acs_conflict_cnt;
+    volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
+    volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
+    volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
+    volatile cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t l1_dbus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t l1_dbus2_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
+    volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
+    volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
+    volatile cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t l1_dbus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t l1_dbus3_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
+    volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
+    volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
+    volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
+    volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
+    volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
+    volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
+    volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
+    volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr;
+    volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
+    volatile cache_sync_l1_cache_preload_int_ena_reg_t sync_l1_cache_preload_int_ena;
+    volatile cache_sync_l1_cache_preload_int_clr_reg_t sync_l1_cache_preload_int_clr;
+    volatile cache_sync_l1_cache_preload_int_raw_reg_t sync_l1_cache_preload_int_raw;
+    volatile cache_sync_l1_cache_preload_int_st_reg_t sync_l1_cache_preload_int_st;
+    volatile cache_sync_l1_cache_preload_exception_reg_t sync_l1_cache_preload_exception;
+    volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
+    volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
+    volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
+    volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
+    volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
+    volatile cache_l1_cache_way_object_reg_t l1_cache_way_object;
+    volatile cache_l1_cache_vaddr_reg_t l1_cache_vaddr;
+    volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
+    uint32_t reserved_26c;
+    volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl;
+    volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
+    volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
+    volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
+    volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
+    volatile cache_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
+    volatile cache_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
+    volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
+    volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
+    volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
+    volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
+    volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
+    volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
+    volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
+    volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
+    volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
+    volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size;
+    volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
+    volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
+    volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
+    volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
+    volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
+    volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
+    volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
+    volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
+    volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
+    volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
+    volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
+    volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
+    volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
+    volatile cache_l2_cache_acs_fail_ctrl_reg_t l2_cache_acs_fail_ctrl;
+    volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
+    volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
+    volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
+    volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
+    volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
+    volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
+    volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
+    volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
+    volatile cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t l2_ibus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
+    volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
+    volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
+    volatile cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t l2_ibus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
+    volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
+    volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
+    volatile cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t l2_ibus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
+    volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
+    volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
+    volatile cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t l2_ibus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
+    volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
+    volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
+    volatile cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t l2_dbus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t l2_dbus0_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
+    volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
+    volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
+    volatile cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t l2_dbus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t l2_dbus1_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
+    volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
+    volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
+    volatile cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t l2_dbus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t l2_dbus2_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
+    volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
+    volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
+    volatile cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t l2_dbus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t l2_dbus3_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
+    volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
+    volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
+    volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
+    volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
+    volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
+    volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
+    volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
+    volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
+    volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
+    volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
+    volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
+    volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
+    volatile cache_l2_cache_way_object_reg_t l2_cache_way_object;
+    volatile cache_l2_cache_vaddr_reg_t l2_cache_vaddr;
+    volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
+    uint32_t reserved_3d0;
+    volatile cache_clock_gate_reg_t clock_gate;
+    uint32_t reserved_3d8[9];
+    volatile cache_date_reg_t date;
+} cache_dev_t;
+
+extern cache_dev_t CACHE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dma2d_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/dma2d_eco5_reg.h
new file mode 100644
index 0000000000..3077ad0e45
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dma2d_eco5_reg.h
@@ -0,0 +1,7537 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DMA2D_OUT_CONF0_CH0_REG register
+ *  Configures the tx direction of channel 0
+ */
+#define DMA2D_OUT_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x0)
+/** DMA2D_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH0    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH0_M  (DMA2D_OUT_AUTO_WRBACK_CH0_V << DMA2D_OUT_AUTO_WRBACK_CH0_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH0_S  0
+/** DMA2D_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH0    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH0_M  (DMA2D_OUT_EOF_MODE_CH0_V << DMA2D_OUT_EOF_MODE_CH0_S)
+#define DMA2D_OUT_EOF_MODE_CH0_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH0_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH0_M  (DMA2D_OUTDSCR_BURST_EN_CH0_V << DMA2D_OUTDSCR_BURST_EN_CH0_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH0_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH0_M  (DMA2D_OUT_ECC_AES_EN_CH0_V << DMA2D_OUT_ECC_AES_EN_CH0_S)
+#define DMA2D_OUT_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH0_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH0_M  (DMA2D_OUT_CHECK_OWNER_CH0_V << DMA2D_OUT_CHECK_OWNER_CH0_S)
+#define DMA2D_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH0_S  4
+/** DMA2D_OUT_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH0_M  (DMA2D_OUT_LOOP_TEST_CH0_V << DMA2D_OUT_LOOP_TEST_CH0_S)
+#define DMA2D_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH0_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH0_V << DMA2D_OUT_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_M  (DMA2D_OUT_DSCR_PORT_EN_CH0_V << DMA2D_OUT_DSCR_PORT_EN_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_M  (DMA2D_OUT_PAGE_BOUND_EN_CH0_V << DMA2D_OUT_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH0_M  (DMA2D_OUT_REORDER_EN_CH0_V << DMA2D_OUT_REORDER_EN_CH0_S)
+#define DMA2D_OUT_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH0_S  16
+/** DMA2D_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH0    (BIT(24))
+#define DMA2D_OUT_RST_CH0_M  (DMA2D_OUT_RST_CH0_V << DMA2D_OUT_RST_CH0_S)
+#define DMA2D_OUT_RST_CH0_V  0x00000001U
+#define DMA2D_OUT_RST_CH0_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH0_M  (DMA2D_OUT_CMD_DISABLE_CH0_V << DMA2D_OUT_CMD_DISABLE_CH0_S)
+#define DMA2D_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH0_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_OUT_INT_RAW_CH0_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x4)
+/** DMA2D_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_RAW_M  (DMA2D_OUT_DONE_CH0_INT_RAW_V << DMA2D_OUT_DONE_CH0_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_RAW_M  (DMA2D_OUT_EOF_CH0_INT_RAW_V << DMA2D_OUT_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x8)
+/** DMA2D_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ENA_M  (DMA2D_OUT_DONE_CH0_INT_ENA_V << DMA2D_OUT_DONE_CH0_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ENA_M  (DMA2D_OUT_EOF_CH0_INT_ENA_V << DMA2D_OUT_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0xc)
+/** DMA2D_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ST_M  (DMA2D_OUT_DONE_CH0_INT_ST_V << DMA2D_OUT_DONE_CH0_INT_ST_S)
+#define DMA2D_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ST_M  (DMA2D_OUT_EOF_CH0_INT_ST_V << DMA2D_OUT_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x10)
+/** DMA2D_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_CLR_M  (DMA2D_OUT_DONE_CH0_INT_CLR_V << DMA2D_OUT_DONE_CH0_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_CLR_M  (DMA2D_OUT_EOF_CH0_INT_CLR_V << DMA2D_OUT_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH0_REG register
+ *  Represents the status of the tx fifo of channel 0
+ */
+#define DMA2D_OUTFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x14)
+/** DMA2D_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH0_M  (DMA2D_OUTFIFO_FULL_L2_CH0_V << DMA2D_OUTFIFO_FULL_L2_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH0_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_M  (DMA2D_OUTFIFO_EMPTY_L2_CH0_V << DMA2D_OUTFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_M  (DMA2D_OUTFIFO_CNT_L2_CH0_V << DMA2D_OUTFIFO_CNT_L2_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH0_V << DMA2D_OUT_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH0_V << DMA2D_OUT_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH0_V << DMA2D_OUT_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH0_V << DMA2D_OUT_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH0_V << DMA2D_OUT_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH0_V << DMA2D_OUT_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH0_V << DMA2D_OUT_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH0_V << DMA2D_OUT_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH0_M  (DMA2D_OUTFIFO_FULL_L1_CH0_V << DMA2D_OUTFIFO_FULL_L1_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH0_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_M  (DMA2D_OUTFIFO_EMPTY_L1_CH0_V << DMA2D_OUTFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_M  (DMA2D_OUTFIFO_CNT_L1_CH0_V << DMA2D_OUTFIFO_CNT_L1_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH0_M  (DMA2D_OUTFIFO_FULL_L3_CH0_V << DMA2D_OUTFIFO_FULL_L3_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH0_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_M  (DMA2D_OUTFIFO_EMPTY_L3_CH0_V << DMA2D_OUTFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_M  (DMA2D_OUTFIFO_CNT_L3_CH0_V << DMA2D_OUTFIFO_CNT_L3_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_OUT_PUSH_CH0_REG register
+ *  Configures the tx fifo of channel 0
+ */
+#define DMA2D_OUT_PUSH_CH0_REG (DR_REG_DMA2D_BASE + 0x18)
+/** DMA2D_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH0    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_M  (DMA2D_OUTFIFO_WDATA_CH0_V << DMA2D_OUTFIFO_WDATA_CH0_S)
+#define DMA2D_OUTFIFO_WDATA_CH0_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_S  0
+/** DMA2D_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH0    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH0_M  (DMA2D_OUTFIFO_PUSH_CH0_V << DMA2D_OUTFIFO_PUSH_CH0_S)
+#define DMA2D_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH0_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH0_REG register
+ *  Configures the tx descriptor operations of channel 0
+ */
+#define DMA2D_OUT_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x1c)
+/** DMA2D_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH0    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH0_M  (DMA2D_OUTLINK_STOP_CH0_V << DMA2D_OUTLINK_STOP_CH0_S)
+#define DMA2D_OUTLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH0_S  20
+/** DMA2D_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH0    (BIT(21))
+#define DMA2D_OUTLINK_START_CH0_M  (DMA2D_OUTLINK_START_CH0_V << DMA2D_OUTLINK_START_CH0_S)
+#define DMA2D_OUTLINK_START_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH0_S  21
+/** DMA2D_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH0    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH0_M  (DMA2D_OUTLINK_RESTART_CH0_V << DMA2D_OUTLINK_RESTART_CH0_S)
+#define DMA2D_OUTLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH0_S  22
+/** DMA2D_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH0    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH0_M  (DMA2D_OUTLINK_PARK_CH0_V << DMA2D_OUTLINK_PARK_CH0_S)
+#define DMA2D_OUTLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH0_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH0_REG register
+ *  Configures the tx descriptor address of channel 0
+ */
+#define DMA2D_OUT_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x20)
+/** DMA2D_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_M  (DMA2D_OUTLINK_ADDR_CH0_V << DMA2D_OUTLINK_ADDR_CH0_S)
+#define DMA2D_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_S  0
+
+/** DMA2D_OUT_STATE_CH0_REG register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+#define DMA2D_OUT_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x24)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_M  (DMA2D_OUTLINK_DSCR_ADDR_CH0_V << DMA2D_OUTLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_M  (DMA2D_OUT_DSCR_STATE_CH0_V << DMA2D_OUT_DSCR_STATE_CH0_S)
+#define DMA2D_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_S  18
+/** DMA2D_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH0    0x0000000FU
+#define DMA2D_OUT_STATE_CH0_M  (DMA2D_OUT_STATE_CH0_V << DMA2D_OUT_STATE_CH0_S)
+#define DMA2D_OUT_STATE_CH0_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH0_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH0    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH0_M  (DMA2D_OUT_RESET_AVAIL_CH0_V << DMA2D_OUT_RESET_AVAIL_CH0_S)
+#define DMA2D_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH0_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x28)
+/** DMA2D_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_M  (DMA2D_OUT_EOF_DES_ADDR_CH0_V << DMA2D_OUT_EOF_DES_ADDR_CH0_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x2c)
+/** DMA2D_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_M  (DMA2D_OUTLINK_DSCR_CH0_V << DMA2D_OUTLINK_DSCR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x30)
+/** DMA2D_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_M  (DMA2D_OUTLINK_DSCR_BF0_CH0_V << DMA2D_OUTLINK_DSCR_BF0_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x34)
+/** DMA2D_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_M  (DMA2D_OUTLINK_DSCR_BF1_CH0_V << DMA2D_OUTLINK_DSCR_BF1_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH0_REG register
+ *  Configures the tx peripheral of channel 0
+ */
+#define DMA2D_OUT_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x38)
+/** DMA2D_OUT_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH0    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_M  (DMA2D_OUT_PERI_SEL_CH0_V << DMA2D_OUT_PERI_SEL_CH0_S)
+#define DMA2D_OUT_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_S  0
+
+/** DMA2D_OUT_ARB_CH0_REG register
+ *  Configures the tx arbiter of channel 0
+ */
+#define DMA2D_OUT_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x3c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH0    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH0_M  (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH0_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH0_S  4
+/** DMA2D_OUT_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:6]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_H_CH0    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH0_M  (DMA2D_OUT_ARB_PRIORITY_H_CH0_V << DMA2D_OUT_ARB_PRIORITY_H_CH0_S)
+#define DMA2D_OUT_ARB_PRIORITY_H_CH0_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH0_S  6
+
+/** DMA2D_OUT_RO_STATUS_CH0_REG register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+#define DMA2D_OUT_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x40)
+/** DMA2D_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH0    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_M  (DMA2D_OUTFIFO_RO_CNT_CH0_V << DMA2D_OUTFIFO_RO_CNT_CH0_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH0_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_M  (DMA2D_OUT_RO_WR_STATE_CH0_V << DMA2D_OUT_RO_WR_STATE_CH0_S)
+#define DMA2D_OUT_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_M  (DMA2D_OUT_RO_RD_STATE_CH0_V << DMA2D_OUT_RO_RD_STATE_CH0_S)
+#define DMA2D_OUT_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_M  (DMA2D_OUT_PIXEL_BYTE_CH0_V << DMA2D_OUT_PIXEL_BYTE_CH0_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH0_V << DMA2D_OUT_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_S  14
+
+/** DMA2D_OUT_RO_PD_CONF_CH0_REG register
+ *  Configures the tx reorder memory of channel 0
+ */
+#define DMA2D_OUT_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x44)
+/** DMA2D_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_M  (DMA2D_OUT_RO_RAM_CLK_FO_CH0_V << DMA2D_OUT_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_OUT_COLOR_CONVERT_CH0_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x48)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH0_V << DMA2D_OUT_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH0_REG register
+ *  Configures the tx scramble of channel 0
+ */
+#define DMA2D_OUT_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x4c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x50)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_M  (DMA2D_OUT_COLOR_PARAM_H0_CH0_V << DMA2D_OUT_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x54)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_M  (DMA2D_OUT_COLOR_PARAM_H1_CH0_V << DMA2D_OUT_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x58)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_M  (DMA2D_OUT_COLOR_PARAM_M0_CH0_V << DMA2D_OUT_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x5c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_M  (DMA2D_OUT_COLOR_PARAM_M1_CH0_V << DMA2D_OUT_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x60)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_M  (DMA2D_OUT_COLOR_PARAM_L0_CH0_V << DMA2D_OUT_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x64)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_M  (DMA2D_OUT_COLOR_PARAM_L1_CH0_V << DMA2D_OUT_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH0_REG register
+ *  Configures the tx etm of channel 0
+ */
+#define DMA2D_OUT_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x68)
+/** DMA2D_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH0    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH0_M  (DMA2D_OUT_ETM_EN_CH0_V << DMA2D_OUT_ETM_EN_CH0_S)
+#define DMA2D_OUT_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH0_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_M  (DMA2D_OUT_ETM_LOOP_EN_CH0_V << DMA2D_OUT_ETM_LOOP_EN_CH0_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_M  (DMA2D_OUT_DSCR_TASK_MAK_CH0_V << DMA2D_OUT_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH0_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH0_REG (DR_REG_DMA2D_BASE + 0x6c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH0 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH0 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S  14
+
+/** DMA2D_OUT_CONF0_CH1_REG register
+ *  Configures the tx direction of channel 1
+ */
+#define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100)
+/** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH1    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH1_M  (DMA2D_OUT_AUTO_WRBACK_CH1_V << DMA2D_OUT_AUTO_WRBACK_CH1_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH1_S  0
+/** DMA2D_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH1    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH1_M  (DMA2D_OUT_EOF_MODE_CH1_V << DMA2D_OUT_EOF_MODE_CH1_S)
+#define DMA2D_OUT_EOF_MODE_CH1_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH1_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH1_M  (DMA2D_OUTDSCR_BURST_EN_CH1_V << DMA2D_OUTDSCR_BURST_EN_CH1_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH1_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH1_M  (DMA2D_OUT_ECC_AES_EN_CH1_V << DMA2D_OUT_ECC_AES_EN_CH1_S)
+#define DMA2D_OUT_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH1_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH1_M  (DMA2D_OUT_CHECK_OWNER_CH1_V << DMA2D_OUT_CHECK_OWNER_CH1_S)
+#define DMA2D_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH1_S  4
+/** DMA2D_OUT_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH1_M  (DMA2D_OUT_LOOP_TEST_CH1_V << DMA2D_OUT_LOOP_TEST_CH1_S)
+#define DMA2D_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH1_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH1_V << DMA2D_OUT_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_M  (DMA2D_OUT_DSCR_PORT_EN_CH1_V << DMA2D_OUT_DSCR_PORT_EN_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_M  (DMA2D_OUT_PAGE_BOUND_EN_CH1_V << DMA2D_OUT_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_OUT_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH1_M  (DMA2D_OUT_REORDER_EN_CH1_V << DMA2D_OUT_REORDER_EN_CH1_S)
+#define DMA2D_OUT_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH1_S  16
+/** DMA2D_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH1    (BIT(24))
+#define DMA2D_OUT_RST_CH1_M  (DMA2D_OUT_RST_CH1_V << DMA2D_OUT_RST_CH1_S)
+#define DMA2D_OUT_RST_CH1_V  0x00000001U
+#define DMA2D_OUT_RST_CH1_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH1_M  (DMA2D_OUT_CMD_DISABLE_CH1_V << DMA2D_OUT_CMD_DISABLE_CH1_S)
+#define DMA2D_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH1_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_OUT_INT_RAW_CH1_REG register
+ *  Raw interrupt status of TX channel 1
+ */
+#define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104)
+/** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_RAW_M  (DMA2D_OUT_DONE_CH1_INT_RAW_V << DMA2D_OUT_DONE_CH1_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_RAW_M  (DMA2D_OUT_EOF_CH1_INT_RAW_V << DMA2D_OUT_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of TX channel 1
+ */
+#define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108)
+/** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ENA_M  (DMA2D_OUT_DONE_CH1_INT_ENA_V << DMA2D_OUT_DONE_CH1_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ENA_M  (DMA2D_OUT_EOF_CH1_INT_ENA_V << DMA2D_OUT_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt status of TX channel 1
+ */
+#define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c)
+/** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ST_M  (DMA2D_OUT_DONE_CH1_INT_ST_V << DMA2D_OUT_DONE_CH1_INT_ST_S)
+#define DMA2D_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ST_M  (DMA2D_OUT_EOF_CH1_INT_ST_V << DMA2D_OUT_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of TX channel 1
+ */
+#define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110)
+/** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_CLR_M  (DMA2D_OUT_DONE_CH1_INT_CLR_V << DMA2D_OUT_DONE_CH1_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_CLR_M  (DMA2D_OUT_EOF_CH1_INT_CLR_V << DMA2D_OUT_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH1_REG register
+ *  Represents the status of the tx fifo of channel 1
+ */
+#define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114)
+/** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH1_M  (DMA2D_OUTFIFO_FULL_L2_CH1_V << DMA2D_OUTFIFO_FULL_L2_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH1_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_M  (DMA2D_OUTFIFO_EMPTY_L2_CH1_V << DMA2D_OUTFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_M  (DMA2D_OUTFIFO_CNT_L2_CH1_V << DMA2D_OUTFIFO_CNT_L2_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH1_V << DMA2D_OUT_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH1_V << DMA2D_OUT_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH1_V << DMA2D_OUT_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH1_V << DMA2D_OUT_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH1_V << DMA2D_OUT_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH1_V << DMA2D_OUT_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH1_V << DMA2D_OUT_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH1_V << DMA2D_OUT_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH1_M  (DMA2D_OUTFIFO_FULL_L1_CH1_V << DMA2D_OUTFIFO_FULL_L1_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH1_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_M  (DMA2D_OUTFIFO_EMPTY_L1_CH1_V << DMA2D_OUTFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_M  (DMA2D_OUTFIFO_CNT_L1_CH1_V << DMA2D_OUTFIFO_CNT_L1_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH1_M  (DMA2D_OUTFIFO_FULL_L3_CH1_V << DMA2D_OUTFIFO_FULL_L3_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH1_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_M  (DMA2D_OUTFIFO_EMPTY_L3_CH1_V << DMA2D_OUTFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_M  (DMA2D_OUTFIFO_CNT_L3_CH1_V << DMA2D_OUTFIFO_CNT_L3_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_OUT_PUSH_CH1_REG register
+ *  Configures the tx fifo of channel 1
+ */
+#define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118)
+/** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH1    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_M  (DMA2D_OUTFIFO_WDATA_CH1_V << DMA2D_OUTFIFO_WDATA_CH1_S)
+#define DMA2D_OUTFIFO_WDATA_CH1_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_S  0
+/** DMA2D_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH1    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH1_M  (DMA2D_OUTFIFO_PUSH_CH1_V << DMA2D_OUTFIFO_PUSH_CH1_S)
+#define DMA2D_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH1_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH1_REG register
+ *  Configures the tx descriptor operations of channel 1
+ */
+#define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c)
+/** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH1    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH1_M  (DMA2D_OUTLINK_STOP_CH1_V << DMA2D_OUTLINK_STOP_CH1_S)
+#define DMA2D_OUTLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH1_S  20
+/** DMA2D_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH1    (BIT(21))
+#define DMA2D_OUTLINK_START_CH1_M  (DMA2D_OUTLINK_START_CH1_V << DMA2D_OUTLINK_START_CH1_S)
+#define DMA2D_OUTLINK_START_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH1_S  21
+/** DMA2D_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH1    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH1_M  (DMA2D_OUTLINK_RESTART_CH1_V << DMA2D_OUTLINK_RESTART_CH1_S)
+#define DMA2D_OUTLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH1_S  22
+/** DMA2D_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH1    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH1_M  (DMA2D_OUTLINK_PARK_CH1_V << DMA2D_OUTLINK_PARK_CH1_S)
+#define DMA2D_OUTLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH1_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH1_REG register
+ *  Configures the tx descriptor address of channel 1
+ */
+#define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120)
+/** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_M  (DMA2D_OUTLINK_ADDR_CH1_V << DMA2D_OUTLINK_ADDR_CH1_S)
+#define DMA2D_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_S  0
+
+/** DMA2D_OUT_STATE_CH1_REG register
+ *  Represents the working status of the tx descriptor of channel 1
+ */
+#define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_M  (DMA2D_OUTLINK_DSCR_ADDR_CH1_V << DMA2D_OUTLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_M  (DMA2D_OUT_DSCR_STATE_CH1_V << DMA2D_OUT_DSCR_STATE_CH1_S)
+#define DMA2D_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_S  18
+/** DMA2D_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH1    0x0000000FU
+#define DMA2D_OUT_STATE_CH1_M  (DMA2D_OUT_STATE_CH1_V << DMA2D_OUT_STATE_CH1_S)
+#define DMA2D_OUT_STATE_CH1_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH1_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH1    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH1_M  (DMA2D_OUT_RESET_AVAIL_CH1_V << DMA2D_OUT_RESET_AVAIL_CH1_S)
+#define DMA2D_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH1_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128)
+/** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_M  (DMA2D_OUT_EOF_DES_ADDR_CH1_V << DMA2D_OUT_EOF_DES_ADDR_CH1_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c)
+/** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_M  (DMA2D_OUTLINK_DSCR_CH1_V << DMA2D_OUTLINK_DSCR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130)
+/** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_M  (DMA2D_OUTLINK_DSCR_BF0_CH1_V << DMA2D_OUTLINK_DSCR_BF0_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134)
+/** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_M  (DMA2D_OUTLINK_DSCR_BF1_CH1_V << DMA2D_OUTLINK_DSCR_BF1_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH1_REG register
+ *  Configures the tx peripheral of channel 1
+ */
+#define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138)
+/** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH1    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_M  (DMA2D_OUT_PERI_SEL_CH1_V << DMA2D_OUT_PERI_SEL_CH1_S)
+#define DMA2D_OUT_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_S  0
+
+/** DMA2D_OUT_ARB_CH1_REG register
+ *  Configures the tx arbiter of channel 1
+ */
+#define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH1    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH1_M  (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH1_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH1_S  4
+/** DMA2D_OUT_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:6]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_H_CH1    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH1_M  (DMA2D_OUT_ARB_PRIORITY_H_CH1_V << DMA2D_OUT_ARB_PRIORITY_H_CH1_S)
+#define DMA2D_OUT_ARB_PRIORITY_H_CH1_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH1_S  6
+
+/** DMA2D_OUT_RO_STATUS_CH1_REG register
+ *  Represents the status of the tx reorder module of channel 1
+ */
+#define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140)
+/** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH1    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_M  (DMA2D_OUTFIFO_RO_CNT_CH1_V << DMA2D_OUTFIFO_RO_CNT_CH1_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH1_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH1 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_M  (DMA2D_OUT_RO_WR_STATE_CH1_V << DMA2D_OUT_RO_WR_STATE_CH1_S)
+#define DMA2D_OUT_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH1 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_M  (DMA2D_OUT_RO_RD_STATE_CH1_V << DMA2D_OUT_RO_RD_STATE_CH1_S)
+#define DMA2D_OUT_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH1 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_M  (DMA2D_OUT_PIXEL_BYTE_CH1_V << DMA2D_OUT_PIXEL_BYTE_CH1_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH1 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH1_V << DMA2D_OUT_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH1_REG register
+ *  Configures the tx color convert of channel 1
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH1_V << DMA2D_OUT_COLOR_INPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH1_REG register
+ *  Configures the tx scramble of channel 1
+ */
+#define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_M  (DMA2D_OUT_COLOR_PARAM_H0_CH1_V << DMA2D_OUT_COLOR_PARAM_H0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_M  (DMA2D_OUT_COLOR_PARAM_H1_CH1_V << DMA2D_OUT_COLOR_PARAM_H1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_M  (DMA2D_OUT_COLOR_PARAM_M0_CH1_V << DMA2D_OUT_COLOR_PARAM_M0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_M  (DMA2D_OUT_COLOR_PARAM_M1_CH1_V << DMA2D_OUT_COLOR_PARAM_M1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_M  (DMA2D_OUT_COLOR_PARAM_L0_CH1_V << DMA2D_OUT_COLOR_PARAM_L0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_M  (DMA2D_OUT_COLOR_PARAM_L1_CH1_V << DMA2D_OUT_COLOR_PARAM_L1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH1_REG register
+ *  Configures the tx etm of channel 1
+ */
+#define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168)
+/** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH1    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH1_M  (DMA2D_OUT_ETM_EN_CH1_V << DMA2D_OUT_ETM_EN_CH1_S)
+#define DMA2D_OUT_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH1_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_M  (DMA2D_OUT_ETM_LOOP_EN_CH1_V << DMA2D_OUT_ETM_LOOP_EN_CH1_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_M  (DMA2D_OUT_DSCR_TASK_MAK_CH1_V << DMA2D_OUT_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH1_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH1_REG (DR_REG_DMA2D_BASE + 0x16c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH1 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH1 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S  14
+
+/** DMA2D_OUT_CONF0_CH2_REG register
+ *  Configures the tx direction of channel 2
+ */
+#define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200)
+/** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH2    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH2_M  (DMA2D_OUT_AUTO_WRBACK_CH2_V << DMA2D_OUT_AUTO_WRBACK_CH2_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH2_S  0
+/** DMA2D_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH2    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH2_M  (DMA2D_OUT_EOF_MODE_CH2_V << DMA2D_OUT_EOF_MODE_CH2_S)
+#define DMA2D_OUT_EOF_MODE_CH2_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH2_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH2    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH2_M  (DMA2D_OUTDSCR_BURST_EN_CH2_V << DMA2D_OUTDSCR_BURST_EN_CH2_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH2_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH2    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH2_M  (DMA2D_OUT_ECC_AES_EN_CH2_V << DMA2D_OUT_ECC_AES_EN_CH2_S)
+#define DMA2D_OUT_ECC_AES_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH2_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH2    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH2_M  (DMA2D_OUT_CHECK_OWNER_CH2_V << DMA2D_OUT_CHECK_OWNER_CH2_S)
+#define DMA2D_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH2_S  4
+/** DMA2D_OUT_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH2    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH2_M  (DMA2D_OUT_LOOP_TEST_CH2_V << DMA2D_OUT_LOOP_TEST_CH2_S)
+#define DMA2D_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH2_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH2_V << DMA2D_OUT_MEM_BURST_LENGTH_CH2_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH2    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_M  (DMA2D_OUT_DSCR_PORT_EN_CH2_V << DMA2D_OUT_DSCR_PORT_EN_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_M  (DMA2D_OUT_PAGE_BOUND_EN_CH2_V << DMA2D_OUT_PAGE_BOUND_EN_CH2_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_S  12
+/** DMA2D_OUT_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH2    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH2_M  (DMA2D_OUT_REORDER_EN_CH2_V << DMA2D_OUT_REORDER_EN_CH2_S)
+#define DMA2D_OUT_REORDER_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH2_S  16
+/** DMA2D_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH2    (BIT(24))
+#define DMA2D_OUT_RST_CH2_M  (DMA2D_OUT_RST_CH2_V << DMA2D_OUT_RST_CH2_S)
+#define DMA2D_OUT_RST_CH2_V  0x00000001U
+#define DMA2D_OUT_RST_CH2_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH2    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH2_M  (DMA2D_OUT_CMD_DISABLE_CH2_V << DMA2D_OUT_CMD_DISABLE_CH2_S)
+#define DMA2D_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH2_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** DMA2D_OUT_INT_RAW_CH2_REG register
+ *  Raw interrupt status of TX channel 2
+ */
+#define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204)
+/** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_RAW_M  (DMA2D_OUT_DONE_CH2_INT_RAW_V << DMA2D_OUT_DONE_CH2_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_RAW_M  (DMA2D_OUT_EOF_CH2_INT_RAW_V << DMA2D_OUT_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of TX channel 2
+ */
+#define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208)
+/** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ENA_M  (DMA2D_OUT_DONE_CH2_INT_ENA_V << DMA2D_OUT_DONE_CH2_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ENA_M  (DMA2D_OUT_EOF_CH2_INT_ENA_V << DMA2D_OUT_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt status of TX channel 2
+ */
+#define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c)
+/** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ST_M  (DMA2D_OUT_DONE_CH2_INT_ST_V << DMA2D_OUT_DONE_CH2_INT_ST_S)
+#define DMA2D_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ST_M  (DMA2D_OUT_EOF_CH2_INT_ST_V << DMA2D_OUT_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of TX channel 2
+ */
+#define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210)
+/** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_CLR_M  (DMA2D_OUT_DONE_CH2_INT_CLR_V << DMA2D_OUT_DONE_CH2_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_CLR_M  (DMA2D_OUT_EOF_CH2_INT_CLR_V << DMA2D_OUT_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH2_REG register
+ *  Represents the status of the tx fifo of channel 2
+ */
+#define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214)
+/** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH2    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH2_M  (DMA2D_OUTFIFO_FULL_L2_CH2_V << DMA2D_OUTFIFO_FULL_L2_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH2_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_M  (DMA2D_OUTFIFO_EMPTY_L2_CH2_V << DMA2D_OUTFIFO_EMPTY_L2_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH2    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_M  (DMA2D_OUTFIFO_CNT_L2_CH2_V << DMA2D_OUTFIFO_CNT_L2_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH2_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH2_V << DMA2D_OUT_REMAIN_UNDER_1B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH2_V << DMA2D_OUT_REMAIN_UNDER_2B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH2_V << DMA2D_OUT_REMAIN_UNDER_3B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH2_V << DMA2D_OUT_REMAIN_UNDER_4B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH2_V << DMA2D_OUT_REMAIN_UNDER_5B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH2_V << DMA2D_OUT_REMAIN_UNDER_6B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH2_V << DMA2D_OUT_REMAIN_UNDER_7B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH2_V << DMA2D_OUT_REMAIN_UNDER_8B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH2    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH2_M  (DMA2D_OUTFIFO_FULL_L1_CH2_V << DMA2D_OUTFIFO_FULL_L1_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH2_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_M  (DMA2D_OUTFIFO_EMPTY_L1_CH2_V << DMA2D_OUTFIFO_EMPTY_L1_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_M  (DMA2D_OUTFIFO_CNT_L1_CH2_V << DMA2D_OUTFIFO_CNT_L1_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH2    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH2_M  (DMA2D_OUTFIFO_FULL_L3_CH2_V << DMA2D_OUTFIFO_FULL_L3_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH2_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_M  (DMA2D_OUTFIFO_EMPTY_L3_CH2_V << DMA2D_OUTFIFO_EMPTY_L3_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_M  (DMA2D_OUTFIFO_CNT_L3_CH2_V << DMA2D_OUTFIFO_CNT_L3_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_S  24
+
+/** DMA2D_OUT_PUSH_CH2_REG register
+ *  Configures the tx fifo of channel 2
+ */
+#define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218)
+/** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH2    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_M  (DMA2D_OUTFIFO_WDATA_CH2_V << DMA2D_OUTFIFO_WDATA_CH2_S)
+#define DMA2D_OUTFIFO_WDATA_CH2_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_S  0
+/** DMA2D_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH2    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH2_M  (DMA2D_OUTFIFO_PUSH_CH2_V << DMA2D_OUTFIFO_PUSH_CH2_S)
+#define DMA2D_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH2_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH2_REG register
+ *  Configures the tx descriptor operations of channel 2
+ */
+#define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c)
+/** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH2    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH2_M  (DMA2D_OUTLINK_STOP_CH2_V << DMA2D_OUTLINK_STOP_CH2_S)
+#define DMA2D_OUTLINK_STOP_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH2_S  20
+/** DMA2D_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH2    (BIT(21))
+#define DMA2D_OUTLINK_START_CH2_M  (DMA2D_OUTLINK_START_CH2_V << DMA2D_OUTLINK_START_CH2_S)
+#define DMA2D_OUTLINK_START_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH2_S  21
+/** DMA2D_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH2    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH2_M  (DMA2D_OUTLINK_RESTART_CH2_V << DMA2D_OUTLINK_RESTART_CH2_S)
+#define DMA2D_OUTLINK_RESTART_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH2_S  22
+/** DMA2D_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH2    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH2_M  (DMA2D_OUTLINK_PARK_CH2_V << DMA2D_OUTLINK_PARK_CH2_S)
+#define DMA2D_OUTLINK_PARK_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH2_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH2_REG register
+ *  Configures the tx descriptor address of channel 2
+ */
+#define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220)
+/** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_M  (DMA2D_OUTLINK_ADDR_CH2_V << DMA2D_OUTLINK_ADDR_CH2_S)
+#define DMA2D_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_S  0
+
+/** DMA2D_OUT_STATE_CH2_REG register
+ *  Represents the working status of the tx descriptor of channel 2
+ */
+#define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_M  (DMA2D_OUTLINK_DSCR_ADDR_CH2_V << DMA2D_OUTLINK_DSCR_ADDR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_S  0
+/** DMA2D_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_M  (DMA2D_OUT_DSCR_STATE_CH2_V << DMA2D_OUT_DSCR_STATE_CH2_S)
+#define DMA2D_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_S  18
+/** DMA2D_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH2    0x0000000FU
+#define DMA2D_OUT_STATE_CH2_M  (DMA2D_OUT_STATE_CH2_V << DMA2D_OUT_STATE_CH2_S)
+#define DMA2D_OUT_STATE_CH2_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH2_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH2    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH2_M  (DMA2D_OUT_RESET_AVAIL_CH2_V << DMA2D_OUT_RESET_AVAIL_CH2_S)
+#define DMA2D_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH2_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228)
+/** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_M  (DMA2D_OUT_EOF_DES_ADDR_CH2_V << DMA2D_OUT_EOF_DES_ADDR_CH2_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c)
+/** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_M  (DMA2D_OUTLINK_DSCR_CH2_V << DMA2D_OUTLINK_DSCR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230)
+/** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_M  (DMA2D_OUTLINK_DSCR_BF0_CH2_V << DMA2D_OUTLINK_DSCR_BF0_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234)
+/** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_M  (DMA2D_OUTLINK_DSCR_BF1_CH2_V << DMA2D_OUTLINK_DSCR_BF1_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH2_REG register
+ *  Configures the tx peripheral of channel 2
+ */
+#define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238)
+/** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH2    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_M  (DMA2D_OUT_PERI_SEL_CH2_V << DMA2D_OUT_PERI_SEL_CH2_S)
+#define DMA2D_OUT_PERI_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_S  0
+
+/** DMA2D_OUT_ARB_CH2_REG register
+ *  Configures the tx arbiter of channel 2
+ */
+#define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH2    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH2_M  (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH2_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH2_S  4
+/** DMA2D_OUT_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:6]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_H_CH2    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH2_M  (DMA2D_OUT_ARB_PRIORITY_H_CH2_V << DMA2D_OUT_ARB_PRIORITY_H_CH2_S)
+#define DMA2D_OUT_ARB_PRIORITY_H_CH2_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH2_S  6
+
+/** DMA2D_OUT_RO_STATUS_CH2_REG register
+ *  Represents the status of the tx reorder module of channel 2
+ */
+#define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240)
+/** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH2    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_M  (DMA2D_OUTFIFO_RO_CNT_CH2_V << DMA2D_OUTFIFO_RO_CNT_CH2_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH2_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH2 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_M  (DMA2D_OUT_RO_WR_STATE_CH2_V << DMA2D_OUT_RO_WR_STATE_CH2_S)
+#define DMA2D_OUT_RO_WR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH2 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_M  (DMA2D_OUT_RO_RD_STATE_CH2_V << DMA2D_OUT_RO_RD_STATE_CH2_S)
+#define DMA2D_OUT_RO_RD_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH2 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH2    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_M  (DMA2D_OUT_PIXEL_BYTE_CH2_V << DMA2D_OUT_PIXEL_BYTE_CH2_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH2_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH2 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH2_V << DMA2D_OUT_BURST_BLOCK_NUM_CH2_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH2_REG register
+ *  Configures the tx color convert of channel 2
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH2_V << DMA2D_OUT_COLOR_INPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH2_REG register
+ *  Configures the tx scramble of channel 2
+ */
+#define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_M  (DMA2D_OUT_COLOR_PARAM_H0_CH2_V << DMA2D_OUT_COLOR_PARAM_H0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_M  (DMA2D_OUT_COLOR_PARAM_H1_CH2_V << DMA2D_OUT_COLOR_PARAM_H1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_M  (DMA2D_OUT_COLOR_PARAM_M0_CH2_V << DMA2D_OUT_COLOR_PARAM_M0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_M  (DMA2D_OUT_COLOR_PARAM_M1_CH2_V << DMA2D_OUT_COLOR_PARAM_M1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_M  (DMA2D_OUT_COLOR_PARAM_L0_CH2_V << DMA2D_OUT_COLOR_PARAM_L0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_M  (DMA2D_OUT_COLOR_PARAM_L1_CH2_V << DMA2D_OUT_COLOR_PARAM_L1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH2_REG register
+ *  Configures the tx etm of channel 2
+ */
+#define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268)
+/** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH2    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH2_M  (DMA2D_OUT_ETM_EN_CH2_V << DMA2D_OUT_ETM_EN_CH2_S)
+#define DMA2D_OUT_ETM_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH2_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH2    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_M  (DMA2D_OUT_ETM_LOOP_EN_CH2_V << DMA2D_OUT_ETM_LOOP_EN_CH2_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_M  (DMA2D_OUT_DSCR_TASK_MAK_CH2_V << DMA2D_OUT_DSCR_TASK_MAK_CH2_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH2_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH2_REG (DR_REG_DMA2D_BASE + 0x26c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH2 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH2 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S  14
+
+/** DMA2D_OUT_CONF0_CH3_REG register
+ *  Configures the tx direction of channel 3
+ */
+#define DMA2D_OUT_CONF0_CH3_REG (DR_REG_DMA2D_BASE + 0x300)
+/** DMA2D_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH3    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH3_M  (DMA2D_OUT_AUTO_WRBACK_CH3_V << DMA2D_OUT_AUTO_WRBACK_CH3_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH3_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH3_S  0
+/** DMA2D_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH3    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH3_M  (DMA2D_OUT_EOF_MODE_CH3_V << DMA2D_OUT_EOF_MODE_CH3_S)
+#define DMA2D_OUT_EOF_MODE_CH3_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH3_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH3    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH3_M  (DMA2D_OUTDSCR_BURST_EN_CH3_V << DMA2D_OUTDSCR_BURST_EN_CH3_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH3_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH3_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH3    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH3_M  (DMA2D_OUT_ECC_AES_EN_CH3_V << DMA2D_OUT_ECC_AES_EN_CH3_S)
+#define DMA2D_OUT_ECC_AES_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH3_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH3    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH3_M  (DMA2D_OUT_CHECK_OWNER_CH3_V << DMA2D_OUT_CHECK_OWNER_CH3_S)
+#define DMA2D_OUT_CHECK_OWNER_CH3_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH3_S  4
+/** DMA2D_OUT_LOOP_TEST_CH3 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH3    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH3_M  (DMA2D_OUT_LOOP_TEST_CH3_V << DMA2D_OUT_LOOP_TEST_CH3_S)
+#define DMA2D_OUT_LOOP_TEST_CH3_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH3_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH3_V << DMA2D_OUT_MEM_BURST_LENGTH_CH3_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH3 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH3    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH3_M  (DMA2D_OUT_DSCR_PORT_EN_CH3_V << DMA2D_OUT_DSCR_PORT_EN_CH3_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH3_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3_M  (DMA2D_OUT_PAGE_BOUND_EN_CH3_V << DMA2D_OUT_PAGE_BOUND_EN_CH3_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3_S  12
+/** DMA2D_OUT_REORDER_EN_CH3 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH3    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH3_M  (DMA2D_OUT_REORDER_EN_CH3_V << DMA2D_OUT_REORDER_EN_CH3_S)
+#define DMA2D_OUT_REORDER_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH3_S  16
+/** DMA2D_OUT_RST_CH3 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH3    (BIT(24))
+#define DMA2D_OUT_RST_CH3_M  (DMA2D_OUT_RST_CH3_V << DMA2D_OUT_RST_CH3_S)
+#define DMA2D_OUT_RST_CH3_V  0x00000001U
+#define DMA2D_OUT_RST_CH3_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH3    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH3_M  (DMA2D_OUT_CMD_DISABLE_CH3_V << DMA2D_OUT_CMD_DISABLE_CH3_S)
+#define DMA2D_OUT_CMD_DISABLE_CH3_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH3_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S  26
+
+/** DMA2D_OUT_INT_RAW_CH3_REG register
+ *  Raw interrupt status of TX channel 3
+ */
+#define DMA2D_OUT_INT_RAW_CH3_REG (DR_REG_DMA2D_BASE + 0x304)
+/** DMA2D_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_RAW_M  (DMA2D_OUT_DONE_CH3_INT_RAW_V << DMA2D_OUT_DONE_CH3_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_RAW_M  (DMA2D_OUT_EOF_CH3_INT_RAW_V << DMA2D_OUT_EOF_CH3_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH3_REG register
+ *  Interrupt enable bits of TX channel 3
+ */
+#define DMA2D_OUT_INT_ENA_CH3_REG (DR_REG_DMA2D_BASE + 0x308)
+/** DMA2D_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_ENA_M  (DMA2D_OUT_DONE_CH3_INT_ENA_V << DMA2D_OUT_DONE_CH3_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_ENA_M  (DMA2D_OUT_EOF_CH3_INT_ENA_V << DMA2D_OUT_EOF_CH3_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH3_REG register
+ *  Masked interrupt status of TX channel 3
+ */
+#define DMA2D_OUT_INT_ST_CH3_REG (DR_REG_DMA2D_BASE + 0x30c)
+/** DMA2D_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_ST_M  (DMA2D_OUT_DONE_CH3_INT_ST_V << DMA2D_OUT_DONE_CH3_INT_ST_S)
+#define DMA2D_OUT_DONE_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_ST_M  (DMA2D_OUT_EOF_CH3_INT_ST_V << DMA2D_OUT_EOF_CH3_INT_ST_S)
+#define DMA2D_OUT_EOF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH3_REG register
+ *  Interrupt clear bits of TX channel 3
+ */
+#define DMA2D_OUT_INT_CLR_CH3_REG (DR_REG_DMA2D_BASE + 0x310)
+/** DMA2D_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_CLR_M  (DMA2D_OUT_DONE_CH3_INT_CLR_V << DMA2D_OUT_DONE_CH3_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_CLR_M  (DMA2D_OUT_EOF_CH3_INT_CLR_V << DMA2D_OUT_EOF_CH3_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH3_REG register
+ *  Represents the status of the tx fifo of channel 3
+ */
+#define DMA2D_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x314)
+/** DMA2D_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH3    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH3_M  (DMA2D_OUTFIFO_FULL_L2_CH3_V << DMA2D_OUTFIFO_FULL_L2_CH3_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH3_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3_M  (DMA2D_OUTFIFO_EMPTY_L2_CH3_V << DMA2D_OUTFIFO_EMPTY_L2_CH3_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH3    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH3_M  (DMA2D_OUTFIFO_CNT_L2_CH3_V << DMA2D_OUTFIFO_CNT_L2_CH3_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH3_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH3_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH3_V << DMA2D_OUT_REMAIN_UNDER_1B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH3_V << DMA2D_OUT_REMAIN_UNDER_2B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH3_V << DMA2D_OUT_REMAIN_UNDER_3B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH3_V << DMA2D_OUT_REMAIN_UNDER_4B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH3 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH3_V << DMA2D_OUT_REMAIN_UNDER_5B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH3 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH3_V << DMA2D_OUT_REMAIN_UNDER_6B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH3 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH3_V << DMA2D_OUT_REMAIN_UNDER_7B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH3 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH3_V << DMA2D_OUT_REMAIN_UNDER_8B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH3    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH3_M  (DMA2D_OUTFIFO_FULL_L1_CH3_V << DMA2D_OUTFIFO_FULL_L1_CH3_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH3_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3_M  (DMA2D_OUTFIFO_EMPTY_L1_CH3_V << DMA2D_OUTFIFO_EMPTY_L1_CH3_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH3    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH3_M  (DMA2D_OUTFIFO_CNT_L1_CH3_V << DMA2D_OUTFIFO_CNT_L1_CH3_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH3_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH3_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH3    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH3_M  (DMA2D_OUTFIFO_FULL_L3_CH3_V << DMA2D_OUTFIFO_FULL_L3_CH3_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH3_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3_M  (DMA2D_OUTFIFO_EMPTY_L3_CH3_V << DMA2D_OUTFIFO_EMPTY_L3_CH3_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH3    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH3_M  (DMA2D_OUTFIFO_CNT_L3_CH3_V << DMA2D_OUTFIFO_CNT_L3_CH3_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH3_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH3_S  24
+
+/** DMA2D_OUT_PUSH_CH3_REG register
+ *  Configures the tx fifo of channel 3
+ */
+#define DMA2D_OUT_PUSH_CH3_REG (DR_REG_DMA2D_BASE + 0x318)
+/** DMA2D_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH3    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH3_M  (DMA2D_OUTFIFO_WDATA_CH3_V << DMA2D_OUTFIFO_WDATA_CH3_S)
+#define DMA2D_OUTFIFO_WDATA_CH3_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH3_S  0
+/** DMA2D_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH3    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH3_M  (DMA2D_OUTFIFO_PUSH_CH3_V << DMA2D_OUTFIFO_PUSH_CH3_S)
+#define DMA2D_OUTFIFO_PUSH_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH3_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH3_REG register
+ *  Configures the tx descriptor operations of channel 3
+ */
+#define DMA2D_OUT_LINK_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x31c)
+/** DMA2D_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH3    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH3_M  (DMA2D_OUTLINK_STOP_CH3_V << DMA2D_OUTLINK_STOP_CH3_S)
+#define DMA2D_OUTLINK_STOP_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH3_S  20
+/** DMA2D_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH3    (BIT(21))
+#define DMA2D_OUTLINK_START_CH3_M  (DMA2D_OUTLINK_START_CH3_V << DMA2D_OUTLINK_START_CH3_S)
+#define DMA2D_OUTLINK_START_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH3_S  21
+/** DMA2D_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH3    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH3_M  (DMA2D_OUTLINK_RESTART_CH3_V << DMA2D_OUTLINK_RESTART_CH3_S)
+#define DMA2D_OUTLINK_RESTART_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH3_S  22
+/** DMA2D_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH3    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH3_M  (DMA2D_OUTLINK_PARK_CH3_V << DMA2D_OUTLINK_PARK_CH3_S)
+#define DMA2D_OUTLINK_PARK_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH3_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH3_REG register
+ *  Configures the tx descriptor address of channel 3
+ */
+#define DMA2D_OUT_LINK_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x320)
+/** DMA2D_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH3_M  (DMA2D_OUTLINK_ADDR_CH3_V << DMA2D_OUTLINK_ADDR_CH3_S)
+#define DMA2D_OUTLINK_ADDR_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH3_S  0
+
+/** DMA2D_OUT_STATE_CH3_REG register
+ *  Represents the working status of the tx descriptor of channel 3
+ */
+#define DMA2D_OUT_STATE_CH3_REG (DR_REG_DMA2D_BASE + 0x324)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3_M  (DMA2D_OUTLINK_DSCR_ADDR_CH3_V << DMA2D_OUTLINK_DSCR_ADDR_CH3_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3_S  0
+/** DMA2D_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH3    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH3_M  (DMA2D_OUT_DSCR_STATE_CH3_V << DMA2D_OUT_DSCR_STATE_CH3_S)
+#define DMA2D_OUT_DSCR_STATE_CH3_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH3_S  18
+/** DMA2D_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH3    0x0000000FU
+#define DMA2D_OUT_STATE_CH3_M  (DMA2D_OUT_STATE_CH3_V << DMA2D_OUT_STATE_CH3_S)
+#define DMA2D_OUT_STATE_CH3_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH3_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH3 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH3    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH3_M  (DMA2D_OUT_RESET_AVAIL_CH3_V << DMA2D_OUT_RESET_AVAIL_CH3_S)
+#define DMA2D_OUT_RESET_AVAIL_CH3_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH3_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x328)
+/** DMA2D_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_M  (DMA2D_OUT_EOF_DES_ADDR_CH3_V << DMA2D_OUT_EOF_DES_ADDR_CH3_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_S  0
+
+/** DMA2D_OUT_DSCR_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_DSCR_CH3_REG (DR_REG_DMA2D_BASE + 0x32c)
+/** DMA2D_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH3_M  (DMA2D_OUTLINK_DSCR_CH3_V << DMA2D_OUTLINK_DSCR_CH3_S)
+#define DMA2D_OUTLINK_DSCR_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH3_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA2D_BASE + 0x330)
+/** DMA2D_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH3_M  (DMA2D_OUTLINK_DSCR_BF0_CH3_V << DMA2D_OUTLINK_DSCR_BF0_CH3_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH3_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA2D_BASE + 0x334)
+/** DMA2D_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH3_M  (DMA2D_OUTLINK_DSCR_BF1_CH3_V << DMA2D_OUTLINK_DSCR_BF1_CH3_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH3_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH3_REG register
+ *  Configures the tx peripheral of channel 3
+ */
+#define DMA2D_OUT_PERI_SEL_CH3_REG (DR_REG_DMA2D_BASE + 0x338)
+/** DMA2D_OUT_PERI_SEL_CH3 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH3    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH3_M  (DMA2D_OUT_PERI_SEL_CH3_V << DMA2D_OUT_PERI_SEL_CH3_S)
+#define DMA2D_OUT_PERI_SEL_CH3_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH3_S  0
+
+/** DMA2D_OUT_ARB_CH3_REG register
+ *  Configures the tx arbiter of channel 3
+ */
+#define DMA2D_OUT_ARB_CH3_REG (DR_REG_DMA2D_BASE + 0x33c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH3_V << DMA2D_OUT_ARB_TOKEN_NUM_CH3_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH3    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH3_M  (DMA2D_OUT_ARB_PRIORITY_CH3_V << DMA2D_OUT_ARB_PRIORITY_CH3_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH3_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH3_S  4
+/** DMA2D_OUT_ARB_PRIORITY_H_CH3 : R/W; bitpos: [7:6]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_H_CH3    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH3_M  (DMA2D_OUT_ARB_PRIORITY_H_CH3_V << DMA2D_OUT_ARB_PRIORITY_H_CH3_S)
+#define DMA2D_OUT_ARB_PRIORITY_H_CH3_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_H_CH3_S  6
+
+/** DMA2D_OUT_RO_STATUS_CH3_REG register
+ *  Represents the status of the tx reorder module of channel 3
+ */
+#define DMA2D_OUT_RO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x340)
+/** DMA2D_OUTFIFO_RO_CNT_CH3 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH3    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH3_M  (DMA2D_OUTFIFO_RO_CNT_CH3_V << DMA2D_OUTFIFO_RO_CNT_CH3_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH3_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH3_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH3 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH3    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH3_M  (DMA2D_OUT_RO_WR_STATE_CH3_V << DMA2D_OUT_RO_WR_STATE_CH3_S)
+#define DMA2D_OUT_RO_WR_STATE_CH3_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH3_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH3 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH3    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH3_M  (DMA2D_OUT_RO_RD_STATE_CH3_V << DMA2D_OUT_RO_RD_STATE_CH3_S)
+#define DMA2D_OUT_RO_RD_STATE_CH3_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH3_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH3 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH3    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH3_M  (DMA2D_OUT_PIXEL_BYTE_CH3_V << DMA2D_OUT_PIXEL_BYTE_CH3_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH3_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH3_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH3 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH3_V << DMA2D_OUT_BURST_BLOCK_NUM_CH3_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH3_REG register
+ *  Configures the tx color convert of channel 3
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH3_REG (DR_REG_DMA2D_BASE + 0x348)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH3 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH3_V << DMA2D_OUT_COLOR_INPUT_SEL_CH3_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH3_REG register
+ *  Configures the tx scramble of channel 3
+ */
+#define DMA2D_OUT_SCRAMBLE_CH3_REG (DR_REG_DMA2D_BASE + 0x34c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH3_REG (DR_REG_DMA2D_BASE + 0x350)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH3 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3_M  (DMA2D_OUT_COLOR_PARAM_H0_CH3_V << DMA2D_OUT_COLOR_PARAM_H0_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH3_REG (DR_REG_DMA2D_BASE + 0x354)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH3 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3_M  (DMA2D_OUT_COLOR_PARAM_H1_CH3_V << DMA2D_OUT_COLOR_PARAM_H1_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH3_REG (DR_REG_DMA2D_BASE + 0x358)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH3 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3_M  (DMA2D_OUT_COLOR_PARAM_M0_CH3_V << DMA2D_OUT_COLOR_PARAM_M0_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH3_REG (DR_REG_DMA2D_BASE + 0x35c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH3 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3_M  (DMA2D_OUT_COLOR_PARAM_M1_CH3_V << DMA2D_OUT_COLOR_PARAM_M1_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH3_REG (DR_REG_DMA2D_BASE + 0x360)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH3 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3_M  (DMA2D_OUT_COLOR_PARAM_L0_CH3_V << DMA2D_OUT_COLOR_PARAM_L0_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH3_REG (DR_REG_DMA2D_BASE + 0x364)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH3 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3_M  (DMA2D_OUT_COLOR_PARAM_L1_CH3_V << DMA2D_OUT_COLOR_PARAM_L1_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH3_REG register
+ *  Configures the tx etm of channel 3
+ */
+#define DMA2D_OUT_ETM_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x368)
+/** DMA2D_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH3    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH3_M  (DMA2D_OUT_ETM_EN_CH3_V << DMA2D_OUT_ETM_EN_CH3_S)
+#define DMA2D_OUT_ETM_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH3_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH3    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH3_M  (DMA2D_OUT_ETM_LOOP_EN_CH3_V << DMA2D_OUT_ETM_LOOP_EN_CH3_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH3_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3_M  (DMA2D_OUT_DSCR_TASK_MAK_CH3_V << DMA2D_OUT_DSCR_TASK_MAK_CH3_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH3_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH3_REG (DR_REG_DMA2D_BASE + 0x36c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH3 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH3 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S  14
+
+/** DMA2D_IN_CONF0_CH0_REG register
+ *  Configures the rx direction of channel 0
+ */
+#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500)
+/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH0    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH0_M  (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH0_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH0_S  0
+/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH0_M  (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S)
+#define DMA2D_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH0_S  2
+/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH0_M  (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S)
+#define DMA2D_IN_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH0_S  3
+/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH0_M  (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S)
+#define DMA2D_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH0_S  4
+/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH0_M  (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S)
+#define DMA2D_IN_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH0_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M  (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH0_M  (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_M  (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH0_M  (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S)
+#define DMA2D_IN_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH0_S  16
+/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH0    (BIT(24))
+#define DMA2D_IN_RST_CH0_M  (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S)
+#define DMA2D_IN_RST_CH0_V  0x00000001U
+#define DMA2D_IN_RST_CH0_S  24
+/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH0_M  (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S)
+#define DMA2D_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH0_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_IN_INT_RAW_CH0_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504)
+/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_RAW_M  (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S)
+#define DMA2D_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508)
+/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ENA_M  (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S)
+#define DMA2D_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH0_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c)
+/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ST_M  (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S)
+#define DMA2D_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M  (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M  (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510)
+/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_CLR_M  (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S)
+#define DMA2D_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH0_REG register
+ *  Represents the status of the rx fifo of channel 0
+ */
+#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514)
+/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH0_M  (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S)
+#define DMA2D_INFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH0_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH0_M  (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_M  (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S)
+#define DMA2D_INFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M  (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M  (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M  (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M  (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M  (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M  (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M  (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M  (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH0_M  (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S)
+#define DMA2D_INFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH0_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH0_M  (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_M  (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S)
+#define DMA2D_INFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_S  17
+/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH0_M  (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S)
+#define DMA2D_INFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH0_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH0_M  (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_M  (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S)
+#define DMA2D_INFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_IN_POP_CH0_REG register
+ *  Configures the rx fifo of channel 0
+ */
+#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518)
+/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH0    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_M  (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S)
+#define DMA2D_INFIFO_RDATA_CH0_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_S  0
+/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH0    (BIT(11))
+#define DMA2D_INFIFO_POP_CH0_M  (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S)
+#define DMA2D_INFIFO_POP_CH0_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH0_S  11
+
+/** DMA2D_IN_LINK_CONF_CH0_REG register
+ *  Configures the rx descriptor operations of channel 0
+ */
+#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c)
+/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH0    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH0_M  (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S)
+#define DMA2D_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH0_S  20
+/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH0    (BIT(21))
+#define DMA2D_INLINK_STOP_CH0_M  (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S)
+#define DMA2D_INLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH0_S  21
+/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH0    (BIT(22))
+#define DMA2D_INLINK_START_CH0_M  (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S)
+#define DMA2D_INLINK_START_CH0_V  0x00000001U
+#define DMA2D_INLINK_START_CH0_S  22
+/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH0    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH0_M  (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S)
+#define DMA2D_INLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH0_S  23
+/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH0    (BIT(24))
+#define DMA2D_INLINK_PARK_CH0_M  (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S)
+#define DMA2D_INLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH0_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH0_REG register
+ *  Configures the rx descriptor address of channel 0
+ */
+#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520)
+/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_M  (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S)
+#define DMA2D_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_S  0
+
+/** DMA2D_IN_STATE_CH0_REG register
+ *  Represents the working status of the rx descriptor of channel 0
+ */
+#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524)
+/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_M  (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_M  (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S)
+#define DMA2D_IN_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_S  18
+/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH0    0x00000007U
+#define DMA2D_IN_STATE_CH0_M  (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S)
+#define DMA2D_IN_STATE_CH0_V  0x00000007U
+#define DMA2D_IN_STATE_CH0_S  20
+/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH0    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH0_M  (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S)
+#define DMA2D_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH0_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_DSCR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530)
+/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_M  (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S)
+#define DMA2D_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534)
+/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_M  (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S)
+#define DMA2D_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538)
+/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_M  (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S)
+#define DMA2D_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_IN_PERI_SEL_CH0_REG register
+ *  Configures the rx peripheral of channel 0
+ */
+#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c)
+/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH0    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_M  (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S)
+#define DMA2D_IN_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_S  0
+
+/** DMA2D_IN_ARB_CH0_REG register
+ *  Configures the rx arbiter of channel 0
+ */
+#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M  (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH0    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH0_M  (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S)
+#define DMA2D_IN_ARB_PRIORITY_CH0_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH0_S  4
+/** DMA2D_IN_ARB_PRIORITY_H_CH0 : R/W; bitpos: [7:5]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_H_CH0    0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH0_M  (DMA2D_IN_ARB_PRIORITY_H_CH0_V << DMA2D_IN_ARB_PRIORITY_H_CH0_S)
+#define DMA2D_IN_ARB_PRIORITY_H_CH0_V  0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH0_S  5
+
+/** DMA2D_IN_RO_STATUS_CH0_REG register
+ *  Represents the status of the rx reorder module of channel 0
+ */
+#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544)
+/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH0    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_M  (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S)
+#define DMA2D_INFIFO_RO_CNT_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_S  0
+/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_M  (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S)
+#define DMA2D_IN_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_S  5
+/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_M  (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S)
+#define DMA2D_IN_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_M  (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S)
+#define DMA2D_IN_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M  (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S  13
+
+/** DMA2D_IN_RO_PD_CONF_CH0_REG register
+ *  Configures the rx reorder memory of channel 0
+ */
+#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548)
+/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M  (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_IN_COLOR_CONVERT_CH0_REG register
+ *  Configures the Rx color convert of channel 0
+ */
+#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c)
+/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+ */
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M  (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+ *  1: YUV422      2: YUV444/420      7: disable color space convert
+ */
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M  (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_IN_SCRAMBLE_CH0_REG register
+ *  Configures the rx scramble of channel 0
+ */
+#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550)
+/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S  0
+/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0;
+ *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+ *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S  3
+
+/** DMA2D_IN_COLOR_PARAM0_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554)
+/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_M  (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM1_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558)
+/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_M  (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM2_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c)
+/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_M  (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM3_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560)
+/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_M  (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM4_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564)
+/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_M  (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM5_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568)
+/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_M  (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_IN_ETM_CONF_CH0_REG register
+ *  Configures the rx etm of channel 0
+ */
+#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c)
+/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH0    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH0_M  (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S)
+#define DMA2D_IN_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH0_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH0_M  (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_M  (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_IN_CONF0_CH1_REG register
+ *  Configures the rx direction of channel 1
+ */
+#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600)
+/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH1    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH1_M  (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH1_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH1_S  0
+/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH1_M  (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S)
+#define DMA2D_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH1_S  2
+/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH1_M  (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S)
+#define DMA2D_IN_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH1_S  3
+/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH1_M  (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S)
+#define DMA2D_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH1_S  4
+/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH1_M  (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S)
+#define DMA2D_IN_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH1_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M  (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH1_M  (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_M  (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH1_M  (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S)
+#define DMA2D_IN_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH1_S  16
+/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH1    (BIT(24))
+#define DMA2D_IN_RST_CH1_M  (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S)
+#define DMA2D_IN_RST_CH1_V  0x00000001U
+#define DMA2D_IN_RST_CH1_S  24
+/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH1_M  (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S)
+#define DMA2D_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH1_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_IN_INT_RAW_CH1_REG register
+ *  Raw interrupt status of RX channel 1
+ */
+#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604)
+/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_RAW_M  (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S)
+#define DMA2D_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of RX channel 1
+ */
+#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608)
+/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ENA_M  (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S)
+#define DMA2D_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH1_REG register
+ *  Masked interrupt status of RX channel 1
+ */
+#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c)
+/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ST_M  (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S)
+#define DMA2D_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M  (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M  (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of RX channel 1
+ */
+#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610)
+/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_CLR_M  (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S)
+#define DMA2D_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH1_REG register
+ *  Represents the status of the rx fifo of channel 1
+ */
+#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614)
+/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH1_M  (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S)
+#define DMA2D_INFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH1_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH1_M  (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_M  (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S)
+#define DMA2D_INFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M  (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M  (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M  (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M  (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M  (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M  (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M  (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M  (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH1_M  (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S)
+#define DMA2D_INFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH1_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH1_M  (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_M  (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S)
+#define DMA2D_INFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_S  17
+/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH1_M  (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S)
+#define DMA2D_INFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH1_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH1_M  (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_M  (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S)
+#define DMA2D_INFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_IN_POP_CH1_REG register
+ *  Configures the rx fifo of channel 1
+ */
+#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618)
+/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH1    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_M  (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S)
+#define DMA2D_INFIFO_RDATA_CH1_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_S  0
+/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH1    (BIT(11))
+#define DMA2D_INFIFO_POP_CH1_M  (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S)
+#define DMA2D_INFIFO_POP_CH1_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH1_S  11
+
+/** DMA2D_IN_LINK_CONF_CH1_REG register
+ *  Configures the rx descriptor operations of channel 1
+ */
+#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c)
+/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH1    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH1_M  (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S)
+#define DMA2D_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH1_S  20
+/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH1    (BIT(21))
+#define DMA2D_INLINK_STOP_CH1_M  (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S)
+#define DMA2D_INLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH1_S  21
+/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH1    (BIT(22))
+#define DMA2D_INLINK_START_CH1_M  (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S)
+#define DMA2D_INLINK_START_CH1_V  0x00000001U
+#define DMA2D_INLINK_START_CH1_S  22
+/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH1    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH1_M  (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S)
+#define DMA2D_INLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH1_S  23
+/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH1    (BIT(24))
+#define DMA2D_INLINK_PARK_CH1_M  (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S)
+#define DMA2D_INLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH1_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH1_REG register
+ *  Configures the rx descriptor address of channel 1
+ */
+#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620)
+/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_M  (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S)
+#define DMA2D_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_S  0
+
+/** DMA2D_IN_STATE_CH1_REG register
+ *  Represents the working status of the rx descriptor of channel 1
+ */
+#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624)
+/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_M  (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_M  (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S)
+#define DMA2D_IN_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_S  18
+/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH1    0x00000007U
+#define DMA2D_IN_STATE_CH1_M  (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S)
+#define DMA2D_IN_STATE_CH1_V  0x00000007U
+#define DMA2D_IN_STATE_CH1_S  20
+/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH1    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH1_M  (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S)
+#define DMA2D_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH1_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_DSCR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630)
+/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_M  (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S)
+#define DMA2D_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634)
+/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_M  (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S)
+#define DMA2D_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638)
+/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_M  (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S)
+#define DMA2D_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_IN_PERI_SEL_CH1_REG register
+ *  Configures the rx peripheral of channel 1
+ */
+#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c)
+/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH1    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_M  (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S)
+#define DMA2D_IN_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_S  0
+
+/** DMA2D_IN_ARB_CH1_REG register
+ *  Configures the rx arbiter of channel 1
+ */
+#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M  (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH1    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH1_M  (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S)
+#define DMA2D_IN_ARB_PRIORITY_CH1_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH1_S  4
+/** DMA2D_IN_ARB_PRIORITY_H_CH1 : R/W; bitpos: [7:5]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_H_CH1    0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH1_M  (DMA2D_IN_ARB_PRIORITY_H_CH1_V << DMA2D_IN_ARB_PRIORITY_H_CH1_S)
+#define DMA2D_IN_ARB_PRIORITY_H_CH1_V  0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH1_S  5
+
+/** DMA2D_IN_RO_STATUS_CH1_REG register
+ *  Represents the status of the rx reorder module of channel 1
+ */
+#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644)
+/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH1    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_M  (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S)
+#define DMA2D_INFIFO_RO_CNT_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_S  0
+/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_M  (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S)
+#define DMA2D_IN_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_S  5
+/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_M  (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S)
+#define DMA2D_IN_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_M  (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S)
+#define DMA2D_IN_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M  (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S  13
+
+/** DMA2D_IN_RO_PD_CONF_CH1_REG register
+ *  Configures the rx reorder memory of channel 1
+ */
+#define DMA2D_IN_RO_PD_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648)
+/** DMA2D_IN_RO_RAM_FORCE_PD_CH1 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH1    (BIT(4))
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_M  (DMA2D_IN_RO_RAM_FORCE_PD_CH1_V << DMA2D_IN_RO_RAM_FORCE_PD_CH1_S)
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH1_S  4
+/** DMA2D_IN_RO_RAM_FORCE_PU_CH1 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH1    (BIT(5))
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_M  (DMA2D_IN_RO_RAM_FORCE_PU_CH1_V << DMA2D_IN_RO_RAM_FORCE_PU_CH1_S)
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH1_S  5
+/** DMA2D_IN_RO_RAM_CLK_FO_CH1 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_IN_RO_RAM_CLK_FO_CH1    (BIT(6))
+#define DMA2D_IN_RO_RAM_CLK_FO_CH1_M  (DMA2D_IN_RO_RAM_CLK_FO_CH1_V << DMA2D_IN_RO_RAM_CLK_FO_CH1_S)
+#define DMA2D_IN_RO_RAM_CLK_FO_CH1_V  0x00000001U
+#define DMA2D_IN_RO_RAM_CLK_FO_CH1_S  6
+
+/** DMA2D_IN_COLOR_CONVERT_CH1_REG register
+ *  Configures the Rx color convert of channel 1
+ */
+#define DMA2D_IN_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x64c)
+/** DMA2D_IN_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+ */
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1    0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_M  (DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S)
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_V  0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH1_S  0
+/** DMA2D_IN_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH1    (BIT(2))
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_M  (DMA2D_IN_COLOR_3B_PROC_EN_CH1_V << DMA2D_IN_COLOR_3B_PROC_EN_CH1_S)
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_V  0x00000001U
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH1_S  2
+/** DMA2D_IN_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+ *  1: YUV422      2: YUV444/420      7: disable color space convert
+ */
+#define DMA2D_IN_COLOR_INPUT_SEL_CH1    0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH1_M  (DMA2D_IN_COLOR_INPUT_SEL_CH1_V << DMA2D_IN_COLOR_INPUT_SEL_CH1_S)
+#define DMA2D_IN_COLOR_INPUT_SEL_CH1_V  0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH1_S  3
+
+/** DMA2D_IN_SCRAMBLE_CH1_REG register
+ *  Configures the rx scramble of channel 1
+ */
+#define DMA2D_IN_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x650)
+/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_M  (DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S)
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH1_S  0
+/** DMA2D_IN_SCRAMBLE_SEL_POST_CH1 : R/W; bitpos: [5:3]; default: 0;
+ *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+ *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_M  (DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S)
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH1_S  3
+
+/** DMA2D_IN_COLOR_PARAM0_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x654)
+/** DMA2D_IN_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H0_CH1    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH1_M  (DMA2D_IN_COLOR_PARAM_H0_CH1_V << DMA2D_IN_COLOR_PARAM_H0_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_H0_CH1_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM1_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x658)
+/** DMA2D_IN_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H1_CH1    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH1_M  (DMA2D_IN_COLOR_PARAM_H1_CH1_V << DMA2D_IN_COLOR_PARAM_H1_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_H1_CH1_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM2_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x65c)
+/** DMA2D_IN_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M0_CH1    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH1_M  (DMA2D_IN_COLOR_PARAM_M0_CH1_V << DMA2D_IN_COLOR_PARAM_M0_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_M0_CH1_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM3_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x660)
+/** DMA2D_IN_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M1_CH1    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH1_M  (DMA2D_IN_COLOR_PARAM_M1_CH1_V << DMA2D_IN_COLOR_PARAM_M1_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_M1_CH1_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM4_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x664)
+/** DMA2D_IN_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L0_CH1    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH1_M  (DMA2D_IN_COLOR_PARAM_L0_CH1_V << DMA2D_IN_COLOR_PARAM_L0_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_L0_CH1_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH1_S  0
+
+/** DMA2D_IN_COLOR_PARAM5_CH1_REG register
+ *  Configures the rx color convert parameter of channel 1
+ */
+#define DMA2D_IN_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x668)
+/** DMA2D_IN_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L1_CH1    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH1_M  (DMA2D_IN_COLOR_PARAM_L1_CH1_V << DMA2D_IN_COLOR_PARAM_L1_CH1_S)
+#define DMA2D_IN_COLOR_PARAM_L1_CH1_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH1_S  0
+
+/** DMA2D_IN_ETM_CONF_CH1_REG register
+ *  Configures the rx etm of channel 1
+ */
+#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x66c)
+/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH1    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH1_M  (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S)
+#define DMA2D_IN_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH1_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH1_M  (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_M  (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_IN_CONF0_CH2_REG register
+ *  Configures the rx direction of channel 2
+ */
+#define DMA2D_IN_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x700)
+/** DMA2D_IN_MEM_TRANS_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH2    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH2_M  (DMA2D_IN_MEM_TRANS_EN_CH2_V << DMA2D_IN_MEM_TRANS_EN_CH2_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH2_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH2_S  0
+/** DMA2D_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH2    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH2_M  (DMA2D_INDSCR_BURST_EN_CH2_V << DMA2D_INDSCR_BURST_EN_CH2_S)
+#define DMA2D_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH2_S  2
+/** DMA2D_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH2    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH2_M  (DMA2D_IN_ECC_AES_EN_CH2_V << DMA2D_IN_ECC_AES_EN_CH2_S)
+#define DMA2D_IN_ECC_AES_EN_CH2_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH2_S  3
+/** DMA2D_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH2    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH2_M  (DMA2D_IN_CHECK_OWNER_CH2_V << DMA2D_IN_CHECK_OWNER_CH2_S)
+#define DMA2D_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH2_S  4
+/** DMA2D_IN_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH2    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH2_M  (DMA2D_IN_LOOP_TEST_CH2_V << DMA2D_IN_LOOP_TEST_CH2_S)
+#define DMA2D_IN_LOOP_TEST_CH2_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH2_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2_M  (DMA2D_IN_MEM_BURST_LENGTH_CH2_V << DMA2D_IN_MEM_BURST_LENGTH_CH2_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH2    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH2_M  (DMA2D_IN_DSCR_PORT_EN_CH2_V << DMA2D_IN_DSCR_PORT_EN_CH2_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH2_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH2_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH2    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH2_M  (DMA2D_IN_PAGE_BOUND_EN_CH2_V << DMA2D_IN_PAGE_BOUND_EN_CH2_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH2_S  12
+/** DMA2D_IN_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH2    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH2_M  (DMA2D_IN_REORDER_EN_CH2_V << DMA2D_IN_REORDER_EN_CH2_S)
+#define DMA2D_IN_REORDER_EN_CH2_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH2_S  16
+/** DMA2D_IN_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH2    (BIT(24))
+#define DMA2D_IN_RST_CH2_M  (DMA2D_IN_RST_CH2_V << DMA2D_IN_RST_CH2_S)
+#define DMA2D_IN_RST_CH2_V  0x00000001U
+#define DMA2D_IN_RST_CH2_S  24
+/** DMA2D_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH2    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH2_M  (DMA2D_IN_CMD_DISABLE_CH2_V << DMA2D_IN_CMD_DISABLE_CH2_S)
+#define DMA2D_IN_CMD_DISABLE_CH2_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH2_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** DMA2D_IN_INT_RAW_CH2_REG register
+ *  Raw interrupt status of RX channel 2
+ */
+#define DMA2D_IN_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x704)
+/** DMA2D_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_RAW_M  (DMA2D_IN_DONE_CH2_INT_RAW_V << DMA2D_IN_DONE_CH2_INT_RAW_S)
+#define DMA2D_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH2_INT_RAW_V << DMA2D_IN_SUC_EOF_CH2_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH2_INT_RAW_V << DMA2D_IN_ERR_EOF_CH2_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of RX channel 2
+ */
+#define DMA2D_IN_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x708)
+/** DMA2D_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_ENA_M  (DMA2D_IN_DONE_CH2_INT_ENA_V << DMA2D_IN_DONE_CH2_INT_ENA_S)
+#define DMA2D_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH2_INT_ENA_V << DMA2D_IN_SUC_EOF_CH2_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH2_INT_ENA_V << DMA2D_IN_ERR_EOF_CH2_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH2_REG register
+ *  Masked interrupt status of RX channel 2
+ */
+#define DMA2D_IN_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x70c)
+/** DMA2D_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH2_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_ST_M  (DMA2D_IN_DONE_CH2_INT_ST_V << DMA2D_IN_DONE_CH2_INT_ST_S)
+#define DMA2D_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST_M  (DMA2D_IN_SUC_EOF_CH2_INT_ST_V << DMA2D_IN_SUC_EOF_CH2_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST_M  (DMA2D_IN_ERR_EOF_CH2_INT_ST_V << DMA2D_IN_ERR_EOF_CH2_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH2_INT_ST_V << DMA2D_IN_DSCR_ERR_CH2_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of RX channel 2
+ */
+#define DMA2D_IN_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x710)
+/** DMA2D_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_CLR_M  (DMA2D_IN_DONE_CH2_INT_CLR_V << DMA2D_IN_DONE_CH2_INT_CLR_S)
+#define DMA2D_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH2_INT_CLR_V << DMA2D_IN_SUC_EOF_CH2_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH2_INT_CLR_V << DMA2D_IN_ERR_EOF_CH2_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH2_REG register
+ *  Represents the status of the rx fifo of channel 2
+ */
+#define DMA2D_INFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x714)
+/** DMA2D_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH2    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH2_M  (DMA2D_INFIFO_FULL_L2_CH2_V << DMA2D_INFIFO_FULL_L2_CH2_S)
+#define DMA2D_INFIFO_FULL_L2_CH2_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH2_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH2    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH2_M  (DMA2D_INFIFO_EMPTY_L2_CH2_V << DMA2D_INFIFO_EMPTY_L2_CH2_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH2_S  1
+/** DMA2D_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH2    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH2_M  (DMA2D_INFIFO_CNT_L2_CH2_V << DMA2D_INFIFO_CNT_L2_CH2_S)
+#define DMA2D_INFIFO_CNT_L2_CH2_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH2_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2_M  (DMA2D_IN_REMAIN_UNDER_1B_CH2_V << DMA2D_IN_REMAIN_UNDER_1B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2_M  (DMA2D_IN_REMAIN_UNDER_2B_CH2_V << DMA2D_IN_REMAIN_UNDER_2B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2_M  (DMA2D_IN_REMAIN_UNDER_3B_CH2_V << DMA2D_IN_REMAIN_UNDER_3B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2_M  (DMA2D_IN_REMAIN_UNDER_4B_CH2_V << DMA2D_IN_REMAIN_UNDER_4B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2_M  (DMA2D_IN_REMAIN_UNDER_5B_CH2_V << DMA2D_IN_REMAIN_UNDER_5B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2_M  (DMA2D_IN_REMAIN_UNDER_6B_CH2_V << DMA2D_IN_REMAIN_UNDER_6B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2_M  (DMA2D_IN_REMAIN_UNDER_7B_CH2_V << DMA2D_IN_REMAIN_UNDER_7B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2_M  (DMA2D_IN_REMAIN_UNDER_8B_CH2_V << DMA2D_IN_REMAIN_UNDER_8B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2_S  14
+/** DMA2D_INFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH2    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH2_M  (DMA2D_INFIFO_FULL_L1_CH2_V << DMA2D_INFIFO_FULL_L1_CH2_S)
+#define DMA2D_INFIFO_FULL_L1_CH2_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH2_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH2    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH2_M  (DMA2D_INFIFO_EMPTY_L1_CH2_V << DMA2D_INFIFO_EMPTY_L1_CH2_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH2_S  16
+/** DMA2D_INFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH2    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH2_M  (DMA2D_INFIFO_CNT_L1_CH2_V << DMA2D_INFIFO_CNT_L1_CH2_S)
+#define DMA2D_INFIFO_CNT_L1_CH2_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH2_S  17
+/** DMA2D_INFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH2    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH2_M  (DMA2D_INFIFO_FULL_L3_CH2_V << DMA2D_INFIFO_FULL_L3_CH2_S)
+#define DMA2D_INFIFO_FULL_L3_CH2_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH2_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH2    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH2_M  (DMA2D_INFIFO_EMPTY_L3_CH2_V << DMA2D_INFIFO_EMPTY_L3_CH2_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH2_S  23
+/** DMA2D_INFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH2    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH2_M  (DMA2D_INFIFO_CNT_L3_CH2_V << DMA2D_INFIFO_CNT_L3_CH2_S)
+#define DMA2D_INFIFO_CNT_L3_CH2_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH2_S  24
+
+/** DMA2D_IN_POP_CH2_REG register
+ *  Configures the rx fifo of channel 2
+ */
+#define DMA2D_IN_POP_CH2_REG (DR_REG_DMA2D_BASE + 0x718)
+/** DMA2D_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH2    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH2_M  (DMA2D_INFIFO_RDATA_CH2_V << DMA2D_INFIFO_RDATA_CH2_S)
+#define DMA2D_INFIFO_RDATA_CH2_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH2_S  0
+/** DMA2D_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH2    (BIT(11))
+#define DMA2D_INFIFO_POP_CH2_M  (DMA2D_INFIFO_POP_CH2_V << DMA2D_INFIFO_POP_CH2_S)
+#define DMA2D_INFIFO_POP_CH2_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH2_S  11
+
+/** DMA2D_IN_LINK_CONF_CH2_REG register
+ *  Configures the rx descriptor operations of channel 2
+ */
+#define DMA2D_IN_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x71c)
+/** DMA2D_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH2    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH2_M  (DMA2D_INLINK_AUTO_RET_CH2_V << DMA2D_INLINK_AUTO_RET_CH2_S)
+#define DMA2D_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH2_S  20
+/** DMA2D_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH2    (BIT(21))
+#define DMA2D_INLINK_STOP_CH2_M  (DMA2D_INLINK_STOP_CH2_V << DMA2D_INLINK_STOP_CH2_S)
+#define DMA2D_INLINK_STOP_CH2_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH2_S  21
+/** DMA2D_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH2    (BIT(22))
+#define DMA2D_INLINK_START_CH2_M  (DMA2D_INLINK_START_CH2_V << DMA2D_INLINK_START_CH2_S)
+#define DMA2D_INLINK_START_CH2_V  0x00000001U
+#define DMA2D_INLINK_START_CH2_S  22
+/** DMA2D_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH2    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH2_M  (DMA2D_INLINK_RESTART_CH2_V << DMA2D_INLINK_RESTART_CH2_S)
+#define DMA2D_INLINK_RESTART_CH2_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH2_S  23
+/** DMA2D_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH2    (BIT(24))
+#define DMA2D_INLINK_PARK_CH2_M  (DMA2D_INLINK_PARK_CH2_V << DMA2D_INLINK_PARK_CH2_S)
+#define DMA2D_INLINK_PARK_CH2_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH2_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH2_REG register
+ *  Configures the rx descriptor address of channel 2
+ */
+#define DMA2D_IN_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x720)
+/** DMA2D_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH2_M  (DMA2D_INLINK_ADDR_CH2_V << DMA2D_INLINK_ADDR_CH2_S)
+#define DMA2D_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH2_S  0
+
+/** DMA2D_IN_STATE_CH2_REG register
+ *  Represents the working status of the rx descriptor of channel 2
+ */
+#define DMA2D_IN_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x724)
+/** DMA2D_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH2_M  (DMA2D_INLINK_DSCR_ADDR_CH2_V << DMA2D_INLINK_DSCR_ADDR_CH2_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH2_S  0
+/** DMA2D_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH2    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH2_M  (DMA2D_IN_DSCR_STATE_CH2_V << DMA2D_IN_DSCR_STATE_CH2_S)
+#define DMA2D_IN_DSCR_STATE_CH2_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH2_S  18
+/** DMA2D_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH2    0x00000007U
+#define DMA2D_IN_STATE_CH2_M  (DMA2D_IN_STATE_CH2_V << DMA2D_IN_STATE_CH2_S)
+#define DMA2D_IN_STATE_CH2_V  0x00000007U
+#define DMA2D_IN_STATE_CH2_S  20
+/** DMA2D_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH2    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH2_M  (DMA2D_IN_RESET_AVAIL_CH2_V << DMA2D_IN_RESET_AVAIL_CH2_S)
+#define DMA2D_IN_RESET_AVAIL_CH2_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH2_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x728)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x72c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_IN_DSCR_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x730)
+/** DMA2D_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH2_M  (DMA2D_INLINK_DSCR_CH2_V << DMA2D_INLINK_DSCR_CH2_S)
+#define DMA2D_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH2_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x734)
+/** DMA2D_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH2_M  (DMA2D_INLINK_DSCR_BF0_CH2_V << DMA2D_INLINK_DSCR_BF0_CH2_S)
+#define DMA2D_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH2_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x738)
+/** DMA2D_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH2_M  (DMA2D_INLINK_DSCR_BF1_CH2_V << DMA2D_INLINK_DSCR_BF1_CH2_S)
+#define DMA2D_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH2_S  0
+
+/** DMA2D_IN_PERI_SEL_CH2_REG register
+ *  Configures the rx peripheral of channel 2
+ */
+#define DMA2D_IN_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x73c)
+/** DMA2D_IN_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH2    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH2_M  (DMA2D_IN_PERI_SEL_CH2_V << DMA2D_IN_PERI_SEL_CH2_S)
+#define DMA2D_IN_PERI_SEL_CH2_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH2_S  0
+
+/** DMA2D_IN_ARB_CH2_REG register
+ *  Configures the rx arbiter of channel 2
+ */
+#define DMA2D_IN_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x740)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2_M  (DMA2D_IN_ARB_TOKEN_NUM_CH2_V << DMA2D_IN_ARB_TOKEN_NUM_CH2_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH2    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH2_M  (DMA2D_IN_ARB_PRIORITY_CH2_V << DMA2D_IN_ARB_PRIORITY_CH2_S)
+#define DMA2D_IN_ARB_PRIORITY_CH2_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH2_S  4
+/** DMA2D_IN_ARB_PRIORITY_H_CH2 : R/W; bitpos: [7:5]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_H_CH2    0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH2_M  (DMA2D_IN_ARB_PRIORITY_H_CH2_V << DMA2D_IN_ARB_PRIORITY_H_CH2_S)
+#define DMA2D_IN_ARB_PRIORITY_H_CH2_V  0x00000007U
+#define DMA2D_IN_ARB_PRIORITY_H_CH2_S  5
+
+/** DMA2D_IN_RO_STATUS_CH2_REG register
+ *  Represents the status of the rx reorder module of channel 2
+ */
+#define DMA2D_IN_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x744)
+/** DMA2D_INFIFO_RO_CNT_CH2 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH2    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH2_M  (DMA2D_INFIFO_RO_CNT_CH2_V << DMA2D_INFIFO_RO_CNT_CH2_S)
+#define DMA2D_INFIFO_RO_CNT_CH2_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH2_S  0
+/** DMA2D_IN_RO_WR_STATE_CH2 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH2    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH2_M  (DMA2D_IN_RO_WR_STATE_CH2_V << DMA2D_IN_RO_WR_STATE_CH2_S)
+#define DMA2D_IN_RO_WR_STATE_CH2_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH2_S  5
+/** DMA2D_IN_RO_RD_STATE_CH2 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH2    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH2_M  (DMA2D_IN_RO_RD_STATE_CH2_V << DMA2D_IN_RO_RD_STATE_CH2_S)
+#define DMA2D_IN_RO_RD_STATE_CH2_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH2_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH2 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH2    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH2_M  (DMA2D_IN_PIXEL_BYTE_CH2_V << DMA2D_IN_PIXEL_BYTE_CH2_S)
+#define DMA2D_IN_PIXEL_BYTE_CH2_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH2_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH2 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2_M  (DMA2D_IN_BURST_BLOCK_NUM_CH2_V << DMA2D_IN_BURST_BLOCK_NUM_CH2_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2_S  13
+
+/** DMA2D_IN_RO_PD_CONF_CH2_REG register
+ *  Configures the rx reorder memory of channel 2
+ */
+#define DMA2D_IN_RO_PD_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x748)
+/** DMA2D_IN_RO_RAM_FORCE_PD_CH2 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH2    (BIT(4))
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_M  (DMA2D_IN_RO_RAM_FORCE_PD_CH2_V << DMA2D_IN_RO_RAM_FORCE_PD_CH2_S)
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH2_S  4
+/** DMA2D_IN_RO_RAM_FORCE_PU_CH2 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH2    (BIT(5))
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_M  (DMA2D_IN_RO_RAM_FORCE_PU_CH2_V << DMA2D_IN_RO_RAM_FORCE_PU_CH2_S)
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH2_S  5
+/** DMA2D_IN_RO_RAM_CLK_FO_CH2 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_IN_RO_RAM_CLK_FO_CH2    (BIT(6))
+#define DMA2D_IN_RO_RAM_CLK_FO_CH2_M  (DMA2D_IN_RO_RAM_CLK_FO_CH2_V << DMA2D_IN_RO_RAM_CLK_FO_CH2_S)
+#define DMA2D_IN_RO_RAM_CLK_FO_CH2_V  0x00000001U
+#define DMA2D_IN_RO_RAM_CLK_FO_CH2_S  6
+
+/** DMA2D_IN_COLOR_CONVERT_CH2_REG register
+ *  Configures the Rx color convert of channel 2
+ */
+#define DMA2D_IN_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x74c)
+/** DMA2D_IN_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+ */
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2    0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_M  (DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S)
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_V  0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH2_S  0
+/** DMA2D_IN_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH2    (BIT(2))
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_M  (DMA2D_IN_COLOR_3B_PROC_EN_CH2_V << DMA2D_IN_COLOR_3B_PROC_EN_CH2_S)
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_V  0x00000001U
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH2_S  2
+/** DMA2D_IN_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+ *  1: YUV422      2: YUV444/420      7: disable color space convert
+ */
+#define DMA2D_IN_COLOR_INPUT_SEL_CH2    0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH2_M  (DMA2D_IN_COLOR_INPUT_SEL_CH2_V << DMA2D_IN_COLOR_INPUT_SEL_CH2_S)
+#define DMA2D_IN_COLOR_INPUT_SEL_CH2_V  0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH2_S  3
+
+/** DMA2D_IN_SCRAMBLE_CH2_REG register
+ *  Configures the rx scramble of channel 2
+ */
+#define DMA2D_IN_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x750)
+/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_M  (DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S)
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH2_S  0
+/** DMA2D_IN_SCRAMBLE_SEL_POST_CH2 : R/W; bitpos: [5:3]; default: 0;
+ *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+ *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_M  (DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S)
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH2_S  3
+
+/** DMA2D_IN_COLOR_PARAM0_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x754)
+/** DMA2D_IN_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H0_CH2    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH2_M  (DMA2D_IN_COLOR_PARAM_H0_CH2_V << DMA2D_IN_COLOR_PARAM_H0_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_H0_CH2_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM1_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x758)
+/** DMA2D_IN_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H1_CH2    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH2_M  (DMA2D_IN_COLOR_PARAM_H1_CH2_V << DMA2D_IN_COLOR_PARAM_H1_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_H1_CH2_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM2_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x75c)
+/** DMA2D_IN_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M0_CH2    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH2_M  (DMA2D_IN_COLOR_PARAM_M0_CH2_V << DMA2D_IN_COLOR_PARAM_M0_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_M0_CH2_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM3_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x760)
+/** DMA2D_IN_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M1_CH2    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH2_M  (DMA2D_IN_COLOR_PARAM_M1_CH2_V << DMA2D_IN_COLOR_PARAM_M1_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_M1_CH2_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM4_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x764)
+/** DMA2D_IN_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L0_CH2    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH2_M  (DMA2D_IN_COLOR_PARAM_L0_CH2_V << DMA2D_IN_COLOR_PARAM_L0_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_L0_CH2_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH2_S  0
+
+/** DMA2D_IN_COLOR_PARAM5_CH2_REG register
+ *  Configures the rx color convert parameter of channel 2
+ */
+#define DMA2D_IN_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x768)
+/** DMA2D_IN_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L1_CH2    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH2_M  (DMA2D_IN_COLOR_PARAM_L1_CH2_V << DMA2D_IN_COLOR_PARAM_L1_CH2_S)
+#define DMA2D_IN_COLOR_PARAM_L1_CH2_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH2_S  0
+
+/** DMA2D_IN_ETM_CONF_CH2_REG register
+ *  Configures the rx etm of channel 2
+ */
+#define DMA2D_IN_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x76c)
+/** DMA2D_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH2    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH2_M  (DMA2D_IN_ETM_EN_CH2_V << DMA2D_IN_ETM_EN_CH2_S)
+#define DMA2D_IN_ETM_EN_CH2_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH2_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH2    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH2_M  (DMA2D_IN_ETM_LOOP_EN_CH2_V << DMA2D_IN_ETM_LOOP_EN_CH2_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH2_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH2_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH2    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH2_M  (DMA2D_IN_DSCR_TASK_MAK_CH2_V << DMA2D_IN_DSCR_TASK_MAK_CH2_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH2_S  2
+
+/** DMA2D_AXI_ERR_REG register
+ *  Represents the status of th axi bus
+ */
+#define DMA2D_AXI_ERR_REG (DR_REG_DMA2D_BASE + 0xa00)
+/** DMA2D_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0;
+ *  AXI read id err cnt
+ */
+#define DMA2D_RID_ERR_CNT    0x0000000FU
+#define DMA2D_RID_ERR_CNT_M  (DMA2D_RID_ERR_CNT_V << DMA2D_RID_ERR_CNT_S)
+#define DMA2D_RID_ERR_CNT_V  0x0000000FU
+#define DMA2D_RID_ERR_CNT_S  0
+/** DMA2D_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0;
+ *  AXI read resp err cnt
+ */
+#define DMA2D_RRESP_ERR_CNT    0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_M  (DMA2D_RRESP_ERR_CNT_V << DMA2D_RRESP_ERR_CNT_S)
+#define DMA2D_RRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_S  4
+/** DMA2D_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0;
+ *  AXI write resp err cnt
+ */
+#define DMA2D_WRESP_ERR_CNT    0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_M  (DMA2D_WRESP_ERR_CNT_V << DMA2D_WRESP_ERR_CNT_S)
+#define DMA2D_WRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_S  8
+/** DMA2D_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0;
+ *  AXI read cmd fifo remain cmd count
+ */
+#define DMA2D_RD_FIFO_CNT    0x00000007U
+#define DMA2D_RD_FIFO_CNT_M  (DMA2D_RD_FIFO_CNT_V << DMA2D_RD_FIFO_CNT_S)
+#define DMA2D_RD_FIFO_CNT_V  0x00000007U
+#define DMA2D_RD_FIFO_CNT_S  12
+/** DMA2D_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0;
+ *  AXI read backup cmd fifo remain cmd count
+ */
+#define DMA2D_RD_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_M  (DMA2D_RD_BAK_FIFO_CNT_V << DMA2D_RD_BAK_FIFO_CNT_S)
+#define DMA2D_RD_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_S  15
+/** DMA2D_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0;
+ *  AXI write cmd fifo remain cmd count
+ */
+#define DMA2D_WR_FIFO_CNT    0x00000007U
+#define DMA2D_WR_FIFO_CNT_M  (DMA2D_WR_FIFO_CNT_V << DMA2D_WR_FIFO_CNT_S)
+#define DMA2D_WR_FIFO_CNT_V  0x00000007U
+#define DMA2D_WR_FIFO_CNT_S  19
+/** DMA2D_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0;
+ *  AXI write backup cmd fifo remain cmd count
+ */
+#define DMA2D_WR_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_M  (DMA2D_WR_BAK_FIFO_CNT_V << DMA2D_WR_BAK_FIFO_CNT_S)
+#define DMA2D_WR_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_S  22
+
+/** DMA2D_RST_CONF_REG register
+ *  Configures the reset of axi
+ */
+#define DMA2D_RST_CONF_REG (DR_REG_DMA2D_BASE + 0xa04)
+/** DMA2D_AXIM_RD_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+ */
+#define DMA2D_AXIM_RD_RST    (BIT(0))
+#define DMA2D_AXIM_RD_RST_M  (DMA2D_AXIM_RD_RST_V << DMA2D_AXIM_RD_RST_S)
+#define DMA2D_AXIM_RD_RST_V  0x00000001U
+#define DMA2D_AXIM_RD_RST_S  0
+/** DMA2D_AXIM_WR_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+ */
+#define DMA2D_AXIM_WR_RST    (BIT(1))
+#define DMA2D_AXIM_WR_RST_M  (DMA2D_AXIM_WR_RST_V << DMA2D_AXIM_WR_RST_S)
+#define DMA2D_AXIM_WR_RST_V  0x00000001U
+#define DMA2D_AXIM_WR_RST_S  1
+/** DMA2D_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define DMA2D_CLK_EN    (BIT(2))
+#define DMA2D_CLK_EN_M  (DMA2D_CLK_EN_V << DMA2D_CLK_EN_S)
+#define DMA2D_CLK_EN_V  0x00000001U
+#define DMA2D_CLK_EN_S  2
+
+/** DMA2D_INTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa08)
+/** DMA2D_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_M  (DMA2D_ACCESS_INTR_MEM_START_ADDR_V << DMA2D_ACCESS_INTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** DMA2D_INTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa0c)
+/** DMA2D_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_M  (DMA2D_ACCESS_INTR_MEM_END_ADDR_V << DMA2D_ACCESS_INTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa10)
+/** DMA2D_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_START_ADDR_V << DMA2D_ACCESS_EXTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa14)
+/** DMA2D_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_END_ADDR_V << DMA2D_ACCESS_EXTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_S  0
+
+/** DMA2D_OUT_ARB_CONFIG_REG register
+ *  Configures the tx arbiter
+ */
+#define DMA2D_OUT_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa18)
+/** DMA2D_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_OUT_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_M  (DMA2D_OUT_ARB_TIMEOUT_NUM_V << DMA2D_OUT_ARB_TIMEOUT_NUM_S)
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_WEIGHT_EN    (BIT(16))
+#define DMA2D_OUT_WEIGHT_EN_M  (DMA2D_OUT_WEIGHT_EN_V << DMA2D_OUT_WEIGHT_EN_S)
+#define DMA2D_OUT_WEIGHT_EN_V  0x00000001U
+#define DMA2D_OUT_WEIGHT_EN_S  16
+
+/** DMA2D_IN_ARB_CONFIG_REG register
+ *  Configures the rx arbiter
+ */
+#define DMA2D_IN_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa1c)
+/** DMA2D_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_IN_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_M  (DMA2D_IN_ARB_TIMEOUT_NUM_V << DMA2D_IN_ARB_TIMEOUT_NUM_S)
+#define DMA2D_IN_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_WEIGHT_EN    (BIT(16))
+#define DMA2D_IN_WEIGHT_EN_M  (DMA2D_IN_WEIGHT_EN_V << DMA2D_IN_WEIGHT_EN_S)
+#define DMA2D_IN_WEIGHT_EN_V  0x00000001U
+#define DMA2D_IN_WEIGHT_EN_S  16
+
+/** DMA2D_RDN_RESULT_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT_REG (DR_REG_DMA2D_BASE + 0xa20)
+/** DMA2D_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_ENA    (BIT(0))
+#define DMA2D_RDN_ENA_M  (DMA2D_RDN_ENA_V << DMA2D_RDN_ENA_S)
+#define DMA2D_RDN_ENA_V  0x00000001U
+#define DMA2D_RDN_ENA_S  0
+/** DMA2D_RDN_RESULT : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT    (BIT(1))
+#define DMA2D_RDN_RESULT_M  (DMA2D_RDN_RESULT_V << DMA2D_RDN_RESULT_S)
+#define DMA2D_RDN_RESULT_V  0x00000001U
+#define DMA2D_RDN_RESULT_S  1
+
+/** DMA2D_RDN_ECO_HIGH_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_HIGH_REG (DR_REG_DMA2D_BASE + 0xa24)
+/** DMA2D_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_HIGH    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_M  (DMA2D_RDN_ECO_HIGH_V << DMA2D_RDN_ECO_HIGH_S)
+#define DMA2D_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_S  0
+
+/** DMA2D_RDN_ECO_LOW_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_LOW_REG (DR_REG_DMA2D_BASE + 0xa28)
+/** DMA2D_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_LOW    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_M  (DMA2D_RDN_ECO_LOW_V << DMA2D_RDN_ECO_LOW_S)
+#define DMA2D_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_S  0
+
+/** DMA2D_DATE_REG register
+ *  register version.
+ */
+#define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c)
+/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 37822864;
+ *  register version.
+ */
+#define DMA2D_DATE    0xFFFFFFFFU
+#define DMA2D_DATE_M  (DMA2D_DATE_V << DMA2D_DATE_S)
+#define DMA2D_DATE_V  0xFFFFFFFFU
+#define DMA2D_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dma2d_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/dma2d_eco5_struct.h
new file mode 100644
index 0000000000..d637f6ecab
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dma2d_eco5_struct.h
@@ -0,0 +1,2085 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of out_conf0_chn register
+ *  Configures the tx direction of channel n
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_chn : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_chn:1;
+        /** out_eof_mode_chn : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_chn:1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn:1;
+        /** out_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_chn:1;
+        /** out_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn:1;
+        /** out_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn:1;
+        /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_chn:3;
+        /** out_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t out_macro_block_size_chn:2;
+        /** out_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t out_dscr_port_en_chn:1;
+        /** out_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** out_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t out_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** out_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_chn:1;
+        /** out_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_chn:1;
+        /** out_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_out_conf0_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Configures the tx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_chn:10;
+        /** outfifo_push_chn : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_chn:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dma2d_out_push_chn_reg_t;
+
+/** Type of out_link_conf_chn register
+ *  Configures the tx descriptor operations of channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_chn : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn:1;
+        /** outlink_start_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn:1;
+        /** outlink_restart_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn:1;
+        /** outlink_park_chn : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_out_link_conf_chn_reg_t;
+
+/** Type of out_link_addr_chn register
+ *  Configures the tx descriptor address of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_link_addr_chn_reg_t;
+
+/** Type of out_arb_chn register
+ *  Configures the tx arbiter of channel n
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_chn:4;
+        /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t out_arb_priority_chn:2;
+        /** out_arb_priority_h_chn : R/W; bitpos: [7:6]; default: 0;
+         *  Set the priority of channel
+         */
+        uint32_t out_arb_priority_h_chn:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dma2d_out_arb_chn_reg_t;
+
+/** Type of out_ro_pd_conf_chn register
+ *  Configures the tx reorder memory of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** out_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t out_ro_ram_force_pd_chn:1;
+        /** out_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t out_ro_ram_force_pu_chn:1;
+        /** out_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t out_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_out_ro_pd_conf_chn_reg_t;
+
+/** Type of out_color_convert_chn register
+ *  Configures the tx color convert of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  YUV444 to YUV422     2: output directly
+         */
+        uint32_t out_color_output_sel_chn:2;
+        /** out_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t out_color_3b_proc_en_chn:1;
+        /** out_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+         *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+         *  disable color space convert
+         */
+        uint32_t out_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_out_color_convert_chn_reg_t;
+
+/** Type of out_scramble_chn register
+ *  Configures the tx scramble of channel n
+ */
+typedef union {
+    struct {
+        /** out_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t out_scramble_sel_pre_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_scramble_chn_reg_t;
+
+/** Type of out_color_param0_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298;
+         *  Set first 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_h0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_out_color_param0_chn_reg_t;
+
+/** Type of out_color_param1_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121;
+         *  Set last 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_h1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_color_param1_chn_reg_t;
+
+/** Type of out_color_param2_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050;
+         *  Set first 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_m0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_out_color_param2_chn_reg_t;
+
+/** Type of out_color_param3_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784;
+         *  Set last 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_m1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_color_param3_chn_reg_t;
+
+/** Type of out_color_param4_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682;
+         *  Set first 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_l0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_out_color_param4_chn_reg_t;
+
+/** Type of out_color_param5_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392;
+         *  Set last 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_l1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_color_param5_chn_reg_t;
+
+/** Type of out_etm_conf_chn register
+ *  Configures the tx etm of channel n
+ */
+typedef union {
+    struct {
+        /** out_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t out_etm_en_chn:1;
+        /** out_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t out_etm_loop_en_chn:1;
+        /** out_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t out_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_out_etm_conf_chn_reg_t;
+
+/** Type of out_dscr_port_blk_chn register
+ *  Configures the tx block size in dscr port mode
+ */
+typedef union {
+    struct {
+        /** out_dscr_port_blk_h_chn : R/W; bitpos: [13:0]; default: 18;
+         *  Set the vertical height of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_h_chn:14;
+        /** out_dscr_port_blk_v_chn : R/W; bitpos: [27:14]; default: 18;
+         *  Set the horizontal width of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_v_chn:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_dscr_port_blk_chn_reg_t;
+
+/** Type of in_conf0_chn register
+ *  Configures the rx direction of channel n
+ */
+typedef union {
+    struct {
+        /** in_mem_trans_en_chn : R/W; bitpos: [0]; default: 0;
+         *  enable memory trans of the same channel
+         */
+        uint32_t in_mem_trans_en_chn:1;
+        uint32_t reserved_1:1;
+        /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_chn:1;
+        /** in_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_chn:1;
+        /** in_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn:1;
+        /** in_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn:1;
+        /** in_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_chn:3;
+        /** in_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t in_macro_block_size_chn:2;
+        /** in_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t in_dscr_port_en_chn:1;
+        /** in_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** in_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t in_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** in_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_chn:1;
+        /** in_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_chn:1;
+        /** in_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_in_conf0_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Configures the rx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_chn:11;
+        /** infifo_pop_chn : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_chn:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dma2d_in_pop_chn_reg_t;
+
+/** Type of in_link_conf_chn register
+ *  Configures the rx descriptor operations of channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn:1;
+        /** inlink_stop_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn:1;
+        /** inlink_start_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn:1;
+        /** inlink_restart_chn : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn:1;
+        /** inlink_park_chn : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_in_link_conf_chn_reg_t;
+
+/** Type of in_link_addr_chn register
+ *  Configures the rx descriptor address of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_link_addr_chn_reg_t;
+
+/** Type of in_arb_chn register
+ *  Configures the rx arbiter of channel n
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_chn:4;
+        /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t in_arb_priority_chn:1;
+        /** in_arb_priority_h_chn : R/W; bitpos: [7:5]; default: 0;
+         *  Set the priority of channel
+         */
+        uint32_t in_arb_priority_h_chn:3;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dma2d_in_arb_chn_reg_t;
+
+/** Type of in_ro_pd_conf_chn register
+ *  Configures the rx reorder memory of channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** in_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t in_ro_ram_force_pd_chn:1;
+        /** in_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t in_ro_ram_force_pu_chn:1;
+        /** in_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t in_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_in_ro_pd_conf_chn_reg_t;
+
+/** Type of in_color_convert_chn register
+ *  Configures the Rx color convert of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+         */
+        uint32_t in_color_output_sel_chn:2;
+        /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t in_color_3b_proc_en_chn:1;
+        /** in_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+         *  1: YUV422      2: YUV444/420      7: disable color space convert
+         */
+        uint32_t in_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_color_convert_chn_reg_t;
+
+/** Type of in_scramble_chn register
+ *  Configures the rx scramble of channel n
+ */
+typedef union {
+    struct {
+        /** in_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_pre_chn:3;
+        /** in_scramble_sel_post_chn : R/W; bitpos: [5:3]; default: 0;
+         *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+         *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_post_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_scramble_chn_reg_t;
+
+/** Type of in_color_param0_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298;
+         *  Set first 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_h0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_in_color_param0_chn_reg_t;
+
+/** Type of in_color_param1_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121;
+         *  Set last 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_h1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_in_color_param1_chn_reg_t;
+
+/** Type of in_color_param2_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050;
+         *  Set first 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_m0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_in_color_param2_chn_reg_t;
+
+/** Type of in_color_param3_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784;
+         *  Set last 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_m1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_in_color_param3_chn_reg_t;
+
+/** Type of in_color_param4_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682;
+         *  Set first 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_l0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_in_color_param4_chn_reg_t;
+
+/** Type of in_color_param5_chn register
+ *  Configures the rx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** in_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392;
+         *  Set last 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_l1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_in_color_param5_chn_reg_t;
+
+/** Type of in_etm_conf_chn register
+ *  Configures the rx etm of channel n
+ */
+typedef union {
+    struct {
+        /** in_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t in_etm_en_chn:1;
+        /** in_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t in_etm_loop_en_chn:1;
+        /** in_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t in_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_in_etm_conf_chn_reg_t;
+
+/** Type of rst_conf register
+ *  Configures the reset of axi
+ */
+typedef union {
+    struct {
+        /** axim_rd_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+         */
+        uint32_t axim_rd_rst:1;
+        /** axim_wr_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+         */
+        uint32_t axim_wr_rst:1;
+        /** clk_en : R/W; bitpos: [2]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_rst_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_end_addr_reg_t;
+
+/** Type of out_arb_config register
+ *  Configures the tx arbiter
+ */
+typedef union {
+    struct {
+        /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t out_arb_timeout_num:16;
+        /** out_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t out_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_out_arb_config_reg_t;
+
+/** Type of in_arb_config register
+ *  Configures the rx arbiter
+ */
+typedef union {
+    struct {
+        /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t in_arb_timeout_num:16;
+        /** in_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t in_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_arb_config_reg_t;
+
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dma2d_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_low_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of out_int_raw_chn register
+ *  Raw interrupt status of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_chn_int_raw:1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_chn_int_raw:1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_chn_int_raw:1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_chn_int_raw:1;
+        /** outfifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_raw:1;
+        /** outfifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_chn_int_raw:1;
+        /** outfifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_raw:1;
+        /** outfifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_chn_int_raw:1;
+        /** outfifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_raw:1;
+        /** outfifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l3_chn_int_raw:1;
+        /** outfifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_raw:1;
+        /** outfifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t outfifo_ro_udf_chn_int_raw:1;
+        /** out_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_raw_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena:1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena:1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena:1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena:1;
+        /** outfifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_ena:1;
+        /** outfifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_ena:1;
+        /** outfifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_ena:1;
+        /** outfifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_ena:1;
+        /** outfifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_ena:1;
+        /** outfifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_ena:1;
+        /** outfifo_ro_ovf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_ena:1;
+        /** outfifo_ro_udf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_ena:1;
+        /** out_dscr_task_ovf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_ena_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt status of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st:1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st:1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st:1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st:1;
+        /** outfifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_st:1;
+        /** outfifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_st:1;
+        /** outfifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_st:1;
+        /** outfifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_st:1;
+        /** outfifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_st:1;
+        /** outfifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_st:1;
+        /** outfifo_ro_ovf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_st:1;
+        /** outfifo_ro_udf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_st:1;
+        /** out_dscr_task_ovf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_st_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr:1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr:1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr:1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr:1;
+        /** outfifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_clr:1;
+        /** outfifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_clr:1;
+        /** outfifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_clr:1;
+        /** outfifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_clr:1;
+        /** outfifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_clr:1;
+        /** outfifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_clr:1;
+        /** outfifo_ro_ovf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_clr:1;
+        /** outfifo_ro_udf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_clr:1;
+        /** out_dscr_task_ovf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_clr_chn_reg_t;
+
+/** Type of in_int_raw_chn register
+ *  Raw interrupt status of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw:1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw:1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_chn_int_raw:1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw:1;
+        /** infifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_chn_int_raw:1;
+        /** infifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_chn_int_raw:1;
+        /** infifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_chn_int_raw:1;
+        /** infifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_chn_int_raw:1;
+        /** infifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l3_chn_int_raw:1;
+        /** infifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l3_chn_int_raw:1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_chn_int_raw:1;
+        /** infifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t infifo_ro_ovf_chn_int_raw:1;
+        /** infifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t infifo_ro_udf_chn_int_raw:1;
+        /** in_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_raw_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena:1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena:1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena:1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena:1;
+        /** infifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_ena:1;
+        /** infifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_ena:1;
+        /** infifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_ena:1;
+        /** infifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_ena:1;
+        /** infifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_ena:1;
+        /** infifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_ena:1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena:1;
+        /** infifo_ro_ovf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_ena:1;
+        /** infifo_ro_udf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_ena:1;
+        /** in_dscr_task_ovf_chn_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_ena_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt status of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st:1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st:1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st:1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st:1;
+        /** infifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_st:1;
+        /** infifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_st:1;
+        /** infifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_st:1;
+        /** infifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_st:1;
+        /** infifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_st:1;
+        /** infifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_st:1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st:1;
+        /** infifo_ro_ovf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_st:1;
+        /** infifo_ro_udf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_st:1;
+        /** in_dscr_task_ovf_chn_int_st : RO; bitpos: [13]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_st_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr:1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr:1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr:1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr:1;
+        /** infifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_clr:1;
+        /** infifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_clr:1;
+        /** infifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_clr:1;
+        /** infifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_clr:1;
+        /** infifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_clr:1;
+        /** infifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_clr:1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr:1;
+        /** infifo_ro_ovf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_clr:1;
+        /** infifo_ro_udf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_clr:1;
+        /** in_dscr_task_ovf_chn_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_clr_chn_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of outfifo_status_chn register
+ *  Represents the status of the tx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l2_chn:1;
+        /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l2_chn:1;
+        /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** out_remain_under_1b_chn : RO; bitpos: [7]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn:1;
+        /** out_remain_under_2b_chn : RO; bitpos: [8]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn:1;
+        /** out_remain_under_3b_chn : RO; bitpos: [9]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn:1;
+        /** out_remain_under_4b_chn : RO; bitpos: [10]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn:1;
+        /** out_remain_under_5b_chn : RO; bitpos: [11]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn:1;
+        /** out_remain_under_6b_chn : RO; bitpos: [12]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn:1;
+        /** out_remain_under_7b_chn : RO; bitpos: [13]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn:1;
+        /** out_remain_under_8b_chn : RO; bitpos: [14]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn:1;
+        /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l1_chn:1;
+        /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l1_chn:1;
+        /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l1_chn:5;
+        /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l3_chn:1;
+        /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l3_chn:1;
+        /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_outfifo_status_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Represents the working status of the tx descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn:18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_chn:2;
+        /** out_state_chn : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_chn:4;
+        /** out_reset_avail_chn : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf1_chn_reg_t;
+
+/** Type of out_ro_status_chn register
+ *  Represents the status of the tx reorder module of channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_ro_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Tx FIFO for
+         *  channel 0.
+         */
+        uint32_t outfifo_ro_cnt_chn:6;
+        /** out_ro_wr_state_chn : RO; bitpos: [7:6]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t out_ro_wr_state_chn:2;
+        /** out_ro_rd_state_chn : RO; bitpos: [9:8]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t out_ro_rd_state_chn:2;
+        /** out_pixel_byte_chn : RO; bitpos: [13:10]; default: 0;
+         *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t out_pixel_byte_chn:4;
+        /** out_burst_block_num_chn : RO; bitpos: [17:14]; default: 0;
+         *  the number of macro blocks contained in a burst of data at TX channel
+         */
+        uint32_t out_burst_block_num_chn:4;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dma2d_out_ro_status_chn_reg_t;
+
+/** Type of infifo_status_chn register
+ *  Represents the status of the rx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_chn:1;
+        /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_chn:1;
+        /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** in_remain_under_1b_chn : RO; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn:1;
+        /** in_remain_under_2b_chn : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn:1;
+        /** in_remain_under_3b_chn : RO; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn:1;
+        /** in_remain_under_4b_chn : RO; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn:1;
+        /** in_remain_under_5b_chn : RO; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn:1;
+        /** in_remain_under_6b_chn : RO; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn:1;
+        /** in_remain_under_7b_chn : RO; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn:1;
+        /** in_remain_under_8b_chn : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn:1;
+        /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_full_l1_chn:1;
+        /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_empty_l1_chn:1;
+        /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_cnt_l1_chn:5;
+        /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_full_l3_chn:1;
+        /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_empty_l3_chn:1;
+        /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_infifo_status_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Represents the working status of the rx descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn:18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn:2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn:3;
+        /** in_reset_avail_chn : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf1_chn_reg_t;
+
+/** Type of in_ro_status_chn register
+ *  Represents the status of the rx reorder module of channel n
+ */
+typedef union {
+    struct {
+        /** infifo_ro_cnt_chn : RO; bitpos: [4:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Rx FIFO for
+         *  channel 0.
+         */
+        uint32_t infifo_ro_cnt_chn:5;
+        /** in_ro_wr_state_chn : RO; bitpos: [6:5]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t in_ro_wr_state_chn:2;
+        /** in_ro_rd_state_chn : RO; bitpos: [8:7]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t in_ro_rd_state_chn:2;
+        /** in_pixel_byte_chn : RO; bitpos: [12:9]; default: 0;
+         *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t in_pixel_byte_chn:4;
+        /** in_burst_block_num_chn : RO; bitpos: [16:13]; default: 0;
+         *  the number of macro blocks contained in a burst of data at RX channel
+         */
+        uint32_t in_burst_block_num_chn:4;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_ro_status_chn_reg_t;
+
+/** Type of axi_err register
+ *  Represents the status of th axi bus
+ */
+typedef union {
+    struct {
+        /** rid_err_cnt : RO; bitpos: [3:0]; default: 0;
+         *  AXI read id err cnt
+         */
+        uint32_t rid_err_cnt:4;
+        /** rresp_err_cnt : RO; bitpos: [7:4]; default: 0;
+         *  AXI read resp err cnt
+         */
+        uint32_t rresp_err_cnt:4;
+        /** wresp_err_cnt : RO; bitpos: [11:8]; default: 0;
+         *  AXI write resp err cnt
+         */
+        uint32_t wresp_err_cnt:4;
+        /** rd_fifo_cnt : RO; bitpos: [14:12]; default: 0;
+         *  AXI read cmd fifo remain cmd count
+         */
+        uint32_t rd_fifo_cnt:3;
+        /** rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0;
+         *  AXI read backup cmd fifo remain cmd count
+         */
+        uint32_t rd_bak_fifo_cnt:4;
+        /** wr_fifo_cnt : RO; bitpos: [21:19]; default: 0;
+         *  AXI write cmd fifo remain cmd count
+         */
+        uint32_t wr_fifo_cnt:3;
+        /** wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0;
+         *  AXI write backup cmd fifo remain cmd count
+         */
+        uint32_t wr_bak_fifo_cnt:4;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} dma2d_axi_err_reg_t;
+
+/** Type of date register
+ *  register version.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 37822864;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} dma2d_date_reg_t;
+
+
+/** Group: Peripheral Select Registers */
+/** Type of out_peri_sel_chn register
+ *  Configures the tx peripheral of channel n
+ */
+typedef union {
+    struct {
+        /** out_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+         *  display-1     2: display-2     3: display-3      7: no choose
+         */
+        uint32_t out_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_peri_sel_chn_reg_t;
+
+/** Type of in_peri_sel_chn register
+ *  Configures the rx peripheral of channel n
+ */
+typedef union {
+    struct {
+        /** in_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+         *  display-1     2: display-2        7: no choose
+         */
+        uint32_t in_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_in_peri_sel_chn_reg_t;
+
+
+typedef struct {
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch0;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch0;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch0;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch0;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch0;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch0;
+    volatile dma2d_out_push_chn_reg_t out_push_ch0;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch0;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch0;
+    volatile dma2d_out_state_chn_reg_t out_state_ch0;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch0;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch0;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch0;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch0;
+    volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf_ch0;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch0;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch0;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch0;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch0;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch0;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch0;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch0;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch0;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch0;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch0;
+    uint32_t reserved_070[36];
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch1;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch1;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch1;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch1;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch1;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch1;
+    volatile dma2d_out_push_chn_reg_t out_push_ch1;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch1;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch1;
+    volatile dma2d_out_state_chn_reg_t out_state_ch1;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch1;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch1;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch1;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch1;
+    uint32_t reserved_144;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch1;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch1;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch1;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch1;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch1;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch1;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch1;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch1;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch1;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch1;
+    uint32_t reserved_170[36];
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch2;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch2;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch2;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch2;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch2;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch2;
+    volatile dma2d_out_push_chn_reg_t out_push_ch2;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch2;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch2;
+    volatile dma2d_out_state_chn_reg_t out_state_ch2;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch2;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch2;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch2;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch2;
+    uint32_t reserved_244;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch2;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch2;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch2;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch2;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch2;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch2;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch2;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch2;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch2;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch2;
+    uint32_t reserved_270[36];
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch3;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch3;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch3;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch3;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch3;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch3;
+    volatile dma2d_out_push_chn_reg_t out_push_ch3;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch3;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch3;
+    volatile dma2d_out_state_chn_reg_t out_state_ch3;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch3;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch3;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch3;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch3;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch3;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch3;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch3;
+    uint32_t reserved_344;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch3;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch3;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch3;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch3;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch3;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch3;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch3;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch3;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch3;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch3;
+    uint32_t reserved_370[100];
+    volatile dma2d_in_conf0_chn_reg_t in_conf0_ch0;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch0;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch0;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st_ch0;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch0;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status_ch0;
+    volatile dma2d_in_pop_chn_reg_t in_pop_ch0;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch0;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch0;
+    volatile dma2d_in_state_chn_reg_t in_state_ch0;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr_ch0;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch0;
+    volatile dma2d_in_arb_chn_reg_t in_arb_ch0;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch0;
+    volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch0;
+    volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch0;
+    volatile dma2d_in_scramble_chn_reg_t in_scramble_ch0;
+    volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch0;
+    volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch0;
+    volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch0;
+    volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch0;
+    volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch0;
+    volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch0;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch0;
+    uint32_t reserved_570[36];
+    volatile dma2d_in_conf0_chn_reg_t in_conf0_ch1;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch1;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch1;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st_ch1;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch1;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status_ch1;
+    volatile dma2d_in_pop_chn_reg_t in_pop_ch1;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch1;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch1;
+    volatile dma2d_in_state_chn_reg_t in_state_ch1;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr_ch1;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch1;
+    volatile dma2d_in_arb_chn_reg_t in_arb_ch1;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch1;
+    volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch1;
+    volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch1;
+    volatile dma2d_in_scramble_chn_reg_t in_scramble_ch1;
+    volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch1;
+    volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch1;
+    volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch1;
+    volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch1;
+    volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch1;
+    volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch1;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch1;
+    uint32_t reserved_670[36];
+    volatile dma2d_in_conf0_chn_reg_t in_conf0_ch2;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch2;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch2;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st_ch2;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch2;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status_ch2;
+    volatile dma2d_in_pop_chn_reg_t in_pop_ch2;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch2;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch2;
+    volatile dma2d_in_state_chn_reg_t in_state_ch2;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr_ch2;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch2;
+    volatile dma2d_in_arb_chn_reg_t in_arb_ch2;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch2;
+    volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch2;
+    volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch2;
+    volatile dma2d_in_scramble_chn_reg_t in_scramble_ch2;
+    volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch2;
+    volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch2;
+    volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch2;
+    volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch2;
+    volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch2;
+    volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch2;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch2;
+    uint32_t reserved_770[164];
+    volatile dma2d_axi_err_reg_t axi_err;
+    volatile dma2d_rst_conf_reg_t rst_conf;
+    volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile dma2d_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile dma2d_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile dma2d_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile dma2d_out_arb_config_reg_t out_arb_config;
+    volatile dma2d_in_arb_config_reg_t in_arb_config;
+    volatile dma2d_rdn_result_reg_t rdn_result;
+    volatile dma2d_rdn_eco_high_reg_t rdn_eco_high;
+    volatile dma2d_rdn_eco_low_reg_t rdn_eco_low;
+    volatile dma2d_date_reg_t date;
+} dma2d_dev_t;
+
+extern dma2d_dev_t DMA2D;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dma2d_dev_t) == 0xa30, "Invalid size of dma2d_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dma2d_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/dma2d_reg.h
new file mode 100644
index 0000000000..b16c0654e9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dma2d_reg.h
@@ -0,0 +1,5270 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13427
+
+/** DMA2D_OUT_CONF0_CH0_REG register
+ *  Configures the tx direction of channel 0
+ */
+#define DMA2D_OUT_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x0)
+/** DMA2D_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH0    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH0_M  (DMA2D_OUT_AUTO_WRBACK_CH0_V << DMA2D_OUT_AUTO_WRBACK_CH0_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH0_S  0
+/** DMA2D_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH0    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH0_M  (DMA2D_OUT_EOF_MODE_CH0_V << DMA2D_OUT_EOF_MODE_CH0_S)
+#define DMA2D_OUT_EOF_MODE_CH0_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH0_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH0_M  (DMA2D_OUTDSCR_BURST_EN_CH0_V << DMA2D_OUTDSCR_BURST_EN_CH0_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH0_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH0_M  (DMA2D_OUT_ECC_AES_EN_CH0_V << DMA2D_OUT_ECC_AES_EN_CH0_S)
+#define DMA2D_OUT_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH0_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH0_M  (DMA2D_OUT_CHECK_OWNER_CH0_V << DMA2D_OUT_CHECK_OWNER_CH0_S)
+#define DMA2D_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH0_S  4
+/** DMA2D_OUT_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH0_M  (DMA2D_OUT_LOOP_TEST_CH0_V << DMA2D_OUT_LOOP_TEST_CH0_S)
+#define DMA2D_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH0_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH0_V << DMA2D_OUT_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_M  (DMA2D_OUT_DSCR_PORT_EN_CH0_V << DMA2D_OUT_DSCR_PORT_EN_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_M  (DMA2D_OUT_PAGE_BOUND_EN_CH0_V << DMA2D_OUT_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH0_M  (DMA2D_OUT_REORDER_EN_CH0_V << DMA2D_OUT_REORDER_EN_CH0_S)
+#define DMA2D_OUT_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH0_S  16
+/** DMA2D_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH0    (BIT(24))
+#define DMA2D_OUT_RST_CH0_M  (DMA2D_OUT_RST_CH0_V << DMA2D_OUT_RST_CH0_S)
+#define DMA2D_OUT_RST_CH0_V  0x00000001U
+#define DMA2D_OUT_RST_CH0_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH0_M  (DMA2D_OUT_CMD_DISABLE_CH0_V << DMA2D_OUT_CMD_DISABLE_CH0_S)
+#define DMA2D_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH0_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_OUT_INT_RAW_CH0_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x4)
+/** DMA2D_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_RAW_M  (DMA2D_OUT_DONE_CH0_INT_RAW_V << DMA2D_OUT_DONE_CH0_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_RAW_M  (DMA2D_OUT_EOF_CH0_INT_RAW_V << DMA2D_OUT_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x8)
+/** DMA2D_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ENA_M  (DMA2D_OUT_DONE_CH0_INT_ENA_V << DMA2D_OUT_DONE_CH0_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ENA_M  (DMA2D_OUT_EOF_CH0_INT_ENA_V << DMA2D_OUT_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0xc)
+/** DMA2D_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ST_M  (DMA2D_OUT_DONE_CH0_INT_ST_V << DMA2D_OUT_DONE_CH0_INT_ST_S)
+#define DMA2D_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ST_M  (DMA2D_OUT_EOF_CH0_INT_ST_V << DMA2D_OUT_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x10)
+/** DMA2D_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_CLR_M  (DMA2D_OUT_DONE_CH0_INT_CLR_V << DMA2D_OUT_DONE_CH0_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_CLR_M  (DMA2D_OUT_EOF_CH0_INT_CLR_V << DMA2D_OUT_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH0_REG register
+ *  Represents the status of the tx fifo of channel 0
+ */
+#define DMA2D_OUTFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x14)
+/** DMA2D_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH0_M  (DMA2D_OUTFIFO_FULL_L2_CH0_V << DMA2D_OUTFIFO_FULL_L2_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH0_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_M  (DMA2D_OUTFIFO_EMPTY_L2_CH0_V << DMA2D_OUTFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_M  (DMA2D_OUTFIFO_CNT_L2_CH0_V << DMA2D_OUTFIFO_CNT_L2_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH0_V << DMA2D_OUT_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH0_V << DMA2D_OUT_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH0_V << DMA2D_OUT_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH0_V << DMA2D_OUT_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH0_V << DMA2D_OUT_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH0_V << DMA2D_OUT_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH0_V << DMA2D_OUT_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH0_V << DMA2D_OUT_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH0_M  (DMA2D_OUTFIFO_FULL_L1_CH0_V << DMA2D_OUTFIFO_FULL_L1_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH0_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_M  (DMA2D_OUTFIFO_EMPTY_L1_CH0_V << DMA2D_OUTFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_M  (DMA2D_OUTFIFO_CNT_L1_CH0_V << DMA2D_OUTFIFO_CNT_L1_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH0_M  (DMA2D_OUTFIFO_FULL_L3_CH0_V << DMA2D_OUTFIFO_FULL_L3_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH0_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_M  (DMA2D_OUTFIFO_EMPTY_L3_CH0_V << DMA2D_OUTFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_M  (DMA2D_OUTFIFO_CNT_L3_CH0_V << DMA2D_OUTFIFO_CNT_L3_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_OUT_PUSH_CH0_REG register
+ *  Configures the tx fifo of channel 0
+ */
+#define DMA2D_OUT_PUSH_CH0_REG (DR_REG_DMA2D_BASE + 0x18)
+/** DMA2D_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH0    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_M  (DMA2D_OUTFIFO_WDATA_CH0_V << DMA2D_OUTFIFO_WDATA_CH0_S)
+#define DMA2D_OUTFIFO_WDATA_CH0_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_S  0
+/** DMA2D_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH0    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH0_M  (DMA2D_OUTFIFO_PUSH_CH0_V << DMA2D_OUTFIFO_PUSH_CH0_S)
+#define DMA2D_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH0_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH0_REG register
+ *  Configures the tx descriptor operations of channel 0
+ */
+#define DMA2D_OUT_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x1c)
+/** DMA2D_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH0    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH0_M  (DMA2D_OUTLINK_STOP_CH0_V << DMA2D_OUTLINK_STOP_CH0_S)
+#define DMA2D_OUTLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH0_S  20
+/** DMA2D_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH0    (BIT(21))
+#define DMA2D_OUTLINK_START_CH0_M  (DMA2D_OUTLINK_START_CH0_V << DMA2D_OUTLINK_START_CH0_S)
+#define DMA2D_OUTLINK_START_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH0_S  21
+/** DMA2D_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH0    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH0_M  (DMA2D_OUTLINK_RESTART_CH0_V << DMA2D_OUTLINK_RESTART_CH0_S)
+#define DMA2D_OUTLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH0_S  22
+/** DMA2D_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH0    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH0_M  (DMA2D_OUTLINK_PARK_CH0_V << DMA2D_OUTLINK_PARK_CH0_S)
+#define DMA2D_OUTLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH0_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH0_REG register
+ *  Configures the tx descriptor address of channel 0
+ */
+#define DMA2D_OUT_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x20)
+/** DMA2D_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_M  (DMA2D_OUTLINK_ADDR_CH0_V << DMA2D_OUTLINK_ADDR_CH0_S)
+#define DMA2D_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_S  0
+
+/** DMA2D_OUT_STATE_CH0_REG register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+#define DMA2D_OUT_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x24)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_M  (DMA2D_OUTLINK_DSCR_ADDR_CH0_V << DMA2D_OUTLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_M  (DMA2D_OUT_DSCR_STATE_CH0_V << DMA2D_OUT_DSCR_STATE_CH0_S)
+#define DMA2D_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_S  18
+/** DMA2D_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH0    0x0000000FU
+#define DMA2D_OUT_STATE_CH0_M  (DMA2D_OUT_STATE_CH0_V << DMA2D_OUT_STATE_CH0_S)
+#define DMA2D_OUT_STATE_CH0_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH0_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH0    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH0_M  (DMA2D_OUT_RESET_AVAIL_CH0_V << DMA2D_OUT_RESET_AVAIL_CH0_S)
+#define DMA2D_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH0_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x28)
+/** DMA2D_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_M  (DMA2D_OUT_EOF_DES_ADDR_CH0_V << DMA2D_OUT_EOF_DES_ADDR_CH0_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x2c)
+/** DMA2D_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_M  (DMA2D_OUTLINK_DSCR_CH0_V << DMA2D_OUTLINK_DSCR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x30)
+/** DMA2D_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_M  (DMA2D_OUTLINK_DSCR_BF0_CH0_V << DMA2D_OUTLINK_DSCR_BF0_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x34)
+/** DMA2D_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_M  (DMA2D_OUTLINK_DSCR_BF1_CH0_V << DMA2D_OUTLINK_DSCR_BF1_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH0_REG register
+ *  Configures the tx peripheral of channel 0
+ */
+#define DMA2D_OUT_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x38)
+/** DMA2D_OUT_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH0    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_M  (DMA2D_OUT_PERI_SEL_CH0_V << DMA2D_OUT_PERI_SEL_CH0_S)
+#define DMA2D_OUT_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_S  0
+
+/** DMA2D_OUT_ARB_CH0_REG register
+ *  Configures the tx arbiter of channel 0
+ */
+#define DMA2D_OUT_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x3c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH0    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH0_M  (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH0_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH0_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH0_REG register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+#define DMA2D_OUT_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x40)
+/** DMA2D_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH0    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_M  (DMA2D_OUTFIFO_RO_CNT_CH0_V << DMA2D_OUTFIFO_RO_CNT_CH0_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH0_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_M  (DMA2D_OUT_RO_WR_STATE_CH0_V << DMA2D_OUT_RO_WR_STATE_CH0_S)
+#define DMA2D_OUT_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_M  (DMA2D_OUT_RO_RD_STATE_CH0_V << DMA2D_OUT_RO_RD_STATE_CH0_S)
+#define DMA2D_OUT_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_M  (DMA2D_OUT_PIXEL_BYTE_CH0_V << DMA2D_OUT_PIXEL_BYTE_CH0_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH0_V << DMA2D_OUT_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_S  14
+
+/** DMA2D_OUT_RO_PD_CONF_CH0_REG register
+ *  Configures the tx reorder memory of channel 0
+ */
+#define DMA2D_OUT_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x44)
+/** DMA2D_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_M  (DMA2D_OUT_RO_RAM_CLK_FO_CH0_V << DMA2D_OUT_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_OUT_COLOR_CONVERT_CH0_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x48)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH0_V << DMA2D_OUT_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH0_REG register
+ *  Configures the tx scramble of channel 0
+ */
+#define DMA2D_OUT_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x4c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x50)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_M  (DMA2D_OUT_COLOR_PARAM_H0_CH0_V << DMA2D_OUT_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x54)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_M  (DMA2D_OUT_COLOR_PARAM_H1_CH0_V << DMA2D_OUT_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x58)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_M  (DMA2D_OUT_COLOR_PARAM_M0_CH0_V << DMA2D_OUT_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x5c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_M  (DMA2D_OUT_COLOR_PARAM_M1_CH0_V << DMA2D_OUT_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x60)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_M  (DMA2D_OUT_COLOR_PARAM_L0_CH0_V << DMA2D_OUT_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x64)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_M  (DMA2D_OUT_COLOR_PARAM_L1_CH0_V << DMA2D_OUT_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH0_REG register
+ *  Configures the tx etm of channel 0
+ */
+#define DMA2D_OUT_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x68)
+/** DMA2D_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH0    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH0_M  (DMA2D_OUT_ETM_EN_CH0_V << DMA2D_OUT_ETM_EN_CH0_S)
+#define DMA2D_OUT_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH0_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_M  (DMA2D_OUT_ETM_LOOP_EN_CH0_V << DMA2D_OUT_ETM_LOOP_EN_CH0_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_M  (DMA2D_OUT_DSCR_TASK_MAK_CH0_V << DMA2D_OUT_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH0_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH0_REG (DR_REG_DMA2D_BASE + 0x6c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH0 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH0 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S  14
+
+/** DMA2D_OUT_CONF0_CH1_REG register
+ *  Configures the tx direction of channel 0
+ */
+#define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100)
+/** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH1    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH1_M  (DMA2D_OUT_AUTO_WRBACK_CH1_V << DMA2D_OUT_AUTO_WRBACK_CH1_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH1_S  0
+/** DMA2D_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH1    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH1_M  (DMA2D_OUT_EOF_MODE_CH1_V << DMA2D_OUT_EOF_MODE_CH1_S)
+#define DMA2D_OUT_EOF_MODE_CH1_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH1_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH1_M  (DMA2D_OUTDSCR_BURST_EN_CH1_V << DMA2D_OUTDSCR_BURST_EN_CH1_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH1_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH1_M  (DMA2D_OUT_ECC_AES_EN_CH1_V << DMA2D_OUT_ECC_AES_EN_CH1_S)
+#define DMA2D_OUT_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH1_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH1_M  (DMA2D_OUT_CHECK_OWNER_CH1_V << DMA2D_OUT_CHECK_OWNER_CH1_S)
+#define DMA2D_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH1_S  4
+/** DMA2D_OUT_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH1_M  (DMA2D_OUT_LOOP_TEST_CH1_V << DMA2D_OUT_LOOP_TEST_CH1_S)
+#define DMA2D_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH1_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH1_V << DMA2D_OUT_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_M  (DMA2D_OUT_DSCR_PORT_EN_CH1_V << DMA2D_OUT_DSCR_PORT_EN_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_M  (DMA2D_OUT_PAGE_BOUND_EN_CH1_V << DMA2D_OUT_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_OUT_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH1_M  (DMA2D_OUT_REORDER_EN_CH1_V << DMA2D_OUT_REORDER_EN_CH1_S)
+#define DMA2D_OUT_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH1_S  16
+/** DMA2D_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH1    (BIT(24))
+#define DMA2D_OUT_RST_CH1_M  (DMA2D_OUT_RST_CH1_V << DMA2D_OUT_RST_CH1_S)
+#define DMA2D_OUT_RST_CH1_V  0x00000001U
+#define DMA2D_OUT_RST_CH1_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH1_M  (DMA2D_OUT_CMD_DISABLE_CH1_V << DMA2D_OUT_CMD_DISABLE_CH1_S)
+#define DMA2D_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH1_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_OUT_INT_RAW_CH1_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104)
+/** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_RAW_M  (DMA2D_OUT_DONE_CH1_INT_RAW_V << DMA2D_OUT_DONE_CH1_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_RAW_M  (DMA2D_OUT_EOF_CH1_INT_RAW_V << DMA2D_OUT_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108)
+/** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ENA_M  (DMA2D_OUT_DONE_CH1_INT_ENA_V << DMA2D_OUT_DONE_CH1_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ENA_M  (DMA2D_OUT_EOF_CH1_INT_ENA_V << DMA2D_OUT_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c)
+/** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ST_M  (DMA2D_OUT_DONE_CH1_INT_ST_V << DMA2D_OUT_DONE_CH1_INT_ST_S)
+#define DMA2D_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ST_M  (DMA2D_OUT_EOF_CH1_INT_ST_V << DMA2D_OUT_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110)
+/** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_CLR_M  (DMA2D_OUT_DONE_CH1_INT_CLR_V << DMA2D_OUT_DONE_CH1_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_CLR_M  (DMA2D_OUT_EOF_CH1_INT_CLR_V << DMA2D_OUT_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH1_REG register
+ *  Represents the status of the tx fifo of channel 0
+ */
+#define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114)
+/** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH1_M  (DMA2D_OUTFIFO_FULL_L2_CH1_V << DMA2D_OUTFIFO_FULL_L2_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH1_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_M  (DMA2D_OUTFIFO_EMPTY_L2_CH1_V << DMA2D_OUTFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_M  (DMA2D_OUTFIFO_CNT_L2_CH1_V << DMA2D_OUTFIFO_CNT_L2_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH1_V << DMA2D_OUT_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH1_V << DMA2D_OUT_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH1_V << DMA2D_OUT_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH1_V << DMA2D_OUT_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH1_V << DMA2D_OUT_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH1_V << DMA2D_OUT_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH1_V << DMA2D_OUT_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH1_V << DMA2D_OUT_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH1_M  (DMA2D_OUTFIFO_FULL_L1_CH1_V << DMA2D_OUTFIFO_FULL_L1_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH1_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_M  (DMA2D_OUTFIFO_EMPTY_L1_CH1_V << DMA2D_OUTFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_M  (DMA2D_OUTFIFO_CNT_L1_CH1_V << DMA2D_OUTFIFO_CNT_L1_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH1_M  (DMA2D_OUTFIFO_FULL_L3_CH1_V << DMA2D_OUTFIFO_FULL_L3_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH1_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_M  (DMA2D_OUTFIFO_EMPTY_L3_CH1_V << DMA2D_OUTFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_M  (DMA2D_OUTFIFO_CNT_L3_CH1_V << DMA2D_OUTFIFO_CNT_L3_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_OUT_PUSH_CH1_REG register
+ *  Configures the tx fifo of channel 0
+ */
+#define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118)
+/** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH1    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_M  (DMA2D_OUTFIFO_WDATA_CH1_V << DMA2D_OUTFIFO_WDATA_CH1_S)
+#define DMA2D_OUTFIFO_WDATA_CH1_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_S  0
+/** DMA2D_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH1    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH1_M  (DMA2D_OUTFIFO_PUSH_CH1_V << DMA2D_OUTFIFO_PUSH_CH1_S)
+#define DMA2D_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH1_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH1_REG register
+ *  Configures the tx descriptor operations of channel 0
+ */
+#define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c)
+/** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH1    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH1_M  (DMA2D_OUTLINK_STOP_CH1_V << DMA2D_OUTLINK_STOP_CH1_S)
+#define DMA2D_OUTLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH1_S  20
+/** DMA2D_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH1    (BIT(21))
+#define DMA2D_OUTLINK_START_CH1_M  (DMA2D_OUTLINK_START_CH1_V << DMA2D_OUTLINK_START_CH1_S)
+#define DMA2D_OUTLINK_START_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH1_S  21
+/** DMA2D_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH1    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH1_M  (DMA2D_OUTLINK_RESTART_CH1_V << DMA2D_OUTLINK_RESTART_CH1_S)
+#define DMA2D_OUTLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH1_S  22
+/** DMA2D_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH1    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH1_M  (DMA2D_OUTLINK_PARK_CH1_V << DMA2D_OUTLINK_PARK_CH1_S)
+#define DMA2D_OUTLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH1_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH1_REG register
+ *  Configures the tx descriptor address of channel 0
+ */
+#define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120)
+/** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_M  (DMA2D_OUTLINK_ADDR_CH1_V << DMA2D_OUTLINK_ADDR_CH1_S)
+#define DMA2D_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_S  0
+
+/** DMA2D_OUT_STATE_CH1_REG register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+#define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_M  (DMA2D_OUTLINK_DSCR_ADDR_CH1_V << DMA2D_OUTLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_M  (DMA2D_OUT_DSCR_STATE_CH1_V << DMA2D_OUT_DSCR_STATE_CH1_S)
+#define DMA2D_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_S  18
+/** DMA2D_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH1    0x0000000FU
+#define DMA2D_OUT_STATE_CH1_M  (DMA2D_OUT_STATE_CH1_V << DMA2D_OUT_STATE_CH1_S)
+#define DMA2D_OUT_STATE_CH1_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH1_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH1    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH1_M  (DMA2D_OUT_RESET_AVAIL_CH1_V << DMA2D_OUT_RESET_AVAIL_CH1_S)
+#define DMA2D_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH1_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128)
+/** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_M  (DMA2D_OUT_EOF_DES_ADDR_CH1_V << DMA2D_OUT_EOF_DES_ADDR_CH1_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c)
+/** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_M  (DMA2D_OUTLINK_DSCR_CH1_V << DMA2D_OUTLINK_DSCR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130)
+/** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_M  (DMA2D_OUTLINK_DSCR_BF0_CH1_V << DMA2D_OUTLINK_DSCR_BF0_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134)
+/** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_M  (DMA2D_OUTLINK_DSCR_BF1_CH1_V << DMA2D_OUTLINK_DSCR_BF1_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH1_REG register
+ *  Configures the tx peripheral of channel 0
+ */
+#define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138)
+/** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH1    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_M  (DMA2D_OUT_PERI_SEL_CH1_V << DMA2D_OUT_PERI_SEL_CH1_S)
+#define DMA2D_OUT_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_S  0
+
+/** DMA2D_OUT_ARB_CH1_REG register
+ *  Configures the tx arbiter of channel 0
+ */
+#define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH1    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH1_M  (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH1_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH1_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH1_REG register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+#define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140)
+/** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH1    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_M  (DMA2D_OUTFIFO_RO_CNT_CH1_V << DMA2D_OUTFIFO_RO_CNT_CH1_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH1_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH1 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_M  (DMA2D_OUT_RO_WR_STATE_CH1_V << DMA2D_OUT_RO_WR_STATE_CH1_S)
+#define DMA2D_OUT_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH1 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_M  (DMA2D_OUT_RO_RD_STATE_CH1_V << DMA2D_OUT_RO_RD_STATE_CH1_S)
+#define DMA2D_OUT_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH1 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_M  (DMA2D_OUT_PIXEL_BYTE_CH1_V << DMA2D_OUT_PIXEL_BYTE_CH1_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH1 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH1_V << DMA2D_OUT_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH1_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH1_V << DMA2D_OUT_COLOR_INPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH1_REG register
+ *  Configures the tx scramble of channel 0
+ */
+#define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_M  (DMA2D_OUT_COLOR_PARAM_H0_CH1_V << DMA2D_OUT_COLOR_PARAM_H0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_M  (DMA2D_OUT_COLOR_PARAM_H1_CH1_V << DMA2D_OUT_COLOR_PARAM_H1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_M  (DMA2D_OUT_COLOR_PARAM_M0_CH1_V << DMA2D_OUT_COLOR_PARAM_M0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_M  (DMA2D_OUT_COLOR_PARAM_M1_CH1_V << DMA2D_OUT_COLOR_PARAM_M1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_M  (DMA2D_OUT_COLOR_PARAM_L0_CH1_V << DMA2D_OUT_COLOR_PARAM_L0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH1_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_M  (DMA2D_OUT_COLOR_PARAM_L1_CH1_V << DMA2D_OUT_COLOR_PARAM_L1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH1_REG register
+ *  Configures the tx etm of channel 0
+ */
+#define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168)
+/** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH1    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH1_M  (DMA2D_OUT_ETM_EN_CH1_V << DMA2D_OUT_ETM_EN_CH1_S)
+#define DMA2D_OUT_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH1_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_M  (DMA2D_OUT_ETM_LOOP_EN_CH1_V << DMA2D_OUT_ETM_LOOP_EN_CH1_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_M  (DMA2D_OUT_DSCR_TASK_MAK_CH1_V << DMA2D_OUT_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH1_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH1_REG (DR_REG_DMA2D_BASE + 0x16c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH1 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH1 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S  14
+
+/** DMA2D_OUT_CONF0_CH2_REG register
+ *  Configures the tx direction of channel 0
+ */
+#define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200)
+/** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH2    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH2_M  (DMA2D_OUT_AUTO_WRBACK_CH2_V << DMA2D_OUT_AUTO_WRBACK_CH2_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH2_S  0
+/** DMA2D_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH2    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH2_M  (DMA2D_OUT_EOF_MODE_CH2_V << DMA2D_OUT_EOF_MODE_CH2_S)
+#define DMA2D_OUT_EOF_MODE_CH2_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH2_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH2    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH2_M  (DMA2D_OUTDSCR_BURST_EN_CH2_V << DMA2D_OUTDSCR_BURST_EN_CH2_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH2_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH2    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH2_M  (DMA2D_OUT_ECC_AES_EN_CH2_V << DMA2D_OUT_ECC_AES_EN_CH2_S)
+#define DMA2D_OUT_ECC_AES_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH2_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH2    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH2_M  (DMA2D_OUT_CHECK_OWNER_CH2_V << DMA2D_OUT_CHECK_OWNER_CH2_S)
+#define DMA2D_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH2_S  4
+/** DMA2D_OUT_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH2    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH2_M  (DMA2D_OUT_LOOP_TEST_CH2_V << DMA2D_OUT_LOOP_TEST_CH2_S)
+#define DMA2D_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH2_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH2_V << DMA2D_OUT_MEM_BURST_LENGTH_CH2_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH2    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_M  (DMA2D_OUT_DSCR_PORT_EN_CH2_V << DMA2D_OUT_DSCR_PORT_EN_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_M  (DMA2D_OUT_PAGE_BOUND_EN_CH2_V << DMA2D_OUT_PAGE_BOUND_EN_CH2_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_S  12
+/** DMA2D_OUT_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH2    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH2_M  (DMA2D_OUT_REORDER_EN_CH2_V << DMA2D_OUT_REORDER_EN_CH2_S)
+#define DMA2D_OUT_REORDER_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH2_S  16
+/** DMA2D_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH2    (BIT(24))
+#define DMA2D_OUT_RST_CH2_M  (DMA2D_OUT_RST_CH2_V << DMA2D_OUT_RST_CH2_S)
+#define DMA2D_OUT_RST_CH2_V  0x00000001U
+#define DMA2D_OUT_RST_CH2_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH2    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH2_M  (DMA2D_OUT_CMD_DISABLE_CH2_V << DMA2D_OUT_CMD_DISABLE_CH2_S)
+#define DMA2D_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH2_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** DMA2D_OUT_INT_RAW_CH2_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204)
+/** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_RAW_M  (DMA2D_OUT_DONE_CH2_INT_RAW_V << DMA2D_OUT_DONE_CH2_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_RAW_M  (DMA2D_OUT_EOF_CH2_INT_RAW_V << DMA2D_OUT_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208)
+/** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ENA_M  (DMA2D_OUT_DONE_CH2_INT_ENA_V << DMA2D_OUT_DONE_CH2_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ENA_M  (DMA2D_OUT_EOF_CH2_INT_ENA_V << DMA2D_OUT_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c)
+/** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ST_M  (DMA2D_OUT_DONE_CH2_INT_ST_V << DMA2D_OUT_DONE_CH2_INT_ST_S)
+#define DMA2D_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ST_M  (DMA2D_OUT_EOF_CH2_INT_ST_V << DMA2D_OUT_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210)
+/** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_CLR_M  (DMA2D_OUT_DONE_CH2_INT_CLR_V << DMA2D_OUT_DONE_CH2_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_CLR_M  (DMA2D_OUT_EOF_CH2_INT_CLR_V << DMA2D_OUT_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH2_REG register
+ *  Represents the status of the tx fifo of channel 0
+ */
+#define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214)
+/** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH2    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH2_M  (DMA2D_OUTFIFO_FULL_L2_CH2_V << DMA2D_OUTFIFO_FULL_L2_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH2_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_M  (DMA2D_OUTFIFO_EMPTY_L2_CH2_V << DMA2D_OUTFIFO_EMPTY_L2_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH2    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_M  (DMA2D_OUTFIFO_CNT_L2_CH2_V << DMA2D_OUTFIFO_CNT_L2_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH2_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH2_V << DMA2D_OUT_REMAIN_UNDER_1B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH2_V << DMA2D_OUT_REMAIN_UNDER_2B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH2_V << DMA2D_OUT_REMAIN_UNDER_3B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH2_V << DMA2D_OUT_REMAIN_UNDER_4B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH2_V << DMA2D_OUT_REMAIN_UNDER_5B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH2_V << DMA2D_OUT_REMAIN_UNDER_6B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH2_V << DMA2D_OUT_REMAIN_UNDER_7B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH2_V << DMA2D_OUT_REMAIN_UNDER_8B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH2    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH2_M  (DMA2D_OUTFIFO_FULL_L1_CH2_V << DMA2D_OUTFIFO_FULL_L1_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH2_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_M  (DMA2D_OUTFIFO_EMPTY_L1_CH2_V << DMA2D_OUTFIFO_EMPTY_L1_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_M  (DMA2D_OUTFIFO_CNT_L1_CH2_V << DMA2D_OUTFIFO_CNT_L1_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH2    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH2_M  (DMA2D_OUTFIFO_FULL_L3_CH2_V << DMA2D_OUTFIFO_FULL_L3_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH2_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_M  (DMA2D_OUTFIFO_EMPTY_L3_CH2_V << DMA2D_OUTFIFO_EMPTY_L3_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_M  (DMA2D_OUTFIFO_CNT_L3_CH2_V << DMA2D_OUTFIFO_CNT_L3_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_S  24
+
+/** DMA2D_OUT_PUSH_CH2_REG register
+ *  Configures the tx fifo of channel 0
+ */
+#define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218)
+/** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH2    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_M  (DMA2D_OUTFIFO_WDATA_CH2_V << DMA2D_OUTFIFO_WDATA_CH2_S)
+#define DMA2D_OUTFIFO_WDATA_CH2_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_S  0
+/** DMA2D_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH2    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH2_M  (DMA2D_OUTFIFO_PUSH_CH2_V << DMA2D_OUTFIFO_PUSH_CH2_S)
+#define DMA2D_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH2_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH2_REG register
+ *  Configures the tx descriptor operations of channel 0
+ */
+#define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c)
+/** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH2    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH2_M  (DMA2D_OUTLINK_STOP_CH2_V << DMA2D_OUTLINK_STOP_CH2_S)
+#define DMA2D_OUTLINK_STOP_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH2_S  20
+/** DMA2D_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH2    (BIT(21))
+#define DMA2D_OUTLINK_START_CH2_M  (DMA2D_OUTLINK_START_CH2_V << DMA2D_OUTLINK_START_CH2_S)
+#define DMA2D_OUTLINK_START_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH2_S  21
+/** DMA2D_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH2    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH2_M  (DMA2D_OUTLINK_RESTART_CH2_V << DMA2D_OUTLINK_RESTART_CH2_S)
+#define DMA2D_OUTLINK_RESTART_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH2_S  22
+/** DMA2D_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH2    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH2_M  (DMA2D_OUTLINK_PARK_CH2_V << DMA2D_OUTLINK_PARK_CH2_S)
+#define DMA2D_OUTLINK_PARK_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH2_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH2_REG register
+ *  Configures the tx descriptor address of channel 0
+ */
+#define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220)
+/** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_M  (DMA2D_OUTLINK_ADDR_CH2_V << DMA2D_OUTLINK_ADDR_CH2_S)
+#define DMA2D_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_S  0
+
+/** DMA2D_OUT_STATE_CH2_REG register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+#define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_M  (DMA2D_OUTLINK_DSCR_ADDR_CH2_V << DMA2D_OUTLINK_DSCR_ADDR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_S  0
+/** DMA2D_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_M  (DMA2D_OUT_DSCR_STATE_CH2_V << DMA2D_OUT_DSCR_STATE_CH2_S)
+#define DMA2D_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_S  18
+/** DMA2D_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH2    0x0000000FU
+#define DMA2D_OUT_STATE_CH2_M  (DMA2D_OUT_STATE_CH2_V << DMA2D_OUT_STATE_CH2_S)
+#define DMA2D_OUT_STATE_CH2_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH2_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH2    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH2_M  (DMA2D_OUT_RESET_AVAIL_CH2_V << DMA2D_OUT_RESET_AVAIL_CH2_S)
+#define DMA2D_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH2_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228)
+/** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_M  (DMA2D_OUT_EOF_DES_ADDR_CH2_V << DMA2D_OUT_EOF_DES_ADDR_CH2_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c)
+/** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_M  (DMA2D_OUTLINK_DSCR_CH2_V << DMA2D_OUTLINK_DSCR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230)
+/** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_M  (DMA2D_OUTLINK_DSCR_BF0_CH2_V << DMA2D_OUTLINK_DSCR_BF0_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234)
+/** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_M  (DMA2D_OUTLINK_DSCR_BF1_CH2_V << DMA2D_OUTLINK_DSCR_BF1_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH2_REG register
+ *  Configures the tx peripheral of channel 0
+ */
+#define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238)
+/** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH2    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_M  (DMA2D_OUT_PERI_SEL_CH2_V << DMA2D_OUT_PERI_SEL_CH2_S)
+#define DMA2D_OUT_PERI_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_S  0
+
+/** DMA2D_OUT_ARB_CH2_REG register
+ *  Configures the tx arbiter of channel 0
+ */
+#define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH2    0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH2_M  (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH2_V  0x00000003U
+#define DMA2D_OUT_ARB_PRIORITY_CH2_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH2_REG register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+#define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240)
+/** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH2    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_M  (DMA2D_OUTFIFO_RO_CNT_CH2_V << DMA2D_OUTFIFO_RO_CNT_CH2_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH2_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH2 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_M  (DMA2D_OUT_RO_WR_STATE_CH2_V << DMA2D_OUT_RO_WR_STATE_CH2_S)
+#define DMA2D_OUT_RO_WR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH2 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_M  (DMA2D_OUT_RO_RD_STATE_CH2_V << DMA2D_OUT_RO_RD_STATE_CH2_S)
+#define DMA2D_OUT_RO_RD_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH2 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH2    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_M  (DMA2D_OUT_PIXEL_BYTE_CH2_V << DMA2D_OUT_PIXEL_BYTE_CH2_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH2_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH2 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH2_V << DMA2D_OUT_BURST_BLOCK_NUM_CH2_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH2_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH2_V << DMA2D_OUT_COLOR_INPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH2_REG register
+ *  Configures the tx scramble of channel 0
+ */
+#define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_M  (DMA2D_OUT_COLOR_PARAM_H0_CH2_V << DMA2D_OUT_COLOR_PARAM_H0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_M  (DMA2D_OUT_COLOR_PARAM_H1_CH2_V << DMA2D_OUT_COLOR_PARAM_H1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_M  (DMA2D_OUT_COLOR_PARAM_M0_CH2_V << DMA2D_OUT_COLOR_PARAM_M0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_M  (DMA2D_OUT_COLOR_PARAM_M1_CH2_V << DMA2D_OUT_COLOR_PARAM_M1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_M  (DMA2D_OUT_COLOR_PARAM_L0_CH2_V << DMA2D_OUT_COLOR_PARAM_L0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH2_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_M  (DMA2D_OUT_COLOR_PARAM_L1_CH2_V << DMA2D_OUT_COLOR_PARAM_L1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH2_REG register
+ *  Configures the tx etm of channel 0
+ */
+#define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268)
+/** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH2    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH2_M  (DMA2D_OUT_ETM_EN_CH2_V << DMA2D_OUT_ETM_EN_CH2_S)
+#define DMA2D_OUT_ETM_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH2_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH2    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_M  (DMA2D_OUT_ETM_LOOP_EN_CH2_V << DMA2D_OUT_ETM_LOOP_EN_CH2_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_M  (DMA2D_OUT_DSCR_TASK_MAK_CH2_V << DMA2D_OUT_DSCR_TASK_MAK_CH2_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH2_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH2_REG (DR_REG_DMA2D_BASE + 0x26c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH2 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH2 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S  14
+
+/** DMA2D_IN_CONF0_CH0_REG register
+ *  Configures the rx direction of channel 0
+ */
+#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500)
+/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH0    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH0_M  (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH0_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH0_S  0
+/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH0_M  (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S)
+#define DMA2D_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH0_S  2
+/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH0_M  (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S)
+#define DMA2D_IN_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH0_S  3
+/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH0_M  (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S)
+#define DMA2D_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH0_S  4
+/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH0_M  (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S)
+#define DMA2D_IN_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH0_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M  (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH0_M  (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_M  (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH0_M  (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S)
+#define DMA2D_IN_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH0_S  16
+/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH0    (BIT(24))
+#define DMA2D_IN_RST_CH0_M  (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S)
+#define DMA2D_IN_RST_CH0_V  0x00000001U
+#define DMA2D_IN_RST_CH0_S  24
+/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH0_M  (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S)
+#define DMA2D_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH0_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_IN_INT_RAW_CH0_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504)
+/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_RAW_M  (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S)
+#define DMA2D_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508)
+/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ENA_M  (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S)
+#define DMA2D_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH0_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c)
+/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ST_M  (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S)
+#define DMA2D_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M  (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M  (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510)
+/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_CLR_M  (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S)
+#define DMA2D_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH0_REG register
+ *  Represents the status of the rx fifo of channel 0
+ */
+#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514)
+/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH0_M  (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S)
+#define DMA2D_INFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH0_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH0_M  (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_M  (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S)
+#define DMA2D_INFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M  (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M  (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M  (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M  (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M  (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M  (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M  (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M  (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH0_M  (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S)
+#define DMA2D_INFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH0_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH0_M  (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_M  (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S)
+#define DMA2D_INFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_S  17
+/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH0_M  (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S)
+#define DMA2D_INFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH0_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH0_M  (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_M  (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S)
+#define DMA2D_INFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_IN_POP_CH0_REG register
+ *  Configures the rx fifo of channel 0
+ */
+#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518)
+/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH0    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_M  (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S)
+#define DMA2D_INFIFO_RDATA_CH0_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_S  0
+/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH0    (BIT(11))
+#define DMA2D_INFIFO_POP_CH0_M  (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S)
+#define DMA2D_INFIFO_POP_CH0_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH0_S  11
+
+/** DMA2D_IN_LINK_CONF_CH0_REG register
+ *  Configures the rx descriptor operations of channel 0
+ */
+#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c)
+/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
+ *  Configure the value of the owner field written back to the inlink descriptor.
+ *  1: Write back 1. 0: Write back 0.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH0    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH0_M  (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S)
+#define DMA2D_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH0_S  20
+/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH0    (BIT(21))
+#define DMA2D_INLINK_STOP_CH0_M  (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S)
+#define DMA2D_INLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH0_S  21
+/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH0    (BIT(22))
+#define DMA2D_INLINK_START_CH0_M  (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S)
+#define DMA2D_INLINK_START_CH0_V  0x00000001U
+#define DMA2D_INLINK_START_CH0_S  22
+/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH0    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH0_M  (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S)
+#define DMA2D_INLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH0_S  23
+/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH0    (BIT(24))
+#define DMA2D_INLINK_PARK_CH0_M  (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S)
+#define DMA2D_INLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH0_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH0_REG register
+ *  Configures the rx descriptor address of channel 0
+ */
+#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520)
+/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_M  (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S)
+#define DMA2D_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_S  0
+
+/** DMA2D_IN_STATE_CH0_REG register
+ *  Represents the working status of the rx descriptor of channel 0
+ */
+#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524)
+/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_M  (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_M  (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S)
+#define DMA2D_IN_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_S  18
+/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH0    0x00000007U
+#define DMA2D_IN_STATE_CH0_M  (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S)
+#define DMA2D_IN_STATE_CH0_V  0x00000007U
+#define DMA2D_IN_STATE_CH0_S  20
+/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH0    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH0_M  (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S)
+#define DMA2D_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH0_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_DSCR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530)
+/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_M  (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S)
+#define DMA2D_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534)
+/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_M  (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S)
+#define DMA2D_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538)
+/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_M  (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S)
+#define DMA2D_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_IN_PERI_SEL_CH0_REG register
+ *  Configures the rx peripheral of channel 0
+ */
+#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c)
+/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH0    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_M  (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S)
+#define DMA2D_IN_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_S  0
+
+/** DMA2D_IN_ARB_CH0_REG register
+ *  Configures the rx arbiter of channel 0
+ */
+#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M  (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH0    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH0_M  (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S)
+#define DMA2D_IN_ARB_PRIORITY_CH0_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH0_S  4
+
+/** DMA2D_IN_RO_STATUS_CH0_REG register
+ *  Represents the status of the rx reorder module of channel 0
+ */
+#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544)
+/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH0    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_M  (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S)
+#define DMA2D_INFIFO_RO_CNT_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_S  0
+/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_M  (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S)
+#define DMA2D_IN_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_S  5
+/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_M  (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S)
+#define DMA2D_IN_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_M  (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S)
+#define DMA2D_IN_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M  (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S  13
+
+/** DMA2D_IN_RO_PD_CONF_CH0_REG register
+ *  Configures the rx reorder memory of channel 0
+ */
+#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548)
+/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M  (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_IN_COLOR_CONVERT_CH0_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c)
+/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  output directly
+ */
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M  (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+ *  1: YUV422      2: YUV444/420      7: disable color space convert
+ */
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M  (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_IN_SCRAMBLE_CH0_REG register
+ *  Configures the rx scramble of channel 0
+ */
+#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550)
+/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S  0
+/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0;
+ *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+ *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S  3
+
+/** DMA2D_IN_COLOR_PARAM0_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554)
+/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_M  (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM1_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558)
+/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_M  (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM2_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c)
+/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_M  (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM3_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560)
+/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_M  (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM4_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564)
+/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_M  (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM5_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568)
+/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_M  (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_IN_ETM_CONF_CH0_REG register
+ *  Configures the rx etm of channel 0
+ */
+#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c)
+/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH0    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH0_M  (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S)
+#define DMA2D_IN_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH0_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH0_M  (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_M  (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_IN_CONF0_CH1_REG register
+ *  Configures the rx direction of channel 0
+ */
+#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600)
+/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH1    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH1_M  (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH1_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH1_S  0
+/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH1_M  (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S)
+#define DMA2D_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH1_S  2
+/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH1_M  (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S)
+#define DMA2D_IN_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH1_S  3
+/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH1_M  (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S)
+#define DMA2D_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH1_S  4
+/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH1_M  (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S)
+#define DMA2D_IN_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH1_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M  (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH1_M  (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_M  (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH1_M  (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S)
+#define DMA2D_IN_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH1_S  16
+/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH1    (BIT(24))
+#define DMA2D_IN_RST_CH1_M  (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S)
+#define DMA2D_IN_RST_CH1_V  0x00000001U
+#define DMA2D_IN_RST_CH1_S  24
+/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH1_M  (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S)
+#define DMA2D_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH1_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_IN_INT_RAW_CH1_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604)
+/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_RAW_M  (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S)
+#define DMA2D_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608)
+/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ENA_M  (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S)
+#define DMA2D_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH1_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c)
+/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ST_M  (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S)
+#define DMA2D_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M  (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M  (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610)
+/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_CLR_M  (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S)
+#define DMA2D_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH1_REG register
+ *  Represents the status of the rx fifo of channel 0
+ */
+#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614)
+/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH1_M  (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S)
+#define DMA2D_INFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH1_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH1_M  (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_M  (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S)
+#define DMA2D_INFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M  (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M  (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M  (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M  (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M  (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M  (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M  (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M  (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH1_M  (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S)
+#define DMA2D_INFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH1_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH1_M  (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_M  (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S)
+#define DMA2D_INFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_S  17
+/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH1_M  (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S)
+#define DMA2D_INFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH1_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH1_M  (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_M  (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S)
+#define DMA2D_INFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_IN_POP_CH1_REG register
+ *  Configures the rx fifo of channel 0
+ */
+#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618)
+/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH1    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_M  (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S)
+#define DMA2D_INFIFO_RDATA_CH1_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_S  0
+/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH1    (BIT(11))
+#define DMA2D_INFIFO_POP_CH1_M  (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S)
+#define DMA2D_INFIFO_POP_CH1_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH1_S  11
+
+/** DMA2D_IN_LINK_CONF_CH1_REG register
+ *  Configures the rx descriptor operations of channel 0
+ */
+#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c)
+/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1;
+ *  Configure the value of the owner field written back to the inlink descriptor.
+ *  1: Write back 1. 0: Write back 0.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH1    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH1_M  (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S)
+#define DMA2D_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH1_S  20
+/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH1    (BIT(21))
+#define DMA2D_INLINK_STOP_CH1_M  (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S)
+#define DMA2D_INLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH1_S  21
+/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH1    (BIT(22))
+#define DMA2D_INLINK_START_CH1_M  (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S)
+#define DMA2D_INLINK_START_CH1_V  0x00000001U
+#define DMA2D_INLINK_START_CH1_S  22
+/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH1    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH1_M  (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S)
+#define DMA2D_INLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH1_S  23
+/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH1    (BIT(24))
+#define DMA2D_INLINK_PARK_CH1_M  (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S)
+#define DMA2D_INLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH1_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH1_REG register
+ *  Configures the rx descriptor address of channel 0
+ */
+#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620)
+/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_M  (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S)
+#define DMA2D_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_S  0
+
+/** DMA2D_IN_STATE_CH1_REG register
+ *  Represents the working status of the rx descriptor of channel 0
+ */
+#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624)
+/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_M  (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_M  (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S)
+#define DMA2D_IN_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_S  18
+/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH1    0x00000007U
+#define DMA2D_IN_STATE_CH1_M  (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S)
+#define DMA2D_IN_STATE_CH1_V  0x00000007U
+#define DMA2D_IN_STATE_CH1_S  20
+/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH1    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH1_M  (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S)
+#define DMA2D_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH1_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_DSCR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630)
+/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_M  (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S)
+#define DMA2D_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634)
+/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_M  (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S)
+#define DMA2D_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638)
+/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_M  (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S)
+#define DMA2D_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_IN_PERI_SEL_CH1_REG register
+ *  Configures the rx peripheral of channel 0
+ */
+#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c)
+/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH1    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_M  (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S)
+#define DMA2D_IN_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_S  0
+
+/** DMA2D_IN_ARB_CH1_REG register
+ *  Configures the rx arbiter of channel 0
+ */
+#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M  (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [4]; default: 1;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH1    (BIT(4))
+#define DMA2D_IN_ARB_PRIORITY_CH1_M  (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S)
+#define DMA2D_IN_ARB_PRIORITY_CH1_V  0x00000001U
+#define DMA2D_IN_ARB_PRIORITY_CH1_S  4
+
+/** DMA2D_IN_RO_STATUS_CH1_REG register
+ *  Represents the status of the rx reorder module of channel 0
+ */
+#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644)
+/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH1    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_M  (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S)
+#define DMA2D_INFIFO_RO_CNT_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_S  0
+/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_M  (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S)
+#define DMA2D_IN_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_S  5
+/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_M  (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S)
+#define DMA2D_IN_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_M  (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S)
+#define DMA2D_IN_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M  (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S  13
+
+/** DMA2D_IN_ETM_CONF_CH1_REG register
+ *  Configures the rx etm of channel 0
+ */
+#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x648)
+/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH1    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH1_M  (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S)
+#define DMA2D_IN_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH1_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH1_M  (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_M  (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_AXI_ERR_REG register
+ *  Represents the status of th axi bus
+ */
+#define DMA2D_AXI_ERR_REG (DR_REG_DMA2D_BASE + 0xa00)
+/** DMA2D_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0;
+ *  AXI read id err cnt
+ */
+#define DMA2D_RID_ERR_CNT    0x0000000FU
+#define DMA2D_RID_ERR_CNT_M  (DMA2D_RID_ERR_CNT_V << DMA2D_RID_ERR_CNT_S)
+#define DMA2D_RID_ERR_CNT_V  0x0000000FU
+#define DMA2D_RID_ERR_CNT_S  0
+/** DMA2D_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0;
+ *  AXI read resp err cnt
+ */
+#define DMA2D_RRESP_ERR_CNT    0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_M  (DMA2D_RRESP_ERR_CNT_V << DMA2D_RRESP_ERR_CNT_S)
+#define DMA2D_RRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_S  4
+/** DMA2D_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0;
+ *  AXI write resp err cnt
+ */
+#define DMA2D_WRESP_ERR_CNT    0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_M  (DMA2D_WRESP_ERR_CNT_V << DMA2D_WRESP_ERR_CNT_S)
+#define DMA2D_WRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_S  8
+/** DMA2D_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0;
+ *  AXI read cmd fifo remain cmd count
+ */
+#define DMA2D_RD_FIFO_CNT    0x00000007U
+#define DMA2D_RD_FIFO_CNT_M  (DMA2D_RD_FIFO_CNT_V << DMA2D_RD_FIFO_CNT_S)
+#define DMA2D_RD_FIFO_CNT_V  0x00000007U
+#define DMA2D_RD_FIFO_CNT_S  12
+/** DMA2D_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0;
+ *  AXI read backup cmd fifo remain cmd count
+ */
+#define DMA2D_RD_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_M  (DMA2D_RD_BAK_FIFO_CNT_V << DMA2D_RD_BAK_FIFO_CNT_S)
+#define DMA2D_RD_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_S  15
+/** DMA2D_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0;
+ *  AXI write cmd fifo remain cmd count
+ */
+#define DMA2D_WR_FIFO_CNT    0x00000007U
+#define DMA2D_WR_FIFO_CNT_M  (DMA2D_WR_FIFO_CNT_V << DMA2D_WR_FIFO_CNT_S)
+#define DMA2D_WR_FIFO_CNT_V  0x00000007U
+#define DMA2D_WR_FIFO_CNT_S  19
+/** DMA2D_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0;
+ *  AXI write backup cmd fifo remain cmd count
+ */
+#define DMA2D_WR_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_M  (DMA2D_WR_BAK_FIFO_CNT_V << DMA2D_WR_BAK_FIFO_CNT_S)
+#define DMA2D_WR_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_S  22
+
+/** DMA2D_RST_CONF_REG register
+ *  Configures the reset of axi
+ */
+#define DMA2D_RST_CONF_REG (DR_REG_DMA2D_BASE + 0xa04)
+/** DMA2D_AXIM_RD_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+ */
+#define DMA2D_AXIM_RD_RST    (BIT(0))
+#define DMA2D_AXIM_RD_RST_M  (DMA2D_AXIM_RD_RST_V << DMA2D_AXIM_RD_RST_S)
+#define DMA2D_AXIM_RD_RST_V  0x00000001U
+#define DMA2D_AXIM_RD_RST_S  0
+/** DMA2D_AXIM_WR_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+ */
+#define DMA2D_AXIM_WR_RST    (BIT(1))
+#define DMA2D_AXIM_WR_RST_M  (DMA2D_AXIM_WR_RST_V << DMA2D_AXIM_WR_RST_S)
+#define DMA2D_AXIM_WR_RST_V  0x00000001U
+#define DMA2D_AXIM_WR_RST_S  1
+/** DMA2D_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define DMA2D_CLK_EN    (BIT(2))
+#define DMA2D_CLK_EN_M  (DMA2D_CLK_EN_V << DMA2D_CLK_EN_S)
+#define DMA2D_CLK_EN_V  0x00000001U
+#define DMA2D_CLK_EN_S  2
+
+/** DMA2D_INTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa08)
+/** DMA2D_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_M  (DMA2D_ACCESS_INTR_MEM_START_ADDR_V << DMA2D_ACCESS_INTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** DMA2D_INTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa0c)
+/** DMA2D_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_M  (DMA2D_ACCESS_INTR_MEM_END_ADDR_V << DMA2D_ACCESS_INTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa10)
+/** DMA2D_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_START_ADDR_V << DMA2D_ACCESS_EXTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa14)
+/** DMA2D_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_END_ADDR_V << DMA2D_ACCESS_EXTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_S  0
+
+/** DMA2D_OUT_ARB_CONFIG_REG register
+ *  Configures the tx arbiter
+ */
+#define DMA2D_OUT_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa18)
+/** DMA2D_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_OUT_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_M  (DMA2D_OUT_ARB_TIMEOUT_NUM_V << DMA2D_OUT_ARB_TIMEOUT_NUM_S)
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_WEIGHT_EN    (BIT(16))
+#define DMA2D_OUT_WEIGHT_EN_M  (DMA2D_OUT_WEIGHT_EN_V << DMA2D_OUT_WEIGHT_EN_S)
+#define DMA2D_OUT_WEIGHT_EN_V  0x00000001U
+#define DMA2D_OUT_WEIGHT_EN_S  16
+
+/** DMA2D_IN_ARB_CONFIG_REG register
+ *  Configures the rx arbiter
+ */
+#define DMA2D_IN_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa1c)
+/** DMA2D_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_IN_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_M  (DMA2D_IN_ARB_TIMEOUT_NUM_V << DMA2D_IN_ARB_TIMEOUT_NUM_S)
+#define DMA2D_IN_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_WEIGHT_EN    (BIT(16))
+#define DMA2D_IN_WEIGHT_EN_M  (DMA2D_IN_WEIGHT_EN_V << DMA2D_IN_WEIGHT_EN_S)
+#define DMA2D_IN_WEIGHT_EN_V  0x00000001U
+#define DMA2D_IN_WEIGHT_EN_S  16
+
+/** DMA2D_RDN_RESULT_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT_REG (DR_REG_DMA2D_BASE + 0xa20)
+/** DMA2D_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_ENA    (BIT(0))
+#define DMA2D_RDN_ENA_M  (DMA2D_RDN_ENA_V << DMA2D_RDN_ENA_S)
+#define DMA2D_RDN_ENA_V  0x00000001U
+#define DMA2D_RDN_ENA_S  0
+/** DMA2D_RDN_RESULT : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT    (BIT(1))
+#define DMA2D_RDN_RESULT_M  (DMA2D_RDN_RESULT_V << DMA2D_RDN_RESULT_S)
+#define DMA2D_RDN_RESULT_V  0x00000001U
+#define DMA2D_RDN_RESULT_S  1
+
+/** DMA2D_RDN_ECO_HIGH_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_HIGH_REG (DR_REG_DMA2D_BASE + 0xa24)
+/** DMA2D_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_HIGH    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_M  (DMA2D_RDN_ECO_HIGH_V << DMA2D_RDN_ECO_HIGH_S)
+#define DMA2D_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_S  0
+
+/** DMA2D_RDN_ECO_LOW_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_LOW_REG (DR_REG_DMA2D_BASE + 0xa28)
+/** DMA2D_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_LOW    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_M  (DMA2D_RDN_ECO_LOW_V << DMA2D_RDN_ECO_LOW_S)
+#define DMA2D_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_S  0
+
+/** DMA2D_DATE_REG register
+ *  register version.
+ */
+#define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c)
+/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 36716816;
+ *  register version.
+ */
+#define DMA2D_DATE    0xFFFFFFFFU
+#define DMA2D_DATE_M  (DMA2D_DATE_V << DMA2D_DATE_S)
+#define DMA2D_DATE_V  0xFFFFFFFFU
+#define DMA2D_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dma2d_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/dma2d_struct.h
new file mode 100644
index 0000000000..30fef532db
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dma2d_struct.h
@@ -0,0 +1,1827 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13427
+
+/** Group: out */
+/** Type of out_conf0_chn register
+ *  Configures the tx direction of channel 0
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_chn : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_chn:1;
+        /** out_eof_mode_chn : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_chn:1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn:1;
+        /** out_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_chn:1;
+        /** out_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn:1;
+        /** out_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn:1;
+        /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_chn:3;
+        /** out_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t out_macro_block_size_chn:2;
+        /** out_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t out_dscr_port_en_chn:1;
+        /** out_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** out_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t out_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** out_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_chn:1;
+        /** out_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_chn:1;
+        /** out_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_out_conf0_chn_reg_t;
+
+/** Type of out_int_raw_chn register
+ *  Raw interrupt status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_chn_int_raw:1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_chn_int_raw:1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_chn_int_raw:1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_chn_int_raw:1;
+        /** outfifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_raw:1;
+        /** outfifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_chn_int_raw:1;
+        /** outfifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_raw:1;
+        /** outfifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_chn_int_raw:1;
+        /** outfifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_raw:1;
+        /** outfifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l3_chn_int_raw:1;
+        /** outfifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_raw:1;
+        /** outfifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t outfifo_ro_udf_chn_int_raw:1;
+        /** out_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_raw_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena:1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena:1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena:1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena:1;
+        /** outfifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_ena:1;
+        /** outfifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_ena:1;
+        /** outfifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_ena:1;
+        /** outfifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_ena:1;
+        /** outfifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_ena:1;
+        /** outfifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_ena:1;
+        /** outfifo_ro_ovf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_ena:1;
+        /** outfifo_ro_udf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_ena:1;
+        /** out_dscr_task_ovf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_ena_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt status of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st:1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st:1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st:1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st:1;
+        /** outfifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_st:1;
+        /** outfifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_st:1;
+        /** outfifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_st:1;
+        /** outfifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_st:1;
+        /** outfifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_st:1;
+        /** outfifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_st:1;
+        /** outfifo_ro_ovf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_st:1;
+        /** outfifo_ro_udf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_st:1;
+        /** out_dscr_task_ovf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_st_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr:1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr:1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr:1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr:1;
+        /** outfifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_clr:1;
+        /** outfifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_clr:1;
+        /** outfifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_clr:1;
+        /** outfifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_clr:1;
+        /** outfifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_clr:1;
+        /** outfifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_clr:1;
+        /** outfifo_ro_ovf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_clr:1;
+        /** outfifo_ro_udf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_clr:1;
+        /** out_dscr_task_ovf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_clr_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Represents the status of the tx fifo of channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l2_chn:1;
+        /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l2_chn:1;
+        /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** out_remain_under_1b_chn : RO; bitpos: [7]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn:1;
+        /** out_remain_under_2b_chn : RO; bitpos: [8]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn:1;
+        /** out_remain_under_3b_chn : RO; bitpos: [9]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn:1;
+        /** out_remain_under_4b_chn : RO; bitpos: [10]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn:1;
+        /** out_remain_under_5b_chn : RO; bitpos: [11]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn:1;
+        /** out_remain_under_6b_chn : RO; bitpos: [12]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn:1;
+        /** out_remain_under_7b_chn : RO; bitpos: [13]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn:1;
+        /** out_remain_under_8b_chn : RO; bitpos: [14]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn:1;
+        /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l1_chn:1;
+        /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l1_chn:1;
+        /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l1_chn:5;
+        /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l3_chn:1;
+        /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l3_chn:1;
+        /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_outfifo_status_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Configures the tx fifo of channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_chn:10;
+        /** outfifo_push_chn : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_chn:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dma2d_out_push_chn_reg_t;
+
+/** Type of out_link_conf_chn register
+ *  Configures the tx descriptor operations of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_chn : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn:1;
+        /** outlink_start_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn:1;
+        /** outlink_restart_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn:1;
+        /** outlink_park_chn : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_out_link_conf_chn_reg_t;
+
+/** Type of out_link_addr_chn register
+ *  Configures the tx descriptor address of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_link_addr_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn:18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_chn:2;
+        /** out_state_chn : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_chn:4;
+        /** out_reset_avail_chn : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf1_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Configures the tx peripheral of channel 0
+ */
+typedef union {
+    struct {
+        /** out_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+         *  display-1     2: display-2     3: display-3      7: no choose
+         */
+        uint32_t out_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_peri_sel_chn_reg_t;
+
+/** Type of out_arb_chn register
+ *  Configures the tx arbiter of channel 0
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_chn:4;
+        /** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t out_arb_priority_chn:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_out_arb_chn_reg_t;
+
+/** Type of out_ro_status_chn register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+typedef union {
+    struct {
+        /** outfifo_ro_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Tx FIFO for
+         *  channel 0.
+         */
+        uint32_t outfifo_ro_cnt_chn:6;
+        /** out_ro_wr_state_chn : RO; bitpos: [7:6]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t out_ro_wr_state_chn:2;
+        /** out_ro_rd_state_chn : RO; bitpos: [9:8]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t out_ro_rd_state_chn:2;
+        /** out_pixel_byte_chn : RO; bitpos: [13:10]; default: 0;
+         *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t out_pixel_byte_chn:4;
+        /** out_burst_block_num_chn : RO; bitpos: [17:14]; default: 0;
+         *  the number of macro blocks contained in a burst of data at TX channel
+         */
+        uint32_t out_burst_block_num_chn:4;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dma2d_out_ro_status_chn_reg_t;
+
+/** Type of out_ro_pd_conf_chn register
+ *  Configures the tx reorder memory of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** out_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t out_ro_ram_force_pd_chn:1;
+        /** out_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t out_ro_ram_force_pu_chn:1;
+        /** out_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t out_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_out_ro_pd_conf_chn_reg_t;
+
+/** Type of out_color_convert_chn register
+ *  Configures the tx color convert of channel 0
+ */
+typedef union {
+    struct {
+        /** out_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  YUV444 to YUV422     2: output directly
+         */
+        uint32_t out_color_output_sel_chn:2;
+        /** out_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t out_color_3b_proc_en_chn:1;
+        /** out_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+         *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+         *  disable color space convert
+         */
+        uint32_t out_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_out_color_convert_chn_reg_t;
+
+/** Type of out_scramble_chn register
+ *  Configures the tx scramble of channel 0
+ */
+typedef union {
+    struct {
+        /** out_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t out_scramble_sel_pre_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_scramble_chn_reg_t;
+
+/** Type of out_etm_conf_chn register
+ *  Configures the tx etm of channel 0
+ */
+typedef union {
+    struct {
+        /** out_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t out_etm_en_chn:1;
+        /** out_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t out_etm_loop_en_chn:1;
+        /** out_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t out_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_out_etm_conf_chn_reg_t;
+
+/** Type of out_dscr_port_blk_chn register
+ *  Configures the tx block size in dscr port mode
+ */
+typedef union {
+    struct {
+        /** out_dscr_port_blk_h_chn : R/W; bitpos: [13:0]; default: 18;
+         *  Set the horizontal width of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_h_chn:14;
+        /** out_dscr_port_blk_v_chn : R/W; bitpos: [27:14]; default: 18;
+         *  Set the vertical height of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_v_chn:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_dscr_port_blk_chn_reg_t;
+
+
+/** Group: in */
+/** Type of in_conf0_chn register
+ *  Configures the rx direction of channel 0
+ */
+typedef union {
+    struct {
+        /** in_mem_trans_en_chn : R/W; bitpos: [0]; default: 0;
+         *  enable memory trans of the same channel
+         */
+        uint32_t in_mem_trans_en_chn:1;
+        uint32_t reserved_1:1;
+        /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_chn:1;
+        /** in_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_chn:1;
+        /** in_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn:1;
+        /** in_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn:1;
+        /** in_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 0. 0: 8 bytes      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_chn:3;
+        /** in_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t in_macro_block_size_chn:2;
+        /** in_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t in_dscr_port_en_chn:1;
+        /** in_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** in_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t in_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** in_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_chn:1;
+        /** in_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_chn:1;
+        /** in_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_in_conf0_chn_reg_t;
+
+/** Type of in_int_raw_chn register
+ *  Raw interrupt status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw:1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw:1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_chn_int_raw:1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw:1;
+        /** infifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_chn_int_raw:1;
+        /** infifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_chn_int_raw:1;
+        /** infifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_chn_int_raw:1;
+        /** infifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_chn_int_raw:1;
+        /** infifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l3_chn_int_raw:1;
+        /** infifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l3_chn_int_raw:1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_chn_int_raw:1;
+        /** infifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t infifo_ro_ovf_chn_int_raw:1;
+        /** infifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t infifo_ro_udf_chn_int_raw:1;
+        /** in_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_raw_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena:1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena:1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena:1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena:1;
+        /** infifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_ena:1;
+        /** infifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_ena:1;
+        /** infifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_ena:1;
+        /** infifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_ena:1;
+        /** infifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_ena:1;
+        /** infifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_ena:1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena:1;
+        /** infifo_ro_ovf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_ena:1;
+        /** infifo_ro_udf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_ena:1;
+        /** in_dscr_task_ovf_chn_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_ena_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt status of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st:1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st:1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st:1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st:1;
+        /** infifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_st:1;
+        /** infifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_st:1;
+        /** infifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_st:1;
+        /** infifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_st:1;
+        /** infifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_st:1;
+        /** infifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_st:1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st:1;
+        /** infifo_ro_ovf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_st:1;
+        /** infifo_ro_udf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_st:1;
+        /** in_dscr_task_ovf_chn_int_st : RO; bitpos: [13]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_st_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of RX channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr:1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr:1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr:1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr:1;
+        /** infifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_clr:1;
+        /** infifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_clr:1;
+        /** infifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_clr:1;
+        /** infifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_clr:1;
+        /** infifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_clr:1;
+        /** infifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_clr:1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr:1;
+        /** infifo_ro_ovf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_clr:1;
+        /** infifo_ro_udf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_clr:1;
+        /** in_dscr_task_ovf_chn_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_clr_chn_reg_t;
+
+/** Type of infifo_status_chn register
+ *  Represents the status of the rx fifo of channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_chn:1;
+        /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_chn:1;
+        /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** in_remain_under_1b_chn : RO; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn:1;
+        /** in_remain_under_2b_chn : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn:1;
+        /** in_remain_under_3b_chn : RO; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn:1;
+        /** in_remain_under_4b_chn : RO; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn:1;
+        /** in_remain_under_5b_chn : RO; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn:1;
+        /** in_remain_under_6b_chn : RO; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn:1;
+        /** in_remain_under_7b_chn : RO; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn:1;
+        /** in_remain_under_8b_chn : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn:1;
+        /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l1_chn:1;
+        /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l1_chn:1;
+        /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l1_chn:5;
+        /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l3_chn:1;
+        /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l3_chn:1;
+        /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_infifo_status_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Configures the rx fifo of channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_chn:11;
+        /** infifo_pop_chn : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_chn:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dma2d_in_pop_chn_reg_t;
+
+/** Type of in_link_conf_chn register
+ *  Configures the rx descriptor operations of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1;
+         *  Configure the value of the owner field written back to the inlink descriptor.
+         *  1: Write back 1. 0: Write back 0.
+         */
+        uint32_t inlink_auto_ret_chn:1;
+        /** inlink_stop_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn:1;
+        /** inlink_start_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn:1;
+        /** inlink_restart_chn : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn:1;
+        /** inlink_park_chn : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_in_link_conf_chn_reg_t;
+
+/** Type of in_link_addr_chn register
+ *  Configures the rx descriptor address of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_link_addr_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Represents the working status of the rx descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn:18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn:2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn:3;
+        /** in_reset_avail_chn : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf1_chn_reg_t;
+
+/** Type of in_peri_sel_chn register
+ *  Configures the rx peripheral of channel 0
+ */
+typedef union {
+    struct {
+        /** in_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+         *  display-1     2: display-2        7: no choose
+         */
+        uint32_t in_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_in_peri_sel_chn_reg_t;
+
+/** Type of in_arb_chn register
+ *  Configures the rx arbiter of channel 0
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_chn : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_chn:4;
+        /** in_arb_priority_chn : R/W; bitpos: [4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t in_arb_priority_chn:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} dma2d_in_arb_chn_reg_t;
+
+/** Type of in_ro_status_chn register
+ *  Represents the status of the rx reorder module of channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_ro_cnt_chn : RO; bitpos: [4:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Rx FIFO for
+         *  channel 0.
+         */
+        uint32_t infifo_ro_cnt_chn:5;
+        /** in_ro_wr_state_chn : RO; bitpos: [6:5]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t in_ro_wr_state_chn:2;
+        /** in_ro_rd_state_chn : RO; bitpos: [8:7]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t in_ro_rd_state_chn:2;
+        /** in_pixel_byte_chn : RO; bitpos: [12:9]; default: 0;
+         *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t in_pixel_byte_chn:4;
+        /** in_burst_block_num_chn : RO; bitpos: [16:13]; default: 0;
+         *  the number of macro blocks contained in a burst of data at RX channel
+         */
+        uint32_t in_burst_block_num_chn:4;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_ro_status_chn_reg_t;
+
+/** Type of in_ro_pd_conf_chn register
+ *  Configures the rx reorder memory of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** in_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t in_ro_ram_force_pd_chn:1;
+        /** in_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t in_ro_ram_force_pu_chn:1;
+        /** in_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t in_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_in_ro_pd_conf_chn_reg_t;
+
+/** Type of in_color_convert_chn register
+ *  Configures the tx color convert of channel 0
+ */
+typedef union {
+    struct {
+        /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  output directly
+         */
+        uint32_t in_color_output_sel_chn:2;
+        /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t in_color_3b_proc_en_chn:1;
+        /** in_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+         *  1: YUV422      2: YUV444/420      7: disable color space convert
+         */
+        uint32_t in_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_color_convert_chn_reg_t;
+
+/** Type of in_scramble_chn register
+ *  Configures the rx scramble of channel 0
+ */
+typedef union {
+    struct {
+        /** in_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_pre_chn:3;
+        /** in_scramble_sel_post_chn : R/W; bitpos: [5:3]; default: 0;
+         *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+         *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_post_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_scramble_chn_reg_t;
+
+/** Type of in_etm_conf_chn register
+ *  Configures the rx etm of channel 0
+ */
+typedef union {
+    struct {
+        /** in_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t in_etm_en_chn:1;
+        /** in_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t in_etm_loop_en_chn:1;
+        /** in_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t in_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_in_etm_conf_chn_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of axi_err register
+ *  Represents the status of th axi bus
+ */
+typedef union {
+    struct {
+        /** rid_err_cnt : RO; bitpos: [3:0]; default: 0;
+         *  AXI read id err cnt
+         */
+        uint32_t rid_err_cnt:4;
+        /** rresp_err_cnt : RO; bitpos: [7:4]; default: 0;
+         *  AXI read resp err cnt
+         */
+        uint32_t rresp_err_cnt:4;
+        /** wresp_err_cnt : RO; bitpos: [11:8]; default: 0;
+         *  AXI write resp err cnt
+         */
+        uint32_t wresp_err_cnt:4;
+        /** rd_fifo_cnt : RO; bitpos: [14:12]; default: 0;
+         *  AXI read cmd fifo remain cmd count
+         */
+        uint32_t rd_fifo_cnt:3;
+        /** rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0;
+         *  AXI read backup cmd fifo remain cmd count
+         */
+        uint32_t rd_bak_fifo_cnt:4;
+        /** wr_fifo_cnt : RO; bitpos: [21:19]; default: 0;
+         *  AXI write cmd fifo remain cmd count
+         */
+        uint32_t wr_fifo_cnt:3;
+        /** wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0;
+         *  AXI write backup cmd fifo remain cmd count
+         */
+        uint32_t wr_bak_fifo_cnt:4;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} dma2d_axi_err_reg_t;
+
+/** Type of date register
+ *  register version.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36716816;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} dma2d_date_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of rst_conf register
+ *  Configures the reset of axi
+ */
+typedef union {
+    struct {
+        /** axim_rd_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+         */
+        uint32_t axim_rd_rst:1;
+        /** axim_wr_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+         */
+        uint32_t axim_wr_rst:1;
+        /** clk_en : R/W; bitpos: [2]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_rst_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944 (0x30100000);
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103 (0x8FFFFFFF);
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944 (0x30100000);
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103 (0x8FFFFFFF);
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_end_addr_reg_t;
+
+/** Type of out_arb_config register
+ *  Configures the tx arbiter
+ */
+typedef union {
+    struct {
+        /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t out_arb_timeout_num:16;
+        /** out_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t out_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_out_arb_config_reg_t;
+
+/** Type of in_arb_config register
+ *  Configures the rx arbiter
+ */
+typedef union {
+    struct {
+        /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t in_arb_timeout_num:16;
+        /** in_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t in_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_arb_config_reg_t;
+
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dma2d_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_low_reg_t;
+
+
+/** Type of in/out_color_param_h/m/l_chn register
+ *  Configures the rx/tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        struct {
+            /** a: R/W; bitpos: [9:0]; default: h:298, m:298, l:298
+             * Set the first parameter of the most/medium/least significant byte of pending 3 bytes
+             */
+            uint32_t a                             :    10;
+            /** b: R/W; bitpos: [20:10]; default: h:0, in_m:1948, l:516
+             * Set the second parameter of the most/medium/least significant byte of pending 3 bytes
+             */
+            uint32_t b                             :    11;
+            uint32_t reserved21                    :    11;
+        };
+        struct {
+            /** c: R/W; bitpos: [41:32]; default: h:409, m:816, l:0
+             * Set the third parameter of the most/medium/least significant byte of pending 3 bytes
+             */
+            uint32_t c                             :    10;
+            /** d: R/W; bitpos: [59:42]; default: h:205238, m:34707, l:191308
+             * Set the fourth parameter of the most/medium/least significant byte of pending 3 bytes
+             */
+            uint32_t d                             :    18;
+            uint32_t reserved60                    :    4;
+        };
+    };
+    uint32_t val[2];
+} dma2d_color_param_reg_t;
+
+typedef struct {
+    volatile dma2d_color_param_reg_t param_h;
+    volatile dma2d_color_param_reg_t param_m;
+    volatile dma2d_color_param_reg_t param_l;
+} dma2d_color_param_group_chn_reg_t;
+
+typedef struct {
+    volatile dma2d_out_conf0_chn_reg_t out_conf0;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status;
+    volatile dma2d_out_push_chn_reg_t out_push;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr;
+    volatile dma2d_out_state_chn_reg_t out_state;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel;
+    volatile dma2d_out_arb_chn_reg_t out_arb;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status;
+    volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf;  /* only exist on channel0 */
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble;
+    volatile dma2d_color_param_group_chn_reg_t out_color_param_group;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk;
+    uint32_t reserved_out[36];
+} dma2d_out_chn_reg_t;
+
+typedef struct {
+    volatile dma2d_in_conf0_chn_reg_t in_conf0;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status;
+    volatile dma2d_in_pop_chn_reg_t in_pop;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr;
+    volatile dma2d_in_state_chn_reg_t in_state;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
+    volatile dma2d_in_arb_chn_reg_t in_arb;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
+    volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf;
+    volatile dma2d_in_color_convert_chn_reg_t in_color_convert;
+    volatile dma2d_in_scramble_chn_reg_t in_scramble;
+    volatile dma2d_color_param_group_chn_reg_t in_color_param_group;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
+    uint32_t reserved_570[36];
+} dma2d_in_ch0_reg_t;
+
+typedef struct {
+    volatile dma2d_in_conf0_chn_reg_t in_conf0;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status;
+    volatile dma2d_in_pop_chn_reg_t in_pop;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr;
+    volatile dma2d_in_state_chn_reg_t in_state;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
+    volatile dma2d_in_arb_chn_reg_t in_arb;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
+    uint32_t reserved_64c[45];
+} dma2d_in_ch1_reg_t;
+
+typedef struct dma2d_dev_t {
+    volatile dma2d_out_chn_reg_t out_channel[3];
+    uint32_t reserved_300[128];
+    volatile dma2d_in_ch0_reg_t in_channel0;
+    volatile dma2d_in_ch1_reg_t in_channel1;
+    uint32_t reserved_700[192];
+    volatile dma2d_axi_err_reg_t axi_err;
+    volatile dma2d_rst_conf_reg_t rst_conf;
+    volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile dma2d_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile dma2d_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile dma2d_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile dma2d_out_arb_config_reg_t out_arb_config;
+    volatile dma2d_in_arb_config_reg_t in_arb_config;
+    volatile dma2d_rdn_result_reg_t rdn_result;
+    volatile dma2d_rdn_eco_high_reg_t rdn_eco_high;
+    volatile dma2d_rdn_eco_low_reg_t rdn_eco_low;
+    volatile dma2d_date_reg_t date;
+} dma2d_dev_t;
+
+extern dma2d_dev_t DMA2D;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dma2d_dev_t) == 0xa30, "Invalid size of dma2d_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dma_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/dma_pms_eco5_reg.h
new file mode 100644
index 0000000000..9bb8b75dbb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dma_pms_eco5_reg.h
@@ -0,0 +1,1576 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_DMA_DATE_REG register
+ *  NA
+ */
+#define TEE_DMA_DATE_REG (DR_REG_TEE_DMA_BASE + 0x0)
+/** TEE_DMA_TEE_DATE : R/W; bitpos: [31:0]; default: 539165460;
+ *  NA
+ */
+#define TEE_DMA_TEE_DATE    0xFFFFFFFFU
+#define TEE_DMA_TEE_DATE_M  (TEE_DMA_TEE_DATE_V << TEE_DMA_TEE_DATE_S)
+#define TEE_DMA_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_DMA_TEE_DATE_S  0
+
+/** TEE_DMA_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_DMA_CLK_EN_REG (DR_REG_TEE_DMA_BASE + 0x4)
+/** TEE_DMA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_DMA_CLK_EN    (BIT(0))
+#define TEE_DMA_CLK_EN_M  (TEE_DMA_CLK_EN_V << TEE_DMA_CLK_EN_S)
+#define TEE_DMA_CLK_EN_V  0x00000001U
+#define TEE_DMA_CLK_EN_S  0
+
+/** TEE_DMA_REGION0_LOW_REG register
+ *  Region0 address low register.
+ */
+#define TEE_DMA_REGION0_LOW_REG (DR_REG_TEE_DMA_BASE + 0x8)
+/** TEE_DMA_REGION0_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region0 address low.
+ */
+#define TEE_DMA_REGION0_LOW    0x000FFFFFU
+#define TEE_DMA_REGION0_LOW_M  (TEE_DMA_REGION0_LOW_V << TEE_DMA_REGION0_LOW_S)
+#define TEE_DMA_REGION0_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION0_LOW_S  12
+
+/** TEE_DMA_REGION0_HIGH_REG register
+ *  Region0 address high register.
+ */
+#define TEE_DMA_REGION0_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xc)
+/** TEE_DMA_REGION0_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region0 address high.
+ */
+#define TEE_DMA_REGION0_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION0_HIGH_M  (TEE_DMA_REGION0_HIGH_V << TEE_DMA_REGION0_HIGH_S)
+#define TEE_DMA_REGION0_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION0_HIGH_S  12
+
+/** TEE_DMA_REGION1_LOW_REG register
+ *  Region1 address low register.
+ */
+#define TEE_DMA_REGION1_LOW_REG (DR_REG_TEE_DMA_BASE + 0x10)
+/** TEE_DMA_REGION1_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region1 address low.
+ */
+#define TEE_DMA_REGION1_LOW    0x000FFFFFU
+#define TEE_DMA_REGION1_LOW_M  (TEE_DMA_REGION1_LOW_V << TEE_DMA_REGION1_LOW_S)
+#define TEE_DMA_REGION1_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION1_LOW_S  12
+
+/** TEE_DMA_REGION1_HIGH_REG register
+ *  Region1 address high register.
+ */
+#define TEE_DMA_REGION1_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x14)
+/** TEE_DMA_REGION1_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region1 address high.
+ */
+#define TEE_DMA_REGION1_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION1_HIGH_M  (TEE_DMA_REGION1_HIGH_V << TEE_DMA_REGION1_HIGH_S)
+#define TEE_DMA_REGION1_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION1_HIGH_S  12
+
+/** TEE_DMA_REGION2_LOW_REG register
+ *  Region2 address low register.
+ */
+#define TEE_DMA_REGION2_LOW_REG (DR_REG_TEE_DMA_BASE + 0x18)
+/** TEE_DMA_REGION2_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region2 address low.
+ */
+#define TEE_DMA_REGION2_LOW    0x000FFFFFU
+#define TEE_DMA_REGION2_LOW_M  (TEE_DMA_REGION2_LOW_V << TEE_DMA_REGION2_LOW_S)
+#define TEE_DMA_REGION2_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION2_LOW_S  12
+
+/** TEE_DMA_REGION2_HIGH_REG register
+ *  Region2 address high register.
+ */
+#define TEE_DMA_REGION2_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x1c)
+/** TEE_DMA_REGION2_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region2 address high.
+ */
+#define TEE_DMA_REGION2_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION2_HIGH_M  (TEE_DMA_REGION2_HIGH_V << TEE_DMA_REGION2_HIGH_S)
+#define TEE_DMA_REGION2_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION2_HIGH_S  12
+
+/** TEE_DMA_REGION3_LOW_REG register
+ *  Region3 address low register.
+ */
+#define TEE_DMA_REGION3_LOW_REG (DR_REG_TEE_DMA_BASE + 0x20)
+/** TEE_DMA_REGION3_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region3 address low.
+ */
+#define TEE_DMA_REGION3_LOW    0x000FFFFFU
+#define TEE_DMA_REGION3_LOW_M  (TEE_DMA_REGION3_LOW_V << TEE_DMA_REGION3_LOW_S)
+#define TEE_DMA_REGION3_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION3_LOW_S  12
+
+/** TEE_DMA_REGION3_HIGH_REG register
+ *  Region3 address high register.
+ */
+#define TEE_DMA_REGION3_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x24)
+/** TEE_DMA_REGION3_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region3 address high.
+ */
+#define TEE_DMA_REGION3_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION3_HIGH_M  (TEE_DMA_REGION3_HIGH_V << TEE_DMA_REGION3_HIGH_S)
+#define TEE_DMA_REGION3_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION3_HIGH_S  12
+
+/** TEE_DMA_REGION4_LOW_REG register
+ *  Region4 address low register.
+ */
+#define TEE_DMA_REGION4_LOW_REG (DR_REG_TEE_DMA_BASE + 0x28)
+/** TEE_DMA_REGION4_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region4 address low.
+ */
+#define TEE_DMA_REGION4_LOW    0x000FFFFFU
+#define TEE_DMA_REGION4_LOW_M  (TEE_DMA_REGION4_LOW_V << TEE_DMA_REGION4_LOW_S)
+#define TEE_DMA_REGION4_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION4_LOW_S  12
+
+/** TEE_DMA_REGION4_HIGH_REG register
+ *  Region4 address high register.
+ */
+#define TEE_DMA_REGION4_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x2c)
+/** TEE_DMA_REGION4_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region4 address high.
+ */
+#define TEE_DMA_REGION4_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION4_HIGH_M  (TEE_DMA_REGION4_HIGH_V << TEE_DMA_REGION4_HIGH_S)
+#define TEE_DMA_REGION4_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION4_HIGH_S  12
+
+/** TEE_DMA_REGION5_LOW_REG register
+ *  Region5 address low register.
+ */
+#define TEE_DMA_REGION5_LOW_REG (DR_REG_TEE_DMA_BASE + 0x30)
+/** TEE_DMA_REGION5_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region5 address low.
+ */
+#define TEE_DMA_REGION5_LOW    0x000FFFFFU
+#define TEE_DMA_REGION5_LOW_M  (TEE_DMA_REGION5_LOW_V << TEE_DMA_REGION5_LOW_S)
+#define TEE_DMA_REGION5_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION5_LOW_S  12
+
+/** TEE_DMA_REGION5_HIGH_REG register
+ *  Region5 address high register.
+ */
+#define TEE_DMA_REGION5_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x34)
+/** TEE_DMA_REGION5_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region5 address high.
+ */
+#define TEE_DMA_REGION5_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION5_HIGH_M  (TEE_DMA_REGION5_HIGH_V << TEE_DMA_REGION5_HIGH_S)
+#define TEE_DMA_REGION5_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION5_HIGH_S  12
+
+/** TEE_DMA_REGION6_LOW_REG register
+ *  Region6 address low register.
+ */
+#define TEE_DMA_REGION6_LOW_REG (DR_REG_TEE_DMA_BASE + 0x38)
+/** TEE_DMA_REGION6_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region6 address low.
+ */
+#define TEE_DMA_REGION6_LOW    0x000FFFFFU
+#define TEE_DMA_REGION6_LOW_M  (TEE_DMA_REGION6_LOW_V << TEE_DMA_REGION6_LOW_S)
+#define TEE_DMA_REGION6_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION6_LOW_S  12
+
+/** TEE_DMA_REGION6_HIGH_REG register
+ *  Region6 address high register.
+ */
+#define TEE_DMA_REGION6_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x3c)
+/** TEE_DMA_REGION6_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region6 address high.
+ */
+#define TEE_DMA_REGION6_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION6_HIGH_M  (TEE_DMA_REGION6_HIGH_V << TEE_DMA_REGION6_HIGH_S)
+#define TEE_DMA_REGION6_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION6_HIGH_S  12
+
+/** TEE_DMA_REGION7_LOW_REG register
+ *  Region7 address low register.
+ */
+#define TEE_DMA_REGION7_LOW_REG (DR_REG_TEE_DMA_BASE + 0x40)
+/** TEE_DMA_REGION7_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region7 address low.
+ */
+#define TEE_DMA_REGION7_LOW    0x000FFFFFU
+#define TEE_DMA_REGION7_LOW_M  (TEE_DMA_REGION7_LOW_V << TEE_DMA_REGION7_LOW_S)
+#define TEE_DMA_REGION7_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION7_LOW_S  12
+
+/** TEE_DMA_REGION7_HIGH_REG register
+ *  Region7 address high register.
+ */
+#define TEE_DMA_REGION7_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x44)
+/** TEE_DMA_REGION7_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region7 address high.
+ */
+#define TEE_DMA_REGION7_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION7_HIGH_M  (TEE_DMA_REGION7_HIGH_V << TEE_DMA_REGION7_HIGH_S)
+#define TEE_DMA_REGION7_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION7_HIGH_S  12
+
+/** TEE_DMA_REGION8_LOW_REG register
+ *  Region8 address low register.
+ */
+#define TEE_DMA_REGION8_LOW_REG (DR_REG_TEE_DMA_BASE + 0x48)
+/** TEE_DMA_REGION8_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region8 address low.
+ */
+#define TEE_DMA_REGION8_LOW    0x000FFFFFU
+#define TEE_DMA_REGION8_LOW_M  (TEE_DMA_REGION8_LOW_V << TEE_DMA_REGION8_LOW_S)
+#define TEE_DMA_REGION8_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION8_LOW_S  12
+
+/** TEE_DMA_REGION8_HIGH_REG register
+ *  Region8 address high register.
+ */
+#define TEE_DMA_REGION8_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x4c)
+/** TEE_DMA_REGION8_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region8 address high.
+ */
+#define TEE_DMA_REGION8_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION8_HIGH_M  (TEE_DMA_REGION8_HIGH_V << TEE_DMA_REGION8_HIGH_S)
+#define TEE_DMA_REGION8_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION8_HIGH_S  12
+
+/** TEE_DMA_REGION9_LOW_REG register
+ *  Region9 address low register.
+ */
+#define TEE_DMA_REGION9_LOW_REG (DR_REG_TEE_DMA_BASE + 0x50)
+/** TEE_DMA_REGION9_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region9 address low.
+ */
+#define TEE_DMA_REGION9_LOW    0x000FFFFFU
+#define TEE_DMA_REGION9_LOW_M  (TEE_DMA_REGION9_LOW_V << TEE_DMA_REGION9_LOW_S)
+#define TEE_DMA_REGION9_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION9_LOW_S  12
+
+/** TEE_DMA_REGION9_HIGH_REG register
+ *  Region9 address high register.
+ */
+#define TEE_DMA_REGION9_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x54)
+/** TEE_DMA_REGION9_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region9 address high.
+ */
+#define TEE_DMA_REGION9_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION9_HIGH_M  (TEE_DMA_REGION9_HIGH_V << TEE_DMA_REGION9_HIGH_S)
+#define TEE_DMA_REGION9_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION9_HIGH_S  12
+
+/** TEE_DMA_REGION10_LOW_REG register
+ *  Region10 address low register.
+ */
+#define TEE_DMA_REGION10_LOW_REG (DR_REG_TEE_DMA_BASE + 0x58)
+/** TEE_DMA_REGION10_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region10 address low.
+ */
+#define TEE_DMA_REGION10_LOW    0x000FFFFFU
+#define TEE_DMA_REGION10_LOW_M  (TEE_DMA_REGION10_LOW_V << TEE_DMA_REGION10_LOW_S)
+#define TEE_DMA_REGION10_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION10_LOW_S  12
+
+/** TEE_DMA_REGION10_HIGH_REG register
+ *  Region10 address high register.
+ */
+#define TEE_DMA_REGION10_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x5c)
+/** TEE_DMA_REGION10_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region10 address high.
+ */
+#define TEE_DMA_REGION10_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION10_HIGH_M  (TEE_DMA_REGION10_HIGH_V << TEE_DMA_REGION10_HIGH_S)
+#define TEE_DMA_REGION10_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION10_HIGH_S  12
+
+/** TEE_DMA_REGION11_LOW_REG register
+ *  Region11 address low register.
+ */
+#define TEE_DMA_REGION11_LOW_REG (DR_REG_TEE_DMA_BASE + 0x60)
+/** TEE_DMA_REGION11_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region11 address low.
+ */
+#define TEE_DMA_REGION11_LOW    0x000FFFFFU
+#define TEE_DMA_REGION11_LOW_M  (TEE_DMA_REGION11_LOW_V << TEE_DMA_REGION11_LOW_S)
+#define TEE_DMA_REGION11_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION11_LOW_S  12
+
+/** TEE_DMA_REGION11_HIGH_REG register
+ *  Region11 address high register.
+ */
+#define TEE_DMA_REGION11_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x64)
+/** TEE_DMA_REGION11_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region11 address high.
+ */
+#define TEE_DMA_REGION11_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION11_HIGH_M  (TEE_DMA_REGION11_HIGH_V << TEE_DMA_REGION11_HIGH_S)
+#define TEE_DMA_REGION11_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION11_HIGH_S  12
+
+/** TEE_DMA_REGION12_LOW_REG register
+ *  Region12 address low register.
+ */
+#define TEE_DMA_REGION12_LOW_REG (DR_REG_TEE_DMA_BASE + 0x68)
+/** TEE_DMA_REGION12_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region12 address low.
+ */
+#define TEE_DMA_REGION12_LOW    0x000FFFFFU
+#define TEE_DMA_REGION12_LOW_M  (TEE_DMA_REGION12_LOW_V << TEE_DMA_REGION12_LOW_S)
+#define TEE_DMA_REGION12_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION12_LOW_S  12
+
+/** TEE_DMA_REGION12_HIGH_REG register
+ *  Region12 address high register.
+ */
+#define TEE_DMA_REGION12_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x6c)
+/** TEE_DMA_REGION12_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region12 address high.
+ */
+#define TEE_DMA_REGION12_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION12_HIGH_M  (TEE_DMA_REGION12_HIGH_V << TEE_DMA_REGION12_HIGH_S)
+#define TEE_DMA_REGION12_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION12_HIGH_S  12
+
+/** TEE_DMA_REGION13_LOW_REG register
+ *  Region13 address low register.
+ */
+#define TEE_DMA_REGION13_LOW_REG (DR_REG_TEE_DMA_BASE + 0x70)
+/** TEE_DMA_REGION13_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region13 address low.
+ */
+#define TEE_DMA_REGION13_LOW    0x000FFFFFU
+#define TEE_DMA_REGION13_LOW_M  (TEE_DMA_REGION13_LOW_V << TEE_DMA_REGION13_LOW_S)
+#define TEE_DMA_REGION13_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION13_LOW_S  12
+
+/** TEE_DMA_REGION13_HIGH_REG register
+ *  Region13 address high register.
+ */
+#define TEE_DMA_REGION13_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x74)
+/** TEE_DMA_REGION13_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region13 address high.
+ */
+#define TEE_DMA_REGION13_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION13_HIGH_M  (TEE_DMA_REGION13_HIGH_V << TEE_DMA_REGION13_HIGH_S)
+#define TEE_DMA_REGION13_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION13_HIGH_S  12
+
+/** TEE_DMA_REGION14_LOW_REG register
+ *  Region14 address low register.
+ */
+#define TEE_DMA_REGION14_LOW_REG (DR_REG_TEE_DMA_BASE + 0x78)
+/** TEE_DMA_REGION14_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region14 address low.
+ */
+#define TEE_DMA_REGION14_LOW    0x000FFFFFU
+#define TEE_DMA_REGION14_LOW_M  (TEE_DMA_REGION14_LOW_V << TEE_DMA_REGION14_LOW_S)
+#define TEE_DMA_REGION14_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION14_LOW_S  12
+
+/** TEE_DMA_REGION14_HIGH_REG register
+ *  Region14 address high register.
+ */
+#define TEE_DMA_REGION14_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x7c)
+/** TEE_DMA_REGION14_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region14 address high.
+ */
+#define TEE_DMA_REGION14_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION14_HIGH_M  (TEE_DMA_REGION14_HIGH_V << TEE_DMA_REGION14_HIGH_S)
+#define TEE_DMA_REGION14_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION14_HIGH_S  12
+
+/** TEE_DMA_REGION15_LOW_REG register
+ *  Region15 address low register.
+ */
+#define TEE_DMA_REGION15_LOW_REG (DR_REG_TEE_DMA_BASE + 0x80)
+/** TEE_DMA_REGION15_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region15 address low.
+ */
+#define TEE_DMA_REGION15_LOW    0x000FFFFFU
+#define TEE_DMA_REGION15_LOW_M  (TEE_DMA_REGION15_LOW_V << TEE_DMA_REGION15_LOW_S)
+#define TEE_DMA_REGION15_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION15_LOW_S  12
+
+/** TEE_DMA_REGION15_HIGH_REG register
+ *  Region15 address high register.
+ */
+#define TEE_DMA_REGION15_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x84)
+/** TEE_DMA_REGION15_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region15 address high.
+ */
+#define TEE_DMA_REGION15_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION15_HIGH_M  (TEE_DMA_REGION15_HIGH_V << TEE_DMA_REGION15_HIGH_S)
+#define TEE_DMA_REGION15_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION15_HIGH_S  12
+
+/** TEE_DMA_REGION16_LOW_REG register
+ *  Region16 address low register.
+ */
+#define TEE_DMA_REGION16_LOW_REG (DR_REG_TEE_DMA_BASE + 0x88)
+/** TEE_DMA_REGION16_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region16 address low.
+ */
+#define TEE_DMA_REGION16_LOW    0x000FFFFFU
+#define TEE_DMA_REGION16_LOW_M  (TEE_DMA_REGION16_LOW_V << TEE_DMA_REGION16_LOW_S)
+#define TEE_DMA_REGION16_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION16_LOW_S  12
+
+/** TEE_DMA_REGION16_HIGH_REG register
+ *  Region16 address high register.
+ */
+#define TEE_DMA_REGION16_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x8c)
+/** TEE_DMA_REGION16_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region16 address high.
+ */
+#define TEE_DMA_REGION16_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION16_HIGH_M  (TEE_DMA_REGION16_HIGH_V << TEE_DMA_REGION16_HIGH_S)
+#define TEE_DMA_REGION16_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION16_HIGH_S  12
+
+/** TEE_DMA_REGION17_LOW_REG register
+ *  Region17 address low register.
+ */
+#define TEE_DMA_REGION17_LOW_REG (DR_REG_TEE_DMA_BASE + 0x90)
+/** TEE_DMA_REGION17_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region17 address low.
+ */
+#define TEE_DMA_REGION17_LOW    0x000FFFFFU
+#define TEE_DMA_REGION17_LOW_M  (TEE_DMA_REGION17_LOW_V << TEE_DMA_REGION17_LOW_S)
+#define TEE_DMA_REGION17_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION17_LOW_S  12
+
+/** TEE_DMA_REGION17_HIGH_REG register
+ *  Region17 address high register.
+ */
+#define TEE_DMA_REGION17_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x94)
+/** TEE_DMA_REGION17_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region17 address high.
+ */
+#define TEE_DMA_REGION17_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION17_HIGH_M  (TEE_DMA_REGION17_HIGH_V << TEE_DMA_REGION17_HIGH_S)
+#define TEE_DMA_REGION17_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION17_HIGH_S  12
+
+/** TEE_DMA_REGION18_LOW_REG register
+ *  Region18 address low register.
+ */
+#define TEE_DMA_REGION18_LOW_REG (DR_REG_TEE_DMA_BASE + 0x98)
+/** TEE_DMA_REGION18_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region18 address low.
+ */
+#define TEE_DMA_REGION18_LOW    0x000FFFFFU
+#define TEE_DMA_REGION18_LOW_M  (TEE_DMA_REGION18_LOW_V << TEE_DMA_REGION18_LOW_S)
+#define TEE_DMA_REGION18_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION18_LOW_S  12
+
+/** TEE_DMA_REGION18_HIGH_REG register
+ *  Region18 address high register.
+ */
+#define TEE_DMA_REGION18_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x9c)
+/** TEE_DMA_REGION18_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region18 address high.
+ */
+#define TEE_DMA_REGION18_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION18_HIGH_M  (TEE_DMA_REGION18_HIGH_V << TEE_DMA_REGION18_HIGH_S)
+#define TEE_DMA_REGION18_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION18_HIGH_S  12
+
+/** TEE_DMA_REGION19_LOW_REG register
+ *  Region19 address low register.
+ */
+#define TEE_DMA_REGION19_LOW_REG (DR_REG_TEE_DMA_BASE + 0xa0)
+/** TEE_DMA_REGION19_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region19 address low.
+ */
+#define TEE_DMA_REGION19_LOW    0x000FFFFFU
+#define TEE_DMA_REGION19_LOW_M  (TEE_DMA_REGION19_LOW_V << TEE_DMA_REGION19_LOW_S)
+#define TEE_DMA_REGION19_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION19_LOW_S  12
+
+/** TEE_DMA_REGION19_HIGH_REG register
+ *  Region19 address high register.
+ */
+#define TEE_DMA_REGION19_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xa4)
+/** TEE_DMA_REGION19_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region19 address high.
+ */
+#define TEE_DMA_REGION19_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION19_HIGH_M  (TEE_DMA_REGION19_HIGH_V << TEE_DMA_REGION19_HIGH_S)
+#define TEE_DMA_REGION19_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION19_HIGH_S  12
+
+/** TEE_DMA_REGION20_LOW_REG register
+ *  Region20 address low register.
+ */
+#define TEE_DMA_REGION20_LOW_REG (DR_REG_TEE_DMA_BASE + 0xa8)
+/** TEE_DMA_REGION20_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region20 address low.
+ */
+#define TEE_DMA_REGION20_LOW    0x000FFFFFU
+#define TEE_DMA_REGION20_LOW_M  (TEE_DMA_REGION20_LOW_V << TEE_DMA_REGION20_LOW_S)
+#define TEE_DMA_REGION20_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION20_LOW_S  12
+
+/** TEE_DMA_REGION20_HIGH_REG register
+ *  Region20 address high register.
+ */
+#define TEE_DMA_REGION20_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xac)
+/** TEE_DMA_REGION20_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region20 address high.
+ */
+#define TEE_DMA_REGION20_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION20_HIGH_M  (TEE_DMA_REGION20_HIGH_V << TEE_DMA_REGION20_HIGH_S)
+#define TEE_DMA_REGION20_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION20_HIGH_S  12
+
+/** TEE_DMA_REGION21_LOW_REG register
+ *  Region21 address low register.
+ */
+#define TEE_DMA_REGION21_LOW_REG (DR_REG_TEE_DMA_BASE + 0xb0)
+/** TEE_DMA_REGION21_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region21 address low.
+ */
+#define TEE_DMA_REGION21_LOW    0x000FFFFFU
+#define TEE_DMA_REGION21_LOW_M  (TEE_DMA_REGION21_LOW_V << TEE_DMA_REGION21_LOW_S)
+#define TEE_DMA_REGION21_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION21_LOW_S  12
+
+/** TEE_DMA_REGION21_HIGH_REG register
+ *  Region21 address high register.
+ */
+#define TEE_DMA_REGION21_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xb4)
+/** TEE_DMA_REGION21_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region21 address high.
+ */
+#define TEE_DMA_REGION21_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION21_HIGH_M  (TEE_DMA_REGION21_HIGH_V << TEE_DMA_REGION21_HIGH_S)
+#define TEE_DMA_REGION21_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION21_HIGH_S  12
+
+/** TEE_DMA_REGION22_LOW_REG register
+ *  Region22 address low register.
+ */
+#define TEE_DMA_REGION22_LOW_REG (DR_REG_TEE_DMA_BASE + 0xb8)
+/** TEE_DMA_REGION22_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region22 address low.
+ */
+#define TEE_DMA_REGION22_LOW    0x000FFFFFU
+#define TEE_DMA_REGION22_LOW_M  (TEE_DMA_REGION22_LOW_V << TEE_DMA_REGION22_LOW_S)
+#define TEE_DMA_REGION22_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION22_LOW_S  12
+
+/** TEE_DMA_REGION22_HIGH_REG register
+ *  Region22 address high register.
+ */
+#define TEE_DMA_REGION22_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xbc)
+/** TEE_DMA_REGION22_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region22 address high.
+ */
+#define TEE_DMA_REGION22_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION22_HIGH_M  (TEE_DMA_REGION22_HIGH_V << TEE_DMA_REGION22_HIGH_S)
+#define TEE_DMA_REGION22_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION22_HIGH_S  12
+
+/** TEE_DMA_REGION23_LOW_REG register
+ *  Region23 address low register.
+ */
+#define TEE_DMA_REGION23_LOW_REG (DR_REG_TEE_DMA_BASE + 0xc0)
+/** TEE_DMA_REGION23_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region23 address low.
+ */
+#define TEE_DMA_REGION23_LOW    0x000FFFFFU
+#define TEE_DMA_REGION23_LOW_M  (TEE_DMA_REGION23_LOW_V << TEE_DMA_REGION23_LOW_S)
+#define TEE_DMA_REGION23_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION23_LOW_S  12
+
+/** TEE_DMA_REGION23_HIGH_REG register
+ *  Region23 address high register.
+ */
+#define TEE_DMA_REGION23_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xc4)
+/** TEE_DMA_REGION23_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region23 address high.
+ */
+#define TEE_DMA_REGION23_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION23_HIGH_M  (TEE_DMA_REGION23_HIGH_V << TEE_DMA_REGION23_HIGH_S)
+#define TEE_DMA_REGION23_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION23_HIGH_S  12
+
+/** TEE_DMA_REGION24_LOW_REG register
+ *  Region24 address low register.
+ */
+#define TEE_DMA_REGION24_LOW_REG (DR_REG_TEE_DMA_BASE + 0xc8)
+/** TEE_DMA_REGION24_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region24 address low.
+ */
+#define TEE_DMA_REGION24_LOW    0x000FFFFFU
+#define TEE_DMA_REGION24_LOW_M  (TEE_DMA_REGION24_LOW_V << TEE_DMA_REGION24_LOW_S)
+#define TEE_DMA_REGION24_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION24_LOW_S  12
+
+/** TEE_DMA_REGION24_HIGH_REG register
+ *  Region24 address high register.
+ */
+#define TEE_DMA_REGION24_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xcc)
+/** TEE_DMA_REGION24_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region24 address high.
+ */
+#define TEE_DMA_REGION24_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION24_HIGH_M  (TEE_DMA_REGION24_HIGH_V << TEE_DMA_REGION24_HIGH_S)
+#define TEE_DMA_REGION24_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION24_HIGH_S  12
+
+/** TEE_DMA_REGION25_LOW_REG register
+ *  Region25 address low register.
+ */
+#define TEE_DMA_REGION25_LOW_REG (DR_REG_TEE_DMA_BASE + 0xd0)
+/** TEE_DMA_REGION25_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region25 address low.
+ */
+#define TEE_DMA_REGION25_LOW    0x000FFFFFU
+#define TEE_DMA_REGION25_LOW_M  (TEE_DMA_REGION25_LOW_V << TEE_DMA_REGION25_LOW_S)
+#define TEE_DMA_REGION25_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION25_LOW_S  12
+
+/** TEE_DMA_REGION25_HIGH_REG register
+ *  Region25 address high register.
+ */
+#define TEE_DMA_REGION25_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xd4)
+/** TEE_DMA_REGION25_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region25 address high.
+ */
+#define TEE_DMA_REGION25_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION25_HIGH_M  (TEE_DMA_REGION25_HIGH_V << TEE_DMA_REGION25_HIGH_S)
+#define TEE_DMA_REGION25_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION25_HIGH_S  12
+
+/** TEE_DMA_REGION26_LOW_REG register
+ *  Region26 address low register.
+ */
+#define TEE_DMA_REGION26_LOW_REG (DR_REG_TEE_DMA_BASE + 0xd8)
+/** TEE_DMA_REGION26_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region26 address low.
+ */
+#define TEE_DMA_REGION26_LOW    0x000FFFFFU
+#define TEE_DMA_REGION26_LOW_M  (TEE_DMA_REGION26_LOW_V << TEE_DMA_REGION26_LOW_S)
+#define TEE_DMA_REGION26_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION26_LOW_S  12
+
+/** TEE_DMA_REGION26_HIGH_REG register
+ *  Region26 address high register.
+ */
+#define TEE_DMA_REGION26_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xdc)
+/** TEE_DMA_REGION26_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region26 address high.
+ */
+#define TEE_DMA_REGION26_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION26_HIGH_M  (TEE_DMA_REGION26_HIGH_V << TEE_DMA_REGION26_HIGH_S)
+#define TEE_DMA_REGION26_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION26_HIGH_S  12
+
+/** TEE_DMA_REGION27_LOW_REG register
+ *  Region27 address low register.
+ */
+#define TEE_DMA_REGION27_LOW_REG (DR_REG_TEE_DMA_BASE + 0xe0)
+/** TEE_DMA_REGION27_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region27 address low.
+ */
+#define TEE_DMA_REGION27_LOW    0x000FFFFFU
+#define TEE_DMA_REGION27_LOW_M  (TEE_DMA_REGION27_LOW_V << TEE_DMA_REGION27_LOW_S)
+#define TEE_DMA_REGION27_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION27_LOW_S  12
+
+/** TEE_DMA_REGION27_HIGH_REG register
+ *  Region27 address high register.
+ */
+#define TEE_DMA_REGION27_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xe4)
+/** TEE_DMA_REGION27_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region27 address high.
+ */
+#define TEE_DMA_REGION27_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION27_HIGH_M  (TEE_DMA_REGION27_HIGH_V << TEE_DMA_REGION27_HIGH_S)
+#define TEE_DMA_REGION27_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION27_HIGH_S  12
+
+/** TEE_DMA_REGION28_LOW_REG register
+ *  Region28 address low register.
+ */
+#define TEE_DMA_REGION28_LOW_REG (DR_REG_TEE_DMA_BASE + 0xe8)
+/** TEE_DMA_REGION28_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region28 address low.
+ */
+#define TEE_DMA_REGION28_LOW    0x000FFFFFU
+#define TEE_DMA_REGION28_LOW_M  (TEE_DMA_REGION28_LOW_V << TEE_DMA_REGION28_LOW_S)
+#define TEE_DMA_REGION28_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION28_LOW_S  12
+
+/** TEE_DMA_REGION28_HIGH_REG register
+ *  Region28 address high register.
+ */
+#define TEE_DMA_REGION28_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xec)
+/** TEE_DMA_REGION28_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region28 address high.
+ */
+#define TEE_DMA_REGION28_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION28_HIGH_M  (TEE_DMA_REGION28_HIGH_V << TEE_DMA_REGION28_HIGH_S)
+#define TEE_DMA_REGION28_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION28_HIGH_S  12
+
+/** TEE_DMA_REGION29_LOW_REG register
+ *  Region29 address low register.
+ */
+#define TEE_DMA_REGION29_LOW_REG (DR_REG_TEE_DMA_BASE + 0xf0)
+/** TEE_DMA_REGION29_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region29 address low.
+ */
+#define TEE_DMA_REGION29_LOW    0x000FFFFFU
+#define TEE_DMA_REGION29_LOW_M  (TEE_DMA_REGION29_LOW_V << TEE_DMA_REGION29_LOW_S)
+#define TEE_DMA_REGION29_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION29_LOW_S  12
+
+/** TEE_DMA_REGION29_HIGH_REG register
+ *  Region29 address high register.
+ */
+#define TEE_DMA_REGION29_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xf4)
+/** TEE_DMA_REGION29_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region29 address high.
+ */
+#define TEE_DMA_REGION29_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION29_HIGH_M  (TEE_DMA_REGION29_HIGH_V << TEE_DMA_REGION29_HIGH_S)
+#define TEE_DMA_REGION29_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION29_HIGH_S  12
+
+/** TEE_DMA_REGION30_LOW_REG register
+ *  Region30 address low register.
+ */
+#define TEE_DMA_REGION30_LOW_REG (DR_REG_TEE_DMA_BASE + 0xf8)
+/** TEE_DMA_REGION30_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region30 address low.
+ */
+#define TEE_DMA_REGION30_LOW    0x000FFFFFU
+#define TEE_DMA_REGION30_LOW_M  (TEE_DMA_REGION30_LOW_V << TEE_DMA_REGION30_LOW_S)
+#define TEE_DMA_REGION30_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION30_LOW_S  12
+
+/** TEE_DMA_REGION30_HIGH_REG register
+ *  Region30 address high register.
+ */
+#define TEE_DMA_REGION30_HIGH_REG (DR_REG_TEE_DMA_BASE + 0xfc)
+/** TEE_DMA_REGION30_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region30 address high.
+ */
+#define TEE_DMA_REGION30_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION30_HIGH_M  (TEE_DMA_REGION30_HIGH_V << TEE_DMA_REGION30_HIGH_S)
+#define TEE_DMA_REGION30_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION30_HIGH_S  12
+
+/** TEE_DMA_REGION31_LOW_REG register
+ *  Region31 address low register.
+ */
+#define TEE_DMA_REGION31_LOW_REG (DR_REG_TEE_DMA_BASE + 0x100)
+/** TEE_DMA_REGION31_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Region31 address low.
+ */
+#define TEE_DMA_REGION31_LOW    0x000FFFFFU
+#define TEE_DMA_REGION31_LOW_M  (TEE_DMA_REGION31_LOW_V << TEE_DMA_REGION31_LOW_S)
+#define TEE_DMA_REGION31_LOW_V  0x000FFFFFU
+#define TEE_DMA_REGION31_LOW_S  12
+
+/** TEE_DMA_REGION31_HIGH_REG register
+ *  Region31 address high register.
+ */
+#define TEE_DMA_REGION31_HIGH_REG (DR_REG_TEE_DMA_BASE + 0x104)
+/** TEE_DMA_REGION31_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Region31 address high.
+ */
+#define TEE_DMA_REGION31_HIGH    0x000FFFFFU
+#define TEE_DMA_REGION31_HIGH_M  (TEE_DMA_REGION31_HIGH_V << TEE_DMA_REGION31_HIGH_S)
+#define TEE_DMA_REGION31_HIGH_V  0x000FFFFFU
+#define TEE_DMA_REGION31_HIGH_S  12
+
+/** TEE_DMA_GMDA_CH0_R_PMS_REG register
+ *  GDMA ch0 read permission control registers.
+ */
+#define TEE_DMA_GMDA_CH0_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x108)
+/** TEE_DMA_GDMA_CH0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch0 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH0_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH0_R_PMS_M  (TEE_DMA_GDMA_CH0_R_PMS_V << TEE_DMA_GDMA_CH0_R_PMS_S)
+#define TEE_DMA_GDMA_CH0_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH0_R_PMS_S  0
+
+/** TEE_DMA_GMDA_CH0_W_PMS_REG register
+ *  GDMA ch0 write permission control registers.
+ */
+#define TEE_DMA_GMDA_CH0_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x10c)
+/** TEE_DMA_GDMA_CH0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch0 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH0_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH0_W_PMS_M  (TEE_DMA_GDMA_CH0_W_PMS_V << TEE_DMA_GDMA_CH0_W_PMS_S)
+#define TEE_DMA_GDMA_CH0_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH0_W_PMS_S  0
+
+/** TEE_DMA_GMDA_CH1_R_PMS_REG register
+ *  GDMA ch1 read permission control registers.
+ */
+#define TEE_DMA_GMDA_CH1_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x110)
+/** TEE_DMA_GDMA_CH1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch1 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH1_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH1_R_PMS_M  (TEE_DMA_GDMA_CH1_R_PMS_V << TEE_DMA_GDMA_CH1_R_PMS_S)
+#define TEE_DMA_GDMA_CH1_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH1_R_PMS_S  0
+
+/** TEE_DMA_GMDA_CH1_W_PMS_REG register
+ *  GDMA ch1 write permission control registers.
+ */
+#define TEE_DMA_GMDA_CH1_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x114)
+/** TEE_DMA_GDMA_CH1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch1 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH1_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH1_W_PMS_M  (TEE_DMA_GDMA_CH1_W_PMS_V << TEE_DMA_GDMA_CH1_W_PMS_S)
+#define TEE_DMA_GDMA_CH1_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH1_W_PMS_S  0
+
+/** TEE_DMA_GMDA_CH2_R_PMS_REG register
+ *  GDMA ch2 read permission control registers.
+ */
+#define TEE_DMA_GMDA_CH2_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x118)
+/** TEE_DMA_GDMA_CH2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch2 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH2_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH2_R_PMS_M  (TEE_DMA_GDMA_CH2_R_PMS_V << TEE_DMA_GDMA_CH2_R_PMS_S)
+#define TEE_DMA_GDMA_CH2_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH2_R_PMS_S  0
+
+/** TEE_DMA_GMDA_CH2_W_PMS_REG register
+ *  GDMA ch2 write permission control registers.
+ */
+#define TEE_DMA_GMDA_CH2_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x11c)
+/** TEE_DMA_GDMA_CH2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch2 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH2_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH2_W_PMS_M  (TEE_DMA_GDMA_CH2_W_PMS_V << TEE_DMA_GDMA_CH2_W_PMS_S)
+#define TEE_DMA_GDMA_CH2_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH2_W_PMS_S  0
+
+/** TEE_DMA_GMDA_CH3_R_PMS_REG register
+ *  GDMA ch3 read permission control registers.
+ */
+#define TEE_DMA_GMDA_CH3_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x120)
+/** TEE_DMA_GDMA_CH3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch3 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH3_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH3_R_PMS_M  (TEE_DMA_GDMA_CH3_R_PMS_V << TEE_DMA_GDMA_CH3_R_PMS_S)
+#define TEE_DMA_GDMA_CH3_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH3_R_PMS_S  0
+
+/** TEE_DMA_GMDA_CH3_W_PMS_REG register
+ *  GDMA ch3 write permission control registers.
+ */
+#define TEE_DMA_GMDA_CH3_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x124)
+/** TEE_DMA_GDMA_CH3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GDMA ch3 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GDMA_CH3_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH3_W_PMS_M  (TEE_DMA_GDMA_CH3_W_PMS_V << TEE_DMA_GDMA_CH3_W_PMS_S)
+#define TEE_DMA_GDMA_CH3_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GDMA_CH3_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_ADC_R_PMS_REG register
+ *  AHB PDMA adc read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x128)
+/** TEE_DMA_AHB_PDMA_ADC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA adc read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS_M  (TEE_DMA_AHB_PDMA_ADC_R_PMS_V << TEE_DMA_AHB_PDMA_ADC_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_ADC_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_ADC_W_PMS_REG register
+ *  AHB PDMA adc write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x12c)
+/** TEE_DMA_AHB_PDMA_ADC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA adc write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS_M  (TEE_DMA_AHB_PDMA_ADC_W_PMS_V << TEE_DMA_AHB_PDMA_ADC_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_ADC_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S0_R_PMS_REG register
+ *  AHB PDMA i2s0 read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x130)
+/** TEE_DMA_AHB_PDMA_I2S0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s0 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_M  (TEE_DMA_AHB_PDMA_I2S0_R_PMS_V << TEE_DMA_AHB_PDMA_I2S0_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S0_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S0_W_PMS_REG register
+ *  AHB PDMA i2s0 write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x134)
+/** TEE_DMA_AHB_PDMA_I2S0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s0 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_M  (TEE_DMA_AHB_PDMA_I2S0_W_PMS_V << TEE_DMA_AHB_PDMA_I2S0_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S0_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S1_R_PMS_REG register
+ *  AHB PDMA i2s1 read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x138)
+/** TEE_DMA_AHB_PDMA_I2S1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s1 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_M  (TEE_DMA_AHB_PDMA_I2S1_R_PMS_V << TEE_DMA_AHB_PDMA_I2S1_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S1_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S1_W_PMS_REG register
+ *  AHB PDMA i2s1 write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x13c)
+/** TEE_DMA_AHB_PDMA_I2S1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s1 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_M  (TEE_DMA_AHB_PDMA_I2S1_W_PMS_V << TEE_DMA_AHB_PDMA_I2S1_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S1_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S2_R_PMS_REG register
+ *  AHB PDMA i2s2 read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x140)
+/** TEE_DMA_AHB_PDMA_I2S2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s2 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_M  (TEE_DMA_AHB_PDMA_I2S2_R_PMS_V << TEE_DMA_AHB_PDMA_I2S2_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S2_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I2S2_W_PMS_REG register
+ *  AHB PDMA i2s2 write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x144)
+/** TEE_DMA_AHB_PDMA_I2S2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i2s2 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_M  (TEE_DMA_AHB_PDMA_I2S2_W_PMS_V << TEE_DMA_AHB_PDMA_I2S2_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I2S2_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_REG register
+ *  AHB PDMA i3s mst read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x148)
+/** TEE_DMA_AHB_PDMA_I3C_MST_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i3c mst read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_M  (TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_V << TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I3C_MST_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_REG register
+ *  AHB PDMA i3c mst  write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x14c)
+/** TEE_DMA_AHB_PDMA_I3C_MST_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA i3c mst  write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_M  (TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_V << TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_I3C_MST_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_UHCI0_R_PMS_REG register
+ *  AHB PDMA uhci0 read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x150)
+/** TEE_DMA_AHB_PDMA_UHCI0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA uhci0 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_M  (TEE_DMA_AHB_PDMA_UHCI0_R_PMS_V << TEE_DMA_AHB_PDMA_UHCI0_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_UHCI0_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_UHCI0_W_PMS_REG register
+ *  AHB PDMA uhci0 write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x154)
+/** TEE_DMA_AHB_PDMA_UHCI0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA uhci0 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_M  (TEE_DMA_AHB_PDMA_UHCI0_W_PMS_V << TEE_DMA_AHB_PDMA_UHCI0_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_UHCI0_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_RMT_R_PMS_REG register
+ *  AHB PDMA rmt read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x158)
+/** TEE_DMA_AHB_PDMA_RMT_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA rmt read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS_M  (TEE_DMA_AHB_PDMA_RMT_R_PMS_V << TEE_DMA_AHB_PDMA_RMT_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_RMT_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_RMT_W_PMS_REG register
+ *  AHB PDMA rmt write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x170)
+/** TEE_DMA_AHB_PDMA_RMT_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA rmt write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS_M  (TEE_DMA_AHB_PDMA_RMT_W_PMS_V << TEE_DMA_AHB_PDMA_RMT_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_RMT_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_REG register
+ *  AXI PDMA lcdcam read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x174)
+/** TEE_DMA_AXI_PDMA_LCDCAM_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA lcdcam read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_M  (TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_V << TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_LCDCAM_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_REG register
+ *  AXI PDMA lcdcam write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x178)
+/** TEE_DMA_AXI_PDMA_LCDCAM_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA lcdcam write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_M  (TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_V << TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_LCDCAM_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_REG register
+ *  AXI PDMA gpspi2 read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x17c)
+/** TEE_DMA_AXI_PDMA_GPSPI2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA gpspi2 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_M  (TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_V << TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI2_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_REG register
+ *  AXI PDMA gpspi2 write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x180)
+/** TEE_DMA_AXI_PDMA_GPSPI2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA gpspi2 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_M  (TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_V << TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI2_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_REG register
+ *  AXI PDMA gpspi3 read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x184)
+/** TEE_DMA_AXI_PDMA_GPSPI3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA gpspi3 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_M  (TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_V << TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI3_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_REG register
+ *  AXI PDMA gpspi3 write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x188)
+/** TEE_DMA_AXI_PDMA_GPSPI3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA gpspi3 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_M  (TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_V << TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_GPSPI3_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_PARLIO_R_PMS_REG register
+ *  AXI PDMA parl io read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x18c)
+/** TEE_DMA_AXI_PDMA_PARLIO_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA parl io read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_M  (TEE_DMA_AXI_PDMA_PARLIO_R_PMS_V << TEE_DMA_AXI_PDMA_PARLIO_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_PARLIO_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_PARLIO_W_PMS_REG register
+ *  AXI PDMA parl io write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x190)
+/** TEE_DMA_AXI_PDMA_PARLIO_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA parl io write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_M  (TEE_DMA_AXI_PDMA_PARLIO_W_PMS_V << TEE_DMA_AXI_PDMA_PARLIO_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_PARLIO_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_AES_R_PMS_REG register
+ *  AXI PDMA aes read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_AES_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x194)
+/** TEE_DMA_AXI_PDMA_AES_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA aes read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_AES_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_AES_R_PMS_M  (TEE_DMA_AXI_PDMA_AES_R_PMS_V << TEE_DMA_AXI_PDMA_AES_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_AES_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_AES_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_AES_W_PMS_REG register
+ *  AXI PDMA aes write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_AES_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x198)
+/** TEE_DMA_AXI_PDMA_AES_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA aes write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_AES_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_AES_W_PMS_M  (TEE_DMA_AXI_PDMA_AES_W_PMS_V << TEE_DMA_AXI_PDMA_AES_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_AES_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_AES_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_SHA_R_PMS_REG register
+ *  AXI PDMA sha read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x19c)
+/** TEE_DMA_AXI_PDMA_SHA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA sha read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS_M  (TEE_DMA_AXI_PDMA_SHA_R_PMS_V << TEE_DMA_AXI_PDMA_SHA_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_SHA_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_SHA_W_PMS_REG register
+ *  AXI PDMA sha write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x1a0)
+/** TEE_DMA_AXI_PDMA_SHA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA sha write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS_M  (TEE_DMA_AXI_PDMA_SHA_W_PMS_V << TEE_DMA_AXI_PDMA_SHA_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_SHA_W_PMS_S  0
+
+/** TEE_DMA_DMA2D_JPEG_PMS_R_REG register
+ *  DMA2D JPEG read permission control registers.
+ */
+#define TEE_DMA_DMA2D_JPEG_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1a4)
+/** TEE_DMA_DMA2D_JPEG_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D JPEG read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_JPEG_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_JPEG_R_PMS_M  (TEE_DMA_DMA2D_JPEG_R_PMS_V << TEE_DMA_DMA2D_JPEG_R_PMS_S)
+#define TEE_DMA_DMA2D_JPEG_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_JPEG_R_PMS_S  0
+
+/** TEE_DMA_DMA2D_JPEG_PMS_W_REG register
+ *  DMA2D JPEG write permission control registers.
+ */
+#define TEE_DMA_DMA2D_JPEG_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1a8)
+/** TEE_DMA_DMA2D_JPEG_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D  JPEG write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_JPEG_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_JPEG_W_PMS_M  (TEE_DMA_DMA2D_JPEG_W_PMS_V << TEE_DMA_DMA2D_JPEG_W_PMS_S)
+#define TEE_DMA_DMA2D_JPEG_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_JPEG_W_PMS_S  0
+
+/** TEE_DMA_USB_PMS_R_REG register
+ *  USB read permission control registers.
+ */
+#define TEE_DMA_USB_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1ac)
+/** TEE_DMA_USB_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  USB read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_USB_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_USB_R_PMS_M  (TEE_DMA_USB_R_PMS_V << TEE_DMA_USB_R_PMS_S)
+#define TEE_DMA_USB_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_USB_R_PMS_S  0
+
+/** TEE_DMA_USB_PMS_W_REG register
+ *  USB write permission control registers.
+ */
+#define TEE_DMA_USB_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1b0)
+/** TEE_DMA_USB_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  USB write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_USB_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_USB_W_PMS_M  (TEE_DMA_USB_W_PMS_V << TEE_DMA_USB_W_PMS_S)
+#define TEE_DMA_USB_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_USB_W_PMS_S  0
+
+/** TEE_DMA_GMAC_PMS_R_REG register
+ *  GMAC read permission control registers.
+ */
+#define TEE_DMA_GMAC_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1b4)
+/** TEE_DMA_GMAC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GMAC read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GMAC_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_GMAC_R_PMS_M  (TEE_DMA_GMAC_R_PMS_V << TEE_DMA_GMAC_R_PMS_S)
+#define TEE_DMA_GMAC_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GMAC_R_PMS_S  0
+
+/** TEE_DMA_GMAC_PMS_W_REG register
+ *  GMAC write permission control registers.
+ */
+#define TEE_DMA_GMAC_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1b8)
+/** TEE_DMA_GMAC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GMAC write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_GMAC_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_GMAC_W_PMS_M  (TEE_DMA_GMAC_W_PMS_V << TEE_DMA_GMAC_W_PMS_S)
+#define TEE_DMA_GMAC_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_GMAC_W_PMS_S  0
+
+/** TEE_DMA_SDMMC_PMS_R_REG register
+ *  SDMMC read permission control registers.
+ */
+#define TEE_DMA_SDMMC_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1bc)
+/** TEE_DMA_SDMMC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  SDMMC read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_SDMMC_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_SDMMC_R_PMS_M  (TEE_DMA_SDMMC_R_PMS_V << TEE_DMA_SDMMC_R_PMS_S)
+#define TEE_DMA_SDMMC_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_SDMMC_R_PMS_S  0
+
+/** TEE_DMA_SDMMC_PMS_W_REG register
+ *  SDMMC write permission control registers.
+ */
+#define TEE_DMA_SDMMC_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1c0)
+/** TEE_DMA_SDMMC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  SDMMC write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_SDMMC_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_SDMMC_W_PMS_M  (TEE_DMA_SDMMC_W_PMS_V << TEE_DMA_SDMMC_W_PMS_S)
+#define TEE_DMA_SDMMC_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_SDMMC_W_PMS_S  0
+
+/** TEE_DMA_USBOTG11_PMS_R_REG register
+ *  USBOTG11 read permission control registers.
+ */
+#define TEE_DMA_USBOTG11_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1c4)
+/** TEE_DMA_USBOTG11_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  USBOTG11 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_USBOTG11_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_USBOTG11_R_PMS_M  (TEE_DMA_USBOTG11_R_PMS_V << TEE_DMA_USBOTG11_R_PMS_S)
+#define TEE_DMA_USBOTG11_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_USBOTG11_R_PMS_S  0
+
+/** TEE_DMA_USBOTG11_PMS_W_REG register
+ *  USBOTG11 write permission control registers.
+ */
+#define TEE_DMA_USBOTG11_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1c8)
+/** TEE_DMA_USBOTG11_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  USBOTG11 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_USBOTG11_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_USBOTG11_W_PMS_M  (TEE_DMA_USBOTG11_W_PMS_V << TEE_DMA_USBOTG11_W_PMS_S)
+#define TEE_DMA_USBOTG11_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_USBOTG11_W_PMS_S  0
+
+/** TEE_DMA_TRACE0_PMS_R_REG register
+ *  TRACE0 read permission control registers.
+ */
+#define TEE_DMA_TRACE0_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1cc)
+/** TEE_DMA_TRACE0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TRACE0 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TRACE0_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_TRACE0_R_PMS_M  (TEE_DMA_TRACE0_R_PMS_V << TEE_DMA_TRACE0_R_PMS_S)
+#define TEE_DMA_TRACE0_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TRACE0_R_PMS_S  0
+
+/** TEE_DMA_TRACE0_PMS_W_REG register
+ *  TRACE0 write permission control registers.
+ */
+#define TEE_DMA_TRACE0_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1d0)
+/** TEE_DMA_TRACE0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TRACE0 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TRACE0_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_TRACE0_W_PMS_M  (TEE_DMA_TRACE0_W_PMS_V << TEE_DMA_TRACE0_W_PMS_S)
+#define TEE_DMA_TRACE0_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TRACE0_W_PMS_S  0
+
+/** TEE_DMA_TRACE1_PMS_R_REG register
+ *  TRACE1 read permission control registers.
+ */
+#define TEE_DMA_TRACE1_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1d4)
+/** TEE_DMA_TRACE1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TRACE1 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TRACE1_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_TRACE1_R_PMS_M  (TEE_DMA_TRACE1_R_PMS_V << TEE_DMA_TRACE1_R_PMS_S)
+#define TEE_DMA_TRACE1_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TRACE1_R_PMS_S  0
+
+/** TEE_DMA_TRACE1_PMS_W_REG register
+ *  TRACE1 write permission control registers.
+ */
+#define TEE_DMA_TRACE1_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1d8)
+/** TEE_DMA_TRACE1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TRACE1 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TRACE1_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_TRACE1_W_PMS_M  (TEE_DMA_TRACE1_W_PMS_V << TEE_DMA_TRACE1_W_PMS_S)
+#define TEE_DMA_TRACE1_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TRACE1_W_PMS_S  0
+
+/** TEE_DMA_L2MEM_MON_PMS_R_REG register
+ *  L2MEM MON read permission control registers.
+ */
+#define TEE_DMA_L2MEM_MON_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1dc)
+/** TEE_DMA_L2MEM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  L2MEM MON read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_L2MEM_MON_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_L2MEM_MON_R_PMS_M  (TEE_DMA_L2MEM_MON_R_PMS_V << TEE_DMA_L2MEM_MON_R_PMS_S)
+#define TEE_DMA_L2MEM_MON_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_L2MEM_MON_R_PMS_S  0
+
+/** TEE_DMA_L2MEM_MON_PMS_W_REG register
+ *  L2MEM MON write permission control registers.
+ */
+#define TEE_DMA_L2MEM_MON_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1e0)
+/** TEE_DMA_L2MEM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  L2MEM MON write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_L2MEM_MON_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_L2MEM_MON_W_PMS_M  (TEE_DMA_L2MEM_MON_W_PMS_V << TEE_DMA_L2MEM_MON_W_PMS_S)
+#define TEE_DMA_L2MEM_MON_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_L2MEM_MON_W_PMS_S  0
+
+/** TEE_DMA_TCM_MON_PMS_R_REG register
+ *  TCM MON read permission control registers.
+ */
+#define TEE_DMA_TCM_MON_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1e4)
+/** TEE_DMA_TCM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TCM MON read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TCM_MON_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_TCM_MON_R_PMS_M  (TEE_DMA_TCM_MON_R_PMS_V << TEE_DMA_TCM_MON_R_PMS_S)
+#define TEE_DMA_TCM_MON_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TCM_MON_R_PMS_S  0
+
+/** TEE_DMA_TCM_MON_PMS_W_REG register
+ *  TCM MON write permission control registers.
+ */
+#define TEE_DMA_TCM_MON_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1e8)
+/** TEE_DMA_TCM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  TCM MON write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_TCM_MON_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_TCM_MON_W_PMS_M  (TEE_DMA_TCM_MON_W_PMS_V << TEE_DMA_TCM_MON_W_PMS_S)
+#define TEE_DMA_TCM_MON_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_TCM_MON_W_PMS_S  0
+
+/** TEE_DMA_REGDMA_PMS_R_REG register
+ *  REGDMA read permission control registers.
+ */
+#define TEE_DMA_REGDMA_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1ec)
+/** TEE_DMA_REGDMA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  REGDMA read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_REGDMA_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_REGDMA_R_PMS_M  (TEE_DMA_REGDMA_R_PMS_V << TEE_DMA_REGDMA_R_PMS_S)
+#define TEE_DMA_REGDMA_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_REGDMA_R_PMS_S  0
+
+/** TEE_DMA_REGDMA_PMS_W_REG register
+ *  REGDMA write permission control registers.
+ */
+#define TEE_DMA_REGDMA_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x1f0)
+/** TEE_DMA_REGDMA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  REGDMA write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_REGDMA_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_REGDMA_W_PMS_M  (TEE_DMA_REGDMA_W_PMS_V << TEE_DMA_REGDMA_W_PMS_S)
+#define TEE_DMA_REGDMA_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_REGDMA_W_PMS_S  0
+
+/** TEE_DMA_H264_PMS_R_REG register
+ *  H264 read permission control registers.
+ */
+#define TEE_DMA_H264_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x1fc)
+/** TEE_DMA_H264_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  H264 read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_H264_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_H264_R_PMS_M  (TEE_DMA_H264_R_PMS_V << TEE_DMA_H264_R_PMS_S)
+#define TEE_DMA_H264_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_H264_R_PMS_S  0
+
+/** TEE_DMA_H264_PMS_W_REG register
+ *  H264 write permission control registers.
+ */
+#define TEE_DMA_H264_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x200)
+/** TEE_DMA_H264_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  H264 write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_H264_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_H264_W_PMS_M  (TEE_DMA_H264_W_PMS_V << TEE_DMA_H264_W_PMS_S)
+#define TEE_DMA_H264_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_H264_W_PMS_S  0
+
+/** TEE_DMA_DMA2D_PPA_PMS_R_REG register
+ *  DMA2D PPA read permission control registers.
+ */
+#define TEE_DMA_DMA2D_PPA_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x204)
+/** TEE_DMA_DMA2D_PPA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D PPA  read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_PPA_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_PPA_R_PMS_M  (TEE_DMA_DMA2D_PPA_R_PMS_V << TEE_DMA_DMA2D_PPA_R_PMS_S)
+#define TEE_DMA_DMA2D_PPA_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_PPA_R_PMS_S  0
+
+/** TEE_DMA_DMA2D_PPA_PMS_W_REG register
+ *  DMA2D PPA  write permission control registers.
+ */
+#define TEE_DMA_DMA2D_PPA_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x208)
+/** TEE_DMA_DMA2D_PPA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D  PPA write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_PPA_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_PPA_W_PMS_M  (TEE_DMA_DMA2D_PPA_W_PMS_V << TEE_DMA_DMA2D_PPA_W_PMS_S)
+#define TEE_DMA_DMA2D_PPA_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_PPA_W_PMS_S  0
+
+/** TEE_DMA_DMA2D_DUMMY_PMS_R_REG register
+ *  DMA2D dummy read permission control registers.
+ */
+#define TEE_DMA_DMA2D_DUMMY_PMS_R_REG (DR_REG_TEE_DMA_BASE + 0x20c)
+/** TEE_DMA_DMA2D_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D dummy  read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_DUMMY_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_DUMMY_R_PMS_M  (TEE_DMA_DMA2D_DUMMY_R_PMS_V << TEE_DMA_DMA2D_DUMMY_R_PMS_S)
+#define TEE_DMA_DMA2D_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_DUMMY_R_PMS_S  0
+
+/** TEE_DMA_DMA2D_DUMMY_PMS_W_REG register
+ *  DMA2D dummy  write permission control registers.
+ */
+#define TEE_DMA_DMA2D_DUMMY_PMS_W_REG (DR_REG_TEE_DMA_BASE + 0x210)
+/** TEE_DMA_DMA2D_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  DMA2D dummy  write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_DMA2D_DUMMY_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_DMA2D_DUMMY_W_PMS_M  (TEE_DMA_DMA2D_DUMMY_W_PMS_V << TEE_DMA_DMA2D_DUMMY_W_PMS_S)
+#define TEE_DMA_DMA2D_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_DMA2D_DUMMY_W_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_DUMMY_R_PMS_REG register
+ *  AHB PDMA dummy read permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x214)
+/** TEE_DMA_AHB_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA dummy read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_M  (TEE_DMA_AHB_PDMA_DUMMY_R_PMS_V << TEE_DMA_AHB_PDMA_DUMMY_R_PMS_S)
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_DUMMY_R_PMS_S  0
+
+/** TEE_DMA_AHB_PDMA_DUMMY_W_PMS_REG register
+ *  AHB PDMA dummy write permission control registers.
+ */
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x218)
+/** TEE_DMA_AHB_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AHB PDMA dummy write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_M  (TEE_DMA_AHB_PDMA_DUMMY_W_PMS_V << TEE_DMA_AHB_PDMA_DUMMY_W_PMS_S)
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AHB_PDMA_DUMMY_W_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_DUMMY_R_PMS_REG register
+ *  AXI PDMA dummy read permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_REG (DR_REG_TEE_DMA_BASE + 0x21c)
+/** TEE_DMA_AXI_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA dummy read permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_M  (TEE_DMA_AXI_PDMA_DUMMY_R_PMS_V << TEE_DMA_AXI_PDMA_DUMMY_R_PMS_S)
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_DUMMY_R_PMS_S  0
+
+/** TEE_DMA_AXI_PDMA_DUMMY_W_PMS_REG register
+ *  AXI PDMA dummy write permission control registers.
+ */
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_REG (DR_REG_TEE_DMA_BASE + 0x220)
+/** TEE_DMA_AXI_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI PDMA dummy write permission control, each bit corresponds to a region.
+ */
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS    0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_M  (TEE_DMA_AXI_PDMA_DUMMY_W_PMS_V << TEE_DMA_AXI_PDMA_DUMMY_W_PMS_S)
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define TEE_DMA_AXI_PDMA_DUMMY_W_PMS_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dma_pms_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/dma_pms_reg.h
new file mode 100644
index 0000000000..c07d10067a
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dma_pms_reg.h
@@ -0,0 +1,1740 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_DMA_DATE_REG register
+ *  Version control register
+ */
+#define PMS_DMA_DATE_REG (DR_REG_DMA_PMS_BASE + 0x0)
+/** PMS_DMA_DATE : R/W; bitpos: [31:0]; default: 539165460;
+ *  Version control register.
+ */
+#define PMS_DMA_DATE    0xFFFFFFFFU
+#define PMS_DMA_DATE_M  (PMS_DMA_DATE_V << PMS_DMA_DATE_S)
+#define PMS_DMA_DATE_V  0xFFFFFFFFU
+#define PMS_DMA_DATE_S  0
+
+/** PMS_DMA_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_DMA_CLK_EN_REG (DR_REG_DMA_PMS_BASE + 0x4)
+/** PMS_DMA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating.
+ *  1: Keep the clock always on.
+ */
+#define PMS_DMA_CLK_EN    (BIT(0))
+#define PMS_DMA_CLK_EN_M  (PMS_DMA_CLK_EN_V << PMS_DMA_CLK_EN_S)
+#define PMS_DMA_CLK_EN_V  0x00000001U
+#define PMS_DMA_CLK_EN_S  0
+
+/** PMS_DMA_REGION0_LOW_REG register
+ *  Region0 start address configuration register
+ */
+#define PMS_DMA_REGION0_LOW_REG (DR_REG_DMA_PMS_BASE + 0x8)
+/** PMS_DMA_REGION0_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region0.
+ */
+#define PMS_DMA_REGION0_LOW    0x000FFFFFU
+#define PMS_DMA_REGION0_LOW_M  (PMS_DMA_REGION0_LOW_V << PMS_DMA_REGION0_LOW_S)
+#define PMS_DMA_REGION0_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION0_LOW_S  12
+
+/** PMS_DMA_REGION0_HIGH_REG register
+ *  Region0 end address configuration register
+ */
+#define PMS_DMA_REGION0_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xc)
+/** PMS_DMA_REGION0_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region0.
+ */
+#define PMS_DMA_REGION0_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION0_HIGH_M  (PMS_DMA_REGION0_HIGH_V << PMS_DMA_REGION0_HIGH_S)
+#define PMS_DMA_REGION0_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION0_HIGH_S  12
+
+/** PMS_DMA_REGION1_LOW_REG register
+ *  Region1 start address configuration register
+ */
+#define PMS_DMA_REGION1_LOW_REG (DR_REG_DMA_PMS_BASE + 0x10)
+/** PMS_DMA_REGION1_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region1.
+ */
+#define PMS_DMA_REGION1_LOW    0x000FFFFFU
+#define PMS_DMA_REGION1_LOW_M  (PMS_DMA_REGION1_LOW_V << PMS_DMA_REGION1_LOW_S)
+#define PMS_DMA_REGION1_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION1_LOW_S  12
+
+/** PMS_DMA_REGION1_HIGH_REG register
+ *  Region1 end address configuration register
+ */
+#define PMS_DMA_REGION1_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x14)
+/** PMS_DMA_REGION1_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region1.
+ */
+#define PMS_DMA_REGION1_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION1_HIGH_M  (PMS_DMA_REGION1_HIGH_V << PMS_DMA_REGION1_HIGH_S)
+#define PMS_DMA_REGION1_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION1_HIGH_S  12
+
+/** PMS_DMA_REGION2_LOW_REG register
+ *  Region2 start address configuration register
+ */
+#define PMS_DMA_REGION2_LOW_REG (DR_REG_DMA_PMS_BASE + 0x18)
+/** PMS_DMA_REGION2_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region2.
+ */
+#define PMS_DMA_REGION2_LOW    0x000FFFFFU
+#define PMS_DMA_REGION2_LOW_M  (PMS_DMA_REGION2_LOW_V << PMS_DMA_REGION2_LOW_S)
+#define PMS_DMA_REGION2_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION2_LOW_S  12
+
+/** PMS_DMA_REGION2_HIGH_REG register
+ *  Region2 end address configuration register
+ */
+#define PMS_DMA_REGION2_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x1c)
+/** PMS_DMA_REGION2_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region2.
+ */
+#define PMS_DMA_REGION2_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION2_HIGH_M  (PMS_DMA_REGION2_HIGH_V << PMS_DMA_REGION2_HIGH_S)
+#define PMS_DMA_REGION2_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION2_HIGH_S  12
+
+/** PMS_DMA_REGION3_LOW_REG register
+ *  Region3 start address configuration register
+ */
+#define PMS_DMA_REGION3_LOW_REG (DR_REG_DMA_PMS_BASE + 0x20)
+/** PMS_DMA_REGION3_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region3.
+ */
+#define PMS_DMA_REGION3_LOW    0x000FFFFFU
+#define PMS_DMA_REGION3_LOW_M  (PMS_DMA_REGION3_LOW_V << PMS_DMA_REGION3_LOW_S)
+#define PMS_DMA_REGION3_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION3_LOW_S  12
+
+/** PMS_DMA_REGION3_HIGH_REG register
+ *  Region3 end address configuration register
+ */
+#define PMS_DMA_REGION3_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x24)
+/** PMS_DMA_REGION3_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region3.
+ */
+#define PMS_DMA_REGION3_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION3_HIGH_M  (PMS_DMA_REGION3_HIGH_V << PMS_DMA_REGION3_HIGH_S)
+#define PMS_DMA_REGION3_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION3_HIGH_S  12
+
+/** PMS_DMA_REGION4_LOW_REG register
+ *  Region4 start address configuration register
+ */
+#define PMS_DMA_REGION4_LOW_REG (DR_REG_DMA_PMS_BASE + 0x28)
+/** PMS_DMA_REGION4_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region4.
+ */
+#define PMS_DMA_REGION4_LOW    0x000FFFFFU
+#define PMS_DMA_REGION4_LOW_M  (PMS_DMA_REGION4_LOW_V << PMS_DMA_REGION4_LOW_S)
+#define PMS_DMA_REGION4_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION4_LOW_S  12
+
+/** PMS_DMA_REGION4_HIGH_REG register
+ *  Region4 end address configuration register
+ */
+#define PMS_DMA_REGION4_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x2c)
+/** PMS_DMA_REGION4_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region4.
+ */
+#define PMS_DMA_REGION4_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION4_HIGH_M  (PMS_DMA_REGION4_HIGH_V << PMS_DMA_REGION4_HIGH_S)
+#define PMS_DMA_REGION4_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION4_HIGH_S  12
+
+/** PMS_DMA_REGION5_LOW_REG register
+ *  Region5 start address configuration register
+ */
+#define PMS_DMA_REGION5_LOW_REG (DR_REG_DMA_PMS_BASE + 0x30)
+/** PMS_DMA_REGION5_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region5.
+ */
+#define PMS_DMA_REGION5_LOW    0x000FFFFFU
+#define PMS_DMA_REGION5_LOW_M  (PMS_DMA_REGION5_LOW_V << PMS_DMA_REGION5_LOW_S)
+#define PMS_DMA_REGION5_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION5_LOW_S  12
+
+/** PMS_DMA_REGION5_HIGH_REG register
+ *  Region5 end address configuration register
+ */
+#define PMS_DMA_REGION5_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x34)
+/** PMS_DMA_REGION5_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region5.
+ */
+#define PMS_DMA_REGION5_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION5_HIGH_M  (PMS_DMA_REGION5_HIGH_V << PMS_DMA_REGION5_HIGH_S)
+#define PMS_DMA_REGION5_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION5_HIGH_S  12
+
+/** PMS_DMA_REGION6_LOW_REG register
+ *  Region6 start address configuration register
+ */
+#define PMS_DMA_REGION6_LOW_REG (DR_REG_DMA_PMS_BASE + 0x38)
+/** PMS_DMA_REGION6_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region6.
+ */
+#define PMS_DMA_REGION6_LOW    0x000FFFFFU
+#define PMS_DMA_REGION6_LOW_M  (PMS_DMA_REGION6_LOW_V << PMS_DMA_REGION6_LOW_S)
+#define PMS_DMA_REGION6_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION6_LOW_S  12
+
+/** PMS_DMA_REGION6_HIGH_REG register
+ *  Region6 end address configuration register
+ */
+#define PMS_DMA_REGION6_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x3c)
+/** PMS_DMA_REGION6_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region6.
+ */
+#define PMS_DMA_REGION6_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION6_HIGH_M  (PMS_DMA_REGION6_HIGH_V << PMS_DMA_REGION6_HIGH_S)
+#define PMS_DMA_REGION6_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION6_HIGH_S  12
+
+/** PMS_DMA_REGION7_LOW_REG register
+ *  Region7 start address configuration register
+ */
+#define PMS_DMA_REGION7_LOW_REG (DR_REG_DMA_PMS_BASE + 0x40)
+/** PMS_DMA_REGION7_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region7.
+ */
+#define PMS_DMA_REGION7_LOW    0x000FFFFFU
+#define PMS_DMA_REGION7_LOW_M  (PMS_DMA_REGION7_LOW_V << PMS_DMA_REGION7_LOW_S)
+#define PMS_DMA_REGION7_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION7_LOW_S  12
+
+/** PMS_DMA_REGION7_HIGH_REG register
+ *  Region7 end address configuration register
+ */
+#define PMS_DMA_REGION7_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x44)
+/** PMS_DMA_REGION7_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region7.
+ */
+#define PMS_DMA_REGION7_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION7_HIGH_M  (PMS_DMA_REGION7_HIGH_V << PMS_DMA_REGION7_HIGH_S)
+#define PMS_DMA_REGION7_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION7_HIGH_S  12
+
+/** PMS_DMA_REGION8_LOW_REG register
+ *  Region8 start address configuration register
+ */
+#define PMS_DMA_REGION8_LOW_REG (DR_REG_DMA_PMS_BASE + 0x48)
+/** PMS_DMA_REGION8_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region8.
+ */
+#define PMS_DMA_REGION8_LOW    0x000FFFFFU
+#define PMS_DMA_REGION8_LOW_M  (PMS_DMA_REGION8_LOW_V << PMS_DMA_REGION8_LOW_S)
+#define PMS_DMA_REGION8_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION8_LOW_S  12
+
+/** PMS_DMA_REGION8_HIGH_REG register
+ *  Region8 end address configuration register
+ */
+#define PMS_DMA_REGION8_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x4c)
+/** PMS_DMA_REGION8_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region8.
+ */
+#define PMS_DMA_REGION8_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION8_HIGH_M  (PMS_DMA_REGION8_HIGH_V << PMS_DMA_REGION8_HIGH_S)
+#define PMS_DMA_REGION8_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION8_HIGH_S  12
+
+/** PMS_DMA_REGION9_LOW_REG register
+ *  Region9 start address configuration register
+ */
+#define PMS_DMA_REGION9_LOW_REG (DR_REG_DMA_PMS_BASE + 0x50)
+/** PMS_DMA_REGION9_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region9.
+ */
+#define PMS_DMA_REGION9_LOW    0x000FFFFFU
+#define PMS_DMA_REGION9_LOW_M  (PMS_DMA_REGION9_LOW_V << PMS_DMA_REGION9_LOW_S)
+#define PMS_DMA_REGION9_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION9_LOW_S  12
+
+/** PMS_DMA_REGION9_HIGH_REG register
+ *  Region9 end address configuration register
+ */
+#define PMS_DMA_REGION9_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x54)
+/** PMS_DMA_REGION9_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region9.
+ */
+#define PMS_DMA_REGION9_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION9_HIGH_M  (PMS_DMA_REGION9_HIGH_V << PMS_DMA_REGION9_HIGH_S)
+#define PMS_DMA_REGION9_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION9_HIGH_S  12
+
+/** PMS_DMA_REGION10_LOW_REG register
+ *  Region10 start address configuration register
+ */
+#define PMS_DMA_REGION10_LOW_REG (DR_REG_DMA_PMS_BASE + 0x58)
+/** PMS_DMA_REGION10_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region10.
+ */
+#define PMS_DMA_REGION10_LOW    0x000FFFFFU
+#define PMS_DMA_REGION10_LOW_M  (PMS_DMA_REGION10_LOW_V << PMS_DMA_REGION10_LOW_S)
+#define PMS_DMA_REGION10_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION10_LOW_S  12
+
+/** PMS_DMA_REGION10_HIGH_REG register
+ *  Region10 end address configuration register
+ */
+#define PMS_DMA_REGION10_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x5c)
+/** PMS_DMA_REGION10_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region10.
+ */
+#define PMS_DMA_REGION10_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION10_HIGH_M  (PMS_DMA_REGION10_HIGH_V << PMS_DMA_REGION10_HIGH_S)
+#define PMS_DMA_REGION10_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION10_HIGH_S  12
+
+/** PMS_DMA_REGION11_LOW_REG register
+ *  Region11 start address configuration register
+ */
+#define PMS_DMA_REGION11_LOW_REG (DR_REG_DMA_PMS_BASE + 0x60)
+/** PMS_DMA_REGION11_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region11.
+ */
+#define PMS_DMA_REGION11_LOW    0x000FFFFFU
+#define PMS_DMA_REGION11_LOW_M  (PMS_DMA_REGION11_LOW_V << PMS_DMA_REGION11_LOW_S)
+#define PMS_DMA_REGION11_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION11_LOW_S  12
+
+/** PMS_DMA_REGION11_HIGH_REG register
+ *  Region11 end address configuration register
+ */
+#define PMS_DMA_REGION11_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x64)
+/** PMS_DMA_REGION11_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region11.
+ */
+#define PMS_DMA_REGION11_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION11_HIGH_M  (PMS_DMA_REGION11_HIGH_V << PMS_DMA_REGION11_HIGH_S)
+#define PMS_DMA_REGION11_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION11_HIGH_S  12
+
+/** PMS_DMA_REGION12_LOW_REG register
+ *  Region12 start address configuration register
+ */
+#define PMS_DMA_REGION12_LOW_REG (DR_REG_DMA_PMS_BASE + 0x68)
+/** PMS_DMA_REGION12_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region12.
+ */
+#define PMS_DMA_REGION12_LOW    0x000FFFFFU
+#define PMS_DMA_REGION12_LOW_M  (PMS_DMA_REGION12_LOW_V << PMS_DMA_REGION12_LOW_S)
+#define PMS_DMA_REGION12_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION12_LOW_S  12
+
+/** PMS_DMA_REGION12_HIGH_REG register
+ *  Region12 end address configuration register
+ */
+#define PMS_DMA_REGION12_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x6c)
+/** PMS_DMA_REGION12_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region12.
+ */
+#define PMS_DMA_REGION12_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION12_HIGH_M  (PMS_DMA_REGION12_HIGH_V << PMS_DMA_REGION12_HIGH_S)
+#define PMS_DMA_REGION12_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION12_HIGH_S  12
+
+/** PMS_DMA_REGION13_LOW_REG register
+ *  Region13 start address configuration register
+ */
+#define PMS_DMA_REGION13_LOW_REG (DR_REG_DMA_PMS_BASE + 0x70)
+/** PMS_DMA_REGION13_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region13.
+ */
+#define PMS_DMA_REGION13_LOW    0x000FFFFFU
+#define PMS_DMA_REGION13_LOW_M  (PMS_DMA_REGION13_LOW_V << PMS_DMA_REGION13_LOW_S)
+#define PMS_DMA_REGION13_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION13_LOW_S  12
+
+/** PMS_DMA_REGION13_HIGH_REG register
+ *  Region13 end address configuration register
+ */
+#define PMS_DMA_REGION13_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x74)
+/** PMS_DMA_REGION13_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region13.
+ */
+#define PMS_DMA_REGION13_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION13_HIGH_M  (PMS_DMA_REGION13_HIGH_V << PMS_DMA_REGION13_HIGH_S)
+#define PMS_DMA_REGION13_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION13_HIGH_S  12
+
+/** PMS_DMA_REGION14_LOW_REG register
+ *  Region14 start address configuration register
+ */
+#define PMS_DMA_REGION14_LOW_REG (DR_REG_DMA_PMS_BASE + 0x78)
+/** PMS_DMA_REGION14_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region14.
+ */
+#define PMS_DMA_REGION14_LOW    0x000FFFFFU
+#define PMS_DMA_REGION14_LOW_M  (PMS_DMA_REGION14_LOW_V << PMS_DMA_REGION14_LOW_S)
+#define PMS_DMA_REGION14_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION14_LOW_S  12
+
+/** PMS_DMA_REGION14_HIGH_REG register
+ *  Region14 end address configuration register
+ */
+#define PMS_DMA_REGION14_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x7c)
+/** PMS_DMA_REGION14_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region14.
+ */
+#define PMS_DMA_REGION14_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION14_HIGH_M  (PMS_DMA_REGION14_HIGH_V << PMS_DMA_REGION14_HIGH_S)
+#define PMS_DMA_REGION14_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION14_HIGH_S  12
+
+/** PMS_DMA_REGION15_LOW_REG register
+ *  Region15 start address configuration register
+ */
+#define PMS_DMA_REGION15_LOW_REG (DR_REG_DMA_PMS_BASE + 0x80)
+/** PMS_DMA_REGION15_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region15.
+ */
+#define PMS_DMA_REGION15_LOW    0x000FFFFFU
+#define PMS_DMA_REGION15_LOW_M  (PMS_DMA_REGION15_LOW_V << PMS_DMA_REGION15_LOW_S)
+#define PMS_DMA_REGION15_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION15_LOW_S  12
+
+/** PMS_DMA_REGION15_HIGH_REG register
+ *  Region15 end address configuration register
+ */
+#define PMS_DMA_REGION15_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x84)
+/** PMS_DMA_REGION15_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region15.
+ */
+#define PMS_DMA_REGION15_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION15_HIGH_M  (PMS_DMA_REGION15_HIGH_V << PMS_DMA_REGION15_HIGH_S)
+#define PMS_DMA_REGION15_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION15_HIGH_S  12
+
+/** PMS_DMA_REGION16_LOW_REG register
+ *  Region16 start address configuration register
+ */
+#define PMS_DMA_REGION16_LOW_REG (DR_REG_DMA_PMS_BASE + 0x88)
+/** PMS_DMA_REGION16_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region16.
+ */
+#define PMS_DMA_REGION16_LOW    0x000FFFFFU
+#define PMS_DMA_REGION16_LOW_M  (PMS_DMA_REGION16_LOW_V << PMS_DMA_REGION16_LOW_S)
+#define PMS_DMA_REGION16_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION16_LOW_S  12
+
+/** PMS_DMA_REGION16_HIGH_REG register
+ *  Region16 end address configuration register
+ */
+#define PMS_DMA_REGION16_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x8c)
+/** PMS_DMA_REGION16_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region16.
+ */
+#define PMS_DMA_REGION16_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION16_HIGH_M  (PMS_DMA_REGION16_HIGH_V << PMS_DMA_REGION16_HIGH_S)
+#define PMS_DMA_REGION16_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION16_HIGH_S  12
+
+/** PMS_DMA_REGION17_LOW_REG register
+ *  Region17 start address configuration register
+ */
+#define PMS_DMA_REGION17_LOW_REG (DR_REG_DMA_PMS_BASE + 0x90)
+/** PMS_DMA_REGION17_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region17.
+ */
+#define PMS_DMA_REGION17_LOW    0x000FFFFFU
+#define PMS_DMA_REGION17_LOW_M  (PMS_DMA_REGION17_LOW_V << PMS_DMA_REGION17_LOW_S)
+#define PMS_DMA_REGION17_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION17_LOW_S  12
+
+/** PMS_DMA_REGION17_HIGH_REG register
+ *  Region17 end address configuration register
+ */
+#define PMS_DMA_REGION17_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x94)
+/** PMS_DMA_REGION17_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region17.
+ */
+#define PMS_DMA_REGION17_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION17_HIGH_M  (PMS_DMA_REGION17_HIGH_V << PMS_DMA_REGION17_HIGH_S)
+#define PMS_DMA_REGION17_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION17_HIGH_S  12
+
+/** PMS_DMA_REGION18_LOW_REG register
+ *  Region18 start address configuration register
+ */
+#define PMS_DMA_REGION18_LOW_REG (DR_REG_DMA_PMS_BASE + 0x98)
+/** PMS_DMA_REGION18_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region18.
+ */
+#define PMS_DMA_REGION18_LOW    0x000FFFFFU
+#define PMS_DMA_REGION18_LOW_M  (PMS_DMA_REGION18_LOW_V << PMS_DMA_REGION18_LOW_S)
+#define PMS_DMA_REGION18_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION18_LOW_S  12
+
+/** PMS_DMA_REGION18_HIGH_REG register
+ *  Region18 end address configuration register
+ */
+#define PMS_DMA_REGION18_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x9c)
+/** PMS_DMA_REGION18_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region18.
+ */
+#define PMS_DMA_REGION18_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION18_HIGH_M  (PMS_DMA_REGION18_HIGH_V << PMS_DMA_REGION18_HIGH_S)
+#define PMS_DMA_REGION18_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION18_HIGH_S  12
+
+/** PMS_DMA_REGION19_LOW_REG register
+ *  Region19 start address configuration register
+ */
+#define PMS_DMA_REGION19_LOW_REG (DR_REG_DMA_PMS_BASE + 0xa0)
+/** PMS_DMA_REGION19_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region19.
+ */
+#define PMS_DMA_REGION19_LOW    0x000FFFFFU
+#define PMS_DMA_REGION19_LOW_M  (PMS_DMA_REGION19_LOW_V << PMS_DMA_REGION19_LOW_S)
+#define PMS_DMA_REGION19_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION19_LOW_S  12
+
+/** PMS_DMA_REGION19_HIGH_REG register
+ *  Region19 end address configuration register
+ */
+#define PMS_DMA_REGION19_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xa4)
+/** PMS_DMA_REGION19_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region19.
+ */
+#define PMS_DMA_REGION19_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION19_HIGH_M  (PMS_DMA_REGION19_HIGH_V << PMS_DMA_REGION19_HIGH_S)
+#define PMS_DMA_REGION19_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION19_HIGH_S  12
+
+/** PMS_DMA_REGION20_LOW_REG register
+ *  Region20 start address configuration register
+ */
+#define PMS_DMA_REGION20_LOW_REG (DR_REG_DMA_PMS_BASE + 0xa8)
+/** PMS_DMA_REGION20_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region20.
+ */
+#define PMS_DMA_REGION20_LOW    0x000FFFFFU
+#define PMS_DMA_REGION20_LOW_M  (PMS_DMA_REGION20_LOW_V << PMS_DMA_REGION20_LOW_S)
+#define PMS_DMA_REGION20_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION20_LOW_S  12
+
+/** PMS_DMA_REGION20_HIGH_REG register
+ *  Region20 end address configuration register
+ */
+#define PMS_DMA_REGION20_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xac)
+/** PMS_DMA_REGION20_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region20.
+ */
+#define PMS_DMA_REGION20_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION20_HIGH_M  (PMS_DMA_REGION20_HIGH_V << PMS_DMA_REGION20_HIGH_S)
+#define PMS_DMA_REGION20_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION20_HIGH_S  12
+
+/** PMS_DMA_REGION21_LOW_REG register
+ *  Region21 start address configuration register
+ */
+#define PMS_DMA_REGION21_LOW_REG (DR_REG_DMA_PMS_BASE + 0xb0)
+/** PMS_DMA_REGION21_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region21.
+ */
+#define PMS_DMA_REGION21_LOW    0x000FFFFFU
+#define PMS_DMA_REGION21_LOW_M  (PMS_DMA_REGION21_LOW_V << PMS_DMA_REGION21_LOW_S)
+#define PMS_DMA_REGION21_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION21_LOW_S  12
+
+/** PMS_DMA_REGION21_HIGH_REG register
+ *  Region21 end address configuration register
+ */
+#define PMS_DMA_REGION21_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xb4)
+/** PMS_DMA_REGION21_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region21.
+ */
+#define PMS_DMA_REGION21_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION21_HIGH_M  (PMS_DMA_REGION21_HIGH_V << PMS_DMA_REGION21_HIGH_S)
+#define PMS_DMA_REGION21_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION21_HIGH_S  12
+
+/** PMS_DMA_REGION22_LOW_REG register
+ *  Region22 start address configuration register
+ */
+#define PMS_DMA_REGION22_LOW_REG (DR_REG_DMA_PMS_BASE + 0xb8)
+/** PMS_DMA_REGION22_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region22.
+ */
+#define PMS_DMA_REGION22_LOW    0x000FFFFFU
+#define PMS_DMA_REGION22_LOW_M  (PMS_DMA_REGION22_LOW_V << PMS_DMA_REGION22_LOW_S)
+#define PMS_DMA_REGION22_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION22_LOW_S  12
+
+/** PMS_DMA_REGION22_HIGH_REG register
+ *  Region22 end address configuration register
+ */
+#define PMS_DMA_REGION22_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xbc)
+/** PMS_DMA_REGION22_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region22.
+ */
+#define PMS_DMA_REGION22_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION22_HIGH_M  (PMS_DMA_REGION22_HIGH_V << PMS_DMA_REGION22_HIGH_S)
+#define PMS_DMA_REGION22_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION22_HIGH_S  12
+
+/** PMS_DMA_REGION23_LOW_REG register
+ *  Region23 start address configuration register
+ */
+#define PMS_DMA_REGION23_LOW_REG (DR_REG_DMA_PMS_BASE + 0xc0)
+/** PMS_DMA_REGION23_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region23.
+ */
+#define PMS_DMA_REGION23_LOW    0x000FFFFFU
+#define PMS_DMA_REGION23_LOW_M  (PMS_DMA_REGION23_LOW_V << PMS_DMA_REGION23_LOW_S)
+#define PMS_DMA_REGION23_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION23_LOW_S  12
+
+/** PMS_DMA_REGION23_HIGH_REG register
+ *  Region23 end address configuration register
+ */
+#define PMS_DMA_REGION23_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xc4)
+/** PMS_DMA_REGION23_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region23.
+ */
+#define PMS_DMA_REGION23_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION23_HIGH_M  (PMS_DMA_REGION23_HIGH_V << PMS_DMA_REGION23_HIGH_S)
+#define PMS_DMA_REGION23_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION23_HIGH_S  12
+
+/** PMS_DMA_REGION24_LOW_REG register
+ *  Region24 start address configuration register
+ */
+#define PMS_DMA_REGION24_LOW_REG (DR_REG_DMA_PMS_BASE + 0xc8)
+/** PMS_DMA_REGION24_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region24.
+ */
+#define PMS_DMA_REGION24_LOW    0x000FFFFFU
+#define PMS_DMA_REGION24_LOW_M  (PMS_DMA_REGION24_LOW_V << PMS_DMA_REGION24_LOW_S)
+#define PMS_DMA_REGION24_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION24_LOW_S  12
+
+/** PMS_DMA_REGION24_HIGH_REG register
+ *  Region24 end address configuration register
+ */
+#define PMS_DMA_REGION24_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xcc)
+/** PMS_DMA_REGION24_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region24.
+ */
+#define PMS_DMA_REGION24_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION24_HIGH_M  (PMS_DMA_REGION24_HIGH_V << PMS_DMA_REGION24_HIGH_S)
+#define PMS_DMA_REGION24_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION24_HIGH_S  12
+
+/** PMS_DMA_REGION25_LOW_REG register
+ *  Region25 start address configuration register
+ */
+#define PMS_DMA_REGION25_LOW_REG (DR_REG_DMA_PMS_BASE + 0xd0)
+/** PMS_DMA_REGION25_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region25.
+ */
+#define PMS_DMA_REGION25_LOW    0x000FFFFFU
+#define PMS_DMA_REGION25_LOW_M  (PMS_DMA_REGION25_LOW_V << PMS_DMA_REGION25_LOW_S)
+#define PMS_DMA_REGION25_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION25_LOW_S  12
+
+/** PMS_DMA_REGION25_HIGH_REG register
+ *  Region25 end address configuration register
+ */
+#define PMS_DMA_REGION25_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xd4)
+/** PMS_DMA_REGION25_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region25.
+ */
+#define PMS_DMA_REGION25_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION25_HIGH_M  (PMS_DMA_REGION25_HIGH_V << PMS_DMA_REGION25_HIGH_S)
+#define PMS_DMA_REGION25_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION25_HIGH_S  12
+
+/** PMS_DMA_REGION26_LOW_REG register
+ *  Region26 start address configuration register
+ */
+#define PMS_DMA_REGION26_LOW_REG (DR_REG_DMA_PMS_BASE + 0xd8)
+/** PMS_DMA_REGION26_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region26.
+ */
+#define PMS_DMA_REGION26_LOW    0x000FFFFFU
+#define PMS_DMA_REGION26_LOW_M  (PMS_DMA_REGION26_LOW_V << PMS_DMA_REGION26_LOW_S)
+#define PMS_DMA_REGION26_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION26_LOW_S  12
+
+/** PMS_DMA_REGION26_HIGH_REG register
+ *  Region26 end address configuration register
+ */
+#define PMS_DMA_REGION26_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xdc)
+/** PMS_DMA_REGION26_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region26.
+ */
+#define PMS_DMA_REGION26_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION26_HIGH_M  (PMS_DMA_REGION26_HIGH_V << PMS_DMA_REGION26_HIGH_S)
+#define PMS_DMA_REGION26_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION26_HIGH_S  12
+
+/** PMS_DMA_REGION27_LOW_REG register
+ *  Region27 start address configuration register
+ */
+#define PMS_DMA_REGION27_LOW_REG (DR_REG_DMA_PMS_BASE + 0xe0)
+/** PMS_DMA_REGION27_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region27.
+ */
+#define PMS_DMA_REGION27_LOW    0x000FFFFFU
+#define PMS_DMA_REGION27_LOW_M  (PMS_DMA_REGION27_LOW_V << PMS_DMA_REGION27_LOW_S)
+#define PMS_DMA_REGION27_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION27_LOW_S  12
+
+/** PMS_DMA_REGION27_HIGH_REG register
+ *  Region27 end address configuration register
+ */
+#define PMS_DMA_REGION27_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xe4)
+/** PMS_DMA_REGION27_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region27.
+ */
+#define PMS_DMA_REGION27_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION27_HIGH_M  (PMS_DMA_REGION27_HIGH_V << PMS_DMA_REGION27_HIGH_S)
+#define PMS_DMA_REGION27_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION27_HIGH_S  12
+
+/** PMS_DMA_REGION28_LOW_REG register
+ *  Region28 start address configuration register
+ */
+#define PMS_DMA_REGION28_LOW_REG (DR_REG_DMA_PMS_BASE + 0xe8)
+/** PMS_DMA_REGION28_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region28.
+ */
+#define PMS_DMA_REGION28_LOW    0x000FFFFFU
+#define PMS_DMA_REGION28_LOW_M  (PMS_DMA_REGION28_LOW_V << PMS_DMA_REGION28_LOW_S)
+#define PMS_DMA_REGION28_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION28_LOW_S  12
+
+/** PMS_DMA_REGION28_HIGH_REG register
+ *  Region28 end address configuration register
+ */
+#define PMS_DMA_REGION28_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xec)
+/** PMS_DMA_REGION28_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region28.
+ */
+#define PMS_DMA_REGION28_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION28_HIGH_M  (PMS_DMA_REGION28_HIGH_V << PMS_DMA_REGION28_HIGH_S)
+#define PMS_DMA_REGION28_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION28_HIGH_S  12
+
+/** PMS_DMA_REGION29_LOW_REG register
+ *  Region29 start address configuration register
+ */
+#define PMS_DMA_REGION29_LOW_REG (DR_REG_DMA_PMS_BASE + 0xf0)
+/** PMS_DMA_REGION29_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region29.
+ */
+#define PMS_DMA_REGION29_LOW    0x000FFFFFU
+#define PMS_DMA_REGION29_LOW_M  (PMS_DMA_REGION29_LOW_V << PMS_DMA_REGION29_LOW_S)
+#define PMS_DMA_REGION29_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION29_LOW_S  12
+
+/** PMS_DMA_REGION29_HIGH_REG register
+ *  Region29 end address configuration register
+ */
+#define PMS_DMA_REGION29_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xf4)
+/** PMS_DMA_REGION29_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region29.
+ */
+#define PMS_DMA_REGION29_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION29_HIGH_M  (PMS_DMA_REGION29_HIGH_V << PMS_DMA_REGION29_HIGH_S)
+#define PMS_DMA_REGION29_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION29_HIGH_S  12
+
+/** PMS_DMA_REGION30_LOW_REG register
+ *  Region30 start address configuration register
+ */
+#define PMS_DMA_REGION30_LOW_REG (DR_REG_DMA_PMS_BASE + 0xf8)
+/** PMS_DMA_REGION30_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region30.
+ */
+#define PMS_DMA_REGION30_LOW    0x000FFFFFU
+#define PMS_DMA_REGION30_LOW_M  (PMS_DMA_REGION30_LOW_V << PMS_DMA_REGION30_LOW_S)
+#define PMS_DMA_REGION30_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION30_LOW_S  12
+
+/** PMS_DMA_REGION30_HIGH_REG register
+ *  Region30 end address configuration register
+ */
+#define PMS_DMA_REGION30_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xfc)
+/** PMS_DMA_REGION30_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region30.
+ */
+#define PMS_DMA_REGION30_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION30_HIGH_M  (PMS_DMA_REGION30_HIGH_V << PMS_DMA_REGION30_HIGH_S)
+#define PMS_DMA_REGION30_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION30_HIGH_S  12
+
+/** PMS_DMA_REGION31_LOW_REG register
+ *  Region31 start address configuration register
+ */
+#define PMS_DMA_REGION31_LOW_REG (DR_REG_DMA_PMS_BASE + 0x100)
+/** PMS_DMA_REGION31_LOW : R/W; bitpos: [31:12]; default: 0;
+ *  Configures the high 20 bits of the start address for region31.
+ */
+#define PMS_DMA_REGION31_LOW    0x000FFFFFU
+#define PMS_DMA_REGION31_LOW_M  (PMS_DMA_REGION31_LOW_V << PMS_DMA_REGION31_LOW_S)
+#define PMS_DMA_REGION31_LOW_V  0x000FFFFFU
+#define PMS_DMA_REGION31_LOW_S  12
+
+/** PMS_DMA_REGION31_HIGH_REG register
+ *  Region31 end address configuration register
+ */
+#define PMS_DMA_REGION31_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x104)
+/** PMS_DMA_REGION31_HIGH : R/W; bitpos: [31:12]; default: 1048575;
+ *  Configures the high 20 bits of the end address for region31.
+ */
+#define PMS_DMA_REGION31_HIGH    0x000FFFFFU
+#define PMS_DMA_REGION31_HIGH_M  (PMS_DMA_REGION31_HIGH_V << PMS_DMA_REGION31_HIGH_S)
+#define PMS_DMA_REGION31_HIGH_V  0x000FFFFFU
+#define PMS_DMA_REGION31_HIGH_S  12
+
+/** PMS_DMA_GDMA_CH0_R_PMS_REG register
+ *  GDMA ch0 read permission control register
+ */
+#define PMS_DMA_GDMA_CH0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x108)
+/** PMS_DMA_GDMA_CH0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch0 to read 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GDMA_CH0_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH0_R_PMS_M  (PMS_DMA_GDMA_CH0_R_PMS_V << PMS_DMA_GDMA_CH0_R_PMS_S)
+#define PMS_DMA_GDMA_CH0_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH0_R_PMS_S  0
+
+/** PMS_DMA_GDMA_CH0_W_PMS_REG register
+ *  GDMA ch0 write permission control register
+ */
+#define PMS_DMA_GDMA_CH0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x10c)
+/** PMS_DMA_GDMA_CH0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch0 to write 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GDMA_CH0_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH0_W_PMS_M  (PMS_DMA_GDMA_CH0_W_PMS_V << PMS_DMA_GDMA_CH0_W_PMS_S)
+#define PMS_DMA_GDMA_CH0_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH0_W_PMS_S  0
+
+/** PMS_DMA_GDMA_CH1_R_PMS_REG register
+ *  GDMA ch1 read permission control register
+ */
+#define PMS_DMA_GDMA_CH1_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x110)
+/** PMS_DMA_GDMA_CH1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch1 to read 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GDMA_CH1_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH1_R_PMS_M  (PMS_DMA_GDMA_CH1_R_PMS_V << PMS_DMA_GDMA_CH1_R_PMS_S)
+#define PMS_DMA_GDMA_CH1_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH1_R_PMS_S  0
+
+/** PMS_DMA_GDMA_CH1_W_PMS_REG register
+ *  GDMA ch1 write permission control register
+ */
+#define PMS_DMA_GDMA_CH1_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x114)
+/** PMS_DMA_GDMA_CH1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch1 to write 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GDMA_CH1_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH1_W_PMS_M  (PMS_DMA_GDMA_CH1_W_PMS_V << PMS_DMA_GDMA_CH1_W_PMS_S)
+#define PMS_DMA_GDMA_CH1_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH1_W_PMS_S  0
+
+/** PMS_DMA_GDMA_CH2_R_PMS_REG register
+ *  GDMA ch2 read permission control register
+ */
+#define PMS_DMA_GDMA_CH2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x118)
+/** PMS_DMA_GDMA_CH2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch2 to read 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GDMA_CH2_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH2_R_PMS_M  (PMS_DMA_GDMA_CH2_R_PMS_V << PMS_DMA_GDMA_CH2_R_PMS_S)
+#define PMS_DMA_GDMA_CH2_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH2_R_PMS_S  0
+
+/** PMS_DMA_GDMA_CH2_W_PMS_REG register
+ *  GDMA ch2 write permission control register
+ */
+#define PMS_DMA_GDMA_CH2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x11c)
+/** PMS_DMA_GDMA_CH2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch2 to write 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GDMA_CH2_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH2_W_PMS_M  (PMS_DMA_GDMA_CH2_W_PMS_V << PMS_DMA_GDMA_CH2_W_PMS_S)
+#define PMS_DMA_GDMA_CH2_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH2_W_PMS_S  0
+
+/** PMS_DMA_GDMA_CH3_R_PMS_REG register
+ *  GDMA ch3 read permission control register
+ */
+#define PMS_DMA_GDMA_CH3_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x120)
+/** PMS_DMA_GDMA_CH3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch3 to read 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GDMA_CH3_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH3_R_PMS_M  (PMS_DMA_GDMA_CH3_R_PMS_V << PMS_DMA_GDMA_CH3_R_PMS_S)
+#define PMS_DMA_GDMA_CH3_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH3_R_PMS_S  0
+
+/** PMS_DMA_GDMA_CH3_W_PMS_REG register
+ *  GDMA ch3 write permission control register
+ */
+#define PMS_DMA_GDMA_CH3_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x124)
+/** PMS_DMA_GDMA_CH3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the permission for GDMA ch3 to write 32 address regions. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GDMA_CH3_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH3_W_PMS_M  (PMS_DMA_GDMA_CH3_W_PMS_V << PMS_DMA_GDMA_CH3_W_PMS_S)
+#define PMS_DMA_GDMA_CH3_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GDMA_CH3_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_ADC_R_PMS_REG register
+ *  GDMA-AHB ADC read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x128)
+/** PMS_DMA_AHB_PDMA_ADC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by ADC. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS_M  (PMS_DMA_AHB_PDMA_ADC_R_PMS_V << PMS_DMA_AHB_PDMA_ADC_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_ADC_W_PMS_REG register
+ *  GDMA-AHB ADC write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x12c)
+/** PMS_DMA_AHB_PDMA_ADC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by ADC. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS_M  (PMS_DMA_AHB_PDMA_ADC_W_PMS_V << PMS_DMA_AHB_PDMA_ADC_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG register
+ *  GDMA-AHB I2S0 read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x130)
+/** PMS_DMA_AHB_PDMA_I2S0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by I2S0. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_M  (PMS_DMA_AHB_PDMA_I2S0_R_PMS_V << PMS_DMA_AHB_PDMA_I2S0_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG register
+ *  GDMA-AHB I2S0 write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x134)
+/** PMS_DMA_AHB_PDMA_I2S0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by I2S0. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_M  (PMS_DMA_AHB_PDMA_I2S0_W_PMS_V << PMS_DMA_AHB_PDMA_I2S0_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG register
+ *  GDMA-AHB I2S1 read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x138)
+/** PMS_DMA_AHB_PDMA_I2S1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by I2S1. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_M  (PMS_DMA_AHB_PDMA_I2S1_R_PMS_V << PMS_DMA_AHB_PDMA_I2S1_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG register
+ *  GDMA-AHB I2S1 write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x13c)
+/** PMS_DMA_AHB_PDMA_I2S1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by I2S1. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_M  (PMS_DMA_AHB_PDMA_I2S1_W_PMS_V << PMS_DMA_AHB_PDMA_I2S1_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG register
+ *  GDMA-AHB I2S2 read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x140)
+/** PMS_DMA_AHB_PDMA_I2S2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by I2S2. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_M  (PMS_DMA_AHB_PDMA_I2S2_R_PMS_V << PMS_DMA_AHB_PDMA_I2S2_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG register
+ *  GDMA-AHB I2S2 write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x144)
+/** PMS_DMA_AHB_PDMA_I2S2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by I2S2. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_M  (PMS_DMA_AHB_PDMA_I2S2_W_PMS_V << PMS_DMA_AHB_PDMA_I2S2_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG register
+ *  GDMA-AHB I3C MST read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x148)
+/** PMS_DMA_AHB_PDMA_I3C_MST_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by I3C  master.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_M  (PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_V << PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG register
+ *  GDMA-AHB I3C MST write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x14c)
+/** PMS_DMA_AHB_PDMA_I3C_MST_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by I3C  master.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_M  (PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_V << PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG register
+ *  GDMA-AHB UHCI read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x150)
+/** PMS_DMA_AHB_PDMA_UHCI0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by UHCI. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_M  (PMS_DMA_AHB_PDMA_UHCI0_R_PMS_V << PMS_DMA_AHB_PDMA_UHCI0_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG register
+ *  GDMA-AHB UHCI write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x154)
+/** PMS_DMA_AHB_PDMA_UHCI0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by UHCI. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_M  (PMS_DMA_AHB_PDMA_UHCI0_W_PMS_V << PMS_DMA_AHB_PDMA_UHCI0_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_RMT_R_PMS_REG register
+ *  GDMA-AHB RMT read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x158)
+/** PMS_DMA_AHB_PDMA_RMT_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by RMT. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS_M  (PMS_DMA_AHB_PDMA_RMT_R_PMS_V << PMS_DMA_AHB_PDMA_RMT_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_RMT_W_PMS_REG register
+ *  GDMA-AHB RMT write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x170)
+/** PMS_DMA_AHB_PDMA_RMT_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by RMT. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS_M  (PMS_DMA_AHB_PDMA_RMT_W_PMS_V << PMS_DMA_AHB_PDMA_RMT_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG register
+ *  GDMA-AXI LCD_CAM read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x174)
+/** PMS_DMA_AXI_PDMA_LCDCAM_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by LCD_CAM. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_M  (PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_V << PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG register
+ *  GDMA-AXI LCD_CAM write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x178)
+/** PMS_DMA_AXI_PDMA_LCDCAM_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by LCD_CAM. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_M  (PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_V << PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG register
+ *  GDMA-AXI GPSPI2 read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x17c)
+/** PMS_DMA_AXI_PDMA_GPSPI2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI2. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_M  (PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_V << PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG register
+ *  GDMA-AXI GPSPI2 write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x180)
+/** PMS_DMA_AXI_PDMA_GPSPI2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI2. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_M  (PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_V << PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG register
+ *  GDMA-AXI GPSPI3 read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x184)
+/** PMS_DMA_AXI_PDMA_GPSPI3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI3. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_M  (PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_V << PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG register
+ *  AXI PDMA GPSPI3 write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x188)
+/** PMS_DMA_AXI_PDMA_GPSPI3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI3. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_M  (PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_V << PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG register
+ *  GDMA-AXI PARLIO read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x18c)
+/** PMS_DMA_AXI_PDMA_PARLIO_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by PARLIO
+ *  (Parallel IO Controller). Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_M  (PMS_DMA_AXI_PDMA_PARLIO_R_PMS_V << PMS_DMA_AXI_PDMA_PARLIO_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG register
+ *  GDMA-AXI PARLIO write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x190)
+/** PMS_DMA_AXI_PDMA_PARLIO_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by PARLIO. Bit
+ *  0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_M  (PMS_DMA_AXI_PDMA_PARLIO_W_PMS_V << PMS_DMA_AXI_PDMA_PARLIO_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_AES_R_PMS_REG register
+ *  GDMA-AXI AES read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_AES_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x194)
+/** PMS_DMA_AXI_PDMA_AES_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by AES. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_AES_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_AES_R_PMS_M  (PMS_DMA_AXI_PDMA_AES_R_PMS_V << PMS_DMA_AXI_PDMA_AES_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_AES_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_AES_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_AES_W_PMS_REG register
+ *  GDMA-AXI AES write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_AES_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x198)
+/** PMS_DMA_AXI_PDMA_AES_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by AES. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_AES_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_AES_W_PMS_M  (PMS_DMA_AXI_PDMA_AES_W_PMS_V << PMS_DMA_AXI_PDMA_AES_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_AES_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_AES_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_SHA_R_PMS_REG register
+ *  GDMA-AXI SHA read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x19c)
+/** PMS_DMA_AXI_PDMA_SHA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by SHA. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS_M  (PMS_DMA_AXI_PDMA_SHA_R_PMS_V << PMS_DMA_AXI_PDMA_SHA_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_SHA_W_PMS_REG register
+ *  GDMA-AXI SHA write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x1a0)
+/** PMS_DMA_AXI_PDMA_SHA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by SHA. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS_M  (PMS_DMA_AXI_PDMA_SHA_W_PMS_V << PMS_DMA_AXI_PDMA_SHA_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS_S  0
+
+/** PMS_DMA_DMA2D_JPEG_PMS_R_REG register
+ *  2D-DMA JPEG read permission control register
+ */
+#define PMS_DMA_DMA2D_JPEG_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1a4)
+/** PMS_DMA_DMA2D_JPEG_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to read 32 address ranges requested by JPEG. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_DMA2D_JPEG_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_JPEG_R_PMS_M  (PMS_DMA_DMA2D_JPEG_R_PMS_V << PMS_DMA_DMA2D_JPEG_R_PMS_S)
+#define PMS_DMA_DMA2D_JPEG_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_JPEG_R_PMS_S  0
+
+/** PMS_DMA_DMA2D_JPEG_PMS_W_REG register
+ *  2D-DMA JPEG write permission control register
+ */
+#define PMS_DMA_DMA2D_JPEG_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1a8)
+/** PMS_DMA_DMA2D_JPEG_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to write 32 address ranges requested by JPEG. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_DMA2D_JPEG_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_JPEG_W_PMS_M  (PMS_DMA_DMA2D_JPEG_W_PMS_V << PMS_DMA_DMA2D_JPEG_W_PMS_S)
+#define PMS_DMA_DMA2D_JPEG_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_JPEG_W_PMS_S  0
+
+/** PMS_DMA_USB_PMS_R_REG register
+ *  High-speed USB 2.0 OTG read permission control register
+ */
+#define PMS_DMA_USB_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ac)
+/** PMS_DMA_USB_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for high-speed USB 2.0 OTG to access 32 address ranges.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_USB_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_USB_R_PMS_M  (PMS_DMA_USB_R_PMS_V << PMS_DMA_USB_R_PMS_S)
+#define PMS_DMA_USB_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_USB_R_PMS_S  0
+
+/** PMS_DMA_USB_PMS_W_REG register
+ *  High-speed USB 2.0 OTG write permission control register
+ */
+#define PMS_DMA_USB_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1b0)
+/** PMS_DMA_USB_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for high-speed USB 2.0 OTG to access 32 address ranges.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_USB_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_USB_W_PMS_M  (PMS_DMA_USB_W_PMS_V << PMS_DMA_USB_W_PMS_S)
+#define PMS_DMA_USB_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_USB_W_PMS_S  0
+
+/** PMS_DMA_GMAC_PMS_R_REG register
+ *  EMAC read permission control register
+ */
+#define PMS_DMA_GMAC_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1b4)
+/** PMS_DMA_GMAC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for EMAC to access 32 address ranges. Bit 0 corresponds
+ *  to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_GMAC_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_GMAC_R_PMS_M  (PMS_DMA_GMAC_R_PMS_V << PMS_DMA_GMAC_R_PMS_S)
+#define PMS_DMA_GMAC_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GMAC_R_PMS_S  0
+
+/** PMS_DMA_GMAC_PMS_W_REG register
+ *  EMAC write permission control register
+ */
+#define PMS_DMA_GMAC_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1b8)
+/** PMS_DMA_GMAC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for EMAC to access 32 address ranges. Bit 0 corresponds
+ *  to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_GMAC_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_GMAC_W_PMS_M  (PMS_DMA_GMAC_W_PMS_V << PMS_DMA_GMAC_W_PMS_S)
+#define PMS_DMA_GMAC_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_GMAC_W_PMS_S  0
+
+/** PMS_DMA_SDMMC_PMS_R_REG register
+ *  SDMMC read permission control register
+ */
+#define PMS_DMA_SDMMC_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1bc)
+/** PMS_DMA_SDMMC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for SDMMC to access 32 address ranges. Bit 0 corresponds
+ *  to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_SDMMC_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_SDMMC_R_PMS_M  (PMS_DMA_SDMMC_R_PMS_V << PMS_DMA_SDMMC_R_PMS_S)
+#define PMS_DMA_SDMMC_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_SDMMC_R_PMS_S  0
+
+/** PMS_DMA_SDMMC_PMS_W_REG register
+ *  SDMMC write permission control register
+ */
+#define PMS_DMA_SDMMC_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1c0)
+/** PMS_DMA_SDMMC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for SDMMC to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_SDMMC_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_SDMMC_W_PMS_M  (PMS_DMA_SDMMC_W_PMS_V << PMS_DMA_SDMMC_W_PMS_S)
+#define PMS_DMA_SDMMC_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_SDMMC_W_PMS_S  0
+
+/** PMS_DMA_USBOTG11_PMS_R_REG register
+ *  Full-speed USB 2.0 OTG full-speed read permission control register
+ */
+#define PMS_DMA_USBOTG11_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1c4)
+/** PMS_DMA_USBOTG11_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for full-speed USB 2.0 OTG to access 32 address ranges.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_USBOTG11_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_USBOTG11_R_PMS_M  (PMS_DMA_USBOTG11_R_PMS_V << PMS_DMA_USBOTG11_R_PMS_S)
+#define PMS_DMA_USBOTG11_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_USBOTG11_R_PMS_S  0
+
+/** PMS_DMA_USBOTG11_PMS_W_REG register
+ *  Full-speed USB 2.0 OTG full-speed write permission control register
+ */
+#define PMS_DMA_USBOTG11_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1c8)
+/** PMS_DMA_USBOTG11_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for full-speed USB 2.0 OTG to access 32 address ranges.
+ *  Bit 0 corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_USBOTG11_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_USBOTG11_W_PMS_M  (PMS_DMA_USBOTG11_W_PMS_V << PMS_DMA_USBOTG11_W_PMS_S)
+#define PMS_DMA_USBOTG11_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_USBOTG11_W_PMS_S  0
+
+/** PMS_DMA_TRACE0_PMS_R_REG register
+ *  TRACE0 read permission control register
+ */
+#define PMS_DMA_TRACE0_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1cc)
+/** PMS_DMA_TRACE0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for TRACE0 to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_TRACE0_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_TRACE0_R_PMS_M  (PMS_DMA_TRACE0_R_PMS_V << PMS_DMA_TRACE0_R_PMS_S)
+#define PMS_DMA_TRACE0_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_TRACE0_R_PMS_S  0
+
+/** PMS_DMA_TRACE0_PMS_W_REG register
+ *  TRACE0 write permission control register
+ */
+#define PMS_DMA_TRACE0_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1d0)
+/** PMS_DMA_TRACE0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for TRACE0 to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_TRACE0_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_TRACE0_W_PMS_M  (PMS_DMA_TRACE0_W_PMS_V << PMS_DMA_TRACE0_W_PMS_S)
+#define PMS_DMA_TRACE0_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_TRACE0_W_PMS_S  0
+
+/** PMS_DMA_TRACE1_PMS_R_REG register
+ *  TRACE1 read permission control register
+ */
+#define PMS_DMA_TRACE1_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1d4)
+/** PMS_DMA_TRACE1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for TRACE1 to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_TRACE1_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_TRACE1_R_PMS_M  (PMS_DMA_TRACE1_R_PMS_V << PMS_DMA_TRACE1_R_PMS_S)
+#define PMS_DMA_TRACE1_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_TRACE1_R_PMS_S  0
+
+/** PMS_DMA_TRACE1_PMS_W_REG register
+ *  TRACE1 write permission control register
+ */
+#define PMS_DMA_TRACE1_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1d8)
+/** PMS_DMA_TRACE1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for TRACE1 to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_TRACE1_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_TRACE1_W_PMS_M  (PMS_DMA_TRACE1_W_PMS_V << PMS_DMA_TRACE1_W_PMS_S)
+#define PMS_DMA_TRACE1_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_TRACE1_W_PMS_S  0
+
+/** PMS_DMA_L2MEM_MON_PMS_R_REG register
+ *  L2MEM Monitor read permission control register
+ */
+#define PMS_DMA_L2MEM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1dc)
+/** PMS_DMA_L2MEM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for L2MEM MON. Each bit corresponds to a region. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_L2MEM_MON_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_L2MEM_MON_R_PMS_M  (PMS_DMA_L2MEM_MON_R_PMS_V << PMS_DMA_L2MEM_MON_R_PMS_S)
+#define PMS_DMA_L2MEM_MON_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_L2MEM_MON_R_PMS_S  0
+
+/** PMS_DMA_L2MEM_MON_PMS_W_REG register
+ *  L2MEM Monitor write permission control register
+ */
+#define PMS_DMA_L2MEM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e0)
+/** PMS_DMA_L2MEM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for L2MEM monitor to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_L2MEM_MON_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_L2MEM_MON_W_PMS_M  (PMS_DMA_L2MEM_MON_W_PMS_V << PMS_DMA_L2MEM_MON_W_PMS_S)
+#define PMS_DMA_L2MEM_MON_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_L2MEM_MON_W_PMS_S  0
+
+/** PMS_DMA_SPM_MON_PMS_R_REG register
+ *  SPM Monitor read permission control register
+ */
+#define PMS_DMA_SPM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1e4)
+/** PMS_DMA_SPM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for SPM MON. Each bit corresponds to a region. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_SPM_MON_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_SPM_MON_R_PMS_M  (PMS_DMA_SPM_MON_R_PMS_V << PMS_DMA_SPM_MON_R_PMS_S)
+#define PMS_DMA_SPM_MON_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_SPM_MON_R_PMS_S  0
+
+/** PMS_DMA_SPM_MON_PMS_W_REG register
+ *  SPM Monitor write permission control register
+ */
+#define PMS_DMA_SPM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e8)
+/** PMS_DMA_SPM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for SPM monitor to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_SPM_MON_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_SPM_MON_W_PMS_M  (PMS_DMA_SPM_MON_W_PMS_V << PMS_DMA_SPM_MON_W_PMS_S)
+#define PMS_DMA_SPM_MON_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_SPM_MON_W_PMS_S  0
+
+/** PMS_DMA_H264_PMS_R_REG register
+ *  H264 DMA read permission control register
+ */
+#define PMS_DMA_H264_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1fc)
+/** PMS_DMA_H264_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures read permission for H264 DMA to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_H264_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_H264_R_PMS_M  (PMS_DMA_H264_R_PMS_V << PMS_DMA_H264_R_PMS_S)
+#define PMS_DMA_H264_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_H264_R_PMS_S  0
+
+/** PMS_DMA_H264_PMS_W_REG register
+ *  H264 DMA write permission control register
+ */
+#define PMS_DMA_H264_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x200)
+/** PMS_DMA_H264_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures write permission for H264 DMA to access 32 address ranges. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_H264_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_H264_W_PMS_M  (PMS_DMA_H264_W_PMS_V << PMS_DMA_H264_W_PMS_S)
+#define PMS_DMA_H264_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_H264_W_PMS_S  0
+
+/** PMS_DMA_DMA2D_PPA_PMS_R_REG register
+ *  2D-DMA PPA read permission control register
+ */
+#define PMS_DMA_DMA2D_PPA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x204)
+/** PMS_DMA_DMA2D_PPA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to read 32 address ranges requested by PPA
+ *  (Pixel-Processing Accelerator). Bit 0 corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_DMA2D_PPA_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_PPA_R_PMS_M  (PMS_DMA_DMA2D_PPA_R_PMS_V << PMS_DMA_DMA2D_PPA_R_PMS_S)
+#define PMS_DMA_DMA2D_PPA_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_PPA_R_PMS_S  0
+
+/** PMS_DMA_DMA2D_PPA_PMS_W_REG register
+ *  2D-DMA PPA write permission control register
+ */
+#define PMS_DMA_DMA2D_PPA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x208)
+/** PMS_DMA_DMA2D_PPA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to write 32 address ranges requested by PPA. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_DMA2D_PPA_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_PPA_W_PMS_M  (PMS_DMA_DMA2D_PPA_W_PMS_V << PMS_DMA_DMA2D_PPA_W_PMS_S)
+#define PMS_DMA_DMA2D_PPA_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_PPA_W_PMS_S  0
+
+/** PMS_DMA_DMA2D_DUMMY_PMS_R_REG register
+ *  2D-DMA dummy read permission control register
+ */
+#define PMS_DMA_DMA2D_DUMMY_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x20c)
+/** PMS_DMA_DMA2D_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to read 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_DMA2D_DUMMY_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_DUMMY_R_PMS_M  (PMS_DMA_DMA2D_DUMMY_R_PMS_V << PMS_DMA_DMA2D_DUMMY_R_PMS_S)
+#define PMS_DMA_DMA2D_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_DUMMY_R_PMS_S  0
+
+/** PMS_DMA_DMA2D_DUMMY_PMS_W_REG register
+ *  2D-DMA dummy write permission control register
+ */
+#define PMS_DMA_DMA2D_DUMMY_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x210)
+/** PMS_DMA_DMA2D_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures 2D-DMA permission to write 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_DMA2D_DUMMY_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_DMA2D_DUMMY_W_PMS_M  (PMS_DMA_DMA2D_DUMMY_W_PMS_V << PMS_DMA_DMA2D_DUMMY_W_PMS_S)
+#define PMS_DMA_DMA2D_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_DMA2D_DUMMY_W_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG register
+ *  GDMA-AHB dummy read permission control register
+ */
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x214)
+/** PMS_DMA_AHB_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to read 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_M  (PMS_DMA_AHB_PDMA_DUMMY_R_PMS_V << PMS_DMA_AHB_PDMA_DUMMY_R_PMS_S)
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_S  0
+
+/** PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG register
+ *  GDMA-AHB dummy write permission control register
+ */
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x218)
+/** PMS_DMA_AHB_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AHB permission to write 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_M  (PMS_DMA_AHB_PDMA_DUMMY_W_PMS_V << PMS_DMA_AHB_PDMA_DUMMY_W_PMS_S)
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG register
+ *  GDMA-AXI dummy read permission control register
+ */
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x21c)
+/** PMS_DMA_AXI_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to read 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable read permission.
+ *  1: Enable read permission.
+ */
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_M  (PMS_DMA_AXI_PDMA_DUMMY_R_PMS_V << PMS_DMA_AXI_PDMA_DUMMY_R_PMS_S)
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_S  0
+
+/** PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG register
+ *  GDMA-AXI dummy write permission control register
+ */
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x220)
+/** PMS_DMA_AXI_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures GDMA-AXI permission to write 32 address ranges requested by Dummy. Bit 0
+ *  corresponds to region0, and so on.
+ *  0: Disable write permission.
+ *  1: Enable write permission.
+ */
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS    0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_M  (PMS_DMA_AXI_PDMA_DUMMY_W_PMS_V << PMS_DMA_AXI_PDMA_DUMMY_W_PMS_S)
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_V  0xFFFFFFFFU
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dma_pms_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/dma_pms_struct.h
new file mode 100644
index 0000000000..4ccb8898e6
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dma_pms_struct.h
@@ -0,0 +1,1919 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Tee version register. */
+/** Type of date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 539165460;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_dma_date_reg_t;
+
+
+/** Group: Tee regbank clock gating control register. */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_dma_clk_en_reg_t;
+
+
+/** Group: Tee region configuration registers. */
+/** Type of region0_low register
+ *  Region0 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region0_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region0 address low.
+         */
+        uint32_t region0_low:20;
+    };
+    uint32_t val;
+} tee_dma_region0_low_reg_t;
+
+/** Type of region0_high register
+ *  Region0 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region0_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region0 address high.
+         */
+        uint32_t region0_high:20;
+    };
+    uint32_t val;
+} tee_dma_region0_high_reg_t;
+
+/** Type of region1_low register
+ *  Region1 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region1_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region1 address low.
+         */
+        uint32_t region1_low:20;
+    };
+    uint32_t val;
+} tee_dma_region1_low_reg_t;
+
+/** Type of region1_high register
+ *  Region1 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region1_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region1 address high.
+         */
+        uint32_t region1_high:20;
+    };
+    uint32_t val;
+} tee_dma_region1_high_reg_t;
+
+/** Type of region2_low register
+ *  Region2 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region2_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region2 address low.
+         */
+        uint32_t region2_low:20;
+    };
+    uint32_t val;
+} tee_dma_region2_low_reg_t;
+
+/** Type of region2_high register
+ *  Region2 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region2_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region2 address high.
+         */
+        uint32_t region2_high:20;
+    };
+    uint32_t val;
+} tee_dma_region2_high_reg_t;
+
+/** Type of region3_low register
+ *  Region3 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region3_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region3 address low.
+         */
+        uint32_t region3_low:20;
+    };
+    uint32_t val;
+} tee_dma_region3_low_reg_t;
+
+/** Type of region3_high register
+ *  Region3 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region3_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region3 address high.
+         */
+        uint32_t region3_high:20;
+    };
+    uint32_t val;
+} tee_dma_region3_high_reg_t;
+
+/** Type of region4_low register
+ *  Region4 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region4_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region4 address low.
+         */
+        uint32_t region4_low:20;
+    };
+    uint32_t val;
+} tee_dma_region4_low_reg_t;
+
+/** Type of region4_high register
+ *  Region4 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region4_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region4 address high.
+         */
+        uint32_t region4_high:20;
+    };
+    uint32_t val;
+} tee_dma_region4_high_reg_t;
+
+/** Type of region5_low register
+ *  Region5 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region5_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region5 address low.
+         */
+        uint32_t region5_low:20;
+    };
+    uint32_t val;
+} tee_dma_region5_low_reg_t;
+
+/** Type of region5_high register
+ *  Region5 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region5_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region5 address high.
+         */
+        uint32_t region5_high:20;
+    };
+    uint32_t val;
+} tee_dma_region5_high_reg_t;
+
+/** Type of region6_low register
+ *  Region6 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region6_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region6 address low.
+         */
+        uint32_t region6_low:20;
+    };
+    uint32_t val;
+} tee_dma_region6_low_reg_t;
+
+/** Type of region6_high register
+ *  Region6 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region6_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region6 address high.
+         */
+        uint32_t region6_high:20;
+    };
+    uint32_t val;
+} tee_dma_region6_high_reg_t;
+
+/** Type of region7_low register
+ *  Region7 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region7_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region7 address low.
+         */
+        uint32_t region7_low:20;
+    };
+    uint32_t val;
+} tee_dma_region7_low_reg_t;
+
+/** Type of region7_high register
+ *  Region7 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region7_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region7 address high.
+         */
+        uint32_t region7_high:20;
+    };
+    uint32_t val;
+} tee_dma_region7_high_reg_t;
+
+/** Type of region8_low register
+ *  Region8 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region8_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region8 address low.
+         */
+        uint32_t region8_low:20;
+    };
+    uint32_t val;
+} tee_dma_region8_low_reg_t;
+
+/** Type of region8_high register
+ *  Region8 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region8_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region8 address high.
+         */
+        uint32_t region8_high:20;
+    };
+    uint32_t val;
+} tee_dma_region8_high_reg_t;
+
+/** Type of region9_low register
+ *  Region9 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region9_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region9 address low.
+         */
+        uint32_t region9_low:20;
+    };
+    uint32_t val;
+} tee_dma_region9_low_reg_t;
+
+/** Type of region9_high register
+ *  Region9 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region9_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region9 address high.
+         */
+        uint32_t region9_high:20;
+    };
+    uint32_t val;
+} tee_dma_region9_high_reg_t;
+
+/** Type of region10_low register
+ *  Region10 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region10_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region10 address low.
+         */
+        uint32_t region10_low:20;
+    };
+    uint32_t val;
+} tee_dma_region10_low_reg_t;
+
+/** Type of region10_high register
+ *  Region10 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region10_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region10 address high.
+         */
+        uint32_t region10_high:20;
+    };
+    uint32_t val;
+} tee_dma_region10_high_reg_t;
+
+/** Type of region11_low register
+ *  Region11 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region11_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region11 address low.
+         */
+        uint32_t region11_low:20;
+    };
+    uint32_t val;
+} tee_dma_region11_low_reg_t;
+
+/** Type of region11_high register
+ *  Region11 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region11_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region11 address high.
+         */
+        uint32_t region11_high:20;
+    };
+    uint32_t val;
+} tee_dma_region11_high_reg_t;
+
+/** Type of region12_low register
+ *  Region12 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region12_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region12 address low.
+         */
+        uint32_t region12_low:20;
+    };
+    uint32_t val;
+} tee_dma_region12_low_reg_t;
+
+/** Type of region12_high register
+ *  Region12 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region12_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region12 address high.
+         */
+        uint32_t region12_high:20;
+    };
+    uint32_t val;
+} tee_dma_region12_high_reg_t;
+
+/** Type of region13_low register
+ *  Region13 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region13_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region13 address low.
+         */
+        uint32_t region13_low:20;
+    };
+    uint32_t val;
+} tee_dma_region13_low_reg_t;
+
+/** Type of region13_high register
+ *  Region13 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region13_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region13 address high.
+         */
+        uint32_t region13_high:20;
+    };
+    uint32_t val;
+} tee_dma_region13_high_reg_t;
+
+/** Type of region14_low register
+ *  Region14 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region14_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region14 address low.
+         */
+        uint32_t region14_low:20;
+    };
+    uint32_t val;
+} tee_dma_region14_low_reg_t;
+
+/** Type of region14_high register
+ *  Region14 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region14_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region14 address high.
+         */
+        uint32_t region14_high:20;
+    };
+    uint32_t val;
+} tee_dma_region14_high_reg_t;
+
+/** Type of region15_low register
+ *  Region15 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region15_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region15 address low.
+         */
+        uint32_t region15_low:20;
+    };
+    uint32_t val;
+} tee_dma_region15_low_reg_t;
+
+/** Type of region15_high register
+ *  Region15 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region15_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region15 address high.
+         */
+        uint32_t region15_high:20;
+    };
+    uint32_t val;
+} tee_dma_region15_high_reg_t;
+
+/** Type of region16_low register
+ *  Region16 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region16_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region16 address low.
+         */
+        uint32_t region16_low:20;
+    };
+    uint32_t val;
+} tee_dma_region16_low_reg_t;
+
+/** Type of region16_high register
+ *  Region16 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region16_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region16 address high.
+         */
+        uint32_t region16_high:20;
+    };
+    uint32_t val;
+} tee_dma_region16_high_reg_t;
+
+/** Type of region17_low register
+ *  Region17 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region17_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region17 address low.
+         */
+        uint32_t region17_low:20;
+    };
+    uint32_t val;
+} tee_dma_region17_low_reg_t;
+
+/** Type of region17_high register
+ *  Region17 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region17_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region17 address high.
+         */
+        uint32_t region17_high:20;
+    };
+    uint32_t val;
+} tee_dma_region17_high_reg_t;
+
+/** Type of region18_low register
+ *  Region18 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region18_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region18 address low.
+         */
+        uint32_t region18_low:20;
+    };
+    uint32_t val;
+} tee_dma_region18_low_reg_t;
+
+/** Type of region18_high register
+ *  Region18 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region18_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region18 address high.
+         */
+        uint32_t region18_high:20;
+    };
+    uint32_t val;
+} tee_dma_region18_high_reg_t;
+
+/** Type of region19_low register
+ *  Region19 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region19_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region19 address low.
+         */
+        uint32_t region19_low:20;
+    };
+    uint32_t val;
+} tee_dma_region19_low_reg_t;
+
+/** Type of region19_high register
+ *  Region19 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region19_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region19 address high.
+         */
+        uint32_t region19_high:20;
+    };
+    uint32_t val;
+} tee_dma_region19_high_reg_t;
+
+/** Type of region20_low register
+ *  Region20 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region20_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region20 address low.
+         */
+        uint32_t region20_low:20;
+    };
+    uint32_t val;
+} tee_dma_region20_low_reg_t;
+
+/** Type of region20_high register
+ *  Region20 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region20_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region20 address high.
+         */
+        uint32_t region20_high:20;
+    };
+    uint32_t val;
+} tee_dma_region20_high_reg_t;
+
+/** Type of region21_low register
+ *  Region21 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region21_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region21 address low.
+         */
+        uint32_t region21_low:20;
+    };
+    uint32_t val;
+} tee_dma_region21_low_reg_t;
+
+/** Type of region21_high register
+ *  Region21 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region21_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region21 address high.
+         */
+        uint32_t region21_high:20;
+    };
+    uint32_t val;
+} tee_dma_region21_high_reg_t;
+
+/** Type of region22_low register
+ *  Region22 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region22_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region22 address low.
+         */
+        uint32_t region22_low:20;
+    };
+    uint32_t val;
+} tee_dma_region22_low_reg_t;
+
+/** Type of region22_high register
+ *  Region22 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region22_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region22 address high.
+         */
+        uint32_t region22_high:20;
+    };
+    uint32_t val;
+} tee_dma_region22_high_reg_t;
+
+/** Type of region23_low register
+ *  Region23 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region23_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region23 address low.
+         */
+        uint32_t region23_low:20;
+    };
+    uint32_t val;
+} tee_dma_region23_low_reg_t;
+
+/** Type of region23_high register
+ *  Region23 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region23_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region23 address high.
+         */
+        uint32_t region23_high:20;
+    };
+    uint32_t val;
+} tee_dma_region23_high_reg_t;
+
+/** Type of region24_low register
+ *  Region24 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region24_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region24 address low.
+         */
+        uint32_t region24_low:20;
+    };
+    uint32_t val;
+} tee_dma_region24_low_reg_t;
+
+/** Type of region24_high register
+ *  Region24 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region24_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region24 address high.
+         */
+        uint32_t region24_high:20;
+    };
+    uint32_t val;
+} tee_dma_region24_high_reg_t;
+
+/** Type of region25_low register
+ *  Region25 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region25_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region25 address low.
+         */
+        uint32_t region25_low:20;
+    };
+    uint32_t val;
+} tee_dma_region25_low_reg_t;
+
+/** Type of region25_high register
+ *  Region25 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region25_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region25 address high.
+         */
+        uint32_t region25_high:20;
+    };
+    uint32_t val;
+} tee_dma_region25_high_reg_t;
+
+/** Type of region26_low register
+ *  Region26 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region26_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region26 address low.
+         */
+        uint32_t region26_low:20;
+    };
+    uint32_t val;
+} tee_dma_region26_low_reg_t;
+
+/** Type of region26_high register
+ *  Region26 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region26_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region26 address high.
+         */
+        uint32_t region26_high:20;
+    };
+    uint32_t val;
+} tee_dma_region26_high_reg_t;
+
+/** Type of region27_low register
+ *  Region27 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region27_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region27 address low.
+         */
+        uint32_t region27_low:20;
+    };
+    uint32_t val;
+} tee_dma_region27_low_reg_t;
+
+/** Type of region27_high register
+ *  Region27 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region27_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region27 address high.
+         */
+        uint32_t region27_high:20;
+    };
+    uint32_t val;
+} tee_dma_region27_high_reg_t;
+
+/** Type of region28_low register
+ *  Region28 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region28_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region28 address low.
+         */
+        uint32_t region28_low:20;
+    };
+    uint32_t val;
+} tee_dma_region28_low_reg_t;
+
+/** Type of region28_high register
+ *  Region28 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region28_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region28 address high.
+         */
+        uint32_t region28_high:20;
+    };
+    uint32_t val;
+} tee_dma_region28_high_reg_t;
+
+/** Type of region29_low register
+ *  Region29 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region29_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region29 address low.
+         */
+        uint32_t region29_low:20;
+    };
+    uint32_t val;
+} tee_dma_region29_low_reg_t;
+
+/** Type of region29_high register
+ *  Region29 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region29_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region29 address high.
+         */
+        uint32_t region29_high:20;
+    };
+    uint32_t val;
+} tee_dma_region29_high_reg_t;
+
+/** Type of region30_low register
+ *  Region30 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region30_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region30 address low.
+         */
+        uint32_t region30_low:20;
+    };
+    uint32_t val;
+} tee_dma_region30_low_reg_t;
+
+/** Type of region30_high register
+ *  Region30 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region30_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region30 address high.
+         */
+        uint32_t region30_high:20;
+    };
+    uint32_t val;
+} tee_dma_region30_high_reg_t;
+
+/** Type of region31_low register
+ *  Region31 address low register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region31_low : R/W; bitpos: [31:12]; default: 0;
+         *  Region31 address low.
+         */
+        uint32_t region31_low:20;
+    };
+    uint32_t val;
+} tee_dma_region31_low_reg_t;
+
+/** Type of region31_high register
+ *  Region31 address high register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** region31_high : R/W; bitpos: [31:12]; default: 1048575;
+         *  Region31 address high.
+         */
+        uint32_t region31_high:20;
+    };
+    uint32_t val;
+} tee_dma_region31_high_reg_t;
+
+
+/** Group: Tee permission control registers. */
+/** Type of gmda_ch0_r_pms register
+ *  GDMA ch0 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch0_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch0 read permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch0_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch0_r_pms_reg_t;
+
+/** Type of gmda_ch0_w_pms register
+ *  GDMA ch0 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch0_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch0 write permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch0_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch0_w_pms_reg_t;
+
+/** Type of gmda_ch1_r_pms register
+ *  GDMA ch1 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch1_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch1 read permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch1_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch1_r_pms_reg_t;
+
+/** Type of gmda_ch1_w_pms register
+ *  GDMA ch1 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch1_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch1 write permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch1_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch1_w_pms_reg_t;
+
+/** Type of gmda_ch2_r_pms register
+ *  GDMA ch2 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch2_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch2 read permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch2_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch2_r_pms_reg_t;
+
+/** Type of gmda_ch2_w_pms register
+ *  GDMA ch2 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch2_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch2 write permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch2_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch2_w_pms_reg_t;
+
+/** Type of gmda_ch3_r_pms register
+ *  GDMA ch3 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch3_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch3 read permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch3_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch3_r_pms_reg_t;
+
+/** Type of gmda_ch3_w_pms register
+ *  GDMA ch3 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gdma_ch3_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GDMA ch3 write permission control, each bit corresponds to a region.
+         */
+        uint32_t gdma_ch3_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmda_ch3_w_pms_reg_t;
+
+/** Type of ahb_pdma_adc_r_pms register
+ *  AHB PDMA adc read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_adc_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA adc read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_adc_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_adc_r_pms_reg_t;
+
+/** Type of ahb_pdma_adc_w_pms register
+ *  AHB PDMA adc write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_adc_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA adc write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_adc_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_adc_w_pms_reg_t;
+
+/** Type of ahb_pdma_i2s0_r_pms register
+ *  AHB PDMA i2s0 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s0_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s0 read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s0_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s0_r_pms_reg_t;
+
+/** Type of ahb_pdma_i2s0_w_pms register
+ *  AHB PDMA i2s0 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s0_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s0 write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s0_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s0_w_pms_reg_t;
+
+/** Type of ahb_pdma_i2s1_r_pms register
+ *  AHB PDMA i2s1 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s1_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s1 read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s1_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s1_r_pms_reg_t;
+
+/** Type of ahb_pdma_i2s1_w_pms register
+ *  AHB PDMA i2s1 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s1_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s1 write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s1_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s1_w_pms_reg_t;
+
+/** Type of ahb_pdma_i2s2_r_pms register
+ *  AHB PDMA i2s2 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s2_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s2 read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s2_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s2_r_pms_reg_t;
+
+/** Type of ahb_pdma_i2s2_w_pms register
+ *  AHB PDMA i2s2 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i2s2_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i2s2 write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i2s2_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i2s2_w_pms_reg_t;
+
+/** Type of ahb_pdma_i3c_mst_r_pms register
+ *  AHB PDMA i3s mst read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i3c_mst_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i3c mst read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i3c_mst_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i3c_mst_r_pms_reg_t;
+
+/** Type of ahb_pdma_i3c_mst_w_pms register
+ *  AHB PDMA i3c mst  write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_i3c_mst_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA i3c mst  write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_i3c_mst_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_i3c_mst_w_pms_reg_t;
+
+/** Type of ahb_pdma_uhci0_r_pms register
+ *  AHB PDMA uhci0 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_uhci0_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA uhci0 read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_uhci0_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_uhci0_r_pms_reg_t;
+
+/** Type of ahb_pdma_uhci0_w_pms register
+ *  AHB PDMA uhci0 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_uhci0_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA uhci0 write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_uhci0_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_uhci0_w_pms_reg_t;
+
+/** Type of ahb_pdma_rmt_r_pms register
+ *  AHB PDMA rmt read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_rmt_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA rmt read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_rmt_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_rmt_r_pms_reg_t;
+
+/** Type of ahb_pdma_rmt_w_pms register
+ *  AHB PDMA rmt write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_rmt_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA rmt write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_rmt_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_rmt_w_pms_reg_t;
+
+/** Type of axi_pdma_lcdcam_r_pms register
+ *  AXI PDMA lcdcam read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_lcdcam_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA lcdcam read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_lcdcam_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_lcdcam_r_pms_reg_t;
+
+/** Type of axi_pdma_lcdcam_w_pms register
+ *  AXI PDMA lcdcam write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_lcdcam_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA lcdcam write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_lcdcam_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_lcdcam_w_pms_reg_t;
+
+/** Type of axi_pdma_gpspi2_r_pms register
+ *  AXI PDMA gpspi2 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_gpspi2_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA gpspi2 read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_gpspi2_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_gpspi2_r_pms_reg_t;
+
+/** Type of axi_pdma_gpspi2_w_pms register
+ *  AXI PDMA gpspi2 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_gpspi2_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA gpspi2 write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_gpspi2_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_gpspi2_w_pms_reg_t;
+
+/** Type of axi_pdma_gpspi3_r_pms register
+ *  AXI PDMA gpspi3 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_gpspi3_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA gpspi3 read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_gpspi3_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_gpspi3_r_pms_reg_t;
+
+/** Type of axi_pdma_gpspi3_w_pms register
+ *  AXI PDMA gpspi3 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_gpspi3_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA gpspi3 write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_gpspi3_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_gpspi3_w_pms_reg_t;
+
+/** Type of axi_pdma_parlio_r_pms register
+ *  AXI PDMA parl io read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_parlio_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA parl io read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_parlio_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_parlio_r_pms_reg_t;
+
+/** Type of axi_pdma_parlio_w_pms register
+ *  AXI PDMA parl io write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_parlio_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA parl io write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_parlio_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_parlio_w_pms_reg_t;
+
+/** Type of axi_pdma_aes_r_pms register
+ *  AXI PDMA aes read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_aes_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA aes read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_aes_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_aes_r_pms_reg_t;
+
+/** Type of axi_pdma_aes_w_pms register
+ *  AXI PDMA aes write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_aes_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA aes write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_aes_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_aes_w_pms_reg_t;
+
+/** Type of axi_pdma_sha_r_pms register
+ *  AXI PDMA sha read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_sha_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA sha read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_sha_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_sha_r_pms_reg_t;
+
+/** Type of axi_pdma_sha_w_pms register
+ *  AXI PDMA sha write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_sha_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA sha write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_sha_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_sha_w_pms_reg_t;
+
+/** Type of dma2d_jpeg_pms_r register
+ *  DMA2D JPEG read permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_jpeg_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D JPEG read permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_jpeg_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_jpeg_pms_r_reg_t;
+
+/** Type of dma2d_jpeg_pms_w register
+ *  DMA2D JPEG write permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_jpeg_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D  JPEG write permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_jpeg_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_jpeg_pms_w_reg_t;
+
+/** Type of usb_pms_r register
+ *  USB read permission control registers.
+ */
+typedef union {
+    struct {
+        /** usb_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  USB read permission control, each bit corresponds to a region.
+         */
+        uint32_t usb_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_usb_pms_r_reg_t;
+
+/** Type of usb_pms_w register
+ *  USB write permission control registers.
+ */
+typedef union {
+    struct {
+        /** usb_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  USB write permission control, each bit corresponds to a region.
+         */
+        uint32_t usb_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_usb_pms_w_reg_t;
+
+/** Type of gmac_pms_r register
+ *  GMAC read permission control registers.
+ */
+typedef union {
+    struct {
+        /** gmac_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GMAC read permission control, each bit corresponds to a region.
+         */
+        uint32_t gmac_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmac_pms_r_reg_t;
+
+/** Type of gmac_pms_w register
+ *  GMAC write permission control registers.
+ */
+typedef union {
+    struct {
+        /** gmac_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GMAC write permission control, each bit corresponds to a region.
+         */
+        uint32_t gmac_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_gmac_pms_w_reg_t;
+
+/** Type of sdmmc_pms_r register
+ *  SDMMC read permission control registers.
+ */
+typedef union {
+    struct {
+        /** sdmmc_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  SDMMC read permission control, each bit corresponds to a region.
+         */
+        uint32_t sdmmc_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_sdmmc_pms_r_reg_t;
+
+/** Type of sdmmc_pms_w register
+ *  SDMMC write permission control registers.
+ */
+typedef union {
+    struct {
+        /** sdmmc_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  SDMMC write permission control, each bit corresponds to a region.
+         */
+        uint32_t sdmmc_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_sdmmc_pms_w_reg_t;
+
+/** Type of usbotg11_pms_r register
+ *  USBOTG11 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** usbotg11_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  USBOTG11 read permission control, each bit corresponds to a region.
+         */
+        uint32_t usbotg11_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_usbotg11_pms_r_reg_t;
+
+/** Type of usbotg11_pms_w register
+ *  USBOTG11 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** usbotg11_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  USBOTG11 write permission control, each bit corresponds to a region.
+         */
+        uint32_t usbotg11_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_usbotg11_pms_w_reg_t;
+
+/** Type of trace0_pms_r register
+ *  TRACE0 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** trace0_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TRACE0 read permission control, each bit corresponds to a region.
+         */
+        uint32_t trace0_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_trace0_pms_r_reg_t;
+
+/** Type of trace0_pms_w register
+ *  TRACE0 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** trace0_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TRACE0 write permission control, each bit corresponds to a region.
+         */
+        uint32_t trace0_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_trace0_pms_w_reg_t;
+
+/** Type of trace1_pms_r register
+ *  TRACE1 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** trace1_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TRACE1 read permission control, each bit corresponds to a region.
+         */
+        uint32_t trace1_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_trace1_pms_r_reg_t;
+
+/** Type of trace1_pms_w register
+ *  TRACE1 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** trace1_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TRACE1 write permission control, each bit corresponds to a region.
+         */
+        uint32_t trace1_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_trace1_pms_w_reg_t;
+
+/** Type of l2mem_mon_pms_r register
+ *  L2MEM MON read permission control registers.
+ */
+typedef union {
+    struct {
+        /** l2mem_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  L2MEM MON read permission control, each bit corresponds to a region.
+         */
+        uint32_t l2mem_mon_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_l2mem_mon_pms_r_reg_t;
+
+/** Type of l2mem_mon_pms_w register
+ *  L2MEM MON write permission control registers.
+ */
+typedef union {
+    struct {
+        /** l2mem_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  L2MEM MON write permission control, each bit corresponds to a region.
+         */
+        uint32_t l2mem_mon_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_l2mem_mon_pms_w_reg_t;
+
+/** Type of tcm_mon_pms_r register
+ *  TCM MON read permission control registers.
+ */
+typedef union {
+    struct {
+        /** tcm_mon_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TCM MON read permission control, each bit corresponds to a region.
+         */
+        uint32_t tcm_mon_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_tcm_mon_pms_r_reg_t;
+
+/** Type of tcm_mon_pms_w register
+ *  TCM MON write permission control registers.
+ */
+typedef union {
+    struct {
+        /** tcm_mon_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  TCM MON write permission control, each bit corresponds to a region.
+         */
+        uint32_t tcm_mon_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_tcm_mon_pms_w_reg_t;
+
+/** Type of regdma_pms_r register
+ *  REGDMA read permission control registers.
+ */
+typedef union {
+    struct {
+        /** regdma_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  REGDMA read permission control, each bit corresponds to a region.
+         */
+        uint32_t regdma_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_regdma_pms_r_reg_t;
+
+/** Type of regdma_pms_w register
+ *  REGDMA write permission control registers.
+ */
+typedef union {
+    struct {
+        /** regdma_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  REGDMA write permission control, each bit corresponds to a region.
+         */
+        uint32_t regdma_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_regdma_pms_w_reg_t;
+
+/** Type of h264_pms_r register
+ *  H264 read permission control registers.
+ */
+typedef union {
+    struct {
+        /** h264_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  H264 read permission control, each bit corresponds to a region.
+         */
+        uint32_t h264_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_h264_pms_r_reg_t;
+
+/** Type of h264_pms_w register
+ *  H264 write permission control registers.
+ */
+typedef union {
+    struct {
+        /** h264_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  H264 write permission control, each bit corresponds to a region.
+         */
+        uint32_t h264_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_h264_pms_w_reg_t;
+
+/** Type of dma2d_ppa_pms_r register
+ *  DMA2D PPA read permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_ppa_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D PPA  read permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_ppa_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_ppa_pms_r_reg_t;
+
+/** Type of dma2d_ppa_pms_w register
+ *  DMA2D PPA  write permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_ppa_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D  PPA write permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_ppa_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_ppa_pms_w_reg_t;
+
+/** Type of dma2d_dummy_pms_r register
+ *  DMA2D dummy read permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_dummy_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D dummy  read permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_dummy_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_dummy_pms_r_reg_t;
+
+/** Type of dma2d_dummy_pms_w register
+ *  DMA2D dummy  write permission control registers.
+ */
+typedef union {
+    struct {
+        /** dma2d_dummy_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  DMA2D dummy  write permission control, each bit corresponds to a region.
+         */
+        uint32_t dma2d_dummy_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_dma2d_dummy_pms_w_reg_t;
+
+/** Type of ahb_pdma_dummy_r_pms register
+ *  AHB PDMA dummy read permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_dummy_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA dummy read permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_dummy_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_dummy_r_pms_reg_t;
+
+/** Type of ahb_pdma_dummy_w_pms register
+ *  AHB PDMA dummy write permission control registers.
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_dummy_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AHB PDMA dummy write permission control, each bit corresponds to a region.
+         */
+        uint32_t ahb_pdma_dummy_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_ahb_pdma_dummy_w_pms_reg_t;
+
+/** Type of axi_pdma_dummy_r_pms register
+ *  AXI PDMA dummy read permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_dummy_r_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA dummy read permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_dummy_r_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_dummy_r_pms_reg_t;
+
+/** Type of axi_pdma_dummy_w_pms register
+ *  AXI PDMA dummy write permission control registers.
+ */
+typedef union {
+    struct {
+        /** axi_pdma_dummy_w_pms : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI PDMA dummy write permission control, each bit corresponds to a region.
+         */
+        uint32_t axi_pdma_dummy_w_pms:32;
+    };
+    uint32_t val;
+} tee_dma_axi_pdma_dummy_w_pms_reg_t;
+
+
+typedef struct {
+    volatile tee_dma_date_reg_t date;
+    volatile tee_dma_clk_en_reg_t clk_en;
+    volatile tee_dma_region0_low_reg_t region0_low;
+    volatile tee_dma_region0_high_reg_t region0_high;
+    volatile tee_dma_region1_low_reg_t region1_low;
+    volatile tee_dma_region1_high_reg_t region1_high;
+    volatile tee_dma_region2_low_reg_t region2_low;
+    volatile tee_dma_region2_high_reg_t region2_high;
+    volatile tee_dma_region3_low_reg_t region3_low;
+    volatile tee_dma_region3_high_reg_t region3_high;
+    volatile tee_dma_region4_low_reg_t region4_low;
+    volatile tee_dma_region4_high_reg_t region4_high;
+    volatile tee_dma_region5_low_reg_t region5_low;
+    volatile tee_dma_region5_high_reg_t region5_high;
+    volatile tee_dma_region6_low_reg_t region6_low;
+    volatile tee_dma_region6_high_reg_t region6_high;
+    volatile tee_dma_region7_low_reg_t region7_low;
+    volatile tee_dma_region7_high_reg_t region7_high;
+    volatile tee_dma_region8_low_reg_t region8_low;
+    volatile tee_dma_region8_high_reg_t region8_high;
+    volatile tee_dma_region9_low_reg_t region9_low;
+    volatile tee_dma_region9_high_reg_t region9_high;
+    volatile tee_dma_region10_low_reg_t region10_low;
+    volatile tee_dma_region10_high_reg_t region10_high;
+    volatile tee_dma_region11_low_reg_t region11_low;
+    volatile tee_dma_region11_high_reg_t region11_high;
+    volatile tee_dma_region12_low_reg_t region12_low;
+    volatile tee_dma_region12_high_reg_t region12_high;
+    volatile tee_dma_region13_low_reg_t region13_low;
+    volatile tee_dma_region13_high_reg_t region13_high;
+    volatile tee_dma_region14_low_reg_t region14_low;
+    volatile tee_dma_region14_high_reg_t region14_high;
+    volatile tee_dma_region15_low_reg_t region15_low;
+    volatile tee_dma_region15_high_reg_t region15_high;
+    volatile tee_dma_region16_low_reg_t region16_low;
+    volatile tee_dma_region16_high_reg_t region16_high;
+    volatile tee_dma_region17_low_reg_t region17_low;
+    volatile tee_dma_region17_high_reg_t region17_high;
+    volatile tee_dma_region18_low_reg_t region18_low;
+    volatile tee_dma_region18_high_reg_t region18_high;
+    volatile tee_dma_region19_low_reg_t region19_low;
+    volatile tee_dma_region19_high_reg_t region19_high;
+    volatile tee_dma_region20_low_reg_t region20_low;
+    volatile tee_dma_region20_high_reg_t region20_high;
+    volatile tee_dma_region21_low_reg_t region21_low;
+    volatile tee_dma_region21_high_reg_t region21_high;
+    volatile tee_dma_region22_low_reg_t region22_low;
+    volatile tee_dma_region22_high_reg_t region22_high;
+    volatile tee_dma_region23_low_reg_t region23_low;
+    volatile tee_dma_region23_high_reg_t region23_high;
+    volatile tee_dma_region24_low_reg_t region24_low;
+    volatile tee_dma_region24_high_reg_t region24_high;
+    volatile tee_dma_region25_low_reg_t region25_low;
+    volatile tee_dma_region25_high_reg_t region25_high;
+    volatile tee_dma_region26_low_reg_t region26_low;
+    volatile tee_dma_region26_high_reg_t region26_high;
+    volatile tee_dma_region27_low_reg_t region27_low;
+    volatile tee_dma_region27_high_reg_t region27_high;
+    volatile tee_dma_region28_low_reg_t region28_low;
+    volatile tee_dma_region28_high_reg_t region28_high;
+    volatile tee_dma_region29_low_reg_t region29_low;
+    volatile tee_dma_region29_high_reg_t region29_high;
+    volatile tee_dma_region30_low_reg_t region30_low;
+    volatile tee_dma_region30_high_reg_t region30_high;
+    volatile tee_dma_region31_low_reg_t region31_low;
+    volatile tee_dma_region31_high_reg_t region31_high;
+    volatile tee_dma_gmda_ch0_r_pms_reg_t gmda_ch0_r_pms;
+    volatile tee_dma_gmda_ch0_w_pms_reg_t gmda_ch0_w_pms;
+    volatile tee_dma_gmda_ch1_r_pms_reg_t gmda_ch1_r_pms;
+    volatile tee_dma_gmda_ch1_w_pms_reg_t gmda_ch1_w_pms;
+    volatile tee_dma_gmda_ch2_r_pms_reg_t gmda_ch2_r_pms;
+    volatile tee_dma_gmda_ch2_w_pms_reg_t gmda_ch2_w_pms;
+    volatile tee_dma_gmda_ch3_r_pms_reg_t gmda_ch3_r_pms;
+    volatile tee_dma_gmda_ch3_w_pms_reg_t gmda_ch3_w_pms;
+    volatile tee_dma_ahb_pdma_adc_r_pms_reg_t ahb_pdma_adc_r_pms;
+    volatile tee_dma_ahb_pdma_adc_w_pms_reg_t ahb_pdma_adc_w_pms;
+    volatile tee_dma_ahb_pdma_i2s0_r_pms_reg_t ahb_pdma_i2s0_r_pms;
+    volatile tee_dma_ahb_pdma_i2s0_w_pms_reg_t ahb_pdma_i2s0_w_pms;
+    volatile tee_dma_ahb_pdma_i2s1_r_pms_reg_t ahb_pdma_i2s1_r_pms;
+    volatile tee_dma_ahb_pdma_i2s1_w_pms_reg_t ahb_pdma_i2s1_w_pms;
+    volatile tee_dma_ahb_pdma_i2s2_r_pms_reg_t ahb_pdma_i2s2_r_pms;
+    volatile tee_dma_ahb_pdma_i2s2_w_pms_reg_t ahb_pdma_i2s2_w_pms;
+    volatile tee_dma_ahb_pdma_i3c_mst_r_pms_reg_t ahb_pdma_i3c_mst_r_pms;
+    volatile tee_dma_ahb_pdma_i3c_mst_w_pms_reg_t ahb_pdma_i3c_mst_w_pms;
+    volatile tee_dma_ahb_pdma_uhci0_r_pms_reg_t ahb_pdma_uhci0_r_pms;
+    volatile tee_dma_ahb_pdma_uhci0_w_pms_reg_t ahb_pdma_uhci0_w_pms;
+    volatile tee_dma_ahb_pdma_rmt_r_pms_reg_t ahb_pdma_rmt_r_pms;
+    uint32_t reserved_15c[5];
+    volatile tee_dma_ahb_pdma_rmt_w_pms_reg_t ahb_pdma_rmt_w_pms;
+    volatile tee_dma_axi_pdma_lcdcam_r_pms_reg_t axi_pdma_lcdcam_r_pms;
+    volatile tee_dma_axi_pdma_lcdcam_w_pms_reg_t axi_pdma_lcdcam_w_pms;
+    volatile tee_dma_axi_pdma_gpspi2_r_pms_reg_t axi_pdma_gpspi2_r_pms;
+    volatile tee_dma_axi_pdma_gpspi2_w_pms_reg_t axi_pdma_gpspi2_w_pms;
+    volatile tee_dma_axi_pdma_gpspi3_r_pms_reg_t axi_pdma_gpspi3_r_pms;
+    volatile tee_dma_axi_pdma_gpspi3_w_pms_reg_t axi_pdma_gpspi3_w_pms;
+    volatile tee_dma_axi_pdma_parlio_r_pms_reg_t axi_pdma_parlio_r_pms;
+    volatile tee_dma_axi_pdma_parlio_w_pms_reg_t axi_pdma_parlio_w_pms;
+    volatile tee_dma_axi_pdma_aes_r_pms_reg_t axi_pdma_aes_r_pms;
+    volatile tee_dma_axi_pdma_aes_w_pms_reg_t axi_pdma_aes_w_pms;
+    volatile tee_dma_axi_pdma_sha_r_pms_reg_t axi_pdma_sha_r_pms;
+    volatile tee_dma_axi_pdma_sha_w_pms_reg_t axi_pdma_sha_w_pms;
+    volatile tee_dma_dma2d_jpeg_pms_r_reg_t dma2d_jpeg_pms_r;
+    volatile tee_dma_dma2d_jpeg_pms_w_reg_t dma2d_jpeg_pms_w;
+    volatile tee_dma_usb_pms_r_reg_t usb_pms_r;
+    volatile tee_dma_usb_pms_w_reg_t usb_pms_w;
+    volatile tee_dma_gmac_pms_r_reg_t gmac_pms_r;
+    volatile tee_dma_gmac_pms_w_reg_t gmac_pms_w;
+    volatile tee_dma_sdmmc_pms_r_reg_t sdmmc_pms_r;
+    volatile tee_dma_sdmmc_pms_w_reg_t sdmmc_pms_w;
+    volatile tee_dma_usbotg11_pms_r_reg_t usbotg11_pms_r;
+    volatile tee_dma_usbotg11_pms_w_reg_t usbotg11_pms_w;
+    volatile tee_dma_trace0_pms_r_reg_t trace0_pms_r;
+    volatile tee_dma_trace0_pms_w_reg_t trace0_pms_w;
+    volatile tee_dma_trace1_pms_r_reg_t trace1_pms_r;
+    volatile tee_dma_trace1_pms_w_reg_t trace1_pms_w;
+    volatile tee_dma_l2mem_mon_pms_r_reg_t l2mem_mon_pms_r;
+    volatile tee_dma_l2mem_mon_pms_w_reg_t l2mem_mon_pms_w;
+    volatile tee_dma_tcm_mon_pms_r_reg_t tcm_mon_pms_r;
+    volatile tee_dma_tcm_mon_pms_w_reg_t tcm_mon_pms_w;
+    volatile tee_dma_regdma_pms_r_reg_t regdma_pms_r;
+    volatile tee_dma_regdma_pms_w_reg_t regdma_pms_w;
+    uint32_t reserved_1f4[2];
+    volatile tee_dma_h264_pms_r_reg_t h264_pms_r;
+    volatile tee_dma_h264_pms_w_reg_t h264_pms_w;
+    volatile tee_dma_dma2d_ppa_pms_r_reg_t dma2d_ppa_pms_r;
+    volatile tee_dma_dma2d_ppa_pms_w_reg_t dma2d_ppa_pms_w;
+    volatile tee_dma_dma2d_dummy_pms_r_reg_t dma2d_dummy_pms_r;
+    volatile tee_dma_dma2d_dummy_pms_w_reg_t dma2d_dummy_pms_w;
+    volatile tee_dma_ahb_pdma_dummy_r_pms_reg_t ahb_pdma_dummy_r_pms;
+    volatile tee_dma_ahb_pdma_dummy_w_pms_reg_t ahb_pdma_dummy_w_pms;
+    volatile tee_dma_axi_pdma_dummy_r_pms_reg_t axi_pdma_dummy_r_pms;
+    volatile tee_dma_axi_pdma_dummy_w_pms_reg_t axi_pdma_dummy_w_pms;
+} tee_dma_dev_t;
+
+extern tee_dma_dev_t DMA_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dma_dev_t) == 0x224, "Invalid size of tee_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ds_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/ds_reg.h
new file mode 100644
index 0000000000..fd6797f0fa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ds_reg.h
@@ -0,0 +1,176 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DS_Y_MEM register
+ *  memory that stores Y
+ */
+#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
+#define DS_Y_MEM_SIZE_BYTES 512
+
+/** DS_M_MEM register
+ *  memory that stores M
+ */
+#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
+#define DS_M_MEM_SIZE_BYTES 512
+
+/** DS_RB_MEM register
+ *  memory that stores Rb
+ */
+#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
+#define DS_RB_MEM_SIZE_BYTES 512
+
+/** DS_BOX_MEM register
+ *  memory that stores BOX
+ */
+#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
+#define DS_BOX_MEM_SIZE_BYTES 48
+
+/** DS_IV_MEM register
+ *  memory that stores IV
+ */
+#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
+#define DS_IV_MEM_SIZE_BYTES 16
+
+/** DS_X_MEM register
+ *  memory that stores X
+ */
+#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
+#define DS_X_MEM_SIZE_BYTES 512
+
+/** DS_Z_MEM register
+ *  memory that stores Z
+ */
+#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
+#define DS_Z_MEM_SIZE_BYTES 512
+
+/** DS_SET_START_REG register
+ *  Activates the DS module
+ */
+#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
+/** DS_SET_START : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to activate the DS peripheral.
+ *  0: Invalid
+ *  1: Activate the DS peripheral
+ */
+#define DS_SET_START    (BIT(0))
+#define DS_SET_START_M  (DS_SET_START_V << DS_SET_START_S)
+#define DS_SET_START_V  0x00000001U
+#define DS_SET_START_S  0
+
+/** DS_SET_CONTINUE_REG register
+ *  DS continue control register
+ */
+#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
+/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  set this bit to continue DS operation.
+ */
+#define DS_SET_CONTINUE    (BIT(0))
+#define DS_SET_CONTINUE_M  (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
+#define DS_SET_CONTINUE_V  0x00000001U
+#define DS_SET_CONTINUE_S  0
+
+/** DS_SET_FINISH_REG register
+ *  Ends DS operation
+ */
+#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
+/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to end DS operation.
+ *  0: Invalid
+ *  1: End DS operation
+ */
+#define DS_SET_FINISH    (BIT(0))
+#define DS_SET_FINISH_M  (DS_SET_FINISH_V << DS_SET_FINISH_S)
+#define DS_SET_FINISH_V  0x00000001U
+#define DS_SET_FINISH_S  0
+
+/** DS_QUERY_BUSY_REG register
+ *  Status of the DS module
+ */
+#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
+/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the DS module is idle.
+ *  0: The DS module is idle
+ *  1: The DS module is busy
+ */
+#define DS_QUERY_BUSY    (BIT(0))
+#define DS_QUERY_BUSY_M  (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
+#define DS_QUERY_BUSY_V  0x00000001U
+#define DS_QUERY_BUSY_S  0
+
+/** DS_QUERY_KEY_WRONG_REG register
+ *  Checks the reason why \begin{math}DS_KEY\end{math} is not ready
+ */
+#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
+/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
+ *  Represents the specific problem with HMAC initialization.
+ *  0: HMAC is not called
+ *  1-15: HMAC was activated, but the DS peripheral did not successfully receive the
+ *  \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
+ */
+#define DS_QUERY_KEY_WRONG    0x0000000FU
+#define DS_QUERY_KEY_WRONG_M  (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
+#define DS_QUERY_KEY_WRONG_V  0x0000000FU
+#define DS_QUERY_KEY_WRONG_S  0
+
+/** DS_QUERY_CHECK_REG register
+ *  Queries DS check result
+ */
+#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
+/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the MD check passes.
+ *  0: The MD check passes
+ *  1: The MD check fails
+ */
+#define DS_MD_ERROR    (BIT(0))
+#define DS_MD_ERROR_M  (DS_MD_ERROR_V << DS_MD_ERROR_S)
+#define DS_MD_ERROR_V  0x00000001U
+#define DS_MD_ERROR_S  0
+/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not the padding check passes.
+ *  0: The padding check passes
+ *  1: The padding check fails
+ */
+#define DS_PADDING_BAD    (BIT(1))
+#define DS_PADDING_BAD_M  (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
+#define DS_PADDING_BAD_V  0x00000001U
+#define DS_PADDING_BAD_S  1
+
+/** DS_KEY_SOURCE_REG register
+ *  DS configure key source register
+ */
+#define DS_KEY_SOURCE_REG (DR_REG_DS_BASE + 0xe18)
+/** DS_KEY_SOURCE : R/W; bitpos: [0]; default: 0;
+ *  digital signature key source bit.
+ *  1'b0: key is from hmac.
+ *  1'b1: key is from key manager.
+ */
+#define DS_KEY_SOURCE    (BIT(0))
+#define DS_KEY_SOURCE_M  (DS_KEY_SOURCE_V << DS_KEY_SOURCE_S)
+#define DS_KEY_SOURCE_V  0x00000001U
+#define DS_KEY_SOURCE_S  0
+
+/** DS_DATE_REG register
+ *  DS version control register
+ */
+#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
+/** DS_DATE : R/W; bitpos: [29:0]; default: 539166977;
+ *  ds version information
+ */
+#define DS_DATE    0x3FFFFFFFU
+#define DS_DATE_M  (DS_DATE_V << DS_DATE_S)
+#define DS_DATE_V  0x3FFFFFFFU
+#define DS_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ds_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/ds_struct.h
new file mode 100644
index 0000000000..317f867a4c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ds_struct.h
@@ -0,0 +1,181 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: memory type */
+
+/** Group: Control/Status registers */
+/** Type of set_start register
+ *  Activates the DS module
+ */
+typedef union {
+    struct {
+        /** set_start : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to activate the DS peripheral.
+         *  0: Invalid
+         *  1: Activate the DS peripheral
+         */
+        uint32_t set_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_set_start_reg_t;
+
+/** Type of set_continue register
+ *  DS continue control register
+ */
+typedef union {
+    struct {
+        /** set_continue : WT; bitpos: [0]; default: 0;
+         *  set this bit to continue DS operation.
+         */
+        uint32_t set_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_set_continue_reg_t;
+
+/** Type of set_finish register
+ *  Ends DS operation
+ */
+typedef union {
+    struct {
+        /** set_finish : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to end DS operation.
+         *  0: Invalid
+         *  1: End DS operation
+         */
+        uint32_t set_finish:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_set_finish_reg_t;
+
+/** Type of query_busy register
+ *  Status of the DS module
+ */
+typedef union {
+    struct {
+        /** query_busy : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the DS module is idle.
+         *  0: The DS module is idle
+         *  1: The DS module is busy
+         */
+        uint32_t query_busy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_query_busy_reg_t;
+
+/** Type of query_key_wrong register
+ *  Checks the reason why \begin{math}DS_KEY\end{math} is not ready
+ */
+typedef union {
+    struct {
+        /** query_key_wrong : RO; bitpos: [3:0]; default: 0;
+         *  Represents the specific problem with HMAC initialization.
+         *  0: HMAC is not called
+         *  1-15: HMAC was activated, but the DS peripheral did not successfully receive the
+         *  \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
+         */
+        uint32_t query_key_wrong:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ds_query_key_wrong_reg_t;
+
+/** Type of query_check register
+ *  Queries DS check result
+ */
+typedef union {
+    struct {
+        /** md_error : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the MD check passes.
+         *  0: The MD check passes
+         *  1: The MD check fails
+         */
+        uint32_t md_error:1;
+        /** padding_bad : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not the padding check passes.
+         *  0: The padding check passes
+         *  1: The padding check fails
+         */
+        uint32_t padding_bad:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ds_query_check_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of key_source register
+ *  DS configure key source register
+ */
+typedef union {
+    struct {
+        /** key_source : R/W; bitpos: [0]; default: 0;
+         *  digital signature key source bit.
+         *  1'b0: key is from hmac.
+         *  1'b1: key is from key manager.
+         */
+        uint32_t key_source:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_key_source_reg_t;
+
+
+/** Group: version control register */
+/** Type of date register
+ *  DS version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 539166977;
+         *  ds version information
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} ds_date_reg_t;
+
+
+typedef struct {
+    volatile uint32_t y[128];
+    volatile uint32_t m[128];
+    volatile uint32_t rb[128];
+    volatile uint32_t box[12];
+    volatile uint32_t iv[4];
+    uint32_t reserved_640[112];
+    volatile uint32_t x[128];
+    volatile uint32_t z[128];
+    uint32_t reserved_c00[128];
+    volatile ds_set_start_reg_t set_start;
+    volatile ds_set_continue_reg_t set_continue;
+    volatile ds_set_finish_reg_t set_finish;
+    volatile ds_query_busy_reg_t query_busy;
+    volatile ds_query_key_wrong_reg_t query_key_wrong;
+    volatile ds_query_check_reg_t query_check;
+    volatile ds_key_source_reg_t key_source;
+    uint32_t reserved_e1c;
+    volatile ds_date_reg_t date;
+} ds_dev_t;
+
+extern ds_dev_t DS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ds_dev_t) == 0xe24, "Invalid size of ds_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_eco5_struct.h
new file mode 100644
index 0000000000..c030f0e037
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_eco5_struct.h
@@ -0,0 +1,5184 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Version Register */
+/** Type of id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_id : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_id:32;
+    };
+    uint32_t val;
+} dmac_id0_reg_t;
+
+/** Type of compver0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_compver : RO; bitpos: [31:0]; default: 842018858;
+         *  NA
+         */
+        uint32_t dmac_compver:32;
+    };
+    uint32_t val;
+} dmac_compver0_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_en:1;
+        /** int_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t int_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dmac_cfg0_reg_t;
+
+/** Type of chen0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en:1;
+        /** ch2_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en:1;
+        /** ch3_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en:1;
+        /** ch4_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en:1;
+        uint32_t reserved_4:4;
+        /** ch1_en_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en_we:1;
+        /** ch2_en_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en_we:1;
+        /** ch3_en_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en_we:1;
+        /** ch4_en_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en_we:1;
+        uint32_t reserved_12:4;
+        /** ch1_susp : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp:1;
+        /** ch2_susp : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp:1;
+        /** ch3_susp : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp:1;
+        /** ch4_susp : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp:1;
+        uint32_t reserved_20:4;
+        /** ch1_susp_we : WO; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp_we:1;
+        /** ch2_susp_we : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp_we:1;
+        /** ch3_susp_we : WO; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp_we:1;
+        /** ch4_susp_we : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp_we:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dmac_chen0_reg_t;
+
+/** Type of chen1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_abort : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort:1;
+        /** ch2_abort : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort:1;
+        /** ch3_abort : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort:1;
+        /** ch4_abort : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort:1;
+        uint32_t reserved_4:4;
+        /** ch1_abort_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort_we:1;
+        /** ch2_abort_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort_we:1;
+        /** ch3_abort_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort_we:1;
+        /** ch4_abort_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort_we:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dmac_chen1_reg_t;
+
+/** Type of reset0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_rst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_rst:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_reset0_reg_t;
+
+/** Type of lowpower_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gbl_cslp_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t gbl_cslp_en:1;
+        /** chnl_cslp_en : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t chnl_cslp_en:1;
+        /** sbiu_cslp_en : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t sbiu_cslp_en:1;
+        /** mxif_cslp_en : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t mxif_cslp_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg0_reg_t;
+
+/** Type of lowpower_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** glch_lpdly : R/W; bitpos: [7:0]; default: 64;
+         *  NA
+         */
+        uint32_t glch_lpdly:8;
+        /** sbiu_lpdly : R/W; bitpos: [15:8]; default: 64;
+         *  NA
+         */
+        uint32_t sbiu_lpdly:8;
+        /** mxif_lpdly : R/W; bitpos: [23:16]; default: 64;
+         *  NA
+         */
+        uint32_t mxif_lpdly:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg1_reg_t;
+
+/** Type of ch1_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sar0:32;
+    };
+    uint32_t val;
+} dmac_ch1_sar0_reg_t;
+
+/** Type of ch1_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sar1:32;
+    };
+    uint32_t val;
+} dmac_ch1_sar1_reg_t;
+
+/** Type of ch1_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dar0:32;
+    };
+    uint32_t val;
+} dmac_ch1_dar0_reg_t;
+
+/** Type of ch1_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dar1:32;
+    };
+    uint32_t val;
+} dmac_ch1_dar1_reg_t;
+
+/** Type of ch1_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_block_ts:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch1_block_ts0_reg_t;
+
+/** Type of ch1_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sms:1;
+        uint32_t reserved_1:1;
+        /** ch1_dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dms:1;
+        uint32_t reserved_3:1;
+        /** ch1_sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sinc:1;
+        uint32_t reserved_5:1;
+        /** ch1_dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dinc:1;
+        uint32_t reserved_7:1;
+        /** ch1_src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t ch1_src_tr_width:3;
+        /** ch1_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t ch1_dst_tr_width:3;
+        /** ch1_src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_msize:4;
+        /** ch1_dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_msize:4;
+        /** ch1_ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ar_cache:4;
+        /** ch1_aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_aw_cache:4;
+        /** ch1_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_nonposted_lastwrite_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch1_ctl0_reg_t;
+
+/** Type of ch1_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ar_prot:3;
+        /** ch1_aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_aw_prot:3;
+        /** ch1_arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_arlen_en:1;
+        /** ch1_arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_arlen:8;
+        /** ch1_awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_awlen_en:1;
+        /** ch1_awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_awlen:8;
+        /** ch1_src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_stat_en:1;
+        /** ch1_dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_stat_en:1;
+        /** ch1_ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ioc_blktfr:1;
+        uint32_t reserved_27:3;
+        /** ch1_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_shadowreg_or_lli_last:1;
+        /** ch1_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_shadowreg_or_lli_valid:1;
+    };
+    uint32_t val;
+} dmac_ch1_ctl1_reg_t;
+
+/** Type of ch1_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_multblk_type:2;
+        /** ch1_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_multblk_type:2;
+        uint32_t reserved_4:14;
+        /** ch1_rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_rd_uid:4;
+        uint32_t reserved_22:3;
+        /** ch1_wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_wr_uid:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dmac_ch1_cfg0_reg_t;
+
+/** Type of ch1_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t ch1_tt_fc:3;
+        /** ch1_hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_hs_sel_src:1;
+        /** ch1_hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_hs_sel_dst:1;
+        /** ch1_src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_hwhs_pol:1;
+        /** ch1_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_hwhs_pol:1;
+        /** ch1_src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_per:2;
+        uint32_t reserved_9:3;
+        /** ch1_dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_per:2;
+        uint32_t reserved_14:3;
+        /** ch1_ch_prior : R/W; bitpos: [19:17]; default: 3;
+         *  NA
+         */
+        uint32_t ch1_ch_prior:3;
+        /** ch1_lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lock_ch:1;
+        /** ch1_lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lock_ch_l:2;
+        /** ch1_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_osr_lmt:4;
+        /** ch1_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_osr_lmt:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch1_cfg1_reg_t;
+
+/** Type of ch1_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lms:1;
+        uint32_t reserved_1:5;
+        /** ch1_loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_loc0:26;
+    };
+    uint32_t val;
+} dmac_ch1_llp0_reg_t;
+
+/** Type of ch1_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_loc1:32;
+    };
+    uint32_t val;
+} dmac_ch1_llp1_reg_t;
+
+/** Type of ch1_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_req_src:1;
+        /** ch1_swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_req_src_we:1;
+        /** ch1_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_sglreq_src:1;
+        /** ch1_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_sglreq_src_we:1;
+        /** ch1_swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_lst_src:1;
+        /** ch1_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_lst_src_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch1_swhssrc0_reg_t;
+
+/** Type of ch1_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_req_dst:1;
+        /** ch1_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_req_dst_we:1;
+        /** ch1_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_sglreq_dst:1;
+        /** ch1_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_sglreq_dst_we:1;
+        /** ch1_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_lst_dst:1;
+        /** ch1_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_swhs_lst_dst_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch1_swhsdst0_reg_t;
+
+/** Type of ch1_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_blk_tfr_resumereq:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_ch1_blk_tfr_resumereq0_reg_t;
+
+/** Type of ch1_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_axi_read_id_suffix:1;
+        uint32_t reserved_1:15;
+        /** ch1_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_axi_write_id_suffix:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_ch1_axi_id0_reg_t;
+
+/** Type of ch1_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_axi_awqos:4;
+        /** ch1_axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_axi_arqos:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dmac_ch1_axi_qos0_reg_t;
+
+/** Type of ch2_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sar0:32;
+    };
+    uint32_t val;
+} dmac_ch2_sar0_reg_t;
+
+/** Type of ch2_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sar1:32;
+    };
+    uint32_t val;
+} dmac_ch2_sar1_reg_t;
+
+/** Type of ch2_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dar0:32;
+    };
+    uint32_t val;
+} dmac_ch2_dar0_reg_t;
+
+/** Type of ch2_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dar1:32;
+    };
+    uint32_t val;
+} dmac_ch2_dar1_reg_t;
+
+/** Type of ch2_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_block_ts:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch2_block_ts0_reg_t;
+
+/** Type of ch2_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sms:1;
+        uint32_t reserved_1:1;
+        /** ch2_dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dms:1;
+        uint32_t reserved_3:1;
+        /** ch2_sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sinc:1;
+        uint32_t reserved_5:1;
+        /** ch2_dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dinc:1;
+        uint32_t reserved_7:1;
+        /** ch2_src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t ch2_src_tr_width:3;
+        /** ch2_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t ch2_dst_tr_width:3;
+        /** ch2_src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_msize:4;
+        /** ch2_dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_msize:4;
+        /** ch2_ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ar_cache:4;
+        /** ch2_aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_aw_cache:4;
+        /** ch2_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_nonposted_lastwrite_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch2_ctl0_reg_t;
+
+/** Type of ch2_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ar_prot:3;
+        /** ch2_aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_aw_prot:3;
+        /** ch2_arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_arlen_en:1;
+        /** ch2_arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_arlen:8;
+        /** ch2_awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_awlen_en:1;
+        /** ch2_awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_awlen:8;
+        /** ch2_src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_stat_en:1;
+        /** ch2_dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_stat_en:1;
+        /** ch2_ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ioc_blktfr:1;
+        uint32_t reserved_27:3;
+        /** ch2_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_shadowreg_or_lli_last:1;
+        /** ch2_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_shadowreg_or_lli_valid:1;
+    };
+    uint32_t val;
+} dmac_ch2_ctl1_reg_t;
+
+/** Type of ch2_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_multblk_type:2;
+        /** ch2_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_multblk_type:2;
+        uint32_t reserved_4:14;
+        /** ch2_rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_rd_uid:4;
+        uint32_t reserved_22:3;
+        /** ch2_wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_wr_uid:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dmac_ch2_cfg0_reg_t;
+
+/** Type of ch2_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t ch2_tt_fc:3;
+        /** ch2_hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_hs_sel_src:1;
+        /** ch2_hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_hs_sel_dst:1;
+        /** ch2_src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_hwhs_pol:1;
+        /** ch2_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_hwhs_pol:1;
+        /** ch2_src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_per:2;
+        uint32_t reserved_9:3;
+        /** ch2_dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_per:2;
+        uint32_t reserved_14:3;
+        /** ch2_ch_prior : R/W; bitpos: [19:17]; default: 2;
+         *  NA
+         */
+        uint32_t ch2_ch_prior:3;
+        /** ch2_lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lock_ch:1;
+        /** ch2_lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lock_ch_l:2;
+        /** ch2_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_osr_lmt:4;
+        /** ch2_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_osr_lmt:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch2_cfg1_reg_t;
+
+/** Type of ch2_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lms:1;
+        uint32_t reserved_1:5;
+        /** ch2_loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_loc0:26;
+    };
+    uint32_t val;
+} dmac_ch2_llp0_reg_t;
+
+/** Type of ch2_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_loc1:32;
+    };
+    uint32_t val;
+} dmac_ch2_llp1_reg_t;
+
+/** Type of ch2_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_req_src:1;
+        /** ch2_swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_req_src_we:1;
+        /** ch2_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_sglreq_src:1;
+        /** ch2_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_sglreq_src_we:1;
+        /** ch2_swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_lst_src:1;
+        /** ch2_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_lst_src_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch2_swhssrc0_reg_t;
+
+/** Type of ch2_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_req_dst:1;
+        /** ch2_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_req_dst_we:1;
+        /** ch2_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_sglreq_dst:1;
+        /** ch2_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_sglreq_dst_we:1;
+        /** ch2_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_lst_dst:1;
+        /** ch2_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_swhs_lst_dst_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch2_swhsdst0_reg_t;
+
+/** Type of ch2_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_blk_tfr_resumereq:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_ch2_blk_tfr_resumereq0_reg_t;
+
+/** Type of ch2_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_axi_read_id_suffix:1;
+        uint32_t reserved_1:15;
+        /** ch2_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_axi_write_id_suffix:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_ch2_axi_id0_reg_t;
+
+/** Type of ch2_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_axi_awqos:4;
+        /** ch2_axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_axi_arqos:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dmac_ch2_axi_qos0_reg_t;
+
+/** Type of ch3_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sar0:32;
+    };
+    uint32_t val;
+} dmac_ch3_sar0_reg_t;
+
+/** Type of ch3_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sar1:32;
+    };
+    uint32_t val;
+} dmac_ch3_sar1_reg_t;
+
+/** Type of ch3_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dar0:32;
+    };
+    uint32_t val;
+} dmac_ch3_dar0_reg_t;
+
+/** Type of ch3_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dar1:32;
+    };
+    uint32_t val;
+} dmac_ch3_dar1_reg_t;
+
+/** Type of ch3_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_block_ts:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch3_block_ts0_reg_t;
+
+/** Type of ch3_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sms:1;
+        uint32_t reserved_1:1;
+        /** ch3_dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dms:1;
+        uint32_t reserved_3:1;
+        /** ch3_sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sinc:1;
+        uint32_t reserved_5:1;
+        /** ch3_dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dinc:1;
+        uint32_t reserved_7:1;
+        /** ch3_src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t ch3_src_tr_width:3;
+        /** ch3_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t ch3_dst_tr_width:3;
+        /** ch3_src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_msize:4;
+        /** ch3_dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_msize:4;
+        /** ch3_ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ar_cache:4;
+        /** ch3_aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_aw_cache:4;
+        /** ch3_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_nonposted_lastwrite_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch3_ctl0_reg_t;
+
+/** Type of ch3_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ar_prot:3;
+        /** ch3_aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_aw_prot:3;
+        /** ch3_arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_arlen_en:1;
+        /** ch3_arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_arlen:8;
+        /** ch3_awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_awlen_en:1;
+        /** ch3_awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_awlen:8;
+        /** ch3_src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_stat_en:1;
+        /** ch3_dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_stat_en:1;
+        /** ch3_ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ioc_blktfr:1;
+        uint32_t reserved_27:3;
+        /** ch3_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_shadowreg_or_lli_last:1;
+        /** ch3_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_shadowreg_or_lli_valid:1;
+    };
+    uint32_t val;
+} dmac_ch3_ctl1_reg_t;
+
+/** Type of ch3_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_multblk_type:2;
+        /** ch3_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_multblk_type:2;
+        uint32_t reserved_4:14;
+        /** ch3_rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_rd_uid:4;
+        uint32_t reserved_22:3;
+        /** ch3_wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_wr_uid:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dmac_ch3_cfg0_reg_t;
+
+/** Type of ch3_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t ch3_tt_fc:3;
+        /** ch3_hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_hs_sel_src:1;
+        /** ch3_hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_hs_sel_dst:1;
+        /** ch3_src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_hwhs_pol:1;
+        /** ch3_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_hwhs_pol:1;
+        /** ch3_src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_per:2;
+        uint32_t reserved_9:3;
+        /** ch3_dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_per:2;
+        uint32_t reserved_14:3;
+        /** ch3_ch_prior : R/W; bitpos: [19:17]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_ch_prior:3;
+        /** ch3_lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lock_ch:1;
+        /** ch3_lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lock_ch_l:2;
+        /** ch3_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_osr_lmt:4;
+        /** ch3_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_osr_lmt:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch3_cfg1_reg_t;
+
+/** Type of ch3_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lms:1;
+        uint32_t reserved_1:5;
+        /** ch3_loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_loc0:26;
+    };
+    uint32_t val;
+} dmac_ch3_llp0_reg_t;
+
+/** Type of ch3_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_loc1:32;
+    };
+    uint32_t val;
+} dmac_ch3_llp1_reg_t;
+
+/** Type of ch3_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_req_src:1;
+        /** ch3_swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_req_src_we:1;
+        /** ch3_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_sglreq_src:1;
+        /** ch3_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_sglreq_src_we:1;
+        /** ch3_swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_lst_src:1;
+        /** ch3_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_lst_src_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch3_swhssrc0_reg_t;
+
+/** Type of ch3_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_req_dst:1;
+        /** ch3_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_req_dst_we:1;
+        /** ch3_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_sglreq_dst:1;
+        /** ch3_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_sglreq_dst_we:1;
+        /** ch3_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_lst_dst:1;
+        /** ch3_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_swhs_lst_dst_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch3_swhsdst0_reg_t;
+
+/** Type of ch3_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_blk_tfr_resumereq:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_ch3_blk_tfr_resumereq0_reg_t;
+
+/** Type of ch3_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_axi_read_id_suffix:1;
+        uint32_t reserved_1:15;
+        /** ch3_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_axi_write_id_suffix:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_ch3_axi_id0_reg_t;
+
+/** Type of ch3_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_axi_awqos:4;
+        /** ch3_axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_axi_arqos:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dmac_ch3_axi_qos0_reg_t;
+
+/** Type of ch4_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sar0:32;
+    };
+    uint32_t val;
+} dmac_ch4_sar0_reg_t;
+
+/** Type of ch4_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sar1:32;
+    };
+    uint32_t val;
+} dmac_ch4_sar1_reg_t;
+
+/** Type of ch4_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dar0:32;
+    };
+    uint32_t val;
+} dmac_ch4_dar0_reg_t;
+
+/** Type of ch4_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dar1:32;
+    };
+    uint32_t val;
+} dmac_ch4_dar1_reg_t;
+
+/** Type of ch4_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_block_ts:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch4_block_ts0_reg_t;
+
+/** Type of ch4_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sms:1;
+        uint32_t reserved_1:1;
+        /** ch4_dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dms:1;
+        uint32_t reserved_3:1;
+        /** ch4_sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sinc:1;
+        uint32_t reserved_5:1;
+        /** ch4_dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dinc:1;
+        uint32_t reserved_7:1;
+        /** ch4_src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t ch4_src_tr_width:3;
+        /** ch4_dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t ch4_dst_tr_width:3;
+        /** ch4_src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_msize:4;
+        /** ch4_dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_msize:4;
+        /** ch4_ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ar_cache:4;
+        /** ch4_aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_aw_cache:4;
+        /** ch4_nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_nonposted_lastwrite_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch4_ctl0_reg_t;
+
+/** Type of ch4_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ar_prot:3;
+        /** ch4_aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_aw_prot:3;
+        /** ch4_arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_arlen_en:1;
+        /** ch4_arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_arlen:8;
+        /** ch4_awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_awlen_en:1;
+        /** ch4_awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_awlen:8;
+        /** ch4_src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_stat_en:1;
+        /** ch4_dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_stat_en:1;
+        /** ch4_ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ioc_blktfr:1;
+        uint32_t reserved_27:3;
+        /** ch4_shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_shadowreg_or_lli_last:1;
+        /** ch4_shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_shadowreg_or_lli_valid:1;
+    };
+    uint32_t val;
+} dmac_ch4_ctl1_reg_t;
+
+/** Type of ch4_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_multblk_type:2;
+        /** ch4_dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_multblk_type:2;
+        uint32_t reserved_4:14;
+        /** ch4_rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_rd_uid:4;
+        uint32_t reserved_22:3;
+        /** ch4_wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_wr_uid:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dmac_ch4_cfg0_reg_t;
+
+/** Type of ch4_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t ch4_tt_fc:3;
+        /** ch4_hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_hs_sel_src:1;
+        /** ch4_hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_hs_sel_dst:1;
+        /** ch4_src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_hwhs_pol:1;
+        /** ch4_dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_hwhs_pol:1;
+        /** ch4_src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_per:2;
+        uint32_t reserved_9:3;
+        /** ch4_dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_per:2;
+        uint32_t reserved_14:3;
+        /** ch4_ch_prior : R/W; bitpos: [19:17]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_prior:3;
+        /** ch4_lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lock_ch:1;
+        /** ch4_lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lock_ch_l:2;
+        /** ch4_src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_osr_lmt:4;
+        /** ch4_dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_osr_lmt:4;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} dmac_ch4_cfg1_reg_t;
+
+/** Type of ch4_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lms:1;
+        uint32_t reserved_1:5;
+        /** ch4_loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_loc0:26;
+    };
+    uint32_t val;
+} dmac_ch4_llp0_reg_t;
+
+/** Type of ch4_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_loc1:32;
+    };
+    uint32_t val;
+} dmac_ch4_llp1_reg_t;
+
+/** Type of ch4_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_req_src:1;
+        /** ch4_swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_req_src_we:1;
+        /** ch4_swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_sglreq_src:1;
+        /** ch4_swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_sglreq_src_we:1;
+        /** ch4_swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_lst_src:1;
+        /** ch4_swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_lst_src_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch4_swhssrc0_reg_t;
+
+/** Type of ch4_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_req_dst:1;
+        /** ch4_swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_req_dst_we:1;
+        /** ch4_swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_sglreq_dst:1;
+        /** ch4_swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_sglreq_dst_we:1;
+        /** ch4_swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_lst_dst:1;
+        /** ch4_swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_swhs_lst_dst_we:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dmac_ch4_swhsdst0_reg_t;
+
+/** Type of ch4_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_blk_tfr_resumereq:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} dmac_ch4_blk_tfr_resumereq0_reg_t;
+
+/** Type of ch4_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_axi_read_id_suffix:1;
+        uint32_t reserved_1:15;
+        /** ch4_axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_axi_write_id_suffix:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_ch4_axi_id0_reg_t;
+
+/** Type of ch4_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_axi_awqos:4;
+        /** ch4_axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_axi_arqos:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dmac_ch4_axi_qos0_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_intstat:1;
+        /** ch2_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_intstat:1;
+        /** ch3_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_intstat:1;
+        /** ch4_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_intstat:1;
+        uint32_t reserved_4:12;
+        /** commonreg_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t commonreg_intstat:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dmac_intstatus0_reg_t;
+
+/** Type of commonreg_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_slvif_commonreg_dec_err_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_dec_err_intstat:1;
+        /** clear_slvif_commonreg_wr2ro_err_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wr2ro_err_intstat:1;
+        /** clear_slvif_commonreg_rd2wo_err_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_rd2wo_err_intstat:1;
+        /** clear_slvif_commonreg_wronhold_err_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wronhold_err_intstat:1;
+        uint32_t reserved_4:3;
+        /** clear_slvif_commonreg_wrparity_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wrparity_err_intstat:1;
+        /** clear_slvif_undefinedreg_dec_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_undefinedreg_dec_err_intstat:1;
+        /** clear_mxif1_rch0_eccprot_correrr_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_correrr_intstat:1;
+        /** clear_mxif1_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif1_rch1_eccprot_correrr_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_correrr_intstat:1;
+        /** clear_mxif1_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif1_bch_eccprot_correrr_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_correrr_intstat:1;
+        /** clear_mxif1_bch_eccprot_uncorrerr_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif2_rch0_eccprot_correrr_intstat : WO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_correrr_intstat:1;
+        /** clear_mxif2_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif2_rch1_eccprot_correrr_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_correrr_intstat:1;
+        /** clear_mxif2_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_uncorrerr_intstat:1;
+        /** clear_mxif2_bch_eccprot_correrr_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_correrr_intstat:1;
+        /** clear_mxif2_bch_eccprot_uncorrerr_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_uncorrerr_intstat:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dmac_commonreg_intclear0_reg_t;
+
+/** Type of commonreg_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intstat:1;
+        /** enable_slvif_commonreg_wr2ro_err_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intstat:1;
+        /** enable_slvif_commonreg_rd2wo_err_intstat : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intstat:1;
+        /** enable_slvif_commonreg_wronhold_err_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intstat:1;
+        uint32_t reserved_4:3;
+        /** enable_slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intstat:1;
+        /** enable_slvif_undefinedreg_dec_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intstat:1;
+        /** enable_mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intstat:1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intstat:1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intstat:1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intstat:1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intstat:1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intstat:1;
+        /** enable_mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intstat:1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intstat:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus_enable0_reg_t;
+
+/** Type of commonreg_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intsignal:1;
+        /** enable_slvif_commonreg_wr2ro_err_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intsignal:1;
+        /** enable_slvif_commonreg_rd2wo_err_intsignal : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intsignal:1;
+        /** enable_slvif_commonreg_wronhold_err_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intsignal:1;
+        uint32_t reserved_4:3;
+        /** enable_slvif_commonreg_wrparity_err_intsignal : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intsignal:1;
+        /** enable_slvif_undefinedreg_dec_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intsignal:1;
+        /** enable_mxif1_rch0_eccprot_correrr_intsignal : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intsignal:1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif1_rch1_eccprot_correrr_intsignal : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intsignal:1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif1_bch_eccprot_correrr_intsignal : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intsignal:1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif2_rch0_eccprot_correrr_intsignal : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intsignal:1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif2_rch1_eccprot_correrr_intsignal : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intsignal:1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intsignal:1;
+        /** enable_mxif2_bch_eccprot_correrr_intsignal : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intsignal:1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intsignal:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dmac_commonreg_intsignal_enable0_reg_t;
+
+/** Type of commonreg_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** slvif_commonreg_dec_err_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_dec_err_intstat:1;
+        /** slvif_commonreg_wr2ro_err_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wr2ro_err_intstat:1;
+        /** slvif_commonreg_rd2wo_err_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_rd2wo_err_intstat:1;
+        /** slvif_commonreg_wronhold_err_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wronhold_err_intstat:1;
+        uint32_t reserved_4:3;
+        /** slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wrparity_err_intstat:1;
+        /** slvif_undefinedreg_dec_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_undefinedreg_dec_err_intstat:1;
+        /** mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_correrr_intstat:1;
+        /** mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_uncorrerr_intstat:1;
+        /** mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_correrr_intstat:1;
+        /** mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_uncorrerr_intstat:1;
+        /** mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_correrr_intstat:1;
+        /** mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_uncorrerr_intstat:1;
+        /** mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_correrr_intstat:1;
+        /** mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_uncorrerr_intstat:1;
+        /** mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_correrr_intstat:1;
+        /** mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_uncorrerr_intstat:1;
+        /** mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_correrr_intstat:1;
+        /** mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_uncorrerr_intstat:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus0_reg_t;
+
+/** Type of ch1_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_block_tfr_done_intstat:1;
+        /** ch1_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch1_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_transcomp_intstat:1;
+        /** ch1_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_transcomp_intstat:1;
+        /** ch1_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_dec_err_intstat:1;
+        /** ch1_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_dec_err_intstat:1;
+        /** ch1_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_slv_err_intstat:1;
+        /** ch1_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_slv_err_intstat:1;
+        /** ch1_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_rd_dec_err_intstat:1;
+        /** ch1_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_wr_dec_err_intstat:1;
+        /** ch1_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_rd_slv_err_intstat:1;
+        /** ch1_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_wr_slv_err_intstat:1;
+        /** ch1_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch1_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch1_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_dec_err_intstat:1;
+        /** ch1_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wr2ro_err_intstat:1;
+        /** ch1_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_rd2rwo_err_intstat:1;
+        /** ch1_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wronchen_err_intstat:1;
+        /** ch1_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch1_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch1_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch1_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_lock_cleared_intstat:1;
+        /** ch1_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_src_suspended_intstat:1;
+        /** ch1_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_suspended_intstat:1;
+        /** ch1_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_disabled_intstat:1;
+        /** ch1_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch1_intstatus_enable0_reg_t;
+
+/** Type of ch1_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_chmem_correrr_intstat:1;
+        /** ch1_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch1_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch1_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch1_intstatus_enable1_reg_t;
+
+/** Type of ch1_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_block_tfr_done_intstat:1;
+        /** ch1_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch1_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_transcomp_intstat:1;
+        /** ch1_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_transcomp_intstat:1;
+        /** ch1_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_dec_err_intstat:1;
+        /** ch1_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_dec_err_intstat:1;
+        /** ch1_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_src_slv_err_intstat:1;
+        /** ch1_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dst_slv_err_intstat:1;
+        /** ch1_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lli_rd_dec_err_intstat:1;
+        /** ch1_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lli_wr_dec_err_intstat:1;
+        /** ch1_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lli_rd_slv_err_intstat:1;
+        /** ch1_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_lli_wr_slv_err_intstat:1;
+        /** ch1_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch1_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch1_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_dec_err_intstat:1;
+        /** ch1_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_wr2ro_err_intstat:1;
+        /** ch1_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_rd2rwo_err_intstat:1;
+        /** ch1_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_wronchen_err_intstat:1;
+        /** ch1_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch1_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch1_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch1_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_lock_cleared_intstat:1;
+        /** ch1_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_src_suspended_intstat:1;
+        /** ch1_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_suspended_intstat:1;
+        /** ch1_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_disabled_intstat:1;
+        /** ch1_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch1_intstatus0_reg_t;
+
+/** Type of ch1_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ecc_prot_chmem_correrr_intstat:1;
+        /** ch1_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch1_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch1_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch1_intstatus1_reg_t;
+
+/** Type of ch1_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_block_tfr_done_intsignal:1;
+        /** ch1_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dma_tfr_done_intsignal:1;
+        uint32_t reserved_2:1;
+        /** ch1_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_transcomp_intsignal:1;
+        /** ch1_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_transcomp_intsignal:1;
+        /** ch1_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_dec_err_intsignal:1;
+        /** ch1_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_dec_err_intsignal:1;
+        /** ch1_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_src_slv_err_intsignal:1;
+        /** ch1_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_dst_slv_err_intsignal:1;
+        /** ch1_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_rd_dec_err_intsignal:1;
+        /** ch1_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_wr_dec_err_intsignal:1;
+        /** ch1_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_rd_slv_err_intsignal:1;
+        /** ch1_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_lli_wr_slv_err_intsignal:1;
+        /** ch1_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_shadowreg_or_lli_invalid_err_intsignal:1;
+        /** ch1_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_multiblktype_err_intsignal:1;
+        uint32_t reserved_15:1;
+        /** ch1_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_dec_err_intsignal:1;
+        /** ch1_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wr2ro_err_intsignal:1;
+        /** ch1_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_rd2rwo_err_intsignal:1;
+        /** ch1_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wronchen_err_intsignal:1;
+        /** ch1_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
+        /** ch1_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wronhold_err_intsignal:1;
+        uint32_t reserved_22:3;
+        /** ch1_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_slvif_wrparity_err_intsignal:1;
+        uint32_t reserved_26:1;
+        /** ch1_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_lock_cleared_intsignal:1;
+        /** ch1_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_src_suspended_intsignal:1;
+        /** ch1_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_suspended_intsignal:1;
+        /** ch1_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_disabled_intsignal:1;
+        /** ch1_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ch_aborted_intsignal:1;
+    };
+    uint32_t val;
+} dmac_ch1_intsignal_enable0_reg_t;
+
+/** Type of ch1_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_chmem_correrr_intsignal:1;
+        /** ch1_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
+        /** ch1_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_uidmem_correrr_intsignal:1;
+        /** ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch1_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch1_intsignal_enable1_reg_t;
+
+/** Type of ch1_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_block_tfr_done_intstat:1;
+        /** ch1_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch1_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_src_transcomp_intstat:1;
+        /** ch1_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_dst_transcomp_intstat:1;
+        /** ch1_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_src_dec_err_intstat:1;
+        /** ch1_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_dst_dec_err_intstat:1;
+        /** ch1_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_src_slv_err_intstat:1;
+        /** ch1_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_dst_slv_err_intstat:1;
+        /** ch1_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_lli_rd_dec_err_intstat:1;
+        /** ch1_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_lli_wr_dec_err_intstat:1;
+        /** ch1_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_lli_rd_slv_err_intstat:1;
+        /** ch1_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_lli_wr_slv_err_intstat:1;
+        /** ch1_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch1_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch1_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_dec_err_intstat:1;
+        /** ch1_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_wr2ro_err_intstat:1;
+        /** ch1_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_rd2rwo_err_intstat:1;
+        /** ch1_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_wronchen_err_intstat:1;
+        /** ch1_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch1_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch1_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch1_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_lock_cleared_intstat:1;
+        /** ch1_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_src_suspended_intstat:1;
+        /** ch1_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_suspended_intstat:1;
+        /** ch1_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_disabled_intstat:1;
+        /** ch1_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch1_intclear0_reg_t;
+
+/** Type of ch1_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ecc_prot_chmem_correrr_intstat:1;
+        /** ch1_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch1_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch1_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch1_intclear1_reg_t;
+
+/** Type of ch2_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_block_tfr_done_intstat:1;
+        /** ch2_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch2_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_transcomp_intstat:1;
+        /** ch2_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_transcomp_intstat:1;
+        /** ch2_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_dec_err_intstat:1;
+        /** ch2_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_dec_err_intstat:1;
+        /** ch2_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_slv_err_intstat:1;
+        /** ch2_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_slv_err_intstat:1;
+        /** ch2_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_rd_dec_err_intstat:1;
+        /** ch2_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_wr_dec_err_intstat:1;
+        /** ch2_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_rd_slv_err_intstat:1;
+        /** ch2_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_wr_slv_err_intstat:1;
+        /** ch2_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch2_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch2_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_dec_err_intstat:1;
+        /** ch2_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wr2ro_err_intstat:1;
+        /** ch2_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_rd2rwo_err_intstat:1;
+        /** ch2_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wronchen_err_intstat:1;
+        /** ch2_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch2_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch2_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch2_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_lock_cleared_intstat:1;
+        /** ch2_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_src_suspended_intstat:1;
+        /** ch2_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_suspended_intstat:1;
+        /** ch2_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_disabled_intstat:1;
+        /** ch2_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch2_intstatus_enable0_reg_t;
+
+/** Type of ch2_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_chmem_correrr_intstat:1;
+        /** ch2_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch2_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch2_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch2_intstatus_enable1_reg_t;
+
+/** Type of ch2_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_block_tfr_done_intstat:1;
+        /** ch2_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch2_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_transcomp_intstat:1;
+        /** ch2_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_transcomp_intstat:1;
+        /** ch2_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_dec_err_intstat:1;
+        /** ch2_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_dec_err_intstat:1;
+        /** ch2_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_src_slv_err_intstat:1;
+        /** ch2_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dst_slv_err_intstat:1;
+        /** ch2_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lli_rd_dec_err_intstat:1;
+        /** ch2_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lli_wr_dec_err_intstat:1;
+        /** ch2_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lli_rd_slv_err_intstat:1;
+        /** ch2_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_lli_wr_slv_err_intstat:1;
+        /** ch2_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch2_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch2_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_dec_err_intstat:1;
+        /** ch2_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_wr2ro_err_intstat:1;
+        /** ch2_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_rd2rwo_err_intstat:1;
+        /** ch2_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_wronchen_err_intstat:1;
+        /** ch2_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch2_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch2_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch2_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_lock_cleared_intstat:1;
+        /** ch2_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_src_suspended_intstat:1;
+        /** ch2_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_suspended_intstat:1;
+        /** ch2_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_disabled_intstat:1;
+        /** ch2_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch2_intstatus0_reg_t;
+
+/** Type of ch2_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ecc_prot_chmem_correrr_intstat:1;
+        /** ch2_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch2_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch2_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch2_intstatus1_reg_t;
+
+/** Type of ch2_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_block_tfr_done_intsignal:1;
+        /** ch2_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dma_tfr_done_intsignal:1;
+        uint32_t reserved_2:1;
+        /** ch2_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_transcomp_intsignal:1;
+        /** ch2_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_transcomp_intsignal:1;
+        /** ch2_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_dec_err_intsignal:1;
+        /** ch2_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_dec_err_intsignal:1;
+        /** ch2_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_src_slv_err_intsignal:1;
+        /** ch2_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_dst_slv_err_intsignal:1;
+        /** ch2_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_rd_dec_err_intsignal:1;
+        /** ch2_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_wr_dec_err_intsignal:1;
+        /** ch2_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_rd_slv_err_intsignal:1;
+        /** ch2_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_lli_wr_slv_err_intsignal:1;
+        /** ch2_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_shadowreg_or_lli_invalid_err_intsignal:1;
+        /** ch2_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_multiblktype_err_intsignal:1;
+        uint32_t reserved_15:1;
+        /** ch2_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_dec_err_intsignal:1;
+        /** ch2_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wr2ro_err_intsignal:1;
+        /** ch2_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_rd2rwo_err_intsignal:1;
+        /** ch2_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wronchen_err_intsignal:1;
+        /** ch2_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
+        /** ch2_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wronhold_err_intsignal:1;
+        uint32_t reserved_22:3;
+        /** ch2_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_slvif_wrparity_err_intsignal:1;
+        uint32_t reserved_26:1;
+        /** ch2_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_lock_cleared_intsignal:1;
+        /** ch2_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_src_suspended_intsignal:1;
+        /** ch2_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_suspended_intsignal:1;
+        /** ch2_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_disabled_intsignal:1;
+        /** ch2_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ch_aborted_intsignal:1;
+    };
+    uint32_t val;
+} dmac_ch2_intsignal_enable0_reg_t;
+
+/** Type of ch2_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_chmem_correrr_intsignal:1;
+        /** ch2_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
+        /** ch2_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_uidmem_correrr_intsignal:1;
+        /** ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch2_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch2_intsignal_enable1_reg_t;
+
+/** Type of ch2_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_block_tfr_done_intstat:1;
+        /** ch2_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch2_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_src_transcomp_intstat:1;
+        /** ch2_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_dst_transcomp_intstat:1;
+        /** ch2_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_src_dec_err_intstat:1;
+        /** ch2_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_dst_dec_err_intstat:1;
+        /** ch2_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_src_slv_err_intstat:1;
+        /** ch2_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_dst_slv_err_intstat:1;
+        /** ch2_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_lli_rd_dec_err_intstat:1;
+        /** ch2_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_lli_wr_dec_err_intstat:1;
+        /** ch2_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_lli_rd_slv_err_intstat:1;
+        /** ch2_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_lli_wr_slv_err_intstat:1;
+        /** ch2_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch2_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch2_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_dec_err_intstat:1;
+        /** ch2_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_wr2ro_err_intstat:1;
+        /** ch2_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_rd2rwo_err_intstat:1;
+        /** ch2_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_wronchen_err_intstat:1;
+        /** ch2_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch2_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch2_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch2_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_lock_cleared_intstat:1;
+        /** ch2_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_src_suspended_intstat:1;
+        /** ch2_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_suspended_intstat:1;
+        /** ch2_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_disabled_intstat:1;
+        /** ch2_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch2_intclear0_reg_t;
+
+/** Type of ch2_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ecc_prot_chmem_correrr_intstat:1;
+        /** ch2_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch2_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch2_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch2_intclear1_reg_t;
+
+/** Type of ch3_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_block_tfr_done_intstat:1;
+        /** ch3_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch3_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_transcomp_intstat:1;
+        /** ch3_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_transcomp_intstat:1;
+        /** ch3_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_dec_err_intstat:1;
+        /** ch3_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_dec_err_intstat:1;
+        /** ch3_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_slv_err_intstat:1;
+        /** ch3_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_slv_err_intstat:1;
+        /** ch3_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_rd_dec_err_intstat:1;
+        /** ch3_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_wr_dec_err_intstat:1;
+        /** ch3_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_rd_slv_err_intstat:1;
+        /** ch3_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_wr_slv_err_intstat:1;
+        /** ch3_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch3_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch3_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_dec_err_intstat:1;
+        /** ch3_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wr2ro_err_intstat:1;
+        /** ch3_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_rd2rwo_err_intstat:1;
+        /** ch3_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wronchen_err_intstat:1;
+        /** ch3_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch3_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch3_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch3_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_lock_cleared_intstat:1;
+        /** ch3_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_src_suspended_intstat:1;
+        /** ch3_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_suspended_intstat:1;
+        /** ch3_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_disabled_intstat:1;
+        /** ch3_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch3_intstatus_enable0_reg_t;
+
+/** Type of ch3_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_chmem_correrr_intstat:1;
+        /** ch3_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch3_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch3_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch3_intstatus_enable1_reg_t;
+
+/** Type of ch3_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_block_tfr_done_intstat:1;
+        /** ch3_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch3_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_transcomp_intstat:1;
+        /** ch3_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_transcomp_intstat:1;
+        /** ch3_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_dec_err_intstat:1;
+        /** ch3_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_dec_err_intstat:1;
+        /** ch3_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_src_slv_err_intstat:1;
+        /** ch3_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dst_slv_err_intstat:1;
+        /** ch3_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lli_rd_dec_err_intstat:1;
+        /** ch3_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lli_wr_dec_err_intstat:1;
+        /** ch3_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lli_rd_slv_err_intstat:1;
+        /** ch3_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_lli_wr_slv_err_intstat:1;
+        /** ch3_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch3_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch3_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_dec_err_intstat:1;
+        /** ch3_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_wr2ro_err_intstat:1;
+        /** ch3_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_rd2rwo_err_intstat:1;
+        /** ch3_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_wronchen_err_intstat:1;
+        /** ch3_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch3_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch3_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch3_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_lock_cleared_intstat:1;
+        /** ch3_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_src_suspended_intstat:1;
+        /** ch3_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_suspended_intstat:1;
+        /** ch3_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_disabled_intstat:1;
+        /** ch3_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch3_intstatus0_reg_t;
+
+/** Type of ch3_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ecc_prot_chmem_correrr_intstat:1;
+        /** ch3_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch3_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch3_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch3_intstatus1_reg_t;
+
+/** Type of ch3_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_block_tfr_done_intsignal:1;
+        /** ch3_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dma_tfr_done_intsignal:1;
+        uint32_t reserved_2:1;
+        /** ch3_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_transcomp_intsignal:1;
+        /** ch3_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_transcomp_intsignal:1;
+        /** ch3_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_dec_err_intsignal:1;
+        /** ch3_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_dec_err_intsignal:1;
+        /** ch3_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_src_slv_err_intsignal:1;
+        /** ch3_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_dst_slv_err_intsignal:1;
+        /** ch3_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_rd_dec_err_intsignal:1;
+        /** ch3_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_wr_dec_err_intsignal:1;
+        /** ch3_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_rd_slv_err_intsignal:1;
+        /** ch3_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_lli_wr_slv_err_intsignal:1;
+        /** ch3_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_shadowreg_or_lli_invalid_err_intsignal:1;
+        /** ch3_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_multiblktype_err_intsignal:1;
+        uint32_t reserved_15:1;
+        /** ch3_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_dec_err_intsignal:1;
+        /** ch3_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wr2ro_err_intsignal:1;
+        /** ch3_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_rd2rwo_err_intsignal:1;
+        /** ch3_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wronchen_err_intsignal:1;
+        /** ch3_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
+        /** ch3_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wronhold_err_intsignal:1;
+        uint32_t reserved_22:3;
+        /** ch3_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_slvif_wrparity_err_intsignal:1;
+        uint32_t reserved_26:1;
+        /** ch3_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_lock_cleared_intsignal:1;
+        /** ch3_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_src_suspended_intsignal:1;
+        /** ch3_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_suspended_intsignal:1;
+        /** ch3_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_disabled_intsignal:1;
+        /** ch3_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ch_aborted_intsignal:1;
+    };
+    uint32_t val;
+} dmac_ch3_intsignal_enable0_reg_t;
+
+/** Type of ch3_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_chmem_correrr_intsignal:1;
+        /** ch3_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
+        /** ch3_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_uidmem_correrr_intsignal:1;
+        /** ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch3_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch3_intsignal_enable1_reg_t;
+
+/** Type of ch3_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_block_tfr_done_intstat:1;
+        /** ch3_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch3_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_src_transcomp_intstat:1;
+        /** ch3_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_dst_transcomp_intstat:1;
+        /** ch3_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_src_dec_err_intstat:1;
+        /** ch3_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_dst_dec_err_intstat:1;
+        /** ch3_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_src_slv_err_intstat:1;
+        /** ch3_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_dst_slv_err_intstat:1;
+        /** ch3_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_lli_rd_dec_err_intstat:1;
+        /** ch3_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_lli_wr_dec_err_intstat:1;
+        /** ch3_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_lli_rd_slv_err_intstat:1;
+        /** ch3_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_lli_wr_slv_err_intstat:1;
+        /** ch3_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch3_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch3_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_dec_err_intstat:1;
+        /** ch3_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_wr2ro_err_intstat:1;
+        /** ch3_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_rd2rwo_err_intstat:1;
+        /** ch3_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_wronchen_err_intstat:1;
+        /** ch3_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch3_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch3_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch3_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_lock_cleared_intstat:1;
+        /** ch3_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_src_suspended_intstat:1;
+        /** ch3_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_suspended_intstat:1;
+        /** ch3_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_disabled_intstat:1;
+        /** ch3_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch3_intclear0_reg_t;
+
+/** Type of ch3_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ecc_prot_chmem_correrr_intstat:1;
+        /** ch3_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch3_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch3_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch3_intclear1_reg_t;
+
+/** Type of ch4_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_block_tfr_done_intstat:1;
+        /** ch4_enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch4_enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_transcomp_intstat:1;
+        /** ch4_enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_transcomp_intstat:1;
+        /** ch4_enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_dec_err_intstat:1;
+        /** ch4_enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_dec_err_intstat:1;
+        /** ch4_enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_slv_err_intstat:1;
+        /** ch4_enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_slv_err_intstat:1;
+        /** ch4_enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_rd_dec_err_intstat:1;
+        /** ch4_enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_wr_dec_err_intstat:1;
+        /** ch4_enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_rd_slv_err_intstat:1;
+        /** ch4_enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_wr_slv_err_intstat:1;
+        /** ch4_enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch4_enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch4_enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_dec_err_intstat:1;
+        /** ch4_enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wr2ro_err_intstat:1;
+        /** ch4_enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_rd2rwo_err_intstat:1;
+        /** ch4_enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wronchen_err_intstat:1;
+        /** ch4_enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch4_enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch4_enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch4_enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_lock_cleared_intstat:1;
+        /** ch4_enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_src_suspended_intstat:1;
+        /** ch4_enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_suspended_intstat:1;
+        /** ch4_enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_disabled_intstat:1;
+        /** ch4_enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch4_intstatus_enable0_reg_t;
+
+/** Type of ch4_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_chmem_correrr_intstat:1;
+        /** ch4_enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch4_enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch4_enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch4_intstatus_enable1_reg_t;
+
+/** Type of ch4_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_block_tfr_done_intstat:1;
+        /** ch4_dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch4_src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_transcomp_intstat:1;
+        /** ch4_dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_transcomp_intstat:1;
+        /** ch4_src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_dec_err_intstat:1;
+        /** ch4_dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_dec_err_intstat:1;
+        /** ch4_src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_src_slv_err_intstat:1;
+        /** ch4_dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dst_slv_err_intstat:1;
+        /** ch4_lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lli_rd_dec_err_intstat:1;
+        /** ch4_lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lli_wr_dec_err_intstat:1;
+        /** ch4_lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lli_rd_slv_err_intstat:1;
+        /** ch4_lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_lli_wr_slv_err_intstat:1;
+        /** ch4_shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch4_slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch4_slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_dec_err_intstat:1;
+        /** ch4_slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_wr2ro_err_intstat:1;
+        /** ch4_slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_rd2rwo_err_intstat:1;
+        /** ch4_slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_wronchen_err_intstat:1;
+        /** ch4_slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch4_slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch4_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch4_ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_lock_cleared_intstat:1;
+        /** ch4_ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_src_suspended_intstat:1;
+        /** ch4_ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_suspended_intstat:1;
+        /** ch4_ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_disabled_intstat:1;
+        /** ch4_ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch4_intstatus0_reg_t;
+
+/** Type of ch4_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ecc_prot_chmem_correrr_intstat:1;
+        /** ch4_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch4_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch4_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch4_intstatus1_reg_t;
+
+/** Type of ch4_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_block_tfr_done_intsignal:1;
+        /** ch4_enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dma_tfr_done_intsignal:1;
+        uint32_t reserved_2:1;
+        /** ch4_enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_transcomp_intsignal:1;
+        /** ch4_enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_transcomp_intsignal:1;
+        /** ch4_enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_dec_err_intsignal:1;
+        /** ch4_enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_dec_err_intsignal:1;
+        /** ch4_enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_src_slv_err_intsignal:1;
+        /** ch4_enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_dst_slv_err_intsignal:1;
+        /** ch4_enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_rd_dec_err_intsignal:1;
+        /** ch4_enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_wr_dec_err_intsignal:1;
+        /** ch4_enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_rd_slv_err_intsignal:1;
+        /** ch4_enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_lli_wr_slv_err_intsignal:1;
+        /** ch4_enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_shadowreg_or_lli_invalid_err_intsignal:1;
+        /** ch4_enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_multiblktype_err_intsignal:1;
+        uint32_t reserved_15:1;
+        /** ch4_enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_dec_err_intsignal:1;
+        /** ch4_enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wr2ro_err_intsignal:1;
+        /** ch4_enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_rd2rwo_err_intsignal:1;
+        /** ch4_enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wronchen_err_intsignal:1;
+        /** ch4_enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_shadowreg_wron_valid_err_intsignal:1;
+        /** ch4_enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wronhold_err_intsignal:1;
+        uint32_t reserved_22:3;
+        /** ch4_enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_slvif_wrparity_err_intsignal:1;
+        uint32_t reserved_26:1;
+        /** ch4_enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_lock_cleared_intsignal:1;
+        /** ch4_enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_src_suspended_intsignal:1;
+        /** ch4_enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_suspended_intsignal:1;
+        /** ch4_enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_disabled_intsignal:1;
+        /** ch4_enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ch_aborted_intsignal:1;
+    };
+    uint32_t val;
+} dmac_ch4_intsignal_enable0_reg_t;
+
+/** Type of ch4_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_chmem_correrr_intsignal:1;
+        /** ch4_enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_chmem_uncorrerr_intsignal:1;
+        /** ch4_enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_uidmem_correrr_intsignal:1;
+        /** ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t ch4_enable_ecc_prot_uidmem_uncorrerr_intsignal:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch4_intsignal_enable1_reg_t;
+
+/** Type of ch4_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_block_tfr_done_intstat:1;
+        /** ch4_clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_dma_tfr_done_intstat:1;
+        uint32_t reserved_2:1;
+        /** ch4_clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_src_transcomp_intstat:1;
+        /** ch4_clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_dst_transcomp_intstat:1;
+        /** ch4_clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_src_dec_err_intstat:1;
+        /** ch4_clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_dst_dec_err_intstat:1;
+        /** ch4_clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_src_slv_err_intstat:1;
+        /** ch4_clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_dst_slv_err_intstat:1;
+        /** ch4_clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_lli_rd_dec_err_intstat:1;
+        /** ch4_clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_lli_wr_dec_err_intstat:1;
+        /** ch4_clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_lli_rd_slv_err_intstat:1;
+        /** ch4_clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_lli_wr_slv_err_intstat:1;
+        /** ch4_clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_shadowreg_or_lli_invalid_err_intstat:1;
+        /** ch4_clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_multiblktype_err_intstat:1;
+        uint32_t reserved_15:1;
+        /** ch4_clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_dec_err_intstat:1;
+        /** ch4_clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_wr2ro_err_intstat:1;
+        /** ch4_clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_rd2rwo_err_intstat:1;
+        /** ch4_clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_wronchen_err_intstat:1;
+        /** ch4_clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_shadowreg_wron_valid_err_intstat:1;
+        /** ch4_clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_wronhold_err_intstat:1;
+        uint32_t reserved_22:3;
+        /** ch4_clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_slvif_wrparity_err_intstat:1;
+        uint32_t reserved_26:1;
+        /** ch4_clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_lock_cleared_intstat:1;
+        /** ch4_clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_src_suspended_intstat:1;
+        /** ch4_clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_suspended_intstat:1;
+        /** ch4_clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_disabled_intstat:1;
+        /** ch4_clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ch_aborted_intstat:1;
+    };
+    uint32_t val;
+} dmac_ch4_intclear0_reg_t;
+
+/** Type of ch4_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ecc_prot_chmem_correrr_intstat:1;
+        /** ch4_clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ecc_prot_chmem_uncorrerr_intstat:1;
+        /** ch4_clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ecc_prot_uidmem_correrr_intstat:1;
+        /** ch4_clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_clear_ecc_prot_uidmem_uncorrerr_intstat:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dmac_ch4_intclear1_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of ch1_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_cmpltd_blk_tfr_size:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch1_status0_reg_t;
+
+/** Type of ch1_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_data_left_in_fifo:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dmac_ch1_status1_reg_t;
+
+/** Type of ch1_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sstat:32;
+    };
+    uint32_t val;
+} dmac_ch1_sstat0_reg_t;
+
+/** Type of ch1_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dstat:32;
+    };
+    uint32_t val;
+} dmac_ch1_dstat0_reg_t;
+
+/** Type of ch1_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch1_sstatar0_reg_t;
+
+/** Type of ch1_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_sstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch1_sstatar1_reg_t;
+
+/** Type of ch1_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch1_dstatar0_reg_t;
+
+/** Type of ch1_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_dstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch1_dstatar1_reg_t;
+
+/** Type of ch2_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_cmpltd_blk_tfr_size:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch2_status0_reg_t;
+
+/** Type of ch2_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_data_left_in_fifo:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dmac_ch2_status1_reg_t;
+
+/** Type of ch2_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sstat:32;
+    };
+    uint32_t val;
+} dmac_ch2_sstat0_reg_t;
+
+/** Type of ch2_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dstat:32;
+    };
+    uint32_t val;
+} dmac_ch2_dstat0_reg_t;
+
+/** Type of ch2_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch2_sstatar0_reg_t;
+
+/** Type of ch2_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_sstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch2_sstatar1_reg_t;
+
+/** Type of ch2_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch2_dstatar0_reg_t;
+
+/** Type of ch2_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch2_dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_dstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch2_dstatar1_reg_t;
+
+/** Type of ch3_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_cmpltd_blk_tfr_size:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch3_status0_reg_t;
+
+/** Type of ch3_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_data_left_in_fifo:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dmac_ch3_status1_reg_t;
+
+/** Type of ch3_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sstat:32;
+    };
+    uint32_t val;
+} dmac_ch3_sstat0_reg_t;
+
+/** Type of ch3_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dstat:32;
+    };
+    uint32_t val;
+} dmac_ch3_dstat0_reg_t;
+
+/** Type of ch3_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch3_sstatar0_reg_t;
+
+/** Type of ch3_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_sstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch3_sstatar1_reg_t;
+
+/** Type of ch3_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch3_dstatar0_reg_t;
+
+/** Type of ch3_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch3_dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_dstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch3_dstatar1_reg_t;
+
+/** Type of ch4_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_cmpltd_blk_tfr_size:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} dmac_ch4_status0_reg_t;
+
+/** Type of ch4_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_data_left_in_fifo:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} dmac_ch4_status1_reg_t;
+
+/** Type of ch4_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sstat:32;
+    };
+    uint32_t val;
+} dmac_ch4_sstat0_reg_t;
+
+/** Type of ch4_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dstat:32;
+    };
+    uint32_t val;
+} dmac_ch4_dstat0_reg_t;
+
+/** Type of ch4_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch4_sstatar0_reg_t;
+
+/** Type of ch4_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_sstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch4_sstatar1_reg_t;
+
+/** Type of ch4_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dstatar0:32;
+    };
+    uint32_t val;
+} dmac_ch4_dstatar0_reg_t;
+
+/** Type of ch4_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch4_dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_dstatar1:32;
+    };
+    uint32_t val;
+} dmac_ch4_dstatar1_reg_t;
+
+
+typedef struct {
+    volatile dmac_id0_reg_t id0;
+    uint32_t reserved_004;
+    volatile dmac_compver0_reg_t compver0;
+    uint32_t reserved_00c;
+    volatile dmac_cfg0_reg_t cfg0;
+    uint32_t reserved_014;
+    volatile dmac_chen0_reg_t chen0;
+    volatile dmac_chen1_reg_t chen1;
+    uint32_t reserved_020[4];
+    volatile dmac_intstatus0_reg_t intstatus0;
+    uint32_t reserved_034;
+    volatile dmac_commonreg_intclear0_reg_t commonreg_intclear0;
+    uint32_t reserved_03c;
+    volatile dmac_commonreg_intstatus_enable0_reg_t commonreg_intstatus_enable0;
+    uint32_t reserved_044;
+    volatile dmac_commonreg_intsignal_enable0_reg_t commonreg_intsignal_enable0;
+    uint32_t reserved_04c;
+    volatile dmac_commonreg_intstatus0_reg_t commonreg_intstatus0;
+    uint32_t reserved_054;
+    volatile dmac_reset0_reg_t reset0;
+    uint32_t reserved_05c;
+    volatile dmac_lowpower_cfg0_reg_t lowpower_cfg0;
+    volatile dmac_lowpower_cfg1_reg_t lowpower_cfg1;
+    uint32_t reserved_068[38];
+    volatile dmac_ch1_sar0_reg_t ch1_sar0;
+    volatile dmac_ch1_sar1_reg_t ch1_sar1;
+    volatile dmac_ch1_dar0_reg_t ch1_dar0;
+    volatile dmac_ch1_dar1_reg_t ch1_dar1;
+    volatile dmac_ch1_block_ts0_reg_t ch1_block_ts0;
+    uint32_t reserved_114;
+    volatile dmac_ch1_ctl0_reg_t ch1_ctl0;
+    volatile dmac_ch1_ctl1_reg_t ch1_ctl1;
+    volatile dmac_ch1_cfg0_reg_t ch1_cfg0;
+    volatile dmac_ch1_cfg1_reg_t ch1_cfg1;
+    volatile dmac_ch1_llp0_reg_t ch1_llp0;
+    volatile dmac_ch1_llp1_reg_t ch1_llp1;
+    volatile dmac_ch1_status0_reg_t ch1_status0;
+    volatile dmac_ch1_status1_reg_t ch1_status1;
+    volatile dmac_ch1_swhssrc0_reg_t ch1_swhssrc0;
+    uint32_t reserved_13c;
+    volatile dmac_ch1_swhsdst0_reg_t ch1_swhsdst0;
+    uint32_t reserved_144;
+    volatile dmac_ch1_blk_tfr_resumereq0_reg_t ch1_blk_tfr_resumereq0;
+    uint32_t reserved_14c;
+    volatile dmac_ch1_axi_id0_reg_t ch1_axi_id0;
+    uint32_t reserved_154;
+    volatile dmac_ch1_axi_qos0_reg_t ch1_axi_qos0;
+    uint32_t reserved_15c;
+    volatile dmac_ch1_sstat0_reg_t ch1_sstat0;
+    uint32_t reserved_164;
+    volatile dmac_ch1_dstat0_reg_t ch1_dstat0;
+    uint32_t reserved_16c;
+    volatile dmac_ch1_sstatar0_reg_t ch1_sstatar0;
+    volatile dmac_ch1_sstatar1_reg_t ch1_sstatar1;
+    volatile dmac_ch1_dstatar0_reg_t ch1_dstatar0;
+    volatile dmac_ch1_dstatar1_reg_t ch1_dstatar1;
+    volatile dmac_ch1_intstatus_enable0_reg_t ch1_intstatus_enable0;
+    volatile dmac_ch1_intstatus_enable1_reg_t ch1_intstatus_enable1;
+    volatile dmac_ch1_intstatus0_reg_t ch1_intstatus0;
+    volatile dmac_ch1_intstatus1_reg_t ch1_intstatus1;
+    volatile dmac_ch1_intsignal_enable0_reg_t ch1_intsignal_enable0;
+    volatile dmac_ch1_intsignal_enable1_reg_t ch1_intsignal_enable1;
+    volatile dmac_ch1_intclear0_reg_t ch1_intclear0;
+    volatile dmac_ch1_intclear1_reg_t ch1_intclear1;
+    uint32_t reserved_1a0[24];
+    volatile dmac_ch2_sar0_reg_t ch2_sar0;
+    volatile dmac_ch2_sar1_reg_t ch2_sar1;
+    volatile dmac_ch2_dar0_reg_t ch2_dar0;
+    volatile dmac_ch2_dar1_reg_t ch2_dar1;
+    volatile dmac_ch2_block_ts0_reg_t ch2_block_ts0;
+    uint32_t reserved_214;
+    volatile dmac_ch2_ctl0_reg_t ch2_ctl0;
+    volatile dmac_ch2_ctl1_reg_t ch2_ctl1;
+    volatile dmac_ch2_cfg0_reg_t ch2_cfg0;
+    volatile dmac_ch2_cfg1_reg_t ch2_cfg1;
+    volatile dmac_ch2_llp0_reg_t ch2_llp0;
+    volatile dmac_ch2_llp1_reg_t ch2_llp1;
+    volatile dmac_ch2_status0_reg_t ch2_status0;
+    volatile dmac_ch2_status1_reg_t ch2_status1;
+    volatile dmac_ch2_swhssrc0_reg_t ch2_swhssrc0;
+    uint32_t reserved_23c;
+    volatile dmac_ch2_swhsdst0_reg_t ch2_swhsdst0;
+    uint32_t reserved_244;
+    volatile dmac_ch2_blk_tfr_resumereq0_reg_t ch2_blk_tfr_resumereq0;
+    uint32_t reserved_24c;
+    volatile dmac_ch2_axi_id0_reg_t ch2_axi_id0;
+    uint32_t reserved_254;
+    volatile dmac_ch2_axi_qos0_reg_t ch2_axi_qos0;
+    uint32_t reserved_25c;
+    volatile dmac_ch2_sstat0_reg_t ch2_sstat0;
+    uint32_t reserved_264;
+    volatile dmac_ch2_dstat0_reg_t ch2_dstat0;
+    uint32_t reserved_26c;
+    volatile dmac_ch2_sstatar0_reg_t ch2_sstatar0;
+    volatile dmac_ch2_sstatar1_reg_t ch2_sstatar1;
+    volatile dmac_ch2_dstatar0_reg_t ch2_dstatar0;
+    volatile dmac_ch2_dstatar1_reg_t ch2_dstatar1;
+    volatile dmac_ch2_intstatus_enable0_reg_t ch2_intstatus_enable0;
+    volatile dmac_ch2_intstatus_enable1_reg_t ch2_intstatus_enable1;
+    volatile dmac_ch2_intstatus0_reg_t ch2_intstatus0;
+    volatile dmac_ch2_intstatus1_reg_t ch2_intstatus1;
+    volatile dmac_ch2_intsignal_enable0_reg_t ch2_intsignal_enable0;
+    volatile dmac_ch2_intsignal_enable1_reg_t ch2_intsignal_enable1;
+    volatile dmac_ch2_intclear0_reg_t ch2_intclear0;
+    volatile dmac_ch2_intclear1_reg_t ch2_intclear1;
+    uint32_t reserved_2a0[24];
+    volatile dmac_ch3_sar0_reg_t ch3_sar0;
+    volatile dmac_ch3_sar1_reg_t ch3_sar1;
+    volatile dmac_ch3_dar0_reg_t ch3_dar0;
+    volatile dmac_ch3_dar1_reg_t ch3_dar1;
+    volatile dmac_ch3_block_ts0_reg_t ch3_block_ts0;
+    uint32_t reserved_314;
+    volatile dmac_ch3_ctl0_reg_t ch3_ctl0;
+    volatile dmac_ch3_ctl1_reg_t ch3_ctl1;
+    volatile dmac_ch3_cfg0_reg_t ch3_cfg0;
+    volatile dmac_ch3_cfg1_reg_t ch3_cfg1;
+    volatile dmac_ch3_llp0_reg_t ch3_llp0;
+    volatile dmac_ch3_llp1_reg_t ch3_llp1;
+    volatile dmac_ch3_status0_reg_t ch3_status0;
+    volatile dmac_ch3_status1_reg_t ch3_status1;
+    volatile dmac_ch3_swhssrc0_reg_t ch3_swhssrc0;
+    uint32_t reserved_33c;
+    volatile dmac_ch3_swhsdst0_reg_t ch3_swhsdst0;
+    uint32_t reserved_344;
+    volatile dmac_ch3_blk_tfr_resumereq0_reg_t ch3_blk_tfr_resumereq0;
+    uint32_t reserved_34c;
+    volatile dmac_ch3_axi_id0_reg_t ch3_axi_id0;
+    uint32_t reserved_354;
+    volatile dmac_ch3_axi_qos0_reg_t ch3_axi_qos0;
+    uint32_t reserved_35c;
+    volatile dmac_ch3_sstat0_reg_t ch3_sstat0;
+    uint32_t reserved_364;
+    volatile dmac_ch3_dstat0_reg_t ch3_dstat0;
+    uint32_t reserved_36c;
+    volatile dmac_ch3_sstatar0_reg_t ch3_sstatar0;
+    volatile dmac_ch3_sstatar1_reg_t ch3_sstatar1;
+    volatile dmac_ch3_dstatar0_reg_t ch3_dstatar0;
+    volatile dmac_ch3_dstatar1_reg_t ch3_dstatar1;
+    volatile dmac_ch3_intstatus_enable0_reg_t ch3_intstatus_enable0;
+    volatile dmac_ch3_intstatus_enable1_reg_t ch3_intstatus_enable1;
+    volatile dmac_ch3_intstatus0_reg_t ch3_intstatus0;
+    volatile dmac_ch3_intstatus1_reg_t ch3_intstatus1;
+    volatile dmac_ch3_intsignal_enable0_reg_t ch3_intsignal_enable0;
+    volatile dmac_ch3_intsignal_enable1_reg_t ch3_intsignal_enable1;
+    volatile dmac_ch3_intclear0_reg_t ch3_intclear0;
+    volatile dmac_ch3_intclear1_reg_t ch3_intclear1;
+    uint32_t reserved_3a0[24];
+    volatile dmac_ch4_sar0_reg_t ch4_sar0;
+    volatile dmac_ch4_sar1_reg_t ch4_sar1;
+    volatile dmac_ch4_dar0_reg_t ch4_dar0;
+    volatile dmac_ch4_dar1_reg_t ch4_dar1;
+    volatile dmac_ch4_block_ts0_reg_t ch4_block_ts0;
+    uint32_t reserved_414;
+    volatile dmac_ch4_ctl0_reg_t ch4_ctl0;
+    volatile dmac_ch4_ctl1_reg_t ch4_ctl1;
+    volatile dmac_ch4_cfg0_reg_t ch4_cfg0;
+    volatile dmac_ch4_cfg1_reg_t ch4_cfg1;
+    volatile dmac_ch4_llp0_reg_t ch4_llp0;
+    volatile dmac_ch4_llp1_reg_t ch4_llp1;
+    volatile dmac_ch4_status0_reg_t ch4_status0;
+    volatile dmac_ch4_status1_reg_t ch4_status1;
+    volatile dmac_ch4_swhssrc0_reg_t ch4_swhssrc0;
+    uint32_t reserved_43c;
+    volatile dmac_ch4_swhsdst0_reg_t ch4_swhsdst0;
+    uint32_t reserved_444;
+    volatile dmac_ch4_blk_tfr_resumereq0_reg_t ch4_blk_tfr_resumereq0;
+    uint32_t reserved_44c;
+    volatile dmac_ch4_axi_id0_reg_t ch4_axi_id0;
+    uint32_t reserved_454;
+    volatile dmac_ch4_axi_qos0_reg_t ch4_axi_qos0;
+    uint32_t reserved_45c;
+    volatile dmac_ch4_sstat0_reg_t ch4_sstat0;
+    uint32_t reserved_464;
+    volatile dmac_ch4_dstat0_reg_t ch4_dstat0;
+    uint32_t reserved_46c;
+    volatile dmac_ch4_sstatar0_reg_t ch4_sstatar0;
+    volatile dmac_ch4_sstatar1_reg_t ch4_sstatar1;
+    volatile dmac_ch4_dstatar0_reg_t ch4_dstatar0;
+    volatile dmac_ch4_dstatar1_reg_t ch4_dstatar1;
+    volatile dmac_ch4_intstatus_enable0_reg_t ch4_intstatus_enable0;
+    volatile dmac_ch4_intstatus_enable1_reg_t ch4_intstatus_enable1;
+    volatile dmac_ch4_intstatus0_reg_t ch4_intstatus0;
+    volatile dmac_ch4_intstatus1_reg_t ch4_intstatus1;
+    volatile dmac_ch4_intsignal_enable0_reg_t ch4_intsignal_enable0;
+    volatile dmac_ch4_intsignal_enable1_reg_t ch4_intsignal_enable1;
+    volatile dmac_ch4_intclear0_reg_t ch4_intclear0;
+    volatile dmac_ch4_intclear1_reg_t ch4_intclear1;
+} dmac_dev_t;
+
+extern dmac_dev_t GDMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dmac_dev_t) == 0x4a0, "Invalid size of dmac_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_reg.h
new file mode 100644
index 0000000000..6aa7a720ed
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_reg.h
@@ -0,0 +1,6880 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DMAC_ID0_REG register
+ *  NA
+ */
+#define DMAC_ID0_REG (DR_REG_DMAC_BASE + 0x0)
+/** DMAC_DMAC_ID : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_DMAC_ID    0xFFFFFFFFU
+#define DMAC_DMAC_ID_M  (DMAC_DMAC_ID_V << DMAC_DMAC_ID_S)
+#define DMAC_DMAC_ID_V  0xFFFFFFFFU
+#define DMAC_DMAC_ID_S  0
+
+/** DMAC_COMPVER0_REG register
+ *  NA
+ */
+#define DMAC_COMPVER0_REG (DR_REG_DMAC_BASE + 0x8)
+/** DMAC_DMAC_COMPVER : RO; bitpos: [31:0]; default: 842018858;
+ *  NA
+ */
+#define DMAC_DMAC_COMPVER    0xFFFFFFFFU
+#define DMAC_DMAC_COMPVER_M  (DMAC_DMAC_COMPVER_V << DMAC_DMAC_COMPVER_S)
+#define DMAC_DMAC_COMPVER_V  0xFFFFFFFFU
+#define DMAC_DMAC_COMPVER_S  0
+
+/** DMAC_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CFG0_REG (DR_REG_DMAC_BASE + 0x10)
+/** DMAC_DMAC_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_DMAC_EN    (BIT(0))
+#define DMAC_DMAC_EN_M  (DMAC_DMAC_EN_V << DMAC_DMAC_EN_S)
+#define DMAC_DMAC_EN_V  0x00000001U
+#define DMAC_DMAC_EN_S  0
+/** DMAC_INT_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_INT_EN    (BIT(1))
+#define DMAC_INT_EN_M  (DMAC_INT_EN_V << DMAC_INT_EN_S)
+#define DMAC_INT_EN_V  0x00000001U
+#define DMAC_INT_EN_S  1
+
+/** DMAC_CHEN0_REG register
+ *  NA
+ */
+#define DMAC_CHEN0_REG (DR_REG_DMAC_BASE + 0x18)
+/** DMAC_CH1_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_EN    (BIT(0))
+#define DMAC_CH1_EN_M  (DMAC_CH1_EN_V << DMAC_CH1_EN_S)
+#define DMAC_CH1_EN_V  0x00000001U
+#define DMAC_CH1_EN_S  0
+/** DMAC_CH2_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_EN    (BIT(1))
+#define DMAC_CH2_EN_M  (DMAC_CH2_EN_V << DMAC_CH2_EN_S)
+#define DMAC_CH2_EN_V  0x00000001U
+#define DMAC_CH2_EN_S  1
+/** DMAC_CH3_EN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_EN    (BIT(2))
+#define DMAC_CH3_EN_M  (DMAC_CH3_EN_V << DMAC_CH3_EN_S)
+#define DMAC_CH3_EN_V  0x00000001U
+#define DMAC_CH3_EN_S  2
+/** DMAC_CH4_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_EN    (BIT(3))
+#define DMAC_CH4_EN_M  (DMAC_CH4_EN_V << DMAC_CH4_EN_S)
+#define DMAC_CH4_EN_V  0x00000001U
+#define DMAC_CH4_EN_S  3
+/** DMAC_CH1_EN_WE : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_EN_WE    (BIT(8))
+#define DMAC_CH1_EN_WE_M  (DMAC_CH1_EN_WE_V << DMAC_CH1_EN_WE_S)
+#define DMAC_CH1_EN_WE_V  0x00000001U
+#define DMAC_CH1_EN_WE_S  8
+/** DMAC_CH2_EN_WE : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_EN_WE    (BIT(9))
+#define DMAC_CH2_EN_WE_M  (DMAC_CH2_EN_WE_V << DMAC_CH2_EN_WE_S)
+#define DMAC_CH2_EN_WE_V  0x00000001U
+#define DMAC_CH2_EN_WE_S  9
+/** DMAC_CH3_EN_WE : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_EN_WE    (BIT(10))
+#define DMAC_CH3_EN_WE_M  (DMAC_CH3_EN_WE_V << DMAC_CH3_EN_WE_S)
+#define DMAC_CH3_EN_WE_V  0x00000001U
+#define DMAC_CH3_EN_WE_S  10
+/** DMAC_CH4_EN_WE : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_EN_WE    (BIT(11))
+#define DMAC_CH4_EN_WE_M  (DMAC_CH4_EN_WE_V << DMAC_CH4_EN_WE_S)
+#define DMAC_CH4_EN_WE_V  0x00000001U
+#define DMAC_CH4_EN_WE_S  11
+/** DMAC_CH1_SUSP : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SUSP    (BIT(16))
+#define DMAC_CH1_SUSP_M  (DMAC_CH1_SUSP_V << DMAC_CH1_SUSP_S)
+#define DMAC_CH1_SUSP_V  0x00000001U
+#define DMAC_CH1_SUSP_S  16
+/** DMAC_CH2_SUSP : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SUSP    (BIT(17))
+#define DMAC_CH2_SUSP_M  (DMAC_CH2_SUSP_V << DMAC_CH2_SUSP_S)
+#define DMAC_CH2_SUSP_V  0x00000001U
+#define DMAC_CH2_SUSP_S  17
+/** DMAC_CH3_SUSP : R/W; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SUSP    (BIT(18))
+#define DMAC_CH3_SUSP_M  (DMAC_CH3_SUSP_V << DMAC_CH3_SUSP_S)
+#define DMAC_CH3_SUSP_V  0x00000001U
+#define DMAC_CH3_SUSP_S  18
+/** DMAC_CH4_SUSP : R/W; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SUSP    (BIT(19))
+#define DMAC_CH4_SUSP_M  (DMAC_CH4_SUSP_V << DMAC_CH4_SUSP_S)
+#define DMAC_CH4_SUSP_V  0x00000001U
+#define DMAC_CH4_SUSP_S  19
+/** DMAC_CH1_SUSP_WE : WO; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SUSP_WE    (BIT(24))
+#define DMAC_CH1_SUSP_WE_M  (DMAC_CH1_SUSP_WE_V << DMAC_CH1_SUSP_WE_S)
+#define DMAC_CH1_SUSP_WE_V  0x00000001U
+#define DMAC_CH1_SUSP_WE_S  24
+/** DMAC_CH2_SUSP_WE : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SUSP_WE    (BIT(25))
+#define DMAC_CH2_SUSP_WE_M  (DMAC_CH2_SUSP_WE_V << DMAC_CH2_SUSP_WE_S)
+#define DMAC_CH2_SUSP_WE_V  0x00000001U
+#define DMAC_CH2_SUSP_WE_S  25
+/** DMAC_CH3_SUSP_WE : WO; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SUSP_WE    (BIT(26))
+#define DMAC_CH3_SUSP_WE_M  (DMAC_CH3_SUSP_WE_V << DMAC_CH3_SUSP_WE_S)
+#define DMAC_CH3_SUSP_WE_V  0x00000001U
+#define DMAC_CH3_SUSP_WE_S  26
+/** DMAC_CH4_SUSP_WE : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SUSP_WE    (BIT(27))
+#define DMAC_CH4_SUSP_WE_M  (DMAC_CH4_SUSP_WE_V << DMAC_CH4_SUSP_WE_S)
+#define DMAC_CH4_SUSP_WE_V  0x00000001U
+#define DMAC_CH4_SUSP_WE_S  27
+
+/** DMAC_CHEN1_REG register
+ *  NA
+ */
+#define DMAC_CHEN1_REG (DR_REG_DMAC_BASE + 0x1c)
+/** DMAC_CH1_ABORT : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ABORT    (BIT(0))
+#define DMAC_CH1_ABORT_M  (DMAC_CH1_ABORT_V << DMAC_CH1_ABORT_S)
+#define DMAC_CH1_ABORT_V  0x00000001U
+#define DMAC_CH1_ABORT_S  0
+/** DMAC_CH2_ABORT : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ABORT    (BIT(1))
+#define DMAC_CH2_ABORT_M  (DMAC_CH2_ABORT_V << DMAC_CH2_ABORT_S)
+#define DMAC_CH2_ABORT_V  0x00000001U
+#define DMAC_CH2_ABORT_S  1
+/** DMAC_CH3_ABORT : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ABORT    (BIT(2))
+#define DMAC_CH3_ABORT_M  (DMAC_CH3_ABORT_V << DMAC_CH3_ABORT_S)
+#define DMAC_CH3_ABORT_V  0x00000001U
+#define DMAC_CH3_ABORT_S  2
+/** DMAC_CH4_ABORT : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ABORT    (BIT(3))
+#define DMAC_CH4_ABORT_M  (DMAC_CH4_ABORT_V << DMAC_CH4_ABORT_S)
+#define DMAC_CH4_ABORT_V  0x00000001U
+#define DMAC_CH4_ABORT_S  3
+/** DMAC_CH1_ABORT_WE : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ABORT_WE    (BIT(8))
+#define DMAC_CH1_ABORT_WE_M  (DMAC_CH1_ABORT_WE_V << DMAC_CH1_ABORT_WE_S)
+#define DMAC_CH1_ABORT_WE_V  0x00000001U
+#define DMAC_CH1_ABORT_WE_S  8
+/** DMAC_CH2_ABORT_WE : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ABORT_WE    (BIT(9))
+#define DMAC_CH2_ABORT_WE_M  (DMAC_CH2_ABORT_WE_V << DMAC_CH2_ABORT_WE_S)
+#define DMAC_CH2_ABORT_WE_V  0x00000001U
+#define DMAC_CH2_ABORT_WE_S  9
+/** DMAC_CH3_ABORT_WE : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ABORT_WE    (BIT(10))
+#define DMAC_CH3_ABORT_WE_M  (DMAC_CH3_ABORT_WE_V << DMAC_CH3_ABORT_WE_S)
+#define DMAC_CH3_ABORT_WE_V  0x00000001U
+#define DMAC_CH3_ABORT_WE_S  10
+/** DMAC_CH4_ABORT_WE : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ABORT_WE    (BIT(11))
+#define DMAC_CH4_ABORT_WE_M  (DMAC_CH4_ABORT_WE_V << DMAC_CH4_ABORT_WE_S)
+#define DMAC_CH4_ABORT_WE_V  0x00000001U
+#define DMAC_CH4_ABORT_WE_S  11
+
+/** DMAC_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x30)
+/** DMAC_CH1_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_INTSTAT    (BIT(0))
+#define DMAC_CH1_INTSTAT_M  (DMAC_CH1_INTSTAT_V << DMAC_CH1_INTSTAT_S)
+#define DMAC_CH1_INTSTAT_V  0x00000001U
+#define DMAC_CH1_INTSTAT_S  0
+/** DMAC_CH2_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_INTSTAT    (BIT(1))
+#define DMAC_CH2_INTSTAT_M  (DMAC_CH2_INTSTAT_V << DMAC_CH2_INTSTAT_S)
+#define DMAC_CH2_INTSTAT_V  0x00000001U
+#define DMAC_CH2_INTSTAT_S  1
+/** DMAC_CH3_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_INTSTAT    (BIT(2))
+#define DMAC_CH3_INTSTAT_M  (DMAC_CH3_INTSTAT_V << DMAC_CH3_INTSTAT_S)
+#define DMAC_CH3_INTSTAT_V  0x00000001U
+#define DMAC_CH3_INTSTAT_S  2
+/** DMAC_CH4_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_INTSTAT    (BIT(3))
+#define DMAC_CH4_INTSTAT_M  (DMAC_CH4_INTSTAT_V << DMAC_CH4_INTSTAT_S)
+#define DMAC_CH4_INTSTAT_V  0x00000001U
+#define DMAC_CH4_INTSTAT_S  3
+/** DMAC_COMMONREG_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_COMMONREG_INTSTAT    (BIT(16))
+#define DMAC_COMMONREG_INTSTAT_M  (DMAC_COMMONREG_INTSTAT_V << DMAC_COMMONREG_INTSTAT_S)
+#define DMAC_COMMONREG_INTSTAT_V  0x00000001U
+#define DMAC_COMMONREG_INTSTAT_S  16
+
+/** DMAC_COMMONREG_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_COMMONREG_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x38)
+/** DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT    (BIT(0))
+#define DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S  0
+/** DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT    (BIT(1))
+#define DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S  1
+/** DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT    (BIT(2))
+#define DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S  2
+/** DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT    (BIT(3))
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S  3
+/** DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT    (BIT(7))
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S  7
+/** DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT    (BIT(8))
+#define DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_M  (DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V << DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S)
+#define DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S  8
+/** DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(9))
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S  9
+/** DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(10))
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  10
+/** DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(11))
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S  11
+/** DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(12))
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  12
+/** DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(13))
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S  13
+/** DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(14))
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S  14
+/** DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(15))
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S  15
+/** DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(16))
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  16
+/** DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(17))
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S  17
+/** DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(18))
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  18
+/** DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(19))
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S  19
+/** DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT : WO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(20))
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CLEAR_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S  20
+
+/** DMAC_COMMONREG_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_COMMONREG_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x40)
+/** DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT    (BIT(0))
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S  0
+/** DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT    (BIT(1))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S  1
+/** DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT    (BIT(2))
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S  2
+/** DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT    (BIT(3))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S  3
+/** DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT : RO; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT    (BIT(7))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S  7
+/** DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT    (BIT(8))
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_M  (DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V << DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S)
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S  8
+/** DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(9))
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S  9
+/** DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(10))
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  10
+/** DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(11))
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S  11
+/** DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(12))
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  12
+/** DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(13))
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S  13
+/** DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(14))
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S  14
+/** DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(15))
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S  15
+/** DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(16))
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  16
+/** DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(17))
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S  17
+/** DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(18))
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  18
+/** DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(19))
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S  19
+/** DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(20))
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S  20
+
+/** DMAC_COMMONREG_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_COMMONREG_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x48)
+/** DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL    (BIT(0))
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL_S  0
+/** DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL    (BIT(1))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL_S  1
+/** DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL    (BIT(2))
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL_S  2
+/** DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL    (BIT(3))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL_S  3
+/** DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_COMMONREG_WRPARITY_ERR_INTSIGNAL_S  7
+/** DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_M  (DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_V << DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_S)
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL_S  8
+/** DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL    (BIT(9))
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_CORRERR_INTSIGNAL_S  9
+/** DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(10))
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_S  10
+/** DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL    (BIT(11))
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_CORRERR_INTSIGNAL_S  11
+/** DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(12))
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_S  12
+/** DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL    (BIT(13))
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_CORRERR_INTSIGNAL_S  13
+/** DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(14))
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF1_BCH_ECCPROT_UNCORRERR_INTSIGNAL_S  14
+/** DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL    (BIT(15))
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_CORRERR_INTSIGNAL_S  15
+/** DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(16))
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSIGNAL_S  16
+/** DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL    (BIT(17))
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_CORRERR_INTSIGNAL_S  17
+/** DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(18))
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSIGNAL_S  18
+/** DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL : RO; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL    (BIT(19))
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_CORRERR_INTSIGNAL_S  19
+/** DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL : RO; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL    (BIT(20))
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_M  (DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_V << DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_S)
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_ENABLE_MXIF2_BCH_ECCPROT_UNCORRERR_INTSIGNAL_S  20
+
+/** DMAC_COMMONREG_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_COMMONREG_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x50)
+/** DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT    (BIT(0))
+#define DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_DEC_ERR_INTSTAT_S  0
+/** DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT    (BIT(1))
+#define DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT_S  1
+/** DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT    (BIT(2))
+#define DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT_S  2
+/** DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT    (BIT(3))
+#define DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT_S  3
+/** DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT    (BIT(7))
+#define DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_M  (DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V << DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_COMMONREG_WRPARITY_ERR_INTSTAT_S  7
+/** DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT    (BIT(8))
+#define DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_M  (DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V << DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S)
+#define DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT_S  8
+/** DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(9))
+#define DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_RCH0_ECCPROT_CORRERR_INTSTAT_S  9
+/** DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(10))
+#define DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  10
+/** DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(11))
+#define DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_RCH1_ECCPROT_CORRERR_INTSTAT_S  11
+/** DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(12))
+#define DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  12
+/** DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(13))
+#define DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_BCH_ECCPROT_CORRERR_INTSTAT_S  13
+/** DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(14))
+#define DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF1_BCH_ECCPROT_UNCORRERR_INTSTAT_S  14
+/** DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT    (BIT(15))
+#define DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_RCH0_ECCPROT_CORRERR_INTSTAT_S  15
+/** DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT    (BIT(16))
+#define DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_RCH0_ECCPROT_UNCORRERR_INTSTAT_S  16
+/** DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT    (BIT(17))
+#define DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_RCH1_ECCPROT_CORRERR_INTSTAT_S  17
+/** DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT    (BIT(18))
+#define DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_RCH1_ECCPROT_UNCORRERR_INTSTAT_S  18
+/** DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT    (BIT(19))
+#define DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_M  (DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V << DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S)
+#define DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_BCH_ECCPROT_CORRERR_INTSTAT_S  19
+/** DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT    (BIT(20))
+#define DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_M  (DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V << DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S)
+#define DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_MXIF2_BCH_ECCPROT_UNCORRERR_INTSTAT_S  20
+
+/** DMAC_RESET0_REG register
+ *  NA
+ */
+#define DMAC_RESET0_REG (DR_REG_DMAC_BASE + 0x58)
+/** DMAC_DMAC_RST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_DMAC_RST    (BIT(0))
+#define DMAC_DMAC_RST_M  (DMAC_DMAC_RST_V << DMAC_DMAC_RST_S)
+#define DMAC_DMAC_RST_V  0x00000001U
+#define DMAC_DMAC_RST_S  0
+
+/** DMAC_LOWPOWER_CFG0_REG register
+ *  NA
+ */
+#define DMAC_LOWPOWER_CFG0_REG (DR_REG_DMAC_BASE + 0x60)
+/** DMAC_GBL_CSLP_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_GBL_CSLP_EN    (BIT(0))
+#define DMAC_GBL_CSLP_EN_M  (DMAC_GBL_CSLP_EN_V << DMAC_GBL_CSLP_EN_S)
+#define DMAC_GBL_CSLP_EN_V  0x00000001U
+#define DMAC_GBL_CSLP_EN_S  0
+/** DMAC_CHNL_CSLP_EN : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CHNL_CSLP_EN    (BIT(1))
+#define DMAC_CHNL_CSLP_EN_M  (DMAC_CHNL_CSLP_EN_V << DMAC_CHNL_CSLP_EN_S)
+#define DMAC_CHNL_CSLP_EN_V  0x00000001U
+#define DMAC_CHNL_CSLP_EN_S  1
+/** DMAC_SBIU_CSLP_EN : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_SBIU_CSLP_EN    (BIT(2))
+#define DMAC_SBIU_CSLP_EN_M  (DMAC_SBIU_CSLP_EN_V << DMAC_SBIU_CSLP_EN_S)
+#define DMAC_SBIU_CSLP_EN_V  0x00000001U
+#define DMAC_SBIU_CSLP_EN_S  2
+/** DMAC_MXIF_CSLP_EN : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_MXIF_CSLP_EN    (BIT(3))
+#define DMAC_MXIF_CSLP_EN_M  (DMAC_MXIF_CSLP_EN_V << DMAC_MXIF_CSLP_EN_S)
+#define DMAC_MXIF_CSLP_EN_V  0x00000001U
+#define DMAC_MXIF_CSLP_EN_S  3
+
+/** DMAC_LOWPOWER_CFG1_REG register
+ *  NA
+ */
+#define DMAC_LOWPOWER_CFG1_REG (DR_REG_DMAC_BASE + 0x64)
+/** DMAC_GLCH_LPDLY : R/W; bitpos: [7:0]; default: 64;
+ *  NA
+ */
+#define DMAC_GLCH_LPDLY    0x000000FFU
+#define DMAC_GLCH_LPDLY_M  (DMAC_GLCH_LPDLY_V << DMAC_GLCH_LPDLY_S)
+#define DMAC_GLCH_LPDLY_V  0x000000FFU
+#define DMAC_GLCH_LPDLY_S  0
+/** DMAC_SBIU_LPDLY : R/W; bitpos: [15:8]; default: 64;
+ *  NA
+ */
+#define DMAC_SBIU_LPDLY    0x000000FFU
+#define DMAC_SBIU_LPDLY_M  (DMAC_SBIU_LPDLY_V << DMAC_SBIU_LPDLY_S)
+#define DMAC_SBIU_LPDLY_V  0x000000FFU
+#define DMAC_SBIU_LPDLY_S  8
+/** DMAC_MXIF_LPDLY : R/W; bitpos: [23:16]; default: 64;
+ *  NA
+ */
+#define DMAC_MXIF_LPDLY    0x000000FFU
+#define DMAC_MXIF_LPDLY_M  (DMAC_MXIF_LPDLY_V << DMAC_MXIF_LPDLY_S)
+#define DMAC_MXIF_LPDLY_V  0x000000FFU
+#define DMAC_MXIF_LPDLY_S  16
+
+/** DMAC_CH1_SAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SAR0_REG (DR_REG_DMAC_BASE + 0x100)
+/** DMAC_CH1_SAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SAR0    0xFFFFFFFFU
+#define DMAC_CH1_SAR0_M  (DMAC_CH1_SAR0_V << DMAC_CH1_SAR0_S)
+#define DMAC_CH1_SAR0_V  0xFFFFFFFFU
+#define DMAC_CH1_SAR0_S  0
+
+/** DMAC_CH1_SAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_SAR1_REG (DR_REG_DMAC_BASE + 0x104)
+/** DMAC_CH1_SAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SAR1    0xFFFFFFFFU
+#define DMAC_CH1_SAR1_M  (DMAC_CH1_SAR1_V << DMAC_CH1_SAR1_S)
+#define DMAC_CH1_SAR1_V  0xFFFFFFFFU
+#define DMAC_CH1_SAR1_S  0
+
+/** DMAC_CH1_DAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_DAR0_REG (DR_REG_DMAC_BASE + 0x108)
+/** DMAC_CH1_DAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DAR0    0xFFFFFFFFU
+#define DMAC_CH1_DAR0_M  (DMAC_CH1_DAR0_V << DMAC_CH1_DAR0_S)
+#define DMAC_CH1_DAR0_V  0xFFFFFFFFU
+#define DMAC_CH1_DAR0_S  0
+
+/** DMAC_CH1_DAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_DAR1_REG (DR_REG_DMAC_BASE + 0x10c)
+/** DMAC_CH1_DAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DAR1    0xFFFFFFFFU
+#define DMAC_CH1_DAR1_M  (DMAC_CH1_DAR1_V << DMAC_CH1_DAR1_S)
+#define DMAC_CH1_DAR1_V  0xFFFFFFFFU
+#define DMAC_CH1_DAR1_S  0
+
+/** DMAC_CH1_BLOCK_TS0_REG register
+ *  NA
+ */
+#define DMAC_CH1_BLOCK_TS0_REG (DR_REG_DMAC_BASE + 0x110)
+/** DMAC_CH1_BLOCK_TS : R/W; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_BLOCK_TS    0x003FFFFFU
+#define DMAC_CH1_BLOCK_TS_M  (DMAC_CH1_BLOCK_TS_V << DMAC_CH1_BLOCK_TS_S)
+#define DMAC_CH1_BLOCK_TS_V  0x003FFFFFU
+#define DMAC_CH1_BLOCK_TS_S  0
+
+/** DMAC_CH1_CTL0_REG register
+ *  NA
+ */
+#define DMAC_CH1_CTL0_REG (DR_REG_DMAC_BASE + 0x118)
+/** DMAC_CH1_SMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SMS    (BIT(0))
+#define DMAC_CH1_SMS_M  (DMAC_CH1_SMS_V << DMAC_CH1_SMS_S)
+#define DMAC_CH1_SMS_V  0x00000001U
+#define DMAC_CH1_SMS_S  0
+/** DMAC_CH1_DMS : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DMS    (BIT(2))
+#define DMAC_CH1_DMS_M  (DMAC_CH1_DMS_V << DMAC_CH1_DMS_S)
+#define DMAC_CH1_DMS_V  0x00000001U
+#define DMAC_CH1_DMS_S  2
+/** DMAC_CH1_SINC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SINC    (BIT(4))
+#define DMAC_CH1_SINC_M  (DMAC_CH1_SINC_V << DMAC_CH1_SINC_S)
+#define DMAC_CH1_SINC_V  0x00000001U
+#define DMAC_CH1_SINC_S  4
+/** DMAC_CH1_DINC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DINC    (BIT(6))
+#define DMAC_CH1_DINC_M  (DMAC_CH1_DINC_V << DMAC_CH1_DINC_S)
+#define DMAC_CH1_DINC_V  0x00000001U
+#define DMAC_CH1_DINC_S  6
+/** DMAC_CH1_SRC_TR_WIDTH : R/W; bitpos: [10:8]; default: 2;
+ *  NA
+ */
+#define DMAC_CH1_SRC_TR_WIDTH    0x00000007U
+#define DMAC_CH1_SRC_TR_WIDTH_M  (DMAC_CH1_SRC_TR_WIDTH_V << DMAC_CH1_SRC_TR_WIDTH_S)
+#define DMAC_CH1_SRC_TR_WIDTH_V  0x00000007U
+#define DMAC_CH1_SRC_TR_WIDTH_S  8
+/** DMAC_CH1_DST_TR_WIDTH : R/W; bitpos: [13:11]; default: 2;
+ *  NA
+ */
+#define DMAC_CH1_DST_TR_WIDTH    0x00000007U
+#define DMAC_CH1_DST_TR_WIDTH_M  (DMAC_CH1_DST_TR_WIDTH_V << DMAC_CH1_DST_TR_WIDTH_S)
+#define DMAC_CH1_DST_TR_WIDTH_V  0x00000007U
+#define DMAC_CH1_DST_TR_WIDTH_S  11
+/** DMAC_CH1_SRC_MSIZE : R/W; bitpos: [17:14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_MSIZE    0x0000000FU
+#define DMAC_CH1_SRC_MSIZE_M  (DMAC_CH1_SRC_MSIZE_V << DMAC_CH1_SRC_MSIZE_S)
+#define DMAC_CH1_SRC_MSIZE_V  0x0000000FU
+#define DMAC_CH1_SRC_MSIZE_S  14
+/** DMAC_CH1_DST_MSIZE : R/W; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_MSIZE    0x0000000FU
+#define DMAC_CH1_DST_MSIZE_M  (DMAC_CH1_DST_MSIZE_V << DMAC_CH1_DST_MSIZE_S)
+#define DMAC_CH1_DST_MSIZE_V  0x0000000FU
+#define DMAC_CH1_DST_MSIZE_S  18
+/** DMAC_CH1_AR_CACHE : R/W; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AR_CACHE    0x0000000FU
+#define DMAC_CH1_AR_CACHE_M  (DMAC_CH1_AR_CACHE_V << DMAC_CH1_AR_CACHE_S)
+#define DMAC_CH1_AR_CACHE_V  0x0000000FU
+#define DMAC_CH1_AR_CACHE_S  22
+/** DMAC_CH1_AW_CACHE : R/W; bitpos: [29:26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AW_CACHE    0x0000000FU
+#define DMAC_CH1_AW_CACHE_M  (DMAC_CH1_AW_CACHE_V << DMAC_CH1_AW_CACHE_S)
+#define DMAC_CH1_AW_CACHE_V  0x0000000FU
+#define DMAC_CH1_AW_CACHE_S  26
+/** DMAC_CH1_NONPOSTED_LASTWRITE_EN : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_NONPOSTED_LASTWRITE_EN    (BIT(30))
+#define DMAC_CH1_NONPOSTED_LASTWRITE_EN_M  (DMAC_CH1_NONPOSTED_LASTWRITE_EN_V << DMAC_CH1_NONPOSTED_LASTWRITE_EN_S)
+#define DMAC_CH1_NONPOSTED_LASTWRITE_EN_V  0x00000001U
+#define DMAC_CH1_NONPOSTED_LASTWRITE_EN_S  30
+
+/** DMAC_CH1_CTL1_REG register
+ *  NA
+ */
+#define DMAC_CH1_CTL1_REG (DR_REG_DMAC_BASE + 0x11c)
+/** DMAC_CH1_AR_PROT : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AR_PROT    0x00000007U
+#define DMAC_CH1_AR_PROT_M  (DMAC_CH1_AR_PROT_V << DMAC_CH1_AR_PROT_S)
+#define DMAC_CH1_AR_PROT_V  0x00000007U
+#define DMAC_CH1_AR_PROT_S  0
+/** DMAC_CH1_AW_PROT : R/W; bitpos: [5:3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AW_PROT    0x00000007U
+#define DMAC_CH1_AW_PROT_M  (DMAC_CH1_AW_PROT_V << DMAC_CH1_AW_PROT_S)
+#define DMAC_CH1_AW_PROT_V  0x00000007U
+#define DMAC_CH1_AW_PROT_S  3
+/** DMAC_CH1_ARLEN_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ARLEN_EN    (BIT(6))
+#define DMAC_CH1_ARLEN_EN_M  (DMAC_CH1_ARLEN_EN_V << DMAC_CH1_ARLEN_EN_S)
+#define DMAC_CH1_ARLEN_EN_V  0x00000001U
+#define DMAC_CH1_ARLEN_EN_S  6
+/** DMAC_CH1_ARLEN : R/W; bitpos: [14:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ARLEN    0x000000FFU
+#define DMAC_CH1_ARLEN_M  (DMAC_CH1_ARLEN_V << DMAC_CH1_ARLEN_S)
+#define DMAC_CH1_ARLEN_V  0x000000FFU
+#define DMAC_CH1_ARLEN_S  7
+/** DMAC_CH1_AWLEN_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AWLEN_EN    (BIT(15))
+#define DMAC_CH1_AWLEN_EN_M  (DMAC_CH1_AWLEN_EN_V << DMAC_CH1_AWLEN_EN_S)
+#define DMAC_CH1_AWLEN_EN_V  0x00000001U
+#define DMAC_CH1_AWLEN_EN_S  15
+/** DMAC_CH1_AWLEN : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AWLEN    0x000000FFU
+#define DMAC_CH1_AWLEN_M  (DMAC_CH1_AWLEN_V << DMAC_CH1_AWLEN_S)
+#define DMAC_CH1_AWLEN_V  0x000000FFU
+#define DMAC_CH1_AWLEN_S  16
+/** DMAC_CH1_SRC_STAT_EN : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_STAT_EN    (BIT(24))
+#define DMAC_CH1_SRC_STAT_EN_M  (DMAC_CH1_SRC_STAT_EN_V << DMAC_CH1_SRC_STAT_EN_S)
+#define DMAC_CH1_SRC_STAT_EN_V  0x00000001U
+#define DMAC_CH1_SRC_STAT_EN_S  24
+/** DMAC_CH1_DST_STAT_EN : R/W; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_STAT_EN    (BIT(25))
+#define DMAC_CH1_DST_STAT_EN_M  (DMAC_CH1_DST_STAT_EN_V << DMAC_CH1_DST_STAT_EN_S)
+#define DMAC_CH1_DST_STAT_EN_V  0x00000001U
+#define DMAC_CH1_DST_STAT_EN_S  25
+/** DMAC_CH1_IOC_BLKTFR : R/W; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_IOC_BLKTFR    (BIT(26))
+#define DMAC_CH1_IOC_BLKTFR_M  (DMAC_CH1_IOC_BLKTFR_V << DMAC_CH1_IOC_BLKTFR_S)
+#define DMAC_CH1_IOC_BLKTFR_V  0x00000001U
+#define DMAC_CH1_IOC_BLKTFR_S  26
+/** DMAC_CH1_SHADOWREG_OR_LLI_LAST : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SHADOWREG_OR_LLI_LAST    (BIT(30))
+#define DMAC_CH1_SHADOWREG_OR_LLI_LAST_M  (DMAC_CH1_SHADOWREG_OR_LLI_LAST_V << DMAC_CH1_SHADOWREG_OR_LLI_LAST_S)
+#define DMAC_CH1_SHADOWREG_OR_LLI_LAST_V  0x00000001U
+#define DMAC_CH1_SHADOWREG_OR_LLI_LAST_S  30
+/** DMAC_CH1_SHADOWREG_OR_LLI_VALID : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SHADOWREG_OR_LLI_VALID    (BIT(31))
+#define DMAC_CH1_SHADOWREG_OR_LLI_VALID_M  (DMAC_CH1_SHADOWREG_OR_LLI_VALID_V << DMAC_CH1_SHADOWREG_OR_LLI_VALID_S)
+#define DMAC_CH1_SHADOWREG_OR_LLI_VALID_V  0x00000001U
+#define DMAC_CH1_SHADOWREG_OR_LLI_VALID_S  31
+
+/** DMAC_CH1_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CH1_CFG0_REG (DR_REG_DMAC_BASE + 0x120)
+/** DMAC_CH1_SRC_MULTBLK_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH1_SRC_MULTBLK_TYPE_M  (DMAC_CH1_SRC_MULTBLK_TYPE_V << DMAC_CH1_SRC_MULTBLK_TYPE_S)
+#define DMAC_CH1_SRC_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH1_SRC_MULTBLK_TYPE_S  0
+/** DMAC_CH1_DST_MULTBLK_TYPE : R/W; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH1_DST_MULTBLK_TYPE_M  (DMAC_CH1_DST_MULTBLK_TYPE_V << DMAC_CH1_DST_MULTBLK_TYPE_S)
+#define DMAC_CH1_DST_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH1_DST_MULTBLK_TYPE_S  2
+/** DMAC_CH1_RD_UID : RO; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_RD_UID    0x0000000FU
+#define DMAC_CH1_RD_UID_M  (DMAC_CH1_RD_UID_V << DMAC_CH1_RD_UID_S)
+#define DMAC_CH1_RD_UID_V  0x0000000FU
+#define DMAC_CH1_RD_UID_S  18
+/** DMAC_CH1_WR_UID : RO; bitpos: [28:25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_WR_UID    0x0000000FU
+#define DMAC_CH1_WR_UID_M  (DMAC_CH1_WR_UID_V << DMAC_CH1_WR_UID_S)
+#define DMAC_CH1_WR_UID_V  0x0000000FU
+#define DMAC_CH1_WR_UID_S  25
+
+/** DMAC_CH1_CFG1_REG register
+ *  NA
+ */
+#define DMAC_CH1_CFG1_REG (DR_REG_DMAC_BASE + 0x124)
+/** DMAC_CH1_TT_FC : R/W; bitpos: [2:0]; default: 3;
+ *  NA
+ */
+#define DMAC_CH1_TT_FC    0x00000007U
+#define DMAC_CH1_TT_FC_M  (DMAC_CH1_TT_FC_V << DMAC_CH1_TT_FC_S)
+#define DMAC_CH1_TT_FC_V  0x00000007U
+#define DMAC_CH1_TT_FC_S  0
+/** DMAC_CH1_HS_SEL_SRC : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_HS_SEL_SRC    (BIT(3))
+#define DMAC_CH1_HS_SEL_SRC_M  (DMAC_CH1_HS_SEL_SRC_V << DMAC_CH1_HS_SEL_SRC_S)
+#define DMAC_CH1_HS_SEL_SRC_V  0x00000001U
+#define DMAC_CH1_HS_SEL_SRC_S  3
+/** DMAC_CH1_HS_SEL_DST : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_HS_SEL_DST    (BIT(4))
+#define DMAC_CH1_HS_SEL_DST_M  (DMAC_CH1_HS_SEL_DST_V << DMAC_CH1_HS_SEL_DST_S)
+#define DMAC_CH1_HS_SEL_DST_V  0x00000001U
+#define DMAC_CH1_HS_SEL_DST_S  4
+/** DMAC_CH1_SRC_HWHS_POL : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_HWHS_POL    (BIT(5))
+#define DMAC_CH1_SRC_HWHS_POL_M  (DMAC_CH1_SRC_HWHS_POL_V << DMAC_CH1_SRC_HWHS_POL_S)
+#define DMAC_CH1_SRC_HWHS_POL_V  0x00000001U
+#define DMAC_CH1_SRC_HWHS_POL_S  5
+/** DMAC_CH1_DST_HWHS_POL : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_HWHS_POL    (BIT(6))
+#define DMAC_CH1_DST_HWHS_POL_M  (DMAC_CH1_DST_HWHS_POL_V << DMAC_CH1_DST_HWHS_POL_S)
+#define DMAC_CH1_DST_HWHS_POL_V  0x00000001U
+#define DMAC_CH1_DST_HWHS_POL_S  6
+/** DMAC_CH1_SRC_PER : R/W; bitpos: [8:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_PER    0x00000003U
+#define DMAC_CH1_SRC_PER_M  (DMAC_CH1_SRC_PER_V << DMAC_CH1_SRC_PER_S)
+#define DMAC_CH1_SRC_PER_V  0x00000003U
+#define DMAC_CH1_SRC_PER_S  7
+/** DMAC_CH1_DST_PER : R/W; bitpos: [13:12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_PER    0x00000003U
+#define DMAC_CH1_DST_PER_M  (DMAC_CH1_DST_PER_V << DMAC_CH1_DST_PER_S)
+#define DMAC_CH1_DST_PER_V  0x00000003U
+#define DMAC_CH1_DST_PER_S  12
+/** DMAC_CH1_CH_PRIOR : R/W; bitpos: [19:17]; default: 3;
+ *  NA
+ */
+#define DMAC_CH1_CH_PRIOR    0x00000007U
+#define DMAC_CH1_CH_PRIOR_M  (DMAC_CH1_CH_PRIOR_V << DMAC_CH1_CH_PRIOR_S)
+#define DMAC_CH1_CH_PRIOR_V  0x00000007U
+#define DMAC_CH1_CH_PRIOR_S  17
+/** DMAC_CH1_LOCK_CH : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LOCK_CH    (BIT(20))
+#define DMAC_CH1_LOCK_CH_M  (DMAC_CH1_LOCK_CH_V << DMAC_CH1_LOCK_CH_S)
+#define DMAC_CH1_LOCK_CH_V  0x00000001U
+#define DMAC_CH1_LOCK_CH_S  20
+/** DMAC_CH1_LOCK_CH_L : RO; bitpos: [22:21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LOCK_CH_L    0x00000003U
+#define DMAC_CH1_LOCK_CH_L_M  (DMAC_CH1_LOCK_CH_L_V << DMAC_CH1_LOCK_CH_L_S)
+#define DMAC_CH1_LOCK_CH_L_V  0x00000003U
+#define DMAC_CH1_LOCK_CH_L_S  21
+/** DMAC_CH1_SRC_OSR_LMT : R/W; bitpos: [26:23]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_OSR_LMT    0x0000000FU
+#define DMAC_CH1_SRC_OSR_LMT_M  (DMAC_CH1_SRC_OSR_LMT_V << DMAC_CH1_SRC_OSR_LMT_S)
+#define DMAC_CH1_SRC_OSR_LMT_V  0x0000000FU
+#define DMAC_CH1_SRC_OSR_LMT_S  23
+/** DMAC_CH1_DST_OSR_LMT : R/W; bitpos: [30:27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_OSR_LMT    0x0000000FU
+#define DMAC_CH1_DST_OSR_LMT_M  (DMAC_CH1_DST_OSR_LMT_V << DMAC_CH1_DST_OSR_LMT_S)
+#define DMAC_CH1_DST_OSR_LMT_V  0x0000000FU
+#define DMAC_CH1_DST_OSR_LMT_S  27
+
+/** DMAC_CH1_LLP0_REG register
+ *  NA
+ */
+#define DMAC_CH1_LLP0_REG (DR_REG_DMAC_BASE + 0x128)
+/** DMAC_CH1_LMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LMS    (BIT(0))
+#define DMAC_CH1_LMS_M  (DMAC_CH1_LMS_V << DMAC_CH1_LMS_S)
+#define DMAC_CH1_LMS_V  0x00000001U
+#define DMAC_CH1_LMS_S  0
+/** DMAC_CH1_LOC0 : R/W; bitpos: [31:6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LOC0    0x03FFFFFFU
+#define DMAC_CH1_LOC0_M  (DMAC_CH1_LOC0_V << DMAC_CH1_LOC0_S)
+#define DMAC_CH1_LOC0_V  0x03FFFFFFU
+#define DMAC_CH1_LOC0_S  6
+
+/** DMAC_CH1_LLP1_REG register
+ *  NA
+ */
+#define DMAC_CH1_LLP1_REG (DR_REG_DMAC_BASE + 0x12c)
+/** DMAC_CH1_LOC1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LOC1    0xFFFFFFFFU
+#define DMAC_CH1_LOC1_M  (DMAC_CH1_LOC1_V << DMAC_CH1_LOC1_S)
+#define DMAC_CH1_LOC1_V  0xFFFFFFFFU
+#define DMAC_CH1_LOC1_S  0
+
+/** DMAC_CH1_STATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH1_STATUS0_REG (DR_REG_DMAC_BASE + 0x130)
+/** DMAC_CH1_CMPLTD_BLK_TFR_SIZE : RO; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CMPLTD_BLK_TFR_SIZE    0x003FFFFFU
+#define DMAC_CH1_CMPLTD_BLK_TFR_SIZE_M  (DMAC_CH1_CMPLTD_BLK_TFR_SIZE_V << DMAC_CH1_CMPLTD_BLK_TFR_SIZE_S)
+#define DMAC_CH1_CMPLTD_BLK_TFR_SIZE_V  0x003FFFFFU
+#define DMAC_CH1_CMPLTD_BLK_TFR_SIZE_S  0
+
+/** DMAC_CH1_STATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH1_STATUS1_REG (DR_REG_DMAC_BASE + 0x134)
+/** DMAC_CH1_DATA_LEFT_IN_FIFO : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DATA_LEFT_IN_FIFO    0x00007FFFU
+#define DMAC_CH1_DATA_LEFT_IN_FIFO_M  (DMAC_CH1_DATA_LEFT_IN_FIFO_V << DMAC_CH1_DATA_LEFT_IN_FIFO_S)
+#define DMAC_CH1_DATA_LEFT_IN_FIFO_V  0x00007FFFU
+#define DMAC_CH1_DATA_LEFT_IN_FIFO_S  0
+
+/** DMAC_CH1_SWHSSRC0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SWHSSRC0_REG (DR_REG_DMAC_BASE + 0x138)
+/** DMAC_CH1_SWHS_REQ_SRC : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_REQ_SRC    (BIT(0))
+#define DMAC_CH1_SWHS_REQ_SRC_M  (DMAC_CH1_SWHS_REQ_SRC_V << DMAC_CH1_SWHS_REQ_SRC_S)
+#define DMAC_CH1_SWHS_REQ_SRC_V  0x00000001U
+#define DMAC_CH1_SWHS_REQ_SRC_S  0
+/** DMAC_CH1_SWHS_REQ_SRC_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_REQ_SRC_WE    (BIT(1))
+#define DMAC_CH1_SWHS_REQ_SRC_WE_M  (DMAC_CH1_SWHS_REQ_SRC_WE_V << DMAC_CH1_SWHS_REQ_SRC_WE_S)
+#define DMAC_CH1_SWHS_REQ_SRC_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_REQ_SRC_WE_S  1
+/** DMAC_CH1_SWHS_SGLREQ_SRC : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_SGLREQ_SRC    (BIT(2))
+#define DMAC_CH1_SWHS_SGLREQ_SRC_M  (DMAC_CH1_SWHS_SGLREQ_SRC_V << DMAC_CH1_SWHS_SGLREQ_SRC_S)
+#define DMAC_CH1_SWHS_SGLREQ_SRC_V  0x00000001U
+#define DMAC_CH1_SWHS_SGLREQ_SRC_S  2
+/** DMAC_CH1_SWHS_SGLREQ_SRC_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_SGLREQ_SRC_WE    (BIT(3))
+#define DMAC_CH1_SWHS_SGLREQ_SRC_WE_M  (DMAC_CH1_SWHS_SGLREQ_SRC_WE_V << DMAC_CH1_SWHS_SGLREQ_SRC_WE_S)
+#define DMAC_CH1_SWHS_SGLREQ_SRC_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_SGLREQ_SRC_WE_S  3
+/** DMAC_CH1_SWHS_LST_SRC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_LST_SRC    (BIT(4))
+#define DMAC_CH1_SWHS_LST_SRC_M  (DMAC_CH1_SWHS_LST_SRC_V << DMAC_CH1_SWHS_LST_SRC_S)
+#define DMAC_CH1_SWHS_LST_SRC_V  0x00000001U
+#define DMAC_CH1_SWHS_LST_SRC_S  4
+/** DMAC_CH1_SWHS_LST_SRC_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_LST_SRC_WE    (BIT(5))
+#define DMAC_CH1_SWHS_LST_SRC_WE_M  (DMAC_CH1_SWHS_LST_SRC_WE_V << DMAC_CH1_SWHS_LST_SRC_WE_S)
+#define DMAC_CH1_SWHS_LST_SRC_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_LST_SRC_WE_S  5
+
+/** DMAC_CH1_SWHSDST0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SWHSDST0_REG (DR_REG_DMAC_BASE + 0x140)
+/** DMAC_CH1_SWHS_REQ_DST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_REQ_DST    (BIT(0))
+#define DMAC_CH1_SWHS_REQ_DST_M  (DMAC_CH1_SWHS_REQ_DST_V << DMAC_CH1_SWHS_REQ_DST_S)
+#define DMAC_CH1_SWHS_REQ_DST_V  0x00000001U
+#define DMAC_CH1_SWHS_REQ_DST_S  0
+/** DMAC_CH1_SWHS_REQ_DST_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_REQ_DST_WE    (BIT(1))
+#define DMAC_CH1_SWHS_REQ_DST_WE_M  (DMAC_CH1_SWHS_REQ_DST_WE_V << DMAC_CH1_SWHS_REQ_DST_WE_S)
+#define DMAC_CH1_SWHS_REQ_DST_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_REQ_DST_WE_S  1
+/** DMAC_CH1_SWHS_SGLREQ_DST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_SGLREQ_DST    (BIT(2))
+#define DMAC_CH1_SWHS_SGLREQ_DST_M  (DMAC_CH1_SWHS_SGLREQ_DST_V << DMAC_CH1_SWHS_SGLREQ_DST_S)
+#define DMAC_CH1_SWHS_SGLREQ_DST_V  0x00000001U
+#define DMAC_CH1_SWHS_SGLREQ_DST_S  2
+/** DMAC_CH1_SWHS_SGLREQ_DST_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_SGLREQ_DST_WE    (BIT(3))
+#define DMAC_CH1_SWHS_SGLREQ_DST_WE_M  (DMAC_CH1_SWHS_SGLREQ_DST_WE_V << DMAC_CH1_SWHS_SGLREQ_DST_WE_S)
+#define DMAC_CH1_SWHS_SGLREQ_DST_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_SGLREQ_DST_WE_S  3
+/** DMAC_CH1_SWHS_LST_DST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_LST_DST    (BIT(4))
+#define DMAC_CH1_SWHS_LST_DST_M  (DMAC_CH1_SWHS_LST_DST_V << DMAC_CH1_SWHS_LST_DST_S)
+#define DMAC_CH1_SWHS_LST_DST_V  0x00000001U
+#define DMAC_CH1_SWHS_LST_DST_S  4
+/** DMAC_CH1_SWHS_LST_DST_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SWHS_LST_DST_WE    (BIT(5))
+#define DMAC_CH1_SWHS_LST_DST_WE_M  (DMAC_CH1_SWHS_LST_DST_WE_V << DMAC_CH1_SWHS_LST_DST_WE_S)
+#define DMAC_CH1_SWHS_LST_DST_WE_V  0x00000001U
+#define DMAC_CH1_SWHS_LST_DST_WE_S  5
+
+/** DMAC_CH1_BLK_TFR_RESUMEREQ0_REG register
+ *  NA
+ */
+#define DMAC_CH1_BLK_TFR_RESUMEREQ0_REG (DR_REG_DMAC_BASE + 0x148)
+/** DMAC_CH1_BLK_TFR_RESUMEREQ : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_BLK_TFR_RESUMEREQ    (BIT(0))
+#define DMAC_CH1_BLK_TFR_RESUMEREQ_M  (DMAC_CH1_BLK_TFR_RESUMEREQ_V << DMAC_CH1_BLK_TFR_RESUMEREQ_S)
+#define DMAC_CH1_BLK_TFR_RESUMEREQ_V  0x00000001U
+#define DMAC_CH1_BLK_TFR_RESUMEREQ_S  0
+
+/** DMAC_CH1_AXI_ID0_REG register
+ *  NA
+ */
+#define DMAC_CH1_AXI_ID0_REG (DR_REG_DMAC_BASE + 0x150)
+/** DMAC_CH1_AXI_READ_ID_SUFFIX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AXI_READ_ID_SUFFIX    (BIT(0))
+#define DMAC_CH1_AXI_READ_ID_SUFFIX_M  (DMAC_CH1_AXI_READ_ID_SUFFIX_V << DMAC_CH1_AXI_READ_ID_SUFFIX_S)
+#define DMAC_CH1_AXI_READ_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH1_AXI_READ_ID_SUFFIX_S  0
+/** DMAC_CH1_AXI_WRITE_ID_SUFFIX : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AXI_WRITE_ID_SUFFIX    (BIT(16))
+#define DMAC_CH1_AXI_WRITE_ID_SUFFIX_M  (DMAC_CH1_AXI_WRITE_ID_SUFFIX_V << DMAC_CH1_AXI_WRITE_ID_SUFFIX_S)
+#define DMAC_CH1_AXI_WRITE_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH1_AXI_WRITE_ID_SUFFIX_S  16
+
+/** DMAC_CH1_AXI_QOS0_REG register
+ *  NA
+ */
+#define DMAC_CH1_AXI_QOS0_REG (DR_REG_DMAC_BASE + 0x158)
+/** DMAC_CH1_AXI_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AXI_AWQOS    0x0000000FU
+#define DMAC_CH1_AXI_AWQOS_M  (DMAC_CH1_AXI_AWQOS_V << DMAC_CH1_AXI_AWQOS_S)
+#define DMAC_CH1_AXI_AWQOS_V  0x0000000FU
+#define DMAC_CH1_AXI_AWQOS_S  0
+/** DMAC_CH1_AXI_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_AXI_ARQOS    0x0000000FU
+#define DMAC_CH1_AXI_ARQOS_M  (DMAC_CH1_AXI_ARQOS_V << DMAC_CH1_AXI_ARQOS_S)
+#define DMAC_CH1_AXI_ARQOS_V  0x0000000FU
+#define DMAC_CH1_AXI_ARQOS_S  4
+
+/** DMAC_CH1_SSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SSTAT0_REG (DR_REG_DMAC_BASE + 0x160)
+/** DMAC_CH1_SSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SSTAT    0xFFFFFFFFU
+#define DMAC_CH1_SSTAT_M  (DMAC_CH1_SSTAT_V << DMAC_CH1_SSTAT_S)
+#define DMAC_CH1_SSTAT_V  0xFFFFFFFFU
+#define DMAC_CH1_SSTAT_S  0
+
+/** DMAC_CH1_DSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH1_DSTAT0_REG (DR_REG_DMAC_BASE + 0x168)
+/** DMAC_CH1_DSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DSTAT    0xFFFFFFFFU
+#define DMAC_CH1_DSTAT_M  (DMAC_CH1_DSTAT_V << DMAC_CH1_DSTAT_S)
+#define DMAC_CH1_DSTAT_V  0xFFFFFFFFU
+#define DMAC_CH1_DSTAT_S  0
+
+/** DMAC_CH1_SSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_SSTATAR0_REG (DR_REG_DMAC_BASE + 0x170)
+/** DMAC_CH1_SSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SSTATAR0    0xFFFFFFFFU
+#define DMAC_CH1_SSTATAR0_M  (DMAC_CH1_SSTATAR0_V << DMAC_CH1_SSTATAR0_S)
+#define DMAC_CH1_SSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH1_SSTATAR0_S  0
+
+/** DMAC_CH1_SSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_SSTATAR1_REG (DR_REG_DMAC_BASE + 0x174)
+/** DMAC_CH1_SSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SSTATAR1    0xFFFFFFFFU
+#define DMAC_CH1_SSTATAR1_M  (DMAC_CH1_SSTATAR1_V << DMAC_CH1_SSTATAR1_S)
+#define DMAC_CH1_SSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH1_SSTATAR1_S  0
+
+/** DMAC_CH1_DSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_DSTATAR0_REG (DR_REG_DMAC_BASE + 0x178)
+/** DMAC_CH1_DSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DSTATAR0    0xFFFFFFFFU
+#define DMAC_CH1_DSTATAR0_M  (DMAC_CH1_DSTATAR0_V << DMAC_CH1_DSTATAR0_S)
+#define DMAC_CH1_DSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH1_DSTATAR0_S  0
+
+/** DMAC_CH1_DSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_DSTATAR1_REG (DR_REG_DMAC_BASE + 0x17c)
+/** DMAC_CH1_DSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DSTATAR1    0xFFFFFFFFU
+#define DMAC_CH1_DSTATAR1_M  (DMAC_CH1_DSTATAR1_V << DMAC_CH1_DSTATAR1_S)
+#define DMAC_CH1_DSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH1_DSTATAR1_S  0
+
+/** DMAC_CH1_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x180)
+/** DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_V << DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_V << DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_V << DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : R/W; bitpos: [13]; default:
+ *  1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_V << DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_V << DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_M  (DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_V << DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH1_INTSTATUS_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSTATUS_ENABLE1_REG (DR_REG_DMAC_BASE + 0x184)
+/** DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH1_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x188)
+/** DMAC_CH1_BLOCK_TFR_DONE_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH1_DMA_TFR_DONE_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH1_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH1_DMA_TFR_DONE_INTSTAT_V << DMAC_CH1_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH1_SRC_TRANSCOMP_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH1_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH1_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH1_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH1_DST_TRANSCOMP_INTSTAT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH1_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH1_DST_TRANSCOMP_INTSTAT_V << DMAC_CH1_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH1_SRC_DEC_ERR_INTSTAT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH1_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH1_SRC_DEC_ERR_INTSTAT_V << DMAC_CH1_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH1_DST_DEC_ERR_INTSTAT : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH1_DST_DEC_ERR_INTSTAT_M  (DMAC_CH1_DST_DEC_ERR_INTSTAT_V << DMAC_CH1_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH1_SRC_SLV_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH1_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH1_SRC_SLV_ERR_INTSTAT_V << DMAC_CH1_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH1_DST_SLV_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH1_DST_SLV_ERR_INTSTAT_M  (DMAC_CH1_DST_SLV_ERR_INTSTAT_V << DMAC_CH1_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH1_SLVIF_DEC_ERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH1_CH_LOCK_CLEARED_INTSTAT : RO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH1_CH_SUSPENDED_INTSTAT : RO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH1_CH_SUSPENDED_INTSTAT_M  (DMAC_CH1_CH_SUSPENDED_INTSTAT_V << DMAC_CH1_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH1_CH_DISABLED_INTSTAT : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH1_CH_DISABLED_INTSTAT_M  (DMAC_CH1_CH_DISABLED_INTSTAT_V << DMAC_CH1_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH1_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH1_CH_ABORTED_INTSTAT : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH1_CH_ABORTED_INTSTAT_M  (DMAC_CH1_CH_ABORTED_INTSTAT_V << DMAC_CH1_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH1_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH1_INTSTATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSTATUS1_REG (DR_REG_DMAC_BASE + 0x18c)
+/** DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH1_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x190)
+/** DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL    (BIT(0))
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_M  (DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V << DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S  0
+/** DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL    (BIT(1))
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_M  (DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_V << DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_DMA_TFR_DONE_INTSIGNAL_S  1
+/** DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL    (BIT(3))
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_M  (DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V << DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S  3
+/** DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL    (BIT(4))
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_M  (DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_V << DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_TRANSCOMP_INTSIGNAL_S  4
+/** DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL    (BIT(5))
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_DEC_ERR_INTSIGNAL_S  5
+/** DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL    (BIT(6))
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_DEC_ERR_INTSIGNAL_S  6
+/** DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SRC_SLV_ERR_INTSIGNAL_S  7
+/** DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_DST_SLV_ERR_INTSIGNAL_S  8
+/** DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL    (BIT(9))
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S  9
+/** DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL    (BIT(10))
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S  10
+/** DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL    (BIT(11))
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S  11
+/** DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL    (BIT(12))
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S  12
+/** DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL : R/W; bitpos: [13];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL    (BIT(13))
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S  13
+/** DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL    (BIT(14))
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S  14
+/** DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL    (BIT(16))
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S  16
+/** DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL    (BIT(17))
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S  17
+/** DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL    (BIT(18))
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S  18
+/** DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL    (BIT(19))
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S  19
+/** DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL    (BIT(20))
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S  20
+/** DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL    (BIT(21))
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S  21
+/** DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL    (BIT(25))
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V << DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S  25
+/** DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL    (BIT(27))
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S  27
+/** DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL    (BIT(28))
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S  28
+/** DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL    (BIT(29))
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_SUSPENDED_INTSIGNAL_S  29
+/** DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL    (BIT(30))
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_DISABLED_INTSIGNAL_S  30
+/** DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL    (BIT(31))
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_M  (DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_V << DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_CH_ABORTED_INTSIGNAL_S  31
+
+/** DMAC_CH1_INTSIGNAL_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTSIGNAL_ENABLE1_REG (DR_REG_DMAC_BASE + 0x194)
+/** DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL    (BIT(0))
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V << DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S  0
+/** DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL    (BIT(1))
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S  1
+/** DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL    (BIT(2))
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V << DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S  2
+/** DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL    (BIT(3))
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH1_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S  3
+
+/** DMAC_CH1_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x198)
+/** DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_V << DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT : WO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_V << DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT : WO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_V << DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : WO; bitpos: [20]; default:
+ *  0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT : WO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT : WO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT : WO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_V << DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT : WO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_V << DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT : WO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_M  (DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_V << DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH1_INTCLEAR1_REG register
+ *  NA
+ */
+#define DMAC_CH1_INTCLEAR1_REG (DR_REG_DMAC_BASE + 0x19c)
+/** DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH1_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH2_SAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SAR0_REG (DR_REG_DMAC_BASE + 0x200)
+/** DMAC_CH2_SAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SAR0    0xFFFFFFFFU
+#define DMAC_CH2_SAR0_M  (DMAC_CH2_SAR0_V << DMAC_CH2_SAR0_S)
+#define DMAC_CH2_SAR0_V  0xFFFFFFFFU
+#define DMAC_CH2_SAR0_S  0
+
+/** DMAC_CH2_SAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_SAR1_REG (DR_REG_DMAC_BASE + 0x204)
+/** DMAC_CH2_SAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SAR1    0xFFFFFFFFU
+#define DMAC_CH2_SAR1_M  (DMAC_CH2_SAR1_V << DMAC_CH2_SAR1_S)
+#define DMAC_CH2_SAR1_V  0xFFFFFFFFU
+#define DMAC_CH2_SAR1_S  0
+
+/** DMAC_CH2_DAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_DAR0_REG (DR_REG_DMAC_BASE + 0x208)
+/** DMAC_CH2_DAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DAR0    0xFFFFFFFFU
+#define DMAC_CH2_DAR0_M  (DMAC_CH2_DAR0_V << DMAC_CH2_DAR0_S)
+#define DMAC_CH2_DAR0_V  0xFFFFFFFFU
+#define DMAC_CH2_DAR0_S  0
+
+/** DMAC_CH2_DAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_DAR1_REG (DR_REG_DMAC_BASE + 0x20c)
+/** DMAC_CH2_DAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DAR1    0xFFFFFFFFU
+#define DMAC_CH2_DAR1_M  (DMAC_CH2_DAR1_V << DMAC_CH2_DAR1_S)
+#define DMAC_CH2_DAR1_V  0xFFFFFFFFU
+#define DMAC_CH2_DAR1_S  0
+
+/** DMAC_CH2_BLOCK_TS0_REG register
+ *  NA
+ */
+#define DMAC_CH2_BLOCK_TS0_REG (DR_REG_DMAC_BASE + 0x210)
+/** DMAC_CH2_BLOCK_TS : R/W; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_BLOCK_TS    0x003FFFFFU
+#define DMAC_CH2_BLOCK_TS_M  (DMAC_CH2_BLOCK_TS_V << DMAC_CH2_BLOCK_TS_S)
+#define DMAC_CH2_BLOCK_TS_V  0x003FFFFFU
+#define DMAC_CH2_BLOCK_TS_S  0
+
+/** DMAC_CH2_CTL0_REG register
+ *  NA
+ */
+#define DMAC_CH2_CTL0_REG (DR_REG_DMAC_BASE + 0x218)
+/** DMAC_CH2_SMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SMS    (BIT(0))
+#define DMAC_CH2_SMS_M  (DMAC_CH2_SMS_V << DMAC_CH2_SMS_S)
+#define DMAC_CH2_SMS_V  0x00000001U
+#define DMAC_CH2_SMS_S  0
+/** DMAC_CH2_DMS : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DMS    (BIT(2))
+#define DMAC_CH2_DMS_M  (DMAC_CH2_DMS_V << DMAC_CH2_DMS_S)
+#define DMAC_CH2_DMS_V  0x00000001U
+#define DMAC_CH2_DMS_S  2
+/** DMAC_CH2_SINC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SINC    (BIT(4))
+#define DMAC_CH2_SINC_M  (DMAC_CH2_SINC_V << DMAC_CH2_SINC_S)
+#define DMAC_CH2_SINC_V  0x00000001U
+#define DMAC_CH2_SINC_S  4
+/** DMAC_CH2_DINC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DINC    (BIT(6))
+#define DMAC_CH2_DINC_M  (DMAC_CH2_DINC_V << DMAC_CH2_DINC_S)
+#define DMAC_CH2_DINC_V  0x00000001U
+#define DMAC_CH2_DINC_S  6
+/** DMAC_CH2_SRC_TR_WIDTH : R/W; bitpos: [10:8]; default: 2;
+ *  NA
+ */
+#define DMAC_CH2_SRC_TR_WIDTH    0x00000007U
+#define DMAC_CH2_SRC_TR_WIDTH_M  (DMAC_CH2_SRC_TR_WIDTH_V << DMAC_CH2_SRC_TR_WIDTH_S)
+#define DMAC_CH2_SRC_TR_WIDTH_V  0x00000007U
+#define DMAC_CH2_SRC_TR_WIDTH_S  8
+/** DMAC_CH2_DST_TR_WIDTH : R/W; bitpos: [13:11]; default: 2;
+ *  NA
+ */
+#define DMAC_CH2_DST_TR_WIDTH    0x00000007U
+#define DMAC_CH2_DST_TR_WIDTH_M  (DMAC_CH2_DST_TR_WIDTH_V << DMAC_CH2_DST_TR_WIDTH_S)
+#define DMAC_CH2_DST_TR_WIDTH_V  0x00000007U
+#define DMAC_CH2_DST_TR_WIDTH_S  11
+/** DMAC_CH2_SRC_MSIZE : R/W; bitpos: [17:14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_MSIZE    0x0000000FU
+#define DMAC_CH2_SRC_MSIZE_M  (DMAC_CH2_SRC_MSIZE_V << DMAC_CH2_SRC_MSIZE_S)
+#define DMAC_CH2_SRC_MSIZE_V  0x0000000FU
+#define DMAC_CH2_SRC_MSIZE_S  14
+/** DMAC_CH2_DST_MSIZE : R/W; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_MSIZE    0x0000000FU
+#define DMAC_CH2_DST_MSIZE_M  (DMAC_CH2_DST_MSIZE_V << DMAC_CH2_DST_MSIZE_S)
+#define DMAC_CH2_DST_MSIZE_V  0x0000000FU
+#define DMAC_CH2_DST_MSIZE_S  18
+/** DMAC_CH2_AR_CACHE : R/W; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AR_CACHE    0x0000000FU
+#define DMAC_CH2_AR_CACHE_M  (DMAC_CH2_AR_CACHE_V << DMAC_CH2_AR_CACHE_S)
+#define DMAC_CH2_AR_CACHE_V  0x0000000FU
+#define DMAC_CH2_AR_CACHE_S  22
+/** DMAC_CH2_AW_CACHE : R/W; bitpos: [29:26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AW_CACHE    0x0000000FU
+#define DMAC_CH2_AW_CACHE_M  (DMAC_CH2_AW_CACHE_V << DMAC_CH2_AW_CACHE_S)
+#define DMAC_CH2_AW_CACHE_V  0x0000000FU
+#define DMAC_CH2_AW_CACHE_S  26
+/** DMAC_CH2_NONPOSTED_LASTWRITE_EN : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_NONPOSTED_LASTWRITE_EN    (BIT(30))
+#define DMAC_CH2_NONPOSTED_LASTWRITE_EN_M  (DMAC_CH2_NONPOSTED_LASTWRITE_EN_V << DMAC_CH2_NONPOSTED_LASTWRITE_EN_S)
+#define DMAC_CH2_NONPOSTED_LASTWRITE_EN_V  0x00000001U
+#define DMAC_CH2_NONPOSTED_LASTWRITE_EN_S  30
+
+/** DMAC_CH2_CTL1_REG register
+ *  NA
+ */
+#define DMAC_CH2_CTL1_REG (DR_REG_DMAC_BASE + 0x21c)
+/** DMAC_CH2_AR_PROT : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AR_PROT    0x00000007U
+#define DMAC_CH2_AR_PROT_M  (DMAC_CH2_AR_PROT_V << DMAC_CH2_AR_PROT_S)
+#define DMAC_CH2_AR_PROT_V  0x00000007U
+#define DMAC_CH2_AR_PROT_S  0
+/** DMAC_CH2_AW_PROT : R/W; bitpos: [5:3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AW_PROT    0x00000007U
+#define DMAC_CH2_AW_PROT_M  (DMAC_CH2_AW_PROT_V << DMAC_CH2_AW_PROT_S)
+#define DMAC_CH2_AW_PROT_V  0x00000007U
+#define DMAC_CH2_AW_PROT_S  3
+/** DMAC_CH2_ARLEN_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ARLEN_EN    (BIT(6))
+#define DMAC_CH2_ARLEN_EN_M  (DMAC_CH2_ARLEN_EN_V << DMAC_CH2_ARLEN_EN_S)
+#define DMAC_CH2_ARLEN_EN_V  0x00000001U
+#define DMAC_CH2_ARLEN_EN_S  6
+/** DMAC_CH2_ARLEN : R/W; bitpos: [14:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ARLEN    0x000000FFU
+#define DMAC_CH2_ARLEN_M  (DMAC_CH2_ARLEN_V << DMAC_CH2_ARLEN_S)
+#define DMAC_CH2_ARLEN_V  0x000000FFU
+#define DMAC_CH2_ARLEN_S  7
+/** DMAC_CH2_AWLEN_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AWLEN_EN    (BIT(15))
+#define DMAC_CH2_AWLEN_EN_M  (DMAC_CH2_AWLEN_EN_V << DMAC_CH2_AWLEN_EN_S)
+#define DMAC_CH2_AWLEN_EN_V  0x00000001U
+#define DMAC_CH2_AWLEN_EN_S  15
+/** DMAC_CH2_AWLEN : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AWLEN    0x000000FFU
+#define DMAC_CH2_AWLEN_M  (DMAC_CH2_AWLEN_V << DMAC_CH2_AWLEN_S)
+#define DMAC_CH2_AWLEN_V  0x000000FFU
+#define DMAC_CH2_AWLEN_S  16
+/** DMAC_CH2_SRC_STAT_EN : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_STAT_EN    (BIT(24))
+#define DMAC_CH2_SRC_STAT_EN_M  (DMAC_CH2_SRC_STAT_EN_V << DMAC_CH2_SRC_STAT_EN_S)
+#define DMAC_CH2_SRC_STAT_EN_V  0x00000001U
+#define DMAC_CH2_SRC_STAT_EN_S  24
+/** DMAC_CH2_DST_STAT_EN : R/W; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_STAT_EN    (BIT(25))
+#define DMAC_CH2_DST_STAT_EN_M  (DMAC_CH2_DST_STAT_EN_V << DMAC_CH2_DST_STAT_EN_S)
+#define DMAC_CH2_DST_STAT_EN_V  0x00000001U
+#define DMAC_CH2_DST_STAT_EN_S  25
+/** DMAC_CH2_IOC_BLKTFR : R/W; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_IOC_BLKTFR    (BIT(26))
+#define DMAC_CH2_IOC_BLKTFR_M  (DMAC_CH2_IOC_BLKTFR_V << DMAC_CH2_IOC_BLKTFR_S)
+#define DMAC_CH2_IOC_BLKTFR_V  0x00000001U
+#define DMAC_CH2_IOC_BLKTFR_S  26
+/** DMAC_CH2_SHADOWREG_OR_LLI_LAST : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SHADOWREG_OR_LLI_LAST    (BIT(30))
+#define DMAC_CH2_SHADOWREG_OR_LLI_LAST_M  (DMAC_CH2_SHADOWREG_OR_LLI_LAST_V << DMAC_CH2_SHADOWREG_OR_LLI_LAST_S)
+#define DMAC_CH2_SHADOWREG_OR_LLI_LAST_V  0x00000001U
+#define DMAC_CH2_SHADOWREG_OR_LLI_LAST_S  30
+/** DMAC_CH2_SHADOWREG_OR_LLI_VALID : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SHADOWREG_OR_LLI_VALID    (BIT(31))
+#define DMAC_CH2_SHADOWREG_OR_LLI_VALID_M  (DMAC_CH2_SHADOWREG_OR_LLI_VALID_V << DMAC_CH2_SHADOWREG_OR_LLI_VALID_S)
+#define DMAC_CH2_SHADOWREG_OR_LLI_VALID_V  0x00000001U
+#define DMAC_CH2_SHADOWREG_OR_LLI_VALID_S  31
+
+/** DMAC_CH2_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CH2_CFG0_REG (DR_REG_DMAC_BASE + 0x220)
+/** DMAC_CH2_SRC_MULTBLK_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH2_SRC_MULTBLK_TYPE_M  (DMAC_CH2_SRC_MULTBLK_TYPE_V << DMAC_CH2_SRC_MULTBLK_TYPE_S)
+#define DMAC_CH2_SRC_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH2_SRC_MULTBLK_TYPE_S  0
+/** DMAC_CH2_DST_MULTBLK_TYPE : R/W; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH2_DST_MULTBLK_TYPE_M  (DMAC_CH2_DST_MULTBLK_TYPE_V << DMAC_CH2_DST_MULTBLK_TYPE_S)
+#define DMAC_CH2_DST_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH2_DST_MULTBLK_TYPE_S  2
+/** DMAC_CH2_RD_UID : RO; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_RD_UID    0x0000000FU
+#define DMAC_CH2_RD_UID_M  (DMAC_CH2_RD_UID_V << DMAC_CH2_RD_UID_S)
+#define DMAC_CH2_RD_UID_V  0x0000000FU
+#define DMAC_CH2_RD_UID_S  18
+/** DMAC_CH2_WR_UID : RO; bitpos: [28:25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_WR_UID    0x0000000FU
+#define DMAC_CH2_WR_UID_M  (DMAC_CH2_WR_UID_V << DMAC_CH2_WR_UID_S)
+#define DMAC_CH2_WR_UID_V  0x0000000FU
+#define DMAC_CH2_WR_UID_S  25
+
+/** DMAC_CH2_CFG1_REG register
+ *  NA
+ */
+#define DMAC_CH2_CFG1_REG (DR_REG_DMAC_BASE + 0x224)
+/** DMAC_CH2_TT_FC : R/W; bitpos: [2:0]; default: 3;
+ *  NA
+ */
+#define DMAC_CH2_TT_FC    0x00000007U
+#define DMAC_CH2_TT_FC_M  (DMAC_CH2_TT_FC_V << DMAC_CH2_TT_FC_S)
+#define DMAC_CH2_TT_FC_V  0x00000007U
+#define DMAC_CH2_TT_FC_S  0
+/** DMAC_CH2_HS_SEL_SRC : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_HS_SEL_SRC    (BIT(3))
+#define DMAC_CH2_HS_SEL_SRC_M  (DMAC_CH2_HS_SEL_SRC_V << DMAC_CH2_HS_SEL_SRC_S)
+#define DMAC_CH2_HS_SEL_SRC_V  0x00000001U
+#define DMAC_CH2_HS_SEL_SRC_S  3
+/** DMAC_CH2_HS_SEL_DST : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_HS_SEL_DST    (BIT(4))
+#define DMAC_CH2_HS_SEL_DST_M  (DMAC_CH2_HS_SEL_DST_V << DMAC_CH2_HS_SEL_DST_S)
+#define DMAC_CH2_HS_SEL_DST_V  0x00000001U
+#define DMAC_CH2_HS_SEL_DST_S  4
+/** DMAC_CH2_SRC_HWHS_POL : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_HWHS_POL    (BIT(5))
+#define DMAC_CH2_SRC_HWHS_POL_M  (DMAC_CH2_SRC_HWHS_POL_V << DMAC_CH2_SRC_HWHS_POL_S)
+#define DMAC_CH2_SRC_HWHS_POL_V  0x00000001U
+#define DMAC_CH2_SRC_HWHS_POL_S  5
+/** DMAC_CH2_DST_HWHS_POL : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_HWHS_POL    (BIT(6))
+#define DMAC_CH2_DST_HWHS_POL_M  (DMAC_CH2_DST_HWHS_POL_V << DMAC_CH2_DST_HWHS_POL_S)
+#define DMAC_CH2_DST_HWHS_POL_V  0x00000001U
+#define DMAC_CH2_DST_HWHS_POL_S  6
+/** DMAC_CH2_SRC_PER : R/W; bitpos: [8:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_PER    0x00000003U
+#define DMAC_CH2_SRC_PER_M  (DMAC_CH2_SRC_PER_V << DMAC_CH2_SRC_PER_S)
+#define DMAC_CH2_SRC_PER_V  0x00000003U
+#define DMAC_CH2_SRC_PER_S  7
+/** DMAC_CH2_DST_PER : R/W; bitpos: [13:12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_PER    0x00000003U
+#define DMAC_CH2_DST_PER_M  (DMAC_CH2_DST_PER_V << DMAC_CH2_DST_PER_S)
+#define DMAC_CH2_DST_PER_V  0x00000003U
+#define DMAC_CH2_DST_PER_S  12
+/** DMAC_CH2_CH_PRIOR : R/W; bitpos: [19:17]; default: 2;
+ *  NA
+ */
+#define DMAC_CH2_CH_PRIOR    0x00000007U
+#define DMAC_CH2_CH_PRIOR_M  (DMAC_CH2_CH_PRIOR_V << DMAC_CH2_CH_PRIOR_S)
+#define DMAC_CH2_CH_PRIOR_V  0x00000007U
+#define DMAC_CH2_CH_PRIOR_S  17
+/** DMAC_CH2_LOCK_CH : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LOCK_CH    (BIT(20))
+#define DMAC_CH2_LOCK_CH_M  (DMAC_CH2_LOCK_CH_V << DMAC_CH2_LOCK_CH_S)
+#define DMAC_CH2_LOCK_CH_V  0x00000001U
+#define DMAC_CH2_LOCK_CH_S  20
+/** DMAC_CH2_LOCK_CH_L : RO; bitpos: [22:21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LOCK_CH_L    0x00000003U
+#define DMAC_CH2_LOCK_CH_L_M  (DMAC_CH2_LOCK_CH_L_V << DMAC_CH2_LOCK_CH_L_S)
+#define DMAC_CH2_LOCK_CH_L_V  0x00000003U
+#define DMAC_CH2_LOCK_CH_L_S  21
+/** DMAC_CH2_SRC_OSR_LMT : R/W; bitpos: [26:23]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_OSR_LMT    0x0000000FU
+#define DMAC_CH2_SRC_OSR_LMT_M  (DMAC_CH2_SRC_OSR_LMT_V << DMAC_CH2_SRC_OSR_LMT_S)
+#define DMAC_CH2_SRC_OSR_LMT_V  0x0000000FU
+#define DMAC_CH2_SRC_OSR_LMT_S  23
+/** DMAC_CH2_DST_OSR_LMT : R/W; bitpos: [30:27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_OSR_LMT    0x0000000FU
+#define DMAC_CH2_DST_OSR_LMT_M  (DMAC_CH2_DST_OSR_LMT_V << DMAC_CH2_DST_OSR_LMT_S)
+#define DMAC_CH2_DST_OSR_LMT_V  0x0000000FU
+#define DMAC_CH2_DST_OSR_LMT_S  27
+
+/** DMAC_CH2_LLP0_REG register
+ *  NA
+ */
+#define DMAC_CH2_LLP0_REG (DR_REG_DMAC_BASE + 0x228)
+/** DMAC_CH2_LMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LMS    (BIT(0))
+#define DMAC_CH2_LMS_M  (DMAC_CH2_LMS_V << DMAC_CH2_LMS_S)
+#define DMAC_CH2_LMS_V  0x00000001U
+#define DMAC_CH2_LMS_S  0
+/** DMAC_CH2_LOC0 : R/W; bitpos: [31:6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LOC0    0x03FFFFFFU
+#define DMAC_CH2_LOC0_M  (DMAC_CH2_LOC0_V << DMAC_CH2_LOC0_S)
+#define DMAC_CH2_LOC0_V  0x03FFFFFFU
+#define DMAC_CH2_LOC0_S  6
+
+/** DMAC_CH2_LLP1_REG register
+ *  NA
+ */
+#define DMAC_CH2_LLP1_REG (DR_REG_DMAC_BASE + 0x22c)
+/** DMAC_CH2_LOC1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LOC1    0xFFFFFFFFU
+#define DMAC_CH2_LOC1_M  (DMAC_CH2_LOC1_V << DMAC_CH2_LOC1_S)
+#define DMAC_CH2_LOC1_V  0xFFFFFFFFU
+#define DMAC_CH2_LOC1_S  0
+
+/** DMAC_CH2_STATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH2_STATUS0_REG (DR_REG_DMAC_BASE + 0x230)
+/** DMAC_CH2_CMPLTD_BLK_TFR_SIZE : RO; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CMPLTD_BLK_TFR_SIZE    0x003FFFFFU
+#define DMAC_CH2_CMPLTD_BLK_TFR_SIZE_M  (DMAC_CH2_CMPLTD_BLK_TFR_SIZE_V << DMAC_CH2_CMPLTD_BLK_TFR_SIZE_S)
+#define DMAC_CH2_CMPLTD_BLK_TFR_SIZE_V  0x003FFFFFU
+#define DMAC_CH2_CMPLTD_BLK_TFR_SIZE_S  0
+
+/** DMAC_CH2_STATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH2_STATUS1_REG (DR_REG_DMAC_BASE + 0x234)
+/** DMAC_CH2_DATA_LEFT_IN_FIFO : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DATA_LEFT_IN_FIFO    0x00007FFFU
+#define DMAC_CH2_DATA_LEFT_IN_FIFO_M  (DMAC_CH2_DATA_LEFT_IN_FIFO_V << DMAC_CH2_DATA_LEFT_IN_FIFO_S)
+#define DMAC_CH2_DATA_LEFT_IN_FIFO_V  0x00007FFFU
+#define DMAC_CH2_DATA_LEFT_IN_FIFO_S  0
+
+/** DMAC_CH2_SWHSSRC0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SWHSSRC0_REG (DR_REG_DMAC_BASE + 0x238)
+/** DMAC_CH2_SWHS_REQ_SRC : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_REQ_SRC    (BIT(0))
+#define DMAC_CH2_SWHS_REQ_SRC_M  (DMAC_CH2_SWHS_REQ_SRC_V << DMAC_CH2_SWHS_REQ_SRC_S)
+#define DMAC_CH2_SWHS_REQ_SRC_V  0x00000001U
+#define DMAC_CH2_SWHS_REQ_SRC_S  0
+/** DMAC_CH2_SWHS_REQ_SRC_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_REQ_SRC_WE    (BIT(1))
+#define DMAC_CH2_SWHS_REQ_SRC_WE_M  (DMAC_CH2_SWHS_REQ_SRC_WE_V << DMAC_CH2_SWHS_REQ_SRC_WE_S)
+#define DMAC_CH2_SWHS_REQ_SRC_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_REQ_SRC_WE_S  1
+/** DMAC_CH2_SWHS_SGLREQ_SRC : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_SGLREQ_SRC    (BIT(2))
+#define DMAC_CH2_SWHS_SGLREQ_SRC_M  (DMAC_CH2_SWHS_SGLREQ_SRC_V << DMAC_CH2_SWHS_SGLREQ_SRC_S)
+#define DMAC_CH2_SWHS_SGLREQ_SRC_V  0x00000001U
+#define DMAC_CH2_SWHS_SGLREQ_SRC_S  2
+/** DMAC_CH2_SWHS_SGLREQ_SRC_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_SGLREQ_SRC_WE    (BIT(3))
+#define DMAC_CH2_SWHS_SGLREQ_SRC_WE_M  (DMAC_CH2_SWHS_SGLREQ_SRC_WE_V << DMAC_CH2_SWHS_SGLREQ_SRC_WE_S)
+#define DMAC_CH2_SWHS_SGLREQ_SRC_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_SGLREQ_SRC_WE_S  3
+/** DMAC_CH2_SWHS_LST_SRC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_LST_SRC    (BIT(4))
+#define DMAC_CH2_SWHS_LST_SRC_M  (DMAC_CH2_SWHS_LST_SRC_V << DMAC_CH2_SWHS_LST_SRC_S)
+#define DMAC_CH2_SWHS_LST_SRC_V  0x00000001U
+#define DMAC_CH2_SWHS_LST_SRC_S  4
+/** DMAC_CH2_SWHS_LST_SRC_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_LST_SRC_WE    (BIT(5))
+#define DMAC_CH2_SWHS_LST_SRC_WE_M  (DMAC_CH2_SWHS_LST_SRC_WE_V << DMAC_CH2_SWHS_LST_SRC_WE_S)
+#define DMAC_CH2_SWHS_LST_SRC_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_LST_SRC_WE_S  5
+
+/** DMAC_CH2_SWHSDST0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SWHSDST0_REG (DR_REG_DMAC_BASE + 0x240)
+/** DMAC_CH2_SWHS_REQ_DST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_REQ_DST    (BIT(0))
+#define DMAC_CH2_SWHS_REQ_DST_M  (DMAC_CH2_SWHS_REQ_DST_V << DMAC_CH2_SWHS_REQ_DST_S)
+#define DMAC_CH2_SWHS_REQ_DST_V  0x00000001U
+#define DMAC_CH2_SWHS_REQ_DST_S  0
+/** DMAC_CH2_SWHS_REQ_DST_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_REQ_DST_WE    (BIT(1))
+#define DMAC_CH2_SWHS_REQ_DST_WE_M  (DMAC_CH2_SWHS_REQ_DST_WE_V << DMAC_CH2_SWHS_REQ_DST_WE_S)
+#define DMAC_CH2_SWHS_REQ_DST_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_REQ_DST_WE_S  1
+/** DMAC_CH2_SWHS_SGLREQ_DST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_SGLREQ_DST    (BIT(2))
+#define DMAC_CH2_SWHS_SGLREQ_DST_M  (DMAC_CH2_SWHS_SGLREQ_DST_V << DMAC_CH2_SWHS_SGLREQ_DST_S)
+#define DMAC_CH2_SWHS_SGLREQ_DST_V  0x00000001U
+#define DMAC_CH2_SWHS_SGLREQ_DST_S  2
+/** DMAC_CH2_SWHS_SGLREQ_DST_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_SGLREQ_DST_WE    (BIT(3))
+#define DMAC_CH2_SWHS_SGLREQ_DST_WE_M  (DMAC_CH2_SWHS_SGLREQ_DST_WE_V << DMAC_CH2_SWHS_SGLREQ_DST_WE_S)
+#define DMAC_CH2_SWHS_SGLREQ_DST_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_SGLREQ_DST_WE_S  3
+/** DMAC_CH2_SWHS_LST_DST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_LST_DST    (BIT(4))
+#define DMAC_CH2_SWHS_LST_DST_M  (DMAC_CH2_SWHS_LST_DST_V << DMAC_CH2_SWHS_LST_DST_S)
+#define DMAC_CH2_SWHS_LST_DST_V  0x00000001U
+#define DMAC_CH2_SWHS_LST_DST_S  4
+/** DMAC_CH2_SWHS_LST_DST_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SWHS_LST_DST_WE    (BIT(5))
+#define DMAC_CH2_SWHS_LST_DST_WE_M  (DMAC_CH2_SWHS_LST_DST_WE_V << DMAC_CH2_SWHS_LST_DST_WE_S)
+#define DMAC_CH2_SWHS_LST_DST_WE_V  0x00000001U
+#define DMAC_CH2_SWHS_LST_DST_WE_S  5
+
+/** DMAC_CH2_BLK_TFR_RESUMEREQ0_REG register
+ *  NA
+ */
+#define DMAC_CH2_BLK_TFR_RESUMEREQ0_REG (DR_REG_DMAC_BASE + 0x248)
+/** DMAC_CH2_BLK_TFR_RESUMEREQ : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_BLK_TFR_RESUMEREQ    (BIT(0))
+#define DMAC_CH2_BLK_TFR_RESUMEREQ_M  (DMAC_CH2_BLK_TFR_RESUMEREQ_V << DMAC_CH2_BLK_TFR_RESUMEREQ_S)
+#define DMAC_CH2_BLK_TFR_RESUMEREQ_V  0x00000001U
+#define DMAC_CH2_BLK_TFR_RESUMEREQ_S  0
+
+/** DMAC_CH2_AXI_ID0_REG register
+ *  NA
+ */
+#define DMAC_CH2_AXI_ID0_REG (DR_REG_DMAC_BASE + 0x250)
+/** DMAC_CH2_AXI_READ_ID_SUFFIX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AXI_READ_ID_SUFFIX    (BIT(0))
+#define DMAC_CH2_AXI_READ_ID_SUFFIX_M  (DMAC_CH2_AXI_READ_ID_SUFFIX_V << DMAC_CH2_AXI_READ_ID_SUFFIX_S)
+#define DMAC_CH2_AXI_READ_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH2_AXI_READ_ID_SUFFIX_S  0
+/** DMAC_CH2_AXI_WRITE_ID_SUFFIX : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AXI_WRITE_ID_SUFFIX    (BIT(16))
+#define DMAC_CH2_AXI_WRITE_ID_SUFFIX_M  (DMAC_CH2_AXI_WRITE_ID_SUFFIX_V << DMAC_CH2_AXI_WRITE_ID_SUFFIX_S)
+#define DMAC_CH2_AXI_WRITE_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH2_AXI_WRITE_ID_SUFFIX_S  16
+
+/** DMAC_CH2_AXI_QOS0_REG register
+ *  NA
+ */
+#define DMAC_CH2_AXI_QOS0_REG (DR_REG_DMAC_BASE + 0x258)
+/** DMAC_CH2_AXI_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AXI_AWQOS    0x0000000FU
+#define DMAC_CH2_AXI_AWQOS_M  (DMAC_CH2_AXI_AWQOS_V << DMAC_CH2_AXI_AWQOS_S)
+#define DMAC_CH2_AXI_AWQOS_V  0x0000000FU
+#define DMAC_CH2_AXI_AWQOS_S  0
+/** DMAC_CH2_AXI_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_AXI_ARQOS    0x0000000FU
+#define DMAC_CH2_AXI_ARQOS_M  (DMAC_CH2_AXI_ARQOS_V << DMAC_CH2_AXI_ARQOS_S)
+#define DMAC_CH2_AXI_ARQOS_V  0x0000000FU
+#define DMAC_CH2_AXI_ARQOS_S  4
+
+/** DMAC_CH2_SSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SSTAT0_REG (DR_REG_DMAC_BASE + 0x260)
+/** DMAC_CH2_SSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SSTAT    0xFFFFFFFFU
+#define DMAC_CH2_SSTAT_M  (DMAC_CH2_SSTAT_V << DMAC_CH2_SSTAT_S)
+#define DMAC_CH2_SSTAT_V  0xFFFFFFFFU
+#define DMAC_CH2_SSTAT_S  0
+
+/** DMAC_CH2_DSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH2_DSTAT0_REG (DR_REG_DMAC_BASE + 0x268)
+/** DMAC_CH2_DSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DSTAT    0xFFFFFFFFU
+#define DMAC_CH2_DSTAT_M  (DMAC_CH2_DSTAT_V << DMAC_CH2_DSTAT_S)
+#define DMAC_CH2_DSTAT_V  0xFFFFFFFFU
+#define DMAC_CH2_DSTAT_S  0
+
+/** DMAC_CH2_SSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_SSTATAR0_REG (DR_REG_DMAC_BASE + 0x270)
+/** DMAC_CH2_SSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SSTATAR0    0xFFFFFFFFU
+#define DMAC_CH2_SSTATAR0_M  (DMAC_CH2_SSTATAR0_V << DMAC_CH2_SSTATAR0_S)
+#define DMAC_CH2_SSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH2_SSTATAR0_S  0
+
+/** DMAC_CH2_SSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_SSTATAR1_REG (DR_REG_DMAC_BASE + 0x274)
+/** DMAC_CH2_SSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SSTATAR1    0xFFFFFFFFU
+#define DMAC_CH2_SSTATAR1_M  (DMAC_CH2_SSTATAR1_V << DMAC_CH2_SSTATAR1_S)
+#define DMAC_CH2_SSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH2_SSTATAR1_S  0
+
+/** DMAC_CH2_DSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_DSTATAR0_REG (DR_REG_DMAC_BASE + 0x278)
+/** DMAC_CH2_DSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DSTATAR0    0xFFFFFFFFU
+#define DMAC_CH2_DSTATAR0_M  (DMAC_CH2_DSTATAR0_V << DMAC_CH2_DSTATAR0_S)
+#define DMAC_CH2_DSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH2_DSTATAR0_S  0
+
+/** DMAC_CH2_DSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_DSTATAR1_REG (DR_REG_DMAC_BASE + 0x27c)
+/** DMAC_CH2_DSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DSTATAR1    0xFFFFFFFFU
+#define DMAC_CH2_DSTATAR1_M  (DMAC_CH2_DSTATAR1_V << DMAC_CH2_DSTATAR1_S)
+#define DMAC_CH2_DSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH2_DSTATAR1_S  0
+
+/** DMAC_CH2_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x280)
+/** DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_V << DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_V << DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_V << DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : R/W; bitpos: [13]; default:
+ *  1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_V << DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_V << DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_M  (DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_V << DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH2_INTSTATUS_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSTATUS_ENABLE1_REG (DR_REG_DMAC_BASE + 0x284)
+/** DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH2_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x288)
+/** DMAC_CH2_BLOCK_TFR_DONE_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH2_DMA_TFR_DONE_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH2_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH2_DMA_TFR_DONE_INTSTAT_V << DMAC_CH2_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH2_SRC_TRANSCOMP_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH2_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH2_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH2_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH2_DST_TRANSCOMP_INTSTAT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH2_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH2_DST_TRANSCOMP_INTSTAT_V << DMAC_CH2_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH2_SRC_DEC_ERR_INTSTAT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH2_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH2_SRC_DEC_ERR_INTSTAT_V << DMAC_CH2_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH2_DST_DEC_ERR_INTSTAT : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH2_DST_DEC_ERR_INTSTAT_M  (DMAC_CH2_DST_DEC_ERR_INTSTAT_V << DMAC_CH2_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH2_SRC_SLV_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH2_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH2_SRC_SLV_ERR_INTSTAT_V << DMAC_CH2_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH2_DST_SLV_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH2_DST_SLV_ERR_INTSTAT_M  (DMAC_CH2_DST_SLV_ERR_INTSTAT_V << DMAC_CH2_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH2_SLVIF_DEC_ERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH2_CH_LOCK_CLEARED_INTSTAT : RO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH2_CH_SUSPENDED_INTSTAT : RO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH2_CH_SUSPENDED_INTSTAT_M  (DMAC_CH2_CH_SUSPENDED_INTSTAT_V << DMAC_CH2_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH2_CH_DISABLED_INTSTAT : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH2_CH_DISABLED_INTSTAT_M  (DMAC_CH2_CH_DISABLED_INTSTAT_V << DMAC_CH2_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH2_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH2_CH_ABORTED_INTSTAT : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH2_CH_ABORTED_INTSTAT_M  (DMAC_CH2_CH_ABORTED_INTSTAT_V << DMAC_CH2_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH2_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH2_INTSTATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSTATUS1_REG (DR_REG_DMAC_BASE + 0x28c)
+/** DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH2_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x290)
+/** DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL    (BIT(0))
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_M  (DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V << DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S  0
+/** DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL    (BIT(1))
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_M  (DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_V << DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_DMA_TFR_DONE_INTSIGNAL_S  1
+/** DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL    (BIT(3))
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_M  (DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V << DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S  3
+/** DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL    (BIT(4))
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_M  (DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_V << DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_TRANSCOMP_INTSIGNAL_S  4
+/** DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL    (BIT(5))
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_DEC_ERR_INTSIGNAL_S  5
+/** DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL    (BIT(6))
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_DEC_ERR_INTSIGNAL_S  6
+/** DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SRC_SLV_ERR_INTSIGNAL_S  7
+/** DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_DST_SLV_ERR_INTSIGNAL_S  8
+/** DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL    (BIT(9))
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S  9
+/** DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL    (BIT(10))
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S  10
+/** DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL    (BIT(11))
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S  11
+/** DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL    (BIT(12))
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S  12
+/** DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL : R/W; bitpos: [13];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL    (BIT(13))
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S  13
+/** DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL    (BIT(14))
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S  14
+/** DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL    (BIT(16))
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S  16
+/** DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL    (BIT(17))
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S  17
+/** DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL    (BIT(18))
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S  18
+/** DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL    (BIT(19))
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S  19
+/** DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL    (BIT(20))
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S  20
+/** DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL    (BIT(21))
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S  21
+/** DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL    (BIT(25))
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V << DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S  25
+/** DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL    (BIT(27))
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S  27
+/** DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL    (BIT(28))
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S  28
+/** DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL    (BIT(29))
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_SUSPENDED_INTSIGNAL_S  29
+/** DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL    (BIT(30))
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_DISABLED_INTSIGNAL_S  30
+/** DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL    (BIT(31))
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_M  (DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_V << DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_CH_ABORTED_INTSIGNAL_S  31
+
+/** DMAC_CH2_INTSIGNAL_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTSIGNAL_ENABLE1_REG (DR_REG_DMAC_BASE + 0x294)
+/** DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL    (BIT(0))
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V << DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S  0
+/** DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL    (BIT(1))
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S  1
+/** DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL    (BIT(2))
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V << DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S  2
+/** DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL    (BIT(3))
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH2_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S  3
+
+/** DMAC_CH2_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x298)
+/** DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_V << DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT : WO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_V << DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT : WO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_V << DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : WO; bitpos: [20]; default:
+ *  0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT : WO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT : WO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT : WO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_V << DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT : WO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_V << DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT : WO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_M  (DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_V << DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH2_INTCLEAR1_REG register
+ *  NA
+ */
+#define DMAC_CH2_INTCLEAR1_REG (DR_REG_DMAC_BASE + 0x29c)
+/** DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH2_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH3_SAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SAR0_REG (DR_REG_DMAC_BASE + 0x300)
+/** DMAC_CH3_SAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SAR0    0xFFFFFFFFU
+#define DMAC_CH3_SAR0_M  (DMAC_CH3_SAR0_V << DMAC_CH3_SAR0_S)
+#define DMAC_CH3_SAR0_V  0xFFFFFFFFU
+#define DMAC_CH3_SAR0_S  0
+
+/** DMAC_CH3_SAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_SAR1_REG (DR_REG_DMAC_BASE + 0x304)
+/** DMAC_CH3_SAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SAR1    0xFFFFFFFFU
+#define DMAC_CH3_SAR1_M  (DMAC_CH3_SAR1_V << DMAC_CH3_SAR1_S)
+#define DMAC_CH3_SAR1_V  0xFFFFFFFFU
+#define DMAC_CH3_SAR1_S  0
+
+/** DMAC_CH3_DAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_DAR0_REG (DR_REG_DMAC_BASE + 0x308)
+/** DMAC_CH3_DAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DAR0    0xFFFFFFFFU
+#define DMAC_CH3_DAR0_M  (DMAC_CH3_DAR0_V << DMAC_CH3_DAR0_S)
+#define DMAC_CH3_DAR0_V  0xFFFFFFFFU
+#define DMAC_CH3_DAR0_S  0
+
+/** DMAC_CH3_DAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_DAR1_REG (DR_REG_DMAC_BASE + 0x30c)
+/** DMAC_CH3_DAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DAR1    0xFFFFFFFFU
+#define DMAC_CH3_DAR1_M  (DMAC_CH3_DAR1_V << DMAC_CH3_DAR1_S)
+#define DMAC_CH3_DAR1_V  0xFFFFFFFFU
+#define DMAC_CH3_DAR1_S  0
+
+/** DMAC_CH3_BLOCK_TS0_REG register
+ *  NA
+ */
+#define DMAC_CH3_BLOCK_TS0_REG (DR_REG_DMAC_BASE + 0x310)
+/** DMAC_CH3_BLOCK_TS : R/W; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_BLOCK_TS    0x003FFFFFU
+#define DMAC_CH3_BLOCK_TS_M  (DMAC_CH3_BLOCK_TS_V << DMAC_CH3_BLOCK_TS_S)
+#define DMAC_CH3_BLOCK_TS_V  0x003FFFFFU
+#define DMAC_CH3_BLOCK_TS_S  0
+
+/** DMAC_CH3_CTL0_REG register
+ *  NA
+ */
+#define DMAC_CH3_CTL0_REG (DR_REG_DMAC_BASE + 0x318)
+/** DMAC_CH3_SMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SMS    (BIT(0))
+#define DMAC_CH3_SMS_M  (DMAC_CH3_SMS_V << DMAC_CH3_SMS_S)
+#define DMAC_CH3_SMS_V  0x00000001U
+#define DMAC_CH3_SMS_S  0
+/** DMAC_CH3_DMS : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DMS    (BIT(2))
+#define DMAC_CH3_DMS_M  (DMAC_CH3_DMS_V << DMAC_CH3_DMS_S)
+#define DMAC_CH3_DMS_V  0x00000001U
+#define DMAC_CH3_DMS_S  2
+/** DMAC_CH3_SINC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SINC    (BIT(4))
+#define DMAC_CH3_SINC_M  (DMAC_CH3_SINC_V << DMAC_CH3_SINC_S)
+#define DMAC_CH3_SINC_V  0x00000001U
+#define DMAC_CH3_SINC_S  4
+/** DMAC_CH3_DINC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DINC    (BIT(6))
+#define DMAC_CH3_DINC_M  (DMAC_CH3_DINC_V << DMAC_CH3_DINC_S)
+#define DMAC_CH3_DINC_V  0x00000001U
+#define DMAC_CH3_DINC_S  6
+/** DMAC_CH3_SRC_TR_WIDTH : R/W; bitpos: [10:8]; default: 2;
+ *  NA
+ */
+#define DMAC_CH3_SRC_TR_WIDTH    0x00000007U
+#define DMAC_CH3_SRC_TR_WIDTH_M  (DMAC_CH3_SRC_TR_WIDTH_V << DMAC_CH3_SRC_TR_WIDTH_S)
+#define DMAC_CH3_SRC_TR_WIDTH_V  0x00000007U
+#define DMAC_CH3_SRC_TR_WIDTH_S  8
+/** DMAC_CH3_DST_TR_WIDTH : R/W; bitpos: [13:11]; default: 2;
+ *  NA
+ */
+#define DMAC_CH3_DST_TR_WIDTH    0x00000007U
+#define DMAC_CH3_DST_TR_WIDTH_M  (DMAC_CH3_DST_TR_WIDTH_V << DMAC_CH3_DST_TR_WIDTH_S)
+#define DMAC_CH3_DST_TR_WIDTH_V  0x00000007U
+#define DMAC_CH3_DST_TR_WIDTH_S  11
+/** DMAC_CH3_SRC_MSIZE : R/W; bitpos: [17:14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_MSIZE    0x0000000FU
+#define DMAC_CH3_SRC_MSIZE_M  (DMAC_CH3_SRC_MSIZE_V << DMAC_CH3_SRC_MSIZE_S)
+#define DMAC_CH3_SRC_MSIZE_V  0x0000000FU
+#define DMAC_CH3_SRC_MSIZE_S  14
+/** DMAC_CH3_DST_MSIZE : R/W; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_MSIZE    0x0000000FU
+#define DMAC_CH3_DST_MSIZE_M  (DMAC_CH3_DST_MSIZE_V << DMAC_CH3_DST_MSIZE_S)
+#define DMAC_CH3_DST_MSIZE_V  0x0000000FU
+#define DMAC_CH3_DST_MSIZE_S  18
+/** DMAC_CH3_AR_CACHE : R/W; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AR_CACHE    0x0000000FU
+#define DMAC_CH3_AR_CACHE_M  (DMAC_CH3_AR_CACHE_V << DMAC_CH3_AR_CACHE_S)
+#define DMAC_CH3_AR_CACHE_V  0x0000000FU
+#define DMAC_CH3_AR_CACHE_S  22
+/** DMAC_CH3_AW_CACHE : R/W; bitpos: [29:26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AW_CACHE    0x0000000FU
+#define DMAC_CH3_AW_CACHE_M  (DMAC_CH3_AW_CACHE_V << DMAC_CH3_AW_CACHE_S)
+#define DMAC_CH3_AW_CACHE_V  0x0000000FU
+#define DMAC_CH3_AW_CACHE_S  26
+/** DMAC_CH3_NONPOSTED_LASTWRITE_EN : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_NONPOSTED_LASTWRITE_EN    (BIT(30))
+#define DMAC_CH3_NONPOSTED_LASTWRITE_EN_M  (DMAC_CH3_NONPOSTED_LASTWRITE_EN_V << DMAC_CH3_NONPOSTED_LASTWRITE_EN_S)
+#define DMAC_CH3_NONPOSTED_LASTWRITE_EN_V  0x00000001U
+#define DMAC_CH3_NONPOSTED_LASTWRITE_EN_S  30
+
+/** DMAC_CH3_CTL1_REG register
+ *  NA
+ */
+#define DMAC_CH3_CTL1_REG (DR_REG_DMAC_BASE + 0x31c)
+/** DMAC_CH3_AR_PROT : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AR_PROT    0x00000007U
+#define DMAC_CH3_AR_PROT_M  (DMAC_CH3_AR_PROT_V << DMAC_CH3_AR_PROT_S)
+#define DMAC_CH3_AR_PROT_V  0x00000007U
+#define DMAC_CH3_AR_PROT_S  0
+/** DMAC_CH3_AW_PROT : R/W; bitpos: [5:3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AW_PROT    0x00000007U
+#define DMAC_CH3_AW_PROT_M  (DMAC_CH3_AW_PROT_V << DMAC_CH3_AW_PROT_S)
+#define DMAC_CH3_AW_PROT_V  0x00000007U
+#define DMAC_CH3_AW_PROT_S  3
+/** DMAC_CH3_ARLEN_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ARLEN_EN    (BIT(6))
+#define DMAC_CH3_ARLEN_EN_M  (DMAC_CH3_ARLEN_EN_V << DMAC_CH3_ARLEN_EN_S)
+#define DMAC_CH3_ARLEN_EN_V  0x00000001U
+#define DMAC_CH3_ARLEN_EN_S  6
+/** DMAC_CH3_ARLEN : R/W; bitpos: [14:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ARLEN    0x000000FFU
+#define DMAC_CH3_ARLEN_M  (DMAC_CH3_ARLEN_V << DMAC_CH3_ARLEN_S)
+#define DMAC_CH3_ARLEN_V  0x000000FFU
+#define DMAC_CH3_ARLEN_S  7
+/** DMAC_CH3_AWLEN_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AWLEN_EN    (BIT(15))
+#define DMAC_CH3_AWLEN_EN_M  (DMAC_CH3_AWLEN_EN_V << DMAC_CH3_AWLEN_EN_S)
+#define DMAC_CH3_AWLEN_EN_V  0x00000001U
+#define DMAC_CH3_AWLEN_EN_S  15
+/** DMAC_CH3_AWLEN : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AWLEN    0x000000FFU
+#define DMAC_CH3_AWLEN_M  (DMAC_CH3_AWLEN_V << DMAC_CH3_AWLEN_S)
+#define DMAC_CH3_AWLEN_V  0x000000FFU
+#define DMAC_CH3_AWLEN_S  16
+/** DMAC_CH3_SRC_STAT_EN : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_STAT_EN    (BIT(24))
+#define DMAC_CH3_SRC_STAT_EN_M  (DMAC_CH3_SRC_STAT_EN_V << DMAC_CH3_SRC_STAT_EN_S)
+#define DMAC_CH3_SRC_STAT_EN_V  0x00000001U
+#define DMAC_CH3_SRC_STAT_EN_S  24
+/** DMAC_CH3_DST_STAT_EN : R/W; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_STAT_EN    (BIT(25))
+#define DMAC_CH3_DST_STAT_EN_M  (DMAC_CH3_DST_STAT_EN_V << DMAC_CH3_DST_STAT_EN_S)
+#define DMAC_CH3_DST_STAT_EN_V  0x00000001U
+#define DMAC_CH3_DST_STAT_EN_S  25
+/** DMAC_CH3_IOC_BLKTFR : R/W; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_IOC_BLKTFR    (BIT(26))
+#define DMAC_CH3_IOC_BLKTFR_M  (DMAC_CH3_IOC_BLKTFR_V << DMAC_CH3_IOC_BLKTFR_S)
+#define DMAC_CH3_IOC_BLKTFR_V  0x00000001U
+#define DMAC_CH3_IOC_BLKTFR_S  26
+/** DMAC_CH3_SHADOWREG_OR_LLI_LAST : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SHADOWREG_OR_LLI_LAST    (BIT(30))
+#define DMAC_CH3_SHADOWREG_OR_LLI_LAST_M  (DMAC_CH3_SHADOWREG_OR_LLI_LAST_V << DMAC_CH3_SHADOWREG_OR_LLI_LAST_S)
+#define DMAC_CH3_SHADOWREG_OR_LLI_LAST_V  0x00000001U
+#define DMAC_CH3_SHADOWREG_OR_LLI_LAST_S  30
+/** DMAC_CH3_SHADOWREG_OR_LLI_VALID : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SHADOWREG_OR_LLI_VALID    (BIT(31))
+#define DMAC_CH3_SHADOWREG_OR_LLI_VALID_M  (DMAC_CH3_SHADOWREG_OR_LLI_VALID_V << DMAC_CH3_SHADOWREG_OR_LLI_VALID_S)
+#define DMAC_CH3_SHADOWREG_OR_LLI_VALID_V  0x00000001U
+#define DMAC_CH3_SHADOWREG_OR_LLI_VALID_S  31
+
+/** DMAC_CH3_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CH3_CFG0_REG (DR_REG_DMAC_BASE + 0x320)
+/** DMAC_CH3_SRC_MULTBLK_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH3_SRC_MULTBLK_TYPE_M  (DMAC_CH3_SRC_MULTBLK_TYPE_V << DMAC_CH3_SRC_MULTBLK_TYPE_S)
+#define DMAC_CH3_SRC_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH3_SRC_MULTBLK_TYPE_S  0
+/** DMAC_CH3_DST_MULTBLK_TYPE : R/W; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH3_DST_MULTBLK_TYPE_M  (DMAC_CH3_DST_MULTBLK_TYPE_V << DMAC_CH3_DST_MULTBLK_TYPE_S)
+#define DMAC_CH3_DST_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH3_DST_MULTBLK_TYPE_S  2
+/** DMAC_CH3_RD_UID : RO; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_RD_UID    0x0000000FU
+#define DMAC_CH3_RD_UID_M  (DMAC_CH3_RD_UID_V << DMAC_CH3_RD_UID_S)
+#define DMAC_CH3_RD_UID_V  0x0000000FU
+#define DMAC_CH3_RD_UID_S  18
+/** DMAC_CH3_WR_UID : RO; bitpos: [28:25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_WR_UID    0x0000000FU
+#define DMAC_CH3_WR_UID_M  (DMAC_CH3_WR_UID_V << DMAC_CH3_WR_UID_S)
+#define DMAC_CH3_WR_UID_V  0x0000000FU
+#define DMAC_CH3_WR_UID_S  25
+
+/** DMAC_CH3_CFG1_REG register
+ *  NA
+ */
+#define DMAC_CH3_CFG1_REG (DR_REG_DMAC_BASE + 0x324)
+/** DMAC_CH3_TT_FC : R/W; bitpos: [2:0]; default: 3;
+ *  NA
+ */
+#define DMAC_CH3_TT_FC    0x00000007U
+#define DMAC_CH3_TT_FC_M  (DMAC_CH3_TT_FC_V << DMAC_CH3_TT_FC_S)
+#define DMAC_CH3_TT_FC_V  0x00000007U
+#define DMAC_CH3_TT_FC_S  0
+/** DMAC_CH3_HS_SEL_SRC : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_HS_SEL_SRC    (BIT(3))
+#define DMAC_CH3_HS_SEL_SRC_M  (DMAC_CH3_HS_SEL_SRC_V << DMAC_CH3_HS_SEL_SRC_S)
+#define DMAC_CH3_HS_SEL_SRC_V  0x00000001U
+#define DMAC_CH3_HS_SEL_SRC_S  3
+/** DMAC_CH3_HS_SEL_DST : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_HS_SEL_DST    (BIT(4))
+#define DMAC_CH3_HS_SEL_DST_M  (DMAC_CH3_HS_SEL_DST_V << DMAC_CH3_HS_SEL_DST_S)
+#define DMAC_CH3_HS_SEL_DST_V  0x00000001U
+#define DMAC_CH3_HS_SEL_DST_S  4
+/** DMAC_CH3_SRC_HWHS_POL : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_HWHS_POL    (BIT(5))
+#define DMAC_CH3_SRC_HWHS_POL_M  (DMAC_CH3_SRC_HWHS_POL_V << DMAC_CH3_SRC_HWHS_POL_S)
+#define DMAC_CH3_SRC_HWHS_POL_V  0x00000001U
+#define DMAC_CH3_SRC_HWHS_POL_S  5
+/** DMAC_CH3_DST_HWHS_POL : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_HWHS_POL    (BIT(6))
+#define DMAC_CH3_DST_HWHS_POL_M  (DMAC_CH3_DST_HWHS_POL_V << DMAC_CH3_DST_HWHS_POL_S)
+#define DMAC_CH3_DST_HWHS_POL_V  0x00000001U
+#define DMAC_CH3_DST_HWHS_POL_S  6
+/** DMAC_CH3_SRC_PER : R/W; bitpos: [8:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_PER    0x00000003U
+#define DMAC_CH3_SRC_PER_M  (DMAC_CH3_SRC_PER_V << DMAC_CH3_SRC_PER_S)
+#define DMAC_CH3_SRC_PER_V  0x00000003U
+#define DMAC_CH3_SRC_PER_S  7
+/** DMAC_CH3_DST_PER : R/W; bitpos: [13:12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_PER    0x00000003U
+#define DMAC_CH3_DST_PER_M  (DMAC_CH3_DST_PER_V << DMAC_CH3_DST_PER_S)
+#define DMAC_CH3_DST_PER_V  0x00000003U
+#define DMAC_CH3_DST_PER_S  12
+/** DMAC_CH3_CH_PRIOR : R/W; bitpos: [19:17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_CH_PRIOR    0x00000007U
+#define DMAC_CH3_CH_PRIOR_M  (DMAC_CH3_CH_PRIOR_V << DMAC_CH3_CH_PRIOR_S)
+#define DMAC_CH3_CH_PRIOR_V  0x00000007U
+#define DMAC_CH3_CH_PRIOR_S  17
+/** DMAC_CH3_LOCK_CH : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LOCK_CH    (BIT(20))
+#define DMAC_CH3_LOCK_CH_M  (DMAC_CH3_LOCK_CH_V << DMAC_CH3_LOCK_CH_S)
+#define DMAC_CH3_LOCK_CH_V  0x00000001U
+#define DMAC_CH3_LOCK_CH_S  20
+/** DMAC_CH3_LOCK_CH_L : RO; bitpos: [22:21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LOCK_CH_L    0x00000003U
+#define DMAC_CH3_LOCK_CH_L_M  (DMAC_CH3_LOCK_CH_L_V << DMAC_CH3_LOCK_CH_L_S)
+#define DMAC_CH3_LOCK_CH_L_V  0x00000003U
+#define DMAC_CH3_LOCK_CH_L_S  21
+/** DMAC_CH3_SRC_OSR_LMT : R/W; bitpos: [26:23]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_OSR_LMT    0x0000000FU
+#define DMAC_CH3_SRC_OSR_LMT_M  (DMAC_CH3_SRC_OSR_LMT_V << DMAC_CH3_SRC_OSR_LMT_S)
+#define DMAC_CH3_SRC_OSR_LMT_V  0x0000000FU
+#define DMAC_CH3_SRC_OSR_LMT_S  23
+/** DMAC_CH3_DST_OSR_LMT : R/W; bitpos: [30:27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_OSR_LMT    0x0000000FU
+#define DMAC_CH3_DST_OSR_LMT_M  (DMAC_CH3_DST_OSR_LMT_V << DMAC_CH3_DST_OSR_LMT_S)
+#define DMAC_CH3_DST_OSR_LMT_V  0x0000000FU
+#define DMAC_CH3_DST_OSR_LMT_S  27
+
+/** DMAC_CH3_LLP0_REG register
+ *  NA
+ */
+#define DMAC_CH3_LLP0_REG (DR_REG_DMAC_BASE + 0x328)
+/** DMAC_CH3_LMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LMS    (BIT(0))
+#define DMAC_CH3_LMS_M  (DMAC_CH3_LMS_V << DMAC_CH3_LMS_S)
+#define DMAC_CH3_LMS_V  0x00000001U
+#define DMAC_CH3_LMS_S  0
+/** DMAC_CH3_LOC0 : R/W; bitpos: [31:6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LOC0    0x03FFFFFFU
+#define DMAC_CH3_LOC0_M  (DMAC_CH3_LOC0_V << DMAC_CH3_LOC0_S)
+#define DMAC_CH3_LOC0_V  0x03FFFFFFU
+#define DMAC_CH3_LOC0_S  6
+
+/** DMAC_CH3_LLP1_REG register
+ *  NA
+ */
+#define DMAC_CH3_LLP1_REG (DR_REG_DMAC_BASE + 0x32c)
+/** DMAC_CH3_LOC1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LOC1    0xFFFFFFFFU
+#define DMAC_CH3_LOC1_M  (DMAC_CH3_LOC1_V << DMAC_CH3_LOC1_S)
+#define DMAC_CH3_LOC1_V  0xFFFFFFFFU
+#define DMAC_CH3_LOC1_S  0
+
+/** DMAC_CH3_STATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH3_STATUS0_REG (DR_REG_DMAC_BASE + 0x330)
+/** DMAC_CH3_CMPLTD_BLK_TFR_SIZE : RO; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CMPLTD_BLK_TFR_SIZE    0x003FFFFFU
+#define DMAC_CH3_CMPLTD_BLK_TFR_SIZE_M  (DMAC_CH3_CMPLTD_BLK_TFR_SIZE_V << DMAC_CH3_CMPLTD_BLK_TFR_SIZE_S)
+#define DMAC_CH3_CMPLTD_BLK_TFR_SIZE_V  0x003FFFFFU
+#define DMAC_CH3_CMPLTD_BLK_TFR_SIZE_S  0
+
+/** DMAC_CH3_STATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH3_STATUS1_REG (DR_REG_DMAC_BASE + 0x334)
+/** DMAC_CH3_DATA_LEFT_IN_FIFO : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DATA_LEFT_IN_FIFO    0x00007FFFU
+#define DMAC_CH3_DATA_LEFT_IN_FIFO_M  (DMAC_CH3_DATA_LEFT_IN_FIFO_V << DMAC_CH3_DATA_LEFT_IN_FIFO_S)
+#define DMAC_CH3_DATA_LEFT_IN_FIFO_V  0x00007FFFU
+#define DMAC_CH3_DATA_LEFT_IN_FIFO_S  0
+
+/** DMAC_CH3_SWHSSRC0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SWHSSRC0_REG (DR_REG_DMAC_BASE + 0x338)
+/** DMAC_CH3_SWHS_REQ_SRC : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_REQ_SRC    (BIT(0))
+#define DMAC_CH3_SWHS_REQ_SRC_M  (DMAC_CH3_SWHS_REQ_SRC_V << DMAC_CH3_SWHS_REQ_SRC_S)
+#define DMAC_CH3_SWHS_REQ_SRC_V  0x00000001U
+#define DMAC_CH3_SWHS_REQ_SRC_S  0
+/** DMAC_CH3_SWHS_REQ_SRC_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_REQ_SRC_WE    (BIT(1))
+#define DMAC_CH3_SWHS_REQ_SRC_WE_M  (DMAC_CH3_SWHS_REQ_SRC_WE_V << DMAC_CH3_SWHS_REQ_SRC_WE_S)
+#define DMAC_CH3_SWHS_REQ_SRC_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_REQ_SRC_WE_S  1
+/** DMAC_CH3_SWHS_SGLREQ_SRC : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_SGLREQ_SRC    (BIT(2))
+#define DMAC_CH3_SWHS_SGLREQ_SRC_M  (DMAC_CH3_SWHS_SGLREQ_SRC_V << DMAC_CH3_SWHS_SGLREQ_SRC_S)
+#define DMAC_CH3_SWHS_SGLREQ_SRC_V  0x00000001U
+#define DMAC_CH3_SWHS_SGLREQ_SRC_S  2
+/** DMAC_CH3_SWHS_SGLREQ_SRC_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_SGLREQ_SRC_WE    (BIT(3))
+#define DMAC_CH3_SWHS_SGLREQ_SRC_WE_M  (DMAC_CH3_SWHS_SGLREQ_SRC_WE_V << DMAC_CH3_SWHS_SGLREQ_SRC_WE_S)
+#define DMAC_CH3_SWHS_SGLREQ_SRC_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_SGLREQ_SRC_WE_S  3
+/** DMAC_CH3_SWHS_LST_SRC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_LST_SRC    (BIT(4))
+#define DMAC_CH3_SWHS_LST_SRC_M  (DMAC_CH3_SWHS_LST_SRC_V << DMAC_CH3_SWHS_LST_SRC_S)
+#define DMAC_CH3_SWHS_LST_SRC_V  0x00000001U
+#define DMAC_CH3_SWHS_LST_SRC_S  4
+/** DMAC_CH3_SWHS_LST_SRC_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_LST_SRC_WE    (BIT(5))
+#define DMAC_CH3_SWHS_LST_SRC_WE_M  (DMAC_CH3_SWHS_LST_SRC_WE_V << DMAC_CH3_SWHS_LST_SRC_WE_S)
+#define DMAC_CH3_SWHS_LST_SRC_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_LST_SRC_WE_S  5
+
+/** DMAC_CH3_SWHSDST0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SWHSDST0_REG (DR_REG_DMAC_BASE + 0x340)
+/** DMAC_CH3_SWHS_REQ_DST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_REQ_DST    (BIT(0))
+#define DMAC_CH3_SWHS_REQ_DST_M  (DMAC_CH3_SWHS_REQ_DST_V << DMAC_CH3_SWHS_REQ_DST_S)
+#define DMAC_CH3_SWHS_REQ_DST_V  0x00000001U
+#define DMAC_CH3_SWHS_REQ_DST_S  0
+/** DMAC_CH3_SWHS_REQ_DST_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_REQ_DST_WE    (BIT(1))
+#define DMAC_CH3_SWHS_REQ_DST_WE_M  (DMAC_CH3_SWHS_REQ_DST_WE_V << DMAC_CH3_SWHS_REQ_DST_WE_S)
+#define DMAC_CH3_SWHS_REQ_DST_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_REQ_DST_WE_S  1
+/** DMAC_CH3_SWHS_SGLREQ_DST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_SGLREQ_DST    (BIT(2))
+#define DMAC_CH3_SWHS_SGLREQ_DST_M  (DMAC_CH3_SWHS_SGLREQ_DST_V << DMAC_CH3_SWHS_SGLREQ_DST_S)
+#define DMAC_CH3_SWHS_SGLREQ_DST_V  0x00000001U
+#define DMAC_CH3_SWHS_SGLREQ_DST_S  2
+/** DMAC_CH3_SWHS_SGLREQ_DST_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_SGLREQ_DST_WE    (BIT(3))
+#define DMAC_CH3_SWHS_SGLREQ_DST_WE_M  (DMAC_CH3_SWHS_SGLREQ_DST_WE_V << DMAC_CH3_SWHS_SGLREQ_DST_WE_S)
+#define DMAC_CH3_SWHS_SGLREQ_DST_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_SGLREQ_DST_WE_S  3
+/** DMAC_CH3_SWHS_LST_DST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_LST_DST    (BIT(4))
+#define DMAC_CH3_SWHS_LST_DST_M  (DMAC_CH3_SWHS_LST_DST_V << DMAC_CH3_SWHS_LST_DST_S)
+#define DMAC_CH3_SWHS_LST_DST_V  0x00000001U
+#define DMAC_CH3_SWHS_LST_DST_S  4
+/** DMAC_CH3_SWHS_LST_DST_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SWHS_LST_DST_WE    (BIT(5))
+#define DMAC_CH3_SWHS_LST_DST_WE_M  (DMAC_CH3_SWHS_LST_DST_WE_V << DMAC_CH3_SWHS_LST_DST_WE_S)
+#define DMAC_CH3_SWHS_LST_DST_WE_V  0x00000001U
+#define DMAC_CH3_SWHS_LST_DST_WE_S  5
+
+/** DMAC_CH3_BLK_TFR_RESUMEREQ0_REG register
+ *  NA
+ */
+#define DMAC_CH3_BLK_TFR_RESUMEREQ0_REG (DR_REG_DMAC_BASE + 0x348)
+/** DMAC_CH3_BLK_TFR_RESUMEREQ : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_BLK_TFR_RESUMEREQ    (BIT(0))
+#define DMAC_CH3_BLK_TFR_RESUMEREQ_M  (DMAC_CH3_BLK_TFR_RESUMEREQ_V << DMAC_CH3_BLK_TFR_RESUMEREQ_S)
+#define DMAC_CH3_BLK_TFR_RESUMEREQ_V  0x00000001U
+#define DMAC_CH3_BLK_TFR_RESUMEREQ_S  0
+
+/** DMAC_CH3_AXI_ID0_REG register
+ *  NA
+ */
+#define DMAC_CH3_AXI_ID0_REG (DR_REG_DMAC_BASE + 0x350)
+/** DMAC_CH3_AXI_READ_ID_SUFFIX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AXI_READ_ID_SUFFIX    (BIT(0))
+#define DMAC_CH3_AXI_READ_ID_SUFFIX_M  (DMAC_CH3_AXI_READ_ID_SUFFIX_V << DMAC_CH3_AXI_READ_ID_SUFFIX_S)
+#define DMAC_CH3_AXI_READ_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH3_AXI_READ_ID_SUFFIX_S  0
+/** DMAC_CH3_AXI_WRITE_ID_SUFFIX : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AXI_WRITE_ID_SUFFIX    (BIT(16))
+#define DMAC_CH3_AXI_WRITE_ID_SUFFIX_M  (DMAC_CH3_AXI_WRITE_ID_SUFFIX_V << DMAC_CH3_AXI_WRITE_ID_SUFFIX_S)
+#define DMAC_CH3_AXI_WRITE_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH3_AXI_WRITE_ID_SUFFIX_S  16
+
+/** DMAC_CH3_AXI_QOS0_REG register
+ *  NA
+ */
+#define DMAC_CH3_AXI_QOS0_REG (DR_REG_DMAC_BASE + 0x358)
+/** DMAC_CH3_AXI_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AXI_AWQOS    0x0000000FU
+#define DMAC_CH3_AXI_AWQOS_M  (DMAC_CH3_AXI_AWQOS_V << DMAC_CH3_AXI_AWQOS_S)
+#define DMAC_CH3_AXI_AWQOS_V  0x0000000FU
+#define DMAC_CH3_AXI_AWQOS_S  0
+/** DMAC_CH3_AXI_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_AXI_ARQOS    0x0000000FU
+#define DMAC_CH3_AXI_ARQOS_M  (DMAC_CH3_AXI_ARQOS_V << DMAC_CH3_AXI_ARQOS_S)
+#define DMAC_CH3_AXI_ARQOS_V  0x0000000FU
+#define DMAC_CH3_AXI_ARQOS_S  4
+
+/** DMAC_CH3_SSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SSTAT0_REG (DR_REG_DMAC_BASE + 0x360)
+/** DMAC_CH3_SSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SSTAT    0xFFFFFFFFU
+#define DMAC_CH3_SSTAT_M  (DMAC_CH3_SSTAT_V << DMAC_CH3_SSTAT_S)
+#define DMAC_CH3_SSTAT_V  0xFFFFFFFFU
+#define DMAC_CH3_SSTAT_S  0
+
+/** DMAC_CH3_DSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH3_DSTAT0_REG (DR_REG_DMAC_BASE + 0x368)
+/** DMAC_CH3_DSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DSTAT    0xFFFFFFFFU
+#define DMAC_CH3_DSTAT_M  (DMAC_CH3_DSTAT_V << DMAC_CH3_DSTAT_S)
+#define DMAC_CH3_DSTAT_V  0xFFFFFFFFU
+#define DMAC_CH3_DSTAT_S  0
+
+/** DMAC_CH3_SSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_SSTATAR0_REG (DR_REG_DMAC_BASE + 0x370)
+/** DMAC_CH3_SSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SSTATAR0    0xFFFFFFFFU
+#define DMAC_CH3_SSTATAR0_M  (DMAC_CH3_SSTATAR0_V << DMAC_CH3_SSTATAR0_S)
+#define DMAC_CH3_SSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH3_SSTATAR0_S  0
+
+/** DMAC_CH3_SSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_SSTATAR1_REG (DR_REG_DMAC_BASE + 0x374)
+/** DMAC_CH3_SSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SSTATAR1    0xFFFFFFFFU
+#define DMAC_CH3_SSTATAR1_M  (DMAC_CH3_SSTATAR1_V << DMAC_CH3_SSTATAR1_S)
+#define DMAC_CH3_SSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH3_SSTATAR1_S  0
+
+/** DMAC_CH3_DSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_DSTATAR0_REG (DR_REG_DMAC_BASE + 0x378)
+/** DMAC_CH3_DSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DSTATAR0    0xFFFFFFFFU
+#define DMAC_CH3_DSTATAR0_M  (DMAC_CH3_DSTATAR0_V << DMAC_CH3_DSTATAR0_S)
+#define DMAC_CH3_DSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH3_DSTATAR0_S  0
+
+/** DMAC_CH3_DSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_DSTATAR1_REG (DR_REG_DMAC_BASE + 0x37c)
+/** DMAC_CH3_DSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DSTATAR1    0xFFFFFFFFU
+#define DMAC_CH3_DSTATAR1_M  (DMAC_CH3_DSTATAR1_V << DMAC_CH3_DSTATAR1_S)
+#define DMAC_CH3_DSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH3_DSTATAR1_S  0
+
+/** DMAC_CH3_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x380)
+/** DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_V << DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_V << DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_V << DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : R/W; bitpos: [13]; default:
+ *  1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_V << DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_V << DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_M  (DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_V << DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH3_INTSTATUS_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSTATUS_ENABLE1_REG (DR_REG_DMAC_BASE + 0x384)
+/** DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH3_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x388)
+/** DMAC_CH3_BLOCK_TFR_DONE_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH3_DMA_TFR_DONE_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH3_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH3_DMA_TFR_DONE_INTSTAT_V << DMAC_CH3_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH3_SRC_TRANSCOMP_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH3_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH3_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH3_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH3_DST_TRANSCOMP_INTSTAT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH3_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH3_DST_TRANSCOMP_INTSTAT_V << DMAC_CH3_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH3_SRC_DEC_ERR_INTSTAT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH3_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH3_SRC_DEC_ERR_INTSTAT_V << DMAC_CH3_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH3_DST_DEC_ERR_INTSTAT : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH3_DST_DEC_ERR_INTSTAT_M  (DMAC_CH3_DST_DEC_ERR_INTSTAT_V << DMAC_CH3_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH3_SRC_SLV_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH3_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH3_SRC_SLV_ERR_INTSTAT_V << DMAC_CH3_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH3_DST_SLV_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH3_DST_SLV_ERR_INTSTAT_M  (DMAC_CH3_DST_SLV_ERR_INTSTAT_V << DMAC_CH3_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH3_SLVIF_DEC_ERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH3_CH_LOCK_CLEARED_INTSTAT : RO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH3_CH_SUSPENDED_INTSTAT : RO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH3_CH_SUSPENDED_INTSTAT_M  (DMAC_CH3_CH_SUSPENDED_INTSTAT_V << DMAC_CH3_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH3_CH_DISABLED_INTSTAT : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH3_CH_DISABLED_INTSTAT_M  (DMAC_CH3_CH_DISABLED_INTSTAT_V << DMAC_CH3_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH3_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH3_CH_ABORTED_INTSTAT : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH3_CH_ABORTED_INTSTAT_M  (DMAC_CH3_CH_ABORTED_INTSTAT_V << DMAC_CH3_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH3_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH3_INTSTATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSTATUS1_REG (DR_REG_DMAC_BASE + 0x38c)
+/** DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH3_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x390)
+/** DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL    (BIT(0))
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_M  (DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V << DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S  0
+/** DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL    (BIT(1))
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_M  (DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_V << DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_DMA_TFR_DONE_INTSIGNAL_S  1
+/** DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL    (BIT(3))
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_M  (DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V << DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S  3
+/** DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL    (BIT(4))
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_M  (DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_V << DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_TRANSCOMP_INTSIGNAL_S  4
+/** DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL    (BIT(5))
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_DEC_ERR_INTSIGNAL_S  5
+/** DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL    (BIT(6))
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_DEC_ERR_INTSIGNAL_S  6
+/** DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SRC_SLV_ERR_INTSIGNAL_S  7
+/** DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_DST_SLV_ERR_INTSIGNAL_S  8
+/** DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL    (BIT(9))
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S  9
+/** DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL    (BIT(10))
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S  10
+/** DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL    (BIT(11))
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S  11
+/** DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL    (BIT(12))
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S  12
+/** DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL : R/W; bitpos: [13];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL    (BIT(13))
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S  13
+/** DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL    (BIT(14))
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S  14
+/** DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL    (BIT(16))
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S  16
+/** DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL    (BIT(17))
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S  17
+/** DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL    (BIT(18))
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S  18
+/** DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL    (BIT(19))
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S  19
+/** DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL    (BIT(20))
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S  20
+/** DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL    (BIT(21))
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S  21
+/** DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL    (BIT(25))
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V << DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S  25
+/** DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL    (BIT(27))
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S  27
+/** DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL    (BIT(28))
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S  28
+/** DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL    (BIT(29))
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_SUSPENDED_INTSIGNAL_S  29
+/** DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL    (BIT(30))
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_DISABLED_INTSIGNAL_S  30
+/** DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL    (BIT(31))
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_M  (DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_V << DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_CH_ABORTED_INTSIGNAL_S  31
+
+/** DMAC_CH3_INTSIGNAL_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTSIGNAL_ENABLE1_REG (DR_REG_DMAC_BASE + 0x394)
+/** DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL    (BIT(0))
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V << DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S  0
+/** DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL    (BIT(1))
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S  1
+/** DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL    (BIT(2))
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V << DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S  2
+/** DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL    (BIT(3))
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH3_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S  3
+
+/** DMAC_CH3_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x398)
+/** DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_V << DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT : WO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_V << DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT : WO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_V << DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : WO; bitpos: [20]; default:
+ *  0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT : WO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT : WO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT : WO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_V << DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT : WO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_V << DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT : WO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_M  (DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_V << DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH3_INTCLEAR1_REG register
+ *  NA
+ */
+#define DMAC_CH3_INTCLEAR1_REG (DR_REG_DMAC_BASE + 0x39c)
+/** DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH3_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH4_SAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SAR0_REG (DR_REG_DMAC_BASE + 0x400)
+/** DMAC_CH4_SAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SAR0    0xFFFFFFFFU
+#define DMAC_CH4_SAR0_M  (DMAC_CH4_SAR0_V << DMAC_CH4_SAR0_S)
+#define DMAC_CH4_SAR0_V  0xFFFFFFFFU
+#define DMAC_CH4_SAR0_S  0
+
+/** DMAC_CH4_SAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_SAR1_REG (DR_REG_DMAC_BASE + 0x404)
+/** DMAC_CH4_SAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SAR1    0xFFFFFFFFU
+#define DMAC_CH4_SAR1_M  (DMAC_CH4_SAR1_V << DMAC_CH4_SAR1_S)
+#define DMAC_CH4_SAR1_V  0xFFFFFFFFU
+#define DMAC_CH4_SAR1_S  0
+
+/** DMAC_CH4_DAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_DAR0_REG (DR_REG_DMAC_BASE + 0x408)
+/** DMAC_CH4_DAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DAR0    0xFFFFFFFFU
+#define DMAC_CH4_DAR0_M  (DMAC_CH4_DAR0_V << DMAC_CH4_DAR0_S)
+#define DMAC_CH4_DAR0_V  0xFFFFFFFFU
+#define DMAC_CH4_DAR0_S  0
+
+/** DMAC_CH4_DAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_DAR1_REG (DR_REG_DMAC_BASE + 0x40c)
+/** DMAC_CH4_DAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DAR1    0xFFFFFFFFU
+#define DMAC_CH4_DAR1_M  (DMAC_CH4_DAR1_V << DMAC_CH4_DAR1_S)
+#define DMAC_CH4_DAR1_V  0xFFFFFFFFU
+#define DMAC_CH4_DAR1_S  0
+
+/** DMAC_CH4_BLOCK_TS0_REG register
+ *  NA
+ */
+#define DMAC_CH4_BLOCK_TS0_REG (DR_REG_DMAC_BASE + 0x410)
+/** DMAC_CH4_BLOCK_TS : R/W; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_BLOCK_TS    0x003FFFFFU
+#define DMAC_CH4_BLOCK_TS_M  (DMAC_CH4_BLOCK_TS_V << DMAC_CH4_BLOCK_TS_S)
+#define DMAC_CH4_BLOCK_TS_V  0x003FFFFFU
+#define DMAC_CH4_BLOCK_TS_S  0
+
+/** DMAC_CH4_CTL0_REG register
+ *  NA
+ */
+#define DMAC_CH4_CTL0_REG (DR_REG_DMAC_BASE + 0x418)
+/** DMAC_CH4_SMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SMS    (BIT(0))
+#define DMAC_CH4_SMS_M  (DMAC_CH4_SMS_V << DMAC_CH4_SMS_S)
+#define DMAC_CH4_SMS_V  0x00000001U
+#define DMAC_CH4_SMS_S  0
+/** DMAC_CH4_DMS : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DMS    (BIT(2))
+#define DMAC_CH4_DMS_M  (DMAC_CH4_DMS_V << DMAC_CH4_DMS_S)
+#define DMAC_CH4_DMS_V  0x00000001U
+#define DMAC_CH4_DMS_S  2
+/** DMAC_CH4_SINC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SINC    (BIT(4))
+#define DMAC_CH4_SINC_M  (DMAC_CH4_SINC_V << DMAC_CH4_SINC_S)
+#define DMAC_CH4_SINC_V  0x00000001U
+#define DMAC_CH4_SINC_S  4
+/** DMAC_CH4_DINC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DINC    (BIT(6))
+#define DMAC_CH4_DINC_M  (DMAC_CH4_DINC_V << DMAC_CH4_DINC_S)
+#define DMAC_CH4_DINC_V  0x00000001U
+#define DMAC_CH4_DINC_S  6
+/** DMAC_CH4_SRC_TR_WIDTH : R/W; bitpos: [10:8]; default: 2;
+ *  NA
+ */
+#define DMAC_CH4_SRC_TR_WIDTH    0x00000007U
+#define DMAC_CH4_SRC_TR_WIDTH_M  (DMAC_CH4_SRC_TR_WIDTH_V << DMAC_CH4_SRC_TR_WIDTH_S)
+#define DMAC_CH4_SRC_TR_WIDTH_V  0x00000007U
+#define DMAC_CH4_SRC_TR_WIDTH_S  8
+/** DMAC_CH4_DST_TR_WIDTH : R/W; bitpos: [13:11]; default: 2;
+ *  NA
+ */
+#define DMAC_CH4_DST_TR_WIDTH    0x00000007U
+#define DMAC_CH4_DST_TR_WIDTH_M  (DMAC_CH4_DST_TR_WIDTH_V << DMAC_CH4_DST_TR_WIDTH_S)
+#define DMAC_CH4_DST_TR_WIDTH_V  0x00000007U
+#define DMAC_CH4_DST_TR_WIDTH_S  11
+/** DMAC_CH4_SRC_MSIZE : R/W; bitpos: [17:14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_MSIZE    0x0000000FU
+#define DMAC_CH4_SRC_MSIZE_M  (DMAC_CH4_SRC_MSIZE_V << DMAC_CH4_SRC_MSIZE_S)
+#define DMAC_CH4_SRC_MSIZE_V  0x0000000FU
+#define DMAC_CH4_SRC_MSIZE_S  14
+/** DMAC_CH4_DST_MSIZE : R/W; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_MSIZE    0x0000000FU
+#define DMAC_CH4_DST_MSIZE_M  (DMAC_CH4_DST_MSIZE_V << DMAC_CH4_DST_MSIZE_S)
+#define DMAC_CH4_DST_MSIZE_V  0x0000000FU
+#define DMAC_CH4_DST_MSIZE_S  18
+/** DMAC_CH4_AR_CACHE : R/W; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AR_CACHE    0x0000000FU
+#define DMAC_CH4_AR_CACHE_M  (DMAC_CH4_AR_CACHE_V << DMAC_CH4_AR_CACHE_S)
+#define DMAC_CH4_AR_CACHE_V  0x0000000FU
+#define DMAC_CH4_AR_CACHE_S  22
+/** DMAC_CH4_AW_CACHE : R/W; bitpos: [29:26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AW_CACHE    0x0000000FU
+#define DMAC_CH4_AW_CACHE_M  (DMAC_CH4_AW_CACHE_V << DMAC_CH4_AW_CACHE_S)
+#define DMAC_CH4_AW_CACHE_V  0x0000000FU
+#define DMAC_CH4_AW_CACHE_S  26
+/** DMAC_CH4_NONPOSTED_LASTWRITE_EN : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_NONPOSTED_LASTWRITE_EN    (BIT(30))
+#define DMAC_CH4_NONPOSTED_LASTWRITE_EN_M  (DMAC_CH4_NONPOSTED_LASTWRITE_EN_V << DMAC_CH4_NONPOSTED_LASTWRITE_EN_S)
+#define DMAC_CH4_NONPOSTED_LASTWRITE_EN_V  0x00000001U
+#define DMAC_CH4_NONPOSTED_LASTWRITE_EN_S  30
+
+/** DMAC_CH4_CTL1_REG register
+ *  NA
+ */
+#define DMAC_CH4_CTL1_REG (DR_REG_DMAC_BASE + 0x41c)
+/** DMAC_CH4_AR_PROT : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AR_PROT    0x00000007U
+#define DMAC_CH4_AR_PROT_M  (DMAC_CH4_AR_PROT_V << DMAC_CH4_AR_PROT_S)
+#define DMAC_CH4_AR_PROT_V  0x00000007U
+#define DMAC_CH4_AR_PROT_S  0
+/** DMAC_CH4_AW_PROT : R/W; bitpos: [5:3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AW_PROT    0x00000007U
+#define DMAC_CH4_AW_PROT_M  (DMAC_CH4_AW_PROT_V << DMAC_CH4_AW_PROT_S)
+#define DMAC_CH4_AW_PROT_V  0x00000007U
+#define DMAC_CH4_AW_PROT_S  3
+/** DMAC_CH4_ARLEN_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ARLEN_EN    (BIT(6))
+#define DMAC_CH4_ARLEN_EN_M  (DMAC_CH4_ARLEN_EN_V << DMAC_CH4_ARLEN_EN_S)
+#define DMAC_CH4_ARLEN_EN_V  0x00000001U
+#define DMAC_CH4_ARLEN_EN_S  6
+/** DMAC_CH4_ARLEN : R/W; bitpos: [14:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ARLEN    0x000000FFU
+#define DMAC_CH4_ARLEN_M  (DMAC_CH4_ARLEN_V << DMAC_CH4_ARLEN_S)
+#define DMAC_CH4_ARLEN_V  0x000000FFU
+#define DMAC_CH4_ARLEN_S  7
+/** DMAC_CH4_AWLEN_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AWLEN_EN    (BIT(15))
+#define DMAC_CH4_AWLEN_EN_M  (DMAC_CH4_AWLEN_EN_V << DMAC_CH4_AWLEN_EN_S)
+#define DMAC_CH4_AWLEN_EN_V  0x00000001U
+#define DMAC_CH4_AWLEN_EN_S  15
+/** DMAC_CH4_AWLEN : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AWLEN    0x000000FFU
+#define DMAC_CH4_AWLEN_M  (DMAC_CH4_AWLEN_V << DMAC_CH4_AWLEN_S)
+#define DMAC_CH4_AWLEN_V  0x000000FFU
+#define DMAC_CH4_AWLEN_S  16
+/** DMAC_CH4_SRC_STAT_EN : R/W; bitpos: [24]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_STAT_EN    (BIT(24))
+#define DMAC_CH4_SRC_STAT_EN_M  (DMAC_CH4_SRC_STAT_EN_V << DMAC_CH4_SRC_STAT_EN_S)
+#define DMAC_CH4_SRC_STAT_EN_V  0x00000001U
+#define DMAC_CH4_SRC_STAT_EN_S  24
+/** DMAC_CH4_DST_STAT_EN : R/W; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_STAT_EN    (BIT(25))
+#define DMAC_CH4_DST_STAT_EN_M  (DMAC_CH4_DST_STAT_EN_V << DMAC_CH4_DST_STAT_EN_S)
+#define DMAC_CH4_DST_STAT_EN_V  0x00000001U
+#define DMAC_CH4_DST_STAT_EN_S  25
+/** DMAC_CH4_IOC_BLKTFR : R/W; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_IOC_BLKTFR    (BIT(26))
+#define DMAC_CH4_IOC_BLKTFR_M  (DMAC_CH4_IOC_BLKTFR_V << DMAC_CH4_IOC_BLKTFR_S)
+#define DMAC_CH4_IOC_BLKTFR_V  0x00000001U
+#define DMAC_CH4_IOC_BLKTFR_S  26
+/** DMAC_CH4_SHADOWREG_OR_LLI_LAST : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SHADOWREG_OR_LLI_LAST    (BIT(30))
+#define DMAC_CH4_SHADOWREG_OR_LLI_LAST_M  (DMAC_CH4_SHADOWREG_OR_LLI_LAST_V << DMAC_CH4_SHADOWREG_OR_LLI_LAST_S)
+#define DMAC_CH4_SHADOWREG_OR_LLI_LAST_V  0x00000001U
+#define DMAC_CH4_SHADOWREG_OR_LLI_LAST_S  30
+/** DMAC_CH4_SHADOWREG_OR_LLI_VALID : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SHADOWREG_OR_LLI_VALID    (BIT(31))
+#define DMAC_CH4_SHADOWREG_OR_LLI_VALID_M  (DMAC_CH4_SHADOWREG_OR_LLI_VALID_V << DMAC_CH4_SHADOWREG_OR_LLI_VALID_S)
+#define DMAC_CH4_SHADOWREG_OR_LLI_VALID_V  0x00000001U
+#define DMAC_CH4_SHADOWREG_OR_LLI_VALID_S  31
+
+/** DMAC_CH4_CFG0_REG register
+ *  NA
+ */
+#define DMAC_CH4_CFG0_REG (DR_REG_DMAC_BASE + 0x420)
+/** DMAC_CH4_SRC_MULTBLK_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH4_SRC_MULTBLK_TYPE_M  (DMAC_CH4_SRC_MULTBLK_TYPE_V << DMAC_CH4_SRC_MULTBLK_TYPE_S)
+#define DMAC_CH4_SRC_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH4_SRC_MULTBLK_TYPE_S  0
+/** DMAC_CH4_DST_MULTBLK_TYPE : R/W; bitpos: [3:2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_MULTBLK_TYPE    0x00000003U
+#define DMAC_CH4_DST_MULTBLK_TYPE_M  (DMAC_CH4_DST_MULTBLK_TYPE_V << DMAC_CH4_DST_MULTBLK_TYPE_S)
+#define DMAC_CH4_DST_MULTBLK_TYPE_V  0x00000003U
+#define DMAC_CH4_DST_MULTBLK_TYPE_S  2
+/** DMAC_CH4_RD_UID : RO; bitpos: [21:18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_RD_UID    0x0000000FU
+#define DMAC_CH4_RD_UID_M  (DMAC_CH4_RD_UID_V << DMAC_CH4_RD_UID_S)
+#define DMAC_CH4_RD_UID_V  0x0000000FU
+#define DMAC_CH4_RD_UID_S  18
+/** DMAC_CH4_WR_UID : RO; bitpos: [28:25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_WR_UID    0x0000000FU
+#define DMAC_CH4_WR_UID_M  (DMAC_CH4_WR_UID_V << DMAC_CH4_WR_UID_S)
+#define DMAC_CH4_WR_UID_V  0x0000000FU
+#define DMAC_CH4_WR_UID_S  25
+
+/** DMAC_CH4_CFG1_REG register
+ *  NA
+ */
+#define DMAC_CH4_CFG1_REG (DR_REG_DMAC_BASE + 0x424)
+/** DMAC_CH4_TT_FC : R/W; bitpos: [2:0]; default: 3;
+ *  NA
+ */
+#define DMAC_CH4_TT_FC    0x00000007U
+#define DMAC_CH4_TT_FC_M  (DMAC_CH4_TT_FC_V << DMAC_CH4_TT_FC_S)
+#define DMAC_CH4_TT_FC_V  0x00000007U
+#define DMAC_CH4_TT_FC_S  0
+/** DMAC_CH4_HS_SEL_SRC : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_HS_SEL_SRC    (BIT(3))
+#define DMAC_CH4_HS_SEL_SRC_M  (DMAC_CH4_HS_SEL_SRC_V << DMAC_CH4_HS_SEL_SRC_S)
+#define DMAC_CH4_HS_SEL_SRC_V  0x00000001U
+#define DMAC_CH4_HS_SEL_SRC_S  3
+/** DMAC_CH4_HS_SEL_DST : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_HS_SEL_DST    (BIT(4))
+#define DMAC_CH4_HS_SEL_DST_M  (DMAC_CH4_HS_SEL_DST_V << DMAC_CH4_HS_SEL_DST_S)
+#define DMAC_CH4_HS_SEL_DST_V  0x00000001U
+#define DMAC_CH4_HS_SEL_DST_S  4
+/** DMAC_CH4_SRC_HWHS_POL : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_HWHS_POL    (BIT(5))
+#define DMAC_CH4_SRC_HWHS_POL_M  (DMAC_CH4_SRC_HWHS_POL_V << DMAC_CH4_SRC_HWHS_POL_S)
+#define DMAC_CH4_SRC_HWHS_POL_V  0x00000001U
+#define DMAC_CH4_SRC_HWHS_POL_S  5
+/** DMAC_CH4_DST_HWHS_POL : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_HWHS_POL    (BIT(6))
+#define DMAC_CH4_DST_HWHS_POL_M  (DMAC_CH4_DST_HWHS_POL_V << DMAC_CH4_DST_HWHS_POL_S)
+#define DMAC_CH4_DST_HWHS_POL_V  0x00000001U
+#define DMAC_CH4_DST_HWHS_POL_S  6
+/** DMAC_CH4_SRC_PER : R/W; bitpos: [8:7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_PER    0x00000003U
+#define DMAC_CH4_SRC_PER_M  (DMAC_CH4_SRC_PER_V << DMAC_CH4_SRC_PER_S)
+#define DMAC_CH4_SRC_PER_V  0x00000003U
+#define DMAC_CH4_SRC_PER_S  7
+/** DMAC_CH4_DST_PER : R/W; bitpos: [13:12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_PER    0x00000003U
+#define DMAC_CH4_DST_PER_M  (DMAC_CH4_DST_PER_V << DMAC_CH4_DST_PER_S)
+#define DMAC_CH4_DST_PER_V  0x00000003U
+#define DMAC_CH4_DST_PER_S  12
+/** DMAC_CH4_CH_PRIOR : R/W; bitpos: [19:17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_PRIOR    0x00000007U
+#define DMAC_CH4_CH_PRIOR_M  (DMAC_CH4_CH_PRIOR_V << DMAC_CH4_CH_PRIOR_S)
+#define DMAC_CH4_CH_PRIOR_V  0x00000007U
+#define DMAC_CH4_CH_PRIOR_S  17
+/** DMAC_CH4_LOCK_CH : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LOCK_CH    (BIT(20))
+#define DMAC_CH4_LOCK_CH_M  (DMAC_CH4_LOCK_CH_V << DMAC_CH4_LOCK_CH_S)
+#define DMAC_CH4_LOCK_CH_V  0x00000001U
+#define DMAC_CH4_LOCK_CH_S  20
+/** DMAC_CH4_LOCK_CH_L : RO; bitpos: [22:21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LOCK_CH_L    0x00000003U
+#define DMAC_CH4_LOCK_CH_L_M  (DMAC_CH4_LOCK_CH_L_V << DMAC_CH4_LOCK_CH_L_S)
+#define DMAC_CH4_LOCK_CH_L_V  0x00000003U
+#define DMAC_CH4_LOCK_CH_L_S  21
+/** DMAC_CH4_SRC_OSR_LMT : R/W; bitpos: [26:23]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_OSR_LMT    0x0000000FU
+#define DMAC_CH4_SRC_OSR_LMT_M  (DMAC_CH4_SRC_OSR_LMT_V << DMAC_CH4_SRC_OSR_LMT_S)
+#define DMAC_CH4_SRC_OSR_LMT_V  0x0000000FU
+#define DMAC_CH4_SRC_OSR_LMT_S  23
+/** DMAC_CH4_DST_OSR_LMT : R/W; bitpos: [30:27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_OSR_LMT    0x0000000FU
+#define DMAC_CH4_DST_OSR_LMT_M  (DMAC_CH4_DST_OSR_LMT_V << DMAC_CH4_DST_OSR_LMT_S)
+#define DMAC_CH4_DST_OSR_LMT_V  0x0000000FU
+#define DMAC_CH4_DST_OSR_LMT_S  27
+
+/** DMAC_CH4_LLP0_REG register
+ *  NA
+ */
+#define DMAC_CH4_LLP0_REG (DR_REG_DMAC_BASE + 0x428)
+/** DMAC_CH4_LMS : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LMS    (BIT(0))
+#define DMAC_CH4_LMS_M  (DMAC_CH4_LMS_V << DMAC_CH4_LMS_S)
+#define DMAC_CH4_LMS_V  0x00000001U
+#define DMAC_CH4_LMS_S  0
+/** DMAC_CH4_LOC0 : R/W; bitpos: [31:6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LOC0    0x03FFFFFFU
+#define DMAC_CH4_LOC0_M  (DMAC_CH4_LOC0_V << DMAC_CH4_LOC0_S)
+#define DMAC_CH4_LOC0_V  0x03FFFFFFU
+#define DMAC_CH4_LOC0_S  6
+
+/** DMAC_CH4_LLP1_REG register
+ *  NA
+ */
+#define DMAC_CH4_LLP1_REG (DR_REG_DMAC_BASE + 0x42c)
+/** DMAC_CH4_LOC1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LOC1    0xFFFFFFFFU
+#define DMAC_CH4_LOC1_M  (DMAC_CH4_LOC1_V << DMAC_CH4_LOC1_S)
+#define DMAC_CH4_LOC1_V  0xFFFFFFFFU
+#define DMAC_CH4_LOC1_S  0
+
+/** DMAC_CH4_STATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH4_STATUS0_REG (DR_REG_DMAC_BASE + 0x430)
+/** DMAC_CH4_CMPLTD_BLK_TFR_SIZE : RO; bitpos: [21:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CMPLTD_BLK_TFR_SIZE    0x003FFFFFU
+#define DMAC_CH4_CMPLTD_BLK_TFR_SIZE_M  (DMAC_CH4_CMPLTD_BLK_TFR_SIZE_V << DMAC_CH4_CMPLTD_BLK_TFR_SIZE_S)
+#define DMAC_CH4_CMPLTD_BLK_TFR_SIZE_V  0x003FFFFFU
+#define DMAC_CH4_CMPLTD_BLK_TFR_SIZE_S  0
+
+/** DMAC_CH4_STATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH4_STATUS1_REG (DR_REG_DMAC_BASE + 0x434)
+/** DMAC_CH4_DATA_LEFT_IN_FIFO : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DATA_LEFT_IN_FIFO    0x00007FFFU
+#define DMAC_CH4_DATA_LEFT_IN_FIFO_M  (DMAC_CH4_DATA_LEFT_IN_FIFO_V << DMAC_CH4_DATA_LEFT_IN_FIFO_S)
+#define DMAC_CH4_DATA_LEFT_IN_FIFO_V  0x00007FFFU
+#define DMAC_CH4_DATA_LEFT_IN_FIFO_S  0
+
+/** DMAC_CH4_SWHSSRC0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SWHSSRC0_REG (DR_REG_DMAC_BASE + 0x438)
+/** DMAC_CH4_SWHS_REQ_SRC : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_REQ_SRC    (BIT(0))
+#define DMAC_CH4_SWHS_REQ_SRC_M  (DMAC_CH4_SWHS_REQ_SRC_V << DMAC_CH4_SWHS_REQ_SRC_S)
+#define DMAC_CH4_SWHS_REQ_SRC_V  0x00000001U
+#define DMAC_CH4_SWHS_REQ_SRC_S  0
+/** DMAC_CH4_SWHS_REQ_SRC_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_REQ_SRC_WE    (BIT(1))
+#define DMAC_CH4_SWHS_REQ_SRC_WE_M  (DMAC_CH4_SWHS_REQ_SRC_WE_V << DMAC_CH4_SWHS_REQ_SRC_WE_S)
+#define DMAC_CH4_SWHS_REQ_SRC_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_REQ_SRC_WE_S  1
+/** DMAC_CH4_SWHS_SGLREQ_SRC : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_SGLREQ_SRC    (BIT(2))
+#define DMAC_CH4_SWHS_SGLREQ_SRC_M  (DMAC_CH4_SWHS_SGLREQ_SRC_V << DMAC_CH4_SWHS_SGLREQ_SRC_S)
+#define DMAC_CH4_SWHS_SGLREQ_SRC_V  0x00000001U
+#define DMAC_CH4_SWHS_SGLREQ_SRC_S  2
+/** DMAC_CH4_SWHS_SGLREQ_SRC_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_SGLREQ_SRC_WE    (BIT(3))
+#define DMAC_CH4_SWHS_SGLREQ_SRC_WE_M  (DMAC_CH4_SWHS_SGLREQ_SRC_WE_V << DMAC_CH4_SWHS_SGLREQ_SRC_WE_S)
+#define DMAC_CH4_SWHS_SGLREQ_SRC_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_SGLREQ_SRC_WE_S  3
+/** DMAC_CH4_SWHS_LST_SRC : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_LST_SRC    (BIT(4))
+#define DMAC_CH4_SWHS_LST_SRC_M  (DMAC_CH4_SWHS_LST_SRC_V << DMAC_CH4_SWHS_LST_SRC_S)
+#define DMAC_CH4_SWHS_LST_SRC_V  0x00000001U
+#define DMAC_CH4_SWHS_LST_SRC_S  4
+/** DMAC_CH4_SWHS_LST_SRC_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_LST_SRC_WE    (BIT(5))
+#define DMAC_CH4_SWHS_LST_SRC_WE_M  (DMAC_CH4_SWHS_LST_SRC_WE_V << DMAC_CH4_SWHS_LST_SRC_WE_S)
+#define DMAC_CH4_SWHS_LST_SRC_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_LST_SRC_WE_S  5
+
+/** DMAC_CH4_SWHSDST0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SWHSDST0_REG (DR_REG_DMAC_BASE + 0x440)
+/** DMAC_CH4_SWHS_REQ_DST : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_REQ_DST    (BIT(0))
+#define DMAC_CH4_SWHS_REQ_DST_M  (DMAC_CH4_SWHS_REQ_DST_V << DMAC_CH4_SWHS_REQ_DST_S)
+#define DMAC_CH4_SWHS_REQ_DST_V  0x00000001U
+#define DMAC_CH4_SWHS_REQ_DST_S  0
+/** DMAC_CH4_SWHS_REQ_DST_WE : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_REQ_DST_WE    (BIT(1))
+#define DMAC_CH4_SWHS_REQ_DST_WE_M  (DMAC_CH4_SWHS_REQ_DST_WE_V << DMAC_CH4_SWHS_REQ_DST_WE_S)
+#define DMAC_CH4_SWHS_REQ_DST_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_REQ_DST_WE_S  1
+/** DMAC_CH4_SWHS_SGLREQ_DST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_SGLREQ_DST    (BIT(2))
+#define DMAC_CH4_SWHS_SGLREQ_DST_M  (DMAC_CH4_SWHS_SGLREQ_DST_V << DMAC_CH4_SWHS_SGLREQ_DST_S)
+#define DMAC_CH4_SWHS_SGLREQ_DST_V  0x00000001U
+#define DMAC_CH4_SWHS_SGLREQ_DST_S  2
+/** DMAC_CH4_SWHS_SGLREQ_DST_WE : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_SGLREQ_DST_WE    (BIT(3))
+#define DMAC_CH4_SWHS_SGLREQ_DST_WE_M  (DMAC_CH4_SWHS_SGLREQ_DST_WE_V << DMAC_CH4_SWHS_SGLREQ_DST_WE_S)
+#define DMAC_CH4_SWHS_SGLREQ_DST_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_SGLREQ_DST_WE_S  3
+/** DMAC_CH4_SWHS_LST_DST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_LST_DST    (BIT(4))
+#define DMAC_CH4_SWHS_LST_DST_M  (DMAC_CH4_SWHS_LST_DST_V << DMAC_CH4_SWHS_LST_DST_S)
+#define DMAC_CH4_SWHS_LST_DST_V  0x00000001U
+#define DMAC_CH4_SWHS_LST_DST_S  4
+/** DMAC_CH4_SWHS_LST_DST_WE : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SWHS_LST_DST_WE    (BIT(5))
+#define DMAC_CH4_SWHS_LST_DST_WE_M  (DMAC_CH4_SWHS_LST_DST_WE_V << DMAC_CH4_SWHS_LST_DST_WE_S)
+#define DMAC_CH4_SWHS_LST_DST_WE_V  0x00000001U
+#define DMAC_CH4_SWHS_LST_DST_WE_S  5
+
+/** DMAC_CH4_BLK_TFR_RESUMEREQ0_REG register
+ *  NA
+ */
+#define DMAC_CH4_BLK_TFR_RESUMEREQ0_REG (DR_REG_DMAC_BASE + 0x448)
+/** DMAC_CH4_BLK_TFR_RESUMEREQ : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_BLK_TFR_RESUMEREQ    (BIT(0))
+#define DMAC_CH4_BLK_TFR_RESUMEREQ_M  (DMAC_CH4_BLK_TFR_RESUMEREQ_V << DMAC_CH4_BLK_TFR_RESUMEREQ_S)
+#define DMAC_CH4_BLK_TFR_RESUMEREQ_V  0x00000001U
+#define DMAC_CH4_BLK_TFR_RESUMEREQ_S  0
+
+/** DMAC_CH4_AXI_ID0_REG register
+ *  NA
+ */
+#define DMAC_CH4_AXI_ID0_REG (DR_REG_DMAC_BASE + 0x450)
+/** DMAC_CH4_AXI_READ_ID_SUFFIX : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AXI_READ_ID_SUFFIX    (BIT(0))
+#define DMAC_CH4_AXI_READ_ID_SUFFIX_M  (DMAC_CH4_AXI_READ_ID_SUFFIX_V << DMAC_CH4_AXI_READ_ID_SUFFIX_S)
+#define DMAC_CH4_AXI_READ_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH4_AXI_READ_ID_SUFFIX_S  0
+/** DMAC_CH4_AXI_WRITE_ID_SUFFIX : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AXI_WRITE_ID_SUFFIX    (BIT(16))
+#define DMAC_CH4_AXI_WRITE_ID_SUFFIX_M  (DMAC_CH4_AXI_WRITE_ID_SUFFIX_V << DMAC_CH4_AXI_WRITE_ID_SUFFIX_S)
+#define DMAC_CH4_AXI_WRITE_ID_SUFFIX_V  0x00000001U
+#define DMAC_CH4_AXI_WRITE_ID_SUFFIX_S  16
+
+/** DMAC_CH4_AXI_QOS0_REG register
+ *  NA
+ */
+#define DMAC_CH4_AXI_QOS0_REG (DR_REG_DMAC_BASE + 0x458)
+/** DMAC_CH4_AXI_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AXI_AWQOS    0x0000000FU
+#define DMAC_CH4_AXI_AWQOS_M  (DMAC_CH4_AXI_AWQOS_V << DMAC_CH4_AXI_AWQOS_S)
+#define DMAC_CH4_AXI_AWQOS_V  0x0000000FU
+#define DMAC_CH4_AXI_AWQOS_S  0
+/** DMAC_CH4_AXI_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_AXI_ARQOS    0x0000000FU
+#define DMAC_CH4_AXI_ARQOS_M  (DMAC_CH4_AXI_ARQOS_V << DMAC_CH4_AXI_ARQOS_S)
+#define DMAC_CH4_AXI_ARQOS_V  0x0000000FU
+#define DMAC_CH4_AXI_ARQOS_S  4
+
+/** DMAC_CH4_SSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SSTAT0_REG (DR_REG_DMAC_BASE + 0x460)
+/** DMAC_CH4_SSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SSTAT    0xFFFFFFFFU
+#define DMAC_CH4_SSTAT_M  (DMAC_CH4_SSTAT_V << DMAC_CH4_SSTAT_S)
+#define DMAC_CH4_SSTAT_V  0xFFFFFFFFU
+#define DMAC_CH4_SSTAT_S  0
+
+/** DMAC_CH4_DSTAT0_REG register
+ *  NA
+ */
+#define DMAC_CH4_DSTAT0_REG (DR_REG_DMAC_BASE + 0x468)
+/** DMAC_CH4_DSTAT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DSTAT    0xFFFFFFFFU
+#define DMAC_CH4_DSTAT_M  (DMAC_CH4_DSTAT_V << DMAC_CH4_DSTAT_S)
+#define DMAC_CH4_DSTAT_V  0xFFFFFFFFU
+#define DMAC_CH4_DSTAT_S  0
+
+/** DMAC_CH4_SSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_SSTATAR0_REG (DR_REG_DMAC_BASE + 0x470)
+/** DMAC_CH4_SSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SSTATAR0    0xFFFFFFFFU
+#define DMAC_CH4_SSTATAR0_M  (DMAC_CH4_SSTATAR0_V << DMAC_CH4_SSTATAR0_S)
+#define DMAC_CH4_SSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH4_SSTATAR0_S  0
+
+/** DMAC_CH4_SSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_SSTATAR1_REG (DR_REG_DMAC_BASE + 0x474)
+/** DMAC_CH4_SSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SSTATAR1    0xFFFFFFFFU
+#define DMAC_CH4_SSTATAR1_M  (DMAC_CH4_SSTATAR1_V << DMAC_CH4_SSTATAR1_S)
+#define DMAC_CH4_SSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH4_SSTATAR1_S  0
+
+/** DMAC_CH4_DSTATAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_DSTATAR0_REG (DR_REG_DMAC_BASE + 0x478)
+/** DMAC_CH4_DSTATAR0 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DSTATAR0    0xFFFFFFFFU
+#define DMAC_CH4_DSTATAR0_M  (DMAC_CH4_DSTATAR0_V << DMAC_CH4_DSTATAR0_S)
+#define DMAC_CH4_DSTATAR0_V  0xFFFFFFFFU
+#define DMAC_CH4_DSTATAR0_S  0
+
+/** DMAC_CH4_DSTATAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_DSTATAR1_REG (DR_REG_DMAC_BASE + 0x47c)
+/** DMAC_CH4_DSTATAR1 : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DSTATAR1    0xFFFFFFFFU
+#define DMAC_CH4_DSTATAR1_M  (DMAC_CH4_DSTATAR1_V << DMAC_CH4_DSTATAR1_S)
+#define DMAC_CH4_DSTATAR1_V  0xFFFFFFFFU
+#define DMAC_CH4_DSTATAR1_S  0
+
+/** DMAC_CH4_INTSTATUS_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSTATUS_ENABLE0_REG (DR_REG_DMAC_BASE + 0x480)
+/** DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_V << DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_V << DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_V << DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : R/W; bitpos: [13]; default:
+ *  1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_V << DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_V << DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_M  (DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_V << DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH4_INTSTATUS_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSTATUS_ENABLE1_REG (DR_REG_DMAC_BASE + 0x484)
+/** DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH4_INTSTATUS0_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSTATUS0_REG (DR_REG_DMAC_BASE + 0x488)
+/** DMAC_CH4_BLOCK_TFR_DONE_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH4_DMA_TFR_DONE_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH4_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH4_DMA_TFR_DONE_INTSTAT_V << DMAC_CH4_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH4_SRC_TRANSCOMP_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH4_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH4_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH4_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH4_DST_TRANSCOMP_INTSTAT : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH4_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH4_DST_TRANSCOMP_INTSTAT_V << DMAC_CH4_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH4_SRC_DEC_ERR_INTSTAT : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH4_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH4_SRC_DEC_ERR_INTSTAT_V << DMAC_CH4_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH4_DST_DEC_ERR_INTSTAT : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH4_DST_DEC_ERR_INTSTAT_M  (DMAC_CH4_DST_DEC_ERR_INTSTAT_V << DMAC_CH4_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH4_SRC_SLV_ERR_INTSTAT : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH4_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH4_SRC_SLV_ERR_INTSTAT_V << DMAC_CH4_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH4_DST_SLV_ERR_INTSTAT : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH4_DST_SLV_ERR_INTSTAT_M  (DMAC_CH4_DST_SLV_ERR_INTSTAT_V << DMAC_CH4_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH4_SLVIF_DEC_ERR_INTSTAT : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT : RO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT : RO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT : RO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : RO; bitpos: [20]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT : RO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH4_CH_LOCK_CLEARED_INTSTAT : RO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH4_CH_SUSPENDED_INTSTAT : RO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH4_CH_SUSPENDED_INTSTAT_M  (DMAC_CH4_CH_SUSPENDED_INTSTAT_V << DMAC_CH4_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH4_CH_DISABLED_INTSTAT : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH4_CH_DISABLED_INTSTAT_M  (DMAC_CH4_CH_DISABLED_INTSTAT_V << DMAC_CH4_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH4_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH4_CH_ABORTED_INTSTAT : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH4_CH_ABORTED_INTSTAT_M  (DMAC_CH4_CH_ABORTED_INTSTAT_V << DMAC_CH4_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH4_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH4_INTSTATUS1_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSTATUS1_REG (DR_REG_DMAC_BASE + 0x48c)
+/** DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+/** DMAC_CH4_INTSIGNAL_ENABLE0_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSIGNAL_ENABLE0_REG (DR_REG_DMAC_BASE + 0x490)
+/** DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL    (BIT(0))
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_M  (DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V << DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_BLOCK_TFR_DONE_INTSIGNAL_S  0
+/** DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL    (BIT(1))
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_M  (DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_V << DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_DMA_TFR_DONE_INTSIGNAL_S  1
+/** DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL    (BIT(3))
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_M  (DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V << DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_TRANSCOMP_INTSIGNAL_S  3
+/** DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL    (BIT(4))
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_M  (DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_V << DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_TRANSCOMP_INTSIGNAL_S  4
+/** DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL    (BIT(5))
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_DEC_ERR_INTSIGNAL_S  5
+/** DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL    (BIT(6))
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_DEC_ERR_INTSIGNAL_S  6
+/** DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL    (BIT(7))
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SRC_SLV_ERR_INTSIGNAL_S  7
+/** DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL    (BIT(8))
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_DST_SLV_ERR_INTSIGNAL_S  8
+/** DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL    (BIT(9))
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_RD_DEC_ERR_INTSIGNAL_S  9
+/** DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL    (BIT(10))
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_WR_DEC_ERR_INTSIGNAL_S  10
+/** DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL    (BIT(11))
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_RD_SLV_ERR_INTSIGNAL_S  11
+/** DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL    (BIT(12))
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_LLI_WR_SLV_ERR_INTSIGNAL_S  12
+/** DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL : R/W; bitpos: [13];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL    (BIT(13))
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL_S  13
+/** DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL    (BIT(14))
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL_S  14
+/** DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL    (BIT(16))
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_DEC_ERR_INTSIGNAL_S  16
+/** DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL    (BIT(17))
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL_S  17
+/** DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL    (BIT(18))
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL_S  18
+/** DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL    (BIT(19))
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL_S  19
+/** DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL : R/W; bitpos: [20];
+ *  default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL    (BIT(20))
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL_S  20
+/** DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL    (BIT(21))
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL_S  21
+/** DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL : RO; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL    (BIT(25))
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V << DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_SLVIF_WRPARITY_ERR_INTSIGNAL_S  25
+/** DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL    (BIT(27))
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_LOCK_CLEARED_INTSIGNAL_S  27
+/** DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL    (BIT(28))
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_SRC_SUSPENDED_INTSIGNAL_S  28
+/** DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL    (BIT(29))
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_SUSPENDED_INTSIGNAL_S  29
+/** DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL    (BIT(30))
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_DISABLED_INTSIGNAL_S  30
+/** DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL    (BIT(31))
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_M  (DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_V << DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_CH_ABORTED_INTSIGNAL_S  31
+
+/** DMAC_CH4_INTSIGNAL_ENABLE1_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTSIGNAL_ENABLE1_REG (DR_REG_DMAC_BASE + 0x494)
+/** DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL    (BIT(0))
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V << DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_CORRERR_INTSIGNAL_S  0
+/** DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL    (BIT(1))
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_CHMEM_UNCORRERR_INTSIGNAL_S  1
+/** DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL : RO; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL    (BIT(2))
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V << DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_CORRERR_INTSIGNAL_S  2
+/** DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL : RO; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL    (BIT(3))
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_M  (DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V << DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S)
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_V  0x00000001U
+#define DMAC_CH4_ENABLE_ECC_PROT_UIDMEM_UNCORRERR_INTSIGNAL_S  3
+
+/** DMAC_CH4_INTCLEAR0_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTCLEAR0_REG (DR_REG_DMAC_BASE + 0x498)
+/** DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT    (BIT(0))
+#define DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_M  (DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_V << DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_BLOCK_TFR_DONE_INTSTAT_S  0
+/** DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT    (BIT(1))
+#define DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_M  (DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_V << DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_S)
+#define DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_DMA_TFR_DONE_INTSTAT_S  1
+/** DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT    (BIT(3))
+#define DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_M  (DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_V << DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SRC_TRANSCOMP_INTSTAT_S  3
+/** DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT : WO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT    (BIT(4))
+#define DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_M  (DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_V << DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_S)
+#define DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_DST_TRANSCOMP_INTSTAT_S  4
+/** DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT : WO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT    (BIT(5))
+#define DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SRC_DEC_ERR_INTSTAT_S  5
+/** DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT : WO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT    (BIT(6))
+#define DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_DST_DEC_ERR_INTSTAT_S  6
+/** DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT : WO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT    (BIT(7))
+#define DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SRC_SLV_ERR_INTSTAT_S  7
+/** DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT    (BIT(8))
+#define DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_V << DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_DST_SLV_ERR_INTSTAT_S  8
+/** DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT : WO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT    (BIT(9))
+#define DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_LLI_RD_DEC_ERR_INTSTAT_S  9
+/** DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT : WO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT    (BIT(10))
+#define DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_LLI_WR_DEC_ERR_INTSTAT_S  10
+/** DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT : WO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT    (BIT(11))
+#define DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V << DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_LLI_RD_SLV_ERR_INTSTAT_S  11
+/** DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT    (BIT(12))
+#define DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V << DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_LLI_WR_SLV_ERR_INTSTAT_S  12
+/** DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT : WO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT    (BIT(13))
+#define DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_S  13
+/** DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT : WO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT    (BIT(14))
+#define DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_S  14
+/** DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT : WO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT    (BIT(16))
+#define DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_DEC_ERR_INTSTAT_S  16
+/** DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT : WO; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT    (BIT(17))
+#define DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_WR2RO_ERR_INTSTAT_S  17
+/** DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT : WO; bitpos: [18]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT    (BIT(18))
+#define DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_RD2RWO_ERR_INTSTAT_S  18
+/** DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT : WO; bitpos: [19]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT    (BIT(19))
+#define DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT_S  19
+/** DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT : WO; bitpos: [20]; default:
+ *  0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT    (BIT(20))
+#define DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_S  20
+/** DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT : WO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT    (BIT(21))
+#define DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT_S  21
+/** DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT : WO; bitpos: [25]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT    (BIT(25))
+#define DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_M  (DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V << DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_SLVIF_WRPARITY_ERR_INTSTAT_S  25
+/** DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT : WO; bitpos: [27]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT    (BIT(27))
+#define DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_V << DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_LOCK_CLEARED_INTSTAT_S  27
+/** DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT : WO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT    (BIT(28))
+#define DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V << DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_SRC_SUSPENDED_INTSTAT_S  28
+/** DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT : WO; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT    (BIT(29))
+#define DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_V << DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_SUSPENDED_INTSTAT_S  29
+/** DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT : WO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT    (BIT(30))
+#define DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_V << DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_DISABLED_INTSTAT_S  30
+/** DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT : WO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT    (BIT(31))
+#define DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_M  (DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_V << DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_S)
+#define DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_CH_ABORTED_INTSTAT_S  31
+
+/** DMAC_CH4_INTCLEAR1_REG register
+ *  NA
+ */
+#define DMAC_CH4_INTCLEAR1_REG (DR_REG_DMAC_BASE + 0x49c)
+/** DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT : WO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT    (BIT(0))
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_M  (DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V << DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_CORRERR_INTSTAT_S  0
+/** DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT : WO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT    (BIT(1))
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_ECC_PROT_CHMEM_UNCORRERR_INTSTAT_S  1
+/** DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT : WO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT    (BIT(2))
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_M  (DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V << DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_CORRERR_INTSTAT_S  2
+/** DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT : WO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT    (BIT(3))
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_M  (DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V << DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S)
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_V  0x00000001U
+#define DMAC_CH4_CLEAR_ECC_PROT_UIDMEM_UNCORRERR_INTSTAT_S  3
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_struct.h
new file mode 100644
index 0000000000..a751e25fc7
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/dw_gdma_struct.h
@@ -0,0 +1,1782 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13429
+
+/** Group: Version Register */
+/** Type of id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_id : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_id: 32;
+    };
+    uint32_t val;
+} dmac_id0_reg_t;
+
+/** Type of compver0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_compver : RO; bitpos: [31:0]; default: 842018858;
+         *  NA
+         */
+        uint32_t dmac_compver: 32;
+    };
+    uint32_t val;
+} dmac_compver0_reg_t;
+
+/** Group: Configuration Registers */
+/** Type of cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_en: 1;
+        /** int_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t int_en: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} dmac_cfg0_reg_t;
+
+/** Type of chen0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en: 1;
+        /** ch2_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en: 1;
+        /** ch3_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en: 1;
+        /** ch4_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en: 1;
+        uint32_t reserved_4: 4;
+        /** ch1_en_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_en_we: 1;
+        /** ch2_en_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_en_we: 1;
+        /** ch3_en_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_en_we: 1;
+        /** ch4_en_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_en_we: 1;
+        uint32_t reserved_12: 4;
+        /** ch1_susp : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp: 1;
+        /** ch2_susp : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp: 1;
+        /** ch3_susp : R/W; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp: 1;
+        /** ch4_susp : R/W; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp: 1;
+        uint32_t reserved_20: 4;
+        /** ch1_susp_we : WO; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_susp_we: 1;
+        /** ch2_susp_we : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_susp_we: 1;
+        /** ch3_susp_we : WO; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_susp_we: 1;
+        /** ch4_susp_we : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_susp_we: 1;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} dmac_chen0_reg_t;
+
+/** Type of chen1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_abort : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort: 1;
+        /** ch2_abort : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort: 1;
+        /** ch3_abort : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort: 1;
+        /** ch4_abort : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort: 1;
+        uint32_t reserved_4: 4;
+        /** ch1_abort_we : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_abort_we: 1;
+        /** ch2_abort_we : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_abort_we: 1;
+        /** ch3_abort_we : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_abort_we: 1;
+        /** ch4_abort_we : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_abort_we: 1;
+        uint32_t reserved_12: 20;
+    };
+    uint32_t val;
+} dmac_chen1_reg_t;
+
+/** Type of reset0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dmac_rst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t dmac_rst: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} dmac_reset0_reg_t;
+
+/** Type of lowpower_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** gbl_cslp_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t gbl_cslp_en: 1;
+        /** chnl_cslp_en : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t chnl_cslp_en: 1;
+        /** sbiu_cslp_en : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t sbiu_cslp_en: 1;
+        /** mxif_cslp_en : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t mxif_cslp_en: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg0_reg_t;
+
+/** Type of lowpower_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** glch_lpdly : R/W; bitpos: [7:0]; default: 64;
+         *  NA
+         */
+        uint32_t glch_lpdly: 8;
+        /** sbiu_lpdly : R/W; bitpos: [15:8]; default: 64;
+         *  NA
+         */
+        uint32_t sbiu_lpdly: 8;
+        /** mxif_lpdly : R/W; bitpos: [23:16]; default: 64;
+         *  NA
+         */
+        uint32_t mxif_lpdly: 8;
+        uint32_t reserved_24: 8;
+    };
+    uint32_t val;
+} dmac_lowpower_cfg1_reg_t;
+
+/** Type of chn_sar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_sar0_reg_t;
+
+/** Type of chn_sar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_sar1_reg_t;
+
+/** Type of chn_dar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_dar0_reg_t;
+
+/** Type of chn_dar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_dar1_reg_t;
+
+/** Type of chn_block_ts0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** block_ts : R/W; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t block_ts: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} dmac_chn_block_ts0_reg_t;
+
+/** Type of chn_ctl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t sms: 1;
+        uint32_t reserved_1: 1;
+        /** dms : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t dms: 1;
+        uint32_t reserved_3: 1;
+        /** sinc : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t sinc: 1;
+        uint32_t reserved_5: 1;
+        /** dinc : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t dinc: 1;
+        uint32_t reserved_7: 1;
+        /** src_tr_width : R/W; bitpos: [10:8]; default: 2;
+         *  NA
+         */
+        uint32_t src_tr_width: 3;
+        /** dst_tr_width : R/W; bitpos: [13:11]; default: 2;
+         *  NA
+         */
+        uint32_t dst_tr_width: 3;
+        /** src_msize : R/W; bitpos: [17:14]; default: 0;
+         *  NA
+         */
+        uint32_t src_msize: 4;
+        /** dst_msize : R/W; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t dst_msize: 4;
+        /** ar_cache : R/W; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t ar_cache: 4;
+        /** aw_cache : R/W; bitpos: [29:26]; default: 0;
+         *  NA
+         */
+        uint32_t aw_cache: 4;
+        /** nonposted_lastwrite_en : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t nonposted_lastwrite_en: 1;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} dmac_chn_ctl0_reg_t;
+
+/** Type of chn_ctl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ar_prot : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t ar_prot: 3;
+        /** aw_prot : R/W; bitpos: [5:3]; default: 0;
+         *  NA
+         */
+        uint32_t aw_prot: 3;
+        /** arlen_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t arlen_en: 1;
+        /** arlen : R/W; bitpos: [14:7]; default: 0;
+         *  NA
+         */
+        uint32_t arlen: 8;
+        /** awlen_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t awlen_en: 1;
+        /** awlen : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t awlen: 8;
+        /** src_stat_en : R/W; bitpos: [24]; default: 0;
+         *  NA
+         */
+        uint32_t src_stat_en: 1;
+        /** dst_stat_en : R/W; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t dst_stat_en: 1;
+        /** ioc_blktfr : R/W; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t ioc_blktfr: 1;
+        uint32_t reserved_27: 3;
+        /** shadowreg_or_lli_last : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t shadowreg_or_lli_last: 1;
+        /** shadowreg_or_lli_valid : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t shadowreg_or_lli_valid: 1;
+    };
+    uint32_t val;
+} dmac_chn_ctl1_reg_t;
+
+/** Type of chn_cfg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** src_multblk_type : R/W; bitpos: [1:0]; default: 0;
+         *  NA
+         */
+        uint32_t src_multblk_type: 2;
+        /** dst_multblk_type : R/W; bitpos: [3:2]; default: 0;
+         *  NA
+         */
+        uint32_t dst_multblk_type: 2;
+        uint32_t reserved_4: 14;
+        /** rd_uid : RO; bitpos: [21:18]; default: 0;
+         *  NA
+         */
+        uint32_t rd_uid: 4;
+        uint32_t reserved_22: 3;
+        /** wr_uid : RO; bitpos: [28:25]; default: 0;
+         *  NA
+         */
+        uint32_t wr_uid: 4;
+        uint32_t reserved_29: 3;
+    };
+    uint32_t val;
+} dmac_chn_cfg0_reg_t;
+
+/** Type of chn_cfg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tt_fc : R/W; bitpos: [2:0]; default: 3;
+         *  NA
+         */
+        uint32_t tt_fc: 3;
+        /** hs_sel_src : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t hs_sel_src: 1;
+        /** hs_sel_dst : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t hs_sel_dst: 1;
+        /** src_hwhs_pol : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t src_hwhs_pol: 1;
+        /** dst_hwhs_pol : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t dst_hwhs_pol: 1;
+        /** src_per : R/W; bitpos: [8:7]; default: 0;
+         *  NA
+         */
+        uint32_t src_per: 2;
+        uint32_t reserved_9: 3;
+        /** dst_per : R/W; bitpos: [13:12]; default: 0;
+         *  NA
+         */
+        uint32_t dst_per: 2;
+        uint32_t reserved_14: 3;
+        /** ch_prior : R/W; bitpos: [19:17]; default: 3;
+         *  NA
+         */
+        uint32_t ch_prior: 3;
+        /** lock_ch : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t lock_ch: 1;
+        /** lock_ch_l : RO; bitpos: [22:21]; default: 0;
+         *  NA
+         */
+        uint32_t lock_ch_l: 2;
+        /** src_osr_lmt : R/W; bitpos: [26:23]; default: 0;
+         *  NA
+         */
+        uint32_t src_osr_lmt: 4;
+        /** dst_osr_lmt : R/W; bitpos: [30:27]; default: 0;
+         *  NA
+         */
+        uint32_t dst_osr_lmt: 4;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} dmac_chn_cfg1_reg_t;
+
+/** Type of chn_llp0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** lms : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t lms: 1;
+        uint32_t reserved_1: 5;
+        /** loc0 : R/W; bitpos: [31:6]; default: 0;
+         *  NA
+         */
+        uint32_t loc0: 26;
+    };
+    uint32_t val;
+} dmac_chn_llp0_reg_t;
+
+/** Type of chn_llp1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** loc1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t loc1: 32;
+    };
+    uint32_t val;
+} dmac_chn_llp1_reg_t;
+
+/** Type of chn_swhssrc0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** swhs_req_src : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_src: 1;
+        /** swhs_req_src_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_src_we: 1;
+        /** swhs_sglreq_src : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_src: 1;
+        /** swhs_sglreq_src_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_src_we: 1;
+        /** swhs_lst_src : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_src: 1;
+        /** swhs_lst_src_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_src_we: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} dmac_chn_swhssrc0_reg_t;
+
+/** Type of chn_swhsdst0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** swhs_req_dst : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_dst: 1;
+        /** swhs_req_dst_we : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_req_dst_we: 1;
+        /** swhs_sglreq_dst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_dst: 1;
+        /** swhs_sglreq_dst_we : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_sglreq_dst_we: 1;
+        /** swhs_lst_dst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_dst: 1;
+        /** swhs_lst_dst_we : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t swhs_lst_dst_we: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} dmac_chn_swhsdst0_reg_t;
+
+/** Type of chn_blk_tfr_resumereq0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** blk_tfr_resumereq : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t blk_tfr_resumereq: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} dmac_chn_blk_tfr_resumereq0_reg_t;
+
+/** Type of chn_axi_id0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** axi_read_id_suffix : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t axi_read_id_suffix: 1;
+        uint32_t reserved_1: 15;
+        /** axi_write_id_suffix : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t axi_write_id_suffix: 1;
+        uint32_t reserved_17: 15;
+    };
+    uint32_t val;
+} dmac_chn_axi_id0_reg_t;
+
+/** Type of chn_axi_qos0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** axi_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t axi_awqos: 4;
+        /** axi_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t axi_arqos: 4;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} dmac_chn_axi_qos0_reg_t;
+
+/** Group: Interrupt Registers */
+/** Type of intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ch1_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ch1_intstat: 1;
+        /** ch2_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ch2_intstat: 1;
+        /** ch3_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ch3_intstat: 1;
+        /** ch4_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ch4_intstat: 1;
+        uint32_t reserved_4: 12;
+        /** commonreg_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t commonreg_intstat: 1;
+        uint32_t reserved_17: 15;
+    };
+    uint32_t val;
+} dmac_intstatus0_reg_t;
+
+/** Type of commonreg_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_slvif_commonreg_dec_err_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_dec_err_intstat: 1;
+        /** clear_slvif_commonreg_wr2ro_err_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wr2ro_err_intstat: 1;
+        /** clear_slvif_commonreg_rd2wo_err_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_rd2wo_err_intstat: 1;
+        /** clear_slvif_commonreg_wronhold_err_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wronhold_err_intstat: 1;
+        uint32_t reserved_4: 3;
+        /** clear_slvif_commonreg_wrparity_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_commonreg_wrparity_err_intstat: 1;
+        /** clear_slvif_undefinedreg_dec_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_undefinedreg_dec_err_intstat: 1;
+        /** clear_mxif1_rch0_eccprot_correrr_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_correrr_intstat: 1;
+        /** clear_mxif1_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch0_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif1_rch1_eccprot_correrr_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_correrr_intstat: 1;
+        /** clear_mxif1_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_rch1_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif1_bch_eccprot_correrr_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_correrr_intstat: 1;
+        /** clear_mxif1_bch_eccprot_uncorrerr_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif1_bch_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif2_rch0_eccprot_correrr_intstat : WO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_correrr_intstat: 1;
+        /** clear_mxif2_rch0_eccprot_uncorrerr_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch0_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif2_rch1_eccprot_correrr_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_correrr_intstat: 1;
+        /** clear_mxif2_rch1_eccprot_uncorrerr_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_rch1_eccprot_uncorrerr_intstat: 1;
+        /** clear_mxif2_bch_eccprot_correrr_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_correrr_intstat: 1;
+        /** clear_mxif2_bch_eccprot_uncorrerr_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t clear_mxif2_bch_eccprot_uncorrerr_intstat: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intclear0_reg_t;
+
+/** Type of commonreg_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intstat: 1;
+        /** enable_slvif_commonreg_wr2ro_err_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intstat: 1;
+        /** enable_slvif_commonreg_rd2wo_err_intstat : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intstat: 1;
+        /** enable_slvif_commonreg_wronhold_err_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intstat: 1;
+        uint32_t reserved_4: 3;
+        /** enable_slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intstat: 1;
+        /** enable_slvif_undefinedreg_dec_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intstat: 1;
+        /** enable_mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intstat: 1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intstat: 1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intstat: 1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intstat: 1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intstat: 1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intstat: 1;
+        /** enable_mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intstat: 1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intstat: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus_enable0_reg_t;
+
+/** Type of commonreg_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_slvif_commonreg_dec_err_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_dec_err_intsignal: 1;
+        /** enable_slvif_commonreg_wr2ro_err_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wr2ro_err_intsignal: 1;
+        /** enable_slvif_commonreg_rd2wo_err_intsignal : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_rd2wo_err_intsignal: 1;
+        /** enable_slvif_commonreg_wronhold_err_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wronhold_err_intsignal: 1;
+        uint32_t reserved_4: 3;
+        /** enable_slvif_commonreg_wrparity_err_intsignal : RO; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_commonreg_wrparity_err_intsignal: 1;
+        /** enable_slvif_undefinedreg_dec_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_undefinedreg_dec_err_intsignal: 1;
+        /** enable_mxif1_rch0_eccprot_correrr_intsignal : RO; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_correrr_intsignal: 1;
+        /** enable_mxif1_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch0_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif1_rch1_eccprot_correrr_intsignal : RO; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_correrr_intsignal: 1;
+        /** enable_mxif1_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_rch1_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif1_bch_eccprot_correrr_intsignal : RO; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_correrr_intsignal: 1;
+        /** enable_mxif1_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif1_bch_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif2_rch0_eccprot_correrr_intsignal : RO; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_correrr_intsignal: 1;
+        /** enable_mxif2_rch0_eccprot_uncorrerr_intsignal : RO; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch0_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif2_rch1_eccprot_correrr_intsignal : RO; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_correrr_intsignal: 1;
+        /** enable_mxif2_rch1_eccprot_uncorrerr_intsignal : RO; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_rch1_eccprot_uncorrerr_intsignal: 1;
+        /** enable_mxif2_bch_eccprot_correrr_intsignal : RO; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_correrr_intsignal: 1;
+        /** enable_mxif2_bch_eccprot_uncorrerr_intsignal : RO; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_mxif2_bch_eccprot_uncorrerr_intsignal: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intsignal_enable0_reg_t;
+
+/** Type of commonreg_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** slvif_commonreg_dec_err_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_dec_err_intstat: 1;
+        /** slvif_commonreg_wr2ro_err_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wr2ro_err_intstat: 1;
+        /** slvif_commonreg_rd2wo_err_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_rd2wo_err_intstat: 1;
+        /** slvif_commonreg_wronhold_err_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wronhold_err_intstat: 1;
+        uint32_t reserved_4: 3;
+        /** slvif_commonreg_wrparity_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_commonreg_wrparity_err_intstat: 1;
+        /** slvif_undefinedreg_dec_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_undefinedreg_dec_err_intstat: 1;
+        /** mxif1_rch0_eccprot_correrr_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_correrr_intstat: 1;
+        /** mxif1_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch0_eccprot_uncorrerr_intstat: 1;
+        /** mxif1_rch1_eccprot_correrr_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_correrr_intstat: 1;
+        /** mxif1_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_rch1_eccprot_uncorrerr_intstat: 1;
+        /** mxif1_bch_eccprot_correrr_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_correrr_intstat: 1;
+        /** mxif1_bch_eccprot_uncorrerr_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t mxif1_bch_eccprot_uncorrerr_intstat: 1;
+        /** mxif2_rch0_eccprot_correrr_intstat : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_correrr_intstat: 1;
+        /** mxif2_rch0_eccprot_uncorrerr_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch0_eccprot_uncorrerr_intstat: 1;
+        /** mxif2_rch1_eccprot_correrr_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_correrr_intstat: 1;
+        /** mxif2_rch1_eccprot_uncorrerr_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_rch1_eccprot_uncorrerr_intstat: 1;
+        /** mxif2_bch_eccprot_correrr_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_correrr_intstat: 1;
+        /** mxif2_bch_eccprot_uncorrerr_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t mxif2_bch_eccprot_uncorrerr_intstat: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} dmac_commonreg_intstatus0_reg_t;
+
+/** Type of chn_intstatus_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_block_tfr_done_intstat : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_block_tfr_done_intstat: 1;
+        /** enable_dma_tfr_done_intstat : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dma_tfr_done_intstat: 1;
+        uint32_t reserved_2: 1;
+        /** enable_src_transcomp_intstat : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_transcomp_intstat: 1;
+        /** enable_dst_transcomp_intstat : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_transcomp_intstat: 1;
+        /** enable_src_dec_err_intstat : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_dec_err_intstat: 1;
+        /** enable_dst_dec_err_intstat : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_dec_err_intstat: 1;
+        /** enable_src_slv_err_intstat : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_slv_err_intstat: 1;
+        /** enable_dst_slv_err_intstat : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_slv_err_intstat: 1;
+        /** enable_lli_rd_dec_err_intstat : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_dec_err_intstat: 1;
+        /** enable_lli_wr_dec_err_intstat : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_dec_err_intstat: 1;
+        /** enable_lli_rd_slv_err_intstat : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_slv_err_intstat: 1;
+        /** enable_lli_wr_slv_err_intstat : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_slv_err_intstat: 1;
+        /** enable_shadowreg_or_lli_invalid_err_intstat : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_shadowreg_or_lli_invalid_err_intstat: 1;
+        /** enable_slvif_multiblktype_err_intstat : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_multiblktype_err_intstat: 1;
+        uint32_t reserved_15: 1;
+        /** enable_slvif_dec_err_intstat : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_dec_err_intstat: 1;
+        /** enable_slvif_wr2ro_err_intstat : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wr2ro_err_intstat: 1;
+        /** enable_slvif_rd2rwo_err_intstat : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_rd2rwo_err_intstat: 1;
+        /** enable_slvif_wronchen_err_intstat : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronchen_err_intstat: 1;
+        /** enable_slvif_shadowreg_wron_valid_err_intstat : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_shadowreg_wron_valid_err_intstat: 1;
+        /** enable_slvif_wronhold_err_intstat : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronhold_err_intstat: 1;
+        uint32_t reserved_22: 3;
+        /** enable_slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wrparity_err_intstat: 1;
+        uint32_t reserved_26: 1;
+        /** enable_ch_lock_cleared_intstat : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_lock_cleared_intstat: 1;
+        /** enable_ch_src_suspended_intstat : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_src_suspended_intstat: 1;
+        /** enable_ch_suspended_intstat : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_suspended_intstat: 1;
+        /** enable_ch_disabled_intstat : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_disabled_intstat: 1;
+        /** enable_ch_aborted_intstat : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_aborted_intstat: 1;
+    };
+    uint32_t val;
+} dmac_chn_intstatus_enable0_reg_t;
+
+/** Type of chn_intstatus_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_correrr_intstat: 1;
+        /** enable_ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_uncorrerr_intstat: 1;
+        /** enable_ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_correrr_intstat: 1;
+        /** enable_ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_uncorrerr_intstat: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intstatus_enable1_reg_t;
+
+/** Type of chn_intstatus0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** block_tfr_done_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t block_tfr_done_intstat: 1;
+        /** dma_tfr_done_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t dma_tfr_done_intstat: 1;
+        uint32_t reserved_2: 1;
+        /** src_transcomp_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t src_transcomp_intstat: 1;
+        /** dst_transcomp_intstat : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t dst_transcomp_intstat: 1;
+        /** src_dec_err_intstat : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t src_dec_err_intstat: 1;
+        /** dst_dec_err_intstat : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t dst_dec_err_intstat: 1;
+        /** src_slv_err_intstat : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t src_slv_err_intstat: 1;
+        /** dst_slv_err_intstat : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t dst_slv_err_intstat: 1;
+        /** lli_rd_dec_err_intstat : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t lli_rd_dec_err_intstat: 1;
+        /** lli_wr_dec_err_intstat : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t lli_wr_dec_err_intstat: 1;
+        /** lli_rd_slv_err_intstat : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t lli_rd_slv_err_intstat: 1;
+        /** lli_wr_slv_err_intstat : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t lli_wr_slv_err_intstat: 1;
+        /** shadowreg_or_lli_invalid_err_intstat : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t shadowreg_or_lli_invalid_err_intstat: 1;
+        /** slvif_multiblktype_err_intstat : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_multiblktype_err_intstat: 1;
+        uint32_t reserved_15: 1;
+        /** slvif_dec_err_intstat : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_dec_err_intstat: 1;
+        /** slvif_wr2ro_err_intstat : RO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wr2ro_err_intstat: 1;
+        /** slvif_rd2rwo_err_intstat : RO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_rd2rwo_err_intstat: 1;
+        /** slvif_wronchen_err_intstat : RO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wronchen_err_intstat: 1;
+        /** slvif_shadowreg_wron_valid_err_intstat : RO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_shadowreg_wron_valid_err_intstat: 1;
+        /** slvif_wronhold_err_intstat : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wronhold_err_intstat: 1;
+        uint32_t reserved_22: 3;
+        /** slvif_wrparity_err_intstat : RO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t slvif_wrparity_err_intstat: 1;
+        uint32_t reserved_26: 1;
+        /** ch_lock_cleared_intstat : RO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t ch_lock_cleared_intstat: 1;
+        /** ch_src_suspended_intstat : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t ch_src_suspended_intstat: 1;
+        /** ch_suspended_intstat : RO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t ch_suspended_intstat: 1;
+        /** ch_disabled_intstat : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t ch_disabled_intstat: 1;
+        /** ch_aborted_intstat : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t ch_aborted_intstat: 1;
+    };
+    uint32_t val;
+} dmac_chn_intstatus0_reg_t;
+
+/** Type of chn_intstatus1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ecc_prot_chmem_correrr_intstat : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_chmem_correrr_intstat: 1;
+        /** ecc_prot_chmem_uncorrerr_intstat : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_chmem_uncorrerr_intstat: 1;
+        /** ecc_prot_uidmem_correrr_intstat : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_uidmem_correrr_intstat: 1;
+        /** ecc_prot_uidmem_uncorrerr_intstat : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t ecc_prot_uidmem_uncorrerr_intstat: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intstatus1_reg_t;
+
+/** Type of chn_intsignal_enable0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_block_tfr_done_intsignal : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_block_tfr_done_intsignal: 1;
+        /** enable_dma_tfr_done_intsignal : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dma_tfr_done_intsignal: 1;
+        uint32_t reserved_2: 1;
+        /** enable_src_transcomp_intsignal : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_transcomp_intsignal: 1;
+        /** enable_dst_transcomp_intsignal : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_transcomp_intsignal: 1;
+        /** enable_src_dec_err_intsignal : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_dec_err_intsignal: 1;
+        /** enable_dst_dec_err_intsignal : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_dec_err_intsignal: 1;
+        /** enable_src_slv_err_intsignal : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t enable_src_slv_err_intsignal: 1;
+        /** enable_dst_slv_err_intsignal : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t enable_dst_slv_err_intsignal: 1;
+        /** enable_lli_rd_dec_err_intsignal : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_dec_err_intsignal: 1;
+        /** enable_lli_wr_dec_err_intsignal : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_dec_err_intsignal: 1;
+        /** enable_lli_rd_slv_err_intsignal : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_rd_slv_err_intsignal: 1;
+        /** enable_lli_wr_slv_err_intsignal : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t enable_lli_wr_slv_err_intsignal: 1;
+        /** enable_shadowreg_or_lli_invalid_err_intsignal : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t enable_shadowreg_or_lli_invalid_err_intsignal: 1;
+        /** enable_slvif_multiblktype_err_intsignal : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_multiblktype_err_intsignal: 1;
+        uint32_t reserved_15: 1;
+        /** enable_slvif_dec_err_intsignal : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_dec_err_intsignal: 1;
+        /** enable_slvif_wr2ro_err_intsignal : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wr2ro_err_intsignal: 1;
+        /** enable_slvif_rd2rwo_err_intsignal : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_rd2rwo_err_intsignal: 1;
+        /** enable_slvif_wronchen_err_intsignal : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronchen_err_intsignal: 1;
+        /** enable_slvif_shadowreg_wron_valid_err_intsignal : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_shadowreg_wron_valid_err_intsignal: 1;
+        /** enable_slvif_wronhold_err_intsignal : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wronhold_err_intsignal: 1;
+        uint32_t reserved_22: 3;
+        /** enable_slvif_wrparity_err_intsignal : RO; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t enable_slvif_wrparity_err_intsignal: 1;
+        uint32_t reserved_26: 1;
+        /** enable_ch_lock_cleared_intsignal : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_lock_cleared_intsignal: 1;
+        /** enable_ch_src_suspended_intsignal : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_src_suspended_intsignal: 1;
+        /** enable_ch_suspended_intsignal : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_suspended_intsignal: 1;
+        /** enable_ch_disabled_intsignal : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_disabled_intsignal: 1;
+        /** enable_ch_aborted_intsignal : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ch_aborted_intsignal: 1;
+    };
+    uint32_t val;
+} dmac_chn_intsignal_enable0_reg_t;
+
+/** Type of chn_intsignal_enable1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** enable_ecc_prot_chmem_correrr_intsignal : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_correrr_intsignal: 1;
+        /** enable_ecc_prot_chmem_uncorrerr_intsignal : RO; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_chmem_uncorrerr_intsignal: 1;
+        /** enable_ecc_prot_uidmem_correrr_intsignal : RO; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_correrr_intsignal: 1;
+        /** enable_ecc_prot_uidmem_uncorrerr_intsignal : RO; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t enable_ecc_prot_uidmem_uncorrerr_intsignal: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intsignal_enable1_reg_t;
+
+/** Type of chn_intclear0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_block_tfr_done_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_block_tfr_done_intstat: 1;
+        /** clear_dma_tfr_done_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dma_tfr_done_intstat: 1;
+        uint32_t reserved_2: 1;
+        /** clear_src_transcomp_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_src_transcomp_intstat: 1;
+        /** clear_dst_transcomp_intstat : WO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dst_transcomp_intstat: 1;
+        /** clear_src_dec_err_intstat : WO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t clear_src_dec_err_intstat: 1;
+        /** clear_dst_dec_err_intstat : WO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dst_dec_err_intstat: 1;
+        /** clear_src_slv_err_intstat : WO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t clear_src_slv_err_intstat: 1;
+        /** clear_dst_slv_err_intstat : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t clear_dst_slv_err_intstat: 1;
+        /** clear_lli_rd_dec_err_intstat : WO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_rd_dec_err_intstat: 1;
+        /** clear_lli_wr_dec_err_intstat : WO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_wr_dec_err_intstat: 1;
+        /** clear_lli_rd_slv_err_intstat : WO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_rd_slv_err_intstat: 1;
+        /** clear_lli_wr_slv_err_intstat : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t clear_lli_wr_slv_err_intstat: 1;
+        /** clear_shadowreg_or_lli_invalid_err_intstat : WO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t clear_shadowreg_or_lli_invalid_err_intstat: 1;
+        /** clear_slvif_multiblktype_err_intstat : WO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_multiblktype_err_intstat: 1;
+        uint32_t reserved_15: 1;
+        /** clear_slvif_dec_err_intstat : WO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_dec_err_intstat: 1;
+        /** clear_slvif_wr2ro_err_intstat : WO; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wr2ro_err_intstat: 1;
+        /** clear_slvif_rd2rwo_err_intstat : WO; bitpos: [18]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_rd2rwo_err_intstat: 1;
+        /** clear_slvif_wronchen_err_intstat : WO; bitpos: [19]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wronchen_err_intstat: 1;
+        /** clear_slvif_shadowreg_wron_valid_err_intstat : WO; bitpos: [20]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_shadowreg_wron_valid_err_intstat: 1;
+        /** clear_slvif_wronhold_err_intstat : WO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wronhold_err_intstat: 1;
+        uint32_t reserved_22: 3;
+        /** clear_slvif_wrparity_err_intstat : WO; bitpos: [25]; default: 0;
+         *  NA
+         */
+        uint32_t clear_slvif_wrparity_err_intstat: 1;
+        uint32_t reserved_26: 1;
+        /** clear_ch_lock_cleared_intstat : WO; bitpos: [27]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_lock_cleared_intstat: 1;
+        /** clear_ch_src_suspended_intstat : WO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_src_suspended_intstat: 1;
+        /** clear_ch_suspended_intstat : WO; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_suspended_intstat: 1;
+        /** clear_ch_disabled_intstat : WO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_disabled_intstat: 1;
+        /** clear_ch_aborted_intstat : WO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ch_aborted_intstat: 1;
+    };
+    uint32_t val;
+} dmac_chn_intclear0_reg_t;
+
+/** Type of chn_intclear1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** clear_ecc_prot_chmem_correrr_intstat : WO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_chmem_correrr_intstat: 1;
+        /** clear_ecc_prot_chmem_uncorrerr_intstat : WO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_chmem_uncorrerr_intstat: 1;
+        /** clear_ecc_prot_uidmem_correrr_intstat : WO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_uidmem_correrr_intstat: 1;
+        /** clear_ecc_prot_uidmem_uncorrerr_intstat : WO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t clear_ecc_prot_uidmem_uncorrerr_intstat: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} dmac_chn_intclear1_reg_t;
+
+/** Group: Status Registers */
+/** Type of chn_status0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cmpltd_blk_tfr_size : RO; bitpos: [21:0]; default: 0;
+         *  NA
+         */
+        uint32_t cmpltd_blk_tfr_size: 22;
+        uint32_t reserved_22: 10;
+    };
+    uint32_t val;
+} dmac_chn_status0_reg_t;
+
+/** Type of chn_status1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** data_left_in_fifo : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t data_left_in_fifo: 15;
+        uint32_t reserved_15: 17;
+    };
+    uint32_t val;
+} dmac_chn_status1_reg_t;
+
+/** Type of chn_sstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sstat: 32;
+    };
+    uint32_t val;
+} dmac_chn_sstat0_reg_t;
+
+/** Type of chn_dstat0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dstat : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dstat: 32;
+    };
+    uint32_t val;
+} dmac_chn_dstat0_reg_t;
+
+/** Type of chn_sstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sstatar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_sstatar0_reg_t;
+
+/** Type of chn_sstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t sstatar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_sstatar1_reg_t;
+
+/** Type of chn_dstatar0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dstatar0 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dstatar0: 32;
+    };
+    uint32_t val;
+} dmac_chn_dstatar0_reg_t;
+
+/** Type of chn_dstatar1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dstatar1 : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dstatar1: 32;
+    };
+    uint32_t val;
+} dmac_chn_dstatar1_reg_t;
+
+typedef struct {
+    volatile dmac_chn_sar0_reg_t sar0;
+    volatile dmac_chn_sar1_reg_t sar1;
+    volatile dmac_chn_dar0_reg_t dar0;
+    volatile dmac_chn_dar1_reg_t dar1;
+    volatile dmac_chn_block_ts0_reg_t block_ts0;
+    uint32_t reserved_114;
+    volatile dmac_chn_ctl0_reg_t ctl0;
+    volatile dmac_chn_ctl1_reg_t ctl1;
+    volatile dmac_chn_cfg0_reg_t cfg0;
+    volatile dmac_chn_cfg1_reg_t cfg1;
+    volatile dmac_chn_llp0_reg_t llp0;
+    volatile dmac_chn_llp1_reg_t llp1;
+    volatile dmac_chn_status0_reg_t status0;
+    volatile dmac_chn_status1_reg_t status1;
+    volatile dmac_chn_swhssrc0_reg_t swhssrc0;
+    uint32_t reserved_13c;
+    volatile dmac_chn_swhsdst0_reg_t swhsdst0;
+    uint32_t reserved_144;
+    volatile dmac_chn_blk_tfr_resumereq0_reg_t blk_tfr_resumereq0;
+    uint32_t reserved_14c;
+    volatile dmac_chn_axi_id0_reg_t axi_id0;
+    uint32_t reserved_154;
+    volatile dmac_chn_axi_qos0_reg_t axi_qos0;
+    uint32_t reserved_15c;
+    volatile dmac_chn_sstat0_reg_t sstat0;
+    uint32_t reserved_164;
+    volatile dmac_chn_dstat0_reg_t dstat0;
+    uint32_t reserved_16c;
+    volatile dmac_chn_sstatar0_reg_t sstatar0;
+    volatile dmac_chn_sstatar1_reg_t sstatar1;
+    volatile dmac_chn_dstatar0_reg_t dstatar0;
+    volatile dmac_chn_dstatar1_reg_t dstatar1;
+    volatile dmac_chn_intstatus_enable0_reg_t int_st_ena0;
+    volatile dmac_chn_intstatus_enable1_reg_t int_st_ena1;
+    volatile dmac_chn_intstatus0_reg_t int_st0;
+    volatile dmac_chn_intstatus1_reg_t int_st1;
+    volatile dmac_chn_intsignal_enable0_reg_t int_sig_ena0;
+    volatile dmac_chn_intsignal_enable1_reg_t int_sig_ena1;
+    volatile dmac_chn_intclear0_reg_t int_clr0;
+    volatile dmac_chn_intclear1_reg_t int_clr1;
+    uint32_t reserved_1a0[24];
+} dmac_channel_reg_t;
+
+typedef struct dw_gdma_dev_t {
+    volatile dmac_id0_reg_t id0;
+    uint32_t reserved_004;
+    volatile dmac_compver0_reg_t compver0;
+    uint32_t reserved_00c;
+    volatile dmac_cfg0_reg_t cfg0;
+    uint32_t reserved_014;
+    volatile dmac_chen0_reg_t chen0;
+    volatile dmac_chen1_reg_t chen1;
+    uint32_t reserved_020[4];
+    volatile dmac_intstatus0_reg_t int_st0;
+    uint32_t reserved_034;
+    volatile dmac_commonreg_intclear0_reg_t common_int_clr0;
+    uint32_t reserved_03c;
+    volatile dmac_commonreg_intstatus_enable0_reg_t common_int_st_ena0;
+    uint32_t reserved_044;
+    volatile dmac_commonreg_intsignal_enable0_reg_t common_int_sig_ena0;
+    uint32_t reserved_04c;
+    volatile dmac_commonreg_intstatus0_reg_t common_int_st0;
+    uint32_t reserved_054;
+    volatile dmac_reset0_reg_t reset0;
+    uint32_t reserved_05c;
+    volatile dmac_lowpower_cfg0_reg_t lowpower_cfg0;
+    volatile dmac_lowpower_cfg1_reg_t lowpower_cfg1;
+    uint32_t reserved_068[38];
+    volatile dmac_channel_reg_t ch[4];
+} dw_gdma_dev_t;
+
+extern dw_gdma_dev_t DW_GDMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dw_gdma_dev_t) == 0x500, "Invalid size of dw_gdma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ecc_mult_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/ecc_mult_reg.h
new file mode 100644
index 0000000000..ac87d7b65a
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ecc_mult_reg.h
@@ -0,0 +1,210 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECC_MULT_INT_RAW_REG register
+ *  ECC raw interrupt status register
+ */
+#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
+/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
+#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_RAW_S  0
+
+/** ECC_MULT_INT_ST_REG register
+ *  ECC masked interrupt status register
+ */
+#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
+/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
+#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ST_S  0
+
+/** ECC_MULT_INT_ENA_REG register
+ *  ECC interrupt enable register
+ */
+#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
+/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
+#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ENA_S  0
+
+/** ECC_MULT_INT_CLR_REG register
+ *  ECC interrupt clear register
+ */
+#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
+/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
+#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_CLR_S  0
+
+/** ECC_MULT_CONF_REG register
+ *  ECC configuration register
+ */
+#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
+/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures whether to start calculation of ECC Accelerator. This bit will be
+ *  self-cleared after the calculation is done.
+ *  0: No effect
+ *  1: Start calculation of ECC Accelerator
+ */
+#define ECC_MULT_START    (BIT(0))
+#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
+#define ECC_MULT_START_V  0x00000001U
+#define ECC_MULT_START_S  0
+/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
+ *  Configures whether to reset ECC Accelerator.
+ *  0: No effect
+ *  1: Reset
+ */
+#define ECC_MULT_RESET    (BIT(1))
+#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
+#define ECC_MULT_RESET_V  0x00000001U
+#define ECC_MULT_RESET_S  1
+/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the key length mode bit of ECC Accelerator.
+ *  0: P-192
+ *  1: P-256
+ *  2: P-384
+ *  3: Reserved.
+ */
+#define ECC_MULT_KEY_LENGTH    0x00000003U
+#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
+#define ECC_MULT_KEY_LENGTH_V  0x00000003U
+#define ECC_MULT_KEY_LENGTH_S  2
+/** ECC_MULT_MOD_BASE : R/W; bitpos: [4]; default: 0;
+ *  Configures the mod base of mod operation, only valid in work_mode 8-11.
+ *  0: n(order of curve)
+ *  1: p(mod base of curve)
+ */
+#define ECC_MULT_MOD_BASE    (BIT(4))
+#define ECC_MULT_MOD_BASE_M  (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
+#define ECC_MULT_MOD_BASE_V  0x00000001U
+#define ECC_MULT_MOD_BASE_S  4
+/** ECC_MULT_WORK_MODE : R/W; bitpos: [8:5]; default: 0;
+ *  Configures the work mode of ECC Accelerator.
+ *  0: Point Multi mode
+ *  1: Reserved
+ *  2: Point Verif mode
+ *  3: Point Verif + Multi mode
+ *  4: Jacobian Point Multi mode
+ *  5: Reserved
+ *  6: Jacobian Point Verif mode
+ *  7: Point Verif + Jacobian Point Multi mode
+ *  8: Mod Add mode
+ *  9. Mod Sub mode
+ *  10: Mod Multi mode
+ *  11: Mod Div mode
+ */
+#define ECC_MULT_WORK_MODE    0x0000000FU
+#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
+#define ECC_MULT_WORK_MODE_V  0x0000000FU
+#define ECC_MULT_WORK_MODE_S  5
+/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [9]; default: 0;
+ *  Configures the security mode of ECC Accelerator.
+ *  0: no secure function enabled.
+ *  1: enable constant-time calculation in all point multiplication modes.
+ */
+#define ECC_MULT_SECURITY_MODE    (BIT(9))
+#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
+#define ECC_MULT_SECURITY_MODE_V  0x00000001U
+#define ECC_MULT_SECURITY_MODE_S  9
+/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
+ *  Represents the verification result of ECC Accelerator, valid only when calculation
+ *  is done.
+ */
+#define ECC_MULT_VERIFICATION_RESULT    (BIT(29))
+#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
+#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
+#define ECC_MULT_VERIFICATION_RESULT_S  29
+/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures whether to force on register clock gate.
+ *  0: No effect
+ *  1: Force on
+ */
+#define ECC_MULT_CLK_EN    (BIT(30))
+#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
+#define ECC_MULT_CLK_EN_V  0x00000001U
+#define ECC_MULT_CLK_EN_S  30
+/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  Configures whether to force on ECC memory clock gate.
+ *  0: No effect
+ *  1: Force on
+ */
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
+
+/** ECC_MULT_DATE_REG register
+ *  Version control register
+ */
+#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
+/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37781792;
+ *  ECC mult version control register
+ */
+#define ECC_MULT_DATE    0x0FFFFFFFU
+#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
+#define ECC_MULT_DATE_V  0x0FFFFFFFU
+#define ECC_MULT_DATE_S  0
+
+/** ECC_MULT_K_MEM register
+ *  The memory that stores k.
+ */
+#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
+#define ECC_MULT_K_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_PX_MEM register
+ *  The memory that stores Px.
+ */
+#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x130)
+#define ECC_MULT_PX_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_PY_MEM register
+ *  The memory that stores Py.
+ */
+#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x160)
+#define ECC_MULT_PY_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_QX_MEM register
+ *  The memory that stores Qx.
+ */
+#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x190)
+#define ECC_MULT_QX_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_QY_MEM register
+ *  The memory that stores Qy.
+ */
+#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x1c0)
+#define ECC_MULT_QY_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_QZ_MEM register
+ *  The memory that stores Qz.
+ */
+#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1f0)
+#define ECC_MULT_QZ_MEM_SIZE_BYTES 48
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ecc_mult_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/ecc_mult_struct.h
new file mode 100644
index 0000000000..8cb5a65ee6
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ecc_mult_struct.h
@@ -0,0 +1,192 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECC raw interrupt status register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECC masked interrupt status register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECC interrupt enable register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECC interrupt clear register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of conf register
+ *  ECC configuration register
+ */
+typedef union {
+    struct {
+        /** start : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether to start calculation of ECC Accelerator. This bit will be
+         *  self-cleared after the calculation is done.
+         *  0: No effect
+         *  1: Start calculation of ECC Accelerator
+         */
+        uint32_t start:1;
+        /** reset : WT; bitpos: [1]; default: 0;
+         *  Configures whether to reset ECC Accelerator.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t reset:1;
+        /** key_length : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the key length mode bit of ECC Accelerator.
+         *  0: P-192
+         *  1: P-256
+         *  2: P-384
+         *  3: Reserved.
+         */
+        uint32_t key_length:2;
+        /** mod_base : R/W; bitpos: [4]; default: 0;
+         *  Configures the mod base of mod operation, only valid in work_mode 8-11.
+         *  0: n(order of curve)
+         *  1: p(mod base of curve)
+         */
+        uint32_t mod_base:1;
+        /** work_mode : R/W; bitpos: [8:5]; default: 0;
+         *  Configures the work mode of ECC Accelerator.
+         *  0: Point Multi mode
+         *  1: Reserved
+         *  2: Point Verif mode
+         *  3: Point Verif + Multi mode
+         *  4: Jacobian Point Multi mode
+         *  5: Reserved
+         *  6: Jacobian Point Verif mode
+         *  7: Point Verif + Jacobian Point Multi mode
+         *  8: Mod Add mode
+         *  9. Mod Sub mode
+         *  10: Mod Multi mode
+         *  11: Mod Div mode
+         */
+        uint32_t work_mode:4;
+        /** security_mode : R/W; bitpos: [9]; default: 0;
+         *  Configures the security mode of ECC Accelerator.
+         *  0: no secure function enabled.
+         *  1: enable constant-time calculation in all point multiplication modes.
+         */
+        uint32_t security_mode:1;
+        uint32_t reserved_10:19;
+        /** verification_result : RO/SS; bitpos: [29]; default: 0;
+         *  Represents the verification result of ECC Accelerator, valid only when calculation
+         *  is done.
+         */
+        uint32_t verification_result:1;
+        /** clk_en : R/W; bitpos: [30]; default: 0;
+         *  Configures whether to force on register clock gate.
+         *  0: No effect
+         *  1: Force on
+         */
+        uint32_t clk_en:1;
+        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
+         *  Configures whether to force on ECC memory clock gate.
+         *  0: No effect
+         *  1: Force on
+         */
+        uint32_t mem_clock_gate_force_on:1;
+    };
+    uint32_t val;
+} ecc_mult_conf_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37781792;
+         *  ECC mult version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecc_mult_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile ecc_mult_int_raw_reg_t int_raw;
+    volatile ecc_mult_int_st_reg_t int_st;
+    volatile ecc_mult_int_ena_reg_t int_ena;
+    volatile ecc_mult_int_clr_reg_t int_clr;
+    volatile ecc_mult_conf_reg_t conf;
+    uint32_t reserved_020[55];
+    volatile ecc_mult_date_reg_t date;
+    volatile uint32_t k[12];
+    volatile uint32_t px[12];
+    volatile uint32_t py[12];
+    volatile uint32_t qx[12];
+    volatile uint32_t qy[12];
+    volatile uint32_t qz[12];
+} ecc_mult_dev_t;
+
+extern ecc_mult_dev_t ECC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecc_mult_dev_t) == 0x220, "Invalid size of ecc_mult_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ecdsa_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/ecdsa_eco5_reg.h
new file mode 100644
index 0000000000..179698edbb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ecdsa_eco5_reg.h
@@ -0,0 +1,359 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECDSA_CONF_REG register
+ *  ECDSA configure register
+ */
+#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
+/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+ *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+ */
+#define ECDSA_WORK_MODE    0x00000003U
+#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
+#define ECDSA_WORK_MODE_V  0x00000003U
+#define ECDSA_WORK_MODE_S  0
+/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0;
+ *  The ecc curve select bit of ECDSA Accelerator.  0: P-192. 1: P-256. 2: P-384.
+ */
+#define ECDSA_ECC_CURVE    0x00000003U
+#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
+#define ECDSA_ECC_CURVE_V  0x00000003U
+#define ECDSA_ECC_CURVE_S  2
+/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0;
+ *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+ *  written by software.
+ */
+#define ECDSA_SOFTWARE_SET_K    (BIT(4))
+#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
+#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_K_S  4
+/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0;
+ *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+ *  software.
+ */
+#define ECDSA_SOFTWARE_SET_Z    (BIT(5))
+#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
+#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_Z_S  5
+/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0;
+ *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+ *  deterministic derivation algorithm.
+ */
+#define ECDSA_DETERMINISTIC_K    (BIT(6))
+#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
+#define ECDSA_DETERMINISTIC_K_V  0x00000001U
+#define ECDSA_DETERMINISTIC_K_S  6
+
+/** ECDSA_CLK_REG register
+ *  ECDSA clock gate register
+ */
+#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
+/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
+#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
+#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
+#define ECDSA_CLK_GATE_FORCE_ON_S  0
+
+/** ECDSA_INT_RAW_REG register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
+/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_RAW    (BIT(0))
+#define ECDSA_PREP_DONE_INT_RAW_M  (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
+#define ECDSA_PREP_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_RAW_S  0
+/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_RAW    (BIT(1))
+#define ECDSA_PROC_DONE_INT_RAW_M  (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
+#define ECDSA_PROC_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_RAW_S  1
+/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_RAW    (BIT(2))
+#define ECDSA_POST_DONE_INT_RAW_M  (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
+#define ECDSA_POST_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_POST_DONE_INT_RAW_S  2
+/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
+#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_RAW_S  3
+
+/** ECDSA_INT_ST_REG register
+ *  ECDSA interrupt status register.
+ */
+#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
+/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_ST    (BIT(0))
+#define ECDSA_PREP_DONE_INT_ST_M  (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
+#define ECDSA_PREP_DONE_INT_ST_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_ST_S  0
+/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_ST    (BIT(1))
+#define ECDSA_PROC_DONE_INT_ST_M  (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
+#define ECDSA_PROC_DONE_INT_ST_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_ST_S  1
+/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_ST    (BIT(2))
+#define ECDSA_POST_DONE_INT_ST_M  (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
+#define ECDSA_POST_DONE_INT_ST_V  0x00000001U
+#define ECDSA_POST_DONE_INT_ST_S  2
+/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ST    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
+#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ST_S  3
+
+/** ECDSA_INT_ENA_REG register
+ *  ECDSA interrupt enable register.
+ */
+#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
+/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_ENA    (BIT(0))
+#define ECDSA_PREP_DONE_INT_ENA_M  (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
+#define ECDSA_PREP_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_ENA_S  0
+/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_ENA    (BIT(1))
+#define ECDSA_PROC_DONE_INT_ENA_M  (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
+#define ECDSA_PROC_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_ENA_S  1
+/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_ENA    (BIT(2))
+#define ECDSA_POST_DONE_INT_ENA_M  (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
+#define ECDSA_POST_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_POST_DONE_INT_ENA_S  2
+/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
+#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ENA_S  3
+
+/** ECDSA_INT_CLR_REG register
+ *  ECDSA interrupt clear register.
+ */
+#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
+/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_CLR    (BIT(0))
+#define ECDSA_PREP_DONE_INT_CLR_M  (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
+#define ECDSA_PREP_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_CLR_S  0
+/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_CLR    (BIT(1))
+#define ECDSA_PROC_DONE_INT_CLR_M  (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
+#define ECDSA_PROC_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_CLR_S  1
+/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_CLR    (BIT(2))
+#define ECDSA_POST_DONE_INT_CLR_M  (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
+#define ECDSA_POST_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_POST_DONE_INT_CLR_S  2
+/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
+#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_CLR_S  3
+
+/** ECDSA_START_REG register
+ *  ECDSA start register
+ */
+#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
+/** ECDSA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+ *  after configuration.
+ */
+#define ECDSA_START    (BIT(0))
+#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
+#define ECDSA_START_V  0x00000001U
+#define ECDSA_START_S  0
+/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_LOAD_DONE    (BIT(1))
+#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
+#define ECDSA_LOAD_DONE_V  0x00000001U
+#define ECDSA_LOAD_DONE_S  1
+/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
+ *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_GET_DONE    (BIT(2))
+#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
+#define ECDSA_GET_DONE_V  0x00000001U
+#define ECDSA_GET_DONE_S  2
+
+/** ECDSA_STATE_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
+/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
+ *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+ *  state.
+ */
+#define ECDSA_BUSY    0x00000003U
+#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
+#define ECDSA_BUSY_V  0x00000003U
+#define ECDSA_BUSY_S  0
+
+/** ECDSA_RESULT_REG register
+ *  ECDSA result register
+ */
+#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
+/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+ *  done.
+ */
+#define ECDSA_OPERATION_RESULT    (BIT(0))
+#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
+#define ECDSA_OPERATION_RESULT_V  0x00000001U
+#define ECDSA_OPERATION_RESULT_S  0
+
+/** ECDSA_DATE_REG register
+ *  Version control register
+ */
+#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
+/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984;
+ *  ECDSA version control register
+ */
+#define ECDSA_DATE    0x0FFFFFFFU
+#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
+#define ECDSA_DATE_V  0x0FFFFFFFU
+#define ECDSA_DATE_S  0
+
+/** ECDSA_SHA_MODE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
+/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
+ *  SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 7: invalid.
+ */
+#define ECDSA_SHA_MODE    0x00000007U
+#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
+#define ECDSA_SHA_MODE_V  0x00000007U
+#define ECDSA_SHA_MODE_S  0
+
+/** ECDSA_SHA_START_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
+/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_START    (BIT(0))
+#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
+#define ECDSA_SHA_START_V  0x00000001U
+#define ECDSA_SHA_START_S  0
+
+/** ECDSA_SHA_CONTINUE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
+/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_CONTINUE    (BIT(0))
+#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
+#define ECDSA_SHA_CONTINUE_V  0x00000001U
+#define ECDSA_SHA_CONTINUE_S  0
+
+/** ECDSA_SHA_BUSY_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
+/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
+ *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+ *  calculation. 0: SHA is idle.
+ */
+#define ECDSA_SHA_BUSY    (BIT(0))
+#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
+#define ECDSA_SHA_BUSY_V  0x00000001U
+#define ECDSA_SHA_BUSY_S  0
+
+/** ECDSA_MESSAGE_MEM register
+ *  The memory that stores message.
+ */
+#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
+#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64
+
+/** ECDSA_R_MEM register
+ *  The memory that stores r.
+ */
+#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0)
+#define ECDSA_R_MEM_SIZE_BYTES 48
+
+/** ECDSA_S_MEM register
+ *  The memory that stores s.
+ */
+#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410)
+#define ECDSA_S_MEM_SIZE_BYTES 48
+
+/** ECDSA_Z_MEM register
+ *  The memory that stores software written z.
+ */
+#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440)
+#define ECDSA_Z_MEM_SIZE_BYTES 48
+
+/** ECDSA_QAX_MEM register
+ *  The memory that stores x coordinates of QA or software written k.
+ */
+#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470)
+#define ECDSA_QAX_MEM_SIZE_BYTES 48
+
+/** ECDSA_QAY_MEM register
+ *  The memory that stores y coordinates of QA.
+ */
+#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0)
+#define ECDSA_QAY_MEM_SIZE_BYTES 48
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ecdsa_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/ecdsa_reg.h
new file mode 100644
index 0000000000..59b58185f8
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ecdsa_reg.h
@@ -0,0 +1,318 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECDSA_CONF_REG register
+ *  ECDSA configure register
+ */
+#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
+/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+ *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+ */
+#define ECDSA_WORK_MODE    0x00000003U
+#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
+#define ECDSA_WORK_MODE_V  0x00000003U
+#define ECDSA_WORK_MODE_S  0
+/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
+ *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
+ */
+#define ECDSA_ECC_CURVE    (BIT(2))
+#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
+#define ECDSA_ECC_CURVE_V  0x00000001U
+#define ECDSA_ECC_CURVE_S  2
+/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
+ *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+ *  written by software.
+ */
+#define ECDSA_SOFTWARE_SET_K    (BIT(3))
+#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
+#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_K_S  3
+/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
+ *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+ *  software.
+ */
+#define ECDSA_SOFTWARE_SET_Z    (BIT(4))
+#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
+#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_Z_S  4
+/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
+ *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+ *  deterministic derivation algorithm.
+ */
+#define ECDSA_DETERMINISTIC_K    (BIT(5))
+#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
+#define ECDSA_DETERMINISTIC_K_V  0x00000001U
+#define ECDSA_DETERMINISTIC_K_S  5
+/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
+ *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
+ */
+#define ECDSA_DETERMINISTIC_LOOP    0x0000FFFFU
+#define ECDSA_DETERMINISTIC_LOOP_M  (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
+#define ECDSA_DETERMINISTIC_LOOP_V  0x0000FFFFU
+#define ECDSA_DETERMINISTIC_LOOP_S  6
+
+/** ECDSA_CLK_REG register
+ *  ECDSA clock gate register
+ */
+#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
+/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
+#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
+#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
+#define ECDSA_CLK_GATE_FORCE_ON_S  0
+
+/** ECDSA_INT_RAW_REG register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
+/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_RAW    (BIT(0))
+#define ECDSA_CALC_DONE_INT_RAW_M  (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
+#define ECDSA_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_RAW_S  0
+/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
+#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_RAW_S  1
+
+/** ECDSA_INT_ST_REG register
+ *  ECDSA interrupt status register.
+ */
+#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
+/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_ST    (BIT(0))
+#define ECDSA_CALC_DONE_INT_ST_M  (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
+#define ECDSA_CALC_DONE_INT_ST_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_ST_S  0
+/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ST    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
+#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ST_S  1
+
+/** ECDSA_INT_ENA_REG register
+ *  ECDSA interrupt enable register.
+ */
+#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
+/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_ENA    (BIT(0))
+#define ECDSA_CALC_DONE_INT_ENA_M  (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
+#define ECDSA_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_ENA_S  0
+/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
+#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ENA_S  1
+
+/** ECDSA_INT_CLR_REG register
+ *  ECDSA interrupt clear register.
+ */
+#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
+/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_CLR    (BIT(0))
+#define ECDSA_CALC_DONE_INT_CLR_M  (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
+#define ECDSA_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_CLR_S  0
+/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
+#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_CLR_S  1
+
+/** ECDSA_START_REG register
+ *  ECDSA start register
+ */
+#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
+/** ECDSA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+ *  after configuration.
+ */
+#define ECDSA_START    (BIT(0))
+#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
+#define ECDSA_START_V  0x00000001U
+#define ECDSA_START_S  0
+/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_LOAD_DONE    (BIT(1))
+#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
+#define ECDSA_LOAD_DONE_V  0x00000001U
+#define ECDSA_LOAD_DONE_S  1
+/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
+ *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_GET_DONE    (BIT(2))
+#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
+#define ECDSA_GET_DONE_V  0x00000001U
+#define ECDSA_GET_DONE_S  2
+
+/** ECDSA_STATE_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
+/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
+ *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+ *  state.
+ */
+#define ECDSA_BUSY    0x00000003U
+#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
+#define ECDSA_BUSY_V  0x00000003U
+#define ECDSA_BUSY_S  0
+
+/** ECDSA_RESULT_REG register
+ *  ECDSA result register
+ */
+#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
+/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+ *  done.
+ */
+#define ECDSA_OPERATION_RESULT    (BIT(0))
+#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
+#define ECDSA_OPERATION_RESULT_V  0x00000001U
+#define ECDSA_OPERATION_RESULT_S  0
+/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
+ *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
+ *  curve order, then actually taken k = k mod n.
+ */
+#define ECDSA_K_VALUE_WARNING    (BIT(1))
+#define ECDSA_K_VALUE_WARNING_M  (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
+#define ECDSA_K_VALUE_WARNING_V  0x00000001U
+#define ECDSA_K_VALUE_WARNING_S  1
+
+/** ECDSA_DATE_REG register
+ *  Version control register
+ */
+#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
+/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
+ *  ECDSA version control register
+ */
+#define ECDSA_DATE    0x0FFFFFFFU
+#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
+#define ECDSA_DATE_V  0x0FFFFFFFU
+#define ECDSA_DATE_S  0
+
+/** ECDSA_SHA_MODE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
+/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
+ *  Others: invalid.
+ */
+#define ECDSA_SHA_MODE    0x00000007U
+#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
+#define ECDSA_SHA_MODE_V  0x00000007U
+#define ECDSA_SHA_MODE_S  0
+
+/** ECDSA_SHA_START_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
+/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_START    (BIT(0))
+#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
+#define ECDSA_SHA_START_V  0x00000001U
+#define ECDSA_SHA_START_S  0
+
+/** ECDSA_SHA_CONTINUE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
+/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_CONTINUE    (BIT(0))
+#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
+#define ECDSA_SHA_CONTINUE_V  0x00000001U
+#define ECDSA_SHA_CONTINUE_S  0
+
+/** ECDSA_SHA_BUSY_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
+/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
+ *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+ *  calculation. 0: SHA is idle.
+ */
+#define ECDSA_SHA_BUSY    (BIT(0))
+#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
+#define ECDSA_SHA_BUSY_V  0x00000001U
+#define ECDSA_SHA_BUSY_S  0
+
+/** ECDSA_MESSAGE_MEM register
+ *  The memory that stores message.
+ */
+#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
+#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
+
+/** ECDSA_R_MEM register
+ *  The memory that stores r.
+ */
+#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
+#define ECDSA_R_MEM_SIZE_BYTES 32
+
+/** ECDSA_S_MEM register
+ *  The memory that stores s.
+ */
+#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
+#define ECDSA_S_MEM_SIZE_BYTES 32
+
+/** ECDSA_Z_MEM register
+ *  The memory that stores software written z.
+ */
+#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
+#define ECDSA_Z_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAX_MEM register
+ *  The memory that stores x coordinates of QA or software written k.
+ */
+#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
+#define ECDSA_QAX_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAY_MEM register
+ *  The memory that stores y coordinates of QA.
+ */
+#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
+#define ECDSA_QAY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/ecdsa_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/ecdsa_struct.h
new file mode 100644
index 0000000000..5f820a7ee2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/ecdsa_struct.h
@@ -0,0 +1,347 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Data Memory */
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  ECDSA configure register
+ */
+typedef union {
+    struct {
+        /** work_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+         *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+         */
+        uint32_t work_mode:2;
+        /** ecc_curve : R/W; bitpos: [3:2]; default: 0;
+         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192. 1: P-256. 2: P-384.
+         */
+        uint32_t ecc_curve:2;
+        /** software_set_k : R/W; bitpos: [4]; default: 0;
+         *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+         *  written by software.
+         */
+        uint32_t software_set_k:1;
+        /** software_set_z : R/W; bitpos: [5]; default: 0;
+         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+         *  software.
+         */
+        uint32_t software_set_z:1;
+        /** deterministic_k : R/W; bitpos: [6]; default: 0;
+         *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+         *  deterministic derivation algorithm.
+         */
+        uint32_t deterministic_k:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ecdsa_conf_reg_t;
+
+/** Type of start register
+ *  ECDSA start register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+         *  after configuration.
+         */
+        uint32_t start:1;
+        /** load_done : WT; bitpos: [1]; default: 0;
+         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t load_done:1;
+        /** get_done : WT; bitpos: [2]; default: 0;
+         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t get_done:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_start_reg_t;
+
+
+/** Group: Clock and reset registers */
+/** Type of clk register
+ *  ECDSA clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_gate_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_raw:1;
+        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_raw:1;
+        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_raw:1;
+        /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECDSA interrupt status register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_st:1;
+        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_st:1;
+        /** post_done_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_st:1;
+        /** sha_release_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECDSA interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_ena:1;
+        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_ena:1;
+        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_ena:1;
+        /** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECDSA interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_clr:1;
+        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_clr:1;
+        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_clr:1;
+        /** sha_release_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_clr_reg_t;
+
+
+/** Group: Status registers */
+/** Type of state register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** busy : RO; bitpos: [1:0]; default: 0;
+         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+         *  state.
+         */
+        uint32_t busy:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of result register
+ *  ECDSA result register
+ */
+typedef union {
+    struct {
+        /** operation_result : RO/SS; bitpos: [0]; default: 0;
+         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+         *  done.
+         */
+        uint32_t operation_result:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_result_reg_t;
+
+
+/** Group: SHA register */
+/** Type of sha_mode register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_mode : R/W; bitpos: [2:0]; default: 0;
+         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
+         *  SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 7: invalid.
+         */
+        uint32_t sha_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_sha_mode_reg_t;
+
+/** Type of sha_start register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_start_reg_t;
+
+/** Type of sha_continue register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_continue : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_continue_reg_t;
+
+/** Type of sha_busy register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** sha_busy : RO; bitpos: [0]; default: 0;
+         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+         *  calculation. 0: SHA is idle.
+         */
+        uint32_t sha_busy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_busy_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37785984;
+         *  ECDSA version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecdsa_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile ecdsa_conf_reg_t conf;
+    volatile ecdsa_clk_reg_t clk;
+    volatile ecdsa_int_raw_reg_t int_raw;
+    volatile ecdsa_int_st_reg_t int_st;
+    volatile ecdsa_int_ena_reg_t int_ena;
+    volatile ecdsa_int_clr_reg_t int_clr;
+    volatile ecdsa_start_reg_t start;
+    volatile ecdsa_state_reg_t state;
+    volatile ecdsa_result_reg_t result;
+    uint32_t reserved_028[53];
+    volatile ecdsa_date_reg_t date;
+    uint32_t reserved_100[64];
+    volatile ecdsa_sha_mode_reg_t sha_mode;
+    uint32_t reserved_204[3];
+    volatile ecdsa_sha_start_reg_t sha_start;
+    volatile ecdsa_sha_continue_reg_t sha_continue;
+    volatile ecdsa_sha_busy_reg_t sha_busy;
+    uint32_t reserved_21c[25];
+    volatile uint32_t message[16];
+    uint32_t reserved_2c0[72];
+    volatile uint32_t r[12];
+    volatile uint32_t s[12];
+    volatile uint32_t z[12];
+    volatile uint32_t qax[12];
+    volatile uint32_t qay[12];
+} ecdsa_dev_t;
+
+extern ecdsa_dev_t ECDSA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/efuse_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/efuse_eco5_struct.h
new file mode 100644
index 0000000000..e24109ae08
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/efuse_eco5_struct.h
@@ -0,0 +1,3689 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: program_data registers */
+/** Type of pgm_datan register
+ *  Represents pgm_datan
+ */
+typedef union {
+    struct {
+        /** pgm_data_n : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the nth 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_n:32;
+    };
+    uint32_t val;
+} efuse_pgm_datan_reg_t;
+
+/** Type of pgm_check_valuen register
+ *  Represents pgm_check_valuen
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the nth RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_n:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_valuen_reg_t;
+
+
+/** Group: block0 registers */
+/** Type of rd_wr_dis register
+ *  Represents rd_wr_dis
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled.  For
+         *  mapping between the bits of this field and the eFuse memory bits, please refer to
+         *  Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.
+         *  1: Disabled
+         *  0: Enabled
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t rd_dis:7;
+        /** recovery_bootloader_flash_sector_0_1 : RO; bitpos: [8:7]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_0_1:2;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Set this bit to disable function of usb switch to jtag in module of usb device.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** recovery_bootloader_flash_sector_2_2 : RO; bitpos: [10]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_2_2:1;
+        uint32_t reserved_11:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Set this bit to disable the function that forces chip into download mode.
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+         *  boot_mode_download.
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Set this bit to disable TWAI function.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0.
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Set odd bits to disable JTAG in the soft way. JTAG can be enabled in HMAC module.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable flash manual encrypt function (except in SPI boot mode).
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** recovery_bootloader_flash_sector_3_6 : RO; bitpos: [24:21]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_3_6:4;
+        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
+         *  0: intphy(gpio24/25) <---> usb_device
+         *  1: intphy(26/27) <---> usb_otg11.1: intphy(gpio26/27) <---> usb_device
+         *  1: intphy(24/25) <---> usb_otg11.
+         */
+        uint32_t usb_phy_sel:1;
+        /** huk_gen_state : RO; bitpos: [30:26]; default: 0;
+         *  Set the bits to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t huk_gen_state:5;
+        /** recovery_bootloader_flash_sector_7_7 : RO; bitpos: [31]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_7_7:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** recovery_bootloader_flash_sector_8_10 : RO; bitpos: [2:0]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_8_10:3;
+        /** recovery_bootloader_flash_sector_11_11 : RO; bitpos: [3]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector_11_11:1;
+        /** km_rnd_switch_cycle : RO; bitpos: [4]; default: 0;
+         *  Set the bits to control key manager random number switch cycle. 0: control by
+         *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+         */
+        uint32_t km_rnd_switch_cycle:1;
+        /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
+         *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
+         *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
+         *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
+         *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t km_deploy_only_once:4;
+        /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
+         *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
+         *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
+         *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t force_use_key_manager_key:4;
+        /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable software written init key, and force use efuse_init_key.
+         */
+        uint32_t force_disable_sw_init_key:1;
+        /** km_xts_key_length_256 : RO; bitpos: [14]; default: 0;
+         *  Set this bit to config flash encryption xts-512 key, else use xts-256 key when
+         *  using the key manager
+         */
+        uint32_t km_xts_key_length_256:1;
+        /** ecc_force_const_time : RO; bitpos: [15]; default: 0;
+         *  Set this bit to permanently turn on ECC const-time mode.
+         */
+        uint32_t ecc_force_const_time:1;
+        uint32_t reserved_16:1;
+        /** wdt_delay_sel : RO; bitpos: [17]; default: 0;
+         *  Select lp wdt timeout threshold at startup = initial timeout value * (2 ^
+         *  (EFUSE_WDT_DELAY_SEL + 1))
+         */
+        uint32_t wdt_delay_sel:1;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+         *  number of 1: disable.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Set this bit to enable revoking first secure boot key.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Set this bit to enable revoking second secure boot key.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Set this bit to enable revoking third secure boot key.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
+         *  Configures the clock random divide mode to determine the dpa secure level
+         */
+        uint32_t sec_dpa_level:2;
+        uint32_t reserved_18:1;
+        /** xts_dpa_clk_enable : RO; bitpos: [19]; default: 0;
+         *  Sets this bit to enable xts clock anti-dpa attack function.
+         */
+        uint32_t xts_dpa_clk_enable:1;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Set this bit to enable secure boot.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Set this bit to enable revoking aggressive secure boot.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** km_deploy_only_once_h : RO; bitpos: [22]; default: 0;
+         *  EFUSE_KM_DEPLOY_ONLY_ONCE and EFUSE_KM_DEPLOY_ONLY_ONCE_H together form one field:
+         *  {EFUSE_KM_DEPLOY_ONLY_ONCE_H, EFUSE_KM_DEPLOY_ONLY_ONCE[3:0]}. Set each bit to
+         *  control whether corresponding key can only be deployed once. 1 is true, 0 is false.
+         *  bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t km_deploy_only_once_h:1;
+        /** force_use_key_manager_key_h : RO; bitpos: [23]; default: 0;
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY and EFUSE_FORCE_USE_KEY_MANAGER_KEY_H together form
+         *  one field: {EFUSE_FORCE_USE_KEY_MANAGER_KEY_H,
+         *  EFUSE_FORCE_USE_KEY_MANAGER_KEY[3:0]}. Set each bit to control whether
+         *  corresponding key must come from key manager. 1 is true, 0 is false. bit 0: ecsda,
+         *  bit 1: xts, bit2: hmac, bit3: ds, bit4:psram
+         */
+        uint32_t force_use_key_manager_key_h:1;
+        uint32_t reserved_24:2;
+        /** flash_ecc_en : RO; bitpos: [26]; default: 0;
+         *  Set this bit to enable ECC for flash boot.
+         */
+        uint32_t flash_ecc_en:1;
+        /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
+         *  Set this bit to disable download via USB-OTG.
+         */
+        uint32_t dis_usb_otg_download_mode:1;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Configures flash waiting time after power-up, in unit of ms. When the value less
+         *  than 15, the waiting time is the configurable value. Otherwise, the waiting time is
+         *  30.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Set this bit to disable direct boot mode
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Set this bit to disable USB-Serial-JTAG print during rom boot.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** lock_km_key : RO; bitpos: [3]; default: 0;
+         *  set this bit to lock the key manager key after deploy
+         */
+        uint32_t lock_km_key:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Set this bit to disable the USB-Serial-JTAG download function.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Set this bit to enable security download mode.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Set the type of UART printing, 00: force enable printing, 01: enable printing when
+         *  GPIO8 is reset at low level, 10: enable printing when GPIO8 is reset at high level,
+         *  11: force disable printing
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [8]; default: 0;
+         *  Set this bit to force ROM code to send a resume command during SPI boot.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [24:9]; default: 0;
+         *  Secure version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
+         *  Represents whether secure boot do fast verification on wake is disabled. 0: enabled
+         *  1: disabled
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad : RO; bitpos: [26]; default: 0;
+         *  Set bits to enable hysteresis function of PAD0~27
+         */
+        uint32_t hys_en_pad:1;
+        /** key_purpose_0_h : RO; bitpos: [27]; default: 0;
+         *  Purpose of Key0. The 5-th bit.
+         */
+        uint32_t key_purpose_0_h:1;
+        /** key_purpose_1_h : RO; bitpos: [28]; default: 0;
+         *  Purpose of Key1. The 5-th bit.
+         */
+        uint32_t key_purpose_1_h:1;
+        /** key_purpose_2_h : RO; bitpos: [29]; default: 0;
+         *  Purpose of Key2. The 5-th bit.
+         */
+        uint32_t key_purpose_2_h:1;
+        /** key_purpose_3_h : RO; bitpos: [30]; default: 0;
+         *  Purpose of Key3. The 5-th bit.
+         */
+        uint32_t key_purpose_3_h:1;
+        /** key_purpose_4_h : RO; bitpos: [31]; default: 0;
+         *  Purpose of Key4. The 5-th bit.
+         */
+        uint32_t key_purpose_4_h:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
+         *  Output LDO VO0 tieh source select. 0: 1'b1 1: sdmmc1 2: reg 3:sdmmc0
+         */
+        uint32_t pxa0_tieh_sel_0:2;
+        /** pvt_glitch_en : RO; bitpos: [2]; default: 0;
+         *  Represents whether to enable PVT power glitch monitor function.
+         *  1:Enable.
+         *  0:Disable
+         */
+        uint32_t pvt_glitch_en:1;
+        uint32_t reserved_3:1;
+        /** key_purpose_5_h : RO; bitpos: [4]; default: 0;
+         *  Purpose of Key5. The 5-th bit.
+         */
+        uint32_t key_purpose_5_h:1;
+        uint32_t reserved_5:2;
+        /** km_disable_deploy_mode_h : RO; bitpos: [7]; default: 0;
+         *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
+         *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
+         *  each bit to control whether corresponding key's deploy mode of new value deployment
+         *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
+         *  bit4:psram
+         */
+        uint32_t km_disable_deploy_mode_h:1;
+        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
+         *  EFUSE_KM_DISABLE_DEPLOY_MODE and EFUSE_KM_DISABLE_DEPLOY_MODE_H together form one
+         *  field: {EFUSE_KM_DISABLE_DEPLOY_MODE_H, EFUSE_KM_DISABLE_DEPLOY_MODE[3:0]}. Set
+         *  each bit to control whether corresponding key's deploy mode of new value deployment
+         *  is disabled. 1 is true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds,
+         *  bit4:psram
+         */
+        uint32_t km_disable_deploy_mode:4;
+        uint32_t reserved_12:4;
+        /** xts_dpa_pseudo_level : RO; bitpos: [17:16]; default: 0;
+         *  Sets this bit to control the xts pseudo-round anti-dpa attack function. 0:
+         *  controlled by register. 1-3: the higher the value is, the more pseudo-rounds are
+         *  inserted to the xts-aes calculation
+         */
+        uint32_t xts_dpa_pseudo_level:2;
+        /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
+         *  HP system power source select. 0:LDO  1: DCDC
+         */
+        uint32_t hp_pwr_src_sel:1;
+        /** secure_boot_sha384_en : RO; bitpos: [19]; default: 0;
+         *  Represents whether secure boot using SHA-384 is enabled. 0: disable 1: enable
+         */
+        uint32_t secure_boot_sha384_en:1;
+        /** dis_wdt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable watch dog.
+         */
+        uint32_t dis_wdt:1;
+        /** dis_swd : RO; bitpos: [21]; default: 0;
+         *  Set bit to disable super-watchdog
+         */
+        uint32_t dis_swd:1;
+        /** pvt_glitch_mode : RO; bitpos: [23:22]; default: 0;
+         *  Use to configure glitch mode
+         */
+        uint32_t pvt_glitch_mode:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+
+/** Group: block1 registers */
+/** Type of rd_mac_sys0 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents MAC address. Low 32-bit.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys0_reg_t;
+
+/** Type of rd_mac_sys1 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Represents MAC address. High 16-bit.
+         */
+        uint32_t mac_1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys1_reg_t;
+
+/** Type of rd_mac_sys3 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
+         *  Represents the first 14-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_0:14;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys3_reg_t;
+
+/** Type of rd_mac_sys4 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the second 32-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_1:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys4_reg_t;
+
+/** Type of rd_mac_sys5 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the third 32-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_2:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys5_reg_t;
+
+
+/** Group: block2 registers */
+/** Type of rd_sys_part1_datan register
+ *  Represents rd_sys_part1_datan
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of first part of system data.
+         */
+        uint32_t sys_data_part1_n:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_datan_reg_t;
+
+
+/** Group: block3 registers */
+/** Type of rd_usr_datan register
+ *  Represents rd_usr_datan
+ */
+typedef union {
+    struct {
+        /** usr_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_datan_reg_t;
+
+
+/** Group: block4 registers */
+/** Type of rd_key0_datan register
+ *  Represents rd_key0_datan
+ */
+typedef union {
+    struct {
+        /** key0_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_datan_reg_t;
+
+
+/** Group: block5 registers */
+/** Type of rd_key1_datan register
+ *  Represents rd_key1_datan
+ */
+typedef union {
+    struct {
+        /** key1_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_datan_reg_t;
+
+
+/** Group: block6 registers */
+/** Type of rd_key2_datan register
+ *  Represents rd_key2_datan
+ */
+typedef union {
+    struct {
+        /** key2_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_datan_reg_t;
+
+
+/** Group: block7 registers */
+/** Type of rd_key3_datan register
+ *  Represents rd_key3_datan
+ */
+typedef union {
+    struct {
+        /** key3_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_datan_reg_t;
+
+
+/** Group: block8 registers */
+/** Type of rd_key4_datan register
+ *  Represents rd_key4_datan
+ */
+typedef union {
+    struct {
+        /** key4_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_datan_reg_t;
+
+
+/** Group: block9 registers */
+/** Type of rd_key5_datan register
+ *  Represents rd_key5_datan
+ */
+typedef union {
+    struct {
+        /** key5_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_datan_reg_t;
+
+
+/** Group: block10 registers */
+/** Type of rd_sys_part2_data0 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the first 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the first 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the second 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the third 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the fourth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the fifth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** usb_device_exchg_pins : RO; bitpos: [4]; default: 0;
+         *  Enable usb device exchange pins of D+ and D-.
+         */
+        uint32_t usb_device_exchg_pins:1;
+        /** usb_otg11_exchg_pins : RO; bitpos: [5]; default: 0;
+         *  Enable usb otg11 exchange pins of D+ and D-.
+         */
+        uint32_t usb_otg11_exchg_pins:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+
+/** Group: block0 error report registers */
+/** Type of rd_repeat_data_err0 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Represents the programming error of EFUSE_RD_DIS
+         */
+        uint32_t rd_dis_err:7;
+        /** recovery_bootloader_flash_sector_0_1_err : RO; bitpos: [8:7]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1
+         */
+        uint32_t recovery_bootloader_flash_sector_0_1_err:2;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_JTAG
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** recovery_bootloader_flash_sector_2_2_err : RO; bitpos: [10]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_2_2
+         */
+        uint32_t recovery_bootloader_flash_sector_2_2_err:1;
+        uint32_t reserved_11:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_TWAI
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** recovery_bootloader_flash_sector_3_6_err : RO; bitpos: [24:21]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_3_6
+         */
+        uint32_t recovery_bootloader_flash_sector_3_6_err:4;
+        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
+         *  Represents the programming error of EFUSE_USB_PHY_SEL
+         */
+        uint32_t usb_phy_sel_err:1;
+        /** huk_gen_state_err : RO; bitpos: [30:26]; default: 0;
+         *  Represents the programming error of EFUSE_HUK_GEN_STATE
+         */
+        uint32_t huk_gen_state_err:5;
+        /** recovery_bootloader_flash_sector_7_7_err : RO; bitpos: [31]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_7_7
+         */
+        uint32_t recovery_bootloader_flash_sector_7_7_err:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err0_reg_t;
+
+/** Type of rd_repeat_data_err1 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** recovery_bootloader_flash_sector_8_10_err : RO; bitpos: [2:0]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_8_10
+         */
+        uint32_t recovery_bootloader_flash_sector_8_10_err:3;
+        /** recovery_bootloader_flash_sector_11_11_err : RO; bitpos: [3]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_11_11
+         */
+        uint32_t recovery_bootloader_flash_sector_11_11_err:1;
+        /** km_rnd_switch_cycle_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
+         */
+        uint32_t km_rnd_switch_cycle_err:1;
+        /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
+         */
+        uint32_t km_deploy_only_once_err:4;
+        /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
+         */
+        uint32_t force_use_key_manager_key_err:4;
+        /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
+         */
+        uint32_t force_disable_sw_init_key_err:1;
+        /** km_xts_key_length_256_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
+         */
+        uint32_t km_xts_key_length_256_err:1;
+        /** ecc_force_const_time_err : RO; bitpos: [15]; default: 0;
+         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
+         */
+        uint32_t ecc_force_const_time_err:1;
+        uint32_t reserved_16:1;
+        /** wdt_delay_sel_err : RO; bitpos: [17]; default: 0;
+         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
+         */
+        uint32_t wdt_delay_sel_err:1;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err1_reg_t;
+
+/** Type of rd_repeat_data_err2 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_5
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
+         */
+        uint32_t sec_dpa_level_err:2;
+        uint32_t reserved_18:1;
+        /** xts_dpa_clk_enable_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
+         */
+        uint32_t xts_dpa_clk_enable_err:1;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        /** km_deploy_only_once_h_err : RO; bitpos: [22]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE_H
+         */
+        uint32_t km_deploy_only_once_h_err:1;
+        /** force_use_key_manager_key_h_err : RO; bitpos: [23]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY_H
+         */
+        uint32_t force_use_key_manager_key_h_err:1;
+        uint32_t reserved_24:2;
+        /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_FLASH_ECC_EN
+         */
+        uint32_t flash_ecc_en_err:1;
+        /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE
+         */
+        uint32_t dis_usb_otg_download_mode_err:1;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Represents the programming error of EFUSE_FLASH_TPUW
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err2_reg_t;
+
+/** Type of rd_repeat_data_err3 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
+         */
+        uint32_t dis_usb_serial_jtag_rom_print_err:1;
+        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
+         *  Represents the programming error of EFUSE_LOCK_KM_KEY
+         */
+        uint32_t lock_km_key_err:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_VERSION
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_HYS_EN_PAD
+         */
+        uint32_t hys_en_pad_err:1;
+        /** key_purpose_0_h_err : RO; bitpos: [27]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_0_H
+         */
+        uint32_t key_purpose_0_h_err:1;
+        /** key_purpose_1_h_err : RO; bitpos: [28]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_1_H
+         */
+        uint32_t key_purpose_1_h_err:1;
+        /** key_purpose_2_h_err : RO; bitpos: [29]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_2_H
+         */
+        uint32_t key_purpose_2_h_err:1;
+        /** key_purpose_3_h_err : RO; bitpos: [30]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_3_H
+         */
+        uint32_t key_purpose_3_h_err:1;
+        /** key_purpose_4_h_err : RO; bitpos: [31]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_4_H
+         */
+        uint32_t key_purpose_4_h_err:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err3_reg_t;
+
+/** Type of rd_repeat_data_err4 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
+         *  Represents the programming error of 0PXA_TIEH_SEL_0
+         */
+        uint32_t pxa0_tieh_sel_0_err:2;
+        /** pvt_glitch_en_err : RO; bitpos: [2]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_GLITCH_EN
+         */
+        uint32_t pvt_glitch_en_err:1;
+        uint32_t reserved_3:1;
+        /** key_purpose_5_h_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_5_H
+         */
+        uint32_t key_purpose_5_h_err:1;
+        uint32_t reserved_5:2;
+        /** km_disable_deploy_mode_h_err : RO; bitpos: [7]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE_H
+         */
+        uint32_t km_disable_deploy_mode_h_err:1;
+        /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
+         */
+        uint32_t km_disable_deploy_mode_err:4;
+        uint32_t reserved_12:4;
+        /** xts_dpa_pseudo_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
+         */
+        uint32_t xts_dpa_pseudo_level_err:2;
+        /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
+         *  Represents the programming error of EFUSE_HP_PWR_SRC_SEL
+         */
+        uint32_t hp_pwr_src_sel_err:1;
+        /** secure_boot_sha384_en_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN
+         */
+        uint32_t secure_boot_sha384_en_err:1;
+        /** dis_wdt_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_WDT
+         */
+        uint32_t dis_wdt_err:1;
+        /** dis_swd_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_SWD
+         */
+        uint32_t dis_swd_err:1;
+        /** pvt_glitch_mode_err : RO; bitpos: [23:22]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_GLITCH_MODE
+         */
+        uint32_t pvt_glitch_mode_err:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err4_reg_t;
+
+
+/** Group: EFUSE ECDSA Configure Registers */
+/** Type of ecdsa register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0;
+         *  Configures which block to use for ECDSA P192 key output.
+         */
+        uint32_t cfg_ecdsa_p192_blk:4;
+        /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0;
+         *  Configures which block to use for ECDSA P256 key output.
+         */
+        uint32_t cfg_ecdsa_p256_blk:4;
+        /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0;
+         *  Configures which block to use for ECDSA P384 key low part output.
+         */
+        uint32_t cfg_ecdsa_p384_l_blk:4;
+        /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0;
+         *  Configures which block to use for ECDSA P256 key high part output.
+         */
+        uint32_t cfg_ecdsa_p384_h_blk:4;
+        /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0;
+         *  Represents which block is used for ECDSA P192 key output.
+         */
+        uint32_t cur_ecdsa_p192_blk:4;
+        /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0;
+         *  Represents which block is used for ECDSA P256 key output.
+         */
+        uint32_t cur_ecdsa_p256_blk:4;
+        /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0;
+         *  Represents which block is used for ECDSA P384 key low part output.
+         */
+        uint32_t cur_ecdsa_p384_l_blk:4;
+        /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0;
+         *  Represents which block is used for ECDSA P384 key high part output.
+         */
+        uint32_t cur_ecdsa_p384_h_blk:4;
+    };
+    uint32_t val;
+} efuse_ecdsa_reg_t;
+
+
+/** Group: RS block error report registers */
+/** Type of rd_rs_data_err0 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_mac_sys
+         */
+        uint32_t rd_mac_sys_err_num:3;
+        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_mac_sys is reliable
+         *  1: Means that programming rd_mac_sys failed and the number of error bytes is over 6.
+         */
+        uint32_t rd_mac_sys_fail:1;
+        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_sys_part1_data
+         */
+        uint32_t rd_sys_part1_data_err_num:3;
+        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_sys_part1_data is reliable
+         *  1: Means that programming rd_sys_part1_data failed and the number of error bytes is
+         *  over 6.
+         */
+        uint32_t rd_sys_part1_data_fail:1;
+        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_usr_data
+         */
+        uint32_t rd_usr_data_err_num:3;
+        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_usr_data is reliable
+         *  1: Means that programming rd_usr_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_usr_data_fail:1;
+        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key0_data
+         */
+        uint32_t rd_key0_data_err_num:3;
+        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key0_data is reliable
+         *  1: Means that programming rd_key0_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key0_data_fail:1;
+        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key1_data
+         */
+        uint32_t rd_key1_data_err_num:3;
+        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key1_data is reliable
+         *  1: Means that programming rd_key1_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key1_data_fail:1;
+        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key2_data
+         */
+        uint32_t rd_key2_data_err_num:3;
+        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key2_data is reliable
+         *  1: Means that programming rd_key2_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key2_data_fail:1;
+        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key3_data
+         */
+        uint32_t rd_key3_data_err_num:3;
+        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key3_data is reliable
+         *  1: Means that programming rd_key3_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key3_data_fail:1;
+        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key4_data
+         */
+        uint32_t rd_key4_data_err_num:3;
+        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key4_data is reliable
+         *  1: Means that programming rd_key4_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key4_data_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err0_reg_t;
+
+/** Type of rd_rs_data_err1 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key5_data
+         */
+        uint32_t rd_key5_data_err_num:3;
+        /** rd_key5_data_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key5_data is reliable
+         *  1: Means that programming rd_key5_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key5_data_fail:1;
+        /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_sys_part2_data
+         */
+        uint32_t rd_sys_part2_data_err_num:3;
+        /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_sys_part2_data is reliable
+         *  1: Means that programming rd_sys_part2_data failed and the number of error bytes is
+         *  over 6.
+         */
+        uint32_t rd_sys_part2_data_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err1_reg_t;
+
+
+/** Group: ******** Registers */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        uint32_t reserved_4:6;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 160;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: EFUSE Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38805904;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
+/** Type of apb2otp_wr_dis register
+ *  eFuse apb2otp block0 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 write disable data.
+         */
+        uint32_t apb2otp_block0_wr_dis:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_wr_dis_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
+/** Type of apb2otp_blk0_backup1_w1 register
+ *  eFuse apb2otp block0 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word1 data.
+         */
+        uint32_t apb2otp_block0_backup1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
+/** Type of apb2otp_blk0_backup1_w2 register
+ *  eFuse apb2otp block0 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word2 data.
+         */
+        uint32_t apb2otp_block0_backup1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
+/** Type of apb2otp_blk0_backup1_w3 register
+ *  eFuse apb2otp block0 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word3 data.
+         */
+        uint32_t apb2otp_block0_backup1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
+/** Type of apb2otp_blk0_backup1_w4 register
+ *  eFuse apb2otp block0 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word4 data.
+         */
+        uint32_t apb2otp_block0_backup1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
+/** Type of apb2otp_blk0_backup1_w5 register
+ *  eFuse apb2otp block0 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word5 data.
+         */
+        uint32_t apb2otp_block0_backup1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
+/** Type of apb2otp_blk0_backup2_w1 register
+ *  eFuse apb2otp block0 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word1 data.
+         */
+        uint32_t apb2otp_block0_backup2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
+/** Type of apb2otp_blk0_backup2_w2 register
+ *  eFuse apb2otp block0 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word2 data.
+         */
+        uint32_t apb2otp_block0_backup2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
+/** Type of apb2otp_blk0_backup2_w3 register
+ *  eFuse apb2otp block0 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word3 data.
+         */
+        uint32_t apb2otp_block0_backup2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
+/** Type of apb2otp_blk0_backup2_w4 register
+ *  eFuse apb2otp block0 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word4 data.
+         */
+        uint32_t apb2otp_block0_backup2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
+/** Type of apb2otp_blk0_backup2_w5 register
+ *  eFuse apb2otp block0 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word5 data.
+         */
+        uint32_t apb2otp_block0_backup2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
+/** Type of apb2otp_blk0_backup3_w1 register
+ *  eFuse apb2otp block0 data register12.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word1 data.
+         */
+        uint32_t apb2otp_block0_backup3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
+/** Type of apb2otp_blk0_backup3_w2 register
+ *  eFuse apb2otp block0 data register13.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word2 data.
+         */
+        uint32_t apb2otp_block0_backup3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
+/** Type of apb2otp_blk0_backup3_w3 register
+ *  eFuse apb2otp block0 data register14.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word3 data.
+         */
+        uint32_t apb2otp_block0_backup3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
+/** Type of apb2otp_blk0_backup3_w4 register
+ *  eFuse apb2otp block0 data register15.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word4 data.
+         */
+        uint32_t apb2otp_block0_backup3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
+/** Type of apb2otp_blk0_backup3_w5 register
+ *  eFuse apb2otp block0 data register16.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word5 data.
+         */
+        uint32_t apb2otp_block0_backup3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
+/** Type of apb2otp_blk0_backup4_w1 register
+ *  eFuse apb2otp block0 data register17.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word1 data.
+         */
+        uint32_t apb2otp_block0_backup4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
+/** Type of apb2otp_blk0_backup4_w2 register
+ *  eFuse apb2otp block0 data register18.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word2 data.
+         */
+        uint32_t apb2otp_block0_backup4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
+/** Type of apb2otp_blk0_backup4_w3 register
+ *  eFuse apb2otp block0 data register19.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word3 data.
+         */
+        uint32_t apb2otp_block0_backup4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
+/** Type of apb2otp_blk0_backup4_w4 register
+ *  eFuse apb2otp block0 data register20.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word4 data.
+         */
+        uint32_t apb2otp_block0_backup4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
+/** Type of apb2otp_blk0_backup4_w5 register
+ *  eFuse apb2otp block0 data register21.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word5 data.
+         */
+        uint32_t apb2otp_block0_backup4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word1 Data */
+/** Type of apb2otp_blk1_w1 register
+ *  eFuse apb2otp block1 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word1 data.
+         */
+        uint32_t apb2otp_block1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word2 Data */
+/** Type of apb2otp_blk1_w2 register
+ *  eFuse apb2otp block1 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word2 data.
+         */
+        uint32_t apb2otp_block1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word3 Data */
+/** Type of apb2otp_blk1_w3 register
+ *  eFuse apb2otp block1 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word3 data.
+         */
+        uint32_t apb2otp_block1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word4 Data */
+/** Type of apb2otp_blk1_w4 register
+ *  eFuse apb2otp block1 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word4 data.
+         */
+        uint32_t apb2otp_block1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word5 Data */
+/** Type of apb2otp_blk1_w5 register
+ *  eFuse apb2otp block1 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word5 data.
+         */
+        uint32_t apb2otp_block1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word6 Data */
+/** Type of apb2otp_blk1_w6 register
+ *  eFuse apb2otp block1 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word6 data.
+         */
+        uint32_t apb2otp_block1_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word7 Data */
+/** Type of apb2otp_blk1_w7 register
+ *  eFuse apb2otp block1 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word7 data.
+         */
+        uint32_t apb2otp_block1_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word8 Data */
+/** Type of apb2otp_blk1_w8 register
+ *  eFuse apb2otp block1 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word8 data.
+         */
+        uint32_t apb2otp_block1_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word9 Data */
+/** Type of apb2otp_blk1_w9 register
+ *  eFuse apb2otp block1 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word9 data.
+         */
+        uint32_t apb2otp_block1_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word1 Data */
+/** Type of apb2otp_blk2_w1 register
+ *  eFuse apb2otp block2 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word1 data.
+         */
+        uint32_t apb2otp_block2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word2 Data */
+/** Type of apb2otp_blk2_w2 register
+ *  eFuse apb2otp block2 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word2 data.
+         */
+        uint32_t apb2otp_block2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word3 Data */
+/** Type of apb2otp_blk2_w3 register
+ *  eFuse apb2otp block2 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word3 data.
+         */
+        uint32_t apb2otp_block2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word4 Data */
+/** Type of apb2otp_blk2_w4 register
+ *  eFuse apb2otp block2 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word4 data.
+         */
+        uint32_t apb2otp_block2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word5 Data */
+/** Type of apb2otp_blk2_w5 register
+ *  eFuse apb2otp block2 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word5 data.
+         */
+        uint32_t apb2otp_block2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word6 Data */
+/** Type of apb2otp_blk2_w6 register
+ *  eFuse apb2otp block2 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word6 data.
+         */
+        uint32_t apb2otp_block2_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word7 Data */
+/** Type of apb2otp_blk2_w7 register
+ *  eFuse apb2otp block2 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word7 data.
+         */
+        uint32_t apb2otp_block2_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word8 Data */
+/** Type of apb2otp_blk2_w8 register
+ *  eFuse apb2otp block2 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word8 data.
+         */
+        uint32_t apb2otp_block2_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word9 Data */
+/** Type of apb2otp_blk2_w9 register
+ *  eFuse apb2otp block2 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word9 data.
+         */
+        uint32_t apb2otp_block2_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word10 Data */
+/** Type of apb2otp_blk2_w10 register
+ *  eFuse apb2otp block2 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word10 data.
+         */
+        uint32_t apb2otp_block2_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk2_w11 register
+ *  eFuse apb2otp block2 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word11 data.
+         */
+        uint32_t apb2otp_block2_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w11_reg_t;
+
+/** Type of apb2otp_blk10_w11 register
+ *  eFuse apb2otp block10 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word11 data.
+         */
+        uint32_t apb2otp_block10_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word1 Data */
+/** Type of apb2otp_blk3_w1 register
+ *  eFuse apb2otp block3 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word1 data.
+         */
+        uint32_t apb2otp_block3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word2 Data */
+/** Type of apb2otp_blk3_w2 register
+ *  eFuse apb2otp block3 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word2 data.
+         */
+        uint32_t apb2otp_block3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word3 Data */
+/** Type of apb2otp_blk3_w3 register
+ *  eFuse apb2otp block3 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word3 data.
+         */
+        uint32_t apb2otp_block3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word4 Data */
+/** Type of apb2otp_blk3_w4 register
+ *  eFuse apb2otp block3 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word4 data.
+         */
+        uint32_t apb2otp_block3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word5 Data */
+/** Type of apb2otp_blk3_w5 register
+ *  eFuse apb2otp block3 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word5 data.
+         */
+        uint32_t apb2otp_block3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word6 Data */
+/** Type of apb2otp_blk3_w6 register
+ *  eFuse apb2otp block3 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word6 data.
+         */
+        uint32_t apb2otp_block3_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word7 Data */
+/** Type of apb2otp_blk3_w7 register
+ *  eFuse apb2otp block3 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word7 data.
+         */
+        uint32_t apb2otp_block3_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word8 Data */
+/** Type of apb2otp_blk3_w8 register
+ *  eFuse apb2otp block3 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word8 data.
+         */
+        uint32_t apb2otp_block3_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word9 Data */
+/** Type of apb2otp_blk3_w9 register
+ *  eFuse apb2otp block3 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word9 data.
+         */
+        uint32_t apb2otp_block3_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word10 Data */
+/** Type of apb2otp_blk3_w10 register
+ *  eFuse apb2otp block3 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word10 data.
+         */
+        uint32_t apb2otp_block3_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word11 Data */
+/** Type of apb2otp_blk3_w11 register
+ *  eFuse apb2otp block3 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word11 data.
+         */
+        uint32_t apb2otp_block3_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word1 Data */
+/** Type of apb2otp_blk4_w1 register
+ *  eFuse apb2otp block4 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word1 data.
+         */
+        uint32_t apb2otp_block4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word2 Data */
+/** Type of apb2otp_blk4_w2 register
+ *  eFuse apb2otp block4 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word2 data.
+         */
+        uint32_t apb2otp_block4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word3 Data */
+/** Type of apb2otp_blk4_w3 register
+ *  eFuse apb2otp block4 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word3 data.
+         */
+        uint32_t apb2otp_block4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word4 Data */
+/** Type of apb2otp_blk4_w4 register
+ *  eFuse apb2otp block4 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word4 data.
+         */
+        uint32_t apb2otp_block4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word5 Data */
+/** Type of apb2otp_blk4_w5 register
+ *  eFuse apb2otp block4 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word5 data.
+         */
+        uint32_t apb2otp_block4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word6 Data */
+/** Type of apb2otp_blk4_w6 register
+ *  eFuse apb2otp block4 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word6 data.
+         */
+        uint32_t apb2otp_block4_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word7 Data */
+/** Type of apb2otp_blk4_w7 register
+ *  eFuse apb2otp block4 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word7 data.
+         */
+        uint32_t apb2otp_block4_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word8 Data */
+/** Type of apb2otp_blk4_w8 register
+ *  eFuse apb2otp block4 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word8 data.
+         */
+        uint32_t apb2otp_block4_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word9 Data */
+/** Type of apb2otp_blk4_w9 register
+ *  eFuse apb2otp block4 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word9 data.
+         */
+        uint32_t apb2otp_block4_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word10 Data */
+/** Type of apb2otp_blk4_w10 register
+ *  eFuse apb2otp block4 data registe10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word10 data.
+         */
+        uint32_t apb2otp_block4_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word11 Data */
+/** Type of apb2otp_blk4_w11 register
+ *  eFuse apb2otp block4 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word11 data.
+         */
+        uint32_t apb2otp_block4_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word1 Data */
+/** Type of apb2otp_blk5_w1 register
+ *  eFuse apb2otp block5 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word1 data.
+         */
+        uint32_t apb2otp_block5_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word2 Data */
+/** Type of apb2otp_blk5_w2 register
+ *  eFuse apb2otp block5 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word2 data.
+         */
+        uint32_t apb2otp_block5_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word3 Data */
+/** Type of apb2otp_blk5_w3 register
+ *  eFuse apb2otp block5 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word3 data.
+         */
+        uint32_t apb2otp_block5_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word4 Data */
+/** Type of apb2otp_blk5_w4 register
+ *  eFuse apb2otp block5 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word4 data.
+         */
+        uint32_t apb2otp_block5_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word5 Data */
+/** Type of apb2otp_blk5_w5 register
+ *  eFuse apb2otp block5 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word5 data.
+         */
+        uint32_t apb2otp_block5_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word6 Data */
+/** Type of apb2otp_blk5_w6 register
+ *  eFuse apb2otp block5 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word6 data.
+         */
+        uint32_t apb2otp_block5_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word7 Data */
+/** Type of apb2otp_blk5_w7 register
+ *  eFuse apb2otp block5 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word7 data.
+         */
+        uint32_t apb2otp_block5_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word8 Data */
+/** Type of apb2otp_blk5_w8 register
+ *  eFuse apb2otp block5 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word8 data.
+         */
+        uint32_t apb2otp_block5_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word9 Data */
+/** Type of apb2otp_blk5_w9 register
+ *  eFuse apb2otp block5 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word9 data.
+         */
+        uint32_t apb2otp_block5_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word10 Data */
+/** Type of apb2otp_blk5_w10 register
+ *  eFuse apb2otp block5 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word10 data.
+         */
+        uint32_t apb2otp_block5_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word11 Data */
+/** Type of apb2otp_blk5_w11 register
+ *  eFuse apb2otp block5 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word11 data.
+         */
+        uint32_t apb2otp_block5_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word1 Data */
+/** Type of apb2otp_blk6_w1 register
+ *  eFuse apb2otp block6 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word1 data.
+         */
+        uint32_t apb2otp_block6_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word2 Data */
+/** Type of apb2otp_blk6_w2 register
+ *  eFuse apb2otp block6 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word2 data.
+         */
+        uint32_t apb2otp_block6_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word3 Data */
+/** Type of apb2otp_blk6_w3 register
+ *  eFuse apb2otp block6 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word3 data.
+         */
+        uint32_t apb2otp_block6_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word4 Data */
+/** Type of apb2otp_blk6_w4 register
+ *  eFuse apb2otp block6 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word4 data.
+         */
+        uint32_t apb2otp_block6_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word5 Data */
+/** Type of apb2otp_blk6_w5 register
+ *  eFuse apb2otp block6 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word5 data.
+         */
+        uint32_t apb2otp_block6_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word6 Data */
+/** Type of apb2otp_blk6_w6 register
+ *  eFuse apb2otp block6 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word6 data.
+         */
+        uint32_t apb2otp_block6_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word7 Data */
+/** Type of apb2otp_blk6_w7 register
+ *  eFuse apb2otp block6 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word7 data.
+         */
+        uint32_t apb2otp_block6_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word8 Data */
+/** Type of apb2otp_blk6_w8 register
+ *  eFuse apb2otp block6 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word8 data.
+         */
+        uint32_t apb2otp_block6_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word9 Data */
+/** Type of apb2otp_blk6_w9 register
+ *  eFuse apb2otp block6 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word9 data.
+         */
+        uint32_t apb2otp_block6_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word10 Data */
+/** Type of apb2otp_blk6_w10 register
+ *  eFuse apb2otp block6 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word10 data.
+         */
+        uint32_t apb2otp_block6_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word11 Data */
+/** Type of apb2otp_blk6_w11 register
+ *  eFuse apb2otp block6 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word11 data.
+         */
+        uint32_t apb2otp_block6_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word1 Data */
+/** Type of apb2otp_blk7_w1 register
+ *  eFuse apb2otp block7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word1 data.
+         */
+        uint32_t apb2otp_block7_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word2 Data */
+/** Type of apb2otp_blk7_w2 register
+ *  eFuse apb2otp block7 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word2 data.
+         */
+        uint32_t apb2otp_block7_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word3 Data */
+/** Type of apb2otp_blk7_w3 register
+ *  eFuse apb2otp block7 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word3 data.
+         */
+        uint32_t apb2otp_block7_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word4 Data */
+/** Type of apb2otp_blk7_w4 register
+ *  eFuse apb2otp block7 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word4 data.
+         */
+        uint32_t apb2otp_block7_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word5 Data */
+/** Type of apb2otp_blk7_w5 register
+ *  eFuse apb2otp block7 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word5 data.
+         */
+        uint32_t apb2otp_block7_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word6 Data */
+/** Type of apb2otp_blk7_w6 register
+ *  eFuse apb2otp block7 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word6 data.
+         */
+        uint32_t apb2otp_block7_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word7 Data */
+/** Type of apb2otp_blk7_w7 register
+ *  eFuse apb2otp block7 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word7 data.
+         */
+        uint32_t apb2otp_block7_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word8 Data */
+/** Type of apb2otp_blk7_w8 register
+ *  eFuse apb2otp block7 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word8 data.
+         */
+        uint32_t apb2otp_block7_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word9 Data */
+/** Type of apb2otp_blk7_w9 register
+ *  eFuse apb2otp block7 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word9 data.
+         */
+        uint32_t apb2otp_block7_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word10 Data */
+/** Type of apb2otp_blk7_w10 register
+ *  eFuse apb2otp block7 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word10 data.
+         */
+        uint32_t apb2otp_block7_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word11 Data */
+/** Type of apb2otp_blk7_w11 register
+ *  eFuse apb2otp block7 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word11 data.
+         */
+        uint32_t apb2otp_block7_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word1 Data */
+/** Type of apb2otp_blk8_w1 register
+ *  eFuse apb2otp block8 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word1 data.
+         */
+        uint32_t apb2otp_block8_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word2 Data */
+/** Type of apb2otp_blk8_w2 register
+ *  eFuse apb2otp block8 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word2 data.
+         */
+        uint32_t apb2otp_block8_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word3 Data */
+/** Type of apb2otp_blk8_w3 register
+ *  eFuse apb2otp block8 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word3 data.
+         */
+        uint32_t apb2otp_block8_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word4 Data */
+/** Type of apb2otp_blk8_w4 register
+ *  eFuse apb2otp block8 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word4 data.
+         */
+        uint32_t apb2otp_block8_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word5 Data */
+/** Type of apb2otp_blk8_w5 register
+ *  eFuse apb2otp block8 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word5 data.
+         */
+        uint32_t apb2otp_block8_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word6 Data */
+/** Type of apb2otp_blk8_w6 register
+ *  eFuse apb2otp block8 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word6 data.
+         */
+        uint32_t apb2otp_block8_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word7 Data */
+/** Type of apb2otp_blk8_w7 register
+ *  eFuse apb2otp block8 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word7 data.
+         */
+        uint32_t apb2otp_block8_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word8 Data */
+/** Type of apb2otp_blk8_w8 register
+ *  eFuse apb2otp block8 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word8 data.
+         */
+        uint32_t apb2otp_block8_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word9 Data */
+/** Type of apb2otp_blk8_w9 register
+ *  eFuse apb2otp block8 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word9 data.
+         */
+        uint32_t apb2otp_block8_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word10 Data */
+/** Type of apb2otp_blk8_w10 register
+ *  eFuse apb2otp block8 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word10 data.
+         */
+        uint32_t apb2otp_block8_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word11 Data */
+/** Type of apb2otp_blk8_w11 register
+ *  eFuse apb2otp block8 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word11 data.
+         */
+        uint32_t apb2otp_block8_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word1 Data */
+/** Type of apb2otp_blk9_w1 register
+ *  eFuse apb2otp block9 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word1 data.
+         */
+        uint32_t apb2otp_block9_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word2 Data */
+/** Type of apb2otp_blk9_w2 register
+ *  eFuse apb2otp block9 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word2 data.
+         */
+        uint32_t apb2otp_block9_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word3 Data */
+/** Type of apb2otp_blk9_w3 register
+ *  eFuse apb2otp block9 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word3 data.
+         */
+        uint32_t apb2otp_block9_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word4 Data */
+/** Type of apb2otp_blk9_w4 register
+ *  eFuse apb2otp block9 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word4 data.
+         */
+        uint32_t apb2otp_block9_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word5 Data */
+/** Type of apb2otp_blk9_w5 register
+ *  eFuse apb2otp block9 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word5 data.
+         */
+        uint32_t apb2otp_block9_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word6 Data */
+/** Type of apb2otp_blk9_w6 register
+ *  eFuse apb2otp block9 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word6 data.
+         */
+        uint32_t apb2otp_block9_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word7 Data */
+/** Type of apb2otp_blk9_w7 register
+ *  eFuse apb2otp block9 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word7 data.
+         */
+        uint32_t apb2otp_block9_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word8 Data */
+/** Type of apb2otp_blk9_w8 register
+ *  eFuse apb2otp block9 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word8 data.
+         */
+        uint32_t apb2otp_block9_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word9 Data */
+/** Type of apb2otp_blk9_w9 register
+ *  eFuse apb2otp block9 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word9 data.
+         */
+        uint32_t apb2otp_block9_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word10 Data */
+/** Type of apb2otp_blk9_w10 register
+ *  eFuse apb2otp block9 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word10 data.
+         */
+        uint32_t apb2otp_block9_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word11 Data */
+/** Type of apb2otp_blk9_w11 register
+ *  eFuse apb2otp block9 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word11 data.
+         */
+        uint32_t apb2otp_block9_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word1 Data */
+/** Type of apb2otp_blk10_w1 register
+ *  eFuse apb2otp block10 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word1 data.
+         */
+        uint32_t apb2otp_block10_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word2 Data */
+/** Type of apb2otp_blk10_w2 register
+ *  eFuse apb2otp block10 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word2 data.
+         */
+        uint32_t apb2otp_block10_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word3 Data */
+/** Type of apb2otp_blk10_w3 register
+ *  eFuse apb2otp block10 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word3 data.
+         */
+        uint32_t apb2otp_block10_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word4 Data */
+/** Type of apb2otp_blk10_w4 register
+ *  eFuse apb2otp block10 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word4 data.
+         */
+        uint32_t apb2otp_block10_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word5 Data */
+/** Type of apb2otp_blk10_w5 register
+ *  eFuse apb2otp block10 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word5 data.
+         */
+        uint32_t apb2otp_block10_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word6 Data */
+/** Type of apb2otp_blk10_w6 register
+ *  eFuse apb2otp block10 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word6 data.
+         */
+        uint32_t apb2otp_block10_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word7 Data */
+/** Type of apb2otp_blk10_w7 register
+ *  eFuse apb2otp block10 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word7 data.
+         */
+        uint32_t apb2otp_block10_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word8 Data */
+/** Type of apb2otp_blk10_w8 register
+ *  eFuse apb2otp block10 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word8 data.
+         */
+        uint32_t apb2otp_block10_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word9 Data */
+/** Type of apb2otp_blk10_w9 register
+ *  eFuse apb2otp block10 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word9 data.
+         */
+        uint32_t apb2otp_block10_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word10 Data */
+/** Type of apb2otp_blk10_w10 register
+ *  eFuse apb2otp block10 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word10 data.
+         */
+        uint32_t apb2otp_block19_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Function Enable Signal */
+/** Type of apb2otp_en register
+ *  eFuse apb2otp enable configuration register.
+ */
+typedef union {
+    struct {
+        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
+         *  Apb2otp mode enable signal.
+         */
+        uint32_t apb2otp_apb2otp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} efuse_apb2otp_en_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_datan_reg_t pgm_datan[8];
+    volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3];
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0;
+    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1;
+    uint32_t reserved_04c;
+    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
+    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
+    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
+    volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8];
+    volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8];
+    volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8];
+    volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8];
+    volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8];
+    volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8];
+    volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8];
+    volatile efuse_rd_key5_datan_reg_t rd_key5_datan[8];
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    uint32_t reserved_174;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
+    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
+    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
+    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
+    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
+    uint32_t reserved_190[8];
+    volatile efuse_ecdsa_reg_t ecdsa;
+    uint32_t reserved_1b4[3];
+    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
+    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    volatile efuse_date_reg_t date;
+    uint32_t reserved_200[384];
+    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
+    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
+    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
+    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
+    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
+    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
+    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
+    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
+    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
+    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
+    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
+    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
+    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
+    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
+    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
+    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
+    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
+    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
+    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
+    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
+    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
+    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
+    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
+    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
+    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
+    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
+    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
+    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
+    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
+    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
+    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
+    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
+    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
+    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
+    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
+    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
+    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
+    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
+    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
+    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
+    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
+    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
+    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
+    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
+    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
+    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
+    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
+    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
+    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
+    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
+    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
+    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
+    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
+    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
+    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
+    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
+    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
+    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
+    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
+    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
+    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
+    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
+    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
+    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
+    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
+    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
+    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
+    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
+    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
+    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
+    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
+    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
+    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
+    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
+    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
+    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
+    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
+    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
+    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
+    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
+    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
+    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
+    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
+    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
+    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
+    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
+    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
+    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
+    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
+    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
+    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
+    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
+    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
+    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
+    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
+    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
+    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
+    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
+    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
+    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
+    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
+    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
+    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
+    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
+    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
+    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
+    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
+    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
+    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
+    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
+    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
+    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
+    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
+    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
+    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
+    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
+    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
+    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
+    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
+    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
+    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
+    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
+    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
+    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
+    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
+    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
+    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
+    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
+    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
+    uint32_t reserved_a04;
+    volatile efuse_apb2otp_en_reg_t apb2otp_en;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/efuse_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/efuse_reg.h
new file mode 100644
index 0000000000..e0a0a82e4e
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/efuse_reg.h
@@ -0,0 +1,4655 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/efuse_defs.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: IDF-13421
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register 0.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Represents whether programming of individual eFuse memory bit is disabled or
+ *  enabled. 1: Disabled. 0 Enabled.
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register 1.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0;
+ *  Enable usb device exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(7))
+#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S)
+#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_DEVICE_EXCHG_PINS_S  7
+/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0;
+ *  Enable usb otg11 exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(8))
+#define EFUSE_USB_OTG11_EXCHG_PINS_M  (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S)
+#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_OTG11_EXCHG_PINS_S  8
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
+ *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  9
+/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0;
+ *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_POWERGLITCH_EN    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
+#define EFUSE_POWERGLITCH_EN_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Represents whether the function that forces chip into download mode is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
+ *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+ *  boot_mode_download.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ *  is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+ *  enabled.
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+ *  enabled.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+ *  mode). 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_DEVICE_DREFH    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_M  (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S)
+#define EFUSE_USB_DEVICE_DREFH_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_S  21
+/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [24:23]; default: 0;
+ *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_OTG11_DREFH    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_M  (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S)
+#define EFUSE_USB_OTG11_DREFH_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_S  23
+/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
+ *  TBD
+ */
+#define EFUSE_USB_PHY_SEL    (BIT(25))
+#define EFUSE_USB_PHY_SEL_M  (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
+#define EFUSE_USB_PHY_SEL_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_S  25
+/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0;
+ *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+ *  of 1 is valid.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_LOW    0x0000003FU
+#define EFUSE_KM_HUK_GEN_STATE_LOW_M  (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S)
+#define EFUSE_KM_HUK_GEN_STATE_LOW_V  0x0000003FU
+#define EFUSE_KM_HUK_GEN_STATE_LOW_S  26
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  BLOCK0 data register 2.
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0;
+ *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+ *  of 1 is valid.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_HIGH    0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S)
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_V  0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0;
+ *  Set bits to control key manager random number switch cycle. 0: control by register.
+ *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_S  3
+/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0;
+ *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+ *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  5
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0;
+ *  Set each bit to control whether corresponding key must come from key manager.. 1 is
+ *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  9
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [13]; default: 0;
+ *  Set this bit to disable software written init key, and force use efuse_init_key.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  13
+/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0;
+ *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
+#define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_S  14
+/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_79    (BIT(15))
+#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
+#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_79_S  15
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+ *  selected. 0: not selected.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+ *  1: enabled. Even number of 1: disabled.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  Represents the purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  Represents the purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  BLOCK0 data register 3.
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  Represents the purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  Represents the purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  Represents the purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  Represents the purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents the spa secure level by configuring the clock random divide mode.
+ */
+#define EFUSE_SEC_DPA_LEVEL    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
+#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_S  16
+/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0;
+ *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+ *  0: not force used.
+ */
+#define EFUSE_ECDSA_ENABLE_SOFT_K    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_M  (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S)
+#define EFUSE_ECDSA_ENABLE_SOFT_K_V  0x00000001U
+#define EFUSE_ECDSA_ENABLE_SOFT_K_S  18
+/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
+ *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
+#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_S  19
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_118    (BIT(22))
+#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
+#define EFUSE_RD_RESERVE_0_118_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_118_S  22
+/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0;
+ *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
+ */
+#define EFUSE_FLASH_TYPE    (BIT(23))
+#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
+#define EFUSE_FLASH_TYPE_V  0x00000001U
+#define EFUSE_FLASH_TYPE_S  23
+/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0;
+ *  Set flash page size.
+ */
+#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
+#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_S  24
+/** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0;
+ *  Set this bit to enable ecc for flash boot.
+ */
+#define EFUSE_FLASH_ECC_EN    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
+#define EFUSE_FLASH_ECC_EN_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_S  26
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [27]; default: 0;
+ *  Set this bit to disable download via USB-OTG.
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  27
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Represents the flash waiting time after power-up, in unit of ms. When the value
+ *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+ *  is 2 times the programmed value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  BLOCK0 data register 4.
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+ *  0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
+ *  TBD
+ */
+#define EFUSE_LOCK_KM_KEY    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
+#define EFUSE_LOCK_KM_KEY_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+ *  disabled.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  Represents the type of UART printing. 00: force enable printing. 01: enable
+ *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+ *  at high level. 11: force disable printing.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
+ *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+ *  forced. 0:not forced.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  8
+/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
+ *  Represents the version used by ESP-IDF anti-rollback feature.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
+ *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
+/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
+ *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
+ *  enabled. 0:disabled.
+ */
+#define EFUSE_HYS_EN_PAD    (BIT(26))
+#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
+#define EFUSE_HYS_EN_PAD_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_S  26
+/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0;
+ *  Set the dcdc voltage default.
+ */
+#define EFUSE_DCDC_VSET    0x0000001FU
+#define EFUSE_DCDC_VSET_M  (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S)
+#define EFUSE_DCDC_VSET_V  0x0000001FU
+#define EFUSE_DCDC_VSET_S  27
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  BLOCK0 data register 5.
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_PXA0_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
+ *  TBD
+ */
+#define EFUSE_PXA0_TIEH_SEL_0    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_M  (EFUSE_PXA0_TIEH_SEL_0_V << EFUSE_PXA0_TIEH_SEL_0_S)
+#define EFUSE_PXA0_TIEH_SEL_0_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_S  0
+/** EFUSE_PXA0_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_PXA0_TIEH_SEL_1    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_M  (EFUSE_PXA0_TIEH_SEL_1_V << EFUSE_PXA0_TIEH_SEL_1_S)
+#define EFUSE_PXA0_TIEH_SEL_1_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_S  2
+/** EFUSE_PXA0_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_PXA0_TIEH_SEL_2    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_M  (EFUSE_PXA0_TIEH_SEL_2_V << EFUSE_PXA0_TIEH_SEL_2_S)
+#define EFUSE_PXA0_TIEH_SEL_2_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_S  4
+/** EFUSE_PXA0_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_PXA0_TIEH_SEL_3    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_M  (EFUSE_PXA0_TIEH_SEL_3_V << EFUSE_PXA0_TIEH_SEL_3_S)
+#define EFUSE_PXA0_TIEH_SEL_3_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_S  6
+/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
+/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0;
+ *  Represents the usb device single-end input low threshold; 0.8 V to 1.04 V with step
+ *  of 80 mV
+ */
+#define EFUSE_USB_DEVICE_DREFL    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_M  (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
+#define EFUSE_USB_DEVICE_DREFL_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_S  12
+/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0;
+ *  Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V with step
+ *  of 80 mV
+ */
+#define EFUSE_USB_OTG11_DREFL    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_M  (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
+#define EFUSE_USB_OTG11_DREFL_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_S  14
+/** EFUSE_RD_RESERVE_0_176 : RW; bitpos: [17:16]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_176    0x00000003U
+#define EFUSE_RD_RESERVE_0_176_M  (EFUSE_RD_RESERVE_0_176_V << EFUSE_RD_RESERVE_0_176_S)
+#define EFUSE_RD_RESERVE_0_176_V  0x00000003U
+#define EFUSE_RD_RESERVE_0_176_S  16
+/** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0;
+ *  HP system power source select. 0:LDO. 1: DCDC.
+ */
+#define EFUSE_HP_PWR_SRC_SEL    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_M  (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S)
+#define EFUSE_HP_PWR_SRC_SEL_V  0x00000001U
+#define EFUSE_HP_PWR_SRC_SEL_S  18
+/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0;
+ *  Select dcdc vset use efuse_dcdc_vset.
+ */
+#define EFUSE_DCDC_VSET_EN    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_M  (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S)
+#define EFUSE_DCDC_VSET_EN_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_S  19
+/** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0;
+ *  Set this bit to disable watch dog.
+ */
+#define EFUSE_DIS_WDT    (BIT(20))
+#define EFUSE_DIS_WDT_M  (EFUSE_DIS_WDT_V << EFUSE_DIS_WDT_S)
+#define EFUSE_DIS_WDT_V  0x00000001U
+#define EFUSE_DIS_WDT_S  20
+/** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0;
+ *  Set this bit to disable super-watchdog.
+ */
+#define EFUSE_DIS_SWD    (BIT(21))
+#define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
+#define EFUSE_DIS_SWD_V  0x00000001U
+#define EFUSE_DIS_SWD_S  21
+/** EFUSE_RD_RESERVE_0_182 : RW; bitpos: [31:22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_182    0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_M  (EFUSE_RD_RESERVE_0_182_V << EFUSE_RD_RESERVE_0_182_S)
+#define EFUSE_RD_RESERVE_0_182_V  0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_S  22
+
+/** EFUSE_RD_MAC_SYS_0_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the low 32 bits of MAC address.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SYS_1_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Stores the high 16 bits of MAC address.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_RESERVED_1_16 : RO; bitpos: [31:16]; default: 0;
+ *  Stores the extended bits of MAC address.
+ */
+#define EFUSE_RESERVED_1_16    0x0000FFFFU
+#define EFUSE_RESERVED_1_16_M  (EFUSE_RESERVED_1_16_V << EFUSE_RESERVED_1_16_S)
+#define EFUSE_RESERVED_1_16_V  0x0000FFFFU
+#define EFUSE_RESERVED_1_16_S  16
+
+/** EFUSE_RD_MAC_SYS_2_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
+ *  Minor chip version
+ */
+#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
+#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_S  0
+/** EFUSE_WAFER_VERSION_MAJOR_LO : R; bitpos: [5:4]; default: 0;
+ *  Major chip version (lower 2 bits)
+ */
+#define EFUSE_WAFER_VERSION_MAJOR_LO    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_LO_M  (EFUSE_WAFER_VERSION_MAJOR_LO_V << EFUSE_WAFER_VERSION_MAJOR_LO_S)
+#define EFUSE_WAFER_VERSION_MAJOR_LO_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_LO_S  4
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(6))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  6
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
+ *  BLK_VERSION_MINOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  8
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  11
+/** EFUSE_PSRAM_CAP : R; bitpos: [15:13]; default: 0;
+ *  PSRAM capacity
+ */
+#define EFUSE_PSRAM_CAP    0x00000007U
+#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
+#define EFUSE_PSRAM_CAP_V  0x00000007U
+#define EFUSE_PSRAM_CAP_S  13
+/** EFUSE_TEMP : R; bitpos: [17:16]; default: 0;
+ *  Operating temperature of the ESP chip
+ */
+#define EFUSE_TEMP    0x00000003U
+#define EFUSE_TEMP_M  (EFUSE_TEMP_V << EFUSE_TEMP_S)
+#define EFUSE_TEMP_V  0x00000003U
+#define EFUSE_TEMP_S  16
+/** EFUSE_PSRAM_VENDOR : R; bitpos: [19:18]; default: 0;
+ *  PSRAM vendor
+ */
+#define EFUSE_PSRAM_VENDOR    0x00000003U
+#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
+#define EFUSE_PSRAM_VENDOR_V  0x00000003U
+#define EFUSE_PSRAM_VENDOR_S  18
+/** EFUSE_PKG_VERSION : R; bitpos: [22:20]; default: 0;
+ *  Package version
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  20
+/** EFUSE_WAFER_VERSION_MAJOR_HI : R; bitpos: [23]; default: 0;
+ *  Major chip version (MSB)
+ */
+#define EFUSE_WAFER_VERSION_MAJOR_HI    (BIT(23))
+#define EFUSE_WAFER_VERSION_MAJOR_HI_M  (EFUSE_WAFER_VERSION_MAJOR_HI_V << EFUSE_WAFER_VERSION_MAJOR_HI_S)
+#define EFUSE_WAFER_VERSION_MAJOR_HI_V  0x00000001U
+#define EFUSE_WAFER_VERSION_MAJOR_HI_S  23
+/** EFUSE_LDO_VO1_DREF : R; bitpos: [27:24]; default: 0;
+ *  Output VO1 parameter
+ */
+#define EFUSE_LDO_VO1_DREF    0x0000000FU
+#define EFUSE_LDO_VO1_DREF_M  (EFUSE_LDO_VO1_DREF_V << EFUSE_LDO_VO1_DREF_S)
+#define EFUSE_LDO_VO1_DREF_V  0x0000000FU
+#define EFUSE_LDO_VO1_DREF_S  24
+/** EFUSE_LDO_VO2_DREF : R; bitpos: [31:28]; default: 0;
+ *  Output VO2 parameter
+ */
+#define EFUSE_LDO_VO2_DREF    0x0000000FU
+#define EFUSE_LDO_VO2_DREF_M  (EFUSE_LDO_VO2_DREF_V << EFUSE_LDO_VO2_DREF_S)
+#define EFUSE_LDO_VO2_DREF_V  0x0000000FU
+#define EFUSE_LDO_VO2_DREF_S  28
+
+/** EFUSE_RD_MAC_SYS_3_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_LDO_VO1_MUL : R; bitpos: [2:0]; default: 0;
+ *  Output VO1 parameter
+ */
+#define EFUSE_LDO_VO1_MUL    0x00000007U
+#define EFUSE_LDO_VO1_MUL_M  (EFUSE_LDO_VO1_MUL_V << EFUSE_LDO_VO1_MUL_S)
+#define EFUSE_LDO_VO1_MUL_V  0x00000007U
+#define EFUSE_LDO_VO1_MUL_S  0
+/** EFUSE_LDO_VO2_MUL : R; bitpos: [5:3]; default: 0;
+ *  Output VO2 parameter
+ */
+#define EFUSE_LDO_VO2_MUL    0x00000007U
+#define EFUSE_LDO_VO2_MUL_M  (EFUSE_LDO_VO2_MUL_V << EFUSE_LDO_VO2_MUL_S)
+#define EFUSE_LDO_VO2_MUL_V  0x00000007U
+#define EFUSE_LDO_VO2_MUL_S  3
+/** EFUSE_LDO_VO3_K : R; bitpos: [13:6]; default: 0;
+ *  Output VO3 calibration parameter
+ */
+#define EFUSE_LDO_VO3_K    0x000000FFU
+#define EFUSE_LDO_VO3_K_M  (EFUSE_LDO_VO3_K_V << EFUSE_LDO_VO3_K_S)
+#define EFUSE_LDO_VO3_K_V  0x000000FFU
+#define EFUSE_LDO_VO3_K_S  6
+/** EFUSE_LDO_VO3_VOS : R; bitpos: [19:14]; default: 0;
+ *  Output VO3 calibration parameter
+ */
+#define EFUSE_LDO_VO3_VOS    0x0000003FU
+#define EFUSE_LDO_VO3_VOS_M  (EFUSE_LDO_VO3_VOS_V << EFUSE_LDO_VO3_VOS_S)
+#define EFUSE_LDO_VO3_VOS_V  0x0000003FU
+#define EFUSE_LDO_VO3_VOS_S  14
+/** EFUSE_LDO_VO3_C : R; bitpos: [25:20]; default: 0;
+ *  Output VO3 calibration parameter
+ */
+#define EFUSE_LDO_VO3_C    0x0000003FU
+#define EFUSE_LDO_VO3_C_M  (EFUSE_LDO_VO3_C_V << EFUSE_LDO_VO3_C_S)
+#define EFUSE_LDO_VO3_C_V  0x0000003FU
+#define EFUSE_LDO_VO3_C_S  20
+/** EFUSE_LDO_VO4_K : R; bitpos: [31:26]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_K    0x0000003FU
+#define EFUSE_LDO_VO4_K_M  (EFUSE_LDO_VO4_K_V << EFUSE_LDO_VO4_K_S)
+#define EFUSE_LDO_VO4_K_V  0x0000003FU
+#define EFUSE_LDO_VO4_K_S  26
+
+/** EFUSE_RD_MAC_SYS_4_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_LDO_VO4_K_1 : R; bitpos: [1:0]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_K_1    0x00000003U
+#define EFUSE_LDO_VO4_K_1_M  (EFUSE_LDO_VO4_K_1_V << EFUSE_LDO_VO4_K_1_S)
+#define EFUSE_LDO_VO4_K_1_V  0x00000003U
+#define EFUSE_LDO_VO4_K_1_S  0
+/** EFUSE_LDO_VO4_VOS : R; bitpos: [7:2]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_VOS    0x0000003FU
+#define EFUSE_LDO_VO4_VOS_M  (EFUSE_LDO_VO4_VOS_V << EFUSE_LDO_VO4_VOS_S)
+#define EFUSE_LDO_VO4_VOS_V  0x0000003FU
+#define EFUSE_LDO_VO4_VOS_S  2
+/** EFUSE_LDO_VO4_C : R; bitpos: [13:8]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_C    0x0000003FU
+#define EFUSE_LDO_VO4_C_M  (EFUSE_LDO_VO4_C_V << EFUSE_LDO_VO4_C_S)
+#define EFUSE_LDO_VO4_C_V  0x0000003FU
+#define EFUSE_LDO_VO4_C_S  8
+/** EFUSE_RESERVED_1_142 : R; bitpos: [15:14]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_142    0x00000003U
+#define EFUSE_RESERVED_1_142_M  (EFUSE_RESERVED_1_142_V << EFUSE_RESERVED_1_142_S)
+#define EFUSE_RESERVED_1_142_V  0x00000003U
+#define EFUSE_RESERVED_1_142_S  14
+/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [19:16]; default: 0;
+ *  Active HP DBIAS of fixed voltage
+ */
+#define EFUSE_ACTIVE_HP_DBIAS    0x0000000FU
+#define EFUSE_ACTIVE_HP_DBIAS_M  (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
+#define EFUSE_ACTIVE_HP_DBIAS_V  0x0000000FU
+#define EFUSE_ACTIVE_HP_DBIAS_S  16
+/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [23:20]; default: 0;
+ *  Active LP DBIAS of fixed voltage
+ */
+#define EFUSE_ACTIVE_LP_DBIAS    0x0000000FU
+#define EFUSE_ACTIVE_LP_DBIAS_M  (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
+#define EFUSE_ACTIVE_LP_DBIAS_V  0x0000000FU
+#define EFUSE_ACTIVE_LP_DBIAS_S  20
+/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [27:24]; default: 0;
+ *  LSLP HP DBIAS of fixed voltage
+ */
+#define EFUSE_LSLP_HP_DBIAS    0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_M  (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
+#define EFUSE_LSLP_HP_DBIAS_V  0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_S  24
+/** EFUSE_DSLP_DBG : R; bitpos: [31:28]; default: 0;
+ *  DSLP BDG of fixed voltage
+ */
+#define EFUSE_DSLP_DBG    0x0000000FU
+#define EFUSE_DSLP_DBG_M  (EFUSE_DSLP_DBG_V << EFUSE_DSLP_DBG_S)
+#define EFUSE_DSLP_DBG_V  0x0000000FU
+#define EFUSE_DSLP_DBG_S  28
+
+/** EFUSE_RD_MAC_SYS_5_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [4:0]; default: 0;
+ *  DSLP LP DBIAS of fixed voltage
+ */
+#define EFUSE_DSLP_LP_DBIAS    0x0000001FU
+#define EFUSE_DSLP_LP_DBIAS_M  (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
+#define EFUSE_DSLP_LP_DBIAS_V  0x0000001FU
+#define EFUSE_DSLP_LP_DBIAS_S  0
+/** EFUSE_LP_DCDC_DBIAS_VOL_GAP : R; bitpos: [9:5]; default: 0;
+ *  DBIAS gap between LP and DCDC
+ */
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP    0x0000001FU
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_M  (EFUSE_LP_DCDC_DBIAS_VOL_GAP_V << EFUSE_LP_DCDC_DBIAS_VOL_GAP_S)
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_V  0x0000001FU
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_S  5
+/** EFUSE_RESERVED_1_170 : R; bitpos: [31:10]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_170    0x003FFFFFU
+#define EFUSE_RESERVED_1_170_M  (EFUSE_RESERVED_1_170_V << EFUSE_RESERVED_1_170_S)
+#define EFUSE_RESERVED_1_170_V  0x003FFFFFU
+#define EFUSE_RESERVED_1_170_S  10
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [9:0]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S  0
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [19:10]; default: 0;
+ *  Average initcode of ADC1 atten1
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S  10
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [29:20]; default: 0;
+ *  Average initcode of ADC1 atten2
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S  20
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [31:30]; default: 0;
+ *  Average initcode of ADC1 atten3
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3    0x00000003U
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V  0x00000003U
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S  30
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
+ *  Average initcode of ADC1 atten3
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1    0x000000FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V  0x000000FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S  0
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN0 : R; bitpos: [17:8]; default: 0;
+ *  Average initcode of ADC2 atten0
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN0_V << EFUSE_ADC2_AVE_INITCODE_ATTEN0_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_S  8
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN1 : R; bitpos: [27:18]; default: 0;
+ *  Average initcode of ADC2 atten1
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1    0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN1_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_S  18
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN2 : R; bitpos: [31:28]; default: 0;
+ *  Average initcode of ADC2 atten2
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2    0x0000000FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN2_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_V  0x0000000FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_S  28
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 : R; bitpos: [5:0]; default: 0;
+ *  Average initcode of ADC2 atten2
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1    0x0000003FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V  0x0000003FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S  0
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN3 : R; bitpos: [15:6]; default: 0;
+ *  Average initcode of ADC2 atten3
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3    0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN3_V << EFUSE_ADC2_AVE_INITCODE_ATTEN3_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_S  6
+/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [25:16]; default: 0;
+ *  HI_DOUT of ADC1 atten0
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_S  16
+/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [31:26]; default: 0;
+ *  HI_DOUT of ADC1 atten1
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1    0x0000003FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_V  0x0000003FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_S  26
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_ADC1_HI_DOUT_ATTEN1_1 : R; bitpos: [3:0]; default: 0;
+ *  HI_DOUT of ADC1 atten1
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1    0x0000000FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_V  0x0000000FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_S  0
+/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [13:4]; default: 0;
+ *  HI_DOUT of ADC1 atten2
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_M  (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_S  4
+/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [23:14]; default: 0;
+ *  HI_DOUT of ADC1 atten3
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_S  14
+/** EFUSE_RESERVED_2_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_248    0x000000FFU
+#define EFUSE_RESERVED_2_248_M  (EFUSE_RESERVED_2_248_V << EFUSE_RESERVED_2_248_S)
+#define EFUSE_RESERVED_2_248_V  0x000000FFU
+#define EFUSE_RESERVED_2_248_S  24
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_ADC2_HI_DOUT_ATTEN0 : R; bitpos: [9:0]; default: 0;
+ *  HI_DOUT of ADC2 atten0
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN0    0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN0_M  (EFUSE_ADC2_HI_DOUT_ATTEN0_V << EFUSE_ADC2_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN0_S  0
+/** EFUSE_ADC2_HI_DOUT_ATTEN1 : R; bitpos: [19:10]; default: 0;
+ *  HI_DOUT of ADC2 atten1
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN1    0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN1_M  (EFUSE_ADC2_HI_DOUT_ATTEN1_V << EFUSE_ADC2_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN1_S  10
+/** EFUSE_ADC2_HI_DOUT_ATTEN2 : R; bitpos: [29:20]; default: 0;
+ *  HI_DOUT of ADC2 atten2
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN2_M  (EFUSE_ADC2_HI_DOUT_ATTEN2_V << EFUSE_ADC2_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN2_S  20
+/** EFUSE_ADC2_HI_DOUT_ATTEN3 : R; bitpos: [31:30]; default: 0;
+ *  HI_DOUT of ADC2 atten3
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN3    0x00000003U
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_M  (EFUSE_ADC2_HI_DOUT_ATTEN3_V << EFUSE_ADC2_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_V  0x00000003U
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_S  30
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_ADC2_HI_DOUT_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
+ *  HI_DOUT of ADC2 atten3
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1    0x000000FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_M  (EFUSE_ADC2_HI_DOUT_ATTEN3_1_V << EFUSE_ADC2_HI_DOUT_ATTEN3_1_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_V  0x000000FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_S  0
+/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
+ *  Gap between ADC1_ch0 and average initcode
+ */
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S  8
+/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
+ *  Gap between ADC1_ch1 and average initcode
+ */
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S  12
+/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
+ *  Gap between ADC1_ch2 and average initcode
+ */
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S  16
+/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
+ *  Gap between ADC1_ch3 and average initcode
+ */
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S  20
+/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
+ *  Gap between ADC1_ch4 and average initcode
+ */
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S  24
+/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
+ *  Gap between ADC1_ch5 and average initcode
+ */
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S  28
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF : R; bitpos: [3:0]; default: 0;
+ *  Gap between ADC1_ch6 and average initcode
+ */
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S  0
+/** EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF : R; bitpos: [7:4]; default: 0;
+ *  Gap between ADC1_ch7 and average initcode
+ */
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S  4
+/** EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
+ *  Gap between ADC2_ch0 and average initcode
+ */
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S  8
+/** EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
+ *  Gap between ADC2_ch1 and average initcode
+ */
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S  12
+/** EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
+ *  Gap between ADC2_ch2 and average initcode
+ */
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S  16
+/** EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
+ *  Gap between ADC2_ch3 and average initcode
+ */
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S  20
+/** EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
+ *  Gap between ADC2_ch4 and average initcode
+ */
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S  24
+/** EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
+ *  Gap between ADC2_ch5 and average initcode
+ */
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S  28
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMPERATURE_SENSOR    0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_M  (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
+#define EFUSE_TEMPERATURE_SENSOR_V  0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_S  0
+/** EFUSE_RESERVED_10_105 : R; bitpos: [31:9]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_10_105    0x007FFFFFU
+#define EFUSE_RESERVED_10_105_M  (EFUSE_RESERVED_10_105_V << EFUSE_RESERVED_10_105_S)
+#define EFUSE_RESERVED_10_105_V  0x007FFFFFU
+#define EFUSE_RESERVED_10_105_S  9
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_ERR0_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  Indicates a programming error of RD_DIS.
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0;
+ *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
+ */
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR    (BIT(7))
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S)
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S  7
+/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
+ */
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR    (BIT(8))
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S)
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S  8
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  Indicates a programming error of DIS_USB_JTAG.
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
+ *  Indicates a programming error of POWERGLITCH_EN.
+ */
+#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_ERR_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
+/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of DIS_TWAI.
+ */
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
+#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
+#define EFUSE_DIS_TWAI_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  Indicates a programming error of JTAG_SEL_ENABLE.
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  Indicates a programming error of SOFT_DIS_JTAG.
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DIS_PAD_JTAG.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DEVICE_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  Indicates a programming error of USB_DEVICE_DREFH.
+ */
+#define EFUSE_USB_DEVICE_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_M  (EFUSE_USB_DEVICE_DREFH_ERR_V << EFUSE_USB_DEVICE_DREFH_ERR_S)
+#define EFUSE_USB_DEVICE_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_S  21
+/** EFUSE_USB_OTG11_DREFH_ERR : RO; bitpos: [24:23]; default: 0;
+ *  Indicates a programming error of USB_OTG11_DREFH.
+ */
+#define EFUSE_USB_OTG11_DREFH_ERR    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_M  (EFUSE_USB_OTG11_DREFH_ERR_V << EFUSE_USB_OTG11_DREFH_ERR_S)
+#define EFUSE_USB_OTG11_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_S  23
+/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of USB_PHY_SEL.
+ */
+#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
+#define EFUSE_USB_PHY_SEL_ERR_M  (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
+#define EFUSE_USB_PHY_SEL_ERR_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_ERR_S  25
+/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0;
+ *  Indicates a programming error of HUK_GEN_STATE_LOW.
+ */
+#define EFUSE_HUK_GEN_STATE_LOW_ERR    0x0000003FU
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_M  (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S)
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_V  0x0000003FU
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_S  26
+
+/** EFUSE_RD_REPEAT_ERR1_REG register
+ *  Programming error record register 1 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0;
+ *  Indicates a programming error of HUK_GEN_STATE_HIGH.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR    0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S)
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V  0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0;
+ *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  3
+/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0;
+ *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  5
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0;
+ *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  9
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  13
+/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of XTS_KEY_LENGTH_256.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S)
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  14
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of WDT_DELAY_SEL.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_0.
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_1.
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR2_REG register
+ *  Programming error record register 2 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_2.
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_3.
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_4.
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_5.
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of SEC_DPA_LEVEL.
+ */
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
+/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0;
+ *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
+ */
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M  (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S)
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V  0x00000001U
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S  18
+/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of CRYPT_DPA_ENABLE.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_EN.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of FLASH_TYPE.
+ */
+#define EFUSE_FLASH_TYPE_ERR    (BIT(23))
+#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
+#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
+#define EFUSE_FLASH_TYPE_ERR_S  23
+/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0;
+ *  Indicates a programming error of FLASH_PAGE_SIZE.
+ */
+#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
+#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_S  24
+/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of FLASH_ECC_EN.
+ */
+#define EFUSE_FLASH_ECC_EN_ERR    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
+#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_ERR_S  26
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0;
+ *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  27
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of FLASH_TPUW.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR3_REG register
+ *  Programming error record register 3 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  Indicates a programming error of DIS_DIRECT_BOOT.
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
+/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
+ *  TBD
+ */
+#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
+#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_ERR_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of UART_PRINT_CONTROL.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of FORCE_SEND_RESUME.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
+ *  Indicates a programming error of SECURE VERSION.
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
+/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of HYS_EN_PAD.
+ */
+#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
+#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
+#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_ERR_S  26
+/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0;
+ *  Indicates a programming error of DCDC_VSET.
+ */
+#define EFUSE_DCDC_VSET_ERR    0x0000001FU
+#define EFUSE_DCDC_VSET_ERR_M  (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S)
+#define EFUSE_DCDC_VSET_ERR_V  0x0000001FU
+#define EFUSE_DCDC_VSET_ERR_S  27
+
+/** EFUSE_RD_REPEAT_ERR4_REG register
+ *  Programming error record register 4 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
+/** EFUSE_PXA0_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+ */
+#define EFUSE_PXA0_TIEH_SEL_0_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_M  (EFUSE_PXA0_TIEH_SEL_0_ERR_V << EFUSE_PXA0_TIEH_SEL_0_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_S  0
+/** EFUSE_PXA0_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_1.
+ */
+#define EFUSE_PXA0_TIEH_SEL_1_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_M  (EFUSE_PXA0_TIEH_SEL_1_ERR_V << EFUSE_PXA0_TIEH_SEL_1_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_S  2
+/** EFUSE_PXA0_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_2.
+ */
+#define EFUSE_PXA0_TIEH_SEL_2_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_M  (EFUSE_PXA0_TIEH_SEL_2_ERR_V << EFUSE_PXA0_TIEH_SEL_2_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_S  4
+/** EFUSE_PXA0_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_3.
+ */
+#define EFUSE_PXA0_TIEH_SEL_3_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_M  (EFUSE_PXA0_TIEH_SEL_3_ERR_V << EFUSE_PXA0_TIEH_SEL_3_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_S  6
+/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  8
+/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0;
+ *  Indicates a programming error of USB_DEVICE_DREFL.
+ */
+#define EFUSE_USB_DEVICE_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_ERR_M  (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S)
+#define EFUSE_USB_DEVICE_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_ERR_S  12
+/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0;
+ *  Indicates a programming error of USB_OTG11_DREFL.
+ */
+#define EFUSE_USB_OTG11_DREFL_ERR    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_ERR_M  (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S)
+#define EFUSE_USB_OTG11_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_ERR_S  14
+/** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0;
+ *  Indicates a programming error of HP_PWR_SRC_SEL.
+ */
+#define EFUSE_HP_PWR_SRC_SEL_ERR    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_ERR_M  (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S)
+#define EFUSE_HP_PWR_SRC_SEL_ERR_V  0x00000001U
+#define EFUSE_HP_PWR_SRC_SEL_ERR_S  18
+/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DCDC_VSET_EN.
+ */
+#define EFUSE_DCDC_VSET_EN_ERR    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_ERR_M  (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S)
+#define EFUSE_DCDC_VSET_EN_ERR_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_ERR_S  19
+/** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_WDT.
+ */
+#define EFUSE_DIS_WDT_ERR    (BIT(20))
+#define EFUSE_DIS_WDT_ERR_M  (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S)
+#define EFUSE_DIS_WDT_ERR_V  0x00000001U
+#define EFUSE_DIS_WDT_ERR_S  20
+/** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of DIS_SWD.
+ */
+#define EFUSE_DIS_SWD_ERR    (BIT(21))
+#define EFUSE_DIS_SWD_ERR_M  (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S)
+#define EFUSE_DIS_SWD_ERR_V  0x00000001U
+#define EFUSE_DIS_SWD_ERR_S  21
+
+/** EFUSE_RD_RS_ERR0_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_MAC_SYS_ERR_NUM    0x00000007U
+#define EFUSE_MAC_SYS_ERR_NUM_M  (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S)
+#define EFUSE_MAC_SYS_ERR_NUM_V  0x00000007U
+#define EFUSE_MAC_SYS_ERR_NUM_S  0
+/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_MAC_SYS_FAIL    (BIT(3))
+#define EFUSE_MAC_SYS_FAIL_M  (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S)
+#define EFUSE_MAC_SYS_FAIL_V  0x00000001U
+#define EFUSE_MAC_SYS_FAIL_S  3
+/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART1_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART1_ERR_NUM_M  (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S)
+#define EFUSE_SYS_PART1_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART1_ERR_NUM_S  4
+/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART1_FAIL    (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART1_FAIL_S  7
+/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the user data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_USR_DATA_FAIL_S  11
+/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY0_ERR_NUM    0x00000007U
+#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY0_ERR_NUM_S  12
+/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
+ *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+ *  key0 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY0_FAIL    (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V  0x00000001U
+#define EFUSE_KEY0_FAIL_S  15
+/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY1_ERR_NUM    0x00000007U
+#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY1_ERR_NUM_S  16
+/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
+ *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+ *  key1 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY1_FAIL    (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V  0x00000001U
+#define EFUSE_KEY1_FAIL_S  19
+/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY2_ERR_NUM    0x00000007U
+#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY2_ERR_NUM_S  20
+/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
+ *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+ *  key2 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY2_FAIL    (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V  0x00000001U
+#define EFUSE_KEY2_FAIL_S  23
+/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY3_ERR_NUM    0x00000007U
+#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY3_ERR_NUM_S  24
+/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
+ *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+ *  key3 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY3_FAIL    (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V  0x00000001U
+#define EFUSE_KEY3_FAIL_S  27
+/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY4_ERR_NUM    0x00000007U
+#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY4_ERR_NUM_S  28
+/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
+ *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+ *  key4 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY4_FAIL    (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V  0x00000001U
+#define EFUSE_KEY4_FAIL_S  31
+
+/** EFUSE_RD_RS_ERR1_REG register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY5_ERR_NUM    0x00000007U
+#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY5_ERR_NUM_S  0
+/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+ *  key5 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY5_FAIL    (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V  0x00000001U
+#define EFUSE_KEY5_FAIL_S  3
+/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART2_FAIL    (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
+#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART2_FAIL_S  7
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to force enable eFuse register configuration clock signal.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
+ *  Configures which block to use for ECDSA key output.
+ */
+#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
+#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_S  16
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
+ *  Indicates the number of block valid bit.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
+ *  Indicates which block is used for ECDSA key output.
+ */
+#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
+#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_S  20
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the read hold time.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
+#define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures the read time.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures the read setup time.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15;
+ *  Configures the waiting time of reading eFuse memory.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the programming setup time.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
+#define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
+ *  Configures the programming hold time.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  24
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160;
+ *  Configures the active programming time.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
+
+/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
+/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to bypass reed solomon correction step.
+ */
+#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
+#define EFUSE_BYPASS_RS_CORRECTION_S  0
+/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
+ *  Configures block number of programming twice operation.
+ */
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
+ *  Set this bit to update multi-bit register signals.
+ */
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
+#define EFUSE_UPDATE_V  0x00000001U
+#define EFUSE_UPDATE_S  12
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
+ *  Configures the inactive programming time.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  13
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+/** EFUSE_APB2OTP_WR_DIS_REG register
+ *  eFuse apb2otp block0 data register1.
+ */
+#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x800)
+/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 write disable data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
+ *  eFuse apb2otp block0 data register2.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x804)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
+ *  eFuse apb2otp block0 data register3.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x808)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
+ *  eFuse apb2otp block0 data register4.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x80c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
+ *  eFuse apb2otp block0 data register5.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x810)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
+ *  eFuse apb2otp block0 data register6.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x814)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
+ *  eFuse apb2otp block0 data register7.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x818)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
+ *  eFuse apb2otp block0 data register8.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x81c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
+ *  eFuse apb2otp block0 data register9.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x820)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
+ *  eFuse apb2otp block0 data register10.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x824)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
+ *  eFuse apb2otp block0 data register11.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x828)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
+ *  eFuse apb2otp block0 data register12.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x82c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
+ *  eFuse apb2otp block0 data register13.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x830)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
+ *  eFuse apb2otp block0 data register14.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x834)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
+ *  eFuse apb2otp block0 data register15.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x838)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
+ *  eFuse apb2otp block0 data register16.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x83c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
+ *  eFuse apb2otp block0 data register17.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x840)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
+ *  eFuse apb2otp block0 data register18.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x844)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
+ *  eFuse apb2otp block0 data register19.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x848)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
+ *  eFuse apb2otp block0 data register20.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x84c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
+ *  eFuse apb2otp block0 data register21.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x850)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W1_REG register
+ *  eFuse apb2otp block1 data register1.
+ */
+#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x854)
+/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
+#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK1_W2_REG register
+ *  eFuse apb2otp block1 data register2.
+ */
+#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x858)
+/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
+#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK1_W3_REG register
+ *  eFuse apb2otp block1 data register3.
+ */
+#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x85c)
+/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
+#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK1_W4_REG register
+ *  eFuse apb2otp block1 data register4.
+ */
+#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x860)
+/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
+#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK1_W5_REG register
+ *  eFuse apb2otp block1 data register5.
+ */
+#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x864)
+/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
+#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W6_REG register
+ *  eFuse apb2otp block1 data register6.
+ */
+#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x868)
+/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
+#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_S  0
+
+/** EFUSE_APB2OTP_BLK1_W7_REG register
+ *  eFuse apb2otp block1 data register7.
+ */
+#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x86c)
+/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
+#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_S  0
+
+/** EFUSE_APB2OTP_BLK1_W8_REG register
+ *  eFuse apb2otp block1 data register8.
+ */
+#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x870)
+/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
+#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_S  0
+
+/** EFUSE_APB2OTP_BLK1_W9_REG register
+ *  eFuse apb2otp block1 data register9.
+ */
+#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x874)
+/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
+#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W1_REG register
+ *  eFuse apb2otp block2 data register1.
+ */
+#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x878)
+/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
+#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK2_W2_REG register
+ *  eFuse apb2otp block2 data register2.
+ */
+#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x87c)
+/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
+#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK2_W3_REG register
+ *  eFuse apb2otp block2 data register3.
+ */
+#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x880)
+/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
+#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK2_W4_REG register
+ *  eFuse apb2otp block2 data register4.
+ */
+#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x884)
+/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
+#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK2_W5_REG register
+ *  eFuse apb2otp block2 data register5.
+ */
+#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x888)
+/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
+#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK2_W6_REG register
+ *  eFuse apb2otp block2 data register6.
+ */
+#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x88c)
+/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
+#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_S  0
+
+/** EFUSE_APB2OTP_BLK2_W7_REG register
+ *  eFuse apb2otp block2 data register7.
+ */
+#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x890)
+/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
+#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_S  0
+
+/** EFUSE_APB2OTP_BLK2_W8_REG register
+ *  eFuse apb2otp block2 data register8.
+ */
+#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x894)
+/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
+#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_S  0
+
+/** EFUSE_APB2OTP_BLK2_W9_REG register
+ *  eFuse apb2otp block2 data register9.
+ */
+#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x898)
+/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
+#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W10_REG register
+ *  eFuse apb2otp block2 data register10.
+ */
+#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x89c)
+/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
+#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_S  0
+
+/** EFUSE_APB2OTP_BLK2_W11_REG register
+ *  eFuse apb2otp block2 data register11.
+ */
+#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x8a0)
+/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
+#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_S  0
+
+/** EFUSE_APB2OTP_BLK3_W1_REG register
+ *  eFuse apb2otp block3 data register1.
+ */
+#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x8a4)
+/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
+#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK3_W2_REG register
+ *  eFuse apb2otp block3 data register2.
+ */
+#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x8a8)
+/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
+#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK3_W3_REG register
+ *  eFuse apb2otp block3 data register3.
+ */
+#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x8ac)
+/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
+#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK3_W4_REG register
+ *  eFuse apb2otp block3 data register4.
+ */
+#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x8b0)
+/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
+#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK3_W5_REG register
+ *  eFuse apb2otp block3 data register5.
+ */
+#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x8b4)
+/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
+#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK3_W6_REG register
+ *  eFuse apb2otp block3 data register6.
+ */
+#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x8b8)
+/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
+#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_S  0
+
+/** EFUSE_APB2OTP_BLK3_W7_REG register
+ *  eFuse apb2otp block3 data register7.
+ */
+#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x8bc)
+/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
+#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_S  0
+
+/** EFUSE_APB2OTP_BLK3_W8_REG register
+ *  eFuse apb2otp block3 data register8.
+ */
+#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x8c0)
+/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
+#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_S  0
+
+/** EFUSE_APB2OTP_BLK3_W9_REG register
+ *  eFuse apb2otp block3 data register9.
+ */
+#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x8c4)
+/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
+#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_S  0
+
+/** EFUSE_APB2OTP_BLK3_W10_REG register
+ *  eFuse apb2otp block3 data register10.
+ */
+#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x8c8)
+/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
+#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_S  0
+
+/** EFUSE_APB2OTP_BLK3_W11_REG register
+ *  eFuse apb2otp block3 data register11.
+ */
+#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x8cc)
+/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
+#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_S  0
+
+/** EFUSE_APB2OTP_BLK4_W1_REG register
+ *  eFuse apb2otp block4 data register1.
+ */
+#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x8d0)
+/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
+#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK4_W2_REG register
+ *  eFuse apb2otp block4 data register2.
+ */
+#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x8d4)
+/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
+#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK4_W3_REG register
+ *  eFuse apb2otp block4 data register3.
+ */
+#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x8d8)
+/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
+#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK4_W4_REG register
+ *  eFuse apb2otp block4 data register4.
+ */
+#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x8dc)
+/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
+#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK4_W5_REG register
+ *  eFuse apb2otp block4 data register5.
+ */
+#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x8e0)
+/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
+#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK4_W6_REG register
+ *  eFuse apb2otp block4 data register6.
+ */
+#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x8e4)
+/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
+#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_S  0
+
+/** EFUSE_APB2OTP_BLK4_W7_REG register
+ *  eFuse apb2otp block4 data register7.
+ */
+#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x8e8)
+/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
+#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_S  0
+
+/** EFUSE_APB2OTP_BLK4_W8_REG register
+ *  eFuse apb2otp block4 data register8.
+ */
+#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x8ec)
+/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
+#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_S  0
+
+/** EFUSE_APB2OTP_BLK4_W9_REG register
+ *  eFuse apb2otp block4 data register9.
+ */
+#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x8f0)
+/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
+#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_S  0
+
+/** EFUSE_APB2OTP_BLK4_W10_REG register
+ *  eFuse apb2otp block4 data registe10.
+ */
+#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x8f4)
+/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
+#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_S  0
+
+/** EFUSE_APB2OTP_BLK4_W11_REG register
+ *  eFuse apb2otp block4 data register11.
+ */
+#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x8f8)
+/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
+#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_S  0
+
+/** EFUSE_APB2OTP_BLK5_W1_REG register
+ *  eFuse apb2otp block5 data register1.
+ */
+#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x8fc)
+/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
+#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_S  0
+
+/** EFUSE_APB2OTP_BLK5_W2_REG register
+ *  eFuse apb2otp block5 data register2.
+ */
+#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x900)
+/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
+#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_S  0
+
+/** EFUSE_APB2OTP_BLK5_W3_REG register
+ *  eFuse apb2otp block5 data register3.
+ */
+#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x904)
+/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
+#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_S  0
+
+/** EFUSE_APB2OTP_BLK5_W4_REG register
+ *  eFuse apb2otp block5 data register4.
+ */
+#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x908)
+/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
+#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_S  0
+
+/** EFUSE_APB2OTP_BLK5_W5_REG register
+ *  eFuse apb2otp block5 data register5.
+ */
+#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x90c)
+/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
+#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_S  0
+
+/** EFUSE_APB2OTP_BLK5_W6_REG register
+ *  eFuse apb2otp block5 data register6.
+ */
+#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x910)
+/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
+#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_S  0
+
+/** EFUSE_APB2OTP_BLK5_W7_REG register
+ *  eFuse apb2otp block5 data register7.
+ */
+#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x914)
+/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
+#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_S  0
+
+/** EFUSE_APB2OTP_BLK5_W8_REG register
+ *  eFuse apb2otp block5 data register8.
+ */
+#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x918)
+/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
+#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_S  0
+
+/** EFUSE_APB2OTP_BLK5_W9_REG register
+ *  eFuse apb2otp block5 data register9.
+ */
+#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x91c)
+/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
+#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_S  0
+
+/** EFUSE_APB2OTP_BLK5_W10_REG register
+ *  eFuse apb2otp block5 data register10.
+ */
+#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x920)
+/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
+#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_S  0
+
+/** EFUSE_APB2OTP_BLK5_W11_REG register
+ *  eFuse apb2otp block5 data register11.
+ */
+#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x924)
+/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
+#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_S  0
+
+/** EFUSE_APB2OTP_BLK6_W1_REG register
+ *  eFuse apb2otp block6 data register1.
+ */
+#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x928)
+/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
+#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_S  0
+
+/** EFUSE_APB2OTP_BLK6_W2_REG register
+ *  eFuse apb2otp block6 data register2.
+ */
+#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x92c)
+/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
+#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_S  0
+
+/** EFUSE_APB2OTP_BLK6_W3_REG register
+ *  eFuse apb2otp block6 data register3.
+ */
+#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x930)
+/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
+#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_S  0
+
+/** EFUSE_APB2OTP_BLK6_W4_REG register
+ *  eFuse apb2otp block6 data register4.
+ */
+#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x934)
+/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
+#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_S  0
+
+/** EFUSE_APB2OTP_BLK6_W5_REG register
+ *  eFuse apb2otp block6 data register5.
+ */
+#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x938)
+/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
+#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_S  0
+
+/** EFUSE_APB2OTP_BLK6_W6_REG register
+ *  eFuse apb2otp block6 data register6.
+ */
+#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x93c)
+/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
+#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_S  0
+
+/** EFUSE_APB2OTP_BLK6_W7_REG register
+ *  eFuse apb2otp block6 data register7.
+ */
+#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x940)
+/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
+#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_S  0
+
+/** EFUSE_APB2OTP_BLK6_W8_REG register
+ *  eFuse apb2otp block6 data register8.
+ */
+#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x944)
+/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
+#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_S  0
+
+/** EFUSE_APB2OTP_BLK6_W9_REG register
+ *  eFuse apb2otp block6 data register9.
+ */
+#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x948)
+/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
+#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_S  0
+
+/** EFUSE_APB2OTP_BLK6_W10_REG register
+ *  eFuse apb2otp block6 data register10.
+ */
+#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x94c)
+/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
+#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_S  0
+
+/** EFUSE_APB2OTP_BLK6_W11_REG register
+ *  eFuse apb2otp block6 data register11.
+ */
+#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x950)
+/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
+#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_S  0
+
+/** EFUSE_APB2OTP_BLK7_W1_REG register
+ *  eFuse apb2otp block7 data register1.
+ */
+#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x954)
+/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
+#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_S  0
+
+/** EFUSE_APB2OTP_BLK7_W2_REG register
+ *  eFuse apb2otp block7 data register2.
+ */
+#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x958)
+/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
+#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_S  0
+
+/** EFUSE_APB2OTP_BLK7_W3_REG register
+ *  eFuse apb2otp block7 data register3.
+ */
+#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x95c)
+/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
+#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_S  0
+
+/** EFUSE_APB2OTP_BLK7_W4_REG register
+ *  eFuse apb2otp block7 data register4.
+ */
+#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x960)
+/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
+#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_S  0
+
+/** EFUSE_APB2OTP_BLK7_W5_REG register
+ *  eFuse apb2otp block7 data register5.
+ */
+#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x964)
+/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
+#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_S  0
+
+/** EFUSE_APB2OTP_BLK7_W6_REG register
+ *  eFuse apb2otp block7 data register6.
+ */
+#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x968)
+/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
+#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_S  0
+
+/** EFUSE_APB2OTP_BLK7_W7_REG register
+ *  eFuse apb2otp block7 data register7.
+ */
+#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x96c)
+/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
+#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_S  0
+
+/** EFUSE_APB2OTP_BLK7_W8_REG register
+ *  eFuse apb2otp block7 data register8.
+ */
+#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x970)
+/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
+#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_S  0
+
+/** EFUSE_APB2OTP_BLK7_W9_REG register
+ *  eFuse apb2otp block7 data register9.
+ */
+#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x974)
+/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
+#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_S  0
+
+/** EFUSE_APB2OTP_BLK7_W10_REG register
+ *  eFuse apb2otp block7 data register10.
+ */
+#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x978)
+/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
+#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_S  0
+
+/** EFUSE_APB2OTP_BLK7_W11_REG register
+ *  eFuse apb2otp block7 data register11.
+ */
+#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x97c)
+/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
+#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_S  0
+
+/** EFUSE_APB2OTP_BLK8_W1_REG register
+ *  eFuse apb2otp block8 data register1.
+ */
+#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x980)
+/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
+#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_S  0
+
+/** EFUSE_APB2OTP_BLK8_W2_REG register
+ *  eFuse apb2otp block8 data register2.
+ */
+#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x984)
+/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
+#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_S  0
+
+/** EFUSE_APB2OTP_BLK8_W3_REG register
+ *  eFuse apb2otp block8 data register3.
+ */
+#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x988)
+/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
+#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_S  0
+
+/** EFUSE_APB2OTP_BLK8_W4_REG register
+ *  eFuse apb2otp block8 data register4.
+ */
+#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x98c)
+/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
+#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_S  0
+
+/** EFUSE_APB2OTP_BLK8_W5_REG register
+ *  eFuse apb2otp block8 data register5.
+ */
+#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x990)
+/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
+#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_S  0
+
+/** EFUSE_APB2OTP_BLK8_W6_REG register
+ *  eFuse apb2otp block8 data register6.
+ */
+#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x994)
+/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
+#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_S  0
+
+/** EFUSE_APB2OTP_BLK8_W7_REG register
+ *  eFuse apb2otp block8 data register7.
+ */
+#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x998)
+/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
+#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_S  0
+
+/** EFUSE_APB2OTP_BLK8_W8_REG register
+ *  eFuse apb2otp block8 data register8.
+ */
+#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x99c)
+/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
+#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_S  0
+
+/** EFUSE_APB2OTP_BLK8_W9_REG register
+ *  eFuse apb2otp block8 data register9.
+ */
+#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x9a0)
+/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
+#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_S  0
+
+/** EFUSE_APB2OTP_BLK8_W10_REG register
+ *  eFuse apb2otp block8 data register10.
+ */
+#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x9a4)
+/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
+#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_S  0
+
+/** EFUSE_APB2OTP_BLK8_W11_REG register
+ *  eFuse apb2otp block8 data register11.
+ */
+#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x9a8)
+/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
+#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_S  0
+
+/** EFUSE_APB2OTP_BLK9_W1_REG register
+ *  eFuse apb2otp block9 data register1.
+ */
+#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x9ac)
+/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
+#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_S  0
+
+/** EFUSE_APB2OTP_BLK9_W2_REG register
+ *  eFuse apb2otp block9 data register2.
+ */
+#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x9b0)
+/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
+#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_S  0
+
+/** EFUSE_APB2OTP_BLK9_W3_REG register
+ *  eFuse apb2otp block9 data register3.
+ */
+#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x9b4)
+/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
+#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_S  0
+
+/** EFUSE_APB2OTP_BLK9_W4_REG register
+ *  eFuse apb2otp block9 data register4.
+ */
+#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x9b8)
+/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
+#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_S  0
+
+/** EFUSE_APB2OTP_BLK9_W5_REG register
+ *  eFuse apb2otp block9 data register5.
+ */
+#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x9bc)
+/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
+#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_S  0
+
+/** EFUSE_APB2OTP_BLK9_W6_REG register
+ *  eFuse apb2otp block9 data register6.
+ */
+#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x9c0)
+/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
+#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_S  0
+
+/** EFUSE_APB2OTP_BLK9_W7_REG register
+ *  eFuse apb2otp block9 data register7.
+ */
+#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x9c4)
+/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
+#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_S  0
+
+/** EFUSE_APB2OTP_BLK9_W8_REG register
+ *  eFuse apb2otp block9 data register8.
+ */
+#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x9c8)
+/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
+#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_S  0
+
+/** EFUSE_APB2OTP_BLK9_W9_REG register
+ *  eFuse apb2otp block9 data register9.
+ */
+#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x9cc)
+/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
+#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_S  0
+
+/** EFUSE_APB2OTP_BLK9_W10_REG register
+ *  eFuse apb2otp block9 data register10.
+ */
+#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x9d0)
+/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
+#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_S  0
+
+/** EFUSE_APB2OTP_BLK9_W11_REG register
+ *  eFuse apb2otp block9 data register11.
+ */
+#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x9d4)
+/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
+#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_S  0
+
+/** EFUSE_APB2OTP_BLK10_W1_REG register
+ *  eFuse apb2otp block10 data register1.
+ */
+#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x9d8)
+/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
+#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_S  0
+
+/** EFUSE_APB2OTP_BLK10_W2_REG register
+ *  eFuse apb2otp block10 data register2.
+ */
+#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x9dc)
+/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
+#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_S  0
+
+/** EFUSE_APB2OTP_BLK10_W3_REG register
+ *  eFuse apb2otp block10 data register3.
+ */
+#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x9e0)
+/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
+#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_S  0
+
+/** EFUSE_APB2OTP_BLK10_W4_REG register
+ *  eFuse apb2otp block10 data register4.
+ */
+#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x9e4)
+/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
+#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_S  0
+
+/** EFUSE_APB2OTP_BLK10_W5_REG register
+ *  eFuse apb2otp block10 data register5.
+ */
+#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x9e8)
+/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
+#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_S  0
+
+/** EFUSE_APB2OTP_BLK10_W6_REG register
+ *  eFuse apb2otp block10 data register6.
+ */
+#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x9ec)
+/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
+#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_S  0
+
+/** EFUSE_APB2OTP_BLK10_W7_REG register
+ *  eFuse apb2otp block10 data register7.
+ */
+#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x9f0)
+/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
+#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_S  0
+
+/** EFUSE_APB2OTP_BLK10_W8_REG register
+ *  eFuse apb2otp block10 data register8.
+ */
+#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x9f4)
+/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
+#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_S  0
+
+/** EFUSE_APB2OTP_BLK10_W9_REG register
+ *  eFuse apb2otp block10 data register9.
+ */
+#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x9f8)
+/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
+#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_S  0
+
+/** EFUSE_APB2OTP_BLK10_W10_REG register
+ *  eFuse apb2otp block10 data register10.
+ */
+#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x9fc)
+/** EFUSE_APB2OTP_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK19_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK19_W10_M  (EFUSE_APB2OTP_BLOCK19_W10_V << EFUSE_APB2OTP_BLOCK19_W10_S)
+#define EFUSE_APB2OTP_BLOCK19_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK19_W10_S  0
+
+/** EFUSE_APB2OTP_BLK10_W11_REG register
+ *  eFuse apb2otp block10 data register11.
+ */
+#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0xa00)
+/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
+#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_S  0
+
+/** EFUSE_APB2OTP_EN_REG register
+ *  eFuse apb2otp enable configuration register.
+ */
+#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0xa08)
+/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
+ *  Apb2otp mode enable signal.
+ */
+#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
+#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
+#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
+#define EFUSE_APB2OTP_APB2OTP_EN_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/efuse_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/efuse_struct.h
new file mode 100644
index 0000000000..b153ab070f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/efuse_struct.h
@@ -0,0 +1,4737 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// TODO: IDF-13421
+
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: ******** Registers */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register 0.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled or
+         *  enabled. 1: Disabled. 0 Enabled.
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register 1.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t rd_dis:7;
+        /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0;
+         *  Enable usb device exchange pins of D+ and D-.
+         */
+        uint32_t usb_device_exchg_pins:1;
+        /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0;
+         *  Enable usb otg11 exchange pins of D+ and D-.
+         */
+        uint32_t usb_otg11_exchg_pins:1;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** powerglitch_en : RO; bitpos: [10]; default: 0;
+         *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+         */
+        uint32_t powerglitch_en:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Represents whether the function that forces chip into download mode is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+         *  boot_mode_download.
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+         *  is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+         *  enabled.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+         *  enabled.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+         *  mode). 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_device_drefh : RO; bitpos: [22:21]; default: 0;
+         *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_device_drefh:2;
+        /** usb_otg11_drefh : RO; bitpos: [24:23]; default: 0;
+         *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_otg11_drefh:2;
+        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
+         *  TBD
+         */
+        uint32_t usb_phy_sel:1;
+        /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0;
+         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t km_huk_gen_state_low:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  BLOCK0 data register 2.
+ */
+typedef union {
+    struct {
+        /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0;
+         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t km_huk_gen_state_high:3;
+        /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0;
+         *  Set bits to control key manager random number switch cycle. 0: control by register.
+         *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
+         */
+        uint32_t km_rnd_switch_cycle:2;
+        /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
+         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         */
+        uint32_t km_deploy_only_once:4;
+        /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
+         *  Set each bit to control whether corresponding key must come from key manager.. 1 is
+         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         */
+        uint32_t force_use_key_manager_key:4;
+        /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable software written init key, and force use efuse_init_key.
+         */
+        uint32_t force_disable_sw_init_key:1;
+        /** xts_key_length_256 : RO; bitpos: [14]; default: 0;
+         *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
+         */
+        uint32_t xts_key_length_256:1;
+        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_79:1;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+         *  selected. 0: not selected.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+         *  1: enabled. Even number of 1: disabled.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Represents the purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Represents the purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  BLOCK0 data register 3.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Represents the purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Represents the purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Represents the purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Represents the purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
+         *  Represents the spa secure level by configuring the clock random divide mode.
+         */
+        uint32_t sec_dpa_level:2;
+        /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0;
+         *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+         *  0: not force used.
+         */
+        uint32_t ecdsa_enable_soft_k:1;
+        /** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
+         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+         */
+        uint32_t crypt_dpa_enable:1;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** rd_reserve_0_118 : RW; bitpos: [22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_118:1;
+        /** flash_type : RO; bitpos: [23]; default: 0;
+         *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
+         */
+        uint32_t flash_type:1;
+        /** flash_page_size : RO; bitpos: [25:24]; default: 0;
+         *  Set flash page size.
+         */
+        uint32_t flash_page_size:2;
+        /** flash_ecc_en : RO; bitpos: [26]; default: 0;
+         *  Set this bit to enable ecc for flash boot.
+         */
+        uint32_t flash_ecc_en:1;
+        /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
+         *  Set this bit to disable download via USB-OTG.
+         */
+        uint32_t dis_usb_otg_download_mode:1;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Represents the flash waiting time after power-up, in unit of ms. When the value
+         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+         *  is 2 times the programmed value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  BLOCK0 data register 4.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+         *  0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** lock_km_key : RO; bitpos: [3]; default: 0;
+         *  TBD
+         */
+        uint32_t lock_km_key:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+         *  disabled.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Represents the type of UART printing. 00: force enable printing. 01: enable
+         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+         *  at high level. 11: force disable printing.
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [8]; default: 0;
+         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+         *  forced. 0:not forced.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [24:9]; default: 0;
+         *  Represents the version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
+         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad : RO; bitpos: [26]; default: 0;
+         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
+         *  enabled. 0:disabled.
+         */
+        uint32_t hys_en_pad:1;
+        /** dcdc_vset : RO; bitpos: [31:27]; default: 0;
+         *  Set the dcdc voltage default.
+         */
+        uint32_t dcdc_vset:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  BLOCK0 data register 5.
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
+         *  TBD
+         */
+        uint32_t pxa0_tieh_sel_0:2;
+        /** pxa0_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
+         *  TBD.
+         */
+        uint32_t pxa0_tieh_sel_1:2;
+        /** pxa0_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
+         *  TBD.
+         */
+        uint32_t pxa0_tieh_sel_2:2;
+        /** pxa0_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
+         *  TBD.
+         */
+        uint32_t pxa0_tieh_sel_3:2;
+        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
+         *  TBD.
+         */
+        uint32_t km_disable_deploy_mode:4;
+        /** usb_device_drefl : RO; bitpos: [13:12]; default: 0;
+         *  Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_device_drefl:2;
+        /** usb_otg11_drefl : RO; bitpos: [15:14]; default: 0;
+         *  Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_otg11_drefl:2;
+        /** rd_reserve_0_176 : RW; bitpos: [17:16]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_176:2;
+        /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
+         *  HP system power source select. 0:LDO. 1: DCDC.
+         */
+        uint32_t hp_pwr_src_sel:1;
+        /** dcdc_vset_en : RO; bitpos: [19]; default: 0;
+         *  Select dcdc vset use efuse_dcdc_vset.
+         */
+        uint32_t dcdc_vset_en:1;
+        /** dis_wdt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable watch dog.
+         */
+        uint32_t dis_wdt:1;
+        /** dis_swd : RO; bitpos: [21]; default: 0;
+         *  Set this bit to disable super-watchdog.
+         */
+        uint32_t dis_swd:1;
+        /** rd_reserve_0_182 : RW; bitpos: [31:22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_182:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_mac_sys_0 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the low 32 bits of MAC address.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_0_reg_t;
+
+/** Type of rd_mac_sys_1 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Stores the high 16 bits of MAC address.
+         */
+        uint32_t mac_1:16;
+        /** reserved_1_16 : RO; bitpos: [31:16]; default: 0;
+         *  Stores the extended bits of MAC address.
+         */
+        uint32_t reserved_1_16:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_1_reg_t;
+
+/** Type of rd_mac_sys_2 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** wafer_version_minor : R; bitpos: [3:0]; default: 0;
+         *  Minor chip version
+         */
+        uint32_t wafer_version_minor:4;
+        /** wafer_version_major_lo : R; bitpos: [5:4]; default: 0;
+         *  Major chip version (lower 2 bits)
+         */
+        uint32_t wafer_version_major_lo:2;
+        /** disable_wafer_version_major : R; bitpos: [6]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** blk_version_minor : R; bitpos: [10:8]; default: 0;
+         *  BLK_VERSION_MINOR of BLOCK2
+         */
+        uint32_t blk_version_minor:3;
+        /** blk_version_major : R; bitpos: [12:11]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2
+         */
+        uint32_t blk_version_major:2;
+        /** psram_cap : R; bitpos: [15:13]; default: 0;
+         *  PSRAM capacity
+         */
+        uint32_t psram_cap:3;
+        /** temp : R; bitpos: [17:16]; default: 0;
+         *  Operating temperature of the ESP chip
+         */
+        uint32_t temp:2;
+        /** psram_vendor : R; bitpos: [19:18]; default: 0;
+         *  PSRAM vendor
+         */
+        uint32_t psram_vendor:2;
+        /** pkg_version : R; bitpos: [22:20]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** wafer_version_major_hi : R; bitpos: [23]; default: 0;
+         *  Major chip version (MSB)
+         */
+        uint32_t wafer_version_major_hi:1;
+        /** ldo_vo1_dref : R; bitpos: [27:24]; default: 0;
+         *  Output VO1 parameter
+         */
+        uint32_t ldo_vo1_dref:4;
+        /** ldo_vo2_dref : R; bitpos: [31:28]; default: 0;
+         *  Output VO2 parameter
+         */
+        uint32_t ldo_vo2_dref:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_2_reg_t;
+
+/** Type of rd_mac_sys_3 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** ldo_vo1_mul : R; bitpos: [2:0]; default: 0;
+         *  Output VO1 parameter
+         */
+        uint32_t ldo_vo1_mul:3;
+        /** ldo_vo2_mul : R; bitpos: [5:3]; default: 0;
+         *  Output VO2 parameter
+         */
+        uint32_t ldo_vo2_mul:3;
+        /** ldo_vo3_k : R; bitpos: [13:6]; default: 0;
+         *  Output VO3 calibration parameter
+         */
+        uint32_t ldo_vo3_k:8;
+        /** ldo_vo3_vos : R; bitpos: [19:14]; default: 0;
+         *  Output VO3 calibration parameter
+         */
+        uint32_t ldo_vo3_vos:6;
+        /** ldo_vo3_c : R; bitpos: [25:20]; default: 0;
+         *  Output VO3 calibration parameter
+         */
+        uint32_t ldo_vo3_c:6;
+        /** ldo_vo4_k : R; bitpos: [31:26]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_k:6;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_3_reg_t;
+
+/** Type of rd_mac_sys_4 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** ldo_vo4_k_1 : R; bitpos: [1:0]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_k_1:2;
+        /** ldo_vo4_vos : R; bitpos: [7:2]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_vos:6;
+        /** ldo_vo4_c : R; bitpos: [13:8]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_c:6;
+        /** reserved_1_142 : R; bitpos: [15:14]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_142:2;
+        /** active_hp_dbias : R; bitpos: [19:16]; default: 0;
+         *  Active HP DBIAS of fixed voltage
+         */
+        uint32_t active_hp_dbias:4;
+        /** active_lp_dbias : R; bitpos: [23:20]; default: 0;
+         *  Active LP DBIAS of fixed voltage
+         */
+        uint32_t active_lp_dbias:4;
+        /** lslp_hp_dbias : R; bitpos: [27:24]; default: 0;
+         *  LSLP HP DBIAS of fixed voltage
+         */
+        uint32_t lslp_hp_dbias:4;
+        /** dslp_dbg : R; bitpos: [31:28]; default: 0;
+         *  DSLP BDG of fixed voltage
+         */
+        uint32_t dslp_dbg:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_4_reg_t;
+
+/** Type of rd_mac_sys_5 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** dslp_lp_dbias : R; bitpos: [4:0]; default: 0;
+         *  DSLP LP DBIAS of fixed voltage
+         */
+        uint32_t dslp_lp_dbias:5;
+        /** lp_dcdc_dbias_vol_gap : R; bitpos: [9:5]; default: 0;
+         *  DBIAS gap between LP and DCDC
+         */
+        uint32_t lp_dcdc_dbias_vol_gap:5;
+        /** reserved_1_170 : R; bitpos: [31:10]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_170:22;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_5_reg_t;
+
+/** Type of rd_sys_part1_data0 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ave_initcode_atten0 : R; bitpos: [9:0]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t adc1_ave_initcode_atten0:10;
+        /** adc1_ave_initcode_atten1 : R; bitpos: [19:10]; default: 0;
+         *  Average initcode of ADC1 atten1
+         */
+        uint32_t adc1_ave_initcode_atten1:10;
+        /** adc1_ave_initcode_atten2 : R; bitpos: [29:20]; default: 0;
+         *  Average initcode of ADC1 atten2
+         */
+        uint32_t adc1_ave_initcode_atten2:10;
+        /** adc1_ave_initcode_atten3 : R; bitpos: [31:30]; default: 0;
+         *  Average initcode of ADC1 atten3
+         */
+        uint32_t adc1_ave_initcode_atten3:2;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ave_initcode_atten3_1 : R; bitpos: [7:0]; default: 0;
+         *  Average initcode of ADC1 atten3
+         */
+        uint32_t adc1_ave_initcode_atten3_1:8;
+        /** adc2_ave_initcode_atten0 : R; bitpos: [17:8]; default: 0;
+         *  Average initcode of ADC2 atten0
+         */
+        uint32_t adc2_ave_initcode_atten0:10;
+        /** adc2_ave_initcode_atten1 : R; bitpos: [27:18]; default: 0;
+         *  Average initcode of ADC2 atten1
+         */
+        uint32_t adc2_ave_initcode_atten1:10;
+        /** adc2_ave_initcode_atten2 : R; bitpos: [31:28]; default: 0;
+         *  Average initcode of ADC2 atten2
+         */
+        uint32_t adc2_ave_initcode_atten2:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc2_ave_initcode_atten2_1 : R; bitpos: [5:0]; default: 0;
+         *  Average initcode of ADC2 atten2
+         */
+        uint32_t adc2_ave_initcode_atten2_1:6;
+        /** adc2_ave_initcode_atten3 : R; bitpos: [15:6]; default: 0;
+         *  Average initcode of ADC2 atten3
+         */
+        uint32_t adc2_ave_initcode_atten3:10;
+        /** adc1_hi_dout_atten0 : R; bitpos: [25:16]; default: 0;
+         *  HI_DOUT of ADC1 atten0
+         */
+        uint32_t adc1_hi_dout_atten0:10;
+        /** adc1_hi_dout_atten1 : R; bitpos: [31:26]; default: 0;
+         *  HI_DOUT of ADC1 atten1
+         */
+        uint32_t adc1_hi_dout_atten1:6;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_hi_dout_atten1_1 : R; bitpos: [3:0]; default: 0;
+         *  HI_DOUT of ADC1 atten1
+         */
+        uint32_t adc1_hi_dout_atten1_1:4;
+        /** adc1_hi_dout_atten2 : R; bitpos: [13:4]; default: 0;
+         *  HI_DOUT of ADC1 atten2
+         */
+        uint32_t adc1_hi_dout_atten2:10;
+        /** adc1_hi_dout_atten3 : R; bitpos: [23:14]; default: 0;
+         *  HI_DOUT of ADC1 atten3
+         */
+        uint32_t adc1_hi_dout_atten3:10;
+        /** reserved_2_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_248:8;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+/** Type of rd_usr_data0 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac:24;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_248:8;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+/** Type of rd_key0_data0 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+/** Type of rd_key1_data0 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+/** Type of rd_key2_data0 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+/** Type of rd_key3_data0 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+/** Type of rd_key4_data0 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+/** Type of rd_key5_data0 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+/** Type of rd_sys_part2_data0 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** adc2_hi_dout_atten0 : R; bitpos: [9:0]; default: 0;
+         *  HI_DOUT of ADC2 atten0
+         */
+        uint32_t adc2_hi_dout_atten0:10;
+        /** adc2_hi_dout_atten1 : R; bitpos: [19:10]; default: 0;
+         *  HI_DOUT of ADC2 atten1
+         */
+        uint32_t adc2_hi_dout_atten1:10;
+        /** adc2_hi_dout_atten2 : R; bitpos: [29:20]; default: 0;
+         *  HI_DOUT of ADC2 atten2
+         */
+        uint32_t adc2_hi_dout_atten2:10;
+        /** adc2_hi_dout_atten3 : R; bitpos: [31:30]; default: 0;
+         *  HI_DOUT of ADC2 atten3
+         */
+        uint32_t adc2_hi_dout_atten3:2;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** adc2_hi_dout_atten3_1 : R; bitpos: [7:0]; default: 0;
+         *  HI_DOUT of ADC2 atten3
+         */
+        uint32_t adc2_hi_dout_atten3_1:8;
+        /** adc1_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
+         *  Gap between ADC1_ch0 and average initcode
+         */
+        uint32_t adc1_ch0_atten0_initcode_diff:4;
+        /** adc1_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
+         *  Gap between ADC1_ch1 and average initcode
+         */
+        uint32_t adc1_ch1_atten0_initcode_diff:4;
+        /** adc1_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
+         *  Gap between ADC1_ch2 and average initcode
+         */
+        uint32_t adc1_ch2_atten0_initcode_diff:4;
+        /** adc1_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
+         *  Gap between ADC1_ch3 and average initcode
+         */
+        uint32_t adc1_ch3_atten0_initcode_diff:4;
+        /** adc1_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
+         *  Gap between ADC1_ch4 and average initcode
+         */
+        uint32_t adc1_ch4_atten0_initcode_diff:4;
+        /** adc1_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
+         *  Gap between ADC1_ch5 and average initcode
+         */
+        uint32_t adc1_ch5_atten0_initcode_diff:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ch6_atten0_initcode_diff : R; bitpos: [3:0]; default: 0;
+         *  Gap between ADC1_ch6 and average initcode
+         */
+        uint32_t adc1_ch6_atten0_initcode_diff:4;
+        /** adc1_ch7_atten0_initcode_diff : R; bitpos: [7:4]; default: 0;
+         *  Gap between ADC1_ch7 and average initcode
+         */
+        uint32_t adc1_ch7_atten0_initcode_diff:4;
+        /** adc2_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
+         *  Gap between ADC2_ch0 and average initcode
+         */
+        uint32_t adc2_ch0_atten0_initcode_diff:4;
+        /** adc2_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
+         *  Gap between ADC2_ch1 and average initcode
+         */
+        uint32_t adc2_ch1_atten0_initcode_diff:4;
+        /** adc2_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
+         *  Gap between ADC2_ch2 and average initcode
+         */
+        uint32_t adc2_ch2_atten0_initcode_diff:4;
+        /** adc2_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
+         *  Gap between ADC2_ch3 and average initcode
+         */
+        uint32_t adc2_ch3_atten0_initcode_diff:4;
+        /** adc2_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
+         *  Gap between ADC2_ch4 and average initcode
+         */
+        uint32_t adc2_ch4_atten0_initcode_diff:4;
+        /** adc2_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
+         *  Gap between ADC2_ch5 and average initcode
+         */
+        uint32_t adc2_ch5_atten0_initcode_diff:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** temperature_sensor : R; bitpos: [8:0]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temperature_sensor:9;
+        /** reserved_10_105 : R; bitpos: [31:9]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_10_105:23;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+/** Type of rd_repeat_err0 register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Indicates a programming error of RD_DIS.
+         */
+        uint32_t rd_dis_err:7;
+        /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0;
+         *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
+         */
+        uint32_t dis_usb_device_exchg_pins_err:1;
+        /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
+         */
+        uint32_t dis_usb_otg11_exchg_pins_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Indicates a programming error of DIS_USB_JTAG.
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** powerglitch_en_err : RO; bitpos: [10]; default: 0;
+         *  Indicates a programming error of POWERGLITCH_EN.
+         */
+        uint32_t powerglitch_en_err:1;
+        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+         */
+        uint32_t dis_usb_serial_jtag_err:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of DIS_TWAI.
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Indicates a programming error of JTAG_SEL_ENABLE.
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Indicates a programming error of SOFT_DIS_JTAG.
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DIS_PAD_JTAG.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_device_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  Indicates a programming error of USB_DEVICE_DREFH.
+         */
+        uint32_t usb_device_drefh_err:2;
+        /** usb_otg11_drefh_err : RO; bitpos: [24:23]; default: 0;
+         *  Indicates a programming error of USB_OTG11_DREFH.
+         */
+        uint32_t usb_otg11_drefh_err:2;
+        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of USB_PHY_SEL.
+         */
+        uint32_t usb_phy_sel_err:1;
+        /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0;
+         *  Indicates a programming error of HUK_GEN_STATE_LOW.
+         */
+        uint32_t huk_gen_state_low_err:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err0_reg_t;
+
+/** Type of rd_repeat_err1 register
+ *  Programming error record register 1 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0;
+         *  Indicates a programming error of HUK_GEN_STATE_HIGH.
+         */
+        uint32_t km_huk_gen_state_high_err:3;
+        /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0;
+         *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
+         */
+        uint32_t km_rnd_switch_cycle_err:2;
+        /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
+         *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+         */
+        uint32_t km_deploy_only_once_err:4;
+        /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
+         *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+         */
+        uint32_t force_use_key_manager_key_err:4;
+        /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+         */
+        uint32_t force_disable_sw_init_key_err:1;
+        /** xts_key_length_256_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of XTS_KEY_LENGTH_256.
+         */
+        uint32_t xts_key_length_256_err:1;
+        uint32_t reserved_15:1;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of WDT_DELAY_SEL.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_0.
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_1.
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err1_reg_t;
+
+/** Type of rd_repeat_err2 register
+ *  Programming error record register 2 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_2.
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_3.
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_4.
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_5.
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of SEC_DPA_LEVEL.
+         */
+        uint32_t sec_dpa_level_err:2;
+        /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0;
+         *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
+         */
+        uint32_t ecdsa_enable_soft_k_err:1;
+        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of CRYPT_DPA_ENABLE.
+         */
+        uint32_t crypt_dpa_enable_err:1;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_EN.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        uint32_t reserved_22:1;
+        /** flash_type_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of FLASH_TYPE.
+         */
+        uint32_t flash_type_err:1;
+        /** flash_page_size_err : RO; bitpos: [25:24]; default: 0;
+         *  Indicates a programming error of FLASH_PAGE_SIZE.
+         */
+        uint32_t flash_page_size_err:2;
+        /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of FLASH_ECC_EN.
+         */
+        uint32_t flash_ecc_en_err:1;
+        /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
+         *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_otg_download_mode_err:1;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of FLASH_TPUW.
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err2_reg_t;
+
+/** Type of rd_repeat_err3 register
+ *  Programming error record register 3 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Indicates a programming error of DIS_DIRECT_BOOT.
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print_err:1;
+        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
+         *  TBD
+         */
+        uint32_t lock_km_key_err:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of UART_PRINT_CONTROL.
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of FORCE_SEND_RESUME.
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
+         *  Indicates a programming error of SECURE VERSION.
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of HYS_EN_PAD.
+         */
+        uint32_t hys_en_pad_err:1;
+        /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0;
+         *  Indicates a programming error of DCDC_VSET.
+         */
+        uint32_t dcdc_vset_err:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err3_reg_t;
+
+/** Type of rd_repeat_err4 register
+ *  Programming error record register 4 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+         */
+        uint32_t pxa0_tieh_sel_0_err:2;
+        /** pxa0_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_1.
+         */
+        uint32_t pxa0_tieh_sel_1_err:2;
+        /** pxa0_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_2.
+         */
+        uint32_t pxa0_tieh_sel_2_err:2;
+        /** pxa0_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_3.
+         */
+        uint32_t pxa0_tieh_sel_3_err:2;
+        /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
+         *  TBD.
+         */
+        uint32_t km_disable_deploy_mode_err:4;
+        /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0;
+         *  Indicates a programming error of USB_DEVICE_DREFL.
+         */
+        uint32_t usb_device_drefl_err:2;
+        /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0;
+         *  Indicates a programming error of USB_OTG11_DREFL.
+         */
+        uint32_t usb_otg11_drefl_err:2;
+        uint32_t reserved_16:2;
+        /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
+         *  Indicates a programming error of HP_PWR_SRC_SEL.
+         */
+        uint32_t hp_pwr_src_sel_err:1;
+        /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DCDC_VSET_EN.
+         */
+        uint32_t dcdc_vset_en_err:1;
+        /** dis_wdt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_WDT.
+         */
+        uint32_t dis_wdt_err:1;
+        /** dis_swd_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of DIS_SWD.
+         */
+        uint32_t dis_swd_err:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err4_reg_t;
+
+/** Type of rd_rs_err0 register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t mac_sys_err_num:3;
+        /** mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t mac_sys_fail:1;
+        /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part1_err_num:3;
+        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part1_fail:1;
+        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t usr_data_err_num:3;
+        /** usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the user data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t usr_data_fail:1;
+        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key0_err_num:3;
+        /** key0_fail : RO; bitpos: [15]; default: 0;
+         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+         *  key0 failed and the number of error bytes is over 6.
+         */
+        uint32_t key0_fail:1;
+        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key1_err_num:3;
+        /** key1_fail : RO; bitpos: [19]; default: 0;
+         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+         *  key1 failed and the number of error bytes is over 6.
+         */
+        uint32_t key1_fail:1;
+        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key2_err_num:3;
+        /** key2_fail : RO; bitpos: [23]; default: 0;
+         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+         *  key2 failed and the number of error bytes is over 6.
+         */
+        uint32_t key2_fail:1;
+        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key3_err_num:3;
+        /** key3_fail : RO; bitpos: [27]; default: 0;
+         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+         *  key3 failed and the number of error bytes is over 6.
+         */
+        uint32_t key3_fail:1;
+        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key4_err_num:3;
+        /** key4_fail : RO; bitpos: [31]; default: 0;
+         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+         *  key4 failed and the number of error bytes is over 6.
+         */
+        uint32_t key4_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_err0_reg_t;
+
+/** Type of rd_rs_err1 register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key5_err_num:3;
+        /** key5_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+         *  key5 failed and the number of error bytes is over 6.
+         */
+        uint32_t key5_fail:1;
+        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part2_err_num:3;
+        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part2_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_err1_reg_t;
+
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
+         *  Configures which block to use for ECDSA key output.
+         */
+        uint32_t cfg_ecdsa_blk:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
+         *  Indicates which block is used for ECDSA key output.
+         */
+        uint32_t cur_ecdsa_blk:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 160;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: EFUSE Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36720720;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
+/** Type of apb2otp_wr_dis register
+ *  eFuse apb2otp block0 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 write disable data.
+         */
+        uint32_t apb2otp_block0_wr_dis:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_wr_dis_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
+/** Type of apb2otp_blk0_backup1_w1 register
+ *  eFuse apb2otp block0 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word1 data.
+         */
+        uint32_t apb2otp_block0_backup1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
+/** Type of apb2otp_blk0_backup1_w2 register
+ *  eFuse apb2otp block0 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word2 data.
+         */
+        uint32_t apb2otp_block0_backup1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
+/** Type of apb2otp_blk0_backup1_w3 register
+ *  eFuse apb2otp block0 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word3 data.
+         */
+        uint32_t apb2otp_block0_backup1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
+/** Type of apb2otp_blk0_backup1_w4 register
+ *  eFuse apb2otp block0 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word4 data.
+         */
+        uint32_t apb2otp_block0_backup1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
+/** Type of apb2otp_blk0_backup1_w5 register
+ *  eFuse apb2otp block0 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word5 data.
+         */
+        uint32_t apb2otp_block0_backup1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
+/** Type of apb2otp_blk0_backup2_w1 register
+ *  eFuse apb2otp block0 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word1 data.
+         */
+        uint32_t apb2otp_block0_backup2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
+/** Type of apb2otp_blk0_backup2_w2 register
+ *  eFuse apb2otp block0 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word2 data.
+         */
+        uint32_t apb2otp_block0_backup2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
+/** Type of apb2otp_blk0_backup2_w3 register
+ *  eFuse apb2otp block0 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word3 data.
+         */
+        uint32_t apb2otp_block0_backup2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
+/** Type of apb2otp_blk0_backup2_w4 register
+ *  eFuse apb2otp block0 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word4 data.
+         */
+        uint32_t apb2otp_block0_backup2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
+/** Type of apb2otp_blk0_backup2_w5 register
+ *  eFuse apb2otp block0 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word5 data.
+         */
+        uint32_t apb2otp_block0_backup2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
+/** Type of apb2otp_blk0_backup3_w1 register
+ *  eFuse apb2otp block0 data register12.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word1 data.
+         */
+        uint32_t apb2otp_block0_backup3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
+/** Type of apb2otp_blk0_backup3_w2 register
+ *  eFuse apb2otp block0 data register13.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word2 data.
+         */
+        uint32_t apb2otp_block0_backup3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
+/** Type of apb2otp_blk0_backup3_w3 register
+ *  eFuse apb2otp block0 data register14.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word3 data.
+         */
+        uint32_t apb2otp_block0_backup3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
+/** Type of apb2otp_blk0_backup3_w4 register
+ *  eFuse apb2otp block0 data register15.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word4 data.
+         */
+        uint32_t apb2otp_block0_backup3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
+/** Type of apb2otp_blk0_backup3_w5 register
+ *  eFuse apb2otp block0 data register16.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word5 data.
+         */
+        uint32_t apb2otp_block0_backup3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
+/** Type of apb2otp_blk0_backup4_w1 register
+ *  eFuse apb2otp block0 data register17.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word1 data.
+         */
+        uint32_t apb2otp_block0_backup4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
+/** Type of apb2otp_blk0_backup4_w2 register
+ *  eFuse apb2otp block0 data register18.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word2 data.
+         */
+        uint32_t apb2otp_block0_backup4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
+/** Type of apb2otp_blk0_backup4_w3 register
+ *  eFuse apb2otp block0 data register19.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word3 data.
+         */
+        uint32_t apb2otp_block0_backup4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
+/** Type of apb2otp_blk0_backup4_w4 register
+ *  eFuse apb2otp block0 data register20.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word4 data.
+         */
+        uint32_t apb2otp_block0_backup4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
+/** Type of apb2otp_blk0_backup4_w5 register
+ *  eFuse apb2otp block0 data register21.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word5 data.
+         */
+        uint32_t apb2otp_block0_backup4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word1 Data */
+/** Type of apb2otp_blk1_w1 register
+ *  eFuse apb2otp block1 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word1 data.
+         */
+        uint32_t apb2otp_block1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word2 Data */
+/** Type of apb2otp_blk1_w2 register
+ *  eFuse apb2otp block1 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word2 data.
+         */
+        uint32_t apb2otp_block1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word3 Data */
+/** Type of apb2otp_blk1_w3 register
+ *  eFuse apb2otp block1 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word3 data.
+         */
+        uint32_t apb2otp_block1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word4 Data */
+/** Type of apb2otp_blk1_w4 register
+ *  eFuse apb2otp block1 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word4 data.
+         */
+        uint32_t apb2otp_block1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word5 Data */
+/** Type of apb2otp_blk1_w5 register
+ *  eFuse apb2otp block1 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word5 data.
+         */
+        uint32_t apb2otp_block1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word6 Data */
+/** Type of apb2otp_blk1_w6 register
+ *  eFuse apb2otp block1 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word6 data.
+         */
+        uint32_t apb2otp_block1_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word7 Data */
+/** Type of apb2otp_blk1_w7 register
+ *  eFuse apb2otp block1 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word7 data.
+         */
+        uint32_t apb2otp_block1_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word8 Data */
+/** Type of apb2otp_blk1_w8 register
+ *  eFuse apb2otp block1 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word8 data.
+         */
+        uint32_t apb2otp_block1_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word9 Data */
+/** Type of apb2otp_blk1_w9 register
+ *  eFuse apb2otp block1 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word9 data.
+         */
+        uint32_t apb2otp_block1_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word1 Data */
+/** Type of apb2otp_blk2_w1 register
+ *  eFuse apb2otp block2 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word1 data.
+         */
+        uint32_t apb2otp_block2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word2 Data */
+/** Type of apb2otp_blk2_w2 register
+ *  eFuse apb2otp block2 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word2 data.
+         */
+        uint32_t apb2otp_block2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word3 Data */
+/** Type of apb2otp_blk2_w3 register
+ *  eFuse apb2otp block2 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word3 data.
+         */
+        uint32_t apb2otp_block2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word4 Data */
+/** Type of apb2otp_blk2_w4 register
+ *  eFuse apb2otp block2 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word4 data.
+         */
+        uint32_t apb2otp_block2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word5 Data */
+/** Type of apb2otp_blk2_w5 register
+ *  eFuse apb2otp block2 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word5 data.
+         */
+        uint32_t apb2otp_block2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word6 Data */
+/** Type of apb2otp_blk2_w6 register
+ *  eFuse apb2otp block2 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word6 data.
+         */
+        uint32_t apb2otp_block2_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word7 Data */
+/** Type of apb2otp_blk2_w7 register
+ *  eFuse apb2otp block2 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word7 data.
+         */
+        uint32_t apb2otp_block2_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word8 Data */
+/** Type of apb2otp_blk2_w8 register
+ *  eFuse apb2otp block2 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word8 data.
+         */
+        uint32_t apb2otp_block2_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word9 Data */
+/** Type of apb2otp_blk2_w9 register
+ *  eFuse apb2otp block2 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word9 data.
+         */
+        uint32_t apb2otp_block2_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word10 Data */
+/** Type of apb2otp_blk2_w10 register
+ *  eFuse apb2otp block2 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word10 data.
+         */
+        uint32_t apb2otp_block2_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk2_w11 register
+ *  eFuse apb2otp block2 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word11 data.
+         */
+        uint32_t apb2otp_block2_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w11_reg_t;
+
+/** Type of apb2otp_blk10_w11 register
+ *  eFuse apb2otp block10 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word11 data.
+         */
+        uint32_t apb2otp_block10_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word1 Data */
+/** Type of apb2otp_blk3_w1 register
+ *  eFuse apb2otp block3 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word1 data.
+         */
+        uint32_t apb2otp_block3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word2 Data */
+/** Type of apb2otp_blk3_w2 register
+ *  eFuse apb2otp block3 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word2 data.
+         */
+        uint32_t apb2otp_block3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word3 Data */
+/** Type of apb2otp_blk3_w3 register
+ *  eFuse apb2otp block3 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word3 data.
+         */
+        uint32_t apb2otp_block3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word4 Data */
+/** Type of apb2otp_blk3_w4 register
+ *  eFuse apb2otp block3 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word4 data.
+         */
+        uint32_t apb2otp_block3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word5 Data */
+/** Type of apb2otp_blk3_w5 register
+ *  eFuse apb2otp block3 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word5 data.
+         */
+        uint32_t apb2otp_block3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word6 Data */
+/** Type of apb2otp_blk3_w6 register
+ *  eFuse apb2otp block3 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word6 data.
+         */
+        uint32_t apb2otp_block3_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word7 Data */
+/** Type of apb2otp_blk3_w7 register
+ *  eFuse apb2otp block3 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word7 data.
+         */
+        uint32_t apb2otp_block3_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word8 Data */
+/** Type of apb2otp_blk3_w8 register
+ *  eFuse apb2otp block3 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word8 data.
+         */
+        uint32_t apb2otp_block3_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word9 Data */
+/** Type of apb2otp_blk3_w9 register
+ *  eFuse apb2otp block3 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word9 data.
+         */
+        uint32_t apb2otp_block3_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word10 Data */
+/** Type of apb2otp_blk3_w10 register
+ *  eFuse apb2otp block3 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word10 data.
+         */
+        uint32_t apb2otp_block3_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word11 Data */
+/** Type of apb2otp_blk3_w11 register
+ *  eFuse apb2otp block3 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word11 data.
+         */
+        uint32_t apb2otp_block3_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word1 Data */
+/** Type of apb2otp_blk4_w1 register
+ *  eFuse apb2otp block4 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word1 data.
+         */
+        uint32_t apb2otp_block4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word2 Data */
+/** Type of apb2otp_blk4_w2 register
+ *  eFuse apb2otp block4 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word2 data.
+         */
+        uint32_t apb2otp_block4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word3 Data */
+/** Type of apb2otp_blk4_w3 register
+ *  eFuse apb2otp block4 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word3 data.
+         */
+        uint32_t apb2otp_block4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word4 Data */
+/** Type of apb2otp_blk4_w4 register
+ *  eFuse apb2otp block4 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word4 data.
+         */
+        uint32_t apb2otp_block4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word5 Data */
+/** Type of apb2otp_blk4_w5 register
+ *  eFuse apb2otp block4 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word5 data.
+         */
+        uint32_t apb2otp_block4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word6 Data */
+/** Type of apb2otp_blk4_w6 register
+ *  eFuse apb2otp block4 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word6 data.
+         */
+        uint32_t apb2otp_block4_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word7 Data */
+/** Type of apb2otp_blk4_w7 register
+ *  eFuse apb2otp block4 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word7 data.
+         */
+        uint32_t apb2otp_block4_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word8 Data */
+/** Type of apb2otp_blk4_w8 register
+ *  eFuse apb2otp block4 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word8 data.
+         */
+        uint32_t apb2otp_block4_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word9 Data */
+/** Type of apb2otp_blk4_w9 register
+ *  eFuse apb2otp block4 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word9 data.
+         */
+        uint32_t apb2otp_block4_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word10 Data */
+/** Type of apb2otp_blk4_w10 register
+ *  eFuse apb2otp block4 data registe10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word10 data.
+         */
+        uint32_t apb2otp_block4_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word11 Data */
+/** Type of apb2otp_blk4_w11 register
+ *  eFuse apb2otp block4 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word11 data.
+         */
+        uint32_t apb2otp_block4_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word1 Data */
+/** Type of apb2otp_blk5_w1 register
+ *  eFuse apb2otp block5 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word1 data.
+         */
+        uint32_t apb2otp_block5_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word2 Data */
+/** Type of apb2otp_blk5_w2 register
+ *  eFuse apb2otp block5 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word2 data.
+         */
+        uint32_t apb2otp_block5_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word3 Data */
+/** Type of apb2otp_blk5_w3 register
+ *  eFuse apb2otp block5 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word3 data.
+         */
+        uint32_t apb2otp_block5_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word4 Data */
+/** Type of apb2otp_blk5_w4 register
+ *  eFuse apb2otp block5 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word4 data.
+         */
+        uint32_t apb2otp_block5_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word5 Data */
+/** Type of apb2otp_blk5_w5 register
+ *  eFuse apb2otp block5 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word5 data.
+         */
+        uint32_t apb2otp_block5_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word6 Data */
+/** Type of apb2otp_blk5_w6 register
+ *  eFuse apb2otp block5 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word6 data.
+         */
+        uint32_t apb2otp_block5_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word7 Data */
+/** Type of apb2otp_blk5_w7 register
+ *  eFuse apb2otp block5 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word7 data.
+         */
+        uint32_t apb2otp_block5_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word8 Data */
+/** Type of apb2otp_blk5_w8 register
+ *  eFuse apb2otp block5 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word8 data.
+         */
+        uint32_t apb2otp_block5_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word9 Data */
+/** Type of apb2otp_blk5_w9 register
+ *  eFuse apb2otp block5 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word9 data.
+         */
+        uint32_t apb2otp_block5_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word10 Data */
+/** Type of apb2otp_blk5_w10 register
+ *  eFuse apb2otp block5 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word10 data.
+         */
+        uint32_t apb2otp_block5_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word11 Data */
+/** Type of apb2otp_blk5_w11 register
+ *  eFuse apb2otp block5 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word11 data.
+         */
+        uint32_t apb2otp_block5_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word1 Data */
+/** Type of apb2otp_blk6_w1 register
+ *  eFuse apb2otp block6 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word1 data.
+         */
+        uint32_t apb2otp_block6_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word2 Data */
+/** Type of apb2otp_blk6_w2 register
+ *  eFuse apb2otp block6 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word2 data.
+         */
+        uint32_t apb2otp_block6_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word3 Data */
+/** Type of apb2otp_blk6_w3 register
+ *  eFuse apb2otp block6 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word3 data.
+         */
+        uint32_t apb2otp_block6_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word4 Data */
+/** Type of apb2otp_blk6_w4 register
+ *  eFuse apb2otp block6 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word4 data.
+         */
+        uint32_t apb2otp_block6_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word5 Data */
+/** Type of apb2otp_blk6_w5 register
+ *  eFuse apb2otp block6 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word5 data.
+         */
+        uint32_t apb2otp_block6_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word6 Data */
+/** Type of apb2otp_blk6_w6 register
+ *  eFuse apb2otp block6 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word6 data.
+         */
+        uint32_t apb2otp_block6_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word7 Data */
+/** Type of apb2otp_blk6_w7 register
+ *  eFuse apb2otp block6 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word7 data.
+         */
+        uint32_t apb2otp_block6_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word8 Data */
+/** Type of apb2otp_blk6_w8 register
+ *  eFuse apb2otp block6 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word8 data.
+         */
+        uint32_t apb2otp_block6_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word9 Data */
+/** Type of apb2otp_blk6_w9 register
+ *  eFuse apb2otp block6 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word9 data.
+         */
+        uint32_t apb2otp_block6_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word10 Data */
+/** Type of apb2otp_blk6_w10 register
+ *  eFuse apb2otp block6 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word10 data.
+         */
+        uint32_t apb2otp_block6_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word11 Data */
+/** Type of apb2otp_blk6_w11 register
+ *  eFuse apb2otp block6 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word11 data.
+         */
+        uint32_t apb2otp_block6_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word1 Data */
+/** Type of apb2otp_blk7_w1 register
+ *  eFuse apb2otp block7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word1 data.
+         */
+        uint32_t apb2otp_block7_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word2 Data */
+/** Type of apb2otp_blk7_w2 register
+ *  eFuse apb2otp block7 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word2 data.
+         */
+        uint32_t apb2otp_block7_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word3 Data */
+/** Type of apb2otp_blk7_w3 register
+ *  eFuse apb2otp block7 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word3 data.
+         */
+        uint32_t apb2otp_block7_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word4 Data */
+/** Type of apb2otp_blk7_w4 register
+ *  eFuse apb2otp block7 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word4 data.
+         */
+        uint32_t apb2otp_block7_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word5 Data */
+/** Type of apb2otp_blk7_w5 register
+ *  eFuse apb2otp block7 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word5 data.
+         */
+        uint32_t apb2otp_block7_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word6 Data */
+/** Type of apb2otp_blk7_w6 register
+ *  eFuse apb2otp block7 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word6 data.
+         */
+        uint32_t apb2otp_block7_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word7 Data */
+/** Type of apb2otp_blk7_w7 register
+ *  eFuse apb2otp block7 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word7 data.
+         */
+        uint32_t apb2otp_block7_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word8 Data */
+/** Type of apb2otp_blk7_w8 register
+ *  eFuse apb2otp block7 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word8 data.
+         */
+        uint32_t apb2otp_block7_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word9 Data */
+/** Type of apb2otp_blk7_w9 register
+ *  eFuse apb2otp block7 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word9 data.
+         */
+        uint32_t apb2otp_block7_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word10 Data */
+/** Type of apb2otp_blk7_w10 register
+ *  eFuse apb2otp block7 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word10 data.
+         */
+        uint32_t apb2otp_block7_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word11 Data */
+/** Type of apb2otp_blk7_w11 register
+ *  eFuse apb2otp block7 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word11 data.
+         */
+        uint32_t apb2otp_block7_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word1 Data */
+/** Type of apb2otp_blk8_w1 register
+ *  eFuse apb2otp block8 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word1 data.
+         */
+        uint32_t apb2otp_block8_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word2 Data */
+/** Type of apb2otp_blk8_w2 register
+ *  eFuse apb2otp block8 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word2 data.
+         */
+        uint32_t apb2otp_block8_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word3 Data */
+/** Type of apb2otp_blk8_w3 register
+ *  eFuse apb2otp block8 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word3 data.
+         */
+        uint32_t apb2otp_block8_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word4 Data */
+/** Type of apb2otp_blk8_w4 register
+ *  eFuse apb2otp block8 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word4 data.
+         */
+        uint32_t apb2otp_block8_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word5 Data */
+/** Type of apb2otp_blk8_w5 register
+ *  eFuse apb2otp block8 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word5 data.
+         */
+        uint32_t apb2otp_block8_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word6 Data */
+/** Type of apb2otp_blk8_w6 register
+ *  eFuse apb2otp block8 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word6 data.
+         */
+        uint32_t apb2otp_block8_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word7 Data */
+/** Type of apb2otp_blk8_w7 register
+ *  eFuse apb2otp block8 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word7 data.
+         */
+        uint32_t apb2otp_block8_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word8 Data */
+/** Type of apb2otp_blk8_w8 register
+ *  eFuse apb2otp block8 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word8 data.
+         */
+        uint32_t apb2otp_block8_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word9 Data */
+/** Type of apb2otp_blk8_w9 register
+ *  eFuse apb2otp block8 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word9 data.
+         */
+        uint32_t apb2otp_block8_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word10 Data */
+/** Type of apb2otp_blk8_w10 register
+ *  eFuse apb2otp block8 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word10 data.
+         */
+        uint32_t apb2otp_block8_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word11 Data */
+/** Type of apb2otp_blk8_w11 register
+ *  eFuse apb2otp block8 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word11 data.
+         */
+        uint32_t apb2otp_block8_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word1 Data */
+/** Type of apb2otp_blk9_w1 register
+ *  eFuse apb2otp block9 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word1 data.
+         */
+        uint32_t apb2otp_block9_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word2 Data */
+/** Type of apb2otp_blk9_w2 register
+ *  eFuse apb2otp block9 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word2 data.
+         */
+        uint32_t apb2otp_block9_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word3 Data */
+/** Type of apb2otp_blk9_w3 register
+ *  eFuse apb2otp block9 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word3 data.
+         */
+        uint32_t apb2otp_block9_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word4 Data */
+/** Type of apb2otp_blk9_w4 register
+ *  eFuse apb2otp block9 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word4 data.
+         */
+        uint32_t apb2otp_block9_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word5 Data */
+/** Type of apb2otp_blk9_w5 register
+ *  eFuse apb2otp block9 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word5 data.
+         */
+        uint32_t apb2otp_block9_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word6 Data */
+/** Type of apb2otp_blk9_w6 register
+ *  eFuse apb2otp block9 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word6 data.
+         */
+        uint32_t apb2otp_block9_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word7 Data */
+/** Type of apb2otp_blk9_w7 register
+ *  eFuse apb2otp block9 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word7 data.
+         */
+        uint32_t apb2otp_block9_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word8 Data */
+/** Type of apb2otp_blk9_w8 register
+ *  eFuse apb2otp block9 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word8 data.
+         */
+        uint32_t apb2otp_block9_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word9 Data */
+/** Type of apb2otp_blk9_w9 register
+ *  eFuse apb2otp block9 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word9 data.
+         */
+        uint32_t apb2otp_block9_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word10 Data */
+/** Type of apb2otp_blk9_w10 register
+ *  eFuse apb2otp block9 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word10 data.
+         */
+        uint32_t apb2otp_block9_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word11 Data */
+/** Type of apb2otp_blk9_w11 register
+ *  eFuse apb2otp block9 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word11 data.
+         */
+        uint32_t apb2otp_block9_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word1 Data */
+/** Type of apb2otp_blk10_w1 register
+ *  eFuse apb2otp block10 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word1 data.
+         */
+        uint32_t apb2otp_block10_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word2 Data */
+/** Type of apb2otp_blk10_w2 register
+ *  eFuse apb2otp block10 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word2 data.
+         */
+        uint32_t apb2otp_block10_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word3 Data */
+/** Type of apb2otp_blk10_w3 register
+ *  eFuse apb2otp block10 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word3 data.
+         */
+        uint32_t apb2otp_block10_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word4 Data */
+/** Type of apb2otp_blk10_w4 register
+ *  eFuse apb2otp block10 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word4 data.
+         */
+        uint32_t apb2otp_block10_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word5 Data */
+/** Type of apb2otp_blk10_w5 register
+ *  eFuse apb2otp block10 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word5 data.
+         */
+        uint32_t apb2otp_block10_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word6 Data */
+/** Type of apb2otp_blk10_w6 register
+ *  eFuse apb2otp block10 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word6 data.
+         */
+        uint32_t apb2otp_block10_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word7 Data */
+/** Type of apb2otp_blk10_w7 register
+ *  eFuse apb2otp block10 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word7 data.
+         */
+        uint32_t apb2otp_block10_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word8 Data */
+/** Type of apb2otp_blk10_w8 register
+ *  eFuse apb2otp block10 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word8 data.
+         */
+        uint32_t apb2otp_block10_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word9 Data */
+/** Type of apb2otp_blk10_w9 register
+ *  eFuse apb2otp block10 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word9 data.
+         */
+        uint32_t apb2otp_block10_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word10 Data */
+/** Type of apb2otp_blk10_w10 register
+ *  eFuse apb2otp block10 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word10 data.
+         */
+        uint32_t apb2otp_block19_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Function Enable Signal */
+/** Type of apb2otp_en register
+ *  eFuse apb2otp enable configuration register.
+ */
+typedef union {
+    struct {
+        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
+         *  Apb2otp mode enable signal.
+         */
+        uint32_t apb2otp_apb2otp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} efuse_apb2otp_en_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0;
+    volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1;
+    volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2;
+    volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3;
+    volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4;
+    volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
+    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
+    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
+    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
+    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
+    uint32_t reserved_190[12];
+    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
+    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    volatile efuse_date_reg_t date;
+    uint32_t reserved_200[384];
+    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
+    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
+    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
+    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
+    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
+    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
+    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
+    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
+    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
+    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
+    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
+    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
+    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
+    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
+    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
+    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
+    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
+    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
+    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
+    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
+    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
+    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
+    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
+    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
+    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
+    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
+    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
+    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
+    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
+    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
+    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
+    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
+    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
+    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
+    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
+    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
+    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
+    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
+    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
+    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
+    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
+    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
+    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
+    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
+    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
+    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
+    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
+    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
+    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
+    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
+    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
+    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
+    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
+    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
+    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
+    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
+    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
+    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
+    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
+    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
+    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
+    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
+    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
+    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
+    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
+    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
+    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
+    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
+    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
+    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
+    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
+    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
+    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
+    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
+    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
+    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
+    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
+    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
+    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
+    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
+    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
+    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
+    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
+    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
+    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
+    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
+    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
+    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
+    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
+    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
+    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
+    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
+    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
+    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
+    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
+    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
+    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
+    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
+    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
+    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
+    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
+    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
+    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
+    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
+    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
+    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
+    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
+    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
+    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
+    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
+    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
+    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
+    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
+    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
+    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
+    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
+    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
+    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
+    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
+    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
+    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
+    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
+    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
+    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
+    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
+    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
+    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
+    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
+    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
+    uint32_t reserved_a04;
+    volatile efuse_apb2otp_en_reg_t apb2otp_en;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/emac_dma_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/emac_dma_struct.h
new file mode 100644
index 0000000000..5607737825
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/emac_dma_struct.h
@@ -0,0 +1,154 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+
+typedef struct emac_dma_dev_s {
+    volatile union {
+        struct {
+            uint32_t sw_rst : 1;         /*When this bit is set  the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC  you should read a zero (0) value in this bit.*/
+            uint32_t dma_arb_sch : 1;    /*This bit specifies the arbitration scheme between the transmit and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX  priority specified in PR (bit[15:14]). 1'b1 Fixed priority (Rx priority to Tx).*/
+            uint32_t desc_skip_len : 5;  /*This bit specifies the number of Word to skip between two unchained descriptors.The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_LEN) value is equal to zero  the descriptor table is taken as contiguous by the DMA in Ring mode.*/
+            uint32_t alt_desc_size : 1;  /*When set  the size of the alternate descriptor increases to 32 bytes.*/
+            uint32_t prog_burst_len : 6; /*These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the number of beats to be transferred is more than 32  then perform the following steps: 1. Set the PBLx8 mode  2. Set the PBL(PROG_BURST_LEN).*/
+            uint32_t pri_ratio : 2;      /*These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit:  2'b00 -- 1: 1    2'b01 -- 2: 0    2'b10 -- 3: 1    2'b11 -- 4: 1*/
+            uint32_t fixed_burst : 1;    /*This bit controls whether the AHB master interface performs fixed burst transfers or not. When set  the AHB interface uses only SINGLE  INCR4  INCR8  or INCR16 during start of the normal burst transfers. When reset  the AHB interface uses SINGLE and INCR burst transfer Operations.*/
+            uint32_t rx_dma_pbl : 6;     /*This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst transfer on the host bus. You can program RPBL with values of 1  2  4  8  16  and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is set high.*/
+            uint32_t use_sep_pbl : 1;    /*When set high  this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When reset to low  the PBL value in Bits[13:8] is applicable for both DMA engines.*/
+            uint32_t pblx8_mode : 1;     /*When set high  this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore  the DMA transfers the data in 8  16  32  64  128  and 256 beats depending on the PBL value.*/
+            uint32_t dmaaddralibea : 1;  /*When this bit is set high and the FIXED_BURST bit is 1  the AHB interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0  the first burst (accessing the start address of data buffer) is not aligned  but subsequent bursts are aligned to the address.*/
+            uint32_t dmamixedburst : 1;  /*When this bit is set high and the FIXED_BURST bit is low  the AHB master interface starts all bursts of a length more than 16 with INCR (undefined burst)  whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less.*/
+            uint32_t reserved27 : 1;
+            uint32_t reserved28 : 2;
+            uint32_t reserved30 : 1;
+            uint32_t reserved31 : 1;
+        };
+        uint32_t val;
+    } dmabusmode;
+    uint32_t dmatxpolldemand; /*When these bits are written with any value  the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host)  the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available  the transmission resumes.*/
+    uint32_t dmarxpolldemand; /*When these bits are written with any value  the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host)  the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available  the Rx DMA returns to the active state.*/
+    uint32_t dmarxbaseaddr;   /*This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only.*/
+    uint32_t dmatxbaseaddr;   /*This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore  these LSB bits are read-only.*/
+    volatile union {
+        struct {
+            uint32_t trans_int : 1;         /*This bit indicates that the frame transmission is complete. When transmission is complete  Bit[31] (OWN) of TDES0 is reset  and the specific frame status information is updated in the Descriptor.*/
+            uint32_t trans_proc_stop : 1;   /*This bit is set when the transmission is stopped.*/
+            uint32_t trans_buf_unavail : 1; /*This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors  the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand Command.*/
+            uint32_t trans_jabber_to : 1;   /*This bit indicates that the Transmit Jabber Timer expired  which happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs  the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.*/
+            uint32_t recv_ovflow : 1;       /*This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application  the overflow status is set in RDES0[11].*/
+            uint32_t trans_undflow : 1;     /*This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.*/
+            uint32_t recv_int : 1;          /*This bit indicates that the frame reception is complete. When reception is complete  the Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor  and the specific frame status information is updated in the descriptor. The reception remains in the Running state.*/
+            uint32_t recv_buf_unavail : 1;  /*This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors  the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued  the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA.*/
+            uint32_t recv_proc_stop : 1;    /*This bit is asserted when the Receive Process enters the Stopped state.*/
+            uint32_t recv_wdt_to : 1;       /*When set  this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout.*/
+            uint32_t early_trans_int : 1;   /*This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO.*/
+            uint32_t reserved11 : 2;
+            uint32_t fatal_bus_err_int : 1; /*This bit indicates that a bus error occurred  as described in Bits [25:23]. When this bit is set  the corresponding DMA engine disables all of its bus accesses.*/
+            uint32_t early_recv_int : 1;    /*This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever occurs earlier).*/
+            uint32_t abn_int_summ : 1;      /*Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Interrupt Enable Register:   Bit[1]: Transmit Process Stopped.  Bit[3]: Transmit Jabber Timeout.  Bit[4]: Receive FIFO Overflow.  Bit[5]: Transmit Underflow.  Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped.  Bit[9]: Receive Watchdog Timeout.  Bit[10]: Early Transmit Interrupt.  Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes AIS to be set  is cleared.*/
+            uint32_t norm_int_summ : 1;     /*Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Interrupt Enable Register:  Bit[0]: Transmit Interrupt.  Bit[2]: Transmit Buffer Unavailable.  Bit[6]: Receive Interrupt.  Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set  is cleared.*/
+            uint32_t recv_proc_state : 3;   /*This field indicates the Receive DMA FSM state. This field does not generate an interrupt.  3'b000: Stopped. Reset or Stop Receive Command issued.  3'b001: Running. Fetching Receive Transfer Descriptor.  3'b010: Reserved for future use.  3'b011: Running. Waiting for RX packets.  3'b100: Suspended. Receive Descriptor Unavailable.  3'b101: Running. Closing Receive Descriptor.  3'b110: TIME_STAMP write state.  3'b111: Running. Transferring the TX packets data from receive buffer to host memory.*/
+            uint32_t trans_proc_state : 3;  /*This field indicates the Transmit DMA FSM state. This field does not generate an interrupt.  3'b000: Stopped. Reset or Stop Transmit Command issued.  3'b001: Running. Fetching Transmit Transfer Descriptor.  3'b010: Reserved for future use.  3'b011: Running. Waiting for TX packets.  3'b100: Suspended. Receive Descriptor Unavailable.  3'b101: Running. Closing Transmit Descriptor.  3'b110: TIME_STAMP write state.  3'b111: Running. Transferring the TX packets data from transmit buffer to host memory.*/
+            uint32_t error_bits : 3;        /*This field indicates the type of error that caused a Bus Error  for example  error response on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate an interrupt.  3'b000: Error during Rx DMA Write Data Transfer.  3'b011: Error during Tx DMA Read Data Transfer.  3'b100: Error during Rx DMA Descriptor Write Access.  3'b101: Error during Tx DMA Descriptor Write Access.  3'b110: Error during Rx DMA Descriptor Read Access.  3'b111: Error during Tx DMA Descriptor Read Access.*/
+            uint32_t reserved26 : 1;
+            uint32_t reserved27 : 1;
+            uint32_t pmt_int : 1;    /*This bit indicates an interrupt event in the PMT module of the ETH_MAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0.*/
+            uint32_t ts_tri_int : 1; /*This bit indicates an interrupt event in the Timestamp Generator block of the ETH_MAC.The software must read the corresponding registers in the ETH_MAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0.*/
+            uint32_t reserved30 : 1;
+            uint32_t reserved31 : 1;
+        };
+        uint32_t val;
+    } dmastatus;
+    volatile union {
+        struct {
+            uint32_t reserved0 : 1;
+            uint32_t start_stop_rx : 1;    /*When this bit is set  the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared  the Rx DMA operation is stopped after the transfer of the current frame.*/
+            uint32_t opt_second_frame : 1; /*When this bit is set  it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained.*/
+            uint32_t rx_thresh_ctrl : 2;   /*These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2'b00: 64， 2'b01: 32， 2'b10: 96， 2'b11: 128 .*/
+            uint32_t drop_gfrm : 1;        /*When set  the MAC drops the received giant frames in the Rx FIFO  that is frames that are larger than the computed giant frame limit.*/
+            uint32_t fwd_under_gf : 1;     /*When set  the Rx FIFO forwards Undersized frames (that is  frames with no Error and length less than 64 bytes) including pad-bytes and CRC.*/
+            uint32_t fwd_err_frame : 1;    /*When this bit is reset  the Rx FIFO drops frames with error status (CRC error collision error   giant frame  watchdog timeout  or overflow).*/
+            uint32_t reserved8 : 1;
+            uint32_t reserved9 : 2;
+            uint32_t reserved11 : 2;
+            uint32_t start_stop_transmission_command : 1; /*When this bit is set  transmission is placed in the Running state  and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset  the transmission process is placed in the Stopped state after completing the transmission of the current frame.*/
+            uint32_t tx_thresh_ctrl : 3;                  /*These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition  full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3'b000: 64  3'b001: 128   3'b010: 192   3'b011: 256  3'b100: 40  3'b101: 32  3'b110: 24  3'b111: 16 .*/
+            uint32_t reserved17 : 3;
+            uint32_t flush_tx_fifo : 1; /*When this bit is set  the transmit FIFO controller logic is reset to its default values  and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete.*/
+            uint32_t tx_str_fwd : 1;    /*When this bit is set  transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set  the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored.*/
+            uint32_t reserved22 : 1;
+            uint32_t reserved23 : 1;
+            uint32_t dis_flush_recv_frames : 1;   /*When this bit is set  the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers.*/
+            uint32_t rx_store_forward : 1;        /*When this bit is set  the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it.*/
+            uint32_t dis_drop_tcpip_err_fram : 1; /*When this bit is set  the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset  all error frames are dropped if the Fwd_Err_Frame bit is reset.*/
+            uint32_t reserved27 : 5;
+        };
+        uint32_t val;
+    } dmaoperation_mode;
+    volatile union {
+        struct {
+            uint32_t dmain_tie : 1;  /*When this bit is set with Normal Interrupt Summary Enable (Bit[16])  the Transmit Interrupt is enabled. When this bit is reset  the Transmit Interrupt is disabled.*/
+            uint32_t dmain_tse : 1;  /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Transmission Stopped Interrupt is enabled. When this bit is reset  the Transmission Stopped Interrupt is disabled.*/
+            uint32_t dmain_tbue : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit 16)  the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset  the Transmit Buffer Unavailable Interrupt is Disabled.*/
+            uint32_t dmain_tjte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset  the Transmit Jabber Timeout Interrupt is disabled.*/
+            uint32_t dmain_oie : 1;  /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Receive Overflow Interrupt is enabled. When this bit is reset  the Overflow Interrupt is disabled.*/
+            uint32_t dmain_uie : 1;  /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Transmit Underflow Interrupt is enabled. When this bit is reset  the Underflow Interrupt is disabled.*/
+            uint32_t dmain_rie : 1;  /*When this bit is set with Normal Interrupt Summary Enable (Bit[16])  the Receive Interrupt is enabled. When this bit is reset  the Receive Interrupt is disabled.*/
+            uint32_t dmain_rbue : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset  the Receive Buffer Unavailable Interrupt is disabled.*/
+            uint32_t dmain_rse : 1;  /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Receive Stopped Interrupt is enabled. When this bit is reset  the Receive Stopped Interrupt is disabled.*/
+            uint32_t dmain_rwte : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset  the Receive Watchdog Timeout Interrupt is disabled.*/
+            uint32_t dmain_etie : 1; /*When this bit is set with an Abnormal Interrupt Summary Enable (Bit[15])  the Early Transmit Interrupt is enabled. When this bit is reset  the Early Transmit Interrupt is disabled.*/
+            uint32_t reserved11 : 2;
+            uint32_t dmain_fbee : 1; /*When this bit is set with Abnormal Interrupt Summary Enable (Bit[15])  the Fatal Bus Error Interrupt is enabled. When this bit is reset  the Fatal Bus Error Enable Interrupt is disabled.*/
+            uint32_t dmain_erie : 1; /*When this bit is set with Normal Interrupt Summary Enable (Bit[16])  the Early Receive Interrupt is enabled. When this bit is reset  the Early Receive Interrupt is disabled.*/
+            uint32_t dmain_aise : 1; /*When this bit is set  abnormal interrupt summary is enabled. When this bit is reset the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status Register:  Bit[1]: Transmit Process Stopped.  Bit[3]: Transmit Jabber Timeout.  Bit[4]: Receive Overflow.  Bit[5]: Transmit Underflow.  Bit[7]: Receive Buffer Unavailable.  Bit[8]: Receive Process Stopped.  Bit[9]: Receive Watchdog Timeout.  Bit[10]: Early Transmit Interrupt.  Bit[13]: Fatal Bus Error.*/
+            uint32_t dmain_nise : 1; /*When this bit is set  normal interrupt summary is enabled. When this bit is reset  normal interrupt summary is disabled. This bit enables the following interrupts in Status Register:  Bit[0]: Transmit Interrupt.  Bit[2]: Transmit Buffer Unavailable.  Bit[6]: Receive Interrupt.  Bit[14]: Early Receive Interrupt.*/
+            uint32_t reserved17 : 15;
+        };
+        uint32_t val;
+    } dmain_en;
+    volatile union {
+        struct {
+            uint32_t missed_fc : 16;    /*This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read.*/
+            uint32_t overflow_bmfc : 1; /*This bit is set every time Missed Frame Counter (Bits[15:0]) overflows that is  the DMA discards an incoming frame because of the Host Receive  Buffer being unavailable with the missed frame counter at maximum value. In such a scenario  the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
+            uint32_t overflow_fc : 11;  /*This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read.*/
+            uint32_t overflow_bfoc : 1; /*This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows  that is  the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario  the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.*/
+            uint32_t reserved29 : 3;
+        };
+        uint32_t val;
+    } dmamissedfr;
+    volatile union {
+        struct {
+            uint32_t riwtc : 8; /*This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out  the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame.*/
+            uint32_t reserved8 : 24;
+        };
+        uint32_t val;
+    } dmarintwdtimer;
+    uint32_t reserved_28;
+    uint32_t reserved_2c;
+    uint32_t reserved_30;
+    uint32_t reserved_34;
+    uint32_t reserved_38;
+    uint32_t reserved_3c;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t dmatxcurrdesc;     /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
+    uint32_t dmarxcurrdesc;     /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
+    uint32_t dmatxcurraddr_buf; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
+    uint32_t dmarxcurraddr_buf; /*The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation.*/
+} emac_dma_dev_t;
+
+extern emac_dma_dev_t EMAC_DMA;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/emac_mac_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/emac_mac_struct.h
new file mode 100644
index 0000000000..a316295a2e
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/emac_mac_struct.h
@@ -0,0 +1,258 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+typedef struct {
+    volatile union {
+        struct {
+            uint32_t mac_address_hi : 16; /*This field contains the upper 16 bits  Bits[47:32] of the eighth 6-byte MAC Address.*/
+            uint32_t reserved16 : 8;
+            uint32_t mask_byte_control : 6; /*These bits are mask control bits for comparison of each of the EMAC_ADDR bytes. When set high  the MAC does not compare the corresponding byte of received DA or SA with the contents of EMAC_ADDR registers. Each bit controls the masking of the bytes as follows:  Bit[29]: EMAC_ADDR High [15:8].  Bit[28]: EMAC_ADDR High [7:0].  Bit[27]: EMAC_ADDR Low [31:24].  Bit[24]: EMAC_ADDR Low [7:0]. You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address.*/
+            uint32_t source_address : 1;    /*When this bit is set  the EMAC_ADDR[47:0] is used to compare with the SA fields of the received frame. When this bit is reset  the EMAC_ADDR[47:0] is used to compare with the DA fields of the received frame.*/
+            uint32_t address_enable : 1;    /*When this bit is set  the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset  the address filter module ignores the address for filtering.*/
+        };
+        uint32_t val;
+    } emacaddrhigh;
+    uint32_t emacaddrlow; /*This field contains the lower 32 bits of the eighth 6-byte MAC address.The content of this field is undefined  so the register needs to be configured after the initialization Process.*/
+} emac_mac_addr_t;
+
+typedef struct emac_mac_dev_s {
+    volatile union {
+        struct {
+            uint32_t pltf : 2;          /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/
+            uint32_t rx : 1;            /*When this bit is set  the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset  the MAC receive state machine is disabled after the completion of the reception of the current frame  and does not receive any further frames from the MII.*/
+            uint32_t tx : 1;            /*When this bit is set  the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset  the MAC transmit state machine is disabled after the completion of the transmission of the current frame  and does not transmit any further frames.*/
+            uint32_t deferralcheck : 1; /*Deferral Check.*/
+            uint32_t backofflimit : 2;  /*The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode.  00: k= min (n  10).  01: k = min (n  8).  10: k = min (n  4).  11: k = min (n  1)  n = retransmission attempt. The random integer r takes the value in the Range 0 ~ 2000.*/
+            uint32_t padcrcstrip : 1;   /*When this bit is set  the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset  the MAC passes all incoming frames  without modifying them to the Host.*/
+            uint32_t reserved8 : 1;
+            uint32_t retry : 1;         /*When this bit is set  the MAC attempts only one transmission. When a collision occurs on the MII interface  the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset  the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex Mode.*/
+            uint32_t rxipcoffload : 1;  /*When this bit is set  the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset  this function is disabled.*/
+            uint32_t duplex : 1;        /*When this bit is set  the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is read only with default value of 1'b1 in the full-duplex-mode.*/
+            uint32_t loopback : 1;      /*When this bit is set  the MAC operates in the loopback mode MII. The MII Receive clock input (CLK_RX) is required for the loopback to work properly  because the transmit clock is not looped-back internally.*/
+            uint32_t rxown : 1;         /*When this bit is set  the MAC disables the reception of frames when the TX_EN is asserted in the half-duplex mode. When this bit is reset  the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full duplex mode.*/
+            uint32_t fespeed : 1;       /*This bit selects the speed in the MII  RMII interface. 0: 10 Mbps. 1: 100 Mbps.*/
+            uint32_t mii : 1;           /*This bit selects the Ethernet line speed. It should be set to 1 for 10 or 100 Mbps operations.In 10 or 100 Mbps operations  this bit  along with FES(EMACFESPEED) bit  it selects the exact linespeed. In the 10/100 Mbps-only operations  the bit is always 1.*/
+            uint32_t disablecrs : 1;    /*When set high  this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low  the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions.*/
+            uint32_t interframegap : 3; /*These bits control the minimum IFG between frames during transmission.  3'b000: 96 bit times.  3'b001: 88 bit times.  3'b010: 80 bit times.  3'b111: 40 bit times. In the half-duplex mode  the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered.*/
+            uint32_t jumboframe : 1;    /*When this bit is set  the MAC allows Jumbo frames of 9 018 bytes (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.*/
+            uint32_t reserved21 : 1;
+            uint32_t jabber : 1;   /*When this bit is set  the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset  the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data (10 240 if JE is set high) during Transmission.*/
+            uint32_t watchdog : 1; /*When this bit is set  the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16 383 bytes. When this bit is reset  the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is set high) or the value programmed in Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes.*/
+            uint32_t reserved24 : 1;
+            uint32_t reserved25 : 1;
+            uint32_t reserved26 : 1;
+            uint32_t ass2kp : 1; /*When set  the MAC considers all frames  with up to 2 000 bytes length  as normal packets.When Bit[20] (JE) is not set  the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set  the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set  setting this bit has no effect on Giant Frame status.*/
+            uint32_t sairc : 3;  /*This field controls the source address insertion or replacement for all transmitted frames.Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]:  2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation.  2'b10: If Bit[30] is set to 0  the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted frames.  2'b11: If Bit[30] is set to 0  the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1  the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames.*/
+            uint32_t reserved31 : 1;
+        };
+        uint32_t val;
+    } gmacconfig;
+    volatile union {
+        struct {
+            uint32_t pmode : 1; /*When this bit is set  the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set.*/
+            uint32_t reserved1 : 1;
+            uint32_t reserved2 : 1;
+            uint32_t daif : 1; /*When this bit is set  the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset  normal filtering of frames is performed.*/
+            uint32_t pam : 1;  /*When set  this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.*/
+            uint32_t dbf : 1;  /*When this bit is set  the AFM(Address Filtering Module) module blocks all incoming broadcast frames. In addition  it overrides all other filter settings. When this bit is reset  the AFM module passes all received broadcast Frames.*/
+            uint32_t pcf : 2;  /*These bits control the forwarding of all control frames (including unicast and multicast Pause frames).   2'b00: MAC filters all control frames from reaching the application.  2'b01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter.  2'b10: MAC forwards all control frames to application even if they fail the Address Filter.  2'b11: MAC forwards control frames that pass the Address Filter.The following conditions should be true for the Pause frames processing:  Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register (Flow Control Register) to 1.  Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set.  Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.*/
+            uint32_t saif : 1; /*When this bit is set  the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset  frames whose SA does not match the SA registers are marked as failing the SA Address filter.*/
+            uint32_t safe : 1; /*When this bit is set  the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails  the MAC drops the frame. When this bit is reset  the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison.*/
+            uint32_t reserved10 : 1;
+            uint32_t reserved11 : 5;
+            uint32_t reserved16 : 1;
+            uint32_t reserved17 : 3;
+            uint32_t reserved20 : 1;
+            uint32_t reserved21 : 1;
+            uint32_t reserved22 : 9;
+            uint32_t receive_all : 1; /*When this bit is set  the MAC Receiver module passes all received frames  irrespective of whether they pass the address filter or not  to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter.*/
+        };
+        uint32_t val;
+    } gmacff;
+    uint32_t reserved_1008;
+    uint32_t reserved_100c;
+    volatile union {
+        struct {
+            uint32_t miibusy : 1;   /*This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.During a PHY register access  the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation  the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed  there is no change in the functionality of this bit even when the PHY is not Present.*/
+            uint32_t miiwrite : 1;  /*When set  this bit indicates to the PHY that this is a Write operation using the MII Data register. If this bit is not set  it indicates that this is a Read operation  that is  placing the data in the MII Data register.*/
+            uint32_t miicsrclk : 4; /*CSR clock range: 1.0 MHz ~ 2.5 MHz.  4'b0000: When the APB clock frequency is 80 MHz  the MDC clock frequency is APB CLK/42  4'b0011: When the APB clock frequency is 40 MHz  the MDC clock frequency is APB CLK/26.*/
+            uint32_t miireg : 5;    /*These bits select the desired MII register in the selected PHY device.*/
+            uint32_t miidev : 5;    /*This field indicates which of the 32 possible PHY devices are being accessed.*/
+            uint32_t reserved16 : 16;
+        };
+        uint32_t val;
+    } emacgmiiaddr;
+    volatile union {
+        struct {
+            uint32_t mii_data : 16; /*This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation.*/
+            uint32_t reserved16 : 16;
+        };
+        uint32_t val;
+    } emacmiidata;
+    volatile union {
+        struct {
+            uint32_t fcbba : 1; /*This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode  this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame  the Application must set this bit to 1'b1. During a transfer of the Control Frame  this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission  the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode  when this bit is set (and TFCE is set)  then backpressure is asserted by the MAC. During backpressure  when the MAC receives a new frame  the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode  the BPA(backpressure activate) is automatically disabled.*/
+            uint32_t tfce : 1;  /*In the full-duplex mode  when this bit is set  the MAC enables the flow control operation to transmit Pause frames. When this bit is reset  the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode  when this bit is set the MAC enables the backpressure operation. When this bit is reset  the backpressure feature is Disabled.*/
+            uint32_t rfce : 1;  /*When this bit is set  the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset  the decode function of the Pause frame is disabled.*/
+            uint32_t upfd : 1;  /*A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set  the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the EMACADDR0 High Register and EMACADDR0 Low Register. When this bit is reset  the MAC only detects Pause frames with unique multicast address.*/
+            uint32_t plt : 2;   /*This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example  if PT = 100H (256 slot-times)  and PLT = 01  then a second Pause frame is automatically transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values:   2'b00: The threshold is Pause time minus 4 slot times (PT-4 slot times).  2'b01: The threshold is Pause time minus 28 slot times (PT-28 slot times).  2'b10: The threshold is Pause time minus 144 slot times (PT-144 slot times).  2'b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface.*/
+            uint32_t reserved6 : 1;
+            uint32_t dzpq : 1; /*When this bit is set  it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset  normal operation with automatic Zero-Quanta Pause frame generation is enabled.*/
+            uint32_t reserved8 : 8;
+            uint32_t pause_time : 16; /*This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.*/
+        };
+        uint32_t val;
+    } gmacfc;
+    uint32_t reserved_101c;
+    uint32_t reserved_1020;
+    volatile union {
+        struct {
+            uint32_t macrpes : 1;  /*When high  this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.*/
+            uint32_t macrffcs : 2; /*When high  this field indicates the active state of the FIFO Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller.*/
+            uint32_t reserved3 : 1;
+            uint32_t mtlrfwcas : 1; /*When high  this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO.*/
+            uint32_t mtlrfrcs : 2;  /*This field gives the state of the Rx FIFO read Controller: 2'b00: IDLE state.2'b01: Reading frame data.2'b10: Reading frame status (or timestamp).2'b11: Flushing the frame data and status.*/
+            uint32_t reserved7 : 1;
+            uint32_t mtlrffls : 2; /*This field gives the status of the fill-level of the Rx FIFO:   2'b00: Rx FIFO Empty.  2'b01: Rx FIFO fill-level below flow-control deactivate threshold.  2'b10: Rx FIFO fill-level above flow-control activate threshold.  2'b11: Rx FIFO Full.*/
+            uint32_t reserved10 : 6;
+            uint32_t mactpes : 1;  /*When high  this bit indicates that the MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state.*/
+            uint32_t mactfcs : 2;  /*This field indicates the state of the MAC Transmit Frame Controller module:   2'b00: IDLE state.  2'b01: Waiting for status of previous frame or IFG or backoff period to be over.  2'b10: Generating and transmitting a Pause frame (in the full-duplex mode).  2'b11: Transferring input frame for transmission.*/
+            uint32_t mactp : 1;    /*When high  this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission.*/
+            uint32_t mtltfrcs : 2; /*This field indicates the state of the Tx FIFO Read Controller:   2'b00: IDLE state.  2'b01: READ state (transferring data to the MAC transmitter).  2'b10: Waiting for TxStatus from the MAC transmitter.  2'b11: Writing the received TxStatus or flushing the Tx FIFO.*/
+            uint32_t mtltfwcs : 1; /*When high  this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO.*/
+            uint32_t reserved23 : 1;
+            uint32_t mtltfnes : 1; /*When high  this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission.*/
+            uint32_t mtltsffs : 1; /*When high  this bit indicates that the MTL TxStatus FIFO is full. Therefore  the MTL cannot accept any more frames for transmission.*/
+            uint32_t reserved26 : 6;
+        };
+        uint32_t val;
+    } emacdebug;
+    uint32_t pmt_rwuffr; /*The MSB (31st bit) must be zero.Bit j[30:0] is the byte mask. If Bit 1/2/3/4 (byte number) of the byte mask is set  the CRC block processes the Filter 1/2/3/4 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type  defining the destination address type of the pattern.When the bit is set  the pattern applies to only multicast packets*/
+    volatile union {
+        struct {
+            uint32_t pwrdwn : 1;   /*When set  the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame.This bit must only be set when MGKPKTEN  GLBLUCAST  or RWKPKTEN bit is set high.*/
+            uint32_t mgkpkten : 1; /*When set  enables generation of a power management event because of magic packet reception.*/
+            uint32_t rwkpkten : 1; /*When set  enables generation of a power management event because of remote wake-up frame reception*/
+            uint32_t reserved3 : 2;
+            uint32_t mgkprcvd : 1; /*When set  this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register.*/
+            uint32_t rwkprcvd : 1; /*When set  this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register.*/
+            uint32_t reserved7 : 2;
+            uint32_t glblucast : 1; /*When set  enables any unicast packet filtered by the MAC (DAFilter) address recognition to be a remote wake-up frame.*/
+            uint32_t reserved10 : 14;
+            uint32_t rwkptr : 5; /*The maximum value of the pointer is 7  the detail information please refer to PMT_RWUFFR.*/
+            uint32_t reserved29 : 2;
+            uint32_t rwkfiltrst : 1; /*When this bit is set  it resets the RWKPTR register to 3’b000.*/
+        };
+        uint32_t val;
+    } pmt_csr;
+    volatile union {
+        struct {
+            uint32_t tlpien : 1; /*When set  this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.*/
+            uint32_t tlpiex : 1; /*When set  this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this register.*/
+            uint32_t rlpien : 1; /*When set  this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register.*/
+            uint32_t rlpiex : 1; /*When set  this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface  exited the LPI state  and resumed the normal reception. This bit is cleared by a read into this register.*/
+            uint32_t reserved4 : 4;
+            uint32_t tlpist : 1; /*When set  this bit indicates that the MAC is transmitting the LPI pattern on the MII interface.*/
+            uint32_t rlpist : 1; /*When set  this bit indicates that the MAC is receiving the LPI pattern on the MII interface.*/
+            uint32_t reserved10 : 6;
+            uint32_t lpien : 1; /*When set  this bit instructs the MAC Transmitter to enter the LPI state. When reset  this bit instructs the MAC to exit the LPI state and resume normal transmission.This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.*/
+            uint32_t pls : 1;   /*This bit indicates the link status of the PHY.When set  the link is considered to be okay (up) and when reset  the link is considered to be down.*/
+            uint32_t reserved18 : 1;
+            uint32_t lpitxa : 1; /*This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side.If the LPITXA and LPIEN bits are set to 1  the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0  the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.*/
+            uint32_t reserved20 : 12;
+        };
+        uint32_t val;
+    } gmaclpi_crs;
+    volatile union {
+        struct {
+            uint32_t lpi_tw_timer : 16; /*This field specifies the minimum time (in microseconds) for which the MAC waits  after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.*/
+            uint32_t lpi_ls_timer : 10; /*This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard.*/
+            uint32_t reserved26 : 6;
+        };
+        uint32_t val;
+    } gmaclpitimerscontrol;
+    volatile union {
+        struct {
+            uint32_t reserved0 : 1;
+            uint32_t reserved1 : 1;
+            uint32_t reserved2 : 1;
+            uint32_t pmtints : 1; /*This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bit[5] and Bit[6] in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit is valid only when you select the optional PMT module during core configuration.*/
+            uint32_t reserved4 : 1;
+            uint32_t reserved5 : 1;
+            uint32_t reserved6 : 1;
+            uint32_t reserved7 : 1;
+            uint32_t reserved8 : 1;
+            uint32_t reserved9 : 1;
+            uint32_t lpiis : 1; /*When the Energy Efficient Ethernet feature is enabled  this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register).*/
+            uint32_t reserved11 : 1;
+            uint32_t reserved12 : 20;
+        };
+        uint32_t val;
+    } emacints;
+    volatile union {
+        struct {
+            uint32_t reserved0 : 1;
+            uint32_t reserved1 : 1;
+            uint32_t reserved2 : 1;
+            uint32_t pmtintmask : 1; /*When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Interrupt Status Register.*/
+            uint32_t reserved4 : 5;
+            uint32_t tsintmask : 1; /*When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Interrupt Status Register. */
+            uint32_t lpiintmask : 1; /*When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Interrupt Status Register.*/
+            uint32_t reserved11 : 21;
+        };
+        uint32_t val;
+    } emacintmask;
+    volatile union {
+        struct {
+            uint32_t address0_hi : 16; /*This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
+            uint32_t reserved16 : 15;
+            uint32_t address_enable0 : 1; /*This bit is always set to 1.*/
+        };
+        uint32_t val;
+    } emacaddr0high;
+    uint32_t emacaddr0low; /*This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames.*/
+    emac_mac_addr_t emacaddr[15];    /*Offset: 0x40-0xC0. MAC Address1-15 registers. Each MAC address register contains the high and low 32-bit fields for MAC addresses 1-15.*/
+    uint32_t reserved_10c4; // AN control register
+    uint32_t reserved_10c8;
+    uint32_t reserved_10cc;
+    uint32_t reserved_10d0;
+    uint32_t reserved_10d4;
+    volatile union {
+        struct {
+            uint32_t link_mode : 1;  /*This bit indicates the current mode of operation of the link:   1'b0: Half-duplex mode.  1'b1: Full-duplex mode.*/
+            uint32_t link_speed : 2; /*This bit indicates the current speed of the link:   2'b00: 2.5 MHz.  2'b01: 25 MHz.  2'b10: 125 MHz.*/
+            uint32_t reserved3 : 1;
+            uint32_t jabber_timeout : 1; /*This bit indicates whether there is jabber timeout error (1'b1) in the received Frame.*/
+            uint32_t reserved5 : 1;
+            uint32_t reserved6 : 10;
+            uint32_t reserved16 : 1;
+            uint32_t reserved17 : 15;
+        };
+        uint32_t val;
+    } emaccstatus;
+    volatile union {
+        struct {
+            uint32_t wdogto : 14; /*When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG is reset  this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field  such frame is terminated and declared as an error frame.*/
+            uint32_t reserved14 : 2;
+            uint32_t pwdogen : 1; /*When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset  the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared  the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG.*/
+            uint32_t reserved17 : 15;
+        };
+        uint32_t val;
+    } emacwdogto;
+} emac_mac_dev_t;
+
+extern emac_mac_dev_t EMAC_MAC;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/emac_ptp_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/emac_ptp_struct.h
new file mode 100644
index 0000000000..ca04887a21
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/emac_ptp_struct.h
@@ -0,0 +1,268 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct emac_ptp_dev_s {
+    volatile union {
+        struct {
+            uint32_t en_timestamp : 1;                /* Timestamp Enable */
+            uint32_t ts_fine_coarse_update : 1;       /* Timestamp Fine or Coarse Update */
+            uint32_t ts_initialize : 1;               /* Timestamp Initialize */
+            uint32_t ts_update : 1;                   /* Timestamp Update */
+            uint32_t en_ts_int_trig : 1;              /* Timestamp Interrupt Trigger Enable */
+            uint32_t addend_reg_update : 1;           /* Addend Reg Update */
+            uint32_t reserved1 : 2;                   /* Reserved */
+            uint32_t en_ts4all : 1;                   /* Enable Timestamp for All Frames */
+            uint32_t ts_digit_bin_roll_ctrl : 1;      /* Timestamp Digital or Binary Rollover Control */
+            uint32_t en_ptp_pkg_proc_ver2_fmt : 1;    /* Enable PTP packet Processing for Version 2 Format */
+            uint32_t en_proc_ptp_ether_frm : 1;       /* Enable Processing of PTP over Ethernet Frames */
+            uint32_t en_proc_ptp_ipv6_udp : 1;        /* Enable Processing of PTP Frames Sent over IPv6-UDP */
+            uint32_t en_proc_ptp_ipv4_udp : 1;        /* Enable Processing of PTP Frames Sent over IPv4-UDP */
+            uint32_t en_ts_snap_event_msg : 1;        /* Enable Timestamp Snapshot for Event Messages */
+            uint32_t en_snap_msg_relevant_master : 1; /* Enable Snapshot for Messages Relevant to Master */
+            uint32_t sel_snap_type : 2;               /* Select PTP packets for Taking Snapshots */
+            uint32_t en_mac_addr_filter : 1;          /* Enable MAC address for PTP Frame Filtering */
+            uint32_t reserved2 : 5;                   /* Reserved */
+            uint32_t aux_snap_fifo_clear : 1;         /* Auxiliary Snapshot FIFO Clear */
+            uint32_t en_aux_snap0 : 1;                /* Auxiliary Snapshot 0 Enable */
+            uint32_t en_aux_snap1 : 1;                /* Auxiliary Snapshot 1 Enable */
+            uint32_t en_aux_snap2 : 1;                /* Auxiliary Snapshot 2 Enable */
+            uint32_t en_aux_snap3 : 1;                /* Auxiliary Snapshot 3 Enable */
+            uint32_t reserved3 : 3;                   /* Reserved */
+        };
+        uint32_t val;
+    } timestamp_ctrl;
+    volatile union {
+        struct {
+            uint32_t sub_second_incre_value : 8; /* Sub-second Increment Value */
+            uint32_t reserved : 24;              /* Reserved */
+        };
+        uint32_t val;
+    } sub_sec_incre;
+    volatile union {
+        struct {
+            uint32_t ts_second : 32; /* Timestamp Second */
+        };
+        uint32_t val;
+    } sys_seconds;
+    volatile union {
+        struct {
+            uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */
+            uint32_t reserved: 1;         /* Reserved */
+        };
+        uint32_t val;
+    } sys_nanosec;
+    volatile union {
+        struct {
+            uint32_t ts_second : 32; /* Timestamp Second */
+        };
+        uint32_t val;
+    } sys_seconds_update;
+    volatile union {
+        struct {
+            uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */
+            uint32_t add_sub : 1;         /* Add or Subtract Time */
+        };
+        uint32_t val;
+    } sys_nanosec_update;
+    volatile union {
+        struct {
+            uint32_t ts_addend_val: 32; /* Timestamp Addend Register */
+        };
+        uint32_t val;
+    } timestamp_addend;
+    volatile union {
+        struct {
+            uint32_t tgt_time_second_val : 32; /* Target Time Seconds Register */
+        };
+        uint32_t val;
+    } tgt_seconds;
+    volatile union {
+        struct {
+            uint32_t tgt_ts_low_reg : 31;   /* Target Timestamp Low Register */
+            uint32_t tgt_time_reg_busy : 1; /* Target Time Register Busy */
+        };
+        uint32_t val;
+    } tgt_nanosec;
+    volatile union {
+        struct {
+            uint32_t ts_higher_word : 16; /* Timestamp Higher Word Register */
+            uint32_t reserved : 16;       /* Reserved */
+        };
+        uint32_t val;
+    } sys_seconds_high;
+    volatile union {
+        struct {
+            uint32_t ts_secons_ovf : 1;             /* Timestamp Seconds Overflow */
+            uint32_t ts_tgt_time_reach : 1;         /* Timestamp Target Time Reached */
+            uint32_t aux_ts_trig_snap : 1;          /* Auxiliary Timestamp Trigger Snapshot */
+            uint32_t ts_tgt_time_err : 1;           /* Timestamp Target Time Error */
+            uint32_t ts_tgt_time_reach_pps1 : 1;    /* Timestamp Target Time Reached for Target Time PPS1 */
+            uint32_t ts_tgt_time_err1 : 1;          /* Timestamp Target Time Error */
+            uint32_t ts_tgt_time_reach_pps2 : 1;    /* Timestamp Target Time Reached for Target Time PPS2 */
+            uint32_t ts_tgt_time_err2 : 1;          /* Timestamp Target Time Error */
+            uint32_t ts_tgt_time_reach_pps3 : 1;    /* Timestamp Target Time Reached for Target Time PPS3 */
+            uint32_t ts_tgt_time_err3 : 1;          /* Timestamp Target Time Error */
+            uint32_t reserved1 : 6;                 /* Reserved */
+            uint32_t aux_ts_snap_trig_identify : 4; /* Auxiliary Timestamp Snapshot Trigger Identifier */
+            uint32_t reserved2 : 4;                 /* Reserved */
+            uint32_t aux_tx_snap_trig_miss : 1;     /* Auxiliary Timestamp Snapshot Trigger Missed */
+            uint32_t aux_ts_snap_num : 5;           /* Number of Auxiliary Timestamp Snapshots */
+            uint32_t reserved : 2;                  /* Reserved */
+        };
+        uint32_t val;
+    } status;
+    volatile union {
+        struct {
+            uint32_t pps_cmd0 : 4;      /* Flexible PPS0 Output Control */
+            uint32_t en_pps0 : 1;       /* Flexible PPS Output Mode Enable */
+            uint32_t tgt_mode_sel0 : 2; /* Target Time Register Mode for PPS0 Output */
+            uint32_t reserved1 : 1;     /* Reserved */
+            uint32_t pps_cmd1 : 3;      /* Flexible PPS1 Output Control */
+            uint32_t reserved2 : 2;     /* Reserved */
+            uint32_t tgt_mode_sel1 : 2; /* Target Time Register Mode for PPS1 Output */
+            uint32_t reserved3 : 1;     /* Reserved */
+            uint32_t pps_cmd2 : 3;      /* Flexible PPS2 Output Control */
+            uint32_t reserved4 : 2;     /* Reserved */
+            uint32_t tgt_mode_sel2 : 2; /* Target Time Register Mode for PPS2 Output */
+            uint32_t reserved5 : 1;     /* Reserved */
+            uint32_t pps_cmd3 : 3;      /* Flexible PPS3 Output Control */
+            uint32_t reserved6 : 2;     /* Reserved */
+            uint32_t tgt_mode_sel3 : 2; /* Target Time Register Mode for PPS3 Output */
+            uint32_t reserved7 : 1;     /* Reserved */
+        };
+        uint32_t val;
+    } pps_ctrl;
+    volatile union {
+        struct {
+            uint32_t aux_ts_low : 31; /* Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. */
+            uint32_t reserved : 1;    /* Reserved */
+        };
+        uint32_t val;
+    } aux_nanosec;
+    volatile union {
+        struct {
+            uint32_t aux_tx_high : 32; /* Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */
+        };
+        uint32_t val;
+    } aux_seconds;
+    volatile union {
+        struct {
+            uint32_t av_ethertype_val : 16;       /* AV EtherType Value */
+            uint32_t ac_queue_pri : 3;            /* AV Priority for Queuing */
+            uint32_t en_queue_non_av_pkt : 1;     /* VLAN Tagged Non-AV Packets Queueing Enable */
+            uint32_t dis_av_chann : 1;            /* AV Channel Disable */
+            uint32_t queue_av_ctrl_pkt_chann : 2; /* Channel for Queuing the AV Control Packets */
+            uint32_t reserved1 : 1;               /* Reserved */
+            uint32_t queue_ptp_pkt_chann : 2;     /* Channel for Queuing the PTP Packets */
+            uint32_t reserved2 : 6;               /* Reserved */
+        };
+        uint32_t val;
+    } av_mac_ctrl;
+    uint32_t reserved1[9]; /* Reserved */
+    volatile union {
+        struct {
+            uint32_t pps0_interval : 32; /* PPS0 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps0_interval;
+    volatile union {
+        struct {
+            uint32_t pps0_width : 32; /* PPS0 Output Signal Width */
+        };
+        uint32_t val;
+    } pps0_width;
+    uint32_t reserved2[6]; /* Reserved */
+    volatile union {
+        struct {
+            uint32_t pps1_tgt_seconds : 32; /* PPS1 Target Time Seconds Register */
+        };
+        uint32_t val;
+    } pps1_tgt_seconds;
+    volatile union {
+        struct {
+            uint32_t pps1_tgt_nanosec : 31;  /* Target Time Low for PPS1 Register */
+            uint32_t pps1_tgt_time_busy : 1; /* PPS1 Target Time Register Busy */
+        };
+        uint32_t val;
+    } pps1_tgt_nanosec;
+    volatile union {
+        struct {
+            uint32_t pps1_interval : 32; /* PPS1 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps1_interval;
+    volatile union {
+        struct {
+            uint32_t pps1_width : 32; /* PPS1 Output Signal Width */
+        };
+        uint32_t val;
+    } pps1_width;
+    uint32_t reserved3[4]; /* Reserved */
+    volatile union {
+        struct {
+            uint32_t pps2_tgt_seconds : 32; /* PPS2 Target Time Seconds Register */
+        };
+        uint32_t val;
+    } pps2_tgt_seconds;
+    volatile union {
+        struct {
+            uint32_t pps2_tgt_nanosec : 31;  /* Target Time Low for PPS2 Register */
+            uint32_t pps2_tgt_time_busy : 1; /* PPS2 Target Time Register Busy */
+        };
+        uint32_t val;
+    } pps2_tgt_nanosec;
+    volatile union {
+        struct {
+            uint32_t pps2_interval : 32; /* PPS2 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps2_interval;
+    volatile union {
+        struct {
+            uint32_t pps2_width : 32; /* PPS2 Output Signal Width */
+        };
+        uint32_t val;
+    } pps2_width;
+    uint32_t reserved4[4]; /* Reserved */
+    volatile union {
+        struct {
+            uint32_t pps3_tgt_seconds : 32; /* PPS3 Target Time Seconds Register */
+        };
+        uint32_t val;
+    } pps3_tgt_seconds;
+    volatile union {
+        struct {
+            uint32_t pps3_tgt_nanosec : 31;  /* Target Time Low for PPS3 Register */
+            uint32_t pps3_tgt_time_busy : 1; /* PPS3 Target Time Register Busy */
+        };
+        uint32_t val;
+    } pps3_tgt_nanosec;
+    volatile union {
+        struct {
+            uint32_t pps3_interval : 32; /* PPS3 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps3_interval;
+    volatile union {
+        struct {
+            uint32_t pps3_width : 32; /* PPS3 Output Signal Width */
+        };
+        uint32_t val;
+    } pps3_width;
+} emac_ptp_dev_t;
+
+extern emac_ptp_dev_t EMAC_PTP;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_eco5_struct.h
new file mode 100644
index 0000000000..a3b88516fa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_eco5_struct.h
@@ -0,0 +1,772 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: SDM Configure Registers */
+/** Type of sigmadeltan register
+ *  Duty Cycle Configure Register of SDMn
+ */
+typedef union {
+    struct {
+        /** sdn_in : R/W; bitpos: [7:0]; default: 0;
+         *  This field is used to configure the duty cycle of sigma delta modulation output.
+         */
+        uint32_t sdn_in:8;
+        /** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
+         *  This field is used to set a divider value to divide APB clock.
+         */
+        uint32_t sdn_prescale:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpiosd_sigmadeltan_reg_t;
+
+/** Type of sigmadelta_misc register
+ *  MISC Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** function_clk_en : R/W; bitpos: [30]; default: 0;
+         *  Clock enable bit of sigma delta modulation.
+         */
+        uint32_t function_clk_en:1;
+        /** spi_swap : R/W; bitpos: [31]; default: 0;
+         *  Reserved.
+         */
+        uint32_t spi_swap:1;
+    };
+    uint32_t val;
+} gpiosd_sigmadelta_misc_reg_t;
+
+
+/** Group: Glitch filter Configure Registers */
+/** Type of glitch_filter_chn register
+ *  Glitch Filter Configure Register of Channeln
+ */
+typedef union {
+    struct {
+        /** filter_ch0_en : R/W; bitpos: [0]; default: 0;
+         *  Glitch Filter channel enable bit.
+         */
+        uint32_t filter_ch0_en:1;
+        /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
+         *  Glitch Filter input io number.
+         */
+        uint32_t filter_ch0_input_io_num:6;
+        /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0;
+         *  Glitch Filter window threshold.
+         */
+        uint32_t filter_ch0_window_thres:6;
+        /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0;
+         *  Glitch Filter window width.
+         */
+        uint32_t filter_ch0_window_width:6;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} gpiosd_glitch_filter_chn_reg_t;
+
+
+/** Group: Etm Configure Registers */
+/** Type of etm_event_chn_cfg register
+ *  Etm Config register of Channeln
+ */
+typedef union {
+    struct {
+        /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
+         *  Etm event channel select gpio.
+         */
+        uint32_t etm_ch0_event_sel:6;
+        uint32_t reserved_6:1;
+        /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
+         *  Etm event send enable bit.
+         */
+        uint32_t etm_ch0_event_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpiosd_etm_event_chn_cfg_reg_t;
+
+/** Type of etm_task_p0_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio0_en:1;
+        /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio0_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio1_en:1;
+        /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio1_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio2_en:1;
+        /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio2_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio3_en:1;
+        /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio3_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p0_cfg_reg_t;
+
+/** Type of etm_task_p1_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio4_en:1;
+        /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio4_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio5_en:1;
+        /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio5_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio6_en:1;
+        /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio6_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio7_en:1;
+        /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio7_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p1_cfg_reg_t;
+
+/** Type of etm_task_p2_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio8_en:1;
+        /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio8_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio9_en:1;
+        /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio9_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio10_en:1;
+        /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio10_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio11_en:1;
+        /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio11_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p2_cfg_reg_t;
+
+/** Type of etm_task_p3_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio12_en:1;
+        /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio12_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio13_en:1;
+        /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio13_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio14_en:1;
+        /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio14_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio15_en:1;
+        /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio15_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p3_cfg_reg_t;
+
+/** Type of etm_task_p4_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio16_en:1;
+        /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio16_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio17_en:1;
+        /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio17_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio18_en:1;
+        /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio18_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio19_en:1;
+        /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio19_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p4_cfg_reg_t;
+
+/** Type of etm_task_p5_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio20_en:1;
+        /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio20_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio21_en:1;
+        /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio21_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio22_en:1;
+        /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio22_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio23_en:1;
+        /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio23_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p5_cfg_reg_t;
+
+/** Type of etm_task_p6_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio24_en:1;
+        /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio24_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio25_en:1;
+        /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio25_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio26_en:1;
+        /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio26_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio27_en:1;
+        /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio27_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p6_cfg_reg_t;
+
+/** Type of etm_task_p7_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio28_en:1;
+        /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio28_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio29_en:1;
+        /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio29_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio30_en:1;
+        /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio30_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio31_en:1;
+        /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio31_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p7_cfg_reg_t;
+
+/** Type of etm_task_p8_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio32_en:1;
+        /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio32_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio33_en:1;
+        /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio33_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio34_en:1;
+        /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio34_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio35_en:1;
+        /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio35_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p8_cfg_reg_t;
+
+/** Type of etm_task_p9_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio36_en:1;
+        /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio36_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio37_en:1;
+        /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio37_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio38_en:1;
+        /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio38_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio39_en:1;
+        /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio39_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p9_cfg_reg_t;
+
+/** Type of etm_task_p10_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio40_en:1;
+        /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio40_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio41_en:1;
+        /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio41_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio42_en:1;
+        /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio42_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio43_en:1;
+        /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio43_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p10_cfg_reg_t;
+
+/** Type of etm_task_p11_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio44_en:1;
+        /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio44_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio45_en:1;
+        /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio45_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio46_en:1;
+        /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio46_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio47_en:1;
+        /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio47_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p11_cfg_reg_t;
+
+/** Type of etm_task_p12_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio48_en:1;
+        /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio48_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio49_en:1;
+        /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio49_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio50_en:1;
+        /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio50_sel:3;
+        uint32_t reserved_20:4;
+        /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio51_en:1;
+        /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio51_sel:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p12_cfg_reg_t;
+
+/** Type of etm_task_p13_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio52_en:1;
+        /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio52_sel:3;
+        uint32_t reserved_4:4;
+        /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio53_en:1;
+        /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio53_sel:3;
+        uint32_t reserved_12:4;
+        /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio54_en:1;
+        /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio54_sel:3;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} gpiosd_etm_task_p13_cfg_reg_t;
+
+
+/** Group: Version Register */
+/** Type of version register
+ *  Version Control Register
+ */
+typedef union {
+    struct {
+        /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952;
+         *  Version control register.
+         */
+        uint32_t gpio_sd_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpiosd_version_reg_t;
+
+
+typedef struct {
+    volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8];
+    uint32_t reserved_020;
+    volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc;
+    uint32_t reserved_028[2];
+    volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8];
+    uint32_t reserved_050[4];
+    volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
+    uint32_t reserved_080[8];
+    volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
+    volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
+    volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
+    volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
+    volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
+    volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
+    volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
+    volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
+    volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
+    volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
+    volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
+    volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
+    volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
+    volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
+    uint32_t reserved_0d8[9];
+    volatile gpiosd_version_reg_t version;
+} gpiosd_dev_t;
+
+extern gpiosd_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_reg.h
new file mode 100644
index 0000000000..ce4b476a72
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_reg.h
@@ -0,0 +1,1455 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIOSD_SIGMADELTA0_REG register
+ *  Duty Cycle Configure Register of SDM0
+ */
+#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIOSD_BASE + 0x0)
+/** GPIOSD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD0_IN    0x000000FFU
+#define GPIO_EXT_SD0_IN_M  (GPIOSD_SD0_IN_V << GPIOSD_SD0_IN_S)
+#define GPIO_EXT_SD0_IN_V  0x000000FFU
+#define GPIO_EXT_SD0_IN_S  0
+/** GPIOSD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD0_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD0_PRESCALE_M  (GPIOSD_SD0_PRESCALE_V << GPIOSD_SD0_PRESCALE_S)
+#define GPIO_EXT_SD0_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD0_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA1_REG register
+ *  Duty Cycle Configure Register of SDM1
+ */
+#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIOSD_BASE + 0x4)
+/** GPIOSD_SD1_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD1_IN    0x000000FFU
+#define GPIO_EXT_SD1_IN_M  (GPIOSD_SD1_IN_V << GPIOSD_SD1_IN_S)
+#define GPIO_EXT_SD1_IN_V  0x000000FFU
+#define GPIO_EXT_SD1_IN_S  0
+/** GPIOSD_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD1_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD1_PRESCALE_M  (GPIOSD_SD1_PRESCALE_V << GPIOSD_SD1_PRESCALE_S)
+#define GPIO_EXT_SD1_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD1_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA2_REG register
+ *  Duty Cycle Configure Register of SDM2
+ */
+#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIOSD_BASE + 0x8)
+/** GPIOSD_SD2_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD2_IN    0x000000FFU
+#define GPIO_EXT_SD2_IN_M  (GPIOSD_SD2_IN_V << GPIOSD_SD2_IN_S)
+#define GPIO_EXT_SD2_IN_V  0x000000FFU
+#define GPIO_EXT_SD2_IN_S  0
+/** GPIOSD_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD2_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD2_PRESCALE_M  (GPIOSD_SD2_PRESCALE_V << GPIOSD_SD2_PRESCALE_S)
+#define GPIO_EXT_SD2_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD2_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA3_REG register
+ *  Duty Cycle Configure Register of SDM3
+ */
+#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIOSD_BASE + 0xc)
+/** GPIOSD_SD3_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD3_IN    0x000000FFU
+#define GPIO_EXT_SD3_IN_M  (GPIOSD_SD3_IN_V << GPIOSD_SD3_IN_S)
+#define GPIO_EXT_SD3_IN_V  0x000000FFU
+#define GPIO_EXT_SD3_IN_S  0
+/** GPIOSD_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD3_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD3_PRESCALE_M  (GPIOSD_SD3_PRESCALE_V << GPIOSD_SD3_PRESCALE_S)
+#define GPIO_EXT_SD3_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD3_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA4_REG register
+ *  Duty Cycle Configure Register of SDM4
+ */
+#define GPIO_EXT_SIGMADELTA4_REG (DR_REG_GPIOSD_BASE + 0x10)
+/** GPIOSD_SD4_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD4_IN    0x000000FFU
+#define GPIO_EXT_SD4_IN_M  (GPIOSD_SD4_IN_V << GPIOSD_SD4_IN_S)
+#define GPIO_EXT_SD4_IN_V  0x000000FFU
+#define GPIO_EXT_SD4_IN_S  0
+/** GPIOSD_SD4_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD4_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD4_PRESCALE_M  (GPIOSD_SD4_PRESCALE_V << GPIOSD_SD4_PRESCALE_S)
+#define GPIO_EXT_SD4_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD4_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA5_REG register
+ *  Duty Cycle Configure Register of SDM5
+ */
+#define GPIO_EXT_SIGMADELTA5_REG (DR_REG_GPIOSD_BASE + 0x14)
+/** GPIOSD_SD5_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD5_IN    0x000000FFU
+#define GPIO_EXT_SD5_IN_M  (GPIOSD_SD5_IN_V << GPIOSD_SD5_IN_S)
+#define GPIO_EXT_SD5_IN_V  0x000000FFU
+#define GPIO_EXT_SD5_IN_S  0
+/** GPIOSD_SD5_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD5_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD5_PRESCALE_M  (GPIOSD_SD5_PRESCALE_V << GPIOSD_SD5_PRESCALE_S)
+#define GPIO_EXT_SD5_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD5_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA6_REG register
+ *  Duty Cycle Configure Register of SDM6
+ */
+#define GPIO_EXT_SIGMADELTA6_REG (DR_REG_GPIOSD_BASE + 0x18)
+/** GPIOSD_SD6_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD6_IN    0x000000FFU
+#define GPIO_EXT_SD6_IN_M  (GPIOSD_SD6_IN_V << GPIOSD_SD6_IN_S)
+#define GPIO_EXT_SD6_IN_V  0x000000FFU
+#define GPIO_EXT_SD6_IN_S  0
+/** GPIOSD_SD6_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD6_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD6_PRESCALE_M  (GPIOSD_SD6_PRESCALE_V << GPIOSD_SD6_PRESCALE_S)
+#define GPIO_EXT_SD6_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD6_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA7_REG register
+ *  Duty Cycle Configure Register of SDM7
+ */
+#define GPIO_EXT_SIGMADELTA7_REG (DR_REG_GPIOSD_BASE + 0x1c)
+/** GPIOSD_SD7_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD7_IN    0x000000FFU
+#define GPIO_EXT_SD7_IN_M  (GPIOSD_SD7_IN_V << GPIOSD_SD7_IN_S)
+#define GPIO_EXT_SD7_IN_V  0x000000FFU
+#define GPIO_EXT_SD7_IN_S  0
+/** GPIOSD_SD7_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_EXT_SD7_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD7_PRESCALE_M  (GPIOSD_SD7_PRESCALE_V << GPIOSD_SD7_PRESCALE_S)
+#define GPIO_EXT_SD7_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD7_PRESCALE_S  8
+
+/** GPIOSD_SIGMADELTA_MISC_REG register
+ *  MISC Register
+ */
+#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIOSD_BASE + 0x24)
+/** GPIOSD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Clock enable bit of sigma delta modulation.
+ */
+#define GPIO_EXT_FUNCTION_CLK_EN    (BIT(30))
+#define GPIO_EXT_FUNCTION_CLK_EN_M  (GPIOSD_FUNCTION_CLK_EN_V << GPIOSD_FUNCTION_CLK_EN_S)
+#define GPIO_EXT_FUNCTION_CLK_EN_V  0x00000001U
+#define GPIO_EXT_FUNCTION_CLK_EN_S  30
+/** GPIOSD_SPI_SWAP : R/W; bitpos: [31]; default: 0;
+ *  Reserved.
+ */
+#define GPIO_EXT_SPI_SWAP    (BIT(31))
+#define GPIO_EXT_SPI_SWAP_M  (GPIOSD_SPI_SWAP_V << GPIOSD_SPI_SWAP_S)
+#define GPIO_EXT_SPI_SWAP_V  0x00000001U
+#define GPIO_EXT_SPI_SWAP_S  31
+
+/** GPIOSD_GLITCH_FILTER_CH0_REG register
+ *  Glitch Filter Configure Register of Channel0
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIOSD_BASE + 0x30)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH1_REG register
+ *  Glitch Filter Configure Register of Channel1
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIOSD_BASE + 0x34)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH2_REG register
+ *  Glitch Filter Configure Register of Channel2
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIOSD_BASE + 0x38)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH3_REG register
+ *  Glitch Filter Configure Register of Channel3
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIOSD_BASE + 0x3c)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH4_REG register
+ *  Glitch Filter Configure Register of Channel4
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIOSD_BASE + 0x40)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH5_REG register
+ *  Glitch Filter Configure Register of Channel5
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIOSD_BASE + 0x44)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH6_REG register
+ *  Glitch Filter Configure Register of Channel6
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIOSD_BASE + 0x48)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_GLITCH_FILTER_CH7_REG register
+ *  Glitch Filter Configure Register of Channel7
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIOSD_BASE + 0x4c)
+/** GPIOSD_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Glitch Filter channel enable bit.
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIOSD_FILTER_CH0_EN_V << GPIOSD_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIOSD_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [6:1]; default: 0;
+ *  Glitch Filter input io number.
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIOSD_FILTER_CH0_INPUT_IO_NUM_V << GPIOSD_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIOSD_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [12:7]; default: 0;
+ *  Glitch Filter window threshold.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIOSD_FILTER_CH0_WINDOW_THRES_V << GPIOSD_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  7
+/** GPIOSD_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [18:13]; default: 0;
+ *  Glitch Filter window width.
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIOSD_FILTER_CH0_WINDOW_WIDTH_V << GPIOSD_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  13
+
+/** GPIOSD_ETM_EVENT_CH0_CFG_REG register
+ *  Etm Config register of Channel0
+ */
+#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIOSD_BASE + 0x60)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH1_CFG_REG register
+ *  Etm Config register of Channel1
+ */
+#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIOSD_BASE + 0x64)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH2_CFG_REG register
+ *  Etm Config register of Channel2
+ */
+#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIOSD_BASE + 0x68)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH3_CFG_REG register
+ *  Etm Config register of Channel3
+ */
+#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIOSD_BASE + 0x6c)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH4_CFG_REG register
+ *  Etm Config register of Channel4
+ */
+#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIOSD_BASE + 0x70)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH5_CFG_REG register
+ *  Etm Config register of Channel5
+ */
+#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIOSD_BASE + 0x74)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH6_CFG_REG register
+ *  Etm Config register of Channel6
+ */
+#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIOSD_BASE + 0x78)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_EVENT_CH7_CFG_REG register
+ *  Etm Config register of Channel7
+ */
+#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIOSD_BASE + 0x7c)
+/** GPIOSD_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0;
+ *  Etm event channel select gpio.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIOSD_ETM_CH0_EVENT_SEL_V << GPIOSD_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000003FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIOSD_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Etm event send enable bit.
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIOSD_ETM_CH0_EVENT_EN_V << GPIOSD_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIOSD_ETM_TASK_P0_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIOSD_BASE + 0xa0)
+/** GPIOSD_ETM_TASK_GPIO0_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO0_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO0_EN_M  (GPIOSD_ETM_TASK_GPIO0_EN_V << GPIOSD_ETM_TASK_GPIO0_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO0_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO0_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO0_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL_M  (GPIOSD_ETM_TASK_GPIO0_SEL_V << GPIOSD_ETM_TASK_GPIO0_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO1_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO1_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO1_EN_M  (GPIOSD_ETM_TASK_GPIO1_EN_V << GPIOSD_ETM_TASK_GPIO1_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO1_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO1_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO1_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL_M  (GPIOSD_ETM_TASK_GPIO1_SEL_V << GPIOSD_ETM_TASK_GPIO1_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO2_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO2_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO2_EN_M  (GPIOSD_ETM_TASK_GPIO2_EN_V << GPIOSD_ETM_TASK_GPIO2_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO2_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO2_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO2_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL_M  (GPIOSD_ETM_TASK_GPIO2_SEL_V << GPIOSD_ETM_TASK_GPIO2_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO3_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO3_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO3_EN_M  (GPIOSD_ETM_TASK_GPIO3_EN_V << GPIOSD_ETM_TASK_GPIO3_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO3_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO3_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO3_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL_M  (GPIOSD_ETM_TASK_GPIO3_SEL_V << GPIOSD_ETM_TASK_GPIO3_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P1_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIOSD_BASE + 0xa4)
+/** GPIOSD_ETM_TASK_GPIO4_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO4_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO4_EN_M  (GPIOSD_ETM_TASK_GPIO4_EN_V << GPIOSD_ETM_TASK_GPIO4_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO4_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO4_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO4_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL_M  (GPIOSD_ETM_TASK_GPIO4_SEL_V << GPIOSD_ETM_TASK_GPIO4_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO5_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO5_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO5_EN_M  (GPIOSD_ETM_TASK_GPIO5_EN_V << GPIOSD_ETM_TASK_GPIO5_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO5_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO5_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO5_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL_M  (GPIOSD_ETM_TASK_GPIO5_SEL_V << GPIOSD_ETM_TASK_GPIO5_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO6_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO6_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO6_EN_M  (GPIOSD_ETM_TASK_GPIO6_EN_V << GPIOSD_ETM_TASK_GPIO6_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO6_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO6_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO6_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL_M  (GPIOSD_ETM_TASK_GPIO6_SEL_V << GPIOSD_ETM_TASK_GPIO6_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO7_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO7_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO7_EN_M  (GPIOSD_ETM_TASK_GPIO7_EN_V << GPIOSD_ETM_TASK_GPIO7_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO7_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO7_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO7_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL_M  (GPIOSD_ETM_TASK_GPIO7_SEL_V << GPIOSD_ETM_TASK_GPIO7_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P2_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIOSD_BASE + 0xa8)
+/** GPIOSD_ETM_TASK_GPIO8_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO8_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO8_EN_M  (GPIOSD_ETM_TASK_GPIO8_EN_V << GPIOSD_ETM_TASK_GPIO8_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO8_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO8_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO8_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL_M  (GPIOSD_ETM_TASK_GPIO8_SEL_V << GPIOSD_ETM_TASK_GPIO8_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO9_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO9_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO9_EN_M  (GPIOSD_ETM_TASK_GPIO9_EN_V << GPIOSD_ETM_TASK_GPIO9_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO9_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO9_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO9_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL_M  (GPIOSD_ETM_TASK_GPIO9_SEL_V << GPIOSD_ETM_TASK_GPIO9_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO10_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO10_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO10_EN_M  (GPIOSD_ETM_TASK_GPIO10_EN_V << GPIOSD_ETM_TASK_GPIO10_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO10_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO10_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO10_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL_M  (GPIOSD_ETM_TASK_GPIO10_SEL_V << GPIOSD_ETM_TASK_GPIO10_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO11_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO11_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO11_EN_M  (GPIOSD_ETM_TASK_GPIO11_EN_V << GPIOSD_ETM_TASK_GPIO11_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO11_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO11_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO11_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL_M  (GPIOSD_ETM_TASK_GPIO11_SEL_V << GPIOSD_ETM_TASK_GPIO11_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P3_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIOSD_BASE + 0xac)
+/** GPIOSD_ETM_TASK_GPIO12_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO12_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO12_EN_M  (GPIOSD_ETM_TASK_GPIO12_EN_V << GPIOSD_ETM_TASK_GPIO12_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO12_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO12_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO12_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL_M  (GPIOSD_ETM_TASK_GPIO12_SEL_V << GPIOSD_ETM_TASK_GPIO12_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO13_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO13_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO13_EN_M  (GPIOSD_ETM_TASK_GPIO13_EN_V << GPIOSD_ETM_TASK_GPIO13_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO13_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO13_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO13_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL_M  (GPIOSD_ETM_TASK_GPIO13_SEL_V << GPIOSD_ETM_TASK_GPIO13_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO14_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO14_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO14_EN_M  (GPIOSD_ETM_TASK_GPIO14_EN_V << GPIOSD_ETM_TASK_GPIO14_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO14_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO14_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO14_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL_M  (GPIOSD_ETM_TASK_GPIO14_SEL_V << GPIOSD_ETM_TASK_GPIO14_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO15_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO15_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO15_EN_M  (GPIOSD_ETM_TASK_GPIO15_EN_V << GPIOSD_ETM_TASK_GPIO15_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO15_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO15_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO15_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL_M  (GPIOSD_ETM_TASK_GPIO15_SEL_V << GPIOSD_ETM_TASK_GPIO15_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P4_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIOSD_BASE + 0xb0)
+/** GPIOSD_ETM_TASK_GPIO16_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO16_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO16_EN_M  (GPIOSD_ETM_TASK_GPIO16_EN_V << GPIOSD_ETM_TASK_GPIO16_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO16_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO16_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO16_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL_M  (GPIOSD_ETM_TASK_GPIO16_SEL_V << GPIOSD_ETM_TASK_GPIO16_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO17_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO17_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO17_EN_M  (GPIOSD_ETM_TASK_GPIO17_EN_V << GPIOSD_ETM_TASK_GPIO17_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO17_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO17_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO17_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL_M  (GPIOSD_ETM_TASK_GPIO17_SEL_V << GPIOSD_ETM_TASK_GPIO17_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO18_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO18_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO18_EN_M  (GPIOSD_ETM_TASK_GPIO18_EN_V << GPIOSD_ETM_TASK_GPIO18_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO18_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO18_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO18_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL_M  (GPIOSD_ETM_TASK_GPIO18_SEL_V << GPIOSD_ETM_TASK_GPIO18_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO19_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO19_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO19_EN_M  (GPIOSD_ETM_TASK_GPIO19_EN_V << GPIOSD_ETM_TASK_GPIO19_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO19_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO19_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO19_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL_M  (GPIOSD_ETM_TASK_GPIO19_SEL_V << GPIOSD_ETM_TASK_GPIO19_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P5_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIOSD_BASE + 0xb4)
+/** GPIOSD_ETM_TASK_GPIO20_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO20_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO20_EN_M  (GPIOSD_ETM_TASK_GPIO20_EN_V << GPIOSD_ETM_TASK_GPIO20_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO20_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO20_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO20_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL_M  (GPIOSD_ETM_TASK_GPIO20_SEL_V << GPIOSD_ETM_TASK_GPIO20_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO21_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO21_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO21_EN_M  (GPIOSD_ETM_TASK_GPIO21_EN_V << GPIOSD_ETM_TASK_GPIO21_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO21_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO21_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO21_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL_M  (GPIOSD_ETM_TASK_GPIO21_SEL_V << GPIOSD_ETM_TASK_GPIO21_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO22_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO22_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO22_EN_M  (GPIOSD_ETM_TASK_GPIO22_EN_V << GPIOSD_ETM_TASK_GPIO22_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO22_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO22_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO22_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL_M  (GPIOSD_ETM_TASK_GPIO22_SEL_V << GPIOSD_ETM_TASK_GPIO22_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO23_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO23_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO23_EN_M  (GPIOSD_ETM_TASK_GPIO23_EN_V << GPIOSD_ETM_TASK_GPIO23_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO23_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO23_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO23_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL_M  (GPIOSD_ETM_TASK_GPIO23_SEL_V << GPIOSD_ETM_TASK_GPIO23_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P6_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P6_CFG_REG (DR_REG_GPIOSD_BASE + 0xb8)
+/** GPIOSD_ETM_TASK_GPIO24_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO24_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO24_EN_M  (GPIOSD_ETM_TASK_GPIO24_EN_V << GPIOSD_ETM_TASK_GPIO24_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO24_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO24_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO24_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL_M  (GPIOSD_ETM_TASK_GPIO24_SEL_V << GPIOSD_ETM_TASK_GPIO24_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO25_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO25_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO25_EN_M  (GPIOSD_ETM_TASK_GPIO25_EN_V << GPIOSD_ETM_TASK_GPIO25_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO25_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO25_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO25_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL_M  (GPIOSD_ETM_TASK_GPIO25_SEL_V << GPIOSD_ETM_TASK_GPIO25_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO26_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO26_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO26_EN_M  (GPIOSD_ETM_TASK_GPIO26_EN_V << GPIOSD_ETM_TASK_GPIO26_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO26_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO26_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO26_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL_M  (GPIOSD_ETM_TASK_GPIO26_SEL_V << GPIOSD_ETM_TASK_GPIO26_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO27_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO27_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO27_EN_M  (GPIOSD_ETM_TASK_GPIO27_EN_V << GPIOSD_ETM_TASK_GPIO27_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO27_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO27_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO27_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL_M  (GPIOSD_ETM_TASK_GPIO27_SEL_V << GPIOSD_ETM_TASK_GPIO27_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P7_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P7_CFG_REG (DR_REG_GPIOSD_BASE + 0xbc)
+/** GPIOSD_ETM_TASK_GPIO28_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO28_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO28_EN_M  (GPIOSD_ETM_TASK_GPIO28_EN_V << GPIOSD_ETM_TASK_GPIO28_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO28_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO28_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO28_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL_M  (GPIOSD_ETM_TASK_GPIO28_SEL_V << GPIOSD_ETM_TASK_GPIO28_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO29_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO29_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO29_EN_M  (GPIOSD_ETM_TASK_GPIO29_EN_V << GPIOSD_ETM_TASK_GPIO29_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO29_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO29_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO29_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL_M  (GPIOSD_ETM_TASK_GPIO29_SEL_V << GPIOSD_ETM_TASK_GPIO29_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO30_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO30_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO30_EN_M  (GPIOSD_ETM_TASK_GPIO30_EN_V << GPIOSD_ETM_TASK_GPIO30_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO30_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO30_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO30_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL_M  (GPIOSD_ETM_TASK_GPIO30_SEL_V << GPIOSD_ETM_TASK_GPIO30_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO31_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO31_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO31_EN_M  (GPIOSD_ETM_TASK_GPIO31_EN_V << GPIOSD_ETM_TASK_GPIO31_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO31_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO31_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO31_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL_M  (GPIOSD_ETM_TASK_GPIO31_SEL_V << GPIOSD_ETM_TASK_GPIO31_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P8_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P8_CFG_REG (DR_REG_GPIOSD_BASE + 0xc0)
+/** GPIOSD_ETM_TASK_GPIO32_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO32_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO32_EN_M  (GPIOSD_ETM_TASK_GPIO32_EN_V << GPIOSD_ETM_TASK_GPIO32_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO32_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO32_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO32_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL_M  (GPIOSD_ETM_TASK_GPIO32_SEL_V << GPIOSD_ETM_TASK_GPIO32_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO33_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO33_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO33_EN_M  (GPIOSD_ETM_TASK_GPIO33_EN_V << GPIOSD_ETM_TASK_GPIO33_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO33_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO33_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO33_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL_M  (GPIOSD_ETM_TASK_GPIO33_SEL_V << GPIOSD_ETM_TASK_GPIO33_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO34_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO34_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO34_EN_M  (GPIOSD_ETM_TASK_GPIO34_EN_V << GPIOSD_ETM_TASK_GPIO34_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO34_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO34_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO34_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL_M  (GPIOSD_ETM_TASK_GPIO34_SEL_V << GPIOSD_ETM_TASK_GPIO34_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO35_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO35_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO35_EN_M  (GPIOSD_ETM_TASK_GPIO35_EN_V << GPIOSD_ETM_TASK_GPIO35_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO35_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO35_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO35_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL_M  (GPIOSD_ETM_TASK_GPIO35_SEL_V << GPIOSD_ETM_TASK_GPIO35_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P9_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P9_CFG_REG (DR_REG_GPIOSD_BASE + 0xc4)
+/** GPIOSD_ETM_TASK_GPIO36_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO36_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO36_EN_M  (GPIOSD_ETM_TASK_GPIO36_EN_V << GPIOSD_ETM_TASK_GPIO36_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO36_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO36_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO36_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL_M  (GPIOSD_ETM_TASK_GPIO36_SEL_V << GPIOSD_ETM_TASK_GPIO36_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO37_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO37_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO37_EN_M  (GPIOSD_ETM_TASK_GPIO37_EN_V << GPIOSD_ETM_TASK_GPIO37_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO37_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO37_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO37_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL_M  (GPIOSD_ETM_TASK_GPIO37_SEL_V << GPIOSD_ETM_TASK_GPIO37_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO38_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO38_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO38_EN_M  (GPIOSD_ETM_TASK_GPIO38_EN_V << GPIOSD_ETM_TASK_GPIO38_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO38_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO38_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO38_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL_M  (GPIOSD_ETM_TASK_GPIO38_SEL_V << GPIOSD_ETM_TASK_GPIO38_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO39_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO39_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO39_EN_M  (GPIOSD_ETM_TASK_GPIO39_EN_V << GPIOSD_ETM_TASK_GPIO39_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO39_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO39_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO39_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL_M  (GPIOSD_ETM_TASK_GPIO39_SEL_V << GPIOSD_ETM_TASK_GPIO39_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P10_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P10_CFG_REG (DR_REG_GPIOSD_BASE + 0xc8)
+/** GPIOSD_ETM_TASK_GPIO40_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO40_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO40_EN_M  (GPIOSD_ETM_TASK_GPIO40_EN_V << GPIOSD_ETM_TASK_GPIO40_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO40_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO40_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO40_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL_M  (GPIOSD_ETM_TASK_GPIO40_SEL_V << GPIOSD_ETM_TASK_GPIO40_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO41_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO41_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO41_EN_M  (GPIOSD_ETM_TASK_GPIO41_EN_V << GPIOSD_ETM_TASK_GPIO41_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO41_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO41_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO41_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL_M  (GPIOSD_ETM_TASK_GPIO41_SEL_V << GPIOSD_ETM_TASK_GPIO41_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO42_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO42_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO42_EN_M  (GPIOSD_ETM_TASK_GPIO42_EN_V << GPIOSD_ETM_TASK_GPIO42_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO42_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO42_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO42_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL_M  (GPIOSD_ETM_TASK_GPIO42_SEL_V << GPIOSD_ETM_TASK_GPIO42_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO43_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO43_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO43_EN_M  (GPIOSD_ETM_TASK_GPIO43_EN_V << GPIOSD_ETM_TASK_GPIO43_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO43_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO43_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO43_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL_M  (GPIOSD_ETM_TASK_GPIO43_SEL_V << GPIOSD_ETM_TASK_GPIO43_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P11_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P11_CFG_REG (DR_REG_GPIOSD_BASE + 0xcc)
+/** GPIOSD_ETM_TASK_GPIO44_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO44_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO44_EN_M  (GPIOSD_ETM_TASK_GPIO44_EN_V << GPIOSD_ETM_TASK_GPIO44_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO44_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO44_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO44_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL_M  (GPIOSD_ETM_TASK_GPIO44_SEL_V << GPIOSD_ETM_TASK_GPIO44_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO45_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO45_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO45_EN_M  (GPIOSD_ETM_TASK_GPIO45_EN_V << GPIOSD_ETM_TASK_GPIO45_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO45_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO45_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO45_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL_M  (GPIOSD_ETM_TASK_GPIO45_SEL_V << GPIOSD_ETM_TASK_GPIO45_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO46_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO46_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO46_EN_M  (GPIOSD_ETM_TASK_GPIO46_EN_V << GPIOSD_ETM_TASK_GPIO46_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO46_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO46_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO46_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL_M  (GPIOSD_ETM_TASK_GPIO46_SEL_V << GPIOSD_ETM_TASK_GPIO46_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO47_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO47_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO47_EN_M  (GPIOSD_ETM_TASK_GPIO47_EN_V << GPIOSD_ETM_TASK_GPIO47_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO47_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO47_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO47_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL_M  (GPIOSD_ETM_TASK_GPIO47_SEL_V << GPIOSD_ETM_TASK_GPIO47_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P12_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P12_CFG_REG (DR_REG_GPIOSD_BASE + 0xd0)
+/** GPIOSD_ETM_TASK_GPIO48_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO48_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO48_EN_M  (GPIOSD_ETM_TASK_GPIO48_EN_V << GPIOSD_ETM_TASK_GPIO48_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO48_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO48_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO48_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL_M  (GPIOSD_ETM_TASK_GPIO48_SEL_V << GPIOSD_ETM_TASK_GPIO48_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO49_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO49_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO49_EN_M  (GPIOSD_ETM_TASK_GPIO49_EN_V << GPIOSD_ETM_TASK_GPIO49_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO49_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO49_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO49_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL_M  (GPIOSD_ETM_TASK_GPIO49_SEL_V << GPIOSD_ETM_TASK_GPIO49_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO50_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO50_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO50_EN_M  (GPIOSD_ETM_TASK_GPIO50_EN_V << GPIOSD_ETM_TASK_GPIO50_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO50_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO50_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO50_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL_M  (GPIOSD_ETM_TASK_GPIO50_SEL_V << GPIOSD_ETM_TASK_GPIO50_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL_S  17
+/** GPIOSD_ETM_TASK_GPIO51_EN : R/W; bitpos: [24]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO51_EN    (BIT(24))
+#define GPIO_EXT_ETM_TASK_GPIO51_EN_M  (GPIOSD_ETM_TASK_GPIO51_EN_V << GPIOSD_ETM_TASK_GPIO51_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO51_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO51_EN_S  24
+/** GPIOSD_ETM_TASK_GPIO51_SEL : R/W; bitpos: [27:25]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL_M  (GPIOSD_ETM_TASK_GPIO51_SEL_V << GPIOSD_ETM_TASK_GPIO51_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL_S  25
+
+/** GPIOSD_ETM_TASK_P13_CFG_REG register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+#define GPIO_EXT_ETM_TASK_P13_CFG_REG (DR_REG_GPIOSD_BASE + 0xd4)
+/** GPIOSD_ETM_TASK_GPIO52_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO52_EN    (BIT(0))
+#define GPIO_EXT_ETM_TASK_GPIO52_EN_M  (GPIOSD_ETM_TASK_GPIO52_EN_V << GPIOSD_ETM_TASK_GPIO52_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO52_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO52_EN_S  0
+/** GPIOSD_ETM_TASK_GPIO52_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL_M  (GPIOSD_ETM_TASK_GPIO52_SEL_V << GPIOSD_ETM_TASK_GPIO52_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL_S  1
+/** GPIOSD_ETM_TASK_GPIO53_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO53_EN    (BIT(8))
+#define GPIO_EXT_ETM_TASK_GPIO53_EN_M  (GPIOSD_ETM_TASK_GPIO53_EN_V << GPIOSD_ETM_TASK_GPIO53_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO53_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO53_EN_S  8
+/** GPIOSD_ETM_TASK_GPIO53_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL_M  (GPIOSD_ETM_TASK_GPIO53_SEL_V << GPIOSD_ETM_TASK_GPIO53_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL_S  9
+/** GPIOSD_ETM_TASK_GPIO54_EN : R/W; bitpos: [16]; default: 0;
+ *  Enable bit of GPIO response etm task.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO54_EN    (BIT(16))
+#define GPIO_EXT_ETM_TASK_GPIO54_EN_M  (GPIOSD_ETM_TASK_GPIO54_EN_V << GPIOSD_ETM_TASK_GPIO54_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO54_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO54_EN_S  16
+/** GPIOSD_ETM_TASK_GPIO54_SEL : R/W; bitpos: [19:17]; default: 0;
+ *  GPIO choose a etm task channel.
+ */
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL_M  (GPIOSD_ETM_TASK_GPIO54_SEL_V << GPIOSD_ETM_TASK_GPIO54_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL_S  17
+
+/** GPIOSD_VERSION_REG register
+ *  Version Control Register
+ */
+#define GPIO_EXT_VERSION_REG (DR_REG_GPIOSD_BASE + 0xfc)
+/** GPIOSD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 35663952;
+ *  Version control register.
+ */
+#define GPIO_EXT_GPIO_SD_DATE    0x0FFFFFFFU
+#define GPIO_EXT_GPIO_SD_DATE_M  (GPIOSD_GPIO_SD_DATE_V << GPIOSD_GPIO_SD_DATE_S)
+#define GPIO_EXT_GPIO_SD_DATE_V  0x0FFFFFFFU
+#define GPIO_EXT_GPIO_SD_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_struct.h
new file mode 100644
index 0000000000..617c6be66c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/gpio_ext_struct.h
@@ -0,0 +1,194 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: SDM Configure Registers */
+/** Type of sigmadeltan register
+ *  Duty Cycle Configure Register of SDMn
+ */
+typedef union {
+    struct {
+        /** duty : R/W; bitpos: [7:0]; default: 0;
+         *  This field is used to configure the duty cycle of sigma delta modulation output.
+         */
+        uint32_t duty: 8;
+        /** prescale : R/W; bitpos: [15:8]; default: 255;
+         *  This field is used to set a divider value to divide APB clock.
+         */
+        uint32_t prescale: 8;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} gpio_sigmadelta_chn_reg_t;
+
+/** Type of sigmadelta_misc register
+ *  MISC Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 30;
+        /** function_clk_en : R/W; bitpos: [30]; default: 0;
+         *  Clock enable bit of sigma delta modulation.
+         */
+        uint32_t function_clk_en: 1;
+        /** spi_swap : R/W; bitpos: [31]; default: 0;
+         *  Reserved.
+         */
+        uint32_t spi_swap: 1;
+    };
+    uint32_t val;
+} gpio_sigmadelta_misc_reg_t;
+
+/** Group: Glitch filter Configure Registers */
+/** Type of glitch_filter_chn register
+ *  Glitch Filter Configure Register of Channeln
+ */
+typedef union {
+    struct {
+        /** filter_chn_en : R/W; bitpos: [0]; default: 0;
+         *  Glitch Filter channel enable bit.
+         */
+        uint32_t filter_chn_en: 1;
+        /** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
+         *  Glitch Filter input io number.
+         */
+        uint32_t filter_chn_input_io_num: 6;
+        /** filter_chn_window_thres : R/W; bitpos: [12:7]; default: 0;
+         *  Glitch Filter window threshold.
+         */
+        uint32_t filter_chn_window_thres: 6;
+        /** filter_chn_window_width : R/W; bitpos: [18:13]; default: 0;
+         *  Glitch Filter window width.
+         */
+        uint32_t filter_chn_window_width: 6;
+        uint32_t reserved_19: 13;
+    };
+    uint32_t val;
+} gpio_glitch_filter_chn_reg_t;
+
+/** Group: Etm Configure Registers */
+/** Type of etm_event_chn_cfg register
+ *  Etm Config register of Channeln
+ */
+typedef union {
+    struct {
+        /** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0;
+         *  Etm event channel select gpio.
+         */
+        uint32_t etm_chn_event_sel: 6;
+        uint32_t reserved_6: 1;
+        /** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
+         *  Etm event send enable bit.
+         */
+        uint32_t etm_chn_event_en: 1;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} gpio_etm_event_chn_cfg_reg_t;
+
+/** Type of etm_task_p0_cfg register
+ *  Etm Configure Register to decide which GPIO been chosen
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio0_en: 1;
+        /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio0_sel: 3;
+        uint32_t reserved_4: 4;
+        /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio1_en: 1;
+        /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio1_sel: 3;
+        uint32_t reserved_12: 4;
+        /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio2_en: 1;
+        /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio2_sel: 3;
+        uint32_t reserved_20: 4;
+        /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
+         *  Enable bit of GPIO response etm task.
+         */
+        uint32_t etm_task_gpio3_en: 1;
+        /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
+         *  GPIO choose a etm task channel.
+         */
+        uint32_t etm_task_gpio3_sel: 3;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} gpio_etm_task_pn_cfg_reg_t;
+
+/** Group: Version Register */
+/** Type of version register
+ *  Version Control Register
+ */
+typedef union {
+    struct {
+        /** gpio_ext_date : R/W; bitpos: [27:0]; default: 35663952;
+         *  Version control register.
+         */
+        uint32_t gpio_ext_date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} gpio_ext_version_reg_t;
+
+typedef struct gpio_sd_dev_t {
+    volatile gpio_sigmadelta_chn_reg_t channel[8];
+    uint32_t reserved_020;
+    volatile gpio_sigmadelta_misc_reg_t misc;
+} gpio_sd_dev_t;
+
+typedef struct gpio_glitch_filter_dev_t {
+    volatile gpio_glitch_filter_chn_reg_t glitch_filter_chn[8];
+} gpio_glitch_filter_dev_t;
+
+typedef struct gpio_etm_dev_t {
+    volatile gpio_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
+    uint32_t reserved_080[8];
+    volatile gpio_etm_task_pn_cfg_reg_t etm_task_pn_cfg[14];
+} gpio_etm_dev_t;
+
+typedef struct {
+    volatile gpio_sd_dev_t sigma_delta;
+    uint32_t reserved_028[2];
+    volatile gpio_glitch_filter_dev_t glitch_filter;
+    uint32_t reserved_050[4];
+    volatile gpio_etm_dev_t etm;
+    uint32_t reserved_0d8[9];
+    volatile gpio_ext_version_reg_t version;
+} gpio_ext_dev_t;
+
+extern gpio_sd_dev_t SDM;
+extern gpio_glitch_filter_dev_t GLITCH_FILTER;
+extern gpio_etm_dev_t GPIO_ETM;
+extern gpio_ext_dev_t GPIO_EXT;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_ext_dev_t) == 0x100, "Invalid size of gpio_ext_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/gpio_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/gpio_reg.h
new file mode 100644
index 0000000000..af324fea51
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/gpio_reg.h
@@ -0,0 +1,12163 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO_BT_SELECT_REG register
+ *  GPIO bit select register
+ */
+#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0)
+/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0;
+ *  GPIO bit select register
+ */
+#define GPIO_BT_SEL    0xFFFFFFFFU
+#define GPIO_BT_SEL_M  (GPIO_BT_SEL_V << GPIO_BT_SEL_S)
+#define GPIO_BT_SEL_V  0xFFFFFFFFU
+#define GPIO_BT_SEL_S  0
+
+/** GPIO_OUT_REG register
+ *  GPIO output register for GPIO0-31
+ */
+#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
+/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+ *  GPIO output register for GPIO0-31
+ */
+#define GPIO_OUT_DATA_ORIG    0xFFFFFFFFU
+#define GPIO_OUT_DATA_ORIG_M  (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S)
+#define GPIO_OUT_DATA_ORIG_V  0xFFFFFFFFU
+#define GPIO_OUT_DATA_ORIG_S  0
+
+/** GPIO_OUT_W1TS_REG register
+ *  GPIO output set register for GPIO0-31
+ */
+#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
+/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output set register for GPIO0-31
+ */
+#define GPIO_OUT_W1TS    0xFFFFFFFFU
+#define GPIO_OUT_W1TS_M  (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S)
+#define GPIO_OUT_W1TS_V  0xFFFFFFFFU
+#define GPIO_OUT_W1TS_S  0
+
+/** GPIO_OUT_W1TC_REG register
+ *  GPIO output clear register for GPIO0-31
+ */
+#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
+/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output clear register for GPIO0-31
+ */
+#define GPIO_OUT_W1TC    0xFFFFFFFFU
+#define GPIO_OUT_W1TC_M  (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S)
+#define GPIO_OUT_W1TC_V  0xFFFFFFFFU
+#define GPIO_OUT_W1TC_S  0
+
+/** GPIO_OUT1_REG register
+ *  GPIO output register for GPIO32-56
+ */
+#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10)
+/** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [24:0]; default: 0;
+ *  GPIO output register for GPIO32-56
+ */
+#define GPIO_OUT1_DATA_ORIG    0x01FFFFFFU
+#define GPIO_OUT1_DATA_ORIG_M  (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S)
+#define GPIO_OUT1_DATA_ORIG_V  0x01FFFFFFU
+#define GPIO_OUT1_DATA_ORIG_S  0
+
+/** GPIO_OUT1_W1TS_REG register
+ *  GPIO output set register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14)
+/** GPIO_OUT1_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output set register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TS    0x01FFFFFFU
+#define GPIO_OUT1_W1TS_M  (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S)
+#define GPIO_OUT1_W1TS_V  0x01FFFFFFU
+#define GPIO_OUT1_W1TS_S  0
+
+/** GPIO_OUT1_W1TC_REG register
+ *  GPIO output clear register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18)
+/** GPIO_OUT1_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output clear register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TC    0x01FFFFFFU
+#define GPIO_OUT1_W1TC_M  (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S)
+#define GPIO_OUT1_W1TC_V  0x01FFFFFFU
+#define GPIO_OUT1_W1TC_S  0
+
+/** GPIO_ENABLE_REG register
+ *  GPIO output enable register for GPIO0-31
+ */
+#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20)
+/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  GPIO output enable register for GPIO0-31
+ */
+#define GPIO_ENABLE_DATA    0xFFFFFFFFU
+#define GPIO_ENABLE_DATA_M  (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S)
+#define GPIO_ENABLE_DATA_V  0xFFFFFFFFU
+#define GPIO_ENABLE_DATA_S  0
+
+/** GPIO_ENABLE_W1TS_REG register
+ *  GPIO output enable set register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24)
+/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output enable set register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TS    0xFFFFFFFFU
+#define GPIO_ENABLE_W1TS_M  (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S)
+#define GPIO_ENABLE_W1TS_V  0xFFFFFFFFU
+#define GPIO_ENABLE_W1TS_S  0
+
+/** GPIO_ENABLE_W1TC_REG register
+ *  GPIO output enable clear register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28)
+/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output enable clear register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TC    0xFFFFFFFFU
+#define GPIO_ENABLE_W1TC_M  (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S)
+#define GPIO_ENABLE_W1TC_V  0xFFFFFFFFU
+#define GPIO_ENABLE_W1TC_S  0
+
+/** GPIO_ENABLE1_REG register
+ *  GPIO output enable register for GPIO32-56
+ */
+#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c)
+/** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [24:0]; default: 0;
+ *  GPIO output enable register for GPIO32-56
+ */
+#define GPIO_ENABLE1_DATA    0x01FFFFFFU
+#define GPIO_ENABLE1_DATA_M  (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S)
+#define GPIO_ENABLE1_DATA_V  0x01FFFFFFU
+#define GPIO_ENABLE1_DATA_S  0
+
+/** GPIO_ENABLE1_W1TS_REG register
+ *  GPIO output enable set register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30)
+/** GPIO_ENABLE1_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output enable set register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TS    0x01FFFFFFU
+#define GPIO_ENABLE1_W1TS_M  (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S)
+#define GPIO_ENABLE1_W1TS_V  0x01FFFFFFU
+#define GPIO_ENABLE1_W1TS_S  0
+
+/** GPIO_ENABLE1_W1TC_REG register
+ *  GPIO output enable clear register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34)
+/** GPIO_ENABLE1_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output enable clear register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TC    0x01FFFFFFU
+#define GPIO_ENABLE1_W1TC_M  (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S)
+#define GPIO_ENABLE1_W1TC_V  0x01FFFFFFU
+#define GPIO_ENABLE1_W1TC_S  0
+
+/** GPIO_STRAP_REG register
+ *  pad strapping register
+ */
+#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38)
+/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
+ *  pad strapping register
+ */
+#define GPIO_STRAPPING    0x0000FFFFU
+#define GPIO_STRAPPING_M  (GPIO_STRAPPING_V << GPIO_STRAPPING_S)
+#define GPIO_STRAPPING_V  0x0000FFFFU
+#define GPIO_STRAPPING_S  0
+
+/** GPIO_IN_REG register
+ *  GPIO input register for GPIO0-31
+ */
+#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c)
+/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0;
+ *  GPIO input register for GPIO0-31
+ */
+#define GPIO_IN_DATA_NEXT    0xFFFFFFFFU
+#define GPIO_IN_DATA_NEXT_M  (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S)
+#define GPIO_IN_DATA_NEXT_V  0xFFFFFFFFU
+#define GPIO_IN_DATA_NEXT_S  0
+
+/** GPIO_IN1_REG register
+ *  GPIO input register for GPIO32-56
+ */
+#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40)
+/** GPIO_IN1_DATA_NEXT : RO; bitpos: [24:0]; default: 0;
+ *  GPIO input register for GPIO32-56
+ */
+#define GPIO_IN1_DATA_NEXT    0x01FFFFFFU
+#define GPIO_IN1_DATA_NEXT_M  (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S)
+#define GPIO_IN1_DATA_NEXT_V  0x01FFFFFFU
+#define GPIO_IN1_DATA_NEXT_S  0
+
+/** GPIO_STATUS_REG register
+ *  GPIO interrupt status register for GPIO0-31
+ */
+#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44)
+/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt status register for GPIO0-31
+ */
+#define GPIO_STATUS_INTERRUPT    0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_M  (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S)
+#define GPIO_STATUS_INTERRUPT_V  0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_S  0
+
+/** GPIO_STATUS_W1TS_REG register
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48)
+/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TS    0xFFFFFFFFU
+#define GPIO_STATUS_W1TS_M  (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S)
+#define GPIO_STATUS_W1TS_V  0xFFFFFFFFU
+#define GPIO_STATUS_W1TS_S  0
+
+/** GPIO_STATUS_W1TC_REG register
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c)
+/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TC    0xFFFFFFFFU
+#define GPIO_STATUS_W1TC_M  (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S)
+#define GPIO_STATUS_W1TC_V  0xFFFFFFFFU
+#define GPIO_STATUS_W1TC_S  0
+
+/** GPIO_STATUS1_REG register
+ *  GPIO interrupt status register for GPIO32-56
+ */
+#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50)
+/** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status register for GPIO32-56
+ */
+#define GPIO_STATUS1_INTERRUPT    0x01FFFFFFU
+#define GPIO_STATUS1_INTERRUPT_M  (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S)
+#define GPIO_STATUS1_INTERRUPT_V  0x01FFFFFFU
+#define GPIO_STATUS1_INTERRUPT_S  0
+
+/** GPIO_STATUS1_W1TS_REG register
+ *  GPIO interrupt status set register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54)
+/** GPIO_STATUS1_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status set register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TS    0x01FFFFFFU
+#define GPIO_STATUS1_W1TS_M  (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S)
+#define GPIO_STATUS1_W1TS_V  0x01FFFFFFU
+#define GPIO_STATUS1_W1TS_S  0
+
+/** GPIO_STATUS1_W1TC_REG register
+ *  GPIO interrupt status clear register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58)
+/** GPIO_STATUS1_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status clear register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TC    0x01FFFFFFU
+#define GPIO_STATUS1_W1TC_M  (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S)
+#define GPIO_STATUS1_W1TC_V  0x01FFFFFFU
+#define GPIO_STATUS1_W1TC_S  0
+
+/** GPIO_INTR_0_REG register
+ *  GPIO interrupt 0 status register for GPIO0-31
+ */
+#define GPIO_INTR_0_REG (DR_REG_GPIO_BASE + 0x5c)
+/** GPIO_INT_0 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 0 status register for GPIO0-31
+ */
+#define GPIO_INT_0    0xFFFFFFFFU
+#define GPIO_INT_0_M  (GPIO_INT_0_V << GPIO_INT_0_S)
+#define GPIO_INT_0_V  0xFFFFFFFFU
+#define GPIO_INT_0_S  0
+
+/** GPIO_INTR1_0_REG register
+ *  GPIO interrupt 0 status register for GPIO32-56
+ */
+#define GPIO_INTR1_0_REG (DR_REG_GPIO_BASE + 0x60)
+/** GPIO_INT1_0 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 0 status register for GPIO32-56
+ */
+#define GPIO_INT1_0    0x01FFFFFFU
+#define GPIO_INT1_0_M  (GPIO_INT1_0_V << GPIO_INT1_0_S)
+#define GPIO_INT1_0_V  0x01FFFFFFU
+#define GPIO_INT1_0_S  0
+
+/** GPIO_INTR_1_REG register
+ *  GPIO interrupt 1 status register for GPIO0-31
+ */
+#define GPIO_INTR_1_REG (DR_REG_GPIO_BASE + 0x64)
+/** GPIO_INT_1 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 1 status register for GPIO0-31
+ */
+#define GPIO_INT_1    0xFFFFFFFFU
+#define GPIO_INT_1_M  (GPIO_INT_1_V << GPIO_INT_1_S)
+#define GPIO_INT_1_V  0xFFFFFFFFU
+#define GPIO_INT_1_S  0
+
+/** GPIO_INTR1_1_REG register
+ *  GPIO interrupt 1 status register for GPIO32-56
+ */
+#define GPIO_INTR1_1_REG (DR_REG_GPIO_BASE + 0x68)
+/** GPIO_INT1_1 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 1 status register for GPIO32-56
+ */
+#define GPIO_INT1_1    0x01FFFFFFU
+#define GPIO_INT1_1_M  (GPIO_INT1_1_V << GPIO_INT1_1_S)
+#define GPIO_INT1_1_V  0x01FFFFFFU
+#define GPIO_INT1_1_S  0
+
+/** GPIO_STATUS_NEXT_REG register
+ *  GPIO interrupt source register for GPIO0-31
+ */
+#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x6c)
+/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt source register for GPIO0-31
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT    0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_M  (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S)
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+/** GPIO_STATUS_NEXT1_REG register
+ *  GPIO interrupt source register for GPIO32-56
+ */
+#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x70)
+/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt source register for GPIO32-56
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT1    0x01FFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT1_M  (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S)
+#define GPIO_STATUS_INTERRUPT_NEXT1_V  0x01FFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT1_S  0
+
+/** GPIO_PIN0_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74)
+/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN0_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_M  (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S)
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S)
+#define GPIO_PIN0_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN0_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_M  (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S)
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN0_INT_TYPE    0x00000007U
+#define GPIO_PIN0_INT_TYPE_M  (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S)
+#define GPIO_PIN0_INT_TYPE_V  0x00000007U
+#define GPIO_PIN0_INT_TYPE_S  7
+/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S)
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN0_CONFIG    0x00000003U
+#define GPIO_PIN0_CONFIG_M  (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S)
+#define GPIO_PIN0_CONFIG_V  0x00000003U
+#define GPIO_PIN0_CONFIG_S  11
+/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN0_INT_ENA    0x0000001FU
+#define GPIO_PIN0_INT_ENA_M  (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S)
+#define GPIO_PIN0_INT_ENA_V  0x0000001FU
+#define GPIO_PIN0_INT_ENA_S  13
+
+/** GPIO_PIN1_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78)
+/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN1_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_M  (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S)
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S)
+#define GPIO_PIN1_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN1_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_M  (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S)
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN1_INT_TYPE    0x00000007U
+#define GPIO_PIN1_INT_TYPE_M  (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S)
+#define GPIO_PIN1_INT_TYPE_V  0x00000007U
+#define GPIO_PIN1_INT_TYPE_S  7
+/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S)
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN1_CONFIG    0x00000003U
+#define GPIO_PIN1_CONFIG_M  (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S)
+#define GPIO_PIN1_CONFIG_V  0x00000003U
+#define GPIO_PIN1_CONFIG_S  11
+/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN1_INT_ENA    0x0000001FU
+#define GPIO_PIN1_INT_ENA_M  (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S)
+#define GPIO_PIN1_INT_ENA_V  0x0000001FU
+#define GPIO_PIN1_INT_ENA_S  13
+
+/** GPIO_PIN2_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c)
+/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN2_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_M  (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S)
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S)
+#define GPIO_PIN2_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN2_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_M  (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S)
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN2_INT_TYPE    0x00000007U
+#define GPIO_PIN2_INT_TYPE_M  (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S)
+#define GPIO_PIN2_INT_TYPE_V  0x00000007U
+#define GPIO_PIN2_INT_TYPE_S  7
+/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S)
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN2_CONFIG    0x00000003U
+#define GPIO_PIN2_CONFIG_M  (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S)
+#define GPIO_PIN2_CONFIG_V  0x00000003U
+#define GPIO_PIN2_CONFIG_S  11
+/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN2_INT_ENA    0x0000001FU
+#define GPIO_PIN2_INT_ENA_M  (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S)
+#define GPIO_PIN2_INT_ENA_V  0x0000001FU
+#define GPIO_PIN2_INT_ENA_S  13
+
+/** GPIO_PIN3_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80)
+/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN3_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_M  (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S)
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S)
+#define GPIO_PIN3_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN3_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_M  (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S)
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN3_INT_TYPE    0x00000007U
+#define GPIO_PIN3_INT_TYPE_M  (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S)
+#define GPIO_PIN3_INT_TYPE_V  0x00000007U
+#define GPIO_PIN3_INT_TYPE_S  7
+/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S)
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN3_CONFIG    0x00000003U
+#define GPIO_PIN3_CONFIG_M  (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S)
+#define GPIO_PIN3_CONFIG_V  0x00000003U
+#define GPIO_PIN3_CONFIG_S  11
+/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN3_INT_ENA    0x0000001FU
+#define GPIO_PIN3_INT_ENA_M  (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S)
+#define GPIO_PIN3_INT_ENA_V  0x0000001FU
+#define GPIO_PIN3_INT_ENA_S  13
+
+/** GPIO_PIN4_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84)
+/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN4_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_M  (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S)
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S)
+#define GPIO_PIN4_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN4_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_M  (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S)
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN4_INT_TYPE    0x00000007U
+#define GPIO_PIN4_INT_TYPE_M  (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S)
+#define GPIO_PIN4_INT_TYPE_V  0x00000007U
+#define GPIO_PIN4_INT_TYPE_S  7
+/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S)
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN4_CONFIG    0x00000003U
+#define GPIO_PIN4_CONFIG_M  (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S)
+#define GPIO_PIN4_CONFIG_V  0x00000003U
+#define GPIO_PIN4_CONFIG_S  11
+/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN4_INT_ENA    0x0000001FU
+#define GPIO_PIN4_INT_ENA_M  (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S)
+#define GPIO_PIN4_INT_ENA_V  0x0000001FU
+#define GPIO_PIN4_INT_ENA_S  13
+
+/** GPIO_PIN5_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88)
+/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN5_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_M  (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S)
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S)
+#define GPIO_PIN5_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN5_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_M  (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S)
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN5_INT_TYPE    0x00000007U
+#define GPIO_PIN5_INT_TYPE_M  (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S)
+#define GPIO_PIN5_INT_TYPE_V  0x00000007U
+#define GPIO_PIN5_INT_TYPE_S  7
+/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S)
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN5_CONFIG    0x00000003U
+#define GPIO_PIN5_CONFIG_M  (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S)
+#define GPIO_PIN5_CONFIG_V  0x00000003U
+#define GPIO_PIN5_CONFIG_S  11
+/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN5_INT_ENA    0x0000001FU
+#define GPIO_PIN5_INT_ENA_M  (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S)
+#define GPIO_PIN5_INT_ENA_V  0x0000001FU
+#define GPIO_PIN5_INT_ENA_S  13
+
+/** GPIO_PIN6_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c)
+/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN6_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_M  (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S)
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S)
+#define GPIO_PIN6_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN6_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_M  (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S)
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN6_INT_TYPE    0x00000007U
+#define GPIO_PIN6_INT_TYPE_M  (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S)
+#define GPIO_PIN6_INT_TYPE_V  0x00000007U
+#define GPIO_PIN6_INT_TYPE_S  7
+/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S)
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN6_CONFIG    0x00000003U
+#define GPIO_PIN6_CONFIG_M  (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S)
+#define GPIO_PIN6_CONFIG_V  0x00000003U
+#define GPIO_PIN6_CONFIG_S  11
+/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN6_INT_ENA    0x0000001FU
+#define GPIO_PIN6_INT_ENA_M  (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S)
+#define GPIO_PIN6_INT_ENA_V  0x0000001FU
+#define GPIO_PIN6_INT_ENA_S  13
+
+/** GPIO_PIN7_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90)
+/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN7_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_M  (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S)
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S)
+#define GPIO_PIN7_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN7_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_M  (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S)
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN7_INT_TYPE    0x00000007U
+#define GPIO_PIN7_INT_TYPE_M  (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S)
+#define GPIO_PIN7_INT_TYPE_V  0x00000007U
+#define GPIO_PIN7_INT_TYPE_S  7
+/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S)
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN7_CONFIG    0x00000003U
+#define GPIO_PIN7_CONFIG_M  (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S)
+#define GPIO_PIN7_CONFIG_V  0x00000003U
+#define GPIO_PIN7_CONFIG_S  11
+/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN7_INT_ENA    0x0000001FU
+#define GPIO_PIN7_INT_ENA_M  (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S)
+#define GPIO_PIN7_INT_ENA_V  0x0000001FU
+#define GPIO_PIN7_INT_ENA_S  13
+
+/** GPIO_PIN8_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94)
+/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN8_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_M  (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S)
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S)
+#define GPIO_PIN8_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN8_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_M  (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S)
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN8_INT_TYPE    0x00000007U
+#define GPIO_PIN8_INT_TYPE_M  (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S)
+#define GPIO_PIN8_INT_TYPE_V  0x00000007U
+#define GPIO_PIN8_INT_TYPE_S  7
+/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S)
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN8_CONFIG    0x00000003U
+#define GPIO_PIN8_CONFIG_M  (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S)
+#define GPIO_PIN8_CONFIG_V  0x00000003U
+#define GPIO_PIN8_CONFIG_S  11
+/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN8_INT_ENA    0x0000001FU
+#define GPIO_PIN8_INT_ENA_M  (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S)
+#define GPIO_PIN8_INT_ENA_V  0x0000001FU
+#define GPIO_PIN8_INT_ENA_S  13
+
+/** GPIO_PIN9_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98)
+/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN9_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_M  (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S)
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S)
+#define GPIO_PIN9_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN9_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_M  (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S)
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN9_INT_TYPE    0x00000007U
+#define GPIO_PIN9_INT_TYPE_M  (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S)
+#define GPIO_PIN9_INT_TYPE_V  0x00000007U
+#define GPIO_PIN9_INT_TYPE_S  7
+/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S)
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN9_CONFIG    0x00000003U
+#define GPIO_PIN9_CONFIG_M  (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S)
+#define GPIO_PIN9_CONFIG_V  0x00000003U
+#define GPIO_PIN9_CONFIG_S  11
+/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN9_INT_ENA    0x0000001FU
+#define GPIO_PIN9_INT_ENA_M  (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S)
+#define GPIO_PIN9_INT_ENA_V  0x0000001FU
+#define GPIO_PIN9_INT_ENA_S  13
+
+/** GPIO_PIN10_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c)
+/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN10_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_M  (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S)
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S)
+#define GPIO_PIN10_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN10_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_M  (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S)
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN10_INT_TYPE    0x00000007U
+#define GPIO_PIN10_INT_TYPE_M  (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S)
+#define GPIO_PIN10_INT_TYPE_V  0x00000007U
+#define GPIO_PIN10_INT_TYPE_S  7
+/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S)
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN10_CONFIG    0x00000003U
+#define GPIO_PIN10_CONFIG_M  (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S)
+#define GPIO_PIN10_CONFIG_V  0x00000003U
+#define GPIO_PIN10_CONFIG_S  11
+/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN10_INT_ENA    0x0000001FU
+#define GPIO_PIN10_INT_ENA_M  (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S)
+#define GPIO_PIN10_INT_ENA_V  0x0000001FU
+#define GPIO_PIN10_INT_ENA_S  13
+
+/** GPIO_PIN11_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0)
+/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN11_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_M  (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S)
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S)
+#define GPIO_PIN11_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN11_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_M  (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S)
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN11_INT_TYPE    0x00000007U
+#define GPIO_PIN11_INT_TYPE_M  (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S)
+#define GPIO_PIN11_INT_TYPE_V  0x00000007U
+#define GPIO_PIN11_INT_TYPE_S  7
+/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S)
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN11_CONFIG    0x00000003U
+#define GPIO_PIN11_CONFIG_M  (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S)
+#define GPIO_PIN11_CONFIG_V  0x00000003U
+#define GPIO_PIN11_CONFIG_S  11
+/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN11_INT_ENA    0x0000001FU
+#define GPIO_PIN11_INT_ENA_M  (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S)
+#define GPIO_PIN11_INT_ENA_V  0x0000001FU
+#define GPIO_PIN11_INT_ENA_S  13
+
+/** GPIO_PIN12_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4)
+/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN12_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_M  (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S)
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S)
+#define GPIO_PIN12_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN12_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_M  (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S)
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN12_INT_TYPE    0x00000007U
+#define GPIO_PIN12_INT_TYPE_M  (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S)
+#define GPIO_PIN12_INT_TYPE_V  0x00000007U
+#define GPIO_PIN12_INT_TYPE_S  7
+/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S)
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN12_CONFIG    0x00000003U
+#define GPIO_PIN12_CONFIG_M  (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S)
+#define GPIO_PIN12_CONFIG_V  0x00000003U
+#define GPIO_PIN12_CONFIG_S  11
+/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN12_INT_ENA    0x0000001FU
+#define GPIO_PIN12_INT_ENA_M  (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S)
+#define GPIO_PIN12_INT_ENA_V  0x0000001FU
+#define GPIO_PIN12_INT_ENA_S  13
+
+/** GPIO_PIN13_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8)
+/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN13_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_M  (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S)
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S)
+#define GPIO_PIN13_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN13_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_M  (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S)
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN13_INT_TYPE    0x00000007U
+#define GPIO_PIN13_INT_TYPE_M  (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S)
+#define GPIO_PIN13_INT_TYPE_V  0x00000007U
+#define GPIO_PIN13_INT_TYPE_S  7
+/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S)
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN13_CONFIG    0x00000003U
+#define GPIO_PIN13_CONFIG_M  (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S)
+#define GPIO_PIN13_CONFIG_V  0x00000003U
+#define GPIO_PIN13_CONFIG_S  11
+/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN13_INT_ENA    0x0000001FU
+#define GPIO_PIN13_INT_ENA_M  (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S)
+#define GPIO_PIN13_INT_ENA_V  0x0000001FU
+#define GPIO_PIN13_INT_ENA_S  13
+
+/** GPIO_PIN14_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac)
+/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN14_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_M  (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S)
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S)
+#define GPIO_PIN14_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN14_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_M  (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S)
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN14_INT_TYPE    0x00000007U
+#define GPIO_PIN14_INT_TYPE_M  (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S)
+#define GPIO_PIN14_INT_TYPE_V  0x00000007U
+#define GPIO_PIN14_INT_TYPE_S  7
+/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S)
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN14_CONFIG    0x00000003U
+#define GPIO_PIN14_CONFIG_M  (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S)
+#define GPIO_PIN14_CONFIG_V  0x00000003U
+#define GPIO_PIN14_CONFIG_S  11
+/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN14_INT_ENA    0x0000001FU
+#define GPIO_PIN14_INT_ENA_M  (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S)
+#define GPIO_PIN14_INT_ENA_V  0x0000001FU
+#define GPIO_PIN14_INT_ENA_S  13
+
+/** GPIO_PIN15_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0)
+/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN15_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_M  (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S)
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S)
+#define GPIO_PIN15_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN15_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_M  (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S)
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN15_INT_TYPE    0x00000007U
+#define GPIO_PIN15_INT_TYPE_M  (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S)
+#define GPIO_PIN15_INT_TYPE_V  0x00000007U
+#define GPIO_PIN15_INT_TYPE_S  7
+/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S)
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN15_CONFIG    0x00000003U
+#define GPIO_PIN15_CONFIG_M  (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S)
+#define GPIO_PIN15_CONFIG_V  0x00000003U
+#define GPIO_PIN15_CONFIG_S  11
+/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN15_INT_ENA    0x0000001FU
+#define GPIO_PIN15_INT_ENA_M  (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S)
+#define GPIO_PIN15_INT_ENA_V  0x0000001FU
+#define GPIO_PIN15_INT_ENA_S  13
+
+/** GPIO_PIN16_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4)
+/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN16_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_M  (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S)
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S)
+#define GPIO_PIN16_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN16_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_M  (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S)
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN16_INT_TYPE    0x00000007U
+#define GPIO_PIN16_INT_TYPE_M  (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S)
+#define GPIO_PIN16_INT_TYPE_V  0x00000007U
+#define GPIO_PIN16_INT_TYPE_S  7
+/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S)
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN16_CONFIG    0x00000003U
+#define GPIO_PIN16_CONFIG_M  (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S)
+#define GPIO_PIN16_CONFIG_V  0x00000003U
+#define GPIO_PIN16_CONFIG_S  11
+/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN16_INT_ENA    0x0000001FU
+#define GPIO_PIN16_INT_ENA_M  (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S)
+#define GPIO_PIN16_INT_ENA_V  0x0000001FU
+#define GPIO_PIN16_INT_ENA_S  13
+
+/** GPIO_PIN17_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8)
+/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN17_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_M  (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S)
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S)
+#define GPIO_PIN17_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN17_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_M  (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S)
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN17_INT_TYPE    0x00000007U
+#define GPIO_PIN17_INT_TYPE_M  (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S)
+#define GPIO_PIN17_INT_TYPE_V  0x00000007U
+#define GPIO_PIN17_INT_TYPE_S  7
+/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S)
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN17_CONFIG    0x00000003U
+#define GPIO_PIN17_CONFIG_M  (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S)
+#define GPIO_PIN17_CONFIG_V  0x00000003U
+#define GPIO_PIN17_CONFIG_S  11
+/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN17_INT_ENA    0x0000001FU
+#define GPIO_PIN17_INT_ENA_M  (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S)
+#define GPIO_PIN17_INT_ENA_V  0x0000001FU
+#define GPIO_PIN17_INT_ENA_S  13
+
+/** GPIO_PIN18_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc)
+/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN18_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_M  (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S)
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S)
+#define GPIO_PIN18_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN18_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_M  (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S)
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN18_INT_TYPE    0x00000007U
+#define GPIO_PIN18_INT_TYPE_M  (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S)
+#define GPIO_PIN18_INT_TYPE_V  0x00000007U
+#define GPIO_PIN18_INT_TYPE_S  7
+/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S)
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN18_CONFIG    0x00000003U
+#define GPIO_PIN18_CONFIG_M  (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S)
+#define GPIO_PIN18_CONFIG_V  0x00000003U
+#define GPIO_PIN18_CONFIG_S  11
+/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN18_INT_ENA    0x0000001FU
+#define GPIO_PIN18_INT_ENA_M  (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S)
+#define GPIO_PIN18_INT_ENA_V  0x0000001FU
+#define GPIO_PIN18_INT_ENA_S  13
+
+/** GPIO_PIN19_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0)
+/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN19_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_M  (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S)
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S)
+#define GPIO_PIN19_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN19_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_M  (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S)
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN19_INT_TYPE    0x00000007U
+#define GPIO_PIN19_INT_TYPE_M  (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S)
+#define GPIO_PIN19_INT_TYPE_V  0x00000007U
+#define GPIO_PIN19_INT_TYPE_S  7
+/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S)
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN19_CONFIG    0x00000003U
+#define GPIO_PIN19_CONFIG_M  (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S)
+#define GPIO_PIN19_CONFIG_V  0x00000003U
+#define GPIO_PIN19_CONFIG_S  11
+/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN19_INT_ENA    0x0000001FU
+#define GPIO_PIN19_INT_ENA_M  (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S)
+#define GPIO_PIN19_INT_ENA_V  0x0000001FU
+#define GPIO_PIN19_INT_ENA_S  13
+
+/** GPIO_PIN20_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4)
+/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN20_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_M  (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S)
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S)
+#define GPIO_PIN20_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN20_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_M  (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S)
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN20_INT_TYPE    0x00000007U
+#define GPIO_PIN20_INT_TYPE_M  (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S)
+#define GPIO_PIN20_INT_TYPE_V  0x00000007U
+#define GPIO_PIN20_INT_TYPE_S  7
+/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S)
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN20_CONFIG    0x00000003U
+#define GPIO_PIN20_CONFIG_M  (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S)
+#define GPIO_PIN20_CONFIG_V  0x00000003U
+#define GPIO_PIN20_CONFIG_S  11
+/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN20_INT_ENA    0x0000001FU
+#define GPIO_PIN20_INT_ENA_M  (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S)
+#define GPIO_PIN20_INT_ENA_V  0x0000001FU
+#define GPIO_PIN20_INT_ENA_S  13
+
+/** GPIO_PIN21_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8)
+/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN21_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_M  (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S)
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S)
+#define GPIO_PIN21_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN21_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_M  (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S)
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN21_INT_TYPE    0x00000007U
+#define GPIO_PIN21_INT_TYPE_M  (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S)
+#define GPIO_PIN21_INT_TYPE_V  0x00000007U
+#define GPIO_PIN21_INT_TYPE_S  7
+/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S)
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN21_CONFIG    0x00000003U
+#define GPIO_PIN21_CONFIG_M  (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S)
+#define GPIO_PIN21_CONFIG_V  0x00000003U
+#define GPIO_PIN21_CONFIG_S  11
+/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN21_INT_ENA    0x0000001FU
+#define GPIO_PIN21_INT_ENA_M  (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S)
+#define GPIO_PIN21_INT_ENA_V  0x0000001FU
+#define GPIO_PIN21_INT_ENA_S  13
+
+/** GPIO_PIN22_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc)
+/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN22_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_M  (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
+#define GPIO_PIN22_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN22_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_M  (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN22_INT_TYPE    0x00000007U
+#define GPIO_PIN22_INT_TYPE_M  (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
+#define GPIO_PIN22_INT_TYPE_V  0x00000007U
+#define GPIO_PIN22_INT_TYPE_S  7
+/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN22_CONFIG    0x00000003U
+#define GPIO_PIN22_CONFIG_M  (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S)
+#define GPIO_PIN22_CONFIG_V  0x00000003U
+#define GPIO_PIN22_CONFIG_S  11
+/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN22_INT_ENA    0x0000001FU
+#define GPIO_PIN22_INT_ENA_M  (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
+#define GPIO_PIN22_INT_ENA_V  0x0000001FU
+#define GPIO_PIN22_INT_ENA_S  13
+
+/** GPIO_PIN23_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0)
+/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN23_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_M  (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
+#define GPIO_PIN23_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN23_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_M  (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN23_INT_TYPE    0x00000007U
+#define GPIO_PIN23_INT_TYPE_M  (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
+#define GPIO_PIN23_INT_TYPE_V  0x00000007U
+#define GPIO_PIN23_INT_TYPE_S  7
+/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN23_CONFIG    0x00000003U
+#define GPIO_PIN23_CONFIG_M  (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S)
+#define GPIO_PIN23_CONFIG_V  0x00000003U
+#define GPIO_PIN23_CONFIG_S  11
+/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN23_INT_ENA    0x0000001FU
+#define GPIO_PIN23_INT_ENA_M  (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
+#define GPIO_PIN23_INT_ENA_V  0x0000001FU
+#define GPIO_PIN23_INT_ENA_S  13
+
+/** GPIO_PIN24_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4)
+/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN24_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_M  (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
+#define GPIO_PIN24_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN24_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_M  (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN24_INT_TYPE    0x00000007U
+#define GPIO_PIN24_INT_TYPE_M  (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
+#define GPIO_PIN24_INT_TYPE_V  0x00000007U
+#define GPIO_PIN24_INT_TYPE_S  7
+/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN24_CONFIG    0x00000003U
+#define GPIO_PIN24_CONFIG_M  (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S)
+#define GPIO_PIN24_CONFIG_V  0x00000003U
+#define GPIO_PIN24_CONFIG_S  11
+/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN24_INT_ENA    0x0000001FU
+#define GPIO_PIN24_INT_ENA_M  (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
+#define GPIO_PIN24_INT_ENA_V  0x0000001FU
+#define GPIO_PIN24_INT_ENA_S  13
+
+/** GPIO_PIN25_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8)
+/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN25_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN25_SYNC2_BYPASS_M  (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S)
+#define GPIO_PIN25_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN25_SYNC2_BYPASS_S  0
+/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN25_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M  (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S)
+#define GPIO_PIN25_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN25_PAD_DRIVER_S  2
+/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN25_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN25_SYNC1_BYPASS_M  (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S)
+#define GPIO_PIN25_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN25_SYNC1_BYPASS_S  3
+/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN25_INT_TYPE    0x00000007U
+#define GPIO_PIN25_INT_TYPE_M  (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S)
+#define GPIO_PIN25_INT_TYPE_V  0x00000007U
+#define GPIO_PIN25_INT_TYPE_S  7
+/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN25_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M  (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S)
+#define GPIO_PIN25_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN25_WAKEUP_ENABLE_S  10
+/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN25_CONFIG    0x00000003U
+#define GPIO_PIN25_CONFIG_M  (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S)
+#define GPIO_PIN25_CONFIG_V  0x00000003U
+#define GPIO_PIN25_CONFIG_S  11
+/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN25_INT_ENA    0x0000001FU
+#define GPIO_PIN25_INT_ENA_M  (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S)
+#define GPIO_PIN25_INT_ENA_V  0x0000001FU
+#define GPIO_PIN25_INT_ENA_S  13
+
+/** GPIO_PIN26_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc)
+/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN26_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN26_SYNC2_BYPASS_M  (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S)
+#define GPIO_PIN26_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN26_SYNC2_BYPASS_S  0
+/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN26_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_M  (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S)
+#define GPIO_PIN26_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN26_PAD_DRIVER_S  2
+/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN26_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN26_SYNC1_BYPASS_M  (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S)
+#define GPIO_PIN26_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN26_SYNC1_BYPASS_S  3
+/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN26_INT_TYPE    0x00000007U
+#define GPIO_PIN26_INT_TYPE_M  (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S)
+#define GPIO_PIN26_INT_TYPE_V  0x00000007U
+#define GPIO_PIN26_INT_TYPE_S  7
+/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN26_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_M  (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S)
+#define GPIO_PIN26_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN26_WAKEUP_ENABLE_S  10
+/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN26_CONFIG    0x00000003U
+#define GPIO_PIN26_CONFIG_M  (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S)
+#define GPIO_PIN26_CONFIG_V  0x00000003U
+#define GPIO_PIN26_CONFIG_S  11
+/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN26_INT_ENA    0x0000001FU
+#define GPIO_PIN26_INT_ENA_M  (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S)
+#define GPIO_PIN26_INT_ENA_V  0x0000001FU
+#define GPIO_PIN26_INT_ENA_S  13
+
+/** GPIO_PIN27_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0)
+/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN27_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN27_SYNC2_BYPASS_M  (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S)
+#define GPIO_PIN27_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN27_SYNC2_BYPASS_S  0
+/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN27_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_M  (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S)
+#define GPIO_PIN27_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN27_PAD_DRIVER_S  2
+/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN27_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN27_SYNC1_BYPASS_M  (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S)
+#define GPIO_PIN27_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN27_SYNC1_BYPASS_S  3
+/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN27_INT_TYPE    0x00000007U
+#define GPIO_PIN27_INT_TYPE_M  (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S)
+#define GPIO_PIN27_INT_TYPE_V  0x00000007U
+#define GPIO_PIN27_INT_TYPE_S  7
+/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN27_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_M  (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S)
+#define GPIO_PIN27_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN27_WAKEUP_ENABLE_S  10
+/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN27_CONFIG    0x00000003U
+#define GPIO_PIN27_CONFIG_M  (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S)
+#define GPIO_PIN27_CONFIG_V  0x00000003U
+#define GPIO_PIN27_CONFIG_S  11
+/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN27_INT_ENA    0x0000001FU
+#define GPIO_PIN27_INT_ENA_M  (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S)
+#define GPIO_PIN27_INT_ENA_V  0x0000001FU
+#define GPIO_PIN27_INT_ENA_S  13
+
+/** GPIO_PIN28_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4)
+/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN28_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN28_SYNC2_BYPASS_M  (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S)
+#define GPIO_PIN28_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN28_SYNC2_BYPASS_S  0
+/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN28_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_M  (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S)
+#define GPIO_PIN28_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN28_PAD_DRIVER_S  2
+/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN28_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN28_SYNC1_BYPASS_M  (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S)
+#define GPIO_PIN28_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN28_SYNC1_BYPASS_S  3
+/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN28_INT_TYPE    0x00000007U
+#define GPIO_PIN28_INT_TYPE_M  (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S)
+#define GPIO_PIN28_INT_TYPE_V  0x00000007U
+#define GPIO_PIN28_INT_TYPE_S  7
+/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN28_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_M  (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S)
+#define GPIO_PIN28_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN28_WAKEUP_ENABLE_S  10
+/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN28_CONFIG    0x00000003U
+#define GPIO_PIN28_CONFIG_M  (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S)
+#define GPIO_PIN28_CONFIG_V  0x00000003U
+#define GPIO_PIN28_CONFIG_S  11
+/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN28_INT_ENA    0x0000001FU
+#define GPIO_PIN28_INT_ENA_M  (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S)
+#define GPIO_PIN28_INT_ENA_V  0x0000001FU
+#define GPIO_PIN28_INT_ENA_S  13
+
+/** GPIO_PIN29_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8)
+/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN29_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN29_SYNC2_BYPASS_M  (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S)
+#define GPIO_PIN29_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN29_SYNC2_BYPASS_S  0
+/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN29_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_M  (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S)
+#define GPIO_PIN29_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN29_PAD_DRIVER_S  2
+/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN29_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN29_SYNC1_BYPASS_M  (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S)
+#define GPIO_PIN29_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN29_SYNC1_BYPASS_S  3
+/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN29_INT_TYPE    0x00000007U
+#define GPIO_PIN29_INT_TYPE_M  (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S)
+#define GPIO_PIN29_INT_TYPE_V  0x00000007U
+#define GPIO_PIN29_INT_TYPE_S  7
+/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN29_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_M  (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S)
+#define GPIO_PIN29_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN29_WAKEUP_ENABLE_S  10
+/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN29_CONFIG    0x00000003U
+#define GPIO_PIN29_CONFIG_M  (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S)
+#define GPIO_PIN29_CONFIG_V  0x00000003U
+#define GPIO_PIN29_CONFIG_S  11
+/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN29_INT_ENA    0x0000001FU
+#define GPIO_PIN29_INT_ENA_M  (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S)
+#define GPIO_PIN29_INT_ENA_V  0x0000001FU
+#define GPIO_PIN29_INT_ENA_S  13
+
+/** GPIO_PIN30_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec)
+/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN30_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN30_SYNC2_BYPASS_M  (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S)
+#define GPIO_PIN30_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN30_SYNC2_BYPASS_S  0
+/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN30_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_M  (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S)
+#define GPIO_PIN30_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN30_PAD_DRIVER_S  2
+/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN30_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN30_SYNC1_BYPASS_M  (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S)
+#define GPIO_PIN30_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN30_SYNC1_BYPASS_S  3
+/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN30_INT_TYPE    0x00000007U
+#define GPIO_PIN30_INT_TYPE_M  (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S)
+#define GPIO_PIN30_INT_TYPE_V  0x00000007U
+#define GPIO_PIN30_INT_TYPE_S  7
+/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN30_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_M  (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S)
+#define GPIO_PIN30_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN30_WAKEUP_ENABLE_S  10
+/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN30_CONFIG    0x00000003U
+#define GPIO_PIN30_CONFIG_M  (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S)
+#define GPIO_PIN30_CONFIG_V  0x00000003U
+#define GPIO_PIN30_CONFIG_S  11
+/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN30_INT_ENA    0x0000001FU
+#define GPIO_PIN30_INT_ENA_M  (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S)
+#define GPIO_PIN30_INT_ENA_V  0x0000001FU
+#define GPIO_PIN30_INT_ENA_S  13
+
+/** GPIO_PIN31_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0)
+/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN31_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN31_SYNC2_BYPASS_M  (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S)
+#define GPIO_PIN31_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN31_SYNC2_BYPASS_S  0
+/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN31_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_M  (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S)
+#define GPIO_PIN31_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN31_PAD_DRIVER_S  2
+/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN31_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN31_SYNC1_BYPASS_M  (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S)
+#define GPIO_PIN31_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN31_SYNC1_BYPASS_S  3
+/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN31_INT_TYPE    0x00000007U
+#define GPIO_PIN31_INT_TYPE_M  (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S)
+#define GPIO_PIN31_INT_TYPE_V  0x00000007U
+#define GPIO_PIN31_INT_TYPE_S  7
+/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN31_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_M  (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S)
+#define GPIO_PIN31_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN31_WAKEUP_ENABLE_S  10
+/** GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN31_CONFIG    0x00000003U
+#define GPIO_PIN31_CONFIG_M  (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S)
+#define GPIO_PIN31_CONFIG_V  0x00000003U
+#define GPIO_PIN31_CONFIG_S  11
+/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN31_INT_ENA    0x0000001FU
+#define GPIO_PIN31_INT_ENA_M  (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S)
+#define GPIO_PIN31_INT_ENA_V  0x0000001FU
+#define GPIO_PIN31_INT_ENA_S  13
+
+/** GPIO_PIN32_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4)
+/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN32_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN32_SYNC2_BYPASS_M  (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S)
+#define GPIO_PIN32_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN32_SYNC2_BYPASS_S  0
+/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN32_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_M  (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S)
+#define GPIO_PIN32_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN32_PAD_DRIVER_S  2
+/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN32_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN32_SYNC1_BYPASS_M  (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S)
+#define GPIO_PIN32_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN32_SYNC1_BYPASS_S  3
+/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN32_INT_TYPE    0x00000007U
+#define GPIO_PIN32_INT_TYPE_M  (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S)
+#define GPIO_PIN32_INT_TYPE_V  0x00000007U
+#define GPIO_PIN32_INT_TYPE_S  7
+/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN32_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_M  (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S)
+#define GPIO_PIN32_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN32_WAKEUP_ENABLE_S  10
+/** GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN32_CONFIG    0x00000003U
+#define GPIO_PIN32_CONFIG_M  (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S)
+#define GPIO_PIN32_CONFIG_V  0x00000003U
+#define GPIO_PIN32_CONFIG_S  11
+/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN32_INT_ENA    0x0000001FU
+#define GPIO_PIN32_INT_ENA_M  (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S)
+#define GPIO_PIN32_INT_ENA_V  0x0000001FU
+#define GPIO_PIN32_INT_ENA_S  13
+
+/** GPIO_PIN33_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8)
+/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN33_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN33_SYNC2_BYPASS_M  (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S)
+#define GPIO_PIN33_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN33_SYNC2_BYPASS_S  0
+/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN33_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_M  (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S)
+#define GPIO_PIN33_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN33_PAD_DRIVER_S  2
+/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN33_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN33_SYNC1_BYPASS_M  (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S)
+#define GPIO_PIN33_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN33_SYNC1_BYPASS_S  3
+/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN33_INT_TYPE    0x00000007U
+#define GPIO_PIN33_INT_TYPE_M  (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S)
+#define GPIO_PIN33_INT_TYPE_V  0x00000007U
+#define GPIO_PIN33_INT_TYPE_S  7
+/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN33_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_M  (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S)
+#define GPIO_PIN33_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN33_WAKEUP_ENABLE_S  10
+/** GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN33_CONFIG    0x00000003U
+#define GPIO_PIN33_CONFIG_M  (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S)
+#define GPIO_PIN33_CONFIG_V  0x00000003U
+#define GPIO_PIN33_CONFIG_S  11
+/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN33_INT_ENA    0x0000001FU
+#define GPIO_PIN33_INT_ENA_M  (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S)
+#define GPIO_PIN33_INT_ENA_V  0x0000001FU
+#define GPIO_PIN33_INT_ENA_S  13
+
+/** GPIO_PIN34_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc)
+/** GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN34_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN34_SYNC2_BYPASS_M  (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S)
+#define GPIO_PIN34_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN34_SYNC2_BYPASS_S  0
+/** GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN34_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_M  (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S)
+#define GPIO_PIN34_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN34_PAD_DRIVER_S  2
+/** GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN34_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN34_SYNC1_BYPASS_M  (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S)
+#define GPIO_PIN34_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN34_SYNC1_BYPASS_S  3
+/** GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN34_INT_TYPE    0x00000007U
+#define GPIO_PIN34_INT_TYPE_M  (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S)
+#define GPIO_PIN34_INT_TYPE_V  0x00000007U
+#define GPIO_PIN34_INT_TYPE_S  7
+/** GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN34_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_M  (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S)
+#define GPIO_PIN34_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN34_WAKEUP_ENABLE_S  10
+/** GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN34_CONFIG    0x00000003U
+#define GPIO_PIN34_CONFIG_M  (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S)
+#define GPIO_PIN34_CONFIG_V  0x00000003U
+#define GPIO_PIN34_CONFIG_S  11
+/** GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN34_INT_ENA    0x0000001FU
+#define GPIO_PIN34_INT_ENA_M  (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S)
+#define GPIO_PIN34_INT_ENA_V  0x0000001FU
+#define GPIO_PIN34_INT_ENA_S  13
+
+/** GPIO_PIN35_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100)
+/** GPIO_PIN35_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN35_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN35_SYNC2_BYPASS_M  (GPIO_PIN35_SYNC2_BYPASS_V << GPIO_PIN35_SYNC2_BYPASS_S)
+#define GPIO_PIN35_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN35_SYNC2_BYPASS_S  0
+/** GPIO_PIN35_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN35_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_M  (GPIO_PIN35_PAD_DRIVER_V << GPIO_PIN35_PAD_DRIVER_S)
+#define GPIO_PIN35_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN35_PAD_DRIVER_S  2
+/** GPIO_PIN35_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN35_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN35_SYNC1_BYPASS_M  (GPIO_PIN35_SYNC1_BYPASS_V << GPIO_PIN35_SYNC1_BYPASS_S)
+#define GPIO_PIN35_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN35_SYNC1_BYPASS_S  3
+/** GPIO_PIN35_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN35_INT_TYPE    0x00000007U
+#define GPIO_PIN35_INT_TYPE_M  (GPIO_PIN35_INT_TYPE_V << GPIO_PIN35_INT_TYPE_S)
+#define GPIO_PIN35_INT_TYPE_V  0x00000007U
+#define GPIO_PIN35_INT_TYPE_S  7
+/** GPIO_PIN35_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN35_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_M  (GPIO_PIN35_WAKEUP_ENABLE_V << GPIO_PIN35_WAKEUP_ENABLE_S)
+#define GPIO_PIN35_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN35_WAKEUP_ENABLE_S  10
+/** GPIO_PIN35_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN35_CONFIG    0x00000003U
+#define GPIO_PIN35_CONFIG_M  (GPIO_PIN35_CONFIG_V << GPIO_PIN35_CONFIG_S)
+#define GPIO_PIN35_CONFIG_V  0x00000003U
+#define GPIO_PIN35_CONFIG_S  11
+/** GPIO_PIN35_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN35_INT_ENA    0x0000001FU
+#define GPIO_PIN35_INT_ENA_M  (GPIO_PIN35_INT_ENA_V << GPIO_PIN35_INT_ENA_S)
+#define GPIO_PIN35_INT_ENA_V  0x0000001FU
+#define GPIO_PIN35_INT_ENA_S  13
+
+/** GPIO_PIN36_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104)
+/** GPIO_PIN36_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN36_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN36_SYNC2_BYPASS_M  (GPIO_PIN36_SYNC2_BYPASS_V << GPIO_PIN36_SYNC2_BYPASS_S)
+#define GPIO_PIN36_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN36_SYNC2_BYPASS_S  0
+/** GPIO_PIN36_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN36_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_M  (GPIO_PIN36_PAD_DRIVER_V << GPIO_PIN36_PAD_DRIVER_S)
+#define GPIO_PIN36_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN36_PAD_DRIVER_S  2
+/** GPIO_PIN36_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN36_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN36_SYNC1_BYPASS_M  (GPIO_PIN36_SYNC1_BYPASS_V << GPIO_PIN36_SYNC1_BYPASS_S)
+#define GPIO_PIN36_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN36_SYNC1_BYPASS_S  3
+/** GPIO_PIN36_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN36_INT_TYPE    0x00000007U
+#define GPIO_PIN36_INT_TYPE_M  (GPIO_PIN36_INT_TYPE_V << GPIO_PIN36_INT_TYPE_S)
+#define GPIO_PIN36_INT_TYPE_V  0x00000007U
+#define GPIO_PIN36_INT_TYPE_S  7
+/** GPIO_PIN36_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN36_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_M  (GPIO_PIN36_WAKEUP_ENABLE_V << GPIO_PIN36_WAKEUP_ENABLE_S)
+#define GPIO_PIN36_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN36_WAKEUP_ENABLE_S  10
+/** GPIO_PIN36_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN36_CONFIG    0x00000003U
+#define GPIO_PIN36_CONFIG_M  (GPIO_PIN36_CONFIG_V << GPIO_PIN36_CONFIG_S)
+#define GPIO_PIN36_CONFIG_V  0x00000003U
+#define GPIO_PIN36_CONFIG_S  11
+/** GPIO_PIN36_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN36_INT_ENA    0x0000001FU
+#define GPIO_PIN36_INT_ENA_M  (GPIO_PIN36_INT_ENA_V << GPIO_PIN36_INT_ENA_S)
+#define GPIO_PIN36_INT_ENA_V  0x0000001FU
+#define GPIO_PIN36_INT_ENA_S  13
+
+/** GPIO_PIN37_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108)
+/** GPIO_PIN37_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN37_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN37_SYNC2_BYPASS_M  (GPIO_PIN37_SYNC2_BYPASS_V << GPIO_PIN37_SYNC2_BYPASS_S)
+#define GPIO_PIN37_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN37_SYNC2_BYPASS_S  0
+/** GPIO_PIN37_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN37_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_M  (GPIO_PIN37_PAD_DRIVER_V << GPIO_PIN37_PAD_DRIVER_S)
+#define GPIO_PIN37_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN37_PAD_DRIVER_S  2
+/** GPIO_PIN37_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN37_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN37_SYNC1_BYPASS_M  (GPIO_PIN37_SYNC1_BYPASS_V << GPIO_PIN37_SYNC1_BYPASS_S)
+#define GPIO_PIN37_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN37_SYNC1_BYPASS_S  3
+/** GPIO_PIN37_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN37_INT_TYPE    0x00000007U
+#define GPIO_PIN37_INT_TYPE_M  (GPIO_PIN37_INT_TYPE_V << GPIO_PIN37_INT_TYPE_S)
+#define GPIO_PIN37_INT_TYPE_V  0x00000007U
+#define GPIO_PIN37_INT_TYPE_S  7
+/** GPIO_PIN37_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN37_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_M  (GPIO_PIN37_WAKEUP_ENABLE_V << GPIO_PIN37_WAKEUP_ENABLE_S)
+#define GPIO_PIN37_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN37_WAKEUP_ENABLE_S  10
+/** GPIO_PIN37_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN37_CONFIG    0x00000003U
+#define GPIO_PIN37_CONFIG_M  (GPIO_PIN37_CONFIG_V << GPIO_PIN37_CONFIG_S)
+#define GPIO_PIN37_CONFIG_V  0x00000003U
+#define GPIO_PIN37_CONFIG_S  11
+/** GPIO_PIN37_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN37_INT_ENA    0x0000001FU
+#define GPIO_PIN37_INT_ENA_M  (GPIO_PIN37_INT_ENA_V << GPIO_PIN37_INT_ENA_S)
+#define GPIO_PIN37_INT_ENA_V  0x0000001FU
+#define GPIO_PIN37_INT_ENA_S  13
+
+/** GPIO_PIN38_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10c)
+/** GPIO_PIN38_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN38_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN38_SYNC2_BYPASS_M  (GPIO_PIN38_SYNC2_BYPASS_V << GPIO_PIN38_SYNC2_BYPASS_S)
+#define GPIO_PIN38_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN38_SYNC2_BYPASS_S  0
+/** GPIO_PIN38_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN38_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_M  (GPIO_PIN38_PAD_DRIVER_V << GPIO_PIN38_PAD_DRIVER_S)
+#define GPIO_PIN38_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN38_PAD_DRIVER_S  2
+/** GPIO_PIN38_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN38_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN38_SYNC1_BYPASS_M  (GPIO_PIN38_SYNC1_BYPASS_V << GPIO_PIN38_SYNC1_BYPASS_S)
+#define GPIO_PIN38_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN38_SYNC1_BYPASS_S  3
+/** GPIO_PIN38_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN38_INT_TYPE    0x00000007U
+#define GPIO_PIN38_INT_TYPE_M  (GPIO_PIN38_INT_TYPE_V << GPIO_PIN38_INT_TYPE_S)
+#define GPIO_PIN38_INT_TYPE_V  0x00000007U
+#define GPIO_PIN38_INT_TYPE_S  7
+/** GPIO_PIN38_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN38_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_M  (GPIO_PIN38_WAKEUP_ENABLE_V << GPIO_PIN38_WAKEUP_ENABLE_S)
+#define GPIO_PIN38_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN38_WAKEUP_ENABLE_S  10
+/** GPIO_PIN38_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN38_CONFIG    0x00000003U
+#define GPIO_PIN38_CONFIG_M  (GPIO_PIN38_CONFIG_V << GPIO_PIN38_CONFIG_S)
+#define GPIO_PIN38_CONFIG_V  0x00000003U
+#define GPIO_PIN38_CONFIG_S  11
+/** GPIO_PIN38_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN38_INT_ENA    0x0000001FU
+#define GPIO_PIN38_INT_ENA_M  (GPIO_PIN38_INT_ENA_V << GPIO_PIN38_INT_ENA_S)
+#define GPIO_PIN38_INT_ENA_V  0x0000001FU
+#define GPIO_PIN38_INT_ENA_S  13
+
+/** GPIO_PIN39_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110)
+/** GPIO_PIN39_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN39_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN39_SYNC2_BYPASS_M  (GPIO_PIN39_SYNC2_BYPASS_V << GPIO_PIN39_SYNC2_BYPASS_S)
+#define GPIO_PIN39_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN39_SYNC2_BYPASS_S  0
+/** GPIO_PIN39_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN39_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_M  (GPIO_PIN39_PAD_DRIVER_V << GPIO_PIN39_PAD_DRIVER_S)
+#define GPIO_PIN39_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN39_PAD_DRIVER_S  2
+/** GPIO_PIN39_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN39_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN39_SYNC1_BYPASS_M  (GPIO_PIN39_SYNC1_BYPASS_V << GPIO_PIN39_SYNC1_BYPASS_S)
+#define GPIO_PIN39_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN39_SYNC1_BYPASS_S  3
+/** GPIO_PIN39_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN39_INT_TYPE    0x00000007U
+#define GPIO_PIN39_INT_TYPE_M  (GPIO_PIN39_INT_TYPE_V << GPIO_PIN39_INT_TYPE_S)
+#define GPIO_PIN39_INT_TYPE_V  0x00000007U
+#define GPIO_PIN39_INT_TYPE_S  7
+/** GPIO_PIN39_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN39_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_M  (GPIO_PIN39_WAKEUP_ENABLE_V << GPIO_PIN39_WAKEUP_ENABLE_S)
+#define GPIO_PIN39_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN39_WAKEUP_ENABLE_S  10
+/** GPIO_PIN39_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN39_CONFIG    0x00000003U
+#define GPIO_PIN39_CONFIG_M  (GPIO_PIN39_CONFIG_V << GPIO_PIN39_CONFIG_S)
+#define GPIO_PIN39_CONFIG_V  0x00000003U
+#define GPIO_PIN39_CONFIG_S  11
+/** GPIO_PIN39_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN39_INT_ENA    0x0000001FU
+#define GPIO_PIN39_INT_ENA_M  (GPIO_PIN39_INT_ENA_V << GPIO_PIN39_INT_ENA_S)
+#define GPIO_PIN39_INT_ENA_V  0x0000001FU
+#define GPIO_PIN39_INT_ENA_S  13
+
+/** GPIO_PIN40_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114)
+/** GPIO_PIN40_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN40_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN40_SYNC2_BYPASS_M  (GPIO_PIN40_SYNC2_BYPASS_V << GPIO_PIN40_SYNC2_BYPASS_S)
+#define GPIO_PIN40_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN40_SYNC2_BYPASS_S  0
+/** GPIO_PIN40_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN40_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN40_PAD_DRIVER_M  (GPIO_PIN40_PAD_DRIVER_V << GPIO_PIN40_PAD_DRIVER_S)
+#define GPIO_PIN40_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN40_PAD_DRIVER_S  2
+/** GPIO_PIN40_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN40_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN40_SYNC1_BYPASS_M  (GPIO_PIN40_SYNC1_BYPASS_V << GPIO_PIN40_SYNC1_BYPASS_S)
+#define GPIO_PIN40_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN40_SYNC1_BYPASS_S  3
+/** GPIO_PIN40_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN40_INT_TYPE    0x00000007U
+#define GPIO_PIN40_INT_TYPE_M  (GPIO_PIN40_INT_TYPE_V << GPIO_PIN40_INT_TYPE_S)
+#define GPIO_PIN40_INT_TYPE_V  0x00000007U
+#define GPIO_PIN40_INT_TYPE_S  7
+/** GPIO_PIN40_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN40_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN40_WAKEUP_ENABLE_M  (GPIO_PIN40_WAKEUP_ENABLE_V << GPIO_PIN40_WAKEUP_ENABLE_S)
+#define GPIO_PIN40_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN40_WAKEUP_ENABLE_S  10
+/** GPIO_PIN40_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN40_CONFIG    0x00000003U
+#define GPIO_PIN40_CONFIG_M  (GPIO_PIN40_CONFIG_V << GPIO_PIN40_CONFIG_S)
+#define GPIO_PIN40_CONFIG_V  0x00000003U
+#define GPIO_PIN40_CONFIG_S  11
+/** GPIO_PIN40_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN40_INT_ENA    0x0000001FU
+#define GPIO_PIN40_INT_ENA_M  (GPIO_PIN40_INT_ENA_V << GPIO_PIN40_INT_ENA_S)
+#define GPIO_PIN40_INT_ENA_V  0x0000001FU
+#define GPIO_PIN40_INT_ENA_S  13
+
+/** GPIO_PIN41_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118)
+/** GPIO_PIN41_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN41_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN41_SYNC2_BYPASS_M  (GPIO_PIN41_SYNC2_BYPASS_V << GPIO_PIN41_SYNC2_BYPASS_S)
+#define GPIO_PIN41_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN41_SYNC2_BYPASS_S  0
+/** GPIO_PIN41_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN41_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN41_PAD_DRIVER_M  (GPIO_PIN41_PAD_DRIVER_V << GPIO_PIN41_PAD_DRIVER_S)
+#define GPIO_PIN41_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN41_PAD_DRIVER_S  2
+/** GPIO_PIN41_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN41_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN41_SYNC1_BYPASS_M  (GPIO_PIN41_SYNC1_BYPASS_V << GPIO_PIN41_SYNC1_BYPASS_S)
+#define GPIO_PIN41_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN41_SYNC1_BYPASS_S  3
+/** GPIO_PIN41_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN41_INT_TYPE    0x00000007U
+#define GPIO_PIN41_INT_TYPE_M  (GPIO_PIN41_INT_TYPE_V << GPIO_PIN41_INT_TYPE_S)
+#define GPIO_PIN41_INT_TYPE_V  0x00000007U
+#define GPIO_PIN41_INT_TYPE_S  7
+/** GPIO_PIN41_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN41_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN41_WAKEUP_ENABLE_M  (GPIO_PIN41_WAKEUP_ENABLE_V << GPIO_PIN41_WAKEUP_ENABLE_S)
+#define GPIO_PIN41_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN41_WAKEUP_ENABLE_S  10
+/** GPIO_PIN41_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN41_CONFIG    0x00000003U
+#define GPIO_PIN41_CONFIG_M  (GPIO_PIN41_CONFIG_V << GPIO_PIN41_CONFIG_S)
+#define GPIO_PIN41_CONFIG_V  0x00000003U
+#define GPIO_PIN41_CONFIG_S  11
+/** GPIO_PIN41_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN41_INT_ENA    0x0000001FU
+#define GPIO_PIN41_INT_ENA_M  (GPIO_PIN41_INT_ENA_V << GPIO_PIN41_INT_ENA_S)
+#define GPIO_PIN41_INT_ENA_V  0x0000001FU
+#define GPIO_PIN41_INT_ENA_S  13
+
+/** GPIO_PIN42_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11c)
+/** GPIO_PIN42_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN42_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN42_SYNC2_BYPASS_M  (GPIO_PIN42_SYNC2_BYPASS_V << GPIO_PIN42_SYNC2_BYPASS_S)
+#define GPIO_PIN42_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN42_SYNC2_BYPASS_S  0
+/** GPIO_PIN42_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN42_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN42_PAD_DRIVER_M  (GPIO_PIN42_PAD_DRIVER_V << GPIO_PIN42_PAD_DRIVER_S)
+#define GPIO_PIN42_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN42_PAD_DRIVER_S  2
+/** GPIO_PIN42_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN42_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN42_SYNC1_BYPASS_M  (GPIO_PIN42_SYNC1_BYPASS_V << GPIO_PIN42_SYNC1_BYPASS_S)
+#define GPIO_PIN42_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN42_SYNC1_BYPASS_S  3
+/** GPIO_PIN42_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN42_INT_TYPE    0x00000007U
+#define GPIO_PIN42_INT_TYPE_M  (GPIO_PIN42_INT_TYPE_V << GPIO_PIN42_INT_TYPE_S)
+#define GPIO_PIN42_INT_TYPE_V  0x00000007U
+#define GPIO_PIN42_INT_TYPE_S  7
+/** GPIO_PIN42_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN42_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN42_WAKEUP_ENABLE_M  (GPIO_PIN42_WAKEUP_ENABLE_V << GPIO_PIN42_WAKEUP_ENABLE_S)
+#define GPIO_PIN42_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN42_WAKEUP_ENABLE_S  10
+/** GPIO_PIN42_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN42_CONFIG    0x00000003U
+#define GPIO_PIN42_CONFIG_M  (GPIO_PIN42_CONFIG_V << GPIO_PIN42_CONFIG_S)
+#define GPIO_PIN42_CONFIG_V  0x00000003U
+#define GPIO_PIN42_CONFIG_S  11
+/** GPIO_PIN42_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN42_INT_ENA    0x0000001FU
+#define GPIO_PIN42_INT_ENA_M  (GPIO_PIN42_INT_ENA_V << GPIO_PIN42_INT_ENA_S)
+#define GPIO_PIN42_INT_ENA_V  0x0000001FU
+#define GPIO_PIN42_INT_ENA_S  13
+
+/** GPIO_PIN43_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120)
+/** GPIO_PIN43_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN43_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN43_SYNC2_BYPASS_M  (GPIO_PIN43_SYNC2_BYPASS_V << GPIO_PIN43_SYNC2_BYPASS_S)
+#define GPIO_PIN43_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN43_SYNC2_BYPASS_S  0
+/** GPIO_PIN43_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN43_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN43_PAD_DRIVER_M  (GPIO_PIN43_PAD_DRIVER_V << GPIO_PIN43_PAD_DRIVER_S)
+#define GPIO_PIN43_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN43_PAD_DRIVER_S  2
+/** GPIO_PIN43_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN43_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN43_SYNC1_BYPASS_M  (GPIO_PIN43_SYNC1_BYPASS_V << GPIO_PIN43_SYNC1_BYPASS_S)
+#define GPIO_PIN43_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN43_SYNC1_BYPASS_S  3
+/** GPIO_PIN43_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN43_INT_TYPE    0x00000007U
+#define GPIO_PIN43_INT_TYPE_M  (GPIO_PIN43_INT_TYPE_V << GPIO_PIN43_INT_TYPE_S)
+#define GPIO_PIN43_INT_TYPE_V  0x00000007U
+#define GPIO_PIN43_INT_TYPE_S  7
+/** GPIO_PIN43_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN43_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN43_WAKEUP_ENABLE_M  (GPIO_PIN43_WAKEUP_ENABLE_V << GPIO_PIN43_WAKEUP_ENABLE_S)
+#define GPIO_PIN43_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN43_WAKEUP_ENABLE_S  10
+/** GPIO_PIN43_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN43_CONFIG    0x00000003U
+#define GPIO_PIN43_CONFIG_M  (GPIO_PIN43_CONFIG_V << GPIO_PIN43_CONFIG_S)
+#define GPIO_PIN43_CONFIG_V  0x00000003U
+#define GPIO_PIN43_CONFIG_S  11
+/** GPIO_PIN43_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN43_INT_ENA    0x0000001FU
+#define GPIO_PIN43_INT_ENA_M  (GPIO_PIN43_INT_ENA_V << GPIO_PIN43_INT_ENA_S)
+#define GPIO_PIN43_INT_ENA_V  0x0000001FU
+#define GPIO_PIN43_INT_ENA_S  13
+
+/** GPIO_PIN44_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124)
+/** GPIO_PIN44_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN44_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN44_SYNC2_BYPASS_M  (GPIO_PIN44_SYNC2_BYPASS_V << GPIO_PIN44_SYNC2_BYPASS_S)
+#define GPIO_PIN44_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN44_SYNC2_BYPASS_S  0
+/** GPIO_PIN44_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN44_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN44_PAD_DRIVER_M  (GPIO_PIN44_PAD_DRIVER_V << GPIO_PIN44_PAD_DRIVER_S)
+#define GPIO_PIN44_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN44_PAD_DRIVER_S  2
+/** GPIO_PIN44_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN44_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN44_SYNC1_BYPASS_M  (GPIO_PIN44_SYNC1_BYPASS_V << GPIO_PIN44_SYNC1_BYPASS_S)
+#define GPIO_PIN44_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN44_SYNC1_BYPASS_S  3
+/** GPIO_PIN44_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN44_INT_TYPE    0x00000007U
+#define GPIO_PIN44_INT_TYPE_M  (GPIO_PIN44_INT_TYPE_V << GPIO_PIN44_INT_TYPE_S)
+#define GPIO_PIN44_INT_TYPE_V  0x00000007U
+#define GPIO_PIN44_INT_TYPE_S  7
+/** GPIO_PIN44_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN44_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN44_WAKEUP_ENABLE_M  (GPIO_PIN44_WAKEUP_ENABLE_V << GPIO_PIN44_WAKEUP_ENABLE_S)
+#define GPIO_PIN44_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN44_WAKEUP_ENABLE_S  10
+/** GPIO_PIN44_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN44_CONFIG    0x00000003U
+#define GPIO_PIN44_CONFIG_M  (GPIO_PIN44_CONFIG_V << GPIO_PIN44_CONFIG_S)
+#define GPIO_PIN44_CONFIG_V  0x00000003U
+#define GPIO_PIN44_CONFIG_S  11
+/** GPIO_PIN44_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN44_INT_ENA    0x0000001FU
+#define GPIO_PIN44_INT_ENA_M  (GPIO_PIN44_INT_ENA_V << GPIO_PIN44_INT_ENA_S)
+#define GPIO_PIN44_INT_ENA_V  0x0000001FU
+#define GPIO_PIN44_INT_ENA_S  13
+
+/** GPIO_PIN45_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN45_REG (DR_REG_GPIO_BASE + 0x128)
+/** GPIO_PIN45_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN45_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN45_SYNC2_BYPASS_M  (GPIO_PIN45_SYNC2_BYPASS_V << GPIO_PIN45_SYNC2_BYPASS_S)
+#define GPIO_PIN45_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN45_SYNC2_BYPASS_S  0
+/** GPIO_PIN45_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN45_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN45_PAD_DRIVER_M  (GPIO_PIN45_PAD_DRIVER_V << GPIO_PIN45_PAD_DRIVER_S)
+#define GPIO_PIN45_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN45_PAD_DRIVER_S  2
+/** GPIO_PIN45_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN45_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN45_SYNC1_BYPASS_M  (GPIO_PIN45_SYNC1_BYPASS_V << GPIO_PIN45_SYNC1_BYPASS_S)
+#define GPIO_PIN45_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN45_SYNC1_BYPASS_S  3
+/** GPIO_PIN45_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN45_INT_TYPE    0x00000007U
+#define GPIO_PIN45_INT_TYPE_M  (GPIO_PIN45_INT_TYPE_V << GPIO_PIN45_INT_TYPE_S)
+#define GPIO_PIN45_INT_TYPE_V  0x00000007U
+#define GPIO_PIN45_INT_TYPE_S  7
+/** GPIO_PIN45_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN45_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN45_WAKEUP_ENABLE_M  (GPIO_PIN45_WAKEUP_ENABLE_V << GPIO_PIN45_WAKEUP_ENABLE_S)
+#define GPIO_PIN45_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN45_WAKEUP_ENABLE_S  10
+/** GPIO_PIN45_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN45_CONFIG    0x00000003U
+#define GPIO_PIN45_CONFIG_M  (GPIO_PIN45_CONFIG_V << GPIO_PIN45_CONFIG_S)
+#define GPIO_PIN45_CONFIG_V  0x00000003U
+#define GPIO_PIN45_CONFIG_S  11
+/** GPIO_PIN45_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN45_INT_ENA    0x0000001FU
+#define GPIO_PIN45_INT_ENA_M  (GPIO_PIN45_INT_ENA_V << GPIO_PIN45_INT_ENA_S)
+#define GPIO_PIN45_INT_ENA_V  0x0000001FU
+#define GPIO_PIN45_INT_ENA_S  13
+
+/** GPIO_PIN46_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN46_REG (DR_REG_GPIO_BASE + 0x12c)
+/** GPIO_PIN46_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN46_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN46_SYNC2_BYPASS_M  (GPIO_PIN46_SYNC2_BYPASS_V << GPIO_PIN46_SYNC2_BYPASS_S)
+#define GPIO_PIN46_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN46_SYNC2_BYPASS_S  0
+/** GPIO_PIN46_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN46_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN46_PAD_DRIVER_M  (GPIO_PIN46_PAD_DRIVER_V << GPIO_PIN46_PAD_DRIVER_S)
+#define GPIO_PIN46_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN46_PAD_DRIVER_S  2
+/** GPIO_PIN46_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN46_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN46_SYNC1_BYPASS_M  (GPIO_PIN46_SYNC1_BYPASS_V << GPIO_PIN46_SYNC1_BYPASS_S)
+#define GPIO_PIN46_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN46_SYNC1_BYPASS_S  3
+/** GPIO_PIN46_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN46_INT_TYPE    0x00000007U
+#define GPIO_PIN46_INT_TYPE_M  (GPIO_PIN46_INT_TYPE_V << GPIO_PIN46_INT_TYPE_S)
+#define GPIO_PIN46_INT_TYPE_V  0x00000007U
+#define GPIO_PIN46_INT_TYPE_S  7
+/** GPIO_PIN46_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN46_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN46_WAKEUP_ENABLE_M  (GPIO_PIN46_WAKEUP_ENABLE_V << GPIO_PIN46_WAKEUP_ENABLE_S)
+#define GPIO_PIN46_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN46_WAKEUP_ENABLE_S  10
+/** GPIO_PIN46_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN46_CONFIG    0x00000003U
+#define GPIO_PIN46_CONFIG_M  (GPIO_PIN46_CONFIG_V << GPIO_PIN46_CONFIG_S)
+#define GPIO_PIN46_CONFIG_V  0x00000003U
+#define GPIO_PIN46_CONFIG_S  11
+/** GPIO_PIN46_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN46_INT_ENA    0x0000001FU
+#define GPIO_PIN46_INT_ENA_M  (GPIO_PIN46_INT_ENA_V << GPIO_PIN46_INT_ENA_S)
+#define GPIO_PIN46_INT_ENA_V  0x0000001FU
+#define GPIO_PIN46_INT_ENA_S  13
+
+/** GPIO_PIN47_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN47_REG (DR_REG_GPIO_BASE + 0x130)
+/** GPIO_PIN47_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN47_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN47_SYNC2_BYPASS_M  (GPIO_PIN47_SYNC2_BYPASS_V << GPIO_PIN47_SYNC2_BYPASS_S)
+#define GPIO_PIN47_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN47_SYNC2_BYPASS_S  0
+/** GPIO_PIN47_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN47_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN47_PAD_DRIVER_M  (GPIO_PIN47_PAD_DRIVER_V << GPIO_PIN47_PAD_DRIVER_S)
+#define GPIO_PIN47_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN47_PAD_DRIVER_S  2
+/** GPIO_PIN47_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN47_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN47_SYNC1_BYPASS_M  (GPIO_PIN47_SYNC1_BYPASS_V << GPIO_PIN47_SYNC1_BYPASS_S)
+#define GPIO_PIN47_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN47_SYNC1_BYPASS_S  3
+/** GPIO_PIN47_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN47_INT_TYPE    0x00000007U
+#define GPIO_PIN47_INT_TYPE_M  (GPIO_PIN47_INT_TYPE_V << GPIO_PIN47_INT_TYPE_S)
+#define GPIO_PIN47_INT_TYPE_V  0x00000007U
+#define GPIO_PIN47_INT_TYPE_S  7
+/** GPIO_PIN47_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN47_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN47_WAKEUP_ENABLE_M  (GPIO_PIN47_WAKEUP_ENABLE_V << GPIO_PIN47_WAKEUP_ENABLE_S)
+#define GPIO_PIN47_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN47_WAKEUP_ENABLE_S  10
+/** GPIO_PIN47_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN47_CONFIG    0x00000003U
+#define GPIO_PIN47_CONFIG_M  (GPIO_PIN47_CONFIG_V << GPIO_PIN47_CONFIG_S)
+#define GPIO_PIN47_CONFIG_V  0x00000003U
+#define GPIO_PIN47_CONFIG_S  11
+/** GPIO_PIN47_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN47_INT_ENA    0x0000001FU
+#define GPIO_PIN47_INT_ENA_M  (GPIO_PIN47_INT_ENA_V << GPIO_PIN47_INT_ENA_S)
+#define GPIO_PIN47_INT_ENA_V  0x0000001FU
+#define GPIO_PIN47_INT_ENA_S  13
+
+/** GPIO_PIN48_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN48_REG (DR_REG_GPIO_BASE + 0x134)
+/** GPIO_PIN48_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN48_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN48_SYNC2_BYPASS_M  (GPIO_PIN48_SYNC2_BYPASS_V << GPIO_PIN48_SYNC2_BYPASS_S)
+#define GPIO_PIN48_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN48_SYNC2_BYPASS_S  0
+/** GPIO_PIN48_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN48_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN48_PAD_DRIVER_M  (GPIO_PIN48_PAD_DRIVER_V << GPIO_PIN48_PAD_DRIVER_S)
+#define GPIO_PIN48_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN48_PAD_DRIVER_S  2
+/** GPIO_PIN48_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN48_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN48_SYNC1_BYPASS_M  (GPIO_PIN48_SYNC1_BYPASS_V << GPIO_PIN48_SYNC1_BYPASS_S)
+#define GPIO_PIN48_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN48_SYNC1_BYPASS_S  3
+/** GPIO_PIN48_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN48_INT_TYPE    0x00000007U
+#define GPIO_PIN48_INT_TYPE_M  (GPIO_PIN48_INT_TYPE_V << GPIO_PIN48_INT_TYPE_S)
+#define GPIO_PIN48_INT_TYPE_V  0x00000007U
+#define GPIO_PIN48_INT_TYPE_S  7
+/** GPIO_PIN48_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN48_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN48_WAKEUP_ENABLE_M  (GPIO_PIN48_WAKEUP_ENABLE_V << GPIO_PIN48_WAKEUP_ENABLE_S)
+#define GPIO_PIN48_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN48_WAKEUP_ENABLE_S  10
+/** GPIO_PIN48_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN48_CONFIG    0x00000003U
+#define GPIO_PIN48_CONFIG_M  (GPIO_PIN48_CONFIG_V << GPIO_PIN48_CONFIG_S)
+#define GPIO_PIN48_CONFIG_V  0x00000003U
+#define GPIO_PIN48_CONFIG_S  11
+/** GPIO_PIN48_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN48_INT_ENA    0x0000001FU
+#define GPIO_PIN48_INT_ENA_M  (GPIO_PIN48_INT_ENA_V << GPIO_PIN48_INT_ENA_S)
+#define GPIO_PIN48_INT_ENA_V  0x0000001FU
+#define GPIO_PIN48_INT_ENA_S  13
+
+/** GPIO_PIN49_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN49_REG (DR_REG_GPIO_BASE + 0x138)
+/** GPIO_PIN49_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN49_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN49_SYNC2_BYPASS_M  (GPIO_PIN49_SYNC2_BYPASS_V << GPIO_PIN49_SYNC2_BYPASS_S)
+#define GPIO_PIN49_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN49_SYNC2_BYPASS_S  0
+/** GPIO_PIN49_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN49_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN49_PAD_DRIVER_M  (GPIO_PIN49_PAD_DRIVER_V << GPIO_PIN49_PAD_DRIVER_S)
+#define GPIO_PIN49_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN49_PAD_DRIVER_S  2
+/** GPIO_PIN49_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN49_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN49_SYNC1_BYPASS_M  (GPIO_PIN49_SYNC1_BYPASS_V << GPIO_PIN49_SYNC1_BYPASS_S)
+#define GPIO_PIN49_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN49_SYNC1_BYPASS_S  3
+/** GPIO_PIN49_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN49_INT_TYPE    0x00000007U
+#define GPIO_PIN49_INT_TYPE_M  (GPIO_PIN49_INT_TYPE_V << GPIO_PIN49_INT_TYPE_S)
+#define GPIO_PIN49_INT_TYPE_V  0x00000007U
+#define GPIO_PIN49_INT_TYPE_S  7
+/** GPIO_PIN49_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN49_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN49_WAKEUP_ENABLE_M  (GPIO_PIN49_WAKEUP_ENABLE_V << GPIO_PIN49_WAKEUP_ENABLE_S)
+#define GPIO_PIN49_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN49_WAKEUP_ENABLE_S  10
+/** GPIO_PIN49_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN49_CONFIG    0x00000003U
+#define GPIO_PIN49_CONFIG_M  (GPIO_PIN49_CONFIG_V << GPIO_PIN49_CONFIG_S)
+#define GPIO_PIN49_CONFIG_V  0x00000003U
+#define GPIO_PIN49_CONFIG_S  11
+/** GPIO_PIN49_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN49_INT_ENA    0x0000001FU
+#define GPIO_PIN49_INT_ENA_M  (GPIO_PIN49_INT_ENA_V << GPIO_PIN49_INT_ENA_S)
+#define GPIO_PIN49_INT_ENA_V  0x0000001FU
+#define GPIO_PIN49_INT_ENA_S  13
+
+/** GPIO_PIN50_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN50_REG (DR_REG_GPIO_BASE + 0x13c)
+/** GPIO_PIN50_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN50_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN50_SYNC2_BYPASS_M  (GPIO_PIN50_SYNC2_BYPASS_V << GPIO_PIN50_SYNC2_BYPASS_S)
+#define GPIO_PIN50_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN50_SYNC2_BYPASS_S  0
+/** GPIO_PIN50_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN50_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN50_PAD_DRIVER_M  (GPIO_PIN50_PAD_DRIVER_V << GPIO_PIN50_PAD_DRIVER_S)
+#define GPIO_PIN50_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN50_PAD_DRIVER_S  2
+/** GPIO_PIN50_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN50_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN50_SYNC1_BYPASS_M  (GPIO_PIN50_SYNC1_BYPASS_V << GPIO_PIN50_SYNC1_BYPASS_S)
+#define GPIO_PIN50_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN50_SYNC1_BYPASS_S  3
+/** GPIO_PIN50_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN50_INT_TYPE    0x00000007U
+#define GPIO_PIN50_INT_TYPE_M  (GPIO_PIN50_INT_TYPE_V << GPIO_PIN50_INT_TYPE_S)
+#define GPIO_PIN50_INT_TYPE_V  0x00000007U
+#define GPIO_PIN50_INT_TYPE_S  7
+/** GPIO_PIN50_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN50_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN50_WAKEUP_ENABLE_M  (GPIO_PIN50_WAKEUP_ENABLE_V << GPIO_PIN50_WAKEUP_ENABLE_S)
+#define GPIO_PIN50_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN50_WAKEUP_ENABLE_S  10
+/** GPIO_PIN50_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN50_CONFIG    0x00000003U
+#define GPIO_PIN50_CONFIG_M  (GPIO_PIN50_CONFIG_V << GPIO_PIN50_CONFIG_S)
+#define GPIO_PIN50_CONFIG_V  0x00000003U
+#define GPIO_PIN50_CONFIG_S  11
+/** GPIO_PIN50_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN50_INT_ENA    0x0000001FU
+#define GPIO_PIN50_INT_ENA_M  (GPIO_PIN50_INT_ENA_V << GPIO_PIN50_INT_ENA_S)
+#define GPIO_PIN50_INT_ENA_V  0x0000001FU
+#define GPIO_PIN50_INT_ENA_S  13
+
+/** GPIO_PIN51_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN51_REG (DR_REG_GPIO_BASE + 0x140)
+/** GPIO_PIN51_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN51_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN51_SYNC2_BYPASS_M  (GPIO_PIN51_SYNC2_BYPASS_V << GPIO_PIN51_SYNC2_BYPASS_S)
+#define GPIO_PIN51_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN51_SYNC2_BYPASS_S  0
+/** GPIO_PIN51_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN51_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN51_PAD_DRIVER_M  (GPIO_PIN51_PAD_DRIVER_V << GPIO_PIN51_PAD_DRIVER_S)
+#define GPIO_PIN51_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN51_PAD_DRIVER_S  2
+/** GPIO_PIN51_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN51_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN51_SYNC1_BYPASS_M  (GPIO_PIN51_SYNC1_BYPASS_V << GPIO_PIN51_SYNC1_BYPASS_S)
+#define GPIO_PIN51_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN51_SYNC1_BYPASS_S  3
+/** GPIO_PIN51_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN51_INT_TYPE    0x00000007U
+#define GPIO_PIN51_INT_TYPE_M  (GPIO_PIN51_INT_TYPE_V << GPIO_PIN51_INT_TYPE_S)
+#define GPIO_PIN51_INT_TYPE_V  0x00000007U
+#define GPIO_PIN51_INT_TYPE_S  7
+/** GPIO_PIN51_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN51_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN51_WAKEUP_ENABLE_M  (GPIO_PIN51_WAKEUP_ENABLE_V << GPIO_PIN51_WAKEUP_ENABLE_S)
+#define GPIO_PIN51_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN51_WAKEUP_ENABLE_S  10
+/** GPIO_PIN51_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN51_CONFIG    0x00000003U
+#define GPIO_PIN51_CONFIG_M  (GPIO_PIN51_CONFIG_V << GPIO_PIN51_CONFIG_S)
+#define GPIO_PIN51_CONFIG_V  0x00000003U
+#define GPIO_PIN51_CONFIG_S  11
+/** GPIO_PIN51_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN51_INT_ENA    0x0000001FU
+#define GPIO_PIN51_INT_ENA_M  (GPIO_PIN51_INT_ENA_V << GPIO_PIN51_INT_ENA_S)
+#define GPIO_PIN51_INT_ENA_V  0x0000001FU
+#define GPIO_PIN51_INT_ENA_S  13
+
+/** GPIO_PIN52_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN52_REG (DR_REG_GPIO_BASE + 0x144)
+/** GPIO_PIN52_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN52_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN52_SYNC2_BYPASS_M  (GPIO_PIN52_SYNC2_BYPASS_V << GPIO_PIN52_SYNC2_BYPASS_S)
+#define GPIO_PIN52_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN52_SYNC2_BYPASS_S  0
+/** GPIO_PIN52_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN52_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN52_PAD_DRIVER_M  (GPIO_PIN52_PAD_DRIVER_V << GPIO_PIN52_PAD_DRIVER_S)
+#define GPIO_PIN52_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN52_PAD_DRIVER_S  2
+/** GPIO_PIN52_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN52_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN52_SYNC1_BYPASS_M  (GPIO_PIN52_SYNC1_BYPASS_V << GPIO_PIN52_SYNC1_BYPASS_S)
+#define GPIO_PIN52_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN52_SYNC1_BYPASS_S  3
+/** GPIO_PIN52_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN52_INT_TYPE    0x00000007U
+#define GPIO_PIN52_INT_TYPE_M  (GPIO_PIN52_INT_TYPE_V << GPIO_PIN52_INT_TYPE_S)
+#define GPIO_PIN52_INT_TYPE_V  0x00000007U
+#define GPIO_PIN52_INT_TYPE_S  7
+/** GPIO_PIN52_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN52_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN52_WAKEUP_ENABLE_M  (GPIO_PIN52_WAKEUP_ENABLE_V << GPIO_PIN52_WAKEUP_ENABLE_S)
+#define GPIO_PIN52_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN52_WAKEUP_ENABLE_S  10
+/** GPIO_PIN52_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN52_CONFIG    0x00000003U
+#define GPIO_PIN52_CONFIG_M  (GPIO_PIN52_CONFIG_V << GPIO_PIN52_CONFIG_S)
+#define GPIO_PIN52_CONFIG_V  0x00000003U
+#define GPIO_PIN52_CONFIG_S  11
+/** GPIO_PIN52_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN52_INT_ENA    0x0000001FU
+#define GPIO_PIN52_INT_ENA_M  (GPIO_PIN52_INT_ENA_V << GPIO_PIN52_INT_ENA_S)
+#define GPIO_PIN52_INT_ENA_V  0x0000001FU
+#define GPIO_PIN52_INT_ENA_S  13
+
+/** GPIO_PIN53_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN53_REG (DR_REG_GPIO_BASE + 0x148)
+/** GPIO_PIN53_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN53_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN53_SYNC2_BYPASS_M  (GPIO_PIN53_SYNC2_BYPASS_V << GPIO_PIN53_SYNC2_BYPASS_S)
+#define GPIO_PIN53_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN53_SYNC2_BYPASS_S  0
+/** GPIO_PIN53_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN53_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN53_PAD_DRIVER_M  (GPIO_PIN53_PAD_DRIVER_V << GPIO_PIN53_PAD_DRIVER_S)
+#define GPIO_PIN53_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN53_PAD_DRIVER_S  2
+/** GPIO_PIN53_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN53_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN53_SYNC1_BYPASS_M  (GPIO_PIN53_SYNC1_BYPASS_V << GPIO_PIN53_SYNC1_BYPASS_S)
+#define GPIO_PIN53_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN53_SYNC1_BYPASS_S  3
+/** GPIO_PIN53_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN53_INT_TYPE    0x00000007U
+#define GPIO_PIN53_INT_TYPE_M  (GPIO_PIN53_INT_TYPE_V << GPIO_PIN53_INT_TYPE_S)
+#define GPIO_PIN53_INT_TYPE_V  0x00000007U
+#define GPIO_PIN53_INT_TYPE_S  7
+/** GPIO_PIN53_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN53_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN53_WAKEUP_ENABLE_M  (GPIO_PIN53_WAKEUP_ENABLE_V << GPIO_PIN53_WAKEUP_ENABLE_S)
+#define GPIO_PIN53_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN53_WAKEUP_ENABLE_S  10
+/** GPIO_PIN53_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN53_CONFIG    0x00000003U
+#define GPIO_PIN53_CONFIG_M  (GPIO_PIN53_CONFIG_V << GPIO_PIN53_CONFIG_S)
+#define GPIO_PIN53_CONFIG_V  0x00000003U
+#define GPIO_PIN53_CONFIG_S  11
+/** GPIO_PIN53_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN53_INT_ENA    0x0000001FU
+#define GPIO_PIN53_INT_ENA_M  (GPIO_PIN53_INT_ENA_V << GPIO_PIN53_INT_ENA_S)
+#define GPIO_PIN53_INT_ENA_V  0x0000001FU
+#define GPIO_PIN53_INT_ENA_S  13
+
+/** GPIO_PIN54_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN54_REG (DR_REG_GPIO_BASE + 0x14c)
+/** GPIO_PIN54_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN54_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN54_SYNC2_BYPASS_M  (GPIO_PIN54_SYNC2_BYPASS_V << GPIO_PIN54_SYNC2_BYPASS_S)
+#define GPIO_PIN54_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN54_SYNC2_BYPASS_S  0
+/** GPIO_PIN54_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN54_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN54_PAD_DRIVER_M  (GPIO_PIN54_PAD_DRIVER_V << GPIO_PIN54_PAD_DRIVER_S)
+#define GPIO_PIN54_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN54_PAD_DRIVER_S  2
+/** GPIO_PIN54_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN54_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN54_SYNC1_BYPASS_M  (GPIO_PIN54_SYNC1_BYPASS_V << GPIO_PIN54_SYNC1_BYPASS_S)
+#define GPIO_PIN54_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN54_SYNC1_BYPASS_S  3
+/** GPIO_PIN54_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN54_INT_TYPE    0x00000007U
+#define GPIO_PIN54_INT_TYPE_M  (GPIO_PIN54_INT_TYPE_V << GPIO_PIN54_INT_TYPE_S)
+#define GPIO_PIN54_INT_TYPE_V  0x00000007U
+#define GPIO_PIN54_INT_TYPE_S  7
+/** GPIO_PIN54_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN54_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN54_WAKEUP_ENABLE_M  (GPIO_PIN54_WAKEUP_ENABLE_V << GPIO_PIN54_WAKEUP_ENABLE_S)
+#define GPIO_PIN54_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN54_WAKEUP_ENABLE_S  10
+/** GPIO_PIN54_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN54_CONFIG    0x00000003U
+#define GPIO_PIN54_CONFIG_M  (GPIO_PIN54_CONFIG_V << GPIO_PIN54_CONFIG_S)
+#define GPIO_PIN54_CONFIG_V  0x00000003U
+#define GPIO_PIN54_CONFIG_S  11
+/** GPIO_PIN54_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN54_INT_ENA    0x0000001FU
+#define GPIO_PIN54_INT_ENA_M  (GPIO_PIN54_INT_ENA_V << GPIO_PIN54_INT_ENA_S)
+#define GPIO_PIN54_INT_ENA_V  0x0000001FU
+#define GPIO_PIN54_INT_ENA_S  13
+
+/** GPIO_PIN55_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN55_REG (DR_REG_GPIO_BASE + 0x150)
+/** GPIO_PIN55_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN55_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN55_SYNC2_BYPASS_M  (GPIO_PIN55_SYNC2_BYPASS_V << GPIO_PIN55_SYNC2_BYPASS_S)
+#define GPIO_PIN55_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN55_SYNC2_BYPASS_S  0
+/** GPIO_PIN55_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN55_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN55_PAD_DRIVER_M  (GPIO_PIN55_PAD_DRIVER_V << GPIO_PIN55_PAD_DRIVER_S)
+#define GPIO_PIN55_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN55_PAD_DRIVER_S  2
+/** GPIO_PIN55_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN55_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN55_SYNC1_BYPASS_M  (GPIO_PIN55_SYNC1_BYPASS_V << GPIO_PIN55_SYNC1_BYPASS_S)
+#define GPIO_PIN55_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN55_SYNC1_BYPASS_S  3
+/** GPIO_PIN55_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN55_INT_TYPE    0x00000007U
+#define GPIO_PIN55_INT_TYPE_M  (GPIO_PIN55_INT_TYPE_V << GPIO_PIN55_INT_TYPE_S)
+#define GPIO_PIN55_INT_TYPE_V  0x00000007U
+#define GPIO_PIN55_INT_TYPE_S  7
+/** GPIO_PIN55_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN55_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN55_WAKEUP_ENABLE_M  (GPIO_PIN55_WAKEUP_ENABLE_V << GPIO_PIN55_WAKEUP_ENABLE_S)
+#define GPIO_PIN55_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN55_WAKEUP_ENABLE_S  10
+/** GPIO_PIN55_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN55_CONFIG    0x00000003U
+#define GPIO_PIN55_CONFIG_M  (GPIO_PIN55_CONFIG_V << GPIO_PIN55_CONFIG_S)
+#define GPIO_PIN55_CONFIG_V  0x00000003U
+#define GPIO_PIN55_CONFIG_S  11
+/** GPIO_PIN55_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN55_INT_ENA    0x0000001FU
+#define GPIO_PIN55_INT_ENA_M  (GPIO_PIN55_INT_ENA_V << GPIO_PIN55_INT_ENA_S)
+#define GPIO_PIN55_INT_ENA_V  0x0000001FU
+#define GPIO_PIN55_INT_ENA_S  13
+
+/** GPIO_PIN56_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN56_REG (DR_REG_GPIO_BASE + 0x154)
+/** GPIO_PIN56_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN56_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN56_SYNC2_BYPASS_M  (GPIO_PIN56_SYNC2_BYPASS_V << GPIO_PIN56_SYNC2_BYPASS_S)
+#define GPIO_PIN56_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN56_SYNC2_BYPASS_S  0
+/** GPIO_PIN56_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN56_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN56_PAD_DRIVER_M  (GPIO_PIN56_PAD_DRIVER_V << GPIO_PIN56_PAD_DRIVER_S)
+#define GPIO_PIN56_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN56_PAD_DRIVER_S  2
+/** GPIO_PIN56_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN56_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN56_SYNC1_BYPASS_M  (GPIO_PIN56_SYNC1_BYPASS_V << GPIO_PIN56_SYNC1_BYPASS_S)
+#define GPIO_PIN56_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN56_SYNC1_BYPASS_S  3
+/** GPIO_PIN56_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN56_INT_TYPE    0x00000007U
+#define GPIO_PIN56_INT_TYPE_M  (GPIO_PIN56_INT_TYPE_V << GPIO_PIN56_INT_TYPE_S)
+#define GPIO_PIN56_INT_TYPE_V  0x00000007U
+#define GPIO_PIN56_INT_TYPE_S  7
+/** GPIO_PIN56_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN56_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN56_WAKEUP_ENABLE_M  (GPIO_PIN56_WAKEUP_ENABLE_V << GPIO_PIN56_WAKEUP_ENABLE_S)
+#define GPIO_PIN56_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN56_WAKEUP_ENABLE_S  10
+/** GPIO_PIN56_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN56_CONFIG    0x00000003U
+#define GPIO_PIN56_CONFIG_M  (GPIO_PIN56_CONFIG_V << GPIO_PIN56_CONFIG_S)
+#define GPIO_PIN56_CONFIG_V  0x00000003U
+#define GPIO_PIN56_CONFIG_S  11
+/** GPIO_PIN56_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN56_INT_ENA    0x0000001FU
+#define GPIO_PIN56_INT_ENA_M  (GPIO_PIN56_INT_ENA_V << GPIO_PIN56_INT_ENA_S)
+#define GPIO_PIN56_INT_ENA_V  0x0000001FU
+#define GPIO_PIN56_INT_ENA_S  13
+
+/** GPIO_FUNC1_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
+/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC1_IN_SEL    0x0000003FU
+#define GPIO_FUNC1_IN_SEL_M  (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S)
+#define GPIO_FUNC1_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC1_IN_SEL_S  0
+/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC1_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC1_IN_INV_SEL_M  (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S)
+#define GPIO_FUNC1_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_IN_INV_SEL_S  6
+/** GPIO_SIG1_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG1_IN_SEL    (BIT(7))
+#define GPIO_SIG1_IN_SEL_M  (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S)
+#define GPIO_SIG1_IN_SEL_V  0x00000001U
+#define GPIO_SIG1_IN_SEL_S  7
+
+/** GPIO_FUNC2_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160)
+/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC2_IN_SEL    0x0000003FU
+#define GPIO_FUNC2_IN_SEL_M  (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S)
+#define GPIO_FUNC2_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC2_IN_SEL_S  0
+/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC2_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC2_IN_INV_SEL_M  (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S)
+#define GPIO_FUNC2_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_IN_INV_SEL_S  6
+/** GPIO_SIG2_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG2_IN_SEL    (BIT(7))
+#define GPIO_SIG2_IN_SEL_M  (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S)
+#define GPIO_SIG2_IN_SEL_V  0x00000001U
+#define GPIO_SIG2_IN_SEL_S  7
+
+/** GPIO_FUNC3_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164)
+/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC3_IN_SEL    0x0000003FU
+#define GPIO_FUNC3_IN_SEL_M  (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S)
+#define GPIO_FUNC3_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC3_IN_SEL_S  0
+/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC3_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC3_IN_INV_SEL_M  (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S)
+#define GPIO_FUNC3_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_IN_INV_SEL_S  6
+/** GPIO_SIG3_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG3_IN_SEL    (BIT(7))
+#define GPIO_SIG3_IN_SEL_M  (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S)
+#define GPIO_SIG3_IN_SEL_V  0x00000001U
+#define GPIO_SIG3_IN_SEL_S  7
+
+/** GPIO_FUNC4_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168)
+/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC4_IN_SEL    0x0000003FU
+#define GPIO_FUNC4_IN_SEL_M  (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S)
+#define GPIO_FUNC4_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC4_IN_SEL_S  0
+/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC4_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC4_IN_INV_SEL_M  (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S)
+#define GPIO_FUNC4_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_IN_INV_SEL_S  6
+/** GPIO_SIG4_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG4_IN_SEL    (BIT(7))
+#define GPIO_SIG4_IN_SEL_M  (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S)
+#define GPIO_SIG4_IN_SEL_V  0x00000001U
+#define GPIO_SIG4_IN_SEL_S  7
+
+/** GPIO_FUNC5_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
+/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC5_IN_SEL    0x0000003FU
+#define GPIO_FUNC5_IN_SEL_M  (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S)
+#define GPIO_FUNC5_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC5_IN_SEL_S  0
+/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC5_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC5_IN_INV_SEL_M  (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S)
+#define GPIO_FUNC5_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_IN_INV_SEL_S  6
+/** GPIO_SIG5_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG5_IN_SEL    (BIT(7))
+#define GPIO_SIG5_IN_SEL_M  (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S)
+#define GPIO_SIG5_IN_SEL_V  0x00000001U
+#define GPIO_SIG5_IN_SEL_S  7
+
+/** GPIO_FUNC6_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170)
+/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC6_IN_SEL    0x0000003FU
+#define GPIO_FUNC6_IN_SEL_M  (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S)
+#define GPIO_FUNC6_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC6_IN_SEL_S  0
+/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC6_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_M  (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S)
+#define GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_IN_INV_SEL_S  6
+/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG6_IN_SEL    (BIT(7))
+#define GPIO_SIG6_IN_SEL_M  (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S)
+#define GPIO_SIG6_IN_SEL_V  0x00000001U
+#define GPIO_SIG6_IN_SEL_S  7
+
+/** GPIO_FUNC7_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174)
+/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC7_IN_SEL    0x0000003FU
+#define GPIO_FUNC7_IN_SEL_M  (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S)
+#define GPIO_FUNC7_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC7_IN_SEL_S  0
+/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC7_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_M  (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S)
+#define GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_IN_INV_SEL_S  6
+/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG7_IN_SEL    (BIT(7))
+#define GPIO_SIG7_IN_SEL_M  (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S)
+#define GPIO_SIG7_IN_SEL_V  0x00000001U
+#define GPIO_SIG7_IN_SEL_S  7
+
+/** GPIO_FUNC8_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178)
+/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC8_IN_SEL    0x0000003FU
+#define GPIO_FUNC8_IN_SEL_M  (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S)
+#define GPIO_FUNC8_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC8_IN_SEL_S  0
+/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC8_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_M  (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S)
+#define GPIO_FUNC8_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_IN_INV_SEL_S  6
+/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG8_IN_SEL    (BIT(7))
+#define GPIO_SIG8_IN_SEL_M  (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S)
+#define GPIO_SIG8_IN_SEL_V  0x00000001U
+#define GPIO_SIG8_IN_SEL_S  7
+
+/** GPIO_FUNC9_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c)
+/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC9_IN_SEL    0x0000003FU
+#define GPIO_FUNC9_IN_SEL_M  (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S)
+#define GPIO_FUNC9_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC9_IN_SEL_S  0
+/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC9_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_M  (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S)
+#define GPIO_FUNC9_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_IN_INV_SEL_S  6
+/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG9_IN_SEL    (BIT(7))
+#define GPIO_SIG9_IN_SEL_M  (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S)
+#define GPIO_SIG9_IN_SEL_V  0x00000001U
+#define GPIO_SIG9_IN_SEL_S  7
+
+/** GPIO_FUNC10_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180)
+/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC10_IN_SEL    0x0000003FU
+#define GPIO_FUNC10_IN_SEL_M  (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S)
+#define GPIO_FUNC10_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC10_IN_SEL_S  0
+/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC10_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_M  (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S)
+#define GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_IN_INV_SEL_S  6
+/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG10_IN_SEL    (BIT(7))
+#define GPIO_SIG10_IN_SEL_M  (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S)
+#define GPIO_SIG10_IN_SEL_V  0x00000001U
+#define GPIO_SIG10_IN_SEL_S  7
+
+/** GPIO_FUNC11_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184)
+/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC11_IN_SEL    0x0000003FU
+#define GPIO_FUNC11_IN_SEL_M  (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S)
+#define GPIO_FUNC11_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC11_IN_SEL_S  0
+/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC11_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_M  (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S)
+#define GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_IN_INV_SEL_S  6
+/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG11_IN_SEL    (BIT(7))
+#define GPIO_SIG11_IN_SEL_M  (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S)
+#define GPIO_SIG11_IN_SEL_V  0x00000001U
+#define GPIO_SIG11_IN_SEL_S  7
+
+/** GPIO_FUNC12_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188)
+/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC12_IN_SEL    0x0000003FU
+#define GPIO_FUNC12_IN_SEL_M  (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S)
+#define GPIO_FUNC12_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC12_IN_SEL_S  0
+/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC12_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_M  (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S)
+#define GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_IN_INV_SEL_S  6
+/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG12_IN_SEL    (BIT(7))
+#define GPIO_SIG12_IN_SEL_M  (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S)
+#define GPIO_SIG12_IN_SEL_V  0x00000001U
+#define GPIO_SIG12_IN_SEL_S  7
+
+/** GPIO_FUNC13_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c)
+/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC13_IN_SEL    0x0000003FU
+#define GPIO_FUNC13_IN_SEL_M  (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S)
+#define GPIO_FUNC13_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC13_IN_SEL_S  0
+/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC13_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_M  (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S)
+#define GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_IN_INV_SEL_S  6
+/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG13_IN_SEL    (BIT(7))
+#define GPIO_SIG13_IN_SEL_M  (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S)
+#define GPIO_SIG13_IN_SEL_V  0x00000001U
+#define GPIO_SIG13_IN_SEL_S  7
+
+/** GPIO_FUNC14_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190)
+/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC14_IN_SEL    0x0000003FU
+#define GPIO_FUNC14_IN_SEL_M  (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S)
+#define GPIO_FUNC14_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC14_IN_SEL_S  0
+/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC14_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_M  (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S)
+#define GPIO_FUNC14_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_IN_INV_SEL_S  6
+/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG14_IN_SEL    (BIT(7))
+#define GPIO_SIG14_IN_SEL_M  (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S)
+#define GPIO_SIG14_IN_SEL_V  0x00000001U
+#define GPIO_SIG14_IN_SEL_S  7
+
+/** GPIO_FUNC15_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194)
+/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC15_IN_SEL    0x0000003FU
+#define GPIO_FUNC15_IN_SEL_M  (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S)
+#define GPIO_FUNC15_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC15_IN_SEL_S  0
+/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC15_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_M  (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S)
+#define GPIO_FUNC15_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_IN_INV_SEL_S  6
+/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG15_IN_SEL    (BIT(7))
+#define GPIO_SIG15_IN_SEL_M  (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S)
+#define GPIO_SIG15_IN_SEL_V  0x00000001U
+#define GPIO_SIG15_IN_SEL_S  7
+
+/** GPIO_FUNC16_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198)
+/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC16_IN_SEL    0x0000003FU
+#define GPIO_FUNC16_IN_SEL_M  (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S)
+#define GPIO_FUNC16_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC16_IN_SEL_S  0
+/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC16_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_M  (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S)
+#define GPIO_FUNC16_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_IN_INV_SEL_S  6
+/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG16_IN_SEL    (BIT(7))
+#define GPIO_SIG16_IN_SEL_M  (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S)
+#define GPIO_SIG16_IN_SEL_V  0x00000001U
+#define GPIO_SIG16_IN_SEL_S  7
+
+/** GPIO_FUNC17_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c)
+/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC17_IN_SEL    0x0000003FU
+#define GPIO_FUNC17_IN_SEL_M  (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S)
+#define GPIO_FUNC17_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC17_IN_SEL_S  0
+/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC17_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_M  (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S)
+#define GPIO_FUNC17_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_IN_INV_SEL_S  6
+/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG17_IN_SEL    (BIT(7))
+#define GPIO_SIG17_IN_SEL_M  (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S)
+#define GPIO_SIG17_IN_SEL_V  0x00000001U
+#define GPIO_SIG17_IN_SEL_S  7
+
+/** GPIO_FUNC18_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0)
+/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC18_IN_SEL    0x0000003FU
+#define GPIO_FUNC18_IN_SEL_M  (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S)
+#define GPIO_FUNC18_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC18_IN_SEL_S  0
+/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC18_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC18_IN_INV_SEL_M  (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S)
+#define GPIO_FUNC18_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_IN_INV_SEL_S  6
+/** GPIO_SIG18_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG18_IN_SEL    (BIT(7))
+#define GPIO_SIG18_IN_SEL_M  (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S)
+#define GPIO_SIG18_IN_SEL_V  0x00000001U
+#define GPIO_SIG18_IN_SEL_S  7
+
+/** GPIO_FUNC19_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4)
+/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC19_IN_SEL    0x0000003FU
+#define GPIO_FUNC19_IN_SEL_M  (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S)
+#define GPIO_FUNC19_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC19_IN_SEL_S  0
+/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC19_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC19_IN_INV_SEL_M  (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S)
+#define GPIO_FUNC19_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_IN_INV_SEL_S  6
+/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG19_IN_SEL    (BIT(7))
+#define GPIO_SIG19_IN_SEL_M  (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S)
+#define GPIO_SIG19_IN_SEL_V  0x00000001U
+#define GPIO_SIG19_IN_SEL_S  7
+
+/** GPIO_FUNC20_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8)
+/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC20_IN_SEL    0x0000003FU
+#define GPIO_FUNC20_IN_SEL_M  (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S)
+#define GPIO_FUNC20_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC20_IN_SEL_S  0
+/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC20_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC20_IN_INV_SEL_M  (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S)
+#define GPIO_FUNC20_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_IN_INV_SEL_S  6
+/** GPIO_SIG20_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG20_IN_SEL    (BIT(7))
+#define GPIO_SIG20_IN_SEL_M  (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S)
+#define GPIO_SIG20_IN_SEL_V  0x00000001U
+#define GPIO_SIG20_IN_SEL_S  7
+
+/** GPIO_FUNC21_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac)
+/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC21_IN_SEL    0x0000003FU
+#define GPIO_FUNC21_IN_SEL_M  (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S)
+#define GPIO_FUNC21_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC21_IN_SEL_S  0
+/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC21_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC21_IN_INV_SEL_M  (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S)
+#define GPIO_FUNC21_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_IN_INV_SEL_S  6
+/** GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG21_IN_SEL    (BIT(7))
+#define GPIO_SIG21_IN_SEL_M  (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S)
+#define GPIO_SIG21_IN_SEL_V  0x00000001U
+#define GPIO_SIG21_IN_SEL_S  7
+
+/** GPIO_FUNC22_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0)
+/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC22_IN_SEL    0x0000003FU
+#define GPIO_FUNC22_IN_SEL_M  (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S)
+#define GPIO_FUNC22_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC22_IN_SEL_S  0
+/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC22_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC22_IN_INV_SEL_M  (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S)
+#define GPIO_FUNC22_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_IN_INV_SEL_S  6
+/** GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG22_IN_SEL    (BIT(7))
+#define GPIO_SIG22_IN_SEL_M  (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S)
+#define GPIO_SIG22_IN_SEL_V  0x00000001U
+#define GPIO_SIG22_IN_SEL_S  7
+
+/** GPIO_FUNC23_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4)
+/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC23_IN_SEL    0x0000003FU
+#define GPIO_FUNC23_IN_SEL_M  (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S)
+#define GPIO_FUNC23_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC23_IN_SEL_S  0
+/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC23_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC23_IN_INV_SEL_M  (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S)
+#define GPIO_FUNC23_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_IN_INV_SEL_S  6
+/** GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG23_IN_SEL    (BIT(7))
+#define GPIO_SIG23_IN_SEL_M  (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S)
+#define GPIO_SIG23_IN_SEL_V  0x00000001U
+#define GPIO_SIG23_IN_SEL_S  7
+
+/** GPIO_FUNC24_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8)
+/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC24_IN_SEL    0x0000003FU
+#define GPIO_FUNC24_IN_SEL_M  (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S)
+#define GPIO_FUNC24_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC24_IN_SEL_S  0
+/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC24_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC24_IN_INV_SEL_M  (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S)
+#define GPIO_FUNC24_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_IN_INV_SEL_S  6
+/** GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG24_IN_SEL    (BIT(7))
+#define GPIO_SIG24_IN_SEL_M  (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S)
+#define GPIO_SIG24_IN_SEL_V  0x00000001U
+#define GPIO_SIG24_IN_SEL_S  7
+
+/** GPIO_FUNC25_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc)
+/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC25_IN_SEL    0x0000003FU
+#define GPIO_FUNC25_IN_SEL_M  (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S)
+#define GPIO_FUNC25_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC25_IN_SEL_S  0
+/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC25_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC25_IN_INV_SEL_M  (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S)
+#define GPIO_FUNC25_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_IN_INV_SEL_S  6
+/** GPIO_SIG25_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG25_IN_SEL    (BIT(7))
+#define GPIO_SIG25_IN_SEL_M  (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S)
+#define GPIO_SIG25_IN_SEL_V  0x00000001U
+#define GPIO_SIG25_IN_SEL_S  7
+
+/** GPIO_FUNC26_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0)
+/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC26_IN_SEL    0x0000003FU
+#define GPIO_FUNC26_IN_SEL_M  (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S)
+#define GPIO_FUNC26_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC26_IN_SEL_S  0
+/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC26_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC26_IN_INV_SEL_M  (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S)
+#define GPIO_FUNC26_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_IN_INV_SEL_S  6
+/** GPIO_SIG26_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG26_IN_SEL    (BIT(7))
+#define GPIO_SIG26_IN_SEL_M  (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S)
+#define GPIO_SIG26_IN_SEL_V  0x00000001U
+#define GPIO_SIG26_IN_SEL_S  7
+
+/** GPIO_FUNC27_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4)
+/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC27_IN_SEL    0x0000003FU
+#define GPIO_FUNC27_IN_SEL_M  (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S)
+#define GPIO_FUNC27_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC27_IN_SEL_S  0
+/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC27_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_M  (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S)
+#define GPIO_FUNC27_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_IN_INV_SEL_S  6
+/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG27_IN_SEL    (BIT(7))
+#define GPIO_SIG27_IN_SEL_M  (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S)
+#define GPIO_SIG27_IN_SEL_V  0x00000001U
+#define GPIO_SIG27_IN_SEL_S  7
+
+/** GPIO_FUNC28_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8)
+/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC28_IN_SEL    0x0000003FU
+#define GPIO_FUNC28_IN_SEL_M  (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S)
+#define GPIO_FUNC28_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC28_IN_SEL_S  0
+/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC28_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_M  (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S)
+#define GPIO_FUNC28_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_IN_INV_SEL_S  6
+/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG28_IN_SEL    (BIT(7))
+#define GPIO_SIG28_IN_SEL_M  (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S)
+#define GPIO_SIG28_IN_SEL_V  0x00000001U
+#define GPIO_SIG28_IN_SEL_S  7
+
+/** GPIO_FUNC29_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc)
+/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC29_IN_SEL    0x0000003FU
+#define GPIO_FUNC29_IN_SEL_M  (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S)
+#define GPIO_FUNC29_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC29_IN_SEL_S  0
+/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC29_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_M  (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S)
+#define GPIO_FUNC29_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_IN_INV_SEL_S  6
+/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG29_IN_SEL    (BIT(7))
+#define GPIO_SIG29_IN_SEL_M  (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S)
+#define GPIO_SIG29_IN_SEL_V  0x00000001U
+#define GPIO_SIG29_IN_SEL_S  7
+
+/** GPIO_FUNC30_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0)
+/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC30_IN_SEL    0x0000003FU
+#define GPIO_FUNC30_IN_SEL_M  (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S)
+#define GPIO_FUNC30_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC30_IN_SEL_S  0
+/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC30_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_M  (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S)
+#define GPIO_FUNC30_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_IN_INV_SEL_S  6
+/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG30_IN_SEL    (BIT(7))
+#define GPIO_SIG30_IN_SEL_M  (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S)
+#define GPIO_SIG30_IN_SEL_V  0x00000001U
+#define GPIO_SIG30_IN_SEL_S  7
+
+/** GPIO_FUNC31_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4)
+/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC31_IN_SEL    0x0000003FU
+#define GPIO_FUNC31_IN_SEL_M  (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S)
+#define GPIO_FUNC31_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC31_IN_SEL_S  0
+/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC31_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_M  (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S)
+#define GPIO_FUNC31_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_IN_INV_SEL_S  6
+/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG31_IN_SEL    (BIT(7))
+#define GPIO_SIG31_IN_SEL_M  (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S)
+#define GPIO_SIG31_IN_SEL_V  0x00000001U
+#define GPIO_SIG31_IN_SEL_S  7
+
+/** GPIO_FUNC32_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8)
+/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC32_IN_SEL    0x0000003FU
+#define GPIO_FUNC32_IN_SEL_M  (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S)
+#define GPIO_FUNC32_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC32_IN_SEL_S  0
+/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC32_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_M  (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S)
+#define GPIO_FUNC32_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_IN_INV_SEL_S  6
+/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG32_IN_SEL    (BIT(7))
+#define GPIO_SIG32_IN_SEL_M  (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S)
+#define GPIO_SIG32_IN_SEL_V  0x00000001U
+#define GPIO_SIG32_IN_SEL_S  7
+
+/** GPIO_FUNC33_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc)
+/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC33_IN_SEL    0x0000003FU
+#define GPIO_FUNC33_IN_SEL_M  (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S)
+#define GPIO_FUNC33_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC33_IN_SEL_S  0
+/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC33_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_M  (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S)
+#define GPIO_FUNC33_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_IN_INV_SEL_S  6
+/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG33_IN_SEL    (BIT(7))
+#define GPIO_SIG33_IN_SEL_M  (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S)
+#define GPIO_SIG33_IN_SEL_V  0x00000001U
+#define GPIO_SIG33_IN_SEL_S  7
+
+/** GPIO_FUNC34_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0)
+/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC34_IN_SEL    0x0000003FU
+#define GPIO_FUNC34_IN_SEL_M  (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S)
+#define GPIO_FUNC34_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC34_IN_SEL_S  0
+/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC34_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_M  (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S)
+#define GPIO_FUNC34_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_IN_INV_SEL_S  6
+/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG34_IN_SEL    (BIT(7))
+#define GPIO_SIG34_IN_SEL_M  (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S)
+#define GPIO_SIG34_IN_SEL_V  0x00000001U
+#define GPIO_SIG34_IN_SEL_S  7
+
+/** GPIO_FUNC35_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4)
+/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC35_IN_SEL    0x0000003FU
+#define GPIO_FUNC35_IN_SEL_M  (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S)
+#define GPIO_FUNC35_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC35_IN_SEL_S  0
+/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC35_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_M  (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S)
+#define GPIO_FUNC35_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_IN_INV_SEL_S  6
+/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG35_IN_SEL    (BIT(7))
+#define GPIO_SIG35_IN_SEL_M  (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S)
+#define GPIO_SIG35_IN_SEL_V  0x00000001U
+#define GPIO_SIG35_IN_SEL_S  7
+
+/** GPIO_FUNC36_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8)
+/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC36_IN_SEL    0x0000003FU
+#define GPIO_FUNC36_IN_SEL_M  (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S)
+#define GPIO_FUNC36_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC36_IN_SEL_S  0
+/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC36_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC36_IN_INV_SEL_M  (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S)
+#define GPIO_FUNC36_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_IN_INV_SEL_S  6
+/** GPIO_SIG36_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG36_IN_SEL    (BIT(7))
+#define GPIO_SIG36_IN_SEL_M  (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S)
+#define GPIO_SIG36_IN_SEL_V  0x00000001U
+#define GPIO_SIG36_IN_SEL_S  7
+
+/** GPIO_FUNC37_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec)
+/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC37_IN_SEL    0x0000003FU
+#define GPIO_FUNC37_IN_SEL_M  (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S)
+#define GPIO_FUNC37_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC37_IN_SEL_S  0
+/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC37_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC37_IN_INV_SEL_M  (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S)
+#define GPIO_FUNC37_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_IN_INV_SEL_S  6
+/** GPIO_SIG37_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG37_IN_SEL    (BIT(7))
+#define GPIO_SIG37_IN_SEL_M  (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S)
+#define GPIO_SIG37_IN_SEL_V  0x00000001U
+#define GPIO_SIG37_IN_SEL_S  7
+
+/** GPIO_FUNC38_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0)
+/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC38_IN_SEL    0x0000003FU
+#define GPIO_FUNC38_IN_SEL_M  (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S)
+#define GPIO_FUNC38_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC38_IN_SEL_S  0
+/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC38_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC38_IN_INV_SEL_M  (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S)
+#define GPIO_FUNC38_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_IN_INV_SEL_S  6
+/** GPIO_SIG38_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG38_IN_SEL    (BIT(7))
+#define GPIO_SIG38_IN_SEL_M  (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S)
+#define GPIO_SIG38_IN_SEL_V  0x00000001U
+#define GPIO_SIG38_IN_SEL_S  7
+
+/** GPIO_FUNC39_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4)
+/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC39_IN_SEL    0x0000003FU
+#define GPIO_FUNC39_IN_SEL_M  (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S)
+#define GPIO_FUNC39_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC39_IN_SEL_S  0
+/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC39_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC39_IN_INV_SEL_M  (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S)
+#define GPIO_FUNC39_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_IN_INV_SEL_S  6
+/** GPIO_SIG39_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG39_IN_SEL    (BIT(7))
+#define GPIO_SIG39_IN_SEL_M  (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S)
+#define GPIO_SIG39_IN_SEL_V  0x00000001U
+#define GPIO_SIG39_IN_SEL_S  7
+
+/** GPIO_FUNC40_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8)
+/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC40_IN_SEL    0x0000003FU
+#define GPIO_FUNC40_IN_SEL_M  (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S)
+#define GPIO_FUNC40_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC40_IN_SEL_S  0
+/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC40_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC40_IN_INV_SEL_M  (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S)
+#define GPIO_FUNC40_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_IN_INV_SEL_S  6
+/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG40_IN_SEL    (BIT(7))
+#define GPIO_SIG40_IN_SEL_M  (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S)
+#define GPIO_SIG40_IN_SEL_V  0x00000001U
+#define GPIO_SIG40_IN_SEL_S  7
+
+/** GPIO_FUNC41_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc)
+/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC41_IN_SEL    0x0000003FU
+#define GPIO_FUNC41_IN_SEL_M  (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S)
+#define GPIO_FUNC41_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC41_IN_SEL_S  0
+/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC41_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_M  (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S)
+#define GPIO_FUNC41_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_IN_INV_SEL_S  6
+/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG41_IN_SEL    (BIT(7))
+#define GPIO_SIG41_IN_SEL_M  (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S)
+#define GPIO_SIG41_IN_SEL_V  0x00000001U
+#define GPIO_SIG41_IN_SEL_S  7
+
+/** GPIO_FUNC42_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200)
+/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC42_IN_SEL    0x0000003FU
+#define GPIO_FUNC42_IN_SEL_M  (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S)
+#define GPIO_FUNC42_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC42_IN_SEL_S  0
+/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC42_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_M  (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S)
+#define GPIO_FUNC42_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_IN_INV_SEL_S  6
+/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG42_IN_SEL    (BIT(7))
+#define GPIO_SIG42_IN_SEL_M  (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S)
+#define GPIO_SIG42_IN_SEL_V  0x00000001U
+#define GPIO_SIG42_IN_SEL_S  7
+
+/** GPIO_FUNC43_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204)
+/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC43_IN_SEL    0x0000003FU
+#define GPIO_FUNC43_IN_SEL_M  (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S)
+#define GPIO_FUNC43_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC43_IN_SEL_S  0
+/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC43_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_M  (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S)
+#define GPIO_FUNC43_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_IN_INV_SEL_S  6
+/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG43_IN_SEL    (BIT(7))
+#define GPIO_SIG43_IN_SEL_M  (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S)
+#define GPIO_SIG43_IN_SEL_V  0x00000001U
+#define GPIO_SIG43_IN_SEL_S  7
+
+/** GPIO_FUNC44_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208)
+/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC44_IN_SEL    0x0000003FU
+#define GPIO_FUNC44_IN_SEL_M  (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S)
+#define GPIO_FUNC44_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC44_IN_SEL_S  0
+/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC44_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC44_IN_INV_SEL_M  (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S)
+#define GPIO_FUNC44_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_IN_INV_SEL_S  6
+/** GPIO_SIG44_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG44_IN_SEL    (BIT(7))
+#define GPIO_SIG44_IN_SEL_M  (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S)
+#define GPIO_SIG44_IN_SEL_V  0x00000001U
+#define GPIO_SIG44_IN_SEL_S  7
+
+/** GPIO_FUNC45_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c)
+/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC45_IN_SEL    0x0000003FU
+#define GPIO_FUNC45_IN_SEL_M  (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S)
+#define GPIO_FUNC45_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC45_IN_SEL_S  0
+/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC45_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC45_IN_INV_SEL_M  (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S)
+#define GPIO_FUNC45_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_IN_INV_SEL_S  6
+/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG45_IN_SEL    (BIT(7))
+#define GPIO_SIG45_IN_SEL_M  (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S)
+#define GPIO_SIG45_IN_SEL_V  0x00000001U
+#define GPIO_SIG45_IN_SEL_S  7
+
+/** GPIO_FUNC47_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214)
+/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC47_IN_SEL    0x0000003FU
+#define GPIO_FUNC47_IN_SEL_M  (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S)
+#define GPIO_FUNC47_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC47_IN_SEL_S  0
+/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC47_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_M  (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S)
+#define GPIO_FUNC47_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_IN_INV_SEL_S  6
+/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG47_IN_SEL    (BIT(7))
+#define GPIO_SIG47_IN_SEL_M  (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S)
+#define GPIO_SIG47_IN_SEL_V  0x00000001U
+#define GPIO_SIG47_IN_SEL_S  7
+
+/** GPIO_FUNC48_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218)
+/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC48_IN_SEL    0x0000003FU
+#define GPIO_FUNC48_IN_SEL_M  (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S)
+#define GPIO_FUNC48_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC48_IN_SEL_S  0
+/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC48_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC48_IN_INV_SEL_M  (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S)
+#define GPIO_FUNC48_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_IN_INV_SEL_S  6
+/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG48_IN_SEL    (BIT(7))
+#define GPIO_SIG48_IN_SEL_M  (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S)
+#define GPIO_SIG48_IN_SEL_V  0x00000001U
+#define GPIO_SIG48_IN_SEL_S  7
+
+/** GPIO_FUNC49_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c)
+/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC49_IN_SEL    0x0000003FU
+#define GPIO_FUNC49_IN_SEL_M  (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S)
+#define GPIO_FUNC49_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC49_IN_SEL_S  0
+/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC49_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC49_IN_INV_SEL_M  (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S)
+#define GPIO_FUNC49_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_IN_INV_SEL_S  6
+/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG49_IN_SEL    (BIT(7))
+#define GPIO_SIG49_IN_SEL_M  (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S)
+#define GPIO_SIG49_IN_SEL_V  0x00000001U
+#define GPIO_SIG49_IN_SEL_S  7
+
+/** GPIO_FUNC50_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220)
+/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC50_IN_SEL    0x0000003FU
+#define GPIO_FUNC50_IN_SEL_M  (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S)
+#define GPIO_FUNC50_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC50_IN_SEL_S  0
+/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC50_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC50_IN_INV_SEL_M  (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S)
+#define GPIO_FUNC50_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_IN_INV_SEL_S  6
+/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG50_IN_SEL    (BIT(7))
+#define GPIO_SIG50_IN_SEL_M  (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S)
+#define GPIO_SIG50_IN_SEL_V  0x00000001U
+#define GPIO_SIG50_IN_SEL_S  7
+
+/** GPIO_FUNC51_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224)
+/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC51_IN_SEL    0x0000003FU
+#define GPIO_FUNC51_IN_SEL_M  (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S)
+#define GPIO_FUNC51_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC51_IN_SEL_S  0
+/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC51_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC51_IN_INV_SEL_M  (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S)
+#define GPIO_FUNC51_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_IN_INV_SEL_S  6
+/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG51_IN_SEL    (BIT(7))
+#define GPIO_SIG51_IN_SEL_M  (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S)
+#define GPIO_SIG51_IN_SEL_V  0x00000001U
+#define GPIO_SIG51_IN_SEL_S  7
+
+/** GPIO_FUNC52_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228)
+/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC52_IN_SEL    0x0000003FU
+#define GPIO_FUNC52_IN_SEL_M  (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S)
+#define GPIO_FUNC52_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC52_IN_SEL_S  0
+/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC52_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC52_IN_INV_SEL_M  (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S)
+#define GPIO_FUNC52_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_IN_INV_SEL_S  6
+/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG52_IN_SEL    (BIT(7))
+#define GPIO_SIG52_IN_SEL_M  (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S)
+#define GPIO_SIG52_IN_SEL_V  0x00000001U
+#define GPIO_SIG52_IN_SEL_S  7
+
+/** GPIO_FUNC53_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c)
+/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC53_IN_SEL    0x0000003FU
+#define GPIO_FUNC53_IN_SEL_M  (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S)
+#define GPIO_FUNC53_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC53_IN_SEL_S  0
+/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC53_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC53_IN_INV_SEL_M  (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S)
+#define GPIO_FUNC53_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_IN_INV_SEL_S  6
+/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG53_IN_SEL    (BIT(7))
+#define GPIO_SIG53_IN_SEL_M  (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S)
+#define GPIO_SIG53_IN_SEL_V  0x00000001U
+#define GPIO_SIG53_IN_SEL_S  7
+
+/** GPIO_FUNC54_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230)
+/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC54_IN_SEL    0x0000003FU
+#define GPIO_FUNC54_IN_SEL_M  (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S)
+#define GPIO_FUNC54_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC54_IN_SEL_S  0
+/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC54_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC54_IN_INV_SEL_M  (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S)
+#define GPIO_FUNC54_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_IN_INV_SEL_S  6
+/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG54_IN_SEL    (BIT(7))
+#define GPIO_SIG54_IN_SEL_M  (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S)
+#define GPIO_SIG54_IN_SEL_V  0x00000001U
+#define GPIO_SIG54_IN_SEL_S  7
+
+/** GPIO_FUNC55_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234)
+/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC55_IN_SEL    0x0000003FU
+#define GPIO_FUNC55_IN_SEL_M  (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S)
+#define GPIO_FUNC55_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC55_IN_SEL_S  0
+/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC55_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC55_IN_INV_SEL_M  (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S)
+#define GPIO_FUNC55_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_IN_INV_SEL_S  6
+/** GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG55_IN_SEL    (BIT(7))
+#define GPIO_SIG55_IN_SEL_M  (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S)
+#define GPIO_SIG55_IN_SEL_V  0x00000001U
+#define GPIO_SIG55_IN_SEL_S  7
+
+/** GPIO_FUNC56_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238)
+/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC56_IN_SEL    0x0000003FU
+#define GPIO_FUNC56_IN_SEL_M  (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S)
+#define GPIO_FUNC56_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC56_IN_SEL_S  0
+/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC56_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC56_IN_INV_SEL_M  (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S)
+#define GPIO_FUNC56_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_IN_INV_SEL_S  6
+/** GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG56_IN_SEL    (BIT(7))
+#define GPIO_SIG56_IN_SEL_M  (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S)
+#define GPIO_SIG56_IN_SEL_V  0x00000001U
+#define GPIO_SIG56_IN_SEL_S  7
+
+/** GPIO_FUNC57_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c)
+/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC57_IN_SEL    0x0000003FU
+#define GPIO_FUNC57_IN_SEL_M  (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S)
+#define GPIO_FUNC57_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC57_IN_SEL_S  0
+/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC57_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC57_IN_INV_SEL_M  (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S)
+#define GPIO_FUNC57_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC57_IN_INV_SEL_S  6
+/** GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG57_IN_SEL    (BIT(7))
+#define GPIO_SIG57_IN_SEL_M  (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S)
+#define GPIO_SIG57_IN_SEL_V  0x00000001U
+#define GPIO_SIG57_IN_SEL_S  7
+
+/** GPIO_FUNC58_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240)
+/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC58_IN_SEL    0x0000003FU
+#define GPIO_FUNC58_IN_SEL_M  (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S)
+#define GPIO_FUNC58_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC58_IN_SEL_S  0
+/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC58_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC58_IN_INV_SEL_M  (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S)
+#define GPIO_FUNC58_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC58_IN_INV_SEL_S  6
+/** GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG58_IN_SEL    (BIT(7))
+#define GPIO_SIG58_IN_SEL_M  (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S)
+#define GPIO_SIG58_IN_SEL_V  0x00000001U
+#define GPIO_SIG58_IN_SEL_S  7
+
+/** GPIO_FUNC59_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244)
+/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC59_IN_SEL    0x0000003FU
+#define GPIO_FUNC59_IN_SEL_M  (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S)
+#define GPIO_FUNC59_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC59_IN_SEL_S  0
+/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC59_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC59_IN_INV_SEL_M  (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S)
+#define GPIO_FUNC59_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC59_IN_INV_SEL_S  6
+/** GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG59_IN_SEL    (BIT(7))
+#define GPIO_SIG59_IN_SEL_M  (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S)
+#define GPIO_SIG59_IN_SEL_V  0x00000001U
+#define GPIO_SIG59_IN_SEL_S  7
+
+/** GPIO_FUNC60_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248)
+/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC60_IN_SEL    0x0000003FU
+#define GPIO_FUNC60_IN_SEL_M  (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S)
+#define GPIO_FUNC60_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC60_IN_SEL_S  0
+/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC60_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC60_IN_INV_SEL_M  (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S)
+#define GPIO_FUNC60_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC60_IN_INV_SEL_S  6
+/** GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG60_IN_SEL    (BIT(7))
+#define GPIO_SIG60_IN_SEL_M  (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S)
+#define GPIO_SIG60_IN_SEL_V  0x00000001U
+#define GPIO_SIG60_IN_SEL_S  7
+
+/** GPIO_FUNC61_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c)
+/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC61_IN_SEL    0x0000003FU
+#define GPIO_FUNC61_IN_SEL_M  (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S)
+#define GPIO_FUNC61_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC61_IN_SEL_S  0
+/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC61_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC61_IN_INV_SEL_M  (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S)
+#define GPIO_FUNC61_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC61_IN_INV_SEL_S  6
+/** GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG61_IN_SEL    (BIT(7))
+#define GPIO_SIG61_IN_SEL_M  (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S)
+#define GPIO_SIG61_IN_SEL_V  0x00000001U
+#define GPIO_SIG61_IN_SEL_S  7
+
+/** GPIO_FUNC62_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250)
+/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC62_IN_SEL    0x0000003FU
+#define GPIO_FUNC62_IN_SEL_M  (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S)
+#define GPIO_FUNC62_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC62_IN_SEL_S  0
+/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC62_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC62_IN_INV_SEL_M  (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S)
+#define GPIO_FUNC62_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC62_IN_INV_SEL_S  6
+/** GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG62_IN_SEL    (BIT(7))
+#define GPIO_SIG62_IN_SEL_M  (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S)
+#define GPIO_SIG62_IN_SEL_V  0x00000001U
+#define GPIO_SIG62_IN_SEL_S  7
+
+/** GPIO_FUNC63_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254)
+/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC63_IN_SEL    0x0000003FU
+#define GPIO_FUNC63_IN_SEL_M  (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S)
+#define GPIO_FUNC63_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC63_IN_SEL_S  0
+/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC63_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC63_IN_INV_SEL_M  (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S)
+#define GPIO_FUNC63_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC63_IN_INV_SEL_S  6
+/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG63_IN_SEL    (BIT(7))
+#define GPIO_SIG63_IN_SEL_M  (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S)
+#define GPIO_SIG63_IN_SEL_V  0x00000001U
+#define GPIO_SIG63_IN_SEL_S  7
+
+/** GPIO_FUNC64_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258)
+/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC64_IN_SEL    0x0000003FU
+#define GPIO_FUNC64_IN_SEL_M  (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S)
+#define GPIO_FUNC64_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC64_IN_SEL_S  0
+/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC64_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_M  (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S)
+#define GPIO_FUNC64_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC64_IN_INV_SEL_S  6
+/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG64_IN_SEL    (BIT(7))
+#define GPIO_SIG64_IN_SEL_M  (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S)
+#define GPIO_SIG64_IN_SEL_V  0x00000001U
+#define GPIO_SIG64_IN_SEL_S  7
+
+/** GPIO_FUNC65_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c)
+/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC65_IN_SEL    0x0000003FU
+#define GPIO_FUNC65_IN_SEL_M  (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S)
+#define GPIO_FUNC65_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC65_IN_SEL_S  0
+/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC65_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_M  (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S)
+#define GPIO_FUNC65_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC65_IN_INV_SEL_S  6
+/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG65_IN_SEL    (BIT(7))
+#define GPIO_SIG65_IN_SEL_M  (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S)
+#define GPIO_SIG65_IN_SEL_V  0x00000001U
+#define GPIO_SIG65_IN_SEL_S  7
+
+/** GPIO_FUNC66_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260)
+/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC66_IN_SEL    0x0000003FU
+#define GPIO_FUNC66_IN_SEL_M  (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S)
+#define GPIO_FUNC66_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC66_IN_SEL_S  0
+/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC66_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_M  (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S)
+#define GPIO_FUNC66_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC66_IN_INV_SEL_S  6
+/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG66_IN_SEL    (BIT(7))
+#define GPIO_SIG66_IN_SEL_M  (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S)
+#define GPIO_SIG66_IN_SEL_V  0x00000001U
+#define GPIO_SIG66_IN_SEL_S  7
+
+/** GPIO_FUNC68_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268)
+/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC68_IN_SEL    0x0000003FU
+#define GPIO_FUNC68_IN_SEL_M  (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S)
+#define GPIO_FUNC68_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC68_IN_SEL_S  0
+/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC68_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_M  (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S)
+#define GPIO_FUNC68_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC68_IN_INV_SEL_S  6
+/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG68_IN_SEL    (BIT(7))
+#define GPIO_SIG68_IN_SEL_M  (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S)
+#define GPIO_SIG68_IN_SEL_V  0x00000001U
+#define GPIO_SIG68_IN_SEL_S  7
+
+/** GPIO_FUNC69_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c)
+/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC69_IN_SEL    0x0000003FU
+#define GPIO_FUNC69_IN_SEL_M  (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S)
+#define GPIO_FUNC69_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC69_IN_SEL_S  0
+/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC69_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_M  (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S)
+#define GPIO_FUNC69_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC69_IN_INV_SEL_S  6
+/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG69_IN_SEL    (BIT(7))
+#define GPIO_SIG69_IN_SEL_M  (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S)
+#define GPIO_SIG69_IN_SEL_V  0x00000001U
+#define GPIO_SIG69_IN_SEL_S  7
+
+/** GPIO_FUNC70_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270)
+/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC70_IN_SEL    0x0000003FU
+#define GPIO_FUNC70_IN_SEL_M  (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S)
+#define GPIO_FUNC70_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC70_IN_SEL_S  0
+/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC70_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC70_IN_INV_SEL_M  (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S)
+#define GPIO_FUNC70_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC70_IN_INV_SEL_S  6
+/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG70_IN_SEL    (BIT(7))
+#define GPIO_SIG70_IN_SEL_M  (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S)
+#define GPIO_SIG70_IN_SEL_V  0x00000001U
+#define GPIO_SIG70_IN_SEL_S  7
+
+/** GPIO_FUNC71_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274)
+/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC71_IN_SEL    0x0000003FU
+#define GPIO_FUNC71_IN_SEL_M  (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S)
+#define GPIO_FUNC71_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC71_IN_SEL_S  0
+/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC71_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC71_IN_INV_SEL_M  (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S)
+#define GPIO_FUNC71_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC71_IN_INV_SEL_S  6
+/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG71_IN_SEL    (BIT(7))
+#define GPIO_SIG71_IN_SEL_M  (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S)
+#define GPIO_SIG71_IN_SEL_V  0x00000001U
+#define GPIO_SIG71_IN_SEL_S  7
+
+/** GPIO_FUNC74_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280)
+/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC74_IN_SEL    0x0000003FU
+#define GPIO_FUNC74_IN_SEL_M  (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S)
+#define GPIO_FUNC74_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC74_IN_SEL_S  0
+/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC74_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_M  (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S)
+#define GPIO_FUNC74_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC74_IN_INV_SEL_S  6
+/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG74_IN_SEL    (BIT(7))
+#define GPIO_SIG74_IN_SEL_M  (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S)
+#define GPIO_SIG74_IN_SEL_V  0x00000001U
+#define GPIO_SIG74_IN_SEL_S  7
+
+/** GPIO_FUNC75_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284)
+/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC75_IN_SEL    0x0000003FU
+#define GPIO_FUNC75_IN_SEL_M  (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S)
+#define GPIO_FUNC75_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC75_IN_SEL_S  0
+/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC75_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC75_IN_INV_SEL_M  (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S)
+#define GPIO_FUNC75_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC75_IN_INV_SEL_S  6
+/** GPIO_SIG75_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG75_IN_SEL    (BIT(7))
+#define GPIO_SIG75_IN_SEL_M  (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S)
+#define GPIO_SIG75_IN_SEL_V  0x00000001U
+#define GPIO_SIG75_IN_SEL_S  7
+
+/** GPIO_FUNC76_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288)
+/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC76_IN_SEL    0x0000003FU
+#define GPIO_FUNC76_IN_SEL_M  (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S)
+#define GPIO_FUNC76_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC76_IN_SEL_S  0
+/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC76_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC76_IN_INV_SEL_M  (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S)
+#define GPIO_FUNC76_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC76_IN_INV_SEL_S  6
+/** GPIO_SIG76_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG76_IN_SEL    (BIT(7))
+#define GPIO_SIG76_IN_SEL_M  (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S)
+#define GPIO_SIG76_IN_SEL_V  0x00000001U
+#define GPIO_SIG76_IN_SEL_S  7
+
+/** GPIO_FUNC77_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c)
+/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC77_IN_SEL    0x0000003FU
+#define GPIO_FUNC77_IN_SEL_M  (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S)
+#define GPIO_FUNC77_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC77_IN_SEL_S  0
+/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC77_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC77_IN_INV_SEL_M  (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S)
+#define GPIO_FUNC77_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC77_IN_INV_SEL_S  6
+/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG77_IN_SEL    (BIT(7))
+#define GPIO_SIG77_IN_SEL_M  (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S)
+#define GPIO_SIG77_IN_SEL_V  0x00000001U
+#define GPIO_SIG77_IN_SEL_S  7
+
+/** GPIO_FUNC78_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290)
+/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC78_IN_SEL    0x0000003FU
+#define GPIO_FUNC78_IN_SEL_M  (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S)
+#define GPIO_FUNC78_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC78_IN_SEL_S  0
+/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC78_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC78_IN_INV_SEL_M  (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S)
+#define GPIO_FUNC78_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC78_IN_INV_SEL_S  6
+/** GPIO_SIG78_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG78_IN_SEL    (BIT(7))
+#define GPIO_SIG78_IN_SEL_M  (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S)
+#define GPIO_SIG78_IN_SEL_V  0x00000001U
+#define GPIO_SIG78_IN_SEL_S  7
+
+/** GPIO_FUNC80_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298)
+/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC80_IN_SEL    0x0000003FU
+#define GPIO_FUNC80_IN_SEL_M  (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S)
+#define GPIO_FUNC80_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC80_IN_SEL_S  0
+/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC80_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC80_IN_INV_SEL_M  (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S)
+#define GPIO_FUNC80_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC80_IN_INV_SEL_S  6
+/** GPIO_SIG80_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG80_IN_SEL    (BIT(7))
+#define GPIO_SIG80_IN_SEL_M  (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S)
+#define GPIO_SIG80_IN_SEL_V  0x00000001U
+#define GPIO_SIG80_IN_SEL_S  7
+
+/** GPIO_FUNC83_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4)
+/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC83_IN_SEL    0x0000003FU
+#define GPIO_FUNC83_IN_SEL_M  (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S)
+#define GPIO_FUNC83_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC83_IN_SEL_S  0
+/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC83_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_M  (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S)
+#define GPIO_FUNC83_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC83_IN_INV_SEL_S  6
+/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG83_IN_SEL    (BIT(7))
+#define GPIO_SIG83_IN_SEL_M  (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S)
+#define GPIO_SIG83_IN_SEL_V  0x00000001U
+#define GPIO_SIG83_IN_SEL_S  7
+
+/** GPIO_FUNC86_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0)
+/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC86_IN_SEL    0x0000003FU
+#define GPIO_FUNC86_IN_SEL_M  (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S)
+#define GPIO_FUNC86_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC86_IN_SEL_S  0
+/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC86_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC86_IN_INV_SEL_M  (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S)
+#define GPIO_FUNC86_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC86_IN_INV_SEL_S  6
+/** GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG86_IN_SEL    (BIT(7))
+#define GPIO_SIG86_IN_SEL_M  (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S)
+#define GPIO_SIG86_IN_SEL_V  0x00000001U
+#define GPIO_SIG86_IN_SEL_S  7
+
+/** GPIO_FUNC89_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc)
+/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC89_IN_SEL    0x0000003FU
+#define GPIO_FUNC89_IN_SEL_M  (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S)
+#define GPIO_FUNC89_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC89_IN_SEL_S  0
+/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC89_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC89_IN_INV_SEL_M  (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S)
+#define GPIO_FUNC89_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC89_IN_INV_SEL_S  6
+/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG89_IN_SEL    (BIT(7))
+#define GPIO_SIG89_IN_SEL_M  (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S)
+#define GPIO_SIG89_IN_SEL_V  0x00000001U
+#define GPIO_SIG89_IN_SEL_S  7
+
+/** GPIO_FUNC90_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0)
+/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC90_IN_SEL    0x0000003FU
+#define GPIO_FUNC90_IN_SEL_M  (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S)
+#define GPIO_FUNC90_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC90_IN_SEL_S  0
+/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC90_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC90_IN_INV_SEL_M  (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S)
+#define GPIO_FUNC90_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC90_IN_INV_SEL_S  6
+/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG90_IN_SEL    (BIT(7))
+#define GPIO_SIG90_IN_SEL_M  (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S)
+#define GPIO_SIG90_IN_SEL_V  0x00000001U
+#define GPIO_SIG90_IN_SEL_S  7
+
+/** GPIO_FUNC91_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4)
+/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC91_IN_SEL    0x0000003FU
+#define GPIO_FUNC91_IN_SEL_M  (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S)
+#define GPIO_FUNC91_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC91_IN_SEL_S  0
+/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC91_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC91_IN_INV_SEL_M  (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S)
+#define GPIO_FUNC91_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC91_IN_INV_SEL_S  6
+/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG91_IN_SEL    (BIT(7))
+#define GPIO_SIG91_IN_SEL_M  (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S)
+#define GPIO_SIG91_IN_SEL_V  0x00000001U
+#define GPIO_SIG91_IN_SEL_S  7
+
+/** GPIO_FUNC92_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8)
+/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC92_IN_SEL    0x0000003FU
+#define GPIO_FUNC92_IN_SEL_M  (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S)
+#define GPIO_FUNC92_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC92_IN_SEL_S  0
+/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC92_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC92_IN_INV_SEL_M  (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S)
+#define GPIO_FUNC92_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC92_IN_INV_SEL_S  6
+/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG92_IN_SEL    (BIT(7))
+#define GPIO_SIG92_IN_SEL_M  (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S)
+#define GPIO_SIG92_IN_SEL_V  0x00000001U
+#define GPIO_SIG92_IN_SEL_S  7
+
+/** GPIO_FUNC93_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc)
+/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC93_IN_SEL    0x0000003FU
+#define GPIO_FUNC93_IN_SEL_M  (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S)
+#define GPIO_FUNC93_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC93_IN_SEL_S  0
+/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC93_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC93_IN_INV_SEL_M  (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S)
+#define GPIO_FUNC93_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC93_IN_INV_SEL_S  6
+/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG93_IN_SEL    (BIT(7))
+#define GPIO_SIG93_IN_SEL_M  (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S)
+#define GPIO_SIG93_IN_SEL_V  0x00000001U
+#define GPIO_SIG93_IN_SEL_S  7
+
+/** GPIO_FUNC94_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0)
+/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC94_IN_SEL    0x0000003FU
+#define GPIO_FUNC94_IN_SEL_M  (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S)
+#define GPIO_FUNC94_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC94_IN_SEL_S  0
+/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC94_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC94_IN_INV_SEL_M  (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S)
+#define GPIO_FUNC94_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC94_IN_INV_SEL_S  6
+/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG94_IN_SEL    (BIT(7))
+#define GPIO_SIG94_IN_SEL_M  (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S)
+#define GPIO_SIG94_IN_SEL_V  0x00000001U
+#define GPIO_SIG94_IN_SEL_S  7
+
+/** GPIO_FUNC95_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4)
+/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC95_IN_SEL    0x0000003FU
+#define GPIO_FUNC95_IN_SEL_M  (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S)
+#define GPIO_FUNC95_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC95_IN_SEL_S  0
+/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC95_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC95_IN_INV_SEL_M  (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S)
+#define GPIO_FUNC95_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC95_IN_INV_SEL_S  6
+/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG95_IN_SEL    (BIT(7))
+#define GPIO_SIG95_IN_SEL_M  (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S)
+#define GPIO_SIG95_IN_SEL_V  0x00000001U
+#define GPIO_SIG95_IN_SEL_S  7
+
+/** GPIO_FUNC96_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8)
+/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC96_IN_SEL    0x0000003FU
+#define GPIO_FUNC96_IN_SEL_M  (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S)
+#define GPIO_FUNC96_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC96_IN_SEL_S  0
+/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC96_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC96_IN_INV_SEL_M  (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S)
+#define GPIO_FUNC96_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC96_IN_INV_SEL_S  6
+/** GPIO_SIG96_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG96_IN_SEL    (BIT(7))
+#define GPIO_SIG96_IN_SEL_M  (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S)
+#define GPIO_SIG96_IN_SEL_V  0x00000001U
+#define GPIO_SIG96_IN_SEL_S  7
+
+/** GPIO_FUNC97_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc)
+/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC97_IN_SEL    0x0000003FU
+#define GPIO_FUNC97_IN_SEL_M  (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S)
+#define GPIO_FUNC97_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC97_IN_SEL_S  0
+/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC97_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_M  (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S)
+#define GPIO_FUNC97_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC97_IN_INV_SEL_S  6
+/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG97_IN_SEL    (BIT(7))
+#define GPIO_SIG97_IN_SEL_M  (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S)
+#define GPIO_SIG97_IN_SEL_V  0x00000001U
+#define GPIO_SIG97_IN_SEL_S  7
+
+/** GPIO_FUNC98_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0)
+/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC98_IN_SEL    0x0000003FU
+#define GPIO_FUNC98_IN_SEL_M  (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S)
+#define GPIO_FUNC98_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC98_IN_SEL_S  0
+/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC98_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_M  (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S)
+#define GPIO_FUNC98_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC98_IN_INV_SEL_S  6
+/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG98_IN_SEL    (BIT(7))
+#define GPIO_SIG98_IN_SEL_M  (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S)
+#define GPIO_SIG98_IN_SEL_V  0x00000001U
+#define GPIO_SIG98_IN_SEL_S  7
+
+/** GPIO_FUNC99_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4)
+/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC99_IN_SEL    0x0000003FU
+#define GPIO_FUNC99_IN_SEL_M  (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S)
+#define GPIO_FUNC99_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC99_IN_SEL_S  0
+/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC99_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_M  (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S)
+#define GPIO_FUNC99_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC99_IN_INV_SEL_S  6
+/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG99_IN_SEL    (BIT(7))
+#define GPIO_SIG99_IN_SEL_M  (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S)
+#define GPIO_SIG99_IN_SEL_V  0x00000001U
+#define GPIO_SIG99_IN_SEL_S  7
+
+/** GPIO_FUNC100_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8)
+/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC100_IN_SEL    0x0000003FU
+#define GPIO_FUNC100_IN_SEL_M  (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S)
+#define GPIO_FUNC100_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC100_IN_SEL_S  0
+/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC100_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_M  (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S)
+#define GPIO_FUNC100_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC100_IN_INV_SEL_S  6
+/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG100_IN_SEL    (BIT(7))
+#define GPIO_SIG100_IN_SEL_M  (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S)
+#define GPIO_SIG100_IN_SEL_V  0x00000001U
+#define GPIO_SIG100_IN_SEL_S  7
+
+/** GPIO_FUNC101_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec)
+/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC101_IN_SEL    0x0000003FU
+#define GPIO_FUNC101_IN_SEL_M  (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S)
+#define GPIO_FUNC101_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC101_IN_SEL_S  0
+/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC101_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC101_IN_INV_SEL_M  (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S)
+#define GPIO_FUNC101_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC101_IN_INV_SEL_S  6
+/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG101_IN_SEL    (BIT(7))
+#define GPIO_SIG101_IN_SEL_M  (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S)
+#define GPIO_SIG101_IN_SEL_V  0x00000001U
+#define GPIO_SIG101_IN_SEL_S  7
+
+/** GPIO_FUNC102_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0)
+/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC102_IN_SEL    0x0000003FU
+#define GPIO_FUNC102_IN_SEL_M  (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S)
+#define GPIO_FUNC102_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC102_IN_SEL_S  0
+/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC102_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC102_IN_INV_SEL_M  (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S)
+#define GPIO_FUNC102_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC102_IN_INV_SEL_S  6
+/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG102_IN_SEL    (BIT(7))
+#define GPIO_SIG102_IN_SEL_M  (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S)
+#define GPIO_SIG102_IN_SEL_V  0x00000001U
+#define GPIO_SIG102_IN_SEL_S  7
+
+/** GPIO_FUNC103_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
+/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC103_IN_SEL    0x0000003FU
+#define GPIO_FUNC103_IN_SEL_M  (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S)
+#define GPIO_FUNC103_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC103_IN_SEL_S  0
+/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC103_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC103_IN_INV_SEL_M  (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S)
+#define GPIO_FUNC103_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC103_IN_INV_SEL_S  6
+/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG103_IN_SEL    (BIT(7))
+#define GPIO_SIG103_IN_SEL_M  (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S)
+#define GPIO_SIG103_IN_SEL_V  0x00000001U
+#define GPIO_SIG103_IN_SEL_S  7
+
+/** GPIO_FUNC104_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
+/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC104_IN_SEL    0x0000003FU
+#define GPIO_FUNC104_IN_SEL_M  (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S)
+#define GPIO_FUNC104_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC104_IN_SEL_S  0
+/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC104_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC104_IN_INV_SEL_M  (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S)
+#define GPIO_FUNC104_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC104_IN_INV_SEL_S  6
+/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG104_IN_SEL    (BIT(7))
+#define GPIO_SIG104_IN_SEL_M  (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S)
+#define GPIO_SIG104_IN_SEL_V  0x00000001U
+#define GPIO_SIG104_IN_SEL_S  7
+
+/** GPIO_FUNC105_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
+/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC105_IN_SEL    0x0000003FU
+#define GPIO_FUNC105_IN_SEL_M  (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S)
+#define GPIO_FUNC105_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC105_IN_SEL_S  0
+/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC105_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC105_IN_INV_SEL_M  (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S)
+#define GPIO_FUNC105_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC105_IN_INV_SEL_S  6
+/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG105_IN_SEL    (BIT(7))
+#define GPIO_SIG105_IN_SEL_M  (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S)
+#define GPIO_SIG105_IN_SEL_V  0x00000001U
+#define GPIO_SIG105_IN_SEL_S  7
+
+/** GPIO_FUNC106_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
+/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC106_IN_SEL    0x0000003FU
+#define GPIO_FUNC106_IN_SEL_M  (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S)
+#define GPIO_FUNC106_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC106_IN_SEL_S  0
+/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC106_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC106_IN_INV_SEL_M  (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S)
+#define GPIO_FUNC106_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC106_IN_INV_SEL_S  6
+/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG106_IN_SEL    (BIT(7))
+#define GPIO_SIG106_IN_SEL_M  (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S)
+#define GPIO_SIG106_IN_SEL_V  0x00000001U
+#define GPIO_SIG106_IN_SEL_S  7
+
+/** GPIO_FUNC107_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
+/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC107_IN_SEL    0x0000003FU
+#define GPIO_FUNC107_IN_SEL_M  (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S)
+#define GPIO_FUNC107_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC107_IN_SEL_S  0
+/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC107_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC107_IN_INV_SEL_M  (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S)
+#define GPIO_FUNC107_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC107_IN_INV_SEL_S  6
+/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG107_IN_SEL    (BIT(7))
+#define GPIO_SIG107_IN_SEL_M  (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S)
+#define GPIO_SIG107_IN_SEL_V  0x00000001U
+#define GPIO_SIG107_IN_SEL_S  7
+
+/** GPIO_FUNC108_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
+/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC108_IN_SEL    0x0000003FU
+#define GPIO_FUNC108_IN_SEL_M  (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S)
+#define GPIO_FUNC108_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC108_IN_SEL_S  0
+/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC108_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC108_IN_INV_SEL_M  (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S)
+#define GPIO_FUNC108_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC108_IN_INV_SEL_S  6
+/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG108_IN_SEL    (BIT(7))
+#define GPIO_SIG108_IN_SEL_M  (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S)
+#define GPIO_SIG108_IN_SEL_V  0x00000001U
+#define GPIO_SIG108_IN_SEL_S  7
+
+/** GPIO_FUNC109_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c)
+/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC109_IN_SEL    0x0000003FU
+#define GPIO_FUNC109_IN_SEL_M  (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S)
+#define GPIO_FUNC109_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC109_IN_SEL_S  0
+/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC109_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC109_IN_INV_SEL_M  (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S)
+#define GPIO_FUNC109_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC109_IN_INV_SEL_S  6
+/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG109_IN_SEL    (BIT(7))
+#define GPIO_SIG109_IN_SEL_M  (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S)
+#define GPIO_SIG109_IN_SEL_V  0x00000001U
+#define GPIO_SIG109_IN_SEL_S  7
+
+/** GPIO_FUNC110_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310)
+/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC110_IN_SEL    0x0000003FU
+#define GPIO_FUNC110_IN_SEL_M  (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S)
+#define GPIO_FUNC110_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC110_IN_SEL_S  0
+/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC110_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC110_IN_INV_SEL_M  (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S)
+#define GPIO_FUNC110_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC110_IN_INV_SEL_S  6
+/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG110_IN_SEL    (BIT(7))
+#define GPIO_SIG110_IN_SEL_M  (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S)
+#define GPIO_SIG110_IN_SEL_V  0x00000001U
+#define GPIO_SIG110_IN_SEL_S  7
+
+/** GPIO_FUNC111_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314)
+/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC111_IN_SEL    0x0000003FU
+#define GPIO_FUNC111_IN_SEL_M  (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S)
+#define GPIO_FUNC111_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC111_IN_SEL_S  0
+/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC111_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC111_IN_INV_SEL_M  (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S)
+#define GPIO_FUNC111_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC111_IN_INV_SEL_S  6
+/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG111_IN_SEL    (BIT(7))
+#define GPIO_SIG111_IN_SEL_M  (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S)
+#define GPIO_SIG111_IN_SEL_V  0x00000001U
+#define GPIO_SIG111_IN_SEL_S  7
+
+/** GPIO_FUNC112_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318)
+/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC112_IN_SEL    0x0000003FU
+#define GPIO_FUNC112_IN_SEL_M  (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S)
+#define GPIO_FUNC112_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC112_IN_SEL_S  0
+/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC112_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC112_IN_INV_SEL_M  (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S)
+#define GPIO_FUNC112_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC112_IN_INV_SEL_S  6
+/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG112_IN_SEL    (BIT(7))
+#define GPIO_SIG112_IN_SEL_M  (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S)
+#define GPIO_SIG112_IN_SEL_V  0x00000001U
+#define GPIO_SIG112_IN_SEL_S  7
+
+/** GPIO_FUNC113_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c)
+/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC113_IN_SEL    0x0000003FU
+#define GPIO_FUNC113_IN_SEL_M  (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S)
+#define GPIO_FUNC113_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC113_IN_SEL_S  0
+/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC113_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC113_IN_INV_SEL_M  (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S)
+#define GPIO_FUNC113_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC113_IN_INV_SEL_S  6
+/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG113_IN_SEL    (BIT(7))
+#define GPIO_SIG113_IN_SEL_M  (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S)
+#define GPIO_SIG113_IN_SEL_V  0x00000001U
+#define GPIO_SIG113_IN_SEL_S  7
+
+/** GPIO_FUNC114_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320)
+/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC114_IN_SEL    0x0000003FU
+#define GPIO_FUNC114_IN_SEL_M  (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S)
+#define GPIO_FUNC114_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC114_IN_SEL_S  0
+/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC114_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC114_IN_INV_SEL_M  (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S)
+#define GPIO_FUNC114_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC114_IN_INV_SEL_S  6
+/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG114_IN_SEL    (BIT(7))
+#define GPIO_SIG114_IN_SEL_M  (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S)
+#define GPIO_SIG114_IN_SEL_V  0x00000001U
+#define GPIO_SIG114_IN_SEL_S  7
+
+/** GPIO_FUNC117_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c)
+/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC117_IN_SEL    0x0000003FU
+#define GPIO_FUNC117_IN_SEL_M  (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S)
+#define GPIO_FUNC117_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC117_IN_SEL_S  0
+/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC117_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC117_IN_INV_SEL_M  (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S)
+#define GPIO_FUNC117_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC117_IN_INV_SEL_S  6
+/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG117_IN_SEL    (BIT(7))
+#define GPIO_SIG117_IN_SEL_M  (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S)
+#define GPIO_SIG117_IN_SEL_V  0x00000001U
+#define GPIO_SIG117_IN_SEL_S  7
+
+/** GPIO_FUNC118_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
+/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC118_IN_SEL    0x0000003FU
+#define GPIO_FUNC118_IN_SEL_M  (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S)
+#define GPIO_FUNC118_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC118_IN_SEL_S  0
+/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC118_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_M  (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S)
+#define GPIO_FUNC118_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC118_IN_INV_SEL_S  6
+/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG118_IN_SEL    (BIT(7))
+#define GPIO_SIG118_IN_SEL_M  (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S)
+#define GPIO_SIG118_IN_SEL_V  0x00000001U
+#define GPIO_SIG118_IN_SEL_S  7
+
+/** GPIO_FUNC126_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350)
+/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC126_IN_SEL    0x0000003FU
+#define GPIO_FUNC126_IN_SEL_M  (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S)
+#define GPIO_FUNC126_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC126_IN_SEL_S  0
+/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC126_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC126_IN_INV_SEL_M  (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S)
+#define GPIO_FUNC126_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC126_IN_INV_SEL_S  6
+/** GPIO_SIG126_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG126_IN_SEL    (BIT(7))
+#define GPIO_SIG126_IN_SEL_M  (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S)
+#define GPIO_SIG126_IN_SEL_V  0x00000001U
+#define GPIO_SIG126_IN_SEL_S  7
+
+/** GPIO_FUNC127_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354)
+/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC127_IN_SEL    0x0000003FU
+#define GPIO_FUNC127_IN_SEL_M  (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S)
+#define GPIO_FUNC127_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC127_IN_SEL_S  0
+/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC127_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC127_IN_INV_SEL_M  (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S)
+#define GPIO_FUNC127_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC127_IN_INV_SEL_S  6
+/** GPIO_SIG127_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG127_IN_SEL    (BIT(7))
+#define GPIO_SIG127_IN_SEL_M  (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S)
+#define GPIO_SIG127_IN_SEL_V  0x00000001U
+#define GPIO_SIG127_IN_SEL_S  7
+
+/** GPIO_FUNC128_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358)
+/** GPIO_FUNC128_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC128_IN_SEL    0x0000003FU
+#define GPIO_FUNC128_IN_SEL_M  (GPIO_FUNC128_IN_SEL_V << GPIO_FUNC128_IN_SEL_S)
+#define GPIO_FUNC128_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC128_IN_SEL_S  0
+/** GPIO_FUNC128_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC128_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC128_IN_INV_SEL_M  (GPIO_FUNC128_IN_INV_SEL_V << GPIO_FUNC128_IN_INV_SEL_S)
+#define GPIO_FUNC128_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC128_IN_INV_SEL_S  6
+/** GPIO_SIG128_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG128_IN_SEL    (BIT(7))
+#define GPIO_SIG128_IN_SEL_M  (GPIO_SIG128_IN_SEL_V << GPIO_SIG128_IN_SEL_S)
+#define GPIO_SIG128_IN_SEL_V  0x00000001U
+#define GPIO_SIG128_IN_SEL_S  7
+
+/** GPIO_FUNC129_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c)
+/** GPIO_FUNC129_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC129_IN_SEL    0x0000003FU
+#define GPIO_FUNC129_IN_SEL_M  (GPIO_FUNC129_IN_SEL_V << GPIO_FUNC129_IN_SEL_S)
+#define GPIO_FUNC129_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC129_IN_SEL_S  0
+/** GPIO_FUNC129_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC129_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC129_IN_INV_SEL_M  (GPIO_FUNC129_IN_INV_SEL_V << GPIO_FUNC129_IN_INV_SEL_S)
+#define GPIO_FUNC129_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC129_IN_INV_SEL_S  6
+/** GPIO_SIG129_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG129_IN_SEL    (BIT(7))
+#define GPIO_SIG129_IN_SEL_M  (GPIO_SIG129_IN_SEL_V << GPIO_SIG129_IN_SEL_S)
+#define GPIO_SIG129_IN_SEL_V  0x00000001U
+#define GPIO_SIG129_IN_SEL_S  7
+
+/** GPIO_FUNC130_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360)
+/** GPIO_FUNC130_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC130_IN_SEL    0x0000003FU
+#define GPIO_FUNC130_IN_SEL_M  (GPIO_FUNC130_IN_SEL_V << GPIO_FUNC130_IN_SEL_S)
+#define GPIO_FUNC130_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC130_IN_SEL_S  0
+/** GPIO_FUNC130_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC130_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC130_IN_INV_SEL_M  (GPIO_FUNC130_IN_INV_SEL_V << GPIO_FUNC130_IN_INV_SEL_S)
+#define GPIO_FUNC130_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC130_IN_INV_SEL_S  6
+/** GPIO_SIG130_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG130_IN_SEL    (BIT(7))
+#define GPIO_SIG130_IN_SEL_M  (GPIO_SIG130_IN_SEL_V << GPIO_SIG130_IN_SEL_S)
+#define GPIO_SIG130_IN_SEL_V  0x00000001U
+#define GPIO_SIG130_IN_SEL_S  7
+
+/** GPIO_FUNC131_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x364)
+/** GPIO_FUNC131_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC131_IN_SEL    0x0000003FU
+#define GPIO_FUNC131_IN_SEL_M  (GPIO_FUNC131_IN_SEL_V << GPIO_FUNC131_IN_SEL_S)
+#define GPIO_FUNC131_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC131_IN_SEL_S  0
+/** GPIO_FUNC131_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC131_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC131_IN_INV_SEL_M  (GPIO_FUNC131_IN_INV_SEL_V << GPIO_FUNC131_IN_INV_SEL_S)
+#define GPIO_FUNC131_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC131_IN_INV_SEL_S  6
+/** GPIO_SIG131_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG131_IN_SEL    (BIT(7))
+#define GPIO_SIG131_IN_SEL_M  (GPIO_SIG131_IN_SEL_V << GPIO_SIG131_IN_SEL_S)
+#define GPIO_SIG131_IN_SEL_V  0x00000001U
+#define GPIO_SIG131_IN_SEL_S  7
+
+/** GPIO_FUNC132_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368)
+/** GPIO_FUNC132_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC132_IN_SEL    0x0000003FU
+#define GPIO_FUNC132_IN_SEL_M  (GPIO_FUNC132_IN_SEL_V << GPIO_FUNC132_IN_SEL_S)
+#define GPIO_FUNC132_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC132_IN_SEL_S  0
+/** GPIO_FUNC132_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC132_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC132_IN_INV_SEL_M  (GPIO_FUNC132_IN_INV_SEL_V << GPIO_FUNC132_IN_INV_SEL_S)
+#define GPIO_FUNC132_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC132_IN_INV_SEL_S  6
+/** GPIO_SIG132_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG132_IN_SEL    (BIT(7))
+#define GPIO_SIG132_IN_SEL_M  (GPIO_SIG132_IN_SEL_V << GPIO_SIG132_IN_SEL_S)
+#define GPIO_SIG132_IN_SEL_V  0x00000001U
+#define GPIO_SIG132_IN_SEL_S  7
+
+/** GPIO_FUNC133_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c)
+/** GPIO_FUNC133_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC133_IN_SEL    0x0000003FU
+#define GPIO_FUNC133_IN_SEL_M  (GPIO_FUNC133_IN_SEL_V << GPIO_FUNC133_IN_SEL_S)
+#define GPIO_FUNC133_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC133_IN_SEL_S  0
+/** GPIO_FUNC133_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC133_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC133_IN_INV_SEL_M  (GPIO_FUNC133_IN_INV_SEL_V << GPIO_FUNC133_IN_INV_SEL_S)
+#define GPIO_FUNC133_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC133_IN_INV_SEL_S  6
+/** GPIO_SIG133_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG133_IN_SEL    (BIT(7))
+#define GPIO_SIG133_IN_SEL_M  (GPIO_SIG133_IN_SEL_V << GPIO_SIG133_IN_SEL_S)
+#define GPIO_SIG133_IN_SEL_V  0x00000001U
+#define GPIO_SIG133_IN_SEL_S  7
+
+/** GPIO_FUNC134_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370)
+/** GPIO_FUNC134_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC134_IN_SEL    0x0000003FU
+#define GPIO_FUNC134_IN_SEL_M  (GPIO_FUNC134_IN_SEL_V << GPIO_FUNC134_IN_SEL_S)
+#define GPIO_FUNC134_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC134_IN_SEL_S  0
+/** GPIO_FUNC134_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC134_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC134_IN_INV_SEL_M  (GPIO_FUNC134_IN_INV_SEL_V << GPIO_FUNC134_IN_INV_SEL_S)
+#define GPIO_FUNC134_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC134_IN_INV_SEL_S  6
+/** GPIO_SIG134_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG134_IN_SEL    (BIT(7))
+#define GPIO_SIG134_IN_SEL_M  (GPIO_SIG134_IN_SEL_V << GPIO_SIG134_IN_SEL_S)
+#define GPIO_SIG134_IN_SEL_V  0x00000001U
+#define GPIO_SIG134_IN_SEL_S  7
+
+/** GPIO_FUNC135_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x374)
+/** GPIO_FUNC135_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC135_IN_SEL    0x0000003FU
+#define GPIO_FUNC135_IN_SEL_M  (GPIO_FUNC135_IN_SEL_V << GPIO_FUNC135_IN_SEL_S)
+#define GPIO_FUNC135_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC135_IN_SEL_S  0
+/** GPIO_FUNC135_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC135_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC135_IN_INV_SEL_M  (GPIO_FUNC135_IN_INV_SEL_V << GPIO_FUNC135_IN_INV_SEL_S)
+#define GPIO_FUNC135_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC135_IN_INV_SEL_S  6
+/** GPIO_SIG135_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG135_IN_SEL    (BIT(7))
+#define GPIO_SIG135_IN_SEL_M  (GPIO_SIG135_IN_SEL_V << GPIO_SIG135_IN_SEL_S)
+#define GPIO_SIG135_IN_SEL_V  0x00000001U
+#define GPIO_SIG135_IN_SEL_S  7
+
+/** GPIO_FUNC136_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378)
+/** GPIO_FUNC136_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC136_IN_SEL    0x0000003FU
+#define GPIO_FUNC136_IN_SEL_M  (GPIO_FUNC136_IN_SEL_V << GPIO_FUNC136_IN_SEL_S)
+#define GPIO_FUNC136_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC136_IN_SEL_S  0
+/** GPIO_FUNC136_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC136_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC136_IN_INV_SEL_M  (GPIO_FUNC136_IN_INV_SEL_V << GPIO_FUNC136_IN_INV_SEL_S)
+#define GPIO_FUNC136_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC136_IN_INV_SEL_S  6
+/** GPIO_SIG136_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG136_IN_SEL    (BIT(7))
+#define GPIO_SIG136_IN_SEL_M  (GPIO_SIG136_IN_SEL_V << GPIO_SIG136_IN_SEL_S)
+#define GPIO_SIG136_IN_SEL_V  0x00000001U
+#define GPIO_SIG136_IN_SEL_S  7
+
+/** GPIO_FUNC137_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c)
+/** GPIO_FUNC137_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC137_IN_SEL    0x0000003FU
+#define GPIO_FUNC137_IN_SEL_M  (GPIO_FUNC137_IN_SEL_V << GPIO_FUNC137_IN_SEL_S)
+#define GPIO_FUNC137_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC137_IN_SEL_S  0
+/** GPIO_FUNC137_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC137_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC137_IN_INV_SEL_M  (GPIO_FUNC137_IN_INV_SEL_V << GPIO_FUNC137_IN_INV_SEL_S)
+#define GPIO_FUNC137_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC137_IN_INV_SEL_S  6
+/** GPIO_SIG137_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG137_IN_SEL    (BIT(7))
+#define GPIO_SIG137_IN_SEL_M  (GPIO_SIG137_IN_SEL_V << GPIO_SIG137_IN_SEL_S)
+#define GPIO_SIG137_IN_SEL_V  0x00000001U
+#define GPIO_SIG137_IN_SEL_S  7
+
+/** GPIO_FUNC140_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x388)
+/** GPIO_FUNC140_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC140_IN_SEL    0x0000003FU
+#define GPIO_FUNC140_IN_SEL_M  (GPIO_FUNC140_IN_SEL_V << GPIO_FUNC140_IN_SEL_S)
+#define GPIO_FUNC140_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC140_IN_SEL_S  0
+/** GPIO_FUNC140_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC140_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC140_IN_INV_SEL_M  (GPIO_FUNC140_IN_INV_SEL_V << GPIO_FUNC140_IN_INV_SEL_S)
+#define GPIO_FUNC140_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC140_IN_INV_SEL_S  6
+/** GPIO_SIG140_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG140_IN_SEL    (BIT(7))
+#define GPIO_SIG140_IN_SEL_M  (GPIO_SIG140_IN_SEL_V << GPIO_SIG140_IN_SEL_S)
+#define GPIO_SIG140_IN_SEL_V  0x00000001U
+#define GPIO_SIG140_IN_SEL_S  7
+
+/** GPIO_FUNC141_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c)
+/** GPIO_FUNC141_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC141_IN_SEL    0x0000003FU
+#define GPIO_FUNC141_IN_SEL_M  (GPIO_FUNC141_IN_SEL_V << GPIO_FUNC141_IN_SEL_S)
+#define GPIO_FUNC141_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC141_IN_SEL_S  0
+/** GPIO_FUNC141_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC141_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC141_IN_INV_SEL_M  (GPIO_FUNC141_IN_INV_SEL_V << GPIO_FUNC141_IN_INV_SEL_S)
+#define GPIO_FUNC141_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC141_IN_INV_SEL_S  6
+/** GPIO_SIG141_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG141_IN_SEL    (BIT(7))
+#define GPIO_SIG141_IN_SEL_M  (GPIO_SIG141_IN_SEL_V << GPIO_SIG141_IN_SEL_S)
+#define GPIO_SIG141_IN_SEL_V  0x00000001U
+#define GPIO_SIG141_IN_SEL_S  7
+
+/** GPIO_FUNC142_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390)
+/** GPIO_FUNC142_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC142_IN_SEL    0x0000003FU
+#define GPIO_FUNC142_IN_SEL_M  (GPIO_FUNC142_IN_SEL_V << GPIO_FUNC142_IN_SEL_S)
+#define GPIO_FUNC142_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC142_IN_SEL_S  0
+/** GPIO_FUNC142_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC142_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC142_IN_INV_SEL_M  (GPIO_FUNC142_IN_INV_SEL_V << GPIO_FUNC142_IN_INV_SEL_S)
+#define GPIO_FUNC142_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC142_IN_INV_SEL_S  6
+/** GPIO_SIG142_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG142_IN_SEL    (BIT(7))
+#define GPIO_SIG142_IN_SEL_M  (GPIO_SIG142_IN_SEL_V << GPIO_SIG142_IN_SEL_S)
+#define GPIO_SIG142_IN_SEL_V  0x00000001U
+#define GPIO_SIG142_IN_SEL_S  7
+
+/** GPIO_FUNC143_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394)
+/** GPIO_FUNC143_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC143_IN_SEL    0x0000003FU
+#define GPIO_FUNC143_IN_SEL_M  (GPIO_FUNC143_IN_SEL_V << GPIO_FUNC143_IN_SEL_S)
+#define GPIO_FUNC143_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC143_IN_SEL_S  0
+/** GPIO_FUNC143_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC143_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC143_IN_INV_SEL_M  (GPIO_FUNC143_IN_INV_SEL_V << GPIO_FUNC143_IN_INV_SEL_S)
+#define GPIO_FUNC143_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC143_IN_INV_SEL_S  6
+/** GPIO_SIG143_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG143_IN_SEL    (BIT(7))
+#define GPIO_SIG143_IN_SEL_M  (GPIO_SIG143_IN_SEL_V << GPIO_SIG143_IN_SEL_S)
+#define GPIO_SIG143_IN_SEL_V  0x00000001U
+#define GPIO_SIG143_IN_SEL_S  7
+
+/** GPIO_FUNC144_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x398)
+/** GPIO_FUNC144_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC144_IN_SEL    0x0000003FU
+#define GPIO_FUNC144_IN_SEL_M  (GPIO_FUNC144_IN_SEL_V << GPIO_FUNC144_IN_SEL_S)
+#define GPIO_FUNC144_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC144_IN_SEL_S  0
+/** GPIO_FUNC144_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC144_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC144_IN_INV_SEL_M  (GPIO_FUNC144_IN_INV_SEL_V << GPIO_FUNC144_IN_INV_SEL_S)
+#define GPIO_FUNC144_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC144_IN_INV_SEL_S  6
+/** GPIO_SIG144_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG144_IN_SEL    (BIT(7))
+#define GPIO_SIG144_IN_SEL_M  (GPIO_SIG144_IN_SEL_V << GPIO_SIG144_IN_SEL_S)
+#define GPIO_SIG144_IN_SEL_V  0x00000001U
+#define GPIO_SIG144_IN_SEL_S  7
+
+/** GPIO_FUNC145_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x39c)
+/** GPIO_FUNC145_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC145_IN_SEL    0x0000003FU
+#define GPIO_FUNC145_IN_SEL_M  (GPIO_FUNC145_IN_SEL_V << GPIO_FUNC145_IN_SEL_S)
+#define GPIO_FUNC145_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC145_IN_SEL_S  0
+/** GPIO_FUNC145_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC145_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC145_IN_INV_SEL_M  (GPIO_FUNC145_IN_INV_SEL_V << GPIO_FUNC145_IN_INV_SEL_S)
+#define GPIO_FUNC145_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC145_IN_INV_SEL_S  6
+/** GPIO_SIG145_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG145_IN_SEL    (BIT(7))
+#define GPIO_SIG145_IN_SEL_M  (GPIO_SIG145_IN_SEL_V << GPIO_SIG145_IN_SEL_S)
+#define GPIO_SIG145_IN_SEL_V  0x00000001U
+#define GPIO_SIG145_IN_SEL_S  7
+
+/** GPIO_FUNC146_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a0)
+/** GPIO_FUNC146_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC146_IN_SEL    0x0000003FU
+#define GPIO_FUNC146_IN_SEL_M  (GPIO_FUNC146_IN_SEL_V << GPIO_FUNC146_IN_SEL_S)
+#define GPIO_FUNC146_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC146_IN_SEL_S  0
+/** GPIO_FUNC146_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC146_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC146_IN_INV_SEL_M  (GPIO_FUNC146_IN_INV_SEL_V << GPIO_FUNC146_IN_INV_SEL_S)
+#define GPIO_FUNC146_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC146_IN_INV_SEL_S  6
+/** GPIO_SIG146_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG146_IN_SEL    (BIT(7))
+#define GPIO_SIG146_IN_SEL_M  (GPIO_SIG146_IN_SEL_V << GPIO_SIG146_IN_SEL_S)
+#define GPIO_SIG146_IN_SEL_V  0x00000001U
+#define GPIO_SIG146_IN_SEL_S  7
+
+/** GPIO_FUNC147_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a4)
+/** GPIO_FUNC147_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC147_IN_SEL    0x0000003FU
+#define GPIO_FUNC147_IN_SEL_M  (GPIO_FUNC147_IN_SEL_V << GPIO_FUNC147_IN_SEL_S)
+#define GPIO_FUNC147_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC147_IN_SEL_S  0
+/** GPIO_FUNC147_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC147_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC147_IN_INV_SEL_M  (GPIO_FUNC147_IN_INV_SEL_V << GPIO_FUNC147_IN_INV_SEL_S)
+#define GPIO_FUNC147_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC147_IN_INV_SEL_S  6
+/** GPIO_SIG147_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG147_IN_SEL    (BIT(7))
+#define GPIO_SIG147_IN_SEL_M  (GPIO_SIG147_IN_SEL_V << GPIO_SIG147_IN_SEL_S)
+#define GPIO_SIG147_IN_SEL_V  0x00000001U
+#define GPIO_SIG147_IN_SEL_S  7
+
+/** GPIO_FUNC148_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a8)
+/** GPIO_FUNC148_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC148_IN_SEL    0x0000003FU
+#define GPIO_FUNC148_IN_SEL_M  (GPIO_FUNC148_IN_SEL_V << GPIO_FUNC148_IN_SEL_S)
+#define GPIO_FUNC148_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC148_IN_SEL_S  0
+/** GPIO_FUNC148_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC148_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC148_IN_INV_SEL_M  (GPIO_FUNC148_IN_INV_SEL_V << GPIO_FUNC148_IN_INV_SEL_S)
+#define GPIO_FUNC148_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC148_IN_INV_SEL_S  6
+/** GPIO_SIG148_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG148_IN_SEL    (BIT(7))
+#define GPIO_SIG148_IN_SEL_M  (GPIO_SIG148_IN_SEL_V << GPIO_SIG148_IN_SEL_S)
+#define GPIO_SIG148_IN_SEL_V  0x00000001U
+#define GPIO_SIG148_IN_SEL_S  7
+
+/** GPIO_FUNC149_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ac)
+/** GPIO_FUNC149_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC149_IN_SEL    0x0000003FU
+#define GPIO_FUNC149_IN_SEL_M  (GPIO_FUNC149_IN_SEL_V << GPIO_FUNC149_IN_SEL_S)
+#define GPIO_FUNC149_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC149_IN_SEL_S  0
+/** GPIO_FUNC149_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC149_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC149_IN_INV_SEL_M  (GPIO_FUNC149_IN_INV_SEL_V << GPIO_FUNC149_IN_INV_SEL_S)
+#define GPIO_FUNC149_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC149_IN_INV_SEL_S  6
+/** GPIO_SIG149_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG149_IN_SEL    (BIT(7))
+#define GPIO_SIG149_IN_SEL_M  (GPIO_SIG149_IN_SEL_V << GPIO_SIG149_IN_SEL_S)
+#define GPIO_SIG149_IN_SEL_V  0x00000001U
+#define GPIO_SIG149_IN_SEL_S  7
+
+/** GPIO_FUNC150_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b0)
+/** GPIO_FUNC150_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC150_IN_SEL    0x0000003FU
+#define GPIO_FUNC150_IN_SEL_M  (GPIO_FUNC150_IN_SEL_V << GPIO_FUNC150_IN_SEL_S)
+#define GPIO_FUNC150_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC150_IN_SEL_S  0
+/** GPIO_FUNC150_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC150_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC150_IN_INV_SEL_M  (GPIO_FUNC150_IN_INV_SEL_V << GPIO_FUNC150_IN_INV_SEL_S)
+#define GPIO_FUNC150_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC150_IN_INV_SEL_S  6
+/** GPIO_SIG150_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG150_IN_SEL    (BIT(7))
+#define GPIO_SIG150_IN_SEL_M  (GPIO_SIG150_IN_SEL_V << GPIO_SIG150_IN_SEL_S)
+#define GPIO_SIG150_IN_SEL_V  0x00000001U
+#define GPIO_SIG150_IN_SEL_S  7
+
+/** GPIO_FUNC151_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b4)
+/** GPIO_FUNC151_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC151_IN_SEL    0x0000003FU
+#define GPIO_FUNC151_IN_SEL_M  (GPIO_FUNC151_IN_SEL_V << GPIO_FUNC151_IN_SEL_S)
+#define GPIO_FUNC151_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC151_IN_SEL_S  0
+/** GPIO_FUNC151_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC151_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC151_IN_INV_SEL_M  (GPIO_FUNC151_IN_INV_SEL_V << GPIO_FUNC151_IN_INV_SEL_S)
+#define GPIO_FUNC151_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC151_IN_INV_SEL_S  6
+/** GPIO_SIG151_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG151_IN_SEL    (BIT(7))
+#define GPIO_SIG151_IN_SEL_M  (GPIO_SIG151_IN_SEL_V << GPIO_SIG151_IN_SEL_S)
+#define GPIO_SIG151_IN_SEL_V  0x00000001U
+#define GPIO_SIG151_IN_SEL_S  7
+
+/** GPIO_FUNC152_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b8)
+/** GPIO_FUNC152_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC152_IN_SEL    0x0000003FU
+#define GPIO_FUNC152_IN_SEL_M  (GPIO_FUNC152_IN_SEL_V << GPIO_FUNC152_IN_SEL_S)
+#define GPIO_FUNC152_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC152_IN_SEL_S  0
+/** GPIO_FUNC152_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC152_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC152_IN_INV_SEL_M  (GPIO_FUNC152_IN_INV_SEL_V << GPIO_FUNC152_IN_INV_SEL_S)
+#define GPIO_FUNC152_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC152_IN_INV_SEL_S  6
+/** GPIO_SIG152_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG152_IN_SEL    (BIT(7))
+#define GPIO_SIG152_IN_SEL_M  (GPIO_SIG152_IN_SEL_V << GPIO_SIG152_IN_SEL_S)
+#define GPIO_SIG152_IN_SEL_V  0x00000001U
+#define GPIO_SIG152_IN_SEL_S  7
+
+/** GPIO_FUNC153_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3bc)
+/** GPIO_FUNC153_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC153_IN_SEL    0x0000003FU
+#define GPIO_FUNC153_IN_SEL_M  (GPIO_FUNC153_IN_SEL_V << GPIO_FUNC153_IN_SEL_S)
+#define GPIO_FUNC153_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC153_IN_SEL_S  0
+/** GPIO_FUNC153_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC153_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC153_IN_INV_SEL_M  (GPIO_FUNC153_IN_INV_SEL_V << GPIO_FUNC153_IN_INV_SEL_S)
+#define GPIO_FUNC153_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC153_IN_INV_SEL_S  6
+/** GPIO_SIG153_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG153_IN_SEL    (BIT(7))
+#define GPIO_SIG153_IN_SEL_M  (GPIO_SIG153_IN_SEL_V << GPIO_SIG153_IN_SEL_S)
+#define GPIO_SIG153_IN_SEL_V  0x00000001U
+#define GPIO_SIG153_IN_SEL_S  7
+
+/** GPIO_FUNC154_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c0)
+/** GPIO_FUNC154_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC154_IN_SEL    0x0000003FU
+#define GPIO_FUNC154_IN_SEL_M  (GPIO_FUNC154_IN_SEL_V << GPIO_FUNC154_IN_SEL_S)
+#define GPIO_FUNC154_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC154_IN_SEL_S  0
+/** GPIO_FUNC154_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC154_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC154_IN_INV_SEL_M  (GPIO_FUNC154_IN_INV_SEL_V << GPIO_FUNC154_IN_INV_SEL_S)
+#define GPIO_FUNC154_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC154_IN_INV_SEL_S  6
+/** GPIO_SIG154_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG154_IN_SEL    (BIT(7))
+#define GPIO_SIG154_IN_SEL_M  (GPIO_SIG154_IN_SEL_V << GPIO_SIG154_IN_SEL_S)
+#define GPIO_SIG154_IN_SEL_V  0x00000001U
+#define GPIO_SIG154_IN_SEL_S  7
+
+/** GPIO_FUNC155_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4)
+/** GPIO_FUNC155_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC155_IN_SEL    0x0000003FU
+#define GPIO_FUNC155_IN_SEL_M  (GPIO_FUNC155_IN_SEL_V << GPIO_FUNC155_IN_SEL_S)
+#define GPIO_FUNC155_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC155_IN_SEL_S  0
+/** GPIO_FUNC155_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC155_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC155_IN_INV_SEL_M  (GPIO_FUNC155_IN_INV_SEL_V << GPIO_FUNC155_IN_INV_SEL_S)
+#define GPIO_FUNC155_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC155_IN_INV_SEL_S  6
+/** GPIO_SIG155_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG155_IN_SEL    (BIT(7))
+#define GPIO_SIG155_IN_SEL_M  (GPIO_SIG155_IN_SEL_V << GPIO_SIG155_IN_SEL_S)
+#define GPIO_SIG155_IN_SEL_V  0x00000001U
+#define GPIO_SIG155_IN_SEL_S  7
+
+/** GPIO_FUNC156_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8)
+/** GPIO_FUNC156_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC156_IN_SEL    0x0000003FU
+#define GPIO_FUNC156_IN_SEL_M  (GPIO_FUNC156_IN_SEL_V << GPIO_FUNC156_IN_SEL_S)
+#define GPIO_FUNC156_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC156_IN_SEL_S  0
+/** GPIO_FUNC156_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC156_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC156_IN_INV_SEL_M  (GPIO_FUNC156_IN_INV_SEL_V << GPIO_FUNC156_IN_INV_SEL_S)
+#define GPIO_FUNC156_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC156_IN_INV_SEL_S  6
+/** GPIO_SIG156_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG156_IN_SEL    (BIT(7))
+#define GPIO_SIG156_IN_SEL_M  (GPIO_SIG156_IN_SEL_V << GPIO_SIG156_IN_SEL_S)
+#define GPIO_SIG156_IN_SEL_V  0x00000001U
+#define GPIO_SIG156_IN_SEL_S  7
+
+/** GPIO_FUNC158_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0)
+/** GPIO_FUNC158_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC158_IN_SEL    0x0000003FU
+#define GPIO_FUNC158_IN_SEL_M  (GPIO_FUNC158_IN_SEL_V << GPIO_FUNC158_IN_SEL_S)
+#define GPIO_FUNC158_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC158_IN_SEL_S  0
+/** GPIO_FUNC158_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC158_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC158_IN_INV_SEL_M  (GPIO_FUNC158_IN_INV_SEL_V << GPIO_FUNC158_IN_INV_SEL_S)
+#define GPIO_FUNC158_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC158_IN_INV_SEL_S  6
+/** GPIO_SIG158_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG158_IN_SEL    (BIT(7))
+#define GPIO_SIG158_IN_SEL_M  (GPIO_SIG158_IN_SEL_V << GPIO_SIG158_IN_SEL_S)
+#define GPIO_SIG158_IN_SEL_V  0x00000001U
+#define GPIO_SIG158_IN_SEL_S  7
+
+/** GPIO_FUNC159_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4)
+/** GPIO_FUNC159_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC159_IN_SEL    0x0000003FU
+#define GPIO_FUNC159_IN_SEL_M  (GPIO_FUNC159_IN_SEL_V << GPIO_FUNC159_IN_SEL_S)
+#define GPIO_FUNC159_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC159_IN_SEL_S  0
+/** GPIO_FUNC159_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC159_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC159_IN_INV_SEL_M  (GPIO_FUNC159_IN_INV_SEL_V << GPIO_FUNC159_IN_INV_SEL_S)
+#define GPIO_FUNC159_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC159_IN_INV_SEL_S  6
+/** GPIO_SIG159_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG159_IN_SEL    (BIT(7))
+#define GPIO_SIG159_IN_SEL_M  (GPIO_SIG159_IN_SEL_V << GPIO_SIG159_IN_SEL_S)
+#define GPIO_SIG159_IN_SEL_V  0x00000001U
+#define GPIO_SIG159_IN_SEL_S  7
+
+/** GPIO_FUNC160_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8)
+/** GPIO_FUNC160_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC160_IN_SEL    0x0000003FU
+#define GPIO_FUNC160_IN_SEL_M  (GPIO_FUNC160_IN_SEL_V << GPIO_FUNC160_IN_SEL_S)
+#define GPIO_FUNC160_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC160_IN_SEL_S  0
+/** GPIO_FUNC160_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC160_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC160_IN_INV_SEL_M  (GPIO_FUNC160_IN_INV_SEL_V << GPIO_FUNC160_IN_INV_SEL_S)
+#define GPIO_FUNC160_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC160_IN_INV_SEL_S  6
+/** GPIO_SIG160_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG160_IN_SEL    (BIT(7))
+#define GPIO_SIG160_IN_SEL_M  (GPIO_SIG160_IN_SEL_V << GPIO_SIG160_IN_SEL_S)
+#define GPIO_SIG160_IN_SEL_V  0x00000001U
+#define GPIO_SIG160_IN_SEL_S  7
+
+/** GPIO_FUNC161_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc)
+/** GPIO_FUNC161_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC161_IN_SEL    0x0000003FU
+#define GPIO_FUNC161_IN_SEL_M  (GPIO_FUNC161_IN_SEL_V << GPIO_FUNC161_IN_SEL_S)
+#define GPIO_FUNC161_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC161_IN_SEL_S  0
+/** GPIO_FUNC161_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC161_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC161_IN_INV_SEL_M  (GPIO_FUNC161_IN_INV_SEL_V << GPIO_FUNC161_IN_INV_SEL_S)
+#define GPIO_FUNC161_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC161_IN_INV_SEL_S  6
+/** GPIO_SIG161_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG161_IN_SEL    (BIT(7))
+#define GPIO_SIG161_IN_SEL_M  (GPIO_SIG161_IN_SEL_V << GPIO_SIG161_IN_SEL_S)
+#define GPIO_SIG161_IN_SEL_V  0x00000001U
+#define GPIO_SIG161_IN_SEL_S  7
+
+/** GPIO_FUNC162_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e0)
+/** GPIO_FUNC162_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC162_IN_SEL    0x0000003FU
+#define GPIO_FUNC162_IN_SEL_M  (GPIO_FUNC162_IN_SEL_V << GPIO_FUNC162_IN_SEL_S)
+#define GPIO_FUNC162_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC162_IN_SEL_S  0
+/** GPIO_FUNC162_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC162_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC162_IN_INV_SEL_M  (GPIO_FUNC162_IN_INV_SEL_V << GPIO_FUNC162_IN_INV_SEL_S)
+#define GPIO_FUNC162_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC162_IN_INV_SEL_S  6
+/** GPIO_SIG162_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG162_IN_SEL    (BIT(7))
+#define GPIO_SIG162_IN_SEL_M  (GPIO_SIG162_IN_SEL_V << GPIO_SIG162_IN_SEL_S)
+#define GPIO_SIG162_IN_SEL_V  0x00000001U
+#define GPIO_SIG162_IN_SEL_S  7
+
+/** GPIO_FUNC163_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4)
+/** GPIO_FUNC163_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC163_IN_SEL    0x0000003FU
+#define GPIO_FUNC163_IN_SEL_M  (GPIO_FUNC163_IN_SEL_V << GPIO_FUNC163_IN_SEL_S)
+#define GPIO_FUNC163_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC163_IN_SEL_S  0
+/** GPIO_FUNC163_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC163_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC163_IN_INV_SEL_M  (GPIO_FUNC163_IN_INV_SEL_V << GPIO_FUNC163_IN_INV_SEL_S)
+#define GPIO_FUNC163_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC163_IN_INV_SEL_S  6
+/** GPIO_SIG163_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG163_IN_SEL    (BIT(7))
+#define GPIO_SIG163_IN_SEL_M  (GPIO_SIG163_IN_SEL_V << GPIO_SIG163_IN_SEL_S)
+#define GPIO_SIG163_IN_SEL_V  0x00000001U
+#define GPIO_SIG163_IN_SEL_S  7
+
+/** GPIO_FUNC164_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8)
+/** GPIO_FUNC164_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC164_IN_SEL    0x0000003FU
+#define GPIO_FUNC164_IN_SEL_M  (GPIO_FUNC164_IN_SEL_V << GPIO_FUNC164_IN_SEL_S)
+#define GPIO_FUNC164_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC164_IN_SEL_S  0
+/** GPIO_FUNC164_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC164_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC164_IN_INV_SEL_M  (GPIO_FUNC164_IN_INV_SEL_V << GPIO_FUNC164_IN_INV_SEL_S)
+#define GPIO_FUNC164_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC164_IN_INV_SEL_S  6
+/** GPIO_SIG164_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG164_IN_SEL    (BIT(7))
+#define GPIO_SIG164_IN_SEL_M  (GPIO_SIG164_IN_SEL_V << GPIO_SIG164_IN_SEL_S)
+#define GPIO_SIG164_IN_SEL_V  0x00000001U
+#define GPIO_SIG164_IN_SEL_S  7
+
+/** GPIO_FUNC165_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec)
+/** GPIO_FUNC165_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC165_IN_SEL    0x0000003FU
+#define GPIO_FUNC165_IN_SEL_M  (GPIO_FUNC165_IN_SEL_V << GPIO_FUNC165_IN_SEL_S)
+#define GPIO_FUNC165_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC165_IN_SEL_S  0
+/** GPIO_FUNC165_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC165_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC165_IN_INV_SEL_M  (GPIO_FUNC165_IN_INV_SEL_V << GPIO_FUNC165_IN_INV_SEL_S)
+#define GPIO_FUNC165_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC165_IN_INV_SEL_S  6
+/** GPIO_SIG165_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG165_IN_SEL    (BIT(7))
+#define GPIO_SIG165_IN_SEL_M  (GPIO_SIG165_IN_SEL_V << GPIO_SIG165_IN_SEL_S)
+#define GPIO_SIG165_IN_SEL_V  0x00000001U
+#define GPIO_SIG165_IN_SEL_S  7
+
+/** GPIO_FUNC166_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f0)
+/** GPIO_FUNC166_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC166_IN_SEL    0x0000003FU
+#define GPIO_FUNC166_IN_SEL_M  (GPIO_FUNC166_IN_SEL_V << GPIO_FUNC166_IN_SEL_S)
+#define GPIO_FUNC166_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC166_IN_SEL_S  0
+/** GPIO_FUNC166_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC166_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC166_IN_INV_SEL_M  (GPIO_FUNC166_IN_INV_SEL_V << GPIO_FUNC166_IN_INV_SEL_S)
+#define GPIO_FUNC166_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC166_IN_INV_SEL_S  6
+/** GPIO_SIG166_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG166_IN_SEL    (BIT(7))
+#define GPIO_SIG166_IN_SEL_M  (GPIO_SIG166_IN_SEL_V << GPIO_SIG166_IN_SEL_S)
+#define GPIO_SIG166_IN_SEL_V  0x00000001U
+#define GPIO_SIG166_IN_SEL_S  7
+
+/** GPIO_FUNC167_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4)
+/** GPIO_FUNC167_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC167_IN_SEL    0x0000003FU
+#define GPIO_FUNC167_IN_SEL_M  (GPIO_FUNC167_IN_SEL_V << GPIO_FUNC167_IN_SEL_S)
+#define GPIO_FUNC167_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC167_IN_SEL_S  0
+/** GPIO_FUNC167_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC167_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC167_IN_INV_SEL_M  (GPIO_FUNC167_IN_INV_SEL_V << GPIO_FUNC167_IN_INV_SEL_S)
+#define GPIO_FUNC167_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC167_IN_INV_SEL_S  6
+/** GPIO_SIG167_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG167_IN_SEL    (BIT(7))
+#define GPIO_SIG167_IN_SEL_M  (GPIO_SIG167_IN_SEL_V << GPIO_SIG167_IN_SEL_S)
+#define GPIO_SIG167_IN_SEL_V  0x00000001U
+#define GPIO_SIG167_IN_SEL_S  7
+
+/** GPIO_FUNC168_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8)
+/** GPIO_FUNC168_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC168_IN_SEL    0x0000003FU
+#define GPIO_FUNC168_IN_SEL_M  (GPIO_FUNC168_IN_SEL_V << GPIO_FUNC168_IN_SEL_S)
+#define GPIO_FUNC168_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC168_IN_SEL_S  0
+/** GPIO_FUNC168_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC168_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC168_IN_INV_SEL_M  (GPIO_FUNC168_IN_INV_SEL_V << GPIO_FUNC168_IN_INV_SEL_S)
+#define GPIO_FUNC168_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC168_IN_INV_SEL_S  6
+/** GPIO_SIG168_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG168_IN_SEL    (BIT(7))
+#define GPIO_SIG168_IN_SEL_M  (GPIO_SIG168_IN_SEL_V << GPIO_SIG168_IN_SEL_S)
+#define GPIO_SIG168_IN_SEL_V  0x00000001U
+#define GPIO_SIG168_IN_SEL_S  7
+
+/** GPIO_FUNC169_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc)
+/** GPIO_FUNC169_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC169_IN_SEL    0x0000003FU
+#define GPIO_FUNC169_IN_SEL_M  (GPIO_FUNC169_IN_SEL_V << GPIO_FUNC169_IN_SEL_S)
+#define GPIO_FUNC169_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC169_IN_SEL_S  0
+/** GPIO_FUNC169_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC169_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC169_IN_INV_SEL_M  (GPIO_FUNC169_IN_INV_SEL_V << GPIO_FUNC169_IN_INV_SEL_S)
+#define GPIO_FUNC169_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC169_IN_INV_SEL_S  6
+/** GPIO_SIG169_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG169_IN_SEL    (BIT(7))
+#define GPIO_SIG169_IN_SEL_M  (GPIO_SIG169_IN_SEL_V << GPIO_SIG169_IN_SEL_S)
+#define GPIO_SIG169_IN_SEL_V  0x00000001U
+#define GPIO_SIG169_IN_SEL_S  7
+
+/** GPIO_FUNC170_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x400)
+/** GPIO_FUNC170_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC170_IN_SEL    0x0000003FU
+#define GPIO_FUNC170_IN_SEL_M  (GPIO_FUNC170_IN_SEL_V << GPIO_FUNC170_IN_SEL_S)
+#define GPIO_FUNC170_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC170_IN_SEL_S  0
+/** GPIO_FUNC170_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC170_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC170_IN_INV_SEL_M  (GPIO_FUNC170_IN_INV_SEL_V << GPIO_FUNC170_IN_INV_SEL_S)
+#define GPIO_FUNC170_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC170_IN_INV_SEL_S  6
+/** GPIO_SIG170_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG170_IN_SEL    (BIT(7))
+#define GPIO_SIG170_IN_SEL_M  (GPIO_SIG170_IN_SEL_V << GPIO_SIG170_IN_SEL_S)
+#define GPIO_SIG170_IN_SEL_V  0x00000001U
+#define GPIO_SIG170_IN_SEL_S  7
+
+/** GPIO_FUNC171_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404)
+/** GPIO_FUNC171_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC171_IN_SEL    0x0000003FU
+#define GPIO_FUNC171_IN_SEL_M  (GPIO_FUNC171_IN_SEL_V << GPIO_FUNC171_IN_SEL_S)
+#define GPIO_FUNC171_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC171_IN_SEL_S  0
+/** GPIO_FUNC171_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC171_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC171_IN_INV_SEL_M  (GPIO_FUNC171_IN_INV_SEL_V << GPIO_FUNC171_IN_INV_SEL_S)
+#define GPIO_FUNC171_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC171_IN_INV_SEL_S  6
+/** GPIO_SIG171_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG171_IN_SEL    (BIT(7))
+#define GPIO_SIG171_IN_SEL_M  (GPIO_SIG171_IN_SEL_V << GPIO_SIG171_IN_SEL_S)
+#define GPIO_SIG171_IN_SEL_V  0x00000001U
+#define GPIO_SIG171_IN_SEL_S  7
+
+/** GPIO_FUNC172_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408)
+/** GPIO_FUNC172_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC172_IN_SEL    0x0000003FU
+#define GPIO_FUNC172_IN_SEL_M  (GPIO_FUNC172_IN_SEL_V << GPIO_FUNC172_IN_SEL_S)
+#define GPIO_FUNC172_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC172_IN_SEL_S  0
+/** GPIO_FUNC172_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC172_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC172_IN_INV_SEL_M  (GPIO_FUNC172_IN_INV_SEL_V << GPIO_FUNC172_IN_INV_SEL_S)
+#define GPIO_FUNC172_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC172_IN_INV_SEL_S  6
+/** GPIO_SIG172_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG172_IN_SEL    (BIT(7))
+#define GPIO_SIG172_IN_SEL_M  (GPIO_SIG172_IN_SEL_V << GPIO_SIG172_IN_SEL_S)
+#define GPIO_SIG172_IN_SEL_V  0x00000001U
+#define GPIO_SIG172_IN_SEL_S  7
+
+/** GPIO_FUNC173_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c)
+/** GPIO_FUNC173_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC173_IN_SEL    0x0000003FU
+#define GPIO_FUNC173_IN_SEL_M  (GPIO_FUNC173_IN_SEL_V << GPIO_FUNC173_IN_SEL_S)
+#define GPIO_FUNC173_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC173_IN_SEL_S  0
+/** GPIO_FUNC173_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC173_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC173_IN_INV_SEL_M  (GPIO_FUNC173_IN_INV_SEL_V << GPIO_FUNC173_IN_INV_SEL_S)
+#define GPIO_FUNC173_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC173_IN_INV_SEL_S  6
+/** GPIO_SIG173_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG173_IN_SEL    (BIT(7))
+#define GPIO_SIG173_IN_SEL_M  (GPIO_SIG173_IN_SEL_V << GPIO_SIG173_IN_SEL_S)
+#define GPIO_SIG173_IN_SEL_V  0x00000001U
+#define GPIO_SIG173_IN_SEL_S  7
+
+/** GPIO_FUNC174_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410)
+/** GPIO_FUNC174_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC174_IN_SEL    0x0000003FU
+#define GPIO_FUNC174_IN_SEL_M  (GPIO_FUNC174_IN_SEL_V << GPIO_FUNC174_IN_SEL_S)
+#define GPIO_FUNC174_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC174_IN_SEL_S  0
+/** GPIO_FUNC174_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC174_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC174_IN_INV_SEL_M  (GPIO_FUNC174_IN_INV_SEL_V << GPIO_FUNC174_IN_INV_SEL_S)
+#define GPIO_FUNC174_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC174_IN_INV_SEL_S  6
+/** GPIO_SIG174_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG174_IN_SEL    (BIT(7))
+#define GPIO_SIG174_IN_SEL_M  (GPIO_SIG174_IN_SEL_V << GPIO_SIG174_IN_SEL_S)
+#define GPIO_SIG174_IN_SEL_V  0x00000001U
+#define GPIO_SIG174_IN_SEL_S  7
+
+/** GPIO_FUNC175_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414)
+/** GPIO_FUNC175_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC175_IN_SEL    0x0000003FU
+#define GPIO_FUNC175_IN_SEL_M  (GPIO_FUNC175_IN_SEL_V << GPIO_FUNC175_IN_SEL_S)
+#define GPIO_FUNC175_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC175_IN_SEL_S  0
+/** GPIO_FUNC175_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC175_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC175_IN_INV_SEL_M  (GPIO_FUNC175_IN_INV_SEL_V << GPIO_FUNC175_IN_INV_SEL_S)
+#define GPIO_FUNC175_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC175_IN_INV_SEL_S  6
+/** GPIO_SIG175_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG175_IN_SEL    (BIT(7))
+#define GPIO_SIG175_IN_SEL_M  (GPIO_SIG175_IN_SEL_V << GPIO_SIG175_IN_SEL_S)
+#define GPIO_SIG175_IN_SEL_V  0x00000001U
+#define GPIO_SIG175_IN_SEL_S  7
+
+/** GPIO_FUNC176_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418)
+/** GPIO_FUNC176_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC176_IN_SEL    0x0000003FU
+#define GPIO_FUNC176_IN_SEL_M  (GPIO_FUNC176_IN_SEL_V << GPIO_FUNC176_IN_SEL_S)
+#define GPIO_FUNC176_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC176_IN_SEL_S  0
+/** GPIO_FUNC176_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC176_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC176_IN_INV_SEL_M  (GPIO_FUNC176_IN_INV_SEL_V << GPIO_FUNC176_IN_INV_SEL_S)
+#define GPIO_FUNC176_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC176_IN_INV_SEL_S  6
+/** GPIO_SIG176_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG176_IN_SEL    (BIT(7))
+#define GPIO_SIG176_IN_SEL_M  (GPIO_SIG176_IN_SEL_V << GPIO_SIG176_IN_SEL_S)
+#define GPIO_SIG176_IN_SEL_V  0x00000001U
+#define GPIO_SIG176_IN_SEL_S  7
+
+/** GPIO_FUNC177_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c)
+/** GPIO_FUNC177_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC177_IN_SEL    0x0000003FU
+#define GPIO_FUNC177_IN_SEL_M  (GPIO_FUNC177_IN_SEL_V << GPIO_FUNC177_IN_SEL_S)
+#define GPIO_FUNC177_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC177_IN_SEL_S  0
+/** GPIO_FUNC177_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC177_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC177_IN_INV_SEL_M  (GPIO_FUNC177_IN_INV_SEL_V << GPIO_FUNC177_IN_INV_SEL_S)
+#define GPIO_FUNC177_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC177_IN_INV_SEL_S  6
+/** GPIO_SIG177_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG177_IN_SEL    (BIT(7))
+#define GPIO_SIG177_IN_SEL_M  (GPIO_SIG177_IN_SEL_V << GPIO_SIG177_IN_SEL_S)
+#define GPIO_SIG177_IN_SEL_V  0x00000001U
+#define GPIO_SIG177_IN_SEL_S  7
+
+/** GPIO_FUNC178_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420)
+/** GPIO_FUNC178_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC178_IN_SEL    0x0000003FU
+#define GPIO_FUNC178_IN_SEL_M  (GPIO_FUNC178_IN_SEL_V << GPIO_FUNC178_IN_SEL_S)
+#define GPIO_FUNC178_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC178_IN_SEL_S  0
+/** GPIO_FUNC178_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC178_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC178_IN_INV_SEL_M  (GPIO_FUNC178_IN_INV_SEL_V << GPIO_FUNC178_IN_INV_SEL_S)
+#define GPIO_FUNC178_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC178_IN_INV_SEL_S  6
+/** GPIO_SIG178_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG178_IN_SEL    (BIT(7))
+#define GPIO_SIG178_IN_SEL_M  (GPIO_SIG178_IN_SEL_V << GPIO_SIG178_IN_SEL_S)
+#define GPIO_SIG178_IN_SEL_V  0x00000001U
+#define GPIO_SIG178_IN_SEL_S  7
+
+/** GPIO_FUNC179_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424)
+/** GPIO_FUNC179_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC179_IN_SEL    0x0000003FU
+#define GPIO_FUNC179_IN_SEL_M  (GPIO_FUNC179_IN_SEL_V << GPIO_FUNC179_IN_SEL_S)
+#define GPIO_FUNC179_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC179_IN_SEL_S  0
+/** GPIO_FUNC179_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC179_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC179_IN_INV_SEL_M  (GPIO_FUNC179_IN_INV_SEL_V << GPIO_FUNC179_IN_INV_SEL_S)
+#define GPIO_FUNC179_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC179_IN_INV_SEL_S  6
+/** GPIO_SIG179_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG179_IN_SEL    (BIT(7))
+#define GPIO_SIG179_IN_SEL_M  (GPIO_SIG179_IN_SEL_V << GPIO_SIG179_IN_SEL_S)
+#define GPIO_SIG179_IN_SEL_V  0x00000001U
+#define GPIO_SIG179_IN_SEL_S  7
+
+/** GPIO_FUNC180_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428)
+/** GPIO_FUNC180_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC180_IN_SEL    0x0000003FU
+#define GPIO_FUNC180_IN_SEL_M  (GPIO_FUNC180_IN_SEL_V << GPIO_FUNC180_IN_SEL_S)
+#define GPIO_FUNC180_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC180_IN_SEL_S  0
+/** GPIO_FUNC180_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC180_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC180_IN_INV_SEL_M  (GPIO_FUNC180_IN_INV_SEL_V << GPIO_FUNC180_IN_INV_SEL_S)
+#define GPIO_FUNC180_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC180_IN_INV_SEL_S  6
+/** GPIO_SIG180_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG180_IN_SEL    (BIT(7))
+#define GPIO_SIG180_IN_SEL_M  (GPIO_SIG180_IN_SEL_V << GPIO_SIG180_IN_SEL_S)
+#define GPIO_SIG180_IN_SEL_V  0x00000001U
+#define GPIO_SIG180_IN_SEL_S  7
+
+/** GPIO_FUNC181_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42c)
+/** GPIO_FUNC181_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC181_IN_SEL    0x0000003FU
+#define GPIO_FUNC181_IN_SEL_M  (GPIO_FUNC181_IN_SEL_V << GPIO_FUNC181_IN_SEL_S)
+#define GPIO_FUNC181_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC181_IN_SEL_S  0
+/** GPIO_FUNC181_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC181_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC181_IN_INV_SEL_M  (GPIO_FUNC181_IN_INV_SEL_V << GPIO_FUNC181_IN_INV_SEL_S)
+#define GPIO_FUNC181_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC181_IN_INV_SEL_S  6
+/** GPIO_SIG181_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG181_IN_SEL    (BIT(7))
+#define GPIO_SIG181_IN_SEL_M  (GPIO_SIG181_IN_SEL_V << GPIO_SIG181_IN_SEL_S)
+#define GPIO_SIG181_IN_SEL_V  0x00000001U
+#define GPIO_SIG181_IN_SEL_S  7
+
+/** GPIO_FUNC182_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430)
+/** GPIO_FUNC182_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC182_IN_SEL    0x0000003FU
+#define GPIO_FUNC182_IN_SEL_M  (GPIO_FUNC182_IN_SEL_V << GPIO_FUNC182_IN_SEL_S)
+#define GPIO_FUNC182_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC182_IN_SEL_S  0
+/** GPIO_FUNC182_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC182_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC182_IN_INV_SEL_M  (GPIO_FUNC182_IN_INV_SEL_V << GPIO_FUNC182_IN_INV_SEL_S)
+#define GPIO_FUNC182_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC182_IN_INV_SEL_S  6
+/** GPIO_SIG182_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG182_IN_SEL    (BIT(7))
+#define GPIO_SIG182_IN_SEL_M  (GPIO_SIG182_IN_SEL_V << GPIO_SIG182_IN_SEL_S)
+#define GPIO_SIG182_IN_SEL_V  0x00000001U
+#define GPIO_SIG182_IN_SEL_S  7
+
+/** GPIO_FUNC183_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434)
+/** GPIO_FUNC183_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC183_IN_SEL    0x0000003FU
+#define GPIO_FUNC183_IN_SEL_M  (GPIO_FUNC183_IN_SEL_V << GPIO_FUNC183_IN_SEL_S)
+#define GPIO_FUNC183_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC183_IN_SEL_S  0
+/** GPIO_FUNC183_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC183_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC183_IN_INV_SEL_M  (GPIO_FUNC183_IN_INV_SEL_V << GPIO_FUNC183_IN_INV_SEL_S)
+#define GPIO_FUNC183_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC183_IN_INV_SEL_S  6
+/** GPIO_SIG183_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG183_IN_SEL    (BIT(7))
+#define GPIO_SIG183_IN_SEL_M  (GPIO_SIG183_IN_SEL_V << GPIO_SIG183_IN_SEL_S)
+#define GPIO_SIG183_IN_SEL_V  0x00000001U
+#define GPIO_SIG183_IN_SEL_S  7
+
+/** GPIO_FUNC184_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x438)
+/** GPIO_FUNC184_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC184_IN_SEL    0x0000003FU
+#define GPIO_FUNC184_IN_SEL_M  (GPIO_FUNC184_IN_SEL_V << GPIO_FUNC184_IN_SEL_S)
+#define GPIO_FUNC184_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC184_IN_SEL_S  0
+/** GPIO_FUNC184_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC184_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC184_IN_INV_SEL_M  (GPIO_FUNC184_IN_INV_SEL_V << GPIO_FUNC184_IN_INV_SEL_S)
+#define GPIO_FUNC184_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC184_IN_INV_SEL_S  6
+/** GPIO_SIG184_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG184_IN_SEL    (BIT(7))
+#define GPIO_SIG184_IN_SEL_M  (GPIO_SIG184_IN_SEL_V << GPIO_SIG184_IN_SEL_S)
+#define GPIO_SIG184_IN_SEL_V  0x00000001U
+#define GPIO_SIG184_IN_SEL_S  7
+
+/** GPIO_FUNC185_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x43c)
+/** GPIO_FUNC185_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC185_IN_SEL    0x0000003FU
+#define GPIO_FUNC185_IN_SEL_M  (GPIO_FUNC185_IN_SEL_V << GPIO_FUNC185_IN_SEL_S)
+#define GPIO_FUNC185_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC185_IN_SEL_S  0
+/** GPIO_FUNC185_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC185_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC185_IN_INV_SEL_M  (GPIO_FUNC185_IN_INV_SEL_V << GPIO_FUNC185_IN_INV_SEL_S)
+#define GPIO_FUNC185_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC185_IN_INV_SEL_S  6
+/** GPIO_SIG185_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG185_IN_SEL    (BIT(7))
+#define GPIO_SIG185_IN_SEL_M  (GPIO_SIG185_IN_SEL_V << GPIO_SIG185_IN_SEL_S)
+#define GPIO_SIG185_IN_SEL_V  0x00000001U
+#define GPIO_SIG185_IN_SEL_S  7
+
+/** GPIO_FUNC186_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x440)
+/** GPIO_FUNC186_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC186_IN_SEL    0x0000003FU
+#define GPIO_FUNC186_IN_SEL_M  (GPIO_FUNC186_IN_SEL_V << GPIO_FUNC186_IN_SEL_S)
+#define GPIO_FUNC186_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC186_IN_SEL_S  0
+/** GPIO_FUNC186_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC186_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC186_IN_INV_SEL_M  (GPIO_FUNC186_IN_INV_SEL_V << GPIO_FUNC186_IN_INV_SEL_S)
+#define GPIO_FUNC186_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC186_IN_INV_SEL_S  6
+/** GPIO_SIG186_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG186_IN_SEL    (BIT(7))
+#define GPIO_SIG186_IN_SEL_M  (GPIO_SIG186_IN_SEL_V << GPIO_SIG186_IN_SEL_S)
+#define GPIO_SIG186_IN_SEL_V  0x00000001U
+#define GPIO_SIG186_IN_SEL_S  7
+
+/** GPIO_FUNC187_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x444)
+/** GPIO_FUNC187_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC187_IN_SEL    0x0000003FU
+#define GPIO_FUNC187_IN_SEL_M  (GPIO_FUNC187_IN_SEL_V << GPIO_FUNC187_IN_SEL_S)
+#define GPIO_FUNC187_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC187_IN_SEL_S  0
+/** GPIO_FUNC187_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC187_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC187_IN_INV_SEL_M  (GPIO_FUNC187_IN_INV_SEL_V << GPIO_FUNC187_IN_INV_SEL_S)
+#define GPIO_FUNC187_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC187_IN_INV_SEL_S  6
+/** GPIO_SIG187_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG187_IN_SEL    (BIT(7))
+#define GPIO_SIG187_IN_SEL_M  (GPIO_SIG187_IN_SEL_V << GPIO_SIG187_IN_SEL_S)
+#define GPIO_SIG187_IN_SEL_V  0x00000001U
+#define GPIO_SIG187_IN_SEL_S  7
+
+/** GPIO_FUNC188_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448)
+/** GPIO_FUNC188_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC188_IN_SEL    0x0000003FU
+#define GPIO_FUNC188_IN_SEL_M  (GPIO_FUNC188_IN_SEL_V << GPIO_FUNC188_IN_SEL_S)
+#define GPIO_FUNC188_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC188_IN_SEL_S  0
+/** GPIO_FUNC188_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC188_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC188_IN_INV_SEL_M  (GPIO_FUNC188_IN_INV_SEL_V << GPIO_FUNC188_IN_INV_SEL_S)
+#define GPIO_FUNC188_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC188_IN_INV_SEL_S  6
+/** GPIO_SIG188_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG188_IN_SEL    (BIT(7))
+#define GPIO_SIG188_IN_SEL_M  (GPIO_SIG188_IN_SEL_V << GPIO_SIG188_IN_SEL_S)
+#define GPIO_SIG188_IN_SEL_V  0x00000001U
+#define GPIO_SIG188_IN_SEL_S  7
+
+/** GPIO_FUNC189_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c)
+/** GPIO_FUNC189_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC189_IN_SEL    0x0000003FU
+#define GPIO_FUNC189_IN_SEL_M  (GPIO_FUNC189_IN_SEL_V << GPIO_FUNC189_IN_SEL_S)
+#define GPIO_FUNC189_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC189_IN_SEL_S  0
+/** GPIO_FUNC189_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC189_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC189_IN_INV_SEL_M  (GPIO_FUNC189_IN_INV_SEL_V << GPIO_FUNC189_IN_INV_SEL_S)
+#define GPIO_FUNC189_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC189_IN_INV_SEL_S  6
+/** GPIO_SIG189_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG189_IN_SEL    (BIT(7))
+#define GPIO_SIG189_IN_SEL_M  (GPIO_SIG189_IN_SEL_V << GPIO_SIG189_IN_SEL_S)
+#define GPIO_SIG189_IN_SEL_V  0x00000001U
+#define GPIO_SIG189_IN_SEL_S  7
+
+/** GPIO_FUNC190_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450)
+/** GPIO_FUNC190_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC190_IN_SEL    0x0000003FU
+#define GPIO_FUNC190_IN_SEL_M  (GPIO_FUNC190_IN_SEL_V << GPIO_FUNC190_IN_SEL_S)
+#define GPIO_FUNC190_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC190_IN_SEL_S  0
+/** GPIO_FUNC190_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC190_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC190_IN_INV_SEL_M  (GPIO_FUNC190_IN_INV_SEL_V << GPIO_FUNC190_IN_INV_SEL_S)
+#define GPIO_FUNC190_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC190_IN_INV_SEL_S  6
+/** GPIO_SIG190_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG190_IN_SEL    (BIT(7))
+#define GPIO_SIG190_IN_SEL_M  (GPIO_SIG190_IN_SEL_V << GPIO_SIG190_IN_SEL_S)
+#define GPIO_SIG190_IN_SEL_V  0x00000001U
+#define GPIO_SIG190_IN_SEL_S  7
+
+/** GPIO_FUNC191_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454)
+/** GPIO_FUNC191_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC191_IN_SEL    0x0000003FU
+#define GPIO_FUNC191_IN_SEL_M  (GPIO_FUNC191_IN_SEL_V << GPIO_FUNC191_IN_SEL_S)
+#define GPIO_FUNC191_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC191_IN_SEL_S  0
+/** GPIO_FUNC191_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC191_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC191_IN_INV_SEL_M  (GPIO_FUNC191_IN_INV_SEL_V << GPIO_FUNC191_IN_INV_SEL_S)
+#define GPIO_FUNC191_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC191_IN_INV_SEL_S  6
+/** GPIO_SIG191_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG191_IN_SEL    (BIT(7))
+#define GPIO_SIG191_IN_SEL_M  (GPIO_SIG191_IN_SEL_V << GPIO_SIG191_IN_SEL_S)
+#define GPIO_SIG191_IN_SEL_V  0x00000001U
+#define GPIO_SIG191_IN_SEL_S  7
+
+/** GPIO_FUNC192_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458)
+/** GPIO_FUNC192_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC192_IN_SEL    0x0000003FU
+#define GPIO_FUNC192_IN_SEL_M  (GPIO_FUNC192_IN_SEL_V << GPIO_FUNC192_IN_SEL_S)
+#define GPIO_FUNC192_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC192_IN_SEL_S  0
+/** GPIO_FUNC192_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC192_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC192_IN_INV_SEL_M  (GPIO_FUNC192_IN_INV_SEL_V << GPIO_FUNC192_IN_INV_SEL_S)
+#define GPIO_FUNC192_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC192_IN_INV_SEL_S  6
+/** GPIO_SIG192_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG192_IN_SEL    (BIT(7))
+#define GPIO_SIG192_IN_SEL_M  (GPIO_SIG192_IN_SEL_V << GPIO_SIG192_IN_SEL_S)
+#define GPIO_SIG192_IN_SEL_V  0x00000001U
+#define GPIO_SIG192_IN_SEL_S  7
+
+/** GPIO_FUNC193_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c)
+/** GPIO_FUNC193_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC193_IN_SEL    0x0000003FU
+#define GPIO_FUNC193_IN_SEL_M  (GPIO_FUNC193_IN_SEL_V << GPIO_FUNC193_IN_SEL_S)
+#define GPIO_FUNC193_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC193_IN_SEL_S  0
+/** GPIO_FUNC193_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC193_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC193_IN_INV_SEL_M  (GPIO_FUNC193_IN_INV_SEL_V << GPIO_FUNC193_IN_INV_SEL_S)
+#define GPIO_FUNC193_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC193_IN_INV_SEL_S  6
+/** GPIO_SIG193_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG193_IN_SEL    (BIT(7))
+#define GPIO_SIG193_IN_SEL_M  (GPIO_SIG193_IN_SEL_V << GPIO_SIG193_IN_SEL_S)
+#define GPIO_SIG193_IN_SEL_V  0x00000001U
+#define GPIO_SIG193_IN_SEL_S  7
+
+/** GPIO_FUNC194_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460)
+/** GPIO_FUNC194_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC194_IN_SEL    0x0000003FU
+#define GPIO_FUNC194_IN_SEL_M  (GPIO_FUNC194_IN_SEL_V << GPIO_FUNC194_IN_SEL_S)
+#define GPIO_FUNC194_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC194_IN_SEL_S  0
+/** GPIO_FUNC194_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC194_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC194_IN_INV_SEL_M  (GPIO_FUNC194_IN_INV_SEL_V << GPIO_FUNC194_IN_INV_SEL_S)
+#define GPIO_FUNC194_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC194_IN_INV_SEL_S  6
+/** GPIO_SIG194_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG194_IN_SEL    (BIT(7))
+#define GPIO_SIG194_IN_SEL_M  (GPIO_SIG194_IN_SEL_V << GPIO_SIG194_IN_SEL_S)
+#define GPIO_SIG194_IN_SEL_V  0x00000001U
+#define GPIO_SIG194_IN_SEL_S  7
+
+/** GPIO_FUNC195_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464)
+/** GPIO_FUNC195_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC195_IN_SEL    0x0000003FU
+#define GPIO_FUNC195_IN_SEL_M  (GPIO_FUNC195_IN_SEL_V << GPIO_FUNC195_IN_SEL_S)
+#define GPIO_FUNC195_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC195_IN_SEL_S  0
+/** GPIO_FUNC195_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC195_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC195_IN_INV_SEL_M  (GPIO_FUNC195_IN_INV_SEL_V << GPIO_FUNC195_IN_INV_SEL_S)
+#define GPIO_FUNC195_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC195_IN_INV_SEL_S  6
+/** GPIO_SIG195_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG195_IN_SEL    (BIT(7))
+#define GPIO_SIG195_IN_SEL_M  (GPIO_SIG195_IN_SEL_V << GPIO_SIG195_IN_SEL_S)
+#define GPIO_SIG195_IN_SEL_V  0x00000001U
+#define GPIO_SIG195_IN_SEL_S  7
+
+/** GPIO_FUNC196_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468)
+/** GPIO_FUNC196_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC196_IN_SEL    0x0000003FU
+#define GPIO_FUNC196_IN_SEL_M  (GPIO_FUNC196_IN_SEL_V << GPIO_FUNC196_IN_SEL_S)
+#define GPIO_FUNC196_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC196_IN_SEL_S  0
+/** GPIO_FUNC196_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC196_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC196_IN_INV_SEL_M  (GPIO_FUNC196_IN_INV_SEL_V << GPIO_FUNC196_IN_INV_SEL_S)
+#define GPIO_FUNC196_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC196_IN_INV_SEL_S  6
+/** GPIO_SIG196_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG196_IN_SEL    (BIT(7))
+#define GPIO_SIG196_IN_SEL_M  (GPIO_SIG196_IN_SEL_V << GPIO_SIG196_IN_SEL_S)
+#define GPIO_SIG196_IN_SEL_V  0x00000001U
+#define GPIO_SIG196_IN_SEL_S  7
+
+/** GPIO_FUNC197_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46c)
+/** GPIO_FUNC197_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC197_IN_SEL    0x0000003FU
+#define GPIO_FUNC197_IN_SEL_M  (GPIO_FUNC197_IN_SEL_V << GPIO_FUNC197_IN_SEL_S)
+#define GPIO_FUNC197_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC197_IN_SEL_S  0
+/** GPIO_FUNC197_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC197_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC197_IN_INV_SEL_M  (GPIO_FUNC197_IN_INV_SEL_V << GPIO_FUNC197_IN_INV_SEL_S)
+#define GPIO_FUNC197_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC197_IN_INV_SEL_S  6
+/** GPIO_SIG197_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG197_IN_SEL    (BIT(7))
+#define GPIO_SIG197_IN_SEL_M  (GPIO_SIG197_IN_SEL_V << GPIO_SIG197_IN_SEL_S)
+#define GPIO_SIG197_IN_SEL_V  0x00000001U
+#define GPIO_SIG197_IN_SEL_S  7
+
+/** GPIO_FUNC198_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470)
+/** GPIO_FUNC198_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC198_IN_SEL    0x0000003FU
+#define GPIO_FUNC198_IN_SEL_M  (GPIO_FUNC198_IN_SEL_V << GPIO_FUNC198_IN_SEL_S)
+#define GPIO_FUNC198_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC198_IN_SEL_S  0
+/** GPIO_FUNC198_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC198_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC198_IN_INV_SEL_M  (GPIO_FUNC198_IN_INV_SEL_V << GPIO_FUNC198_IN_INV_SEL_S)
+#define GPIO_FUNC198_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC198_IN_INV_SEL_S  6
+/** GPIO_SIG198_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG198_IN_SEL    (BIT(7))
+#define GPIO_SIG198_IN_SEL_M  (GPIO_SIG198_IN_SEL_V << GPIO_SIG198_IN_SEL_S)
+#define GPIO_SIG198_IN_SEL_V  0x00000001U
+#define GPIO_SIG198_IN_SEL_S  7
+
+/** GPIO_FUNC199_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474)
+/** GPIO_FUNC199_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC199_IN_SEL    0x0000003FU
+#define GPIO_FUNC199_IN_SEL_M  (GPIO_FUNC199_IN_SEL_V << GPIO_FUNC199_IN_SEL_S)
+#define GPIO_FUNC199_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC199_IN_SEL_S  0
+/** GPIO_FUNC199_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC199_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC199_IN_INV_SEL_M  (GPIO_FUNC199_IN_INV_SEL_V << GPIO_FUNC199_IN_INV_SEL_S)
+#define GPIO_FUNC199_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC199_IN_INV_SEL_S  6
+/** GPIO_SIG199_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG199_IN_SEL    (BIT(7))
+#define GPIO_SIG199_IN_SEL_M  (GPIO_SIG199_IN_SEL_V << GPIO_SIG199_IN_SEL_S)
+#define GPIO_SIG199_IN_SEL_V  0x00000001U
+#define GPIO_SIG199_IN_SEL_S  7
+
+/** GPIO_FUNC200_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478)
+/** GPIO_FUNC200_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC200_IN_SEL    0x0000003FU
+#define GPIO_FUNC200_IN_SEL_M  (GPIO_FUNC200_IN_SEL_V << GPIO_FUNC200_IN_SEL_S)
+#define GPIO_FUNC200_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC200_IN_SEL_S  0
+/** GPIO_FUNC200_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC200_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC200_IN_INV_SEL_M  (GPIO_FUNC200_IN_INV_SEL_V << GPIO_FUNC200_IN_INV_SEL_S)
+#define GPIO_FUNC200_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC200_IN_INV_SEL_S  6
+/** GPIO_SIG200_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG200_IN_SEL    (BIT(7))
+#define GPIO_SIG200_IN_SEL_M  (GPIO_SIG200_IN_SEL_V << GPIO_SIG200_IN_SEL_S)
+#define GPIO_SIG200_IN_SEL_V  0x00000001U
+#define GPIO_SIG200_IN_SEL_S  7
+
+/** GPIO_FUNC201_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47c)
+/** GPIO_FUNC201_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC201_IN_SEL    0x0000003FU
+#define GPIO_FUNC201_IN_SEL_M  (GPIO_FUNC201_IN_SEL_V << GPIO_FUNC201_IN_SEL_S)
+#define GPIO_FUNC201_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC201_IN_SEL_S  0
+/** GPIO_FUNC201_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC201_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC201_IN_INV_SEL_M  (GPIO_FUNC201_IN_INV_SEL_V << GPIO_FUNC201_IN_INV_SEL_S)
+#define GPIO_FUNC201_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC201_IN_INV_SEL_S  6
+/** GPIO_SIG201_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG201_IN_SEL    (BIT(7))
+#define GPIO_SIG201_IN_SEL_M  (GPIO_SIG201_IN_SEL_V << GPIO_SIG201_IN_SEL_S)
+#define GPIO_SIG201_IN_SEL_V  0x00000001U
+#define GPIO_SIG201_IN_SEL_S  7
+
+/** GPIO_FUNC202_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480)
+/** GPIO_FUNC202_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC202_IN_SEL    0x0000003FU
+#define GPIO_FUNC202_IN_SEL_M  (GPIO_FUNC202_IN_SEL_V << GPIO_FUNC202_IN_SEL_S)
+#define GPIO_FUNC202_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC202_IN_SEL_S  0
+/** GPIO_FUNC202_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC202_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC202_IN_INV_SEL_M  (GPIO_FUNC202_IN_INV_SEL_V << GPIO_FUNC202_IN_INV_SEL_S)
+#define GPIO_FUNC202_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC202_IN_INV_SEL_S  6
+/** GPIO_SIG202_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG202_IN_SEL    (BIT(7))
+#define GPIO_SIG202_IN_SEL_M  (GPIO_SIG202_IN_SEL_V << GPIO_SIG202_IN_SEL_S)
+#define GPIO_SIG202_IN_SEL_V  0x00000001U
+#define GPIO_SIG202_IN_SEL_S  7
+
+/** GPIO_FUNC203_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484)
+/** GPIO_FUNC203_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC203_IN_SEL    0x0000003FU
+#define GPIO_FUNC203_IN_SEL_M  (GPIO_FUNC203_IN_SEL_V << GPIO_FUNC203_IN_SEL_S)
+#define GPIO_FUNC203_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC203_IN_SEL_S  0
+/** GPIO_FUNC203_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC203_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC203_IN_INV_SEL_M  (GPIO_FUNC203_IN_INV_SEL_V << GPIO_FUNC203_IN_INV_SEL_S)
+#define GPIO_FUNC203_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC203_IN_INV_SEL_S  6
+/** GPIO_SIG203_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG203_IN_SEL    (BIT(7))
+#define GPIO_SIG203_IN_SEL_M  (GPIO_SIG203_IN_SEL_V << GPIO_SIG203_IN_SEL_S)
+#define GPIO_SIG203_IN_SEL_V  0x00000001U
+#define GPIO_SIG203_IN_SEL_S  7
+
+/** GPIO_FUNC214_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b0)
+/** GPIO_FUNC214_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC214_IN_SEL    0x0000003FU
+#define GPIO_FUNC214_IN_SEL_M  (GPIO_FUNC214_IN_SEL_V << GPIO_FUNC214_IN_SEL_S)
+#define GPIO_FUNC214_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC214_IN_SEL_S  0
+/** GPIO_FUNC214_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC214_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC214_IN_INV_SEL_M  (GPIO_FUNC214_IN_INV_SEL_V << GPIO_FUNC214_IN_INV_SEL_S)
+#define GPIO_FUNC214_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC214_IN_INV_SEL_S  6
+/** GPIO_SIG214_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG214_IN_SEL    (BIT(7))
+#define GPIO_SIG214_IN_SEL_M  (GPIO_SIG214_IN_SEL_V << GPIO_SIG214_IN_SEL_S)
+#define GPIO_SIG214_IN_SEL_V  0x00000001U
+#define GPIO_SIG214_IN_SEL_S  7
+
+/** GPIO_FUNC215_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b4)
+/** GPIO_FUNC215_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC215_IN_SEL    0x0000003FU
+#define GPIO_FUNC215_IN_SEL_M  (GPIO_FUNC215_IN_SEL_V << GPIO_FUNC215_IN_SEL_S)
+#define GPIO_FUNC215_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC215_IN_SEL_S  0
+/** GPIO_FUNC215_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC215_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC215_IN_INV_SEL_M  (GPIO_FUNC215_IN_INV_SEL_V << GPIO_FUNC215_IN_INV_SEL_S)
+#define GPIO_FUNC215_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC215_IN_INV_SEL_S  6
+/** GPIO_SIG215_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG215_IN_SEL    (BIT(7))
+#define GPIO_SIG215_IN_SEL_M  (GPIO_SIG215_IN_SEL_V << GPIO_SIG215_IN_SEL_S)
+#define GPIO_SIG215_IN_SEL_V  0x00000001U
+#define GPIO_SIG215_IN_SEL_S  7
+
+/** GPIO_FUNC216_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b8)
+/** GPIO_FUNC216_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC216_IN_SEL    0x0000003FU
+#define GPIO_FUNC216_IN_SEL_M  (GPIO_FUNC216_IN_SEL_V << GPIO_FUNC216_IN_SEL_S)
+#define GPIO_FUNC216_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC216_IN_SEL_S  0
+/** GPIO_FUNC216_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC216_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC216_IN_INV_SEL_M  (GPIO_FUNC216_IN_INV_SEL_V << GPIO_FUNC216_IN_INV_SEL_S)
+#define GPIO_FUNC216_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC216_IN_INV_SEL_S  6
+/** GPIO_SIG216_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG216_IN_SEL    (BIT(7))
+#define GPIO_SIG216_IN_SEL_M  (GPIO_SIG216_IN_SEL_V << GPIO_SIG216_IN_SEL_S)
+#define GPIO_SIG216_IN_SEL_V  0x00000001U
+#define GPIO_SIG216_IN_SEL_S  7
+
+/** GPIO_FUNC217_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4bc)
+/** GPIO_FUNC217_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC217_IN_SEL    0x0000003FU
+#define GPIO_FUNC217_IN_SEL_M  (GPIO_FUNC217_IN_SEL_V << GPIO_FUNC217_IN_SEL_S)
+#define GPIO_FUNC217_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC217_IN_SEL_S  0
+/** GPIO_FUNC217_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC217_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC217_IN_INV_SEL_M  (GPIO_FUNC217_IN_INV_SEL_V << GPIO_FUNC217_IN_INV_SEL_S)
+#define GPIO_FUNC217_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC217_IN_INV_SEL_S  6
+/** GPIO_SIG217_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG217_IN_SEL    (BIT(7))
+#define GPIO_SIG217_IN_SEL_M  (GPIO_SIG217_IN_SEL_V << GPIO_SIG217_IN_SEL_S)
+#define GPIO_SIG217_IN_SEL_V  0x00000001U
+#define GPIO_SIG217_IN_SEL_S  7
+
+/** GPIO_FUNC218_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c0)
+/** GPIO_FUNC218_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC218_IN_SEL    0x0000003FU
+#define GPIO_FUNC218_IN_SEL_M  (GPIO_FUNC218_IN_SEL_V << GPIO_FUNC218_IN_SEL_S)
+#define GPIO_FUNC218_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC218_IN_SEL_S  0
+/** GPIO_FUNC218_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC218_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC218_IN_INV_SEL_M  (GPIO_FUNC218_IN_INV_SEL_V << GPIO_FUNC218_IN_INV_SEL_S)
+#define GPIO_FUNC218_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC218_IN_INV_SEL_S  6
+/** GPIO_SIG218_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG218_IN_SEL    (BIT(7))
+#define GPIO_SIG218_IN_SEL_M  (GPIO_SIG218_IN_SEL_V << GPIO_SIG218_IN_SEL_S)
+#define GPIO_SIG218_IN_SEL_V  0x00000001U
+#define GPIO_SIG218_IN_SEL_S  7
+
+/** GPIO_FUNC219_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c4)
+/** GPIO_FUNC219_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC219_IN_SEL    0x0000003FU
+#define GPIO_FUNC219_IN_SEL_M  (GPIO_FUNC219_IN_SEL_V << GPIO_FUNC219_IN_SEL_S)
+#define GPIO_FUNC219_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC219_IN_SEL_S  0
+/** GPIO_FUNC219_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC219_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC219_IN_INV_SEL_M  (GPIO_FUNC219_IN_INV_SEL_V << GPIO_FUNC219_IN_INV_SEL_S)
+#define GPIO_FUNC219_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC219_IN_INV_SEL_S  6
+/** GPIO_SIG219_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG219_IN_SEL    (BIT(7))
+#define GPIO_SIG219_IN_SEL_M  (GPIO_SIG219_IN_SEL_V << GPIO_SIG219_IN_SEL_S)
+#define GPIO_SIG219_IN_SEL_V  0x00000001U
+#define GPIO_SIG219_IN_SEL_S  7
+
+/** GPIO_FUNC220_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c8)
+/** GPIO_FUNC220_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC220_IN_SEL    0x0000003FU
+#define GPIO_FUNC220_IN_SEL_M  (GPIO_FUNC220_IN_SEL_V << GPIO_FUNC220_IN_SEL_S)
+#define GPIO_FUNC220_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC220_IN_SEL_S  0
+/** GPIO_FUNC220_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC220_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC220_IN_INV_SEL_M  (GPIO_FUNC220_IN_INV_SEL_V << GPIO_FUNC220_IN_INV_SEL_S)
+#define GPIO_FUNC220_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC220_IN_INV_SEL_S  6
+/** GPIO_SIG220_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG220_IN_SEL    (BIT(7))
+#define GPIO_SIG220_IN_SEL_M  (GPIO_SIG220_IN_SEL_V << GPIO_SIG220_IN_SEL_S)
+#define GPIO_SIG220_IN_SEL_V  0x00000001U
+#define GPIO_SIG220_IN_SEL_S  7
+
+/** GPIO_FUNC221_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4cc)
+/** GPIO_FUNC221_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC221_IN_SEL    0x0000003FU
+#define GPIO_FUNC221_IN_SEL_M  (GPIO_FUNC221_IN_SEL_V << GPIO_FUNC221_IN_SEL_S)
+#define GPIO_FUNC221_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC221_IN_SEL_S  0
+/** GPIO_FUNC221_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC221_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC221_IN_INV_SEL_M  (GPIO_FUNC221_IN_INV_SEL_V << GPIO_FUNC221_IN_INV_SEL_S)
+#define GPIO_FUNC221_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC221_IN_INV_SEL_S  6
+/** GPIO_SIG221_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG221_IN_SEL    (BIT(7))
+#define GPIO_SIG221_IN_SEL_M  (GPIO_SIG221_IN_SEL_V << GPIO_SIG221_IN_SEL_S)
+#define GPIO_SIG221_IN_SEL_V  0x00000001U
+#define GPIO_SIG221_IN_SEL_S  7
+
+/** GPIO_FUNC222_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d0)
+/** GPIO_FUNC222_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC222_IN_SEL    0x0000003FU
+#define GPIO_FUNC222_IN_SEL_M  (GPIO_FUNC222_IN_SEL_V << GPIO_FUNC222_IN_SEL_S)
+#define GPIO_FUNC222_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC222_IN_SEL_S  0
+/** GPIO_FUNC222_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC222_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC222_IN_INV_SEL_M  (GPIO_FUNC222_IN_INV_SEL_V << GPIO_FUNC222_IN_INV_SEL_S)
+#define GPIO_FUNC222_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC222_IN_INV_SEL_S  6
+/** GPIO_SIG222_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG222_IN_SEL    (BIT(7))
+#define GPIO_SIG222_IN_SEL_M  (GPIO_SIG222_IN_SEL_V << GPIO_SIG222_IN_SEL_S)
+#define GPIO_SIG222_IN_SEL_V  0x00000001U
+#define GPIO_SIG222_IN_SEL_S  7
+
+/** GPIO_FUNC223_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d4)
+/** GPIO_FUNC223_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC223_IN_SEL    0x0000003FU
+#define GPIO_FUNC223_IN_SEL_M  (GPIO_FUNC223_IN_SEL_V << GPIO_FUNC223_IN_SEL_S)
+#define GPIO_FUNC223_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC223_IN_SEL_S  0
+/** GPIO_FUNC223_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC223_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC223_IN_INV_SEL_M  (GPIO_FUNC223_IN_INV_SEL_V << GPIO_FUNC223_IN_INV_SEL_S)
+#define GPIO_FUNC223_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC223_IN_INV_SEL_S  6
+/** GPIO_SIG223_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG223_IN_SEL    (BIT(7))
+#define GPIO_SIG223_IN_SEL_M  (GPIO_SIG223_IN_SEL_V << GPIO_SIG223_IN_SEL_S)
+#define GPIO_SIG223_IN_SEL_V  0x00000001U
+#define GPIO_SIG223_IN_SEL_S  7
+
+/** GPIO_FUNC224_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d8)
+/** GPIO_FUNC224_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC224_IN_SEL    0x0000003FU
+#define GPIO_FUNC224_IN_SEL_M  (GPIO_FUNC224_IN_SEL_V << GPIO_FUNC224_IN_SEL_S)
+#define GPIO_FUNC224_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC224_IN_SEL_S  0
+/** GPIO_FUNC224_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC224_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC224_IN_INV_SEL_M  (GPIO_FUNC224_IN_INV_SEL_V << GPIO_FUNC224_IN_INV_SEL_S)
+#define GPIO_FUNC224_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC224_IN_INV_SEL_S  6
+/** GPIO_SIG224_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG224_IN_SEL    (BIT(7))
+#define GPIO_SIG224_IN_SEL_M  (GPIO_SIG224_IN_SEL_V << GPIO_SIG224_IN_SEL_S)
+#define GPIO_SIG224_IN_SEL_V  0x00000001U
+#define GPIO_SIG224_IN_SEL_S  7
+
+/** GPIO_FUNC225_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4dc)
+/** GPIO_FUNC225_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC225_IN_SEL    0x0000003FU
+#define GPIO_FUNC225_IN_SEL_M  (GPIO_FUNC225_IN_SEL_V << GPIO_FUNC225_IN_SEL_S)
+#define GPIO_FUNC225_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC225_IN_SEL_S  0
+/** GPIO_FUNC225_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC225_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC225_IN_INV_SEL_M  (GPIO_FUNC225_IN_INV_SEL_V << GPIO_FUNC225_IN_INV_SEL_S)
+#define GPIO_FUNC225_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC225_IN_INV_SEL_S  6
+/** GPIO_SIG225_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG225_IN_SEL    (BIT(7))
+#define GPIO_SIG225_IN_SEL_M  (GPIO_SIG225_IN_SEL_V << GPIO_SIG225_IN_SEL_S)
+#define GPIO_SIG225_IN_SEL_V  0x00000001U
+#define GPIO_SIG225_IN_SEL_S  7
+
+/** GPIO_FUNC226_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e0)
+/** GPIO_FUNC226_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC226_IN_SEL    0x0000003FU
+#define GPIO_FUNC226_IN_SEL_M  (GPIO_FUNC226_IN_SEL_V << GPIO_FUNC226_IN_SEL_S)
+#define GPIO_FUNC226_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC226_IN_SEL_S  0
+/** GPIO_FUNC226_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC226_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC226_IN_INV_SEL_M  (GPIO_FUNC226_IN_INV_SEL_V << GPIO_FUNC226_IN_INV_SEL_S)
+#define GPIO_FUNC226_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC226_IN_INV_SEL_S  6
+/** GPIO_SIG226_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG226_IN_SEL    (BIT(7))
+#define GPIO_SIG226_IN_SEL_M  (GPIO_SIG226_IN_SEL_V << GPIO_SIG226_IN_SEL_S)
+#define GPIO_SIG226_IN_SEL_V  0x00000001U
+#define GPIO_SIG226_IN_SEL_S  7
+
+/** GPIO_FUNC227_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e4)
+/** GPIO_FUNC227_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC227_IN_SEL    0x0000003FU
+#define GPIO_FUNC227_IN_SEL_M  (GPIO_FUNC227_IN_SEL_V << GPIO_FUNC227_IN_SEL_S)
+#define GPIO_FUNC227_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC227_IN_SEL_S  0
+/** GPIO_FUNC227_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC227_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC227_IN_INV_SEL_M  (GPIO_FUNC227_IN_INV_SEL_V << GPIO_FUNC227_IN_INV_SEL_S)
+#define GPIO_FUNC227_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC227_IN_INV_SEL_S  6
+/** GPIO_SIG227_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG227_IN_SEL    (BIT(7))
+#define GPIO_SIG227_IN_SEL_M  (GPIO_SIG227_IN_SEL_V << GPIO_SIG227_IN_SEL_S)
+#define GPIO_SIG227_IN_SEL_V  0x00000001U
+#define GPIO_SIG227_IN_SEL_S  7
+
+/** GPIO_FUNC228_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e8)
+/** GPIO_FUNC228_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC228_IN_SEL    0x0000003FU
+#define GPIO_FUNC228_IN_SEL_M  (GPIO_FUNC228_IN_SEL_V << GPIO_FUNC228_IN_SEL_S)
+#define GPIO_FUNC228_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC228_IN_SEL_S  0
+/** GPIO_FUNC228_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC228_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC228_IN_INV_SEL_M  (GPIO_FUNC228_IN_INV_SEL_V << GPIO_FUNC228_IN_INV_SEL_S)
+#define GPIO_FUNC228_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC228_IN_INV_SEL_S  6
+/** GPIO_SIG228_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG228_IN_SEL    (BIT(7))
+#define GPIO_SIG228_IN_SEL_M  (GPIO_SIG228_IN_SEL_V << GPIO_SIG228_IN_SEL_S)
+#define GPIO_SIG228_IN_SEL_V  0x00000001U
+#define GPIO_SIG228_IN_SEL_S  7
+
+/** GPIO_FUNC229_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ec)
+/** GPIO_FUNC229_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC229_IN_SEL    0x0000003FU
+#define GPIO_FUNC229_IN_SEL_M  (GPIO_FUNC229_IN_SEL_V << GPIO_FUNC229_IN_SEL_S)
+#define GPIO_FUNC229_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC229_IN_SEL_S  0
+/** GPIO_FUNC229_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC229_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC229_IN_INV_SEL_M  (GPIO_FUNC229_IN_INV_SEL_V << GPIO_FUNC229_IN_INV_SEL_S)
+#define GPIO_FUNC229_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC229_IN_INV_SEL_S  6
+/** GPIO_SIG229_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG229_IN_SEL    (BIT(7))
+#define GPIO_SIG229_IN_SEL_M  (GPIO_SIG229_IN_SEL_V << GPIO_SIG229_IN_SEL_S)
+#define GPIO_SIG229_IN_SEL_V  0x00000001U
+#define GPIO_SIG229_IN_SEL_S  7
+
+/** GPIO_FUNC230_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f0)
+/** GPIO_FUNC230_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC230_IN_SEL    0x0000003FU
+#define GPIO_FUNC230_IN_SEL_M  (GPIO_FUNC230_IN_SEL_V << GPIO_FUNC230_IN_SEL_S)
+#define GPIO_FUNC230_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC230_IN_SEL_S  0
+/** GPIO_FUNC230_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC230_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC230_IN_INV_SEL_M  (GPIO_FUNC230_IN_INV_SEL_V << GPIO_FUNC230_IN_INV_SEL_S)
+#define GPIO_FUNC230_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC230_IN_INV_SEL_S  6
+/** GPIO_SIG230_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG230_IN_SEL    (BIT(7))
+#define GPIO_SIG230_IN_SEL_M  (GPIO_SIG230_IN_SEL_V << GPIO_SIG230_IN_SEL_S)
+#define GPIO_SIG230_IN_SEL_V  0x00000001U
+#define GPIO_SIG230_IN_SEL_S  7
+
+/** GPIO_FUNC231_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f4)
+/** GPIO_FUNC231_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC231_IN_SEL    0x0000003FU
+#define GPIO_FUNC231_IN_SEL_M  (GPIO_FUNC231_IN_SEL_V << GPIO_FUNC231_IN_SEL_S)
+#define GPIO_FUNC231_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC231_IN_SEL_S  0
+/** GPIO_FUNC231_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC231_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC231_IN_INV_SEL_M  (GPIO_FUNC231_IN_INV_SEL_V << GPIO_FUNC231_IN_INV_SEL_S)
+#define GPIO_FUNC231_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC231_IN_INV_SEL_S  6
+/** GPIO_SIG231_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG231_IN_SEL    (BIT(7))
+#define GPIO_SIG231_IN_SEL_M  (GPIO_SIG231_IN_SEL_V << GPIO_SIG231_IN_SEL_S)
+#define GPIO_SIG231_IN_SEL_V  0x00000001U
+#define GPIO_SIG231_IN_SEL_S  7
+
+/** GPIO_FUNC232_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f8)
+/** GPIO_FUNC232_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC232_IN_SEL    0x0000003FU
+#define GPIO_FUNC232_IN_SEL_M  (GPIO_FUNC232_IN_SEL_V << GPIO_FUNC232_IN_SEL_S)
+#define GPIO_FUNC232_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC232_IN_SEL_S  0
+/** GPIO_FUNC232_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC232_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC232_IN_INV_SEL_M  (GPIO_FUNC232_IN_INV_SEL_V << GPIO_FUNC232_IN_INV_SEL_S)
+#define GPIO_FUNC232_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC232_IN_INV_SEL_S  6
+/** GPIO_SIG232_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG232_IN_SEL    (BIT(7))
+#define GPIO_SIG232_IN_SEL_M  (GPIO_SIG232_IN_SEL_V << GPIO_SIG232_IN_SEL_S)
+#define GPIO_SIG232_IN_SEL_V  0x00000001U
+#define GPIO_SIG232_IN_SEL_S  7
+
+/** GPIO_FUNC233_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4fc)
+/** GPIO_FUNC233_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC233_IN_SEL    0x0000003FU
+#define GPIO_FUNC233_IN_SEL_M  (GPIO_FUNC233_IN_SEL_V << GPIO_FUNC233_IN_SEL_S)
+#define GPIO_FUNC233_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC233_IN_SEL_S  0
+/** GPIO_FUNC233_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC233_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC233_IN_INV_SEL_M  (GPIO_FUNC233_IN_INV_SEL_V << GPIO_FUNC233_IN_INV_SEL_S)
+#define GPIO_FUNC233_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC233_IN_INV_SEL_S  6
+/** GPIO_SIG233_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG233_IN_SEL    (BIT(7))
+#define GPIO_SIG233_IN_SEL_M  (GPIO_SIG233_IN_SEL_V << GPIO_SIG233_IN_SEL_S)
+#define GPIO_SIG233_IN_SEL_V  0x00000001U
+#define GPIO_SIG233_IN_SEL_S  7
+
+/** GPIO_FUNC234_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x500)
+/** GPIO_FUNC234_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC234_IN_SEL    0x0000003FU
+#define GPIO_FUNC234_IN_SEL_M  (GPIO_FUNC234_IN_SEL_V << GPIO_FUNC234_IN_SEL_S)
+#define GPIO_FUNC234_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC234_IN_SEL_S  0
+/** GPIO_FUNC234_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC234_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC234_IN_INV_SEL_M  (GPIO_FUNC234_IN_INV_SEL_V << GPIO_FUNC234_IN_INV_SEL_S)
+#define GPIO_FUNC234_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC234_IN_INV_SEL_S  6
+/** GPIO_SIG234_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG234_IN_SEL    (BIT(7))
+#define GPIO_SIG234_IN_SEL_M  (GPIO_SIG234_IN_SEL_V << GPIO_SIG234_IN_SEL_S)
+#define GPIO_SIG234_IN_SEL_V  0x00000001U
+#define GPIO_SIG234_IN_SEL_S  7
+
+/** GPIO_FUNC235_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x504)
+/** GPIO_FUNC235_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC235_IN_SEL    0x0000003FU
+#define GPIO_FUNC235_IN_SEL_M  (GPIO_FUNC235_IN_SEL_V << GPIO_FUNC235_IN_SEL_S)
+#define GPIO_FUNC235_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC235_IN_SEL_S  0
+/** GPIO_FUNC235_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC235_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC235_IN_INV_SEL_M  (GPIO_FUNC235_IN_INV_SEL_V << GPIO_FUNC235_IN_INV_SEL_S)
+#define GPIO_FUNC235_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC235_IN_INV_SEL_S  6
+/** GPIO_SIG235_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG235_IN_SEL    (BIT(7))
+#define GPIO_SIG235_IN_SEL_M  (GPIO_SIG235_IN_SEL_V << GPIO_SIG235_IN_SEL_S)
+#define GPIO_SIG235_IN_SEL_V  0x00000001U
+#define GPIO_SIG235_IN_SEL_S  7
+
+/** GPIO_FUNC236_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x508)
+/** GPIO_FUNC236_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC236_IN_SEL    0x0000003FU
+#define GPIO_FUNC236_IN_SEL_M  (GPIO_FUNC236_IN_SEL_V << GPIO_FUNC236_IN_SEL_S)
+#define GPIO_FUNC236_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC236_IN_SEL_S  0
+/** GPIO_FUNC236_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC236_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC236_IN_INV_SEL_M  (GPIO_FUNC236_IN_INV_SEL_V << GPIO_FUNC236_IN_INV_SEL_S)
+#define GPIO_FUNC236_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC236_IN_INV_SEL_S  6
+/** GPIO_SIG236_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG236_IN_SEL    (BIT(7))
+#define GPIO_SIG236_IN_SEL_M  (GPIO_SIG236_IN_SEL_V << GPIO_SIG236_IN_SEL_S)
+#define GPIO_SIG236_IN_SEL_V  0x00000001U
+#define GPIO_SIG236_IN_SEL_S  7
+
+/** GPIO_FUNC237_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x50c)
+/** GPIO_FUNC237_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC237_IN_SEL    0x0000003FU
+#define GPIO_FUNC237_IN_SEL_M  (GPIO_FUNC237_IN_SEL_V << GPIO_FUNC237_IN_SEL_S)
+#define GPIO_FUNC237_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC237_IN_SEL_S  0
+/** GPIO_FUNC237_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC237_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC237_IN_INV_SEL_M  (GPIO_FUNC237_IN_INV_SEL_V << GPIO_FUNC237_IN_INV_SEL_S)
+#define GPIO_FUNC237_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC237_IN_INV_SEL_S  6
+/** GPIO_SIG237_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG237_IN_SEL    (BIT(7))
+#define GPIO_SIG237_IN_SEL_M  (GPIO_SIG237_IN_SEL_V << GPIO_SIG237_IN_SEL_S)
+#define GPIO_SIG237_IN_SEL_V  0x00000001U
+#define GPIO_SIG237_IN_SEL_S  7
+
+/** GPIO_FUNC238_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x510)
+/** GPIO_FUNC238_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC238_IN_SEL    0x0000003FU
+#define GPIO_FUNC238_IN_SEL_M  (GPIO_FUNC238_IN_SEL_V << GPIO_FUNC238_IN_SEL_S)
+#define GPIO_FUNC238_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC238_IN_SEL_S  0
+/** GPIO_FUNC238_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC238_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC238_IN_INV_SEL_M  (GPIO_FUNC238_IN_INV_SEL_V << GPIO_FUNC238_IN_INV_SEL_S)
+#define GPIO_FUNC238_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC238_IN_INV_SEL_S  6
+/** GPIO_SIG238_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG238_IN_SEL    (BIT(7))
+#define GPIO_SIG238_IN_SEL_M  (GPIO_SIG238_IN_SEL_V << GPIO_SIG238_IN_SEL_S)
+#define GPIO_SIG238_IN_SEL_V  0x00000001U
+#define GPIO_SIG238_IN_SEL_S  7
+
+/** GPIO_FUNC239_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x514)
+/** GPIO_FUNC239_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC239_IN_SEL    0x0000003FU
+#define GPIO_FUNC239_IN_SEL_M  (GPIO_FUNC239_IN_SEL_V << GPIO_FUNC239_IN_SEL_S)
+#define GPIO_FUNC239_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC239_IN_SEL_S  0
+/** GPIO_FUNC239_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC239_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC239_IN_INV_SEL_M  (GPIO_FUNC239_IN_INV_SEL_V << GPIO_FUNC239_IN_INV_SEL_S)
+#define GPIO_FUNC239_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC239_IN_INV_SEL_S  6
+/** GPIO_SIG239_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG239_IN_SEL    (BIT(7))
+#define GPIO_SIG239_IN_SEL_M  (GPIO_SIG239_IN_SEL_V << GPIO_SIG239_IN_SEL_S)
+#define GPIO_SIG239_IN_SEL_V  0x00000001U
+#define GPIO_SIG239_IN_SEL_S  7
+
+/** GPIO_FUNC240_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x518)
+/** GPIO_FUNC240_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC240_IN_SEL    0x0000003FU
+#define GPIO_FUNC240_IN_SEL_M  (GPIO_FUNC240_IN_SEL_V << GPIO_FUNC240_IN_SEL_S)
+#define GPIO_FUNC240_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC240_IN_SEL_S  0
+/** GPIO_FUNC240_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC240_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC240_IN_INV_SEL_M  (GPIO_FUNC240_IN_INV_SEL_V << GPIO_FUNC240_IN_INV_SEL_S)
+#define GPIO_FUNC240_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC240_IN_INV_SEL_S  6
+/** GPIO_SIG240_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG240_IN_SEL    (BIT(7))
+#define GPIO_SIG240_IN_SEL_M  (GPIO_SIG240_IN_SEL_V << GPIO_SIG240_IN_SEL_S)
+#define GPIO_SIG240_IN_SEL_V  0x00000001U
+#define GPIO_SIG240_IN_SEL_S  7
+
+/** GPIO_FUNC241_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x51c)
+/** GPIO_FUNC241_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC241_IN_SEL    0x0000003FU
+#define GPIO_FUNC241_IN_SEL_M  (GPIO_FUNC241_IN_SEL_V << GPIO_FUNC241_IN_SEL_S)
+#define GPIO_FUNC241_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC241_IN_SEL_S  0
+/** GPIO_FUNC241_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC241_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC241_IN_INV_SEL_M  (GPIO_FUNC241_IN_INV_SEL_V << GPIO_FUNC241_IN_INV_SEL_S)
+#define GPIO_FUNC241_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC241_IN_INV_SEL_S  6
+/** GPIO_SIG241_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG241_IN_SEL    (BIT(7))
+#define GPIO_SIG241_IN_SEL_M  (GPIO_SIG241_IN_SEL_V << GPIO_SIG241_IN_SEL_S)
+#define GPIO_SIG241_IN_SEL_V  0x00000001U
+#define GPIO_SIG241_IN_SEL_S  7
+
+/** GPIO_FUNC242_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x520)
+/** GPIO_FUNC242_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC242_IN_SEL    0x0000003FU
+#define GPIO_FUNC242_IN_SEL_M  (GPIO_FUNC242_IN_SEL_V << GPIO_FUNC242_IN_SEL_S)
+#define GPIO_FUNC242_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC242_IN_SEL_S  0
+/** GPIO_FUNC242_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC242_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC242_IN_INV_SEL_M  (GPIO_FUNC242_IN_INV_SEL_V << GPIO_FUNC242_IN_INV_SEL_S)
+#define GPIO_FUNC242_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC242_IN_INV_SEL_S  6
+/** GPIO_SIG242_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG242_IN_SEL    (BIT(7))
+#define GPIO_SIG242_IN_SEL_M  (GPIO_SIG242_IN_SEL_V << GPIO_SIG242_IN_SEL_S)
+#define GPIO_SIG242_IN_SEL_V  0x00000001U
+#define GPIO_SIG242_IN_SEL_S  7
+
+/** GPIO_FUNC243_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x524)
+/** GPIO_FUNC243_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC243_IN_SEL    0x0000003FU
+#define GPIO_FUNC243_IN_SEL_M  (GPIO_FUNC243_IN_SEL_V << GPIO_FUNC243_IN_SEL_S)
+#define GPIO_FUNC243_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC243_IN_SEL_S  0
+/** GPIO_FUNC243_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC243_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC243_IN_INV_SEL_M  (GPIO_FUNC243_IN_INV_SEL_V << GPIO_FUNC243_IN_INV_SEL_S)
+#define GPIO_FUNC243_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC243_IN_INV_SEL_S  6
+/** GPIO_SIG243_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG243_IN_SEL    (BIT(7))
+#define GPIO_SIG243_IN_SEL_M  (GPIO_SIG243_IN_SEL_V << GPIO_SIG243_IN_SEL_S)
+#define GPIO_SIG243_IN_SEL_V  0x00000001U
+#define GPIO_SIG243_IN_SEL_S  7
+
+/** GPIO_FUNC244_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x528)
+/** GPIO_FUNC244_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC244_IN_SEL    0x0000003FU
+#define GPIO_FUNC244_IN_SEL_M  (GPIO_FUNC244_IN_SEL_V << GPIO_FUNC244_IN_SEL_S)
+#define GPIO_FUNC244_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC244_IN_SEL_S  0
+/** GPIO_FUNC244_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC244_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC244_IN_INV_SEL_M  (GPIO_FUNC244_IN_INV_SEL_V << GPIO_FUNC244_IN_INV_SEL_S)
+#define GPIO_FUNC244_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC244_IN_INV_SEL_S  6
+/** GPIO_SIG244_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG244_IN_SEL    (BIT(7))
+#define GPIO_SIG244_IN_SEL_M  (GPIO_SIG244_IN_SEL_V << GPIO_SIG244_IN_SEL_S)
+#define GPIO_SIG244_IN_SEL_V  0x00000001U
+#define GPIO_SIG244_IN_SEL_S  7
+
+/** GPIO_FUNC245_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x52c)
+/** GPIO_FUNC245_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC245_IN_SEL    0x0000003FU
+#define GPIO_FUNC245_IN_SEL_M  (GPIO_FUNC245_IN_SEL_V << GPIO_FUNC245_IN_SEL_S)
+#define GPIO_FUNC245_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC245_IN_SEL_S  0
+/** GPIO_FUNC245_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC245_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC245_IN_INV_SEL_M  (GPIO_FUNC245_IN_INV_SEL_V << GPIO_FUNC245_IN_INV_SEL_S)
+#define GPIO_FUNC245_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC245_IN_INV_SEL_S  6
+/** GPIO_SIG245_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG245_IN_SEL    (BIT(7))
+#define GPIO_SIG245_IN_SEL_M  (GPIO_SIG245_IN_SEL_V << GPIO_SIG245_IN_SEL_S)
+#define GPIO_SIG245_IN_SEL_V  0x00000001U
+#define GPIO_SIG245_IN_SEL_S  7
+
+/** GPIO_FUNC246_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x530)
+/** GPIO_FUNC246_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC246_IN_SEL    0x0000003FU
+#define GPIO_FUNC246_IN_SEL_M  (GPIO_FUNC246_IN_SEL_V << GPIO_FUNC246_IN_SEL_S)
+#define GPIO_FUNC246_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC246_IN_SEL_S  0
+/** GPIO_FUNC246_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC246_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC246_IN_INV_SEL_M  (GPIO_FUNC246_IN_INV_SEL_V << GPIO_FUNC246_IN_INV_SEL_S)
+#define GPIO_FUNC246_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC246_IN_INV_SEL_S  6
+/** GPIO_SIG246_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG246_IN_SEL    (BIT(7))
+#define GPIO_SIG246_IN_SEL_M  (GPIO_SIG246_IN_SEL_V << GPIO_SIG246_IN_SEL_S)
+#define GPIO_SIG246_IN_SEL_V  0x00000001U
+#define GPIO_SIG246_IN_SEL_S  7
+
+/** GPIO_FUNC247_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x534)
+/** GPIO_FUNC247_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC247_IN_SEL    0x0000003FU
+#define GPIO_FUNC247_IN_SEL_M  (GPIO_FUNC247_IN_SEL_V << GPIO_FUNC247_IN_SEL_S)
+#define GPIO_FUNC247_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC247_IN_SEL_S  0
+/** GPIO_FUNC247_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC247_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC247_IN_INV_SEL_M  (GPIO_FUNC247_IN_INV_SEL_V << GPIO_FUNC247_IN_INV_SEL_S)
+#define GPIO_FUNC247_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC247_IN_INV_SEL_S  6
+/** GPIO_SIG247_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG247_IN_SEL    (BIT(7))
+#define GPIO_SIG247_IN_SEL_M  (GPIO_SIG247_IN_SEL_V << GPIO_SIG247_IN_SEL_S)
+#define GPIO_SIG247_IN_SEL_V  0x00000001U
+#define GPIO_SIG247_IN_SEL_S  7
+
+/** GPIO_FUNC248_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x538)
+/** GPIO_FUNC248_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC248_IN_SEL    0x0000003FU
+#define GPIO_FUNC248_IN_SEL_M  (GPIO_FUNC248_IN_SEL_V << GPIO_FUNC248_IN_SEL_S)
+#define GPIO_FUNC248_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC248_IN_SEL_S  0
+/** GPIO_FUNC248_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC248_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC248_IN_INV_SEL_M  (GPIO_FUNC248_IN_INV_SEL_V << GPIO_FUNC248_IN_INV_SEL_S)
+#define GPIO_FUNC248_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC248_IN_INV_SEL_S  6
+/** GPIO_SIG248_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG248_IN_SEL    (BIT(7))
+#define GPIO_SIG248_IN_SEL_M  (GPIO_SIG248_IN_SEL_V << GPIO_SIG248_IN_SEL_S)
+#define GPIO_SIG248_IN_SEL_V  0x00000001U
+#define GPIO_SIG248_IN_SEL_S  7
+
+/** GPIO_FUNC249_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x53c)
+/** GPIO_FUNC249_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC249_IN_SEL    0x0000003FU
+#define GPIO_FUNC249_IN_SEL_M  (GPIO_FUNC249_IN_SEL_V << GPIO_FUNC249_IN_SEL_S)
+#define GPIO_FUNC249_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC249_IN_SEL_S  0
+/** GPIO_FUNC249_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC249_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC249_IN_INV_SEL_M  (GPIO_FUNC249_IN_INV_SEL_V << GPIO_FUNC249_IN_INV_SEL_S)
+#define GPIO_FUNC249_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC249_IN_INV_SEL_S  6
+/** GPIO_SIG249_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG249_IN_SEL    (BIT(7))
+#define GPIO_SIG249_IN_SEL_M  (GPIO_SIG249_IN_SEL_V << GPIO_SIG249_IN_SEL_S)
+#define GPIO_SIG249_IN_SEL_V  0x00000001U
+#define GPIO_SIG249_IN_SEL_S  7
+
+/** GPIO_FUNC250_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x540)
+/** GPIO_FUNC250_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC250_IN_SEL    0x0000003FU
+#define GPIO_FUNC250_IN_SEL_M  (GPIO_FUNC250_IN_SEL_V << GPIO_FUNC250_IN_SEL_S)
+#define GPIO_FUNC250_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC250_IN_SEL_S  0
+/** GPIO_FUNC250_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC250_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC250_IN_INV_SEL_M  (GPIO_FUNC250_IN_INV_SEL_V << GPIO_FUNC250_IN_INV_SEL_S)
+#define GPIO_FUNC250_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC250_IN_INV_SEL_S  6
+/** GPIO_SIG250_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG250_IN_SEL    (BIT(7))
+#define GPIO_SIG250_IN_SEL_M  (GPIO_SIG250_IN_SEL_V << GPIO_SIG250_IN_SEL_S)
+#define GPIO_SIG250_IN_SEL_V  0x00000001U
+#define GPIO_SIG250_IN_SEL_S  7
+
+/** GPIO_FUNC251_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x544)
+/** GPIO_FUNC251_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC251_IN_SEL    0x0000003FU
+#define GPIO_FUNC251_IN_SEL_M  (GPIO_FUNC251_IN_SEL_V << GPIO_FUNC251_IN_SEL_S)
+#define GPIO_FUNC251_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC251_IN_SEL_S  0
+/** GPIO_FUNC251_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC251_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC251_IN_INV_SEL_M  (GPIO_FUNC251_IN_INV_SEL_V << GPIO_FUNC251_IN_INV_SEL_S)
+#define GPIO_FUNC251_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC251_IN_INV_SEL_S  6
+/** GPIO_SIG251_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG251_IN_SEL    (BIT(7))
+#define GPIO_SIG251_IN_SEL_M  (GPIO_SIG251_IN_SEL_V << GPIO_SIG251_IN_SEL_S)
+#define GPIO_SIG251_IN_SEL_V  0x00000001U
+#define GPIO_SIG251_IN_SEL_S  7
+
+/** GPIO_FUNC252_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x548)
+/** GPIO_FUNC252_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC252_IN_SEL    0x0000003FU
+#define GPIO_FUNC252_IN_SEL_M  (GPIO_FUNC252_IN_SEL_V << GPIO_FUNC252_IN_SEL_S)
+#define GPIO_FUNC252_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC252_IN_SEL_S  0
+/** GPIO_FUNC252_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC252_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC252_IN_INV_SEL_M  (GPIO_FUNC252_IN_INV_SEL_V << GPIO_FUNC252_IN_INV_SEL_S)
+#define GPIO_FUNC252_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC252_IN_INV_SEL_S  6
+/** GPIO_SIG252_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG252_IN_SEL    (BIT(7))
+#define GPIO_SIG252_IN_SEL_M  (GPIO_SIG252_IN_SEL_V << GPIO_SIG252_IN_SEL_S)
+#define GPIO_SIG252_IN_SEL_V  0x00000001U
+#define GPIO_SIG252_IN_SEL_S  7
+
+/** GPIO_FUNC253_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x54c)
+/** GPIO_FUNC253_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC253_IN_SEL    0x0000003FU
+#define GPIO_FUNC253_IN_SEL_M  (GPIO_FUNC253_IN_SEL_V << GPIO_FUNC253_IN_SEL_S)
+#define GPIO_FUNC253_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC253_IN_SEL_S  0
+/** GPIO_FUNC253_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC253_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC253_IN_INV_SEL_M  (GPIO_FUNC253_IN_INV_SEL_V << GPIO_FUNC253_IN_INV_SEL_S)
+#define GPIO_FUNC253_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC253_IN_INV_SEL_S  6
+/** GPIO_SIG253_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG253_IN_SEL    (BIT(7))
+#define GPIO_SIG253_IN_SEL_M  (GPIO_SIG253_IN_SEL_V << GPIO_SIG253_IN_SEL_S)
+#define GPIO_SIG253_IN_SEL_V  0x00000001U
+#define GPIO_SIG253_IN_SEL_S  7
+
+/** GPIO_FUNC254_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x550)
+/** GPIO_FUNC254_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC254_IN_SEL    0x0000003FU
+#define GPIO_FUNC254_IN_SEL_M  (GPIO_FUNC254_IN_SEL_V << GPIO_FUNC254_IN_SEL_S)
+#define GPIO_FUNC254_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC254_IN_SEL_S  0
+/** GPIO_FUNC254_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC254_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC254_IN_INV_SEL_M  (GPIO_FUNC254_IN_INV_SEL_V << GPIO_FUNC254_IN_INV_SEL_S)
+#define GPIO_FUNC254_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC254_IN_INV_SEL_S  6
+/** GPIO_SIG254_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG254_IN_SEL    (BIT(7))
+#define GPIO_SIG254_IN_SEL_M  (GPIO_SIG254_IN_SEL_V << GPIO_SIG254_IN_SEL_S)
+#define GPIO_SIG254_IN_SEL_V  0x00000001U
+#define GPIO_SIG254_IN_SEL_S  7
+
+/** GPIO_FUNC255_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554)
+/** GPIO_FUNC255_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC255_IN_SEL    0x0000003FU
+#define GPIO_FUNC255_IN_SEL_M  (GPIO_FUNC255_IN_SEL_V << GPIO_FUNC255_IN_SEL_S)
+#define GPIO_FUNC255_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC255_IN_SEL_S  0
+/** GPIO_FUNC255_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC255_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC255_IN_INV_SEL_M  (GPIO_FUNC255_IN_INV_SEL_V << GPIO_FUNC255_IN_INV_SEL_S)
+#define GPIO_FUNC255_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC255_IN_INV_SEL_S  6
+/** GPIO_SIG255_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG255_IN_SEL    (BIT(7))
+#define GPIO_SIG255_IN_SEL_M  (GPIO_SIG255_IN_SEL_V << GPIO_SIG255_IN_SEL_S)
+#define GPIO_SIG255_IN_SEL_V  0x00000001U
+#define GPIO_SIG255_IN_SEL_S  7
+
+/** GPIO_FUNC0_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558)
+/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC0_OUT_SEL    0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_M  (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S)
+#define GPIO_FUNC0_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_S  0
+/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC0_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S)
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OUT_INV_SEL_S  9
+/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC0_OEN_SEL    (BIT(10))
+#define GPIO_FUNC0_OEN_SEL_M  (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S)
+#define GPIO_FUNC0_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC0_OEN_SEL_S  10
+/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC0_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC0_OEN_INV_SEL_M  (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S)
+#define GPIO_FUNC0_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC1_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c)
+/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC1_OUT_SEL    0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_M  (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S)
+#define GPIO_FUNC1_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_S  0
+/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC1_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S)
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OUT_INV_SEL_S  9
+/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC1_OEN_SEL    (BIT(10))
+#define GPIO_FUNC1_OEN_SEL_M  (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S)
+#define GPIO_FUNC1_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC1_OEN_SEL_S  10
+/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC1_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC1_OEN_INV_SEL_M  (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S)
+#define GPIO_FUNC1_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC2_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560)
+/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC2_OUT_SEL    0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_M  (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S)
+#define GPIO_FUNC2_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_S  0
+/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC2_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S)
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OUT_INV_SEL_S  9
+/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC2_OEN_SEL    (BIT(10))
+#define GPIO_FUNC2_OEN_SEL_M  (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S)
+#define GPIO_FUNC2_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC2_OEN_SEL_S  10
+/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC2_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC2_OEN_INV_SEL_M  (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S)
+#define GPIO_FUNC2_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC3_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564)
+/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC3_OUT_SEL    0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_M  (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S)
+#define GPIO_FUNC3_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_S  0
+/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC3_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S)
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OUT_INV_SEL_S  9
+/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC3_OEN_SEL    (BIT(10))
+#define GPIO_FUNC3_OEN_SEL_M  (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S)
+#define GPIO_FUNC3_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC3_OEN_SEL_S  10
+/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC3_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC3_OEN_INV_SEL_M  (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S)
+#define GPIO_FUNC3_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC4_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568)
+/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC4_OUT_SEL    0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_M  (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S)
+#define GPIO_FUNC4_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_S  0
+/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC4_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S)
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OUT_INV_SEL_S  9
+/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC4_OEN_SEL    (BIT(10))
+#define GPIO_FUNC4_OEN_SEL_M  (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S)
+#define GPIO_FUNC4_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC4_OEN_SEL_S  10
+/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC4_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC4_OEN_INV_SEL_M  (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S)
+#define GPIO_FUNC4_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC5_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c)
+/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC5_OUT_SEL    0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_M  (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S)
+#define GPIO_FUNC5_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_S  0
+/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC5_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S)
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OUT_INV_SEL_S  9
+/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC5_OEN_SEL    (BIT(10))
+#define GPIO_FUNC5_OEN_SEL_M  (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S)
+#define GPIO_FUNC5_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC5_OEN_SEL_S  10
+/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC5_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC5_OEN_INV_SEL_M  (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S)
+#define GPIO_FUNC5_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC6_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570)
+/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC6_OUT_SEL    0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_M  (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S)
+#define GPIO_FUNC6_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_S  0
+/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC6_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S)
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OUT_INV_SEL_S  9
+/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC6_OEN_SEL    (BIT(10))
+#define GPIO_FUNC6_OEN_SEL_M  (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S)
+#define GPIO_FUNC6_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC6_OEN_SEL_S  10
+/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC6_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC6_OEN_INV_SEL_M  (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S)
+#define GPIO_FUNC6_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC7_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574)
+/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC7_OUT_SEL    0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_M  (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S)
+#define GPIO_FUNC7_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_S  0
+/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC7_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S)
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OUT_INV_SEL_S  9
+/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC7_OEN_SEL    (BIT(10))
+#define GPIO_FUNC7_OEN_SEL_M  (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S)
+#define GPIO_FUNC7_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC7_OEN_SEL_S  10
+/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC7_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC7_OEN_INV_SEL_M  (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S)
+#define GPIO_FUNC7_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC8_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578)
+/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC8_OUT_SEL    0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_M  (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S)
+#define GPIO_FUNC8_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_S  0
+/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC8_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S)
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OUT_INV_SEL_S  9
+/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC8_OEN_SEL    (BIT(10))
+#define GPIO_FUNC8_OEN_SEL_M  (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S)
+#define GPIO_FUNC8_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC8_OEN_SEL_S  10
+/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC8_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC8_OEN_INV_SEL_M  (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S)
+#define GPIO_FUNC8_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC9_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c)
+/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC9_OUT_SEL    0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_M  (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S)
+#define GPIO_FUNC9_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_S  0
+/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC9_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S)
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OUT_INV_SEL_S  9
+/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC9_OEN_SEL    (BIT(10))
+#define GPIO_FUNC9_OEN_SEL_M  (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S)
+#define GPIO_FUNC9_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC9_OEN_SEL_S  10
+/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC9_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC9_OEN_INV_SEL_M  (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S)
+#define GPIO_FUNC9_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC10_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580)
+/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC10_OUT_SEL    0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_M  (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S)
+#define GPIO_FUNC10_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_S  0
+/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC10_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S)
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OUT_INV_SEL_S  9
+/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC10_OEN_SEL    (BIT(10))
+#define GPIO_FUNC10_OEN_SEL_M  (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S)
+#define GPIO_FUNC10_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC10_OEN_SEL_S  10
+/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC10_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC10_OEN_INV_SEL_M  (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S)
+#define GPIO_FUNC10_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC11_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584)
+/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC11_OUT_SEL    0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_M  (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S)
+#define GPIO_FUNC11_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_S  0
+/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC11_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S)
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OUT_INV_SEL_S  9
+/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC11_OEN_SEL    (BIT(10))
+#define GPIO_FUNC11_OEN_SEL_M  (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S)
+#define GPIO_FUNC11_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC11_OEN_SEL_S  10
+/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC11_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC11_OEN_INV_SEL_M  (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S)
+#define GPIO_FUNC11_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC12_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588)
+/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC12_OUT_SEL    0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_M  (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S)
+#define GPIO_FUNC12_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_S  0
+/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC12_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S)
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OUT_INV_SEL_S  9
+/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC12_OEN_SEL    (BIT(10))
+#define GPIO_FUNC12_OEN_SEL_M  (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S)
+#define GPIO_FUNC12_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC12_OEN_SEL_S  10
+/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC12_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC12_OEN_INV_SEL_M  (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S)
+#define GPIO_FUNC12_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC13_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c)
+/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC13_OUT_SEL    0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_M  (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S)
+#define GPIO_FUNC13_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_S  0
+/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC13_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S)
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OUT_INV_SEL_S  9
+/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC13_OEN_SEL    (BIT(10))
+#define GPIO_FUNC13_OEN_SEL_M  (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S)
+#define GPIO_FUNC13_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC13_OEN_SEL_S  10
+/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC13_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC13_OEN_INV_SEL_M  (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S)
+#define GPIO_FUNC13_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC14_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590)
+/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC14_OUT_SEL    0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_M  (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S)
+#define GPIO_FUNC14_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_S  0
+/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC14_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S)
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OUT_INV_SEL_S  9
+/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC14_OEN_SEL    (BIT(10))
+#define GPIO_FUNC14_OEN_SEL_M  (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S)
+#define GPIO_FUNC14_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC14_OEN_SEL_S  10
+/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC14_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC14_OEN_INV_SEL_M  (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S)
+#define GPIO_FUNC14_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC15_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594)
+/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC15_OUT_SEL    0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_M  (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S)
+#define GPIO_FUNC15_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_S  0
+/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC15_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S)
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OUT_INV_SEL_S  9
+/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC15_OEN_SEL    (BIT(10))
+#define GPIO_FUNC15_OEN_SEL_M  (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S)
+#define GPIO_FUNC15_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC15_OEN_SEL_S  10
+/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC15_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC15_OEN_INV_SEL_M  (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S)
+#define GPIO_FUNC15_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC16_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598)
+/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC16_OUT_SEL    0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_M  (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S)
+#define GPIO_FUNC16_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_S  0
+/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC16_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S)
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OUT_INV_SEL_S  9
+/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC16_OEN_SEL    (BIT(10))
+#define GPIO_FUNC16_OEN_SEL_M  (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S)
+#define GPIO_FUNC16_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC16_OEN_SEL_S  10
+/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC16_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC16_OEN_INV_SEL_M  (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S)
+#define GPIO_FUNC16_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC17_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c)
+/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC17_OUT_SEL    0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_M  (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S)
+#define GPIO_FUNC17_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_S  0
+/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC17_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S)
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OUT_INV_SEL_S  9
+/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC17_OEN_SEL    (BIT(10))
+#define GPIO_FUNC17_OEN_SEL_M  (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S)
+#define GPIO_FUNC17_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC17_OEN_SEL_S  10
+/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC17_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC17_OEN_INV_SEL_M  (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S)
+#define GPIO_FUNC17_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC18_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0)
+/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC18_OUT_SEL    0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_M  (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S)
+#define GPIO_FUNC18_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_S  0
+/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC18_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S)
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OUT_INV_SEL_S  9
+/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC18_OEN_SEL    (BIT(10))
+#define GPIO_FUNC18_OEN_SEL_M  (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S)
+#define GPIO_FUNC18_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC18_OEN_SEL_S  10
+/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC18_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC18_OEN_INV_SEL_M  (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S)
+#define GPIO_FUNC18_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC19_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4)
+/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC19_OUT_SEL    0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_M  (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S)
+#define GPIO_FUNC19_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_S  0
+/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC19_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S)
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OUT_INV_SEL_S  9
+/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC19_OEN_SEL    (BIT(10))
+#define GPIO_FUNC19_OEN_SEL_M  (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S)
+#define GPIO_FUNC19_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC19_OEN_SEL_S  10
+/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC19_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC19_OEN_INV_SEL_M  (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S)
+#define GPIO_FUNC19_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC20_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8)
+/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC20_OUT_SEL    0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_M  (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S)
+#define GPIO_FUNC20_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_S  0
+/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC20_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S)
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OUT_INV_SEL_S  9
+/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC20_OEN_SEL    (BIT(10))
+#define GPIO_FUNC20_OEN_SEL_M  (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S)
+#define GPIO_FUNC20_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC20_OEN_SEL_S  10
+/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC20_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC20_OEN_INV_SEL_M  (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S)
+#define GPIO_FUNC20_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC21_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac)
+/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC21_OUT_SEL    0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_M  (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S)
+#define GPIO_FUNC21_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_S  0
+/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC21_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S)
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OUT_INV_SEL_S  9
+/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC21_OEN_SEL    (BIT(10))
+#define GPIO_FUNC21_OEN_SEL_M  (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S)
+#define GPIO_FUNC21_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC21_OEN_SEL_S  10
+/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC21_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC21_OEN_INV_SEL_M  (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S)
+#define GPIO_FUNC21_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC22_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0)
+/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC22_OUT_SEL    0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_M  (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
+#define GPIO_FUNC22_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_S  0
+/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC22_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OUT_INV_SEL_S  9
+/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC22_OEN_SEL    (BIT(10))
+#define GPIO_FUNC22_OEN_SEL_M  (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S)
+#define GPIO_FUNC22_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC22_OEN_SEL_S  10
+/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC22_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC22_OEN_INV_SEL_M  (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S)
+#define GPIO_FUNC22_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC23_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4)
+/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC23_OUT_SEL    0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_M  (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
+#define GPIO_FUNC23_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_S  0
+/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC23_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OUT_INV_SEL_S  9
+/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC23_OEN_SEL    (BIT(10))
+#define GPIO_FUNC23_OEN_SEL_M  (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S)
+#define GPIO_FUNC23_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC23_OEN_SEL_S  10
+/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC23_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC23_OEN_INV_SEL_M  (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S)
+#define GPIO_FUNC23_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC24_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8)
+/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC24_OUT_SEL    0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_M  (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
+#define GPIO_FUNC24_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_S  0
+/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC24_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OUT_INV_SEL_S  9
+/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC24_OEN_SEL    (BIT(10))
+#define GPIO_FUNC24_OEN_SEL_M  (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S)
+#define GPIO_FUNC24_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC24_OEN_SEL_S  10
+/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC24_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC24_OEN_INV_SEL_M  (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S)
+#define GPIO_FUNC24_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC25_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc)
+/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC25_OUT_SEL    0x000001FFU
+#define GPIO_FUNC25_OUT_SEL_M  (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S)
+#define GPIO_FUNC25_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC25_OUT_SEL_S  0
+/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC25_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_M  (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S)
+#define GPIO_FUNC25_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_OUT_INV_SEL_S  9
+/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC25_OEN_SEL    (BIT(10))
+#define GPIO_FUNC25_OEN_SEL_M  (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S)
+#define GPIO_FUNC25_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC25_OEN_SEL_S  10
+/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC25_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC25_OEN_INV_SEL_M  (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S)
+#define GPIO_FUNC25_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC26_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0)
+/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC26_OUT_SEL    0x000001FFU
+#define GPIO_FUNC26_OUT_SEL_M  (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S)
+#define GPIO_FUNC26_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC26_OUT_SEL_S  0
+/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC26_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_M  (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S)
+#define GPIO_FUNC26_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_OUT_INV_SEL_S  9
+/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC26_OEN_SEL    (BIT(10))
+#define GPIO_FUNC26_OEN_SEL_M  (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S)
+#define GPIO_FUNC26_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC26_OEN_SEL_S  10
+/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC26_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC26_OEN_INV_SEL_M  (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S)
+#define GPIO_FUNC26_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC27_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4)
+/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC27_OUT_SEL    0x000001FFU
+#define GPIO_FUNC27_OUT_SEL_M  (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S)
+#define GPIO_FUNC27_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC27_OUT_SEL_S  0
+/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC27_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_M  (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S)
+#define GPIO_FUNC27_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_OUT_INV_SEL_S  9
+/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC27_OEN_SEL    (BIT(10))
+#define GPIO_FUNC27_OEN_SEL_M  (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S)
+#define GPIO_FUNC27_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC27_OEN_SEL_S  10
+/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC27_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC27_OEN_INV_SEL_M  (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S)
+#define GPIO_FUNC27_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC28_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8)
+/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC28_OUT_SEL    0x000001FFU
+#define GPIO_FUNC28_OUT_SEL_M  (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S)
+#define GPIO_FUNC28_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC28_OUT_SEL_S  0
+/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC28_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_M  (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S)
+#define GPIO_FUNC28_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_OUT_INV_SEL_S  9
+/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC28_OEN_SEL    (BIT(10))
+#define GPIO_FUNC28_OEN_SEL_M  (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S)
+#define GPIO_FUNC28_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC28_OEN_SEL_S  10
+/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC28_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC28_OEN_INV_SEL_M  (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S)
+#define GPIO_FUNC28_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC29_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc)
+/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC29_OUT_SEL    0x000001FFU
+#define GPIO_FUNC29_OUT_SEL_M  (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S)
+#define GPIO_FUNC29_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC29_OUT_SEL_S  0
+/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC29_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_M  (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S)
+#define GPIO_FUNC29_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_OUT_INV_SEL_S  9
+/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC29_OEN_SEL    (BIT(10))
+#define GPIO_FUNC29_OEN_SEL_M  (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S)
+#define GPIO_FUNC29_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC29_OEN_SEL_S  10
+/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC29_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC29_OEN_INV_SEL_M  (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S)
+#define GPIO_FUNC29_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC30_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0)
+/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC30_OUT_SEL    0x000001FFU
+#define GPIO_FUNC30_OUT_SEL_M  (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S)
+#define GPIO_FUNC30_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC30_OUT_SEL_S  0
+/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC30_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_M  (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S)
+#define GPIO_FUNC30_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_OUT_INV_SEL_S  9
+/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC30_OEN_SEL    (BIT(10))
+#define GPIO_FUNC30_OEN_SEL_M  (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S)
+#define GPIO_FUNC30_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC30_OEN_SEL_S  10
+/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC30_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC30_OEN_INV_SEL_M  (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S)
+#define GPIO_FUNC30_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC31_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4)
+/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC31_OUT_SEL    0x000001FFU
+#define GPIO_FUNC31_OUT_SEL_M  (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S)
+#define GPIO_FUNC31_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC31_OUT_SEL_S  0
+/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC31_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_M  (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S)
+#define GPIO_FUNC31_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_OUT_INV_SEL_S  9
+/** GPIO_FUNC31_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC31_OEN_SEL    (BIT(10))
+#define GPIO_FUNC31_OEN_SEL_M  (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S)
+#define GPIO_FUNC31_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC31_OEN_SEL_S  10
+/** GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC31_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC31_OEN_INV_SEL_M  (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S)
+#define GPIO_FUNC31_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC32_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8)
+/** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC32_OUT_SEL    0x000001FFU
+#define GPIO_FUNC32_OUT_SEL_M  (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S)
+#define GPIO_FUNC32_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC32_OUT_SEL_S  0
+/** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC32_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_M  (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S)
+#define GPIO_FUNC32_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_OUT_INV_SEL_S  9
+/** GPIO_FUNC32_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC32_OEN_SEL    (BIT(10))
+#define GPIO_FUNC32_OEN_SEL_M  (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S)
+#define GPIO_FUNC32_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC32_OEN_SEL_S  10
+/** GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC32_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC32_OEN_INV_SEL_M  (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S)
+#define GPIO_FUNC32_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC33_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc)
+/** GPIO_FUNC33_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC33_OUT_SEL    0x000001FFU
+#define GPIO_FUNC33_OUT_SEL_M  (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S)
+#define GPIO_FUNC33_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC33_OUT_SEL_S  0
+/** GPIO_FUNC33_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC33_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_M  (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S)
+#define GPIO_FUNC33_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_OUT_INV_SEL_S  9
+/** GPIO_FUNC33_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC33_OEN_SEL    (BIT(10))
+#define GPIO_FUNC33_OEN_SEL_M  (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S)
+#define GPIO_FUNC33_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC33_OEN_SEL_S  10
+/** GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC33_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC33_OEN_INV_SEL_M  (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S)
+#define GPIO_FUNC33_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC34_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e0)
+/** GPIO_FUNC34_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC34_OUT_SEL    0x000001FFU
+#define GPIO_FUNC34_OUT_SEL_M  (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S)
+#define GPIO_FUNC34_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC34_OUT_SEL_S  0
+/** GPIO_FUNC34_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC34_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_M  (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S)
+#define GPIO_FUNC34_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_OUT_INV_SEL_S  9
+/** GPIO_FUNC34_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC34_OEN_SEL    (BIT(10))
+#define GPIO_FUNC34_OEN_SEL_M  (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S)
+#define GPIO_FUNC34_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC34_OEN_SEL_S  10
+/** GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC34_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC34_OEN_INV_SEL_M  (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S)
+#define GPIO_FUNC34_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC35_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e4)
+/** GPIO_FUNC35_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC35_OUT_SEL    0x000001FFU
+#define GPIO_FUNC35_OUT_SEL_M  (GPIO_FUNC35_OUT_SEL_V << GPIO_FUNC35_OUT_SEL_S)
+#define GPIO_FUNC35_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC35_OUT_SEL_S  0
+/** GPIO_FUNC35_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC35_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_M  (GPIO_FUNC35_OUT_INV_SEL_V << GPIO_FUNC35_OUT_INV_SEL_S)
+#define GPIO_FUNC35_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_OUT_INV_SEL_S  9
+/** GPIO_FUNC35_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC35_OEN_SEL    (BIT(10))
+#define GPIO_FUNC35_OEN_SEL_M  (GPIO_FUNC35_OEN_SEL_V << GPIO_FUNC35_OEN_SEL_S)
+#define GPIO_FUNC35_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC35_OEN_SEL_S  10
+/** GPIO_FUNC35_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC35_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC35_OEN_INV_SEL_M  (GPIO_FUNC35_OEN_INV_SEL_V << GPIO_FUNC35_OEN_INV_SEL_S)
+#define GPIO_FUNC35_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC36_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e8)
+/** GPIO_FUNC36_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC36_OUT_SEL    0x000001FFU
+#define GPIO_FUNC36_OUT_SEL_M  (GPIO_FUNC36_OUT_SEL_V << GPIO_FUNC36_OUT_SEL_S)
+#define GPIO_FUNC36_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC36_OUT_SEL_S  0
+/** GPIO_FUNC36_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC36_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_M  (GPIO_FUNC36_OUT_INV_SEL_V << GPIO_FUNC36_OUT_INV_SEL_S)
+#define GPIO_FUNC36_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_OUT_INV_SEL_S  9
+/** GPIO_FUNC36_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC36_OEN_SEL    (BIT(10))
+#define GPIO_FUNC36_OEN_SEL_M  (GPIO_FUNC36_OEN_SEL_V << GPIO_FUNC36_OEN_SEL_S)
+#define GPIO_FUNC36_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC36_OEN_SEL_S  10
+/** GPIO_FUNC36_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC36_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC36_OEN_INV_SEL_M  (GPIO_FUNC36_OEN_INV_SEL_V << GPIO_FUNC36_OEN_INV_SEL_S)
+#define GPIO_FUNC36_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC37_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ec)
+/** GPIO_FUNC37_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC37_OUT_SEL    0x000001FFU
+#define GPIO_FUNC37_OUT_SEL_M  (GPIO_FUNC37_OUT_SEL_V << GPIO_FUNC37_OUT_SEL_S)
+#define GPIO_FUNC37_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC37_OUT_SEL_S  0
+/** GPIO_FUNC37_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC37_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_M  (GPIO_FUNC37_OUT_INV_SEL_V << GPIO_FUNC37_OUT_INV_SEL_S)
+#define GPIO_FUNC37_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_OUT_INV_SEL_S  9
+/** GPIO_FUNC37_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC37_OEN_SEL    (BIT(10))
+#define GPIO_FUNC37_OEN_SEL_M  (GPIO_FUNC37_OEN_SEL_V << GPIO_FUNC37_OEN_SEL_S)
+#define GPIO_FUNC37_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC37_OEN_SEL_S  10
+/** GPIO_FUNC37_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC37_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC37_OEN_INV_SEL_M  (GPIO_FUNC37_OEN_INV_SEL_V << GPIO_FUNC37_OEN_INV_SEL_S)
+#define GPIO_FUNC37_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC38_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f0)
+/** GPIO_FUNC38_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC38_OUT_SEL    0x000001FFU
+#define GPIO_FUNC38_OUT_SEL_M  (GPIO_FUNC38_OUT_SEL_V << GPIO_FUNC38_OUT_SEL_S)
+#define GPIO_FUNC38_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC38_OUT_SEL_S  0
+/** GPIO_FUNC38_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC38_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_M  (GPIO_FUNC38_OUT_INV_SEL_V << GPIO_FUNC38_OUT_INV_SEL_S)
+#define GPIO_FUNC38_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_OUT_INV_SEL_S  9
+/** GPIO_FUNC38_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC38_OEN_SEL    (BIT(10))
+#define GPIO_FUNC38_OEN_SEL_M  (GPIO_FUNC38_OEN_SEL_V << GPIO_FUNC38_OEN_SEL_S)
+#define GPIO_FUNC38_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC38_OEN_SEL_S  10
+/** GPIO_FUNC38_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC38_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC38_OEN_INV_SEL_M  (GPIO_FUNC38_OEN_INV_SEL_V << GPIO_FUNC38_OEN_INV_SEL_S)
+#define GPIO_FUNC38_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC39_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f4)
+/** GPIO_FUNC39_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC39_OUT_SEL    0x000001FFU
+#define GPIO_FUNC39_OUT_SEL_M  (GPIO_FUNC39_OUT_SEL_V << GPIO_FUNC39_OUT_SEL_S)
+#define GPIO_FUNC39_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC39_OUT_SEL_S  0
+/** GPIO_FUNC39_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC39_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_M  (GPIO_FUNC39_OUT_INV_SEL_V << GPIO_FUNC39_OUT_INV_SEL_S)
+#define GPIO_FUNC39_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_OUT_INV_SEL_S  9
+/** GPIO_FUNC39_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC39_OEN_SEL    (BIT(10))
+#define GPIO_FUNC39_OEN_SEL_M  (GPIO_FUNC39_OEN_SEL_V << GPIO_FUNC39_OEN_SEL_S)
+#define GPIO_FUNC39_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC39_OEN_SEL_S  10
+/** GPIO_FUNC39_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC39_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC39_OEN_INV_SEL_M  (GPIO_FUNC39_OEN_INV_SEL_V << GPIO_FUNC39_OEN_INV_SEL_S)
+#define GPIO_FUNC39_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC40_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f8)
+/** GPIO_FUNC40_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC40_OUT_SEL    0x000001FFU
+#define GPIO_FUNC40_OUT_SEL_M  (GPIO_FUNC40_OUT_SEL_V << GPIO_FUNC40_OUT_SEL_S)
+#define GPIO_FUNC40_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC40_OUT_SEL_S  0
+/** GPIO_FUNC40_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC40_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC40_OUT_INV_SEL_M  (GPIO_FUNC40_OUT_INV_SEL_V << GPIO_FUNC40_OUT_INV_SEL_S)
+#define GPIO_FUNC40_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_OUT_INV_SEL_S  9
+/** GPIO_FUNC40_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC40_OEN_SEL    (BIT(10))
+#define GPIO_FUNC40_OEN_SEL_M  (GPIO_FUNC40_OEN_SEL_V << GPIO_FUNC40_OEN_SEL_S)
+#define GPIO_FUNC40_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC40_OEN_SEL_S  10
+/** GPIO_FUNC40_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC40_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC40_OEN_INV_SEL_M  (GPIO_FUNC40_OEN_INV_SEL_V << GPIO_FUNC40_OEN_INV_SEL_S)
+#define GPIO_FUNC40_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC41_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5fc)
+/** GPIO_FUNC41_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC41_OUT_SEL    0x000001FFU
+#define GPIO_FUNC41_OUT_SEL_M  (GPIO_FUNC41_OUT_SEL_V << GPIO_FUNC41_OUT_SEL_S)
+#define GPIO_FUNC41_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC41_OUT_SEL_S  0
+/** GPIO_FUNC41_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC41_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC41_OUT_INV_SEL_M  (GPIO_FUNC41_OUT_INV_SEL_V << GPIO_FUNC41_OUT_INV_SEL_S)
+#define GPIO_FUNC41_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_OUT_INV_SEL_S  9
+/** GPIO_FUNC41_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC41_OEN_SEL    (BIT(10))
+#define GPIO_FUNC41_OEN_SEL_M  (GPIO_FUNC41_OEN_SEL_V << GPIO_FUNC41_OEN_SEL_S)
+#define GPIO_FUNC41_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC41_OEN_SEL_S  10
+/** GPIO_FUNC41_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC41_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC41_OEN_INV_SEL_M  (GPIO_FUNC41_OEN_INV_SEL_V << GPIO_FUNC41_OEN_INV_SEL_S)
+#define GPIO_FUNC41_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC42_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600)
+/** GPIO_FUNC42_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC42_OUT_SEL    0x000001FFU
+#define GPIO_FUNC42_OUT_SEL_M  (GPIO_FUNC42_OUT_SEL_V << GPIO_FUNC42_OUT_SEL_S)
+#define GPIO_FUNC42_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC42_OUT_SEL_S  0
+/** GPIO_FUNC42_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC42_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC42_OUT_INV_SEL_M  (GPIO_FUNC42_OUT_INV_SEL_V << GPIO_FUNC42_OUT_INV_SEL_S)
+#define GPIO_FUNC42_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_OUT_INV_SEL_S  9
+/** GPIO_FUNC42_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC42_OEN_SEL    (BIT(10))
+#define GPIO_FUNC42_OEN_SEL_M  (GPIO_FUNC42_OEN_SEL_V << GPIO_FUNC42_OEN_SEL_S)
+#define GPIO_FUNC42_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC42_OEN_SEL_S  10
+/** GPIO_FUNC42_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC42_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC42_OEN_INV_SEL_M  (GPIO_FUNC42_OEN_INV_SEL_V << GPIO_FUNC42_OEN_INV_SEL_S)
+#define GPIO_FUNC42_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC43_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604)
+/** GPIO_FUNC43_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC43_OUT_SEL    0x000001FFU
+#define GPIO_FUNC43_OUT_SEL_M  (GPIO_FUNC43_OUT_SEL_V << GPIO_FUNC43_OUT_SEL_S)
+#define GPIO_FUNC43_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC43_OUT_SEL_S  0
+/** GPIO_FUNC43_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC43_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC43_OUT_INV_SEL_M  (GPIO_FUNC43_OUT_INV_SEL_V << GPIO_FUNC43_OUT_INV_SEL_S)
+#define GPIO_FUNC43_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_OUT_INV_SEL_S  9
+/** GPIO_FUNC43_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC43_OEN_SEL    (BIT(10))
+#define GPIO_FUNC43_OEN_SEL_M  (GPIO_FUNC43_OEN_SEL_V << GPIO_FUNC43_OEN_SEL_S)
+#define GPIO_FUNC43_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC43_OEN_SEL_S  10
+/** GPIO_FUNC43_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC43_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC43_OEN_INV_SEL_M  (GPIO_FUNC43_OEN_INV_SEL_V << GPIO_FUNC43_OEN_INV_SEL_S)
+#define GPIO_FUNC43_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC44_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x608)
+/** GPIO_FUNC44_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC44_OUT_SEL    0x000001FFU
+#define GPIO_FUNC44_OUT_SEL_M  (GPIO_FUNC44_OUT_SEL_V << GPIO_FUNC44_OUT_SEL_S)
+#define GPIO_FUNC44_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC44_OUT_SEL_S  0
+/** GPIO_FUNC44_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC44_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC44_OUT_INV_SEL_M  (GPIO_FUNC44_OUT_INV_SEL_V << GPIO_FUNC44_OUT_INV_SEL_S)
+#define GPIO_FUNC44_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_OUT_INV_SEL_S  9
+/** GPIO_FUNC44_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC44_OEN_SEL    (BIT(10))
+#define GPIO_FUNC44_OEN_SEL_M  (GPIO_FUNC44_OEN_SEL_V << GPIO_FUNC44_OEN_SEL_S)
+#define GPIO_FUNC44_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC44_OEN_SEL_S  10
+/** GPIO_FUNC44_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC44_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC44_OEN_INV_SEL_M  (GPIO_FUNC44_OEN_INV_SEL_V << GPIO_FUNC44_OEN_INV_SEL_S)
+#define GPIO_FUNC44_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC45_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC45_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x60c)
+/** GPIO_FUNC45_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC45_OUT_SEL    0x000001FFU
+#define GPIO_FUNC45_OUT_SEL_M  (GPIO_FUNC45_OUT_SEL_V << GPIO_FUNC45_OUT_SEL_S)
+#define GPIO_FUNC45_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC45_OUT_SEL_S  0
+/** GPIO_FUNC45_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC45_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC45_OUT_INV_SEL_M  (GPIO_FUNC45_OUT_INV_SEL_V << GPIO_FUNC45_OUT_INV_SEL_S)
+#define GPIO_FUNC45_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_OUT_INV_SEL_S  9
+/** GPIO_FUNC45_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC45_OEN_SEL    (BIT(10))
+#define GPIO_FUNC45_OEN_SEL_M  (GPIO_FUNC45_OEN_SEL_V << GPIO_FUNC45_OEN_SEL_S)
+#define GPIO_FUNC45_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC45_OEN_SEL_S  10
+/** GPIO_FUNC45_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC45_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC45_OEN_INV_SEL_M  (GPIO_FUNC45_OEN_INV_SEL_V << GPIO_FUNC45_OEN_INV_SEL_S)
+#define GPIO_FUNC45_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC46_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC46_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x610)
+/** GPIO_FUNC46_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC46_OUT_SEL    0x000001FFU
+#define GPIO_FUNC46_OUT_SEL_M  (GPIO_FUNC46_OUT_SEL_V << GPIO_FUNC46_OUT_SEL_S)
+#define GPIO_FUNC46_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC46_OUT_SEL_S  0
+/** GPIO_FUNC46_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC46_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC46_OUT_INV_SEL_M  (GPIO_FUNC46_OUT_INV_SEL_V << GPIO_FUNC46_OUT_INV_SEL_S)
+#define GPIO_FUNC46_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_OUT_INV_SEL_S  9
+/** GPIO_FUNC46_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC46_OEN_SEL    (BIT(10))
+#define GPIO_FUNC46_OEN_SEL_M  (GPIO_FUNC46_OEN_SEL_V << GPIO_FUNC46_OEN_SEL_S)
+#define GPIO_FUNC46_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC46_OEN_SEL_S  10
+/** GPIO_FUNC46_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC46_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC46_OEN_INV_SEL_M  (GPIO_FUNC46_OEN_INV_SEL_V << GPIO_FUNC46_OEN_INV_SEL_S)
+#define GPIO_FUNC46_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC47_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC47_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x614)
+/** GPIO_FUNC47_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC47_OUT_SEL    0x000001FFU
+#define GPIO_FUNC47_OUT_SEL_M  (GPIO_FUNC47_OUT_SEL_V << GPIO_FUNC47_OUT_SEL_S)
+#define GPIO_FUNC47_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC47_OUT_SEL_S  0
+/** GPIO_FUNC47_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC47_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC47_OUT_INV_SEL_M  (GPIO_FUNC47_OUT_INV_SEL_V << GPIO_FUNC47_OUT_INV_SEL_S)
+#define GPIO_FUNC47_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_OUT_INV_SEL_S  9
+/** GPIO_FUNC47_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC47_OEN_SEL    (BIT(10))
+#define GPIO_FUNC47_OEN_SEL_M  (GPIO_FUNC47_OEN_SEL_V << GPIO_FUNC47_OEN_SEL_S)
+#define GPIO_FUNC47_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC47_OEN_SEL_S  10
+/** GPIO_FUNC47_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC47_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC47_OEN_INV_SEL_M  (GPIO_FUNC47_OEN_INV_SEL_V << GPIO_FUNC47_OEN_INV_SEL_S)
+#define GPIO_FUNC47_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC48_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC48_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x618)
+/** GPIO_FUNC48_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC48_OUT_SEL    0x000001FFU
+#define GPIO_FUNC48_OUT_SEL_M  (GPIO_FUNC48_OUT_SEL_V << GPIO_FUNC48_OUT_SEL_S)
+#define GPIO_FUNC48_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC48_OUT_SEL_S  0
+/** GPIO_FUNC48_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC48_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC48_OUT_INV_SEL_M  (GPIO_FUNC48_OUT_INV_SEL_V << GPIO_FUNC48_OUT_INV_SEL_S)
+#define GPIO_FUNC48_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_OUT_INV_SEL_S  9
+/** GPIO_FUNC48_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC48_OEN_SEL    (BIT(10))
+#define GPIO_FUNC48_OEN_SEL_M  (GPIO_FUNC48_OEN_SEL_V << GPIO_FUNC48_OEN_SEL_S)
+#define GPIO_FUNC48_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC48_OEN_SEL_S  10
+/** GPIO_FUNC48_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC48_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC48_OEN_INV_SEL_M  (GPIO_FUNC48_OEN_INV_SEL_V << GPIO_FUNC48_OEN_INV_SEL_S)
+#define GPIO_FUNC48_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC49_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC49_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x61c)
+/** GPIO_FUNC49_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC49_OUT_SEL    0x000001FFU
+#define GPIO_FUNC49_OUT_SEL_M  (GPIO_FUNC49_OUT_SEL_V << GPIO_FUNC49_OUT_SEL_S)
+#define GPIO_FUNC49_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC49_OUT_SEL_S  0
+/** GPIO_FUNC49_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC49_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC49_OUT_INV_SEL_M  (GPIO_FUNC49_OUT_INV_SEL_V << GPIO_FUNC49_OUT_INV_SEL_S)
+#define GPIO_FUNC49_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_OUT_INV_SEL_S  9
+/** GPIO_FUNC49_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC49_OEN_SEL    (BIT(10))
+#define GPIO_FUNC49_OEN_SEL_M  (GPIO_FUNC49_OEN_SEL_V << GPIO_FUNC49_OEN_SEL_S)
+#define GPIO_FUNC49_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC49_OEN_SEL_S  10
+/** GPIO_FUNC49_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC49_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC49_OEN_INV_SEL_M  (GPIO_FUNC49_OEN_INV_SEL_V << GPIO_FUNC49_OEN_INV_SEL_S)
+#define GPIO_FUNC49_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC50_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC50_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x620)
+/** GPIO_FUNC50_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC50_OUT_SEL    0x000001FFU
+#define GPIO_FUNC50_OUT_SEL_M  (GPIO_FUNC50_OUT_SEL_V << GPIO_FUNC50_OUT_SEL_S)
+#define GPIO_FUNC50_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC50_OUT_SEL_S  0
+/** GPIO_FUNC50_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC50_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC50_OUT_INV_SEL_M  (GPIO_FUNC50_OUT_INV_SEL_V << GPIO_FUNC50_OUT_INV_SEL_S)
+#define GPIO_FUNC50_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_OUT_INV_SEL_S  9
+/** GPIO_FUNC50_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC50_OEN_SEL    (BIT(10))
+#define GPIO_FUNC50_OEN_SEL_M  (GPIO_FUNC50_OEN_SEL_V << GPIO_FUNC50_OEN_SEL_S)
+#define GPIO_FUNC50_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC50_OEN_SEL_S  10
+/** GPIO_FUNC50_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC50_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC50_OEN_INV_SEL_M  (GPIO_FUNC50_OEN_INV_SEL_V << GPIO_FUNC50_OEN_INV_SEL_S)
+#define GPIO_FUNC50_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC51_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC51_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x624)
+/** GPIO_FUNC51_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC51_OUT_SEL    0x000001FFU
+#define GPIO_FUNC51_OUT_SEL_M  (GPIO_FUNC51_OUT_SEL_V << GPIO_FUNC51_OUT_SEL_S)
+#define GPIO_FUNC51_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC51_OUT_SEL_S  0
+/** GPIO_FUNC51_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC51_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC51_OUT_INV_SEL_M  (GPIO_FUNC51_OUT_INV_SEL_V << GPIO_FUNC51_OUT_INV_SEL_S)
+#define GPIO_FUNC51_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_OUT_INV_SEL_S  9
+/** GPIO_FUNC51_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC51_OEN_SEL    (BIT(10))
+#define GPIO_FUNC51_OEN_SEL_M  (GPIO_FUNC51_OEN_SEL_V << GPIO_FUNC51_OEN_SEL_S)
+#define GPIO_FUNC51_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC51_OEN_SEL_S  10
+/** GPIO_FUNC51_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC51_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC51_OEN_INV_SEL_M  (GPIO_FUNC51_OEN_INV_SEL_V << GPIO_FUNC51_OEN_INV_SEL_S)
+#define GPIO_FUNC51_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC52_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC52_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x628)
+/** GPIO_FUNC52_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC52_OUT_SEL    0x000001FFU
+#define GPIO_FUNC52_OUT_SEL_M  (GPIO_FUNC52_OUT_SEL_V << GPIO_FUNC52_OUT_SEL_S)
+#define GPIO_FUNC52_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC52_OUT_SEL_S  0
+/** GPIO_FUNC52_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC52_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC52_OUT_INV_SEL_M  (GPIO_FUNC52_OUT_INV_SEL_V << GPIO_FUNC52_OUT_INV_SEL_S)
+#define GPIO_FUNC52_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_OUT_INV_SEL_S  9
+/** GPIO_FUNC52_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC52_OEN_SEL    (BIT(10))
+#define GPIO_FUNC52_OEN_SEL_M  (GPIO_FUNC52_OEN_SEL_V << GPIO_FUNC52_OEN_SEL_S)
+#define GPIO_FUNC52_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC52_OEN_SEL_S  10
+/** GPIO_FUNC52_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC52_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC52_OEN_INV_SEL_M  (GPIO_FUNC52_OEN_INV_SEL_V << GPIO_FUNC52_OEN_INV_SEL_S)
+#define GPIO_FUNC52_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC53_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC53_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x62c)
+/** GPIO_FUNC53_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC53_OUT_SEL    0x000001FFU
+#define GPIO_FUNC53_OUT_SEL_M  (GPIO_FUNC53_OUT_SEL_V << GPIO_FUNC53_OUT_SEL_S)
+#define GPIO_FUNC53_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC53_OUT_SEL_S  0
+/** GPIO_FUNC53_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC53_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC53_OUT_INV_SEL_M  (GPIO_FUNC53_OUT_INV_SEL_V << GPIO_FUNC53_OUT_INV_SEL_S)
+#define GPIO_FUNC53_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_OUT_INV_SEL_S  9
+/** GPIO_FUNC53_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC53_OEN_SEL    (BIT(10))
+#define GPIO_FUNC53_OEN_SEL_M  (GPIO_FUNC53_OEN_SEL_V << GPIO_FUNC53_OEN_SEL_S)
+#define GPIO_FUNC53_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC53_OEN_SEL_S  10
+/** GPIO_FUNC53_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC53_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC53_OEN_INV_SEL_M  (GPIO_FUNC53_OEN_INV_SEL_V << GPIO_FUNC53_OEN_INV_SEL_S)
+#define GPIO_FUNC53_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC54_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC54_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x630)
+/** GPIO_FUNC54_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC54_OUT_SEL    0x000001FFU
+#define GPIO_FUNC54_OUT_SEL_M  (GPIO_FUNC54_OUT_SEL_V << GPIO_FUNC54_OUT_SEL_S)
+#define GPIO_FUNC54_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC54_OUT_SEL_S  0
+/** GPIO_FUNC54_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC54_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC54_OUT_INV_SEL_M  (GPIO_FUNC54_OUT_INV_SEL_V << GPIO_FUNC54_OUT_INV_SEL_S)
+#define GPIO_FUNC54_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_OUT_INV_SEL_S  9
+/** GPIO_FUNC54_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC54_OEN_SEL    (BIT(10))
+#define GPIO_FUNC54_OEN_SEL_M  (GPIO_FUNC54_OEN_SEL_V << GPIO_FUNC54_OEN_SEL_S)
+#define GPIO_FUNC54_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC54_OEN_SEL_S  10
+/** GPIO_FUNC54_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC54_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC54_OEN_INV_SEL_M  (GPIO_FUNC54_OEN_INV_SEL_V << GPIO_FUNC54_OEN_INV_SEL_S)
+#define GPIO_FUNC54_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC55_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC55_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x634)
+/** GPIO_FUNC55_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC55_OUT_SEL    0x000001FFU
+#define GPIO_FUNC55_OUT_SEL_M  (GPIO_FUNC55_OUT_SEL_V << GPIO_FUNC55_OUT_SEL_S)
+#define GPIO_FUNC55_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC55_OUT_SEL_S  0
+/** GPIO_FUNC55_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC55_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC55_OUT_INV_SEL_M  (GPIO_FUNC55_OUT_INV_SEL_V << GPIO_FUNC55_OUT_INV_SEL_S)
+#define GPIO_FUNC55_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_OUT_INV_SEL_S  9
+/** GPIO_FUNC55_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC55_OEN_SEL    (BIT(10))
+#define GPIO_FUNC55_OEN_SEL_M  (GPIO_FUNC55_OEN_SEL_V << GPIO_FUNC55_OEN_SEL_S)
+#define GPIO_FUNC55_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC55_OEN_SEL_S  10
+/** GPIO_FUNC55_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC55_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC55_OEN_INV_SEL_M  (GPIO_FUNC55_OEN_INV_SEL_V << GPIO_FUNC55_OEN_INV_SEL_S)
+#define GPIO_FUNC55_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC56_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC56_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x638)
+/** GPIO_FUNC56_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC56_OUT_SEL    0x000001FFU
+#define GPIO_FUNC56_OUT_SEL_M  (GPIO_FUNC56_OUT_SEL_V << GPIO_FUNC56_OUT_SEL_S)
+#define GPIO_FUNC56_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC56_OUT_SEL_S  0
+/** GPIO_FUNC56_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC56_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC56_OUT_INV_SEL_M  (GPIO_FUNC56_OUT_INV_SEL_V << GPIO_FUNC56_OUT_INV_SEL_S)
+#define GPIO_FUNC56_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_OUT_INV_SEL_S  9
+/** GPIO_FUNC56_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC56_OEN_SEL    (BIT(10))
+#define GPIO_FUNC56_OEN_SEL_M  (GPIO_FUNC56_OEN_SEL_V << GPIO_FUNC56_OEN_SEL_S)
+#define GPIO_FUNC56_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC56_OEN_SEL_S  10
+/** GPIO_FUNC56_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC56_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC56_OEN_INV_SEL_M  (GPIO_FUNC56_OEN_INV_SEL_V << GPIO_FUNC56_OEN_INV_SEL_S)
+#define GPIO_FUNC56_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_OEN_INV_SEL_S  11
+
+/** GPIO_INTR_2_REG register
+ *  GPIO interrupt 2 status register for GPIO0-31
+ */
+#define GPIO_INTR_2_REG (DR_REG_GPIO_BASE + 0x63c)
+/** GPIO_INT_2 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 2 status register for GPIO0-31
+ */
+#define GPIO_INT_2    0xFFFFFFFFU
+#define GPIO_INT_2_M  (GPIO_INT_2_V << GPIO_INT_2_S)
+#define GPIO_INT_2_V  0xFFFFFFFFU
+#define GPIO_INT_2_S  0
+
+/** GPIO_INTR1_2_REG register
+ *  GPIO interrupt 2 status register for GPIO32-56
+ */
+#define GPIO_INTR1_2_REG (DR_REG_GPIO_BASE + 0x640)
+/** GPIO_INT1_2 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 2 status register for GPIO32-56
+ */
+#define GPIO_INT1_2    0x01FFFFFFU
+#define GPIO_INT1_2_M  (GPIO_INT1_2_V << GPIO_INT1_2_S)
+#define GPIO_INT1_2_V  0x01FFFFFFU
+#define GPIO_INT1_2_S  0
+
+/** GPIO_INTR_3_REG register
+ *  GPIO interrupt 3 status register for GPIO0-31
+ */
+#define GPIO_INTR_3_REG (DR_REG_GPIO_BASE + 0x644)
+/** GPIO_INT_3 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 3 status register for GPIO0-31
+ */
+#define GPIO_INT_3    0xFFFFFFFFU
+#define GPIO_INT_3_M  (GPIO_INT_3_V << GPIO_INT_3_S)
+#define GPIO_INT_3_V  0xFFFFFFFFU
+#define GPIO_INT_3_S  0
+
+/** GPIO_INTR1_3_REG register
+ *  GPIO interrupt 3 status register for GPIO32-56
+ */
+#define GPIO_INTR1_3_REG (DR_REG_GPIO_BASE + 0x648)
+/** GPIO_INT1_3 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 3 status register for GPIO32-56
+ */
+#define GPIO_INT1_3    0x01FFFFFFU
+#define GPIO_INT1_3_M  (GPIO_INT1_3_V << GPIO_INT1_3_S)
+#define GPIO_INT1_3_V  0x01FFFFFFU
+#define GPIO_INT1_3_S  0
+
+/** GPIO_CLOCK_GATE_REG register
+ *  GPIO clock gate register
+ */
+#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x64c)
+/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  set this bit to enable GPIO clock gate
+ */
+#define GPIO_CLK_EN    (BIT(0))
+#define GPIO_CLK_EN_M  (GPIO_CLK_EN_V << GPIO_CLK_EN_S)
+#define GPIO_CLK_EN_V  0x00000001U
+#define GPIO_CLK_EN_S  0
+
+/** GPIO_INT_RAW_REG register
+ *  analog comparator interrupt raw
+ */
+#define GPIO_INT_RAW_REG (DR_REG_GPIO_BASE + 0x700)
+/** GPIO_COMP0_NEG_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  analog comparator pos edge interrupt raw
+ */
+#define GPIO_COMP0_NEG_INT_RAW    (BIT(0))
+#define GPIO_COMP0_NEG_INT_RAW_M  (GPIO_COMP0_NEG_INT_RAW_V << GPIO_COMP0_NEG_INT_RAW_S)
+#define GPIO_COMP0_NEG_INT_RAW_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_RAW_S  0
+/** GPIO_COMP0_POS_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  analog comparator neg edge interrupt raw
+ */
+#define GPIO_COMP0_POS_INT_RAW    (BIT(1))
+#define GPIO_COMP0_POS_INT_RAW_M  (GPIO_COMP0_POS_INT_RAW_V << GPIO_COMP0_POS_INT_RAW_S)
+#define GPIO_COMP0_POS_INT_RAW_V  0x00000001U
+#define GPIO_COMP0_POS_INT_RAW_S  1
+/** GPIO_COMP0_ALL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  analog comparator neg or pos edge interrupt raw
+ */
+#define GPIO_COMP0_ALL_INT_RAW    (BIT(2))
+#define GPIO_COMP0_ALL_INT_RAW_M  (GPIO_COMP0_ALL_INT_RAW_V << GPIO_COMP0_ALL_INT_RAW_S)
+#define GPIO_COMP0_ALL_INT_RAW_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_RAW_S  2
+/** GPIO_COMP1_NEG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  analog comparator pos edge interrupt raw
+ */
+#define GPIO_COMP1_NEG_INT_RAW    (BIT(3))
+#define GPIO_COMP1_NEG_INT_RAW_M  (GPIO_COMP1_NEG_INT_RAW_V << GPIO_COMP1_NEG_INT_RAW_S)
+#define GPIO_COMP1_NEG_INT_RAW_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_RAW_S  3
+/** GPIO_COMP1_POS_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  analog comparator neg edge interrupt raw
+ */
+#define GPIO_COMP1_POS_INT_RAW    (BIT(4))
+#define GPIO_COMP1_POS_INT_RAW_M  (GPIO_COMP1_POS_INT_RAW_V << GPIO_COMP1_POS_INT_RAW_S)
+#define GPIO_COMP1_POS_INT_RAW_V  0x00000001U
+#define GPIO_COMP1_POS_INT_RAW_S  4
+/** GPIO_COMP1_ALL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  analog comparator neg or pos edge interrupt raw
+ */
+#define GPIO_COMP1_ALL_INT_RAW    (BIT(5))
+#define GPIO_COMP1_ALL_INT_RAW_M  (GPIO_COMP1_ALL_INT_RAW_V << GPIO_COMP1_ALL_INT_RAW_S)
+#define GPIO_COMP1_ALL_INT_RAW_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_RAW_S  5
+/** GPIO_BISTOK_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  pad bistok interrupt raw
+ */
+#define GPIO_BISTOK_INT_RAW    (BIT(6))
+#define GPIO_BISTOK_INT_RAW_M  (GPIO_BISTOK_INT_RAW_V << GPIO_BISTOK_INT_RAW_S)
+#define GPIO_BISTOK_INT_RAW_V  0x00000001U
+#define GPIO_BISTOK_INT_RAW_S  6
+/** GPIO_BISTFAIL_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  pad bistfail interrupt raw
+ */
+#define GPIO_BISTFAIL_INT_RAW    (BIT(7))
+#define GPIO_BISTFAIL_INT_RAW_M  (GPIO_BISTFAIL_INT_RAW_V << GPIO_BISTFAIL_INT_RAW_S)
+#define GPIO_BISTFAIL_INT_RAW_V  0x00000001U
+#define GPIO_BISTFAIL_INT_RAW_S  7
+
+/** GPIO_INT_ST_REG register
+ *  analog comparator interrupt status
+ */
+#define GPIO_INT_ST_REG (DR_REG_GPIO_BASE + 0x704)
+/** GPIO_COMP0_NEG_INT_ST : RO; bitpos: [0]; default: 0;
+ *  analog comparator pos edge interrupt status
+ */
+#define GPIO_COMP0_NEG_INT_ST    (BIT(0))
+#define GPIO_COMP0_NEG_INT_ST_M  (GPIO_COMP0_NEG_INT_ST_V << GPIO_COMP0_NEG_INT_ST_S)
+#define GPIO_COMP0_NEG_INT_ST_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_ST_S  0
+/** GPIO_COMP0_POS_INT_ST : RO; bitpos: [1]; default: 0;
+ *  analog comparator neg edge interrupt status
+ */
+#define GPIO_COMP0_POS_INT_ST    (BIT(1))
+#define GPIO_COMP0_POS_INT_ST_M  (GPIO_COMP0_POS_INT_ST_V << GPIO_COMP0_POS_INT_ST_S)
+#define GPIO_COMP0_POS_INT_ST_V  0x00000001U
+#define GPIO_COMP0_POS_INT_ST_S  1
+/** GPIO_COMP0_ALL_INT_ST : RO; bitpos: [2]; default: 0;
+ *  analog comparator neg or pos edge interrupt status
+ */
+#define GPIO_COMP0_ALL_INT_ST    (BIT(2))
+#define GPIO_COMP0_ALL_INT_ST_M  (GPIO_COMP0_ALL_INT_ST_V << GPIO_COMP0_ALL_INT_ST_S)
+#define GPIO_COMP0_ALL_INT_ST_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_ST_S  2
+/** GPIO_COMP1_NEG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  analog comparator pos edge interrupt status
+ */
+#define GPIO_COMP1_NEG_INT_ST    (BIT(3))
+#define GPIO_COMP1_NEG_INT_ST_M  (GPIO_COMP1_NEG_INT_ST_V << GPIO_COMP1_NEG_INT_ST_S)
+#define GPIO_COMP1_NEG_INT_ST_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_ST_S  3
+/** GPIO_COMP1_POS_INT_ST : RO; bitpos: [4]; default: 0;
+ *  analog comparator neg edge interrupt status
+ */
+#define GPIO_COMP1_POS_INT_ST    (BIT(4))
+#define GPIO_COMP1_POS_INT_ST_M  (GPIO_COMP1_POS_INT_ST_V << GPIO_COMP1_POS_INT_ST_S)
+#define GPIO_COMP1_POS_INT_ST_V  0x00000001U
+#define GPIO_COMP1_POS_INT_ST_S  4
+/** GPIO_COMP1_ALL_INT_ST : RO; bitpos: [5]; default: 0;
+ *  analog comparator neg or pos edge interrupt status
+ */
+#define GPIO_COMP1_ALL_INT_ST    (BIT(5))
+#define GPIO_COMP1_ALL_INT_ST_M  (GPIO_COMP1_ALL_INT_ST_V << GPIO_COMP1_ALL_INT_ST_S)
+#define GPIO_COMP1_ALL_INT_ST_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_ST_S  5
+/** GPIO_BISTOK_INT_ST : RO; bitpos: [6]; default: 0;
+ *  pad bistok interrupt status
+ */
+#define GPIO_BISTOK_INT_ST    (BIT(6))
+#define GPIO_BISTOK_INT_ST_M  (GPIO_BISTOK_INT_ST_V << GPIO_BISTOK_INT_ST_S)
+#define GPIO_BISTOK_INT_ST_V  0x00000001U
+#define GPIO_BISTOK_INT_ST_S  6
+/** GPIO_BISTFAIL_INT_ST : RO; bitpos: [7]; default: 0;
+ *  pad bistfail interrupt status
+ */
+#define GPIO_BISTFAIL_INT_ST    (BIT(7))
+#define GPIO_BISTFAIL_INT_ST_M  (GPIO_BISTFAIL_INT_ST_V << GPIO_BISTFAIL_INT_ST_S)
+#define GPIO_BISTFAIL_INT_ST_V  0x00000001U
+#define GPIO_BISTFAIL_INT_ST_S  7
+
+/** GPIO_INT_ENA_REG register
+ *  analog comparator interrupt enable
+ */
+#define GPIO_INT_ENA_REG (DR_REG_GPIO_BASE + 0x708)
+/** GPIO_COMP0_NEG_INT_ENA : R/W; bitpos: [0]; default: 1;
+ *  analog comparator pos edge interrupt enable
+ */
+#define GPIO_COMP0_NEG_INT_ENA    (BIT(0))
+#define GPIO_COMP0_NEG_INT_ENA_M  (GPIO_COMP0_NEG_INT_ENA_V << GPIO_COMP0_NEG_INT_ENA_S)
+#define GPIO_COMP0_NEG_INT_ENA_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_ENA_S  0
+/** GPIO_COMP0_POS_INT_ENA : R/W; bitpos: [1]; default: 1;
+ *  analog comparator neg edge interrupt enable
+ */
+#define GPIO_COMP0_POS_INT_ENA    (BIT(1))
+#define GPIO_COMP0_POS_INT_ENA_M  (GPIO_COMP0_POS_INT_ENA_V << GPIO_COMP0_POS_INT_ENA_S)
+#define GPIO_COMP0_POS_INT_ENA_V  0x00000001U
+#define GPIO_COMP0_POS_INT_ENA_S  1
+/** GPIO_COMP0_ALL_INT_ENA : R/W; bitpos: [2]; default: 1;
+ *  analog comparator neg or pos edge interrupt enable
+ */
+#define GPIO_COMP0_ALL_INT_ENA    (BIT(2))
+#define GPIO_COMP0_ALL_INT_ENA_M  (GPIO_COMP0_ALL_INT_ENA_V << GPIO_COMP0_ALL_INT_ENA_S)
+#define GPIO_COMP0_ALL_INT_ENA_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_ENA_S  2
+/** GPIO_COMP1_NEG_INT_ENA : R/W; bitpos: [3]; default: 1;
+ *  analog comparator pos edge interrupt enable
+ */
+#define GPIO_COMP1_NEG_INT_ENA    (BIT(3))
+#define GPIO_COMP1_NEG_INT_ENA_M  (GPIO_COMP1_NEG_INT_ENA_V << GPIO_COMP1_NEG_INT_ENA_S)
+#define GPIO_COMP1_NEG_INT_ENA_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_ENA_S  3
+/** GPIO_COMP1_POS_INT_ENA : R/W; bitpos: [4]; default: 1;
+ *  analog comparator neg edge interrupt enable
+ */
+#define GPIO_COMP1_POS_INT_ENA    (BIT(4))
+#define GPIO_COMP1_POS_INT_ENA_M  (GPIO_COMP1_POS_INT_ENA_V << GPIO_COMP1_POS_INT_ENA_S)
+#define GPIO_COMP1_POS_INT_ENA_V  0x00000001U
+#define GPIO_COMP1_POS_INT_ENA_S  4
+/** GPIO_COMP1_ALL_INT_ENA : R/W; bitpos: [5]; default: 1;
+ *  analog comparator neg or pos edge interrupt enable
+ */
+#define GPIO_COMP1_ALL_INT_ENA    (BIT(5))
+#define GPIO_COMP1_ALL_INT_ENA_M  (GPIO_COMP1_ALL_INT_ENA_V << GPIO_COMP1_ALL_INT_ENA_S)
+#define GPIO_COMP1_ALL_INT_ENA_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_ENA_S  5
+/** GPIO_BISTOK_INT_ENA : R/W; bitpos: [6]; default: 1;
+ *  pad bistok interrupt enable
+ */
+#define GPIO_BISTOK_INT_ENA    (BIT(6))
+#define GPIO_BISTOK_INT_ENA_M  (GPIO_BISTOK_INT_ENA_V << GPIO_BISTOK_INT_ENA_S)
+#define GPIO_BISTOK_INT_ENA_V  0x00000001U
+#define GPIO_BISTOK_INT_ENA_S  6
+/** GPIO_BISTFAIL_INT_ENA : R/W; bitpos: [7]; default: 1;
+ *  pad bistfail interrupt enable
+ */
+#define GPIO_BISTFAIL_INT_ENA    (BIT(7))
+#define GPIO_BISTFAIL_INT_ENA_M  (GPIO_BISTFAIL_INT_ENA_V << GPIO_BISTFAIL_INT_ENA_S)
+#define GPIO_BISTFAIL_INT_ENA_V  0x00000001U
+#define GPIO_BISTFAIL_INT_ENA_S  7
+
+/** GPIO_INT_CLR_REG register
+ *  analog comparator interrupt clear
+ */
+#define GPIO_INT_CLR_REG (DR_REG_GPIO_BASE + 0x70c)
+/** GPIO_COMP0_NEG_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  analog comparator pos edge interrupt clear
+ */
+#define GPIO_COMP0_NEG_INT_CLR    (BIT(0))
+#define GPIO_COMP0_NEG_INT_CLR_M  (GPIO_COMP0_NEG_INT_CLR_V << GPIO_COMP0_NEG_INT_CLR_S)
+#define GPIO_COMP0_NEG_INT_CLR_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_CLR_S  0
+/** GPIO_COMP0_POS_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  analog comparator neg edge interrupt clear
+ */
+#define GPIO_COMP0_POS_INT_CLR    (BIT(1))
+#define GPIO_COMP0_POS_INT_CLR_M  (GPIO_COMP0_POS_INT_CLR_V << GPIO_COMP0_POS_INT_CLR_S)
+#define GPIO_COMP0_POS_INT_CLR_V  0x00000001U
+#define GPIO_COMP0_POS_INT_CLR_S  1
+/** GPIO_COMP0_ALL_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  analog comparator neg or pos edge interrupt clear
+ */
+#define GPIO_COMP0_ALL_INT_CLR    (BIT(2))
+#define GPIO_COMP0_ALL_INT_CLR_M  (GPIO_COMP0_ALL_INT_CLR_V << GPIO_COMP0_ALL_INT_CLR_S)
+#define GPIO_COMP0_ALL_INT_CLR_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_CLR_S  2
+/** GPIO_COMP1_NEG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  analog comparator pos edge interrupt clear
+ */
+#define GPIO_COMP1_NEG_INT_CLR    (BIT(3))
+#define GPIO_COMP1_NEG_INT_CLR_M  (GPIO_COMP1_NEG_INT_CLR_V << GPIO_COMP1_NEG_INT_CLR_S)
+#define GPIO_COMP1_NEG_INT_CLR_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_CLR_S  3
+/** GPIO_COMP1_POS_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  analog comparator neg edge interrupt clear
+ */
+#define GPIO_COMP1_POS_INT_CLR    (BIT(4))
+#define GPIO_COMP1_POS_INT_CLR_M  (GPIO_COMP1_POS_INT_CLR_V << GPIO_COMP1_POS_INT_CLR_S)
+#define GPIO_COMP1_POS_INT_CLR_V  0x00000001U
+#define GPIO_COMP1_POS_INT_CLR_S  4
+/** GPIO_COMP1_ALL_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  analog comparator neg or pos edge interrupt clear
+ */
+#define GPIO_COMP1_ALL_INT_CLR    (BIT(5))
+#define GPIO_COMP1_ALL_INT_CLR_M  (GPIO_COMP1_ALL_INT_CLR_V << GPIO_COMP1_ALL_INT_CLR_S)
+#define GPIO_COMP1_ALL_INT_CLR_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_CLR_S  5
+/** GPIO_BISTOK_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  pad bistok interrupt enable
+ */
+#define GPIO_BISTOK_INT_CLR    (BIT(6))
+#define GPIO_BISTOK_INT_CLR_M  (GPIO_BISTOK_INT_CLR_V << GPIO_BISTOK_INT_CLR_S)
+#define GPIO_BISTOK_INT_CLR_V  0x00000001U
+#define GPIO_BISTOK_INT_CLR_S  6
+/** GPIO_BISTFAIL_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  pad bistfail interrupt enable
+ */
+#define GPIO_BISTFAIL_INT_CLR    (BIT(7))
+#define GPIO_BISTFAIL_INT_CLR_M  (GPIO_BISTFAIL_INT_CLR_V << GPIO_BISTFAIL_INT_CLR_S)
+#define GPIO_BISTFAIL_INT_CLR_V  0x00000001U
+#define GPIO_BISTFAIL_INT_CLR_S  7
+
+/** GPIO_ZERO_DET0_FILTER_CNT_REG register
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET0_FILTER_CNT_REG (DR_REG_GPIO_BASE + 0x710)
+/** GPIO_ZERO_DET0_FILTER_CNT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET0_FILTER_CNT    0xFFFFFFFFU
+#define GPIO_ZERO_DET0_FILTER_CNT_M  (GPIO_ZERO_DET0_FILTER_CNT_V << GPIO_ZERO_DET0_FILTER_CNT_S)
+#define GPIO_ZERO_DET0_FILTER_CNT_V  0xFFFFFFFFU
+#define GPIO_ZERO_DET0_FILTER_CNT_S  0
+
+/** GPIO_ZERO_DET1_FILTER_CNT_REG register
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET1_FILTER_CNT_REG (DR_REG_GPIO_BASE + 0x714)
+/** GPIO_ZERO_DET1_FILTER_CNT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET1_FILTER_CNT    0xFFFFFFFFU
+#define GPIO_ZERO_DET1_FILTER_CNT_M  (GPIO_ZERO_DET1_FILTER_CNT_V << GPIO_ZERO_DET1_FILTER_CNT_S)
+#define GPIO_ZERO_DET1_FILTER_CNT_V  0xFFFFFFFFU
+#define GPIO_ZERO_DET1_FILTER_CNT_S  0
+
+/** GPIO_SEND_SEQ_REG register
+ *  High speed sdio pad bist send sequence
+ */
+#define GPIO_SEND_SEQ_REG (DR_REG_GPIO_BASE + 0x718)
+/** GPIO_SEND_SEQ : R/W; bitpos: [31:0]; default: 305419896;
+ *  High speed sdio pad bist send sequence
+ */
+#define GPIO_SEND_SEQ    0xFFFFFFFFU
+#define GPIO_SEND_SEQ_M  (GPIO_SEND_SEQ_V << GPIO_SEND_SEQ_S)
+#define GPIO_SEND_SEQ_V  0xFFFFFFFFU
+#define GPIO_SEND_SEQ_S  0
+
+/** GPIO_RECIVE_SEQ_REG register
+ *  High speed sdio pad bist receive sequence
+ */
+#define GPIO_RECIVE_SEQ_REG (DR_REG_GPIO_BASE + 0x71c)
+/** GPIO_RECIVE_SEQ : RO; bitpos: [31:0]; default: 0;
+ *  High speed sdio pad bist receive sequence
+ */
+#define GPIO_RECIVE_SEQ    0xFFFFFFFFU
+#define GPIO_RECIVE_SEQ_M  (GPIO_RECIVE_SEQ_V << GPIO_RECIVE_SEQ_S)
+#define GPIO_RECIVE_SEQ_V  0xFFFFFFFFU
+#define GPIO_RECIVE_SEQ_S  0
+
+/** GPIO_BISTIN_SEL_REG register
+ *  High speed sdio pad bist in pad sel
+ */
+#define GPIO_BISTIN_SEL_REG (DR_REG_GPIO_BASE + 0x720)
+/** GPIO_BISTIN_SEL : R/W; bitpos: [3:0]; default: 15;
+ *  High speed sdio pad bist in pad sel 0:pad39, 1: pad40...
+ */
+#define GPIO_BISTIN_SEL    0x0000000FU
+#define GPIO_BISTIN_SEL_M  (GPIO_BISTIN_SEL_V << GPIO_BISTIN_SEL_S)
+#define GPIO_BISTIN_SEL_V  0x0000000FU
+#define GPIO_BISTIN_SEL_S  0
+
+/** GPIO_BIST_CTRL_REG register
+ *  High speed sdio pad bist control
+ */
+#define GPIO_BIST_CTRL_REG (DR_REG_GPIO_BASE + 0x724)
+/** GPIO_BIST_PAD_OE : R/W; bitpos: [0]; default: 1;
+ *  High speed sdio pad bist out pad oe
+ */
+#define GPIO_BIST_PAD_OE    (BIT(0))
+#define GPIO_BIST_PAD_OE_M  (GPIO_BIST_PAD_OE_V << GPIO_BIST_PAD_OE_S)
+#define GPIO_BIST_PAD_OE_V  0x00000001U
+#define GPIO_BIST_PAD_OE_S  0
+/** GPIO_BIST_START : WT; bitpos: [1]; default: 0;
+ *  High speed sdio pad bist start
+ */
+#define GPIO_BIST_START    (BIT(1))
+#define GPIO_BIST_START_M  (GPIO_BIST_START_V << GPIO_BIST_START_S)
+#define GPIO_BIST_START_V  0x00000001U
+#define GPIO_BIST_START_S  1
+/** GPIO_BIST_MODE : R/W; bitpos: [2]; default: 0;
+ *  Set 1 to enable sdio pad ddr200 bist mode
+ */
+#define GPIO_BIST_MODE    (BIT(2))
+#define GPIO_BIST_MODE_M  (GPIO_BIST_MODE_V << GPIO_BIST_MODE_S)
+#define GPIO_BIST_MODE_V  0x00000001U
+#define GPIO_BIST_MODE_S  2
+
+/** GPIO_DATE_REG register
+ *  GPIO version register
+ */
+#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x7fc)
+/** GPIO_DATE : R/W; bitpos: [27:0]; default: 2363942;
+ *  version register
+ */
+#define GPIO_DATE    0x0FFFFFFFU
+#define GPIO_DATE_M  (GPIO_DATE_V << GPIO_DATE_S)
+#define GPIO_DATE_V  0x0FFFFFFFU
+#define GPIO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/gpio_sig_map.h b/components/soc/esp32p4/register/hw_ver2/soc/gpio_sig_map.h
new file mode 100644
index 0000000000..65c4a503c0
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/gpio_sig_map.h
@@ -0,0 +1,483 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define SD_CARD_CCLK_2_PAD_OUT_IDX               0
+#define SD_CARD_CCMD_2_PAD_IN_IDX                1
+#define SD_CARD_CCMD_2_PAD_OUT_IDX               1
+#define SD_CARD_CDATA0_2_PAD_IN_IDX              2
+#define SD_CARD_CDATA0_2_PAD_OUT_IDX             2
+#define SD_CARD_CDATA1_2_PAD_IN_IDX              3
+#define SD_CARD_CDATA1_2_PAD_OUT_IDX             3
+#define SD_CARD_CDATA2_2_PAD_IN_IDX              4
+#define SD_CARD_CDATA2_2_PAD_OUT_IDX             4
+#define SD_CARD_CDATA3_2_PAD_IN_IDX              5
+#define SD_CARD_CDATA3_2_PAD_OUT_IDX             5
+#define SD_CARD_CDATA4_2_PAD_IN_IDX              6
+#define SD_CARD_CDATA4_2_PAD_OUT_IDX             6
+#define SD_CARD_CDATA5_2_PAD_IN_IDX              7
+#define SD_CARD_CDATA5_2_PAD_OUT_IDX             7
+#define SD_CARD_CDATA6_2_PAD_IN_IDX              8
+#define SD_CARD_CDATA6_2_PAD_OUT_IDX             8
+#define SD_CARD_CDATA7_2_PAD_IN_IDX              9
+#define SD_CARD_CDATA7_2_PAD_OUT_IDX             9
+#define UART0_RXD_PAD_IN_IDX                     10
+#define UART0_TXD_PAD_OUT_IDX                    10
+#define UART0_CTS_PAD_IN_IDX                     11
+#define UART0_RTS_PAD_OUT_IDX                    11
+#define UART0_DSR_PAD_IN_IDX                     12
+#define UART0_DTR_PAD_OUT_IDX                    12
+#define UART1_RXD_PAD_IN_IDX                     13
+#define UART1_TXD_PAD_OUT_IDX                    13
+#define UART1_CTS_PAD_IN_IDX                     14
+#define UART1_RTS_PAD_OUT_IDX                    14
+#define UART1_DSR_PAD_IN_IDX                     15
+#define UART1_DTR_PAD_OUT_IDX                    15
+#define UART2_RXD_PAD_IN_IDX                     16
+#define UART2_TXD_PAD_OUT_IDX                    16
+#define UART2_CTS_PAD_IN_IDX                     17
+#define UART2_RTS_PAD_OUT_IDX                    17
+#define UART2_DSR_PAD_IN_IDX                     18
+#define UART2_DTR_PAD_OUT_IDX                    18
+#define UART3_RXD_PAD_IN_IDX                     19
+#define UART3_TXD_PAD_OUT_IDX                    19
+#define UART3_CTS_PAD_IN_IDX                     20
+#define UART3_RTS_PAD_OUT_IDX                    20
+#define UART3_DSR_PAD_IN_IDX                     21
+#define UART3_DTR_PAD_OUT_IDX                    21
+#define UART4_RXD_PAD_IN_IDX                     22
+#define UART4_TXD_PAD_OUT_IDX                    22
+#define UART4_CTS_PAD_IN_IDX                     23
+#define UART4_RTS_PAD_OUT_IDX                    23
+#define UART4_DSR_PAD_IN_IDX                     24
+#define UART4_DTR_PAD_OUT_IDX                    24
+#define I2S0_O_BCK_PAD_IN_IDX                    25
+#define I2S0_O_BCK_PAD_OUT_IDX                   25
+#define I2S0_MCLK_PAD_IN_IDX                     26
+#define I2S0_MCLK_PAD_OUT_IDX                    26
+#define I2S0_O_WS_PAD_IN_IDX                     27
+#define I2S0_O_WS_PAD_OUT_IDX                    27
+#define I2S0_I_SD_PAD_IN_IDX                     28
+#define I2S0_O_SD_PAD_OUT_IDX                    28
+#define I2S0_I_BCK_PAD_IN_IDX                    29
+#define I2S0_I_BCK_PAD_OUT_IDX                   29
+#define I2S0_I_WS_PAD_IN_IDX                     30
+#define I2S0_I_WS_PAD_OUT_IDX                    30
+#define I2S1_O_BCK_PAD_IN_IDX                    31
+#define I2S1_O_BCK_PAD_OUT_IDX                   31
+#define I2S1_MCLK_PAD_IN_IDX                     32
+#define I2S1_MCLK_PAD_OUT_IDX                    32
+#define I2S1_O_WS_PAD_IN_IDX                     33
+#define I2S1_O_WS_PAD_OUT_IDX                    33
+#define I2S1_I_SD_PAD_IN_IDX                     34
+#define I2S1_O_SD_PAD_OUT_IDX                    34
+#define I2S1_I_BCK_PAD_IN_IDX                    35
+#define I2S1_I_BCK_PAD_OUT_IDX                   35
+#define I2S1_I_WS_PAD_IN_IDX                     36
+#define I2S1_I_WS_PAD_OUT_IDX                    36
+#define I2S2_O_BCK_PAD_IN_IDX                    37
+#define I2S2_O_BCK_PAD_OUT_IDX                   37
+#define I2S2_MCLK_PAD_IN_IDX                     38
+#define I2S2_MCLK_PAD_OUT_IDX                    38
+#define I2S2_O_WS_PAD_IN_IDX                     39
+#define I2S2_O_WS_PAD_OUT_IDX                    39
+#define I2S2_I_SD_PAD_IN_IDX                     40
+#define I2S2_O_SD_PAD_OUT_IDX                    40
+#define I2S2_I_BCK_PAD_IN_IDX                    41
+#define I2S2_I_BCK_PAD_OUT_IDX                   41
+#define I2S2_I_WS_PAD_IN_IDX                     42
+#define I2S2_I_WS_PAD_OUT_IDX                    42
+#define I2S0_I_SD1_PAD_IN_IDX                    43
+#define I2S0_O_SD1_PAD_OUT_IDX                   43
+#define I2S0_I_SD2_PAD_IN_IDX                    44
+#define SPI2_DQS_PAD_OUT_IDX                     44
+#define I2S0_I_SD3_PAD_IN_IDX                    45
+#define SPI3_CS2_PAD_OUT_IDX                     45
+#define SPI3_CS1_PAD_OUT_IDX                     46
+#define SPI3_CK_PAD_IN_IDX                       47
+#define SPI3_CK_PAD_OUT_IDX                      47
+#define SPI3_Q_PAD_IN_IDX                        48
+#define SPI3_QO_PAD_OUT_IDX                      48
+#define SPI3_D_PAD_IN_IDX                        49
+#define SPI3_D_PAD_OUT_IDX                       49
+#define SPI3_HOLD_PAD_IN_IDX                     50
+#define SPI3_HOLD_PAD_OUT_IDX                    50
+#define SPI3_WP_PAD_IN_IDX                       51
+#define SPI3_WP_PAD_OUT_IDX                      51
+#define SPI3_CS_PAD_IN_IDX                       52
+#define SPI3_CS_PAD_OUT_IDX                      52
+#define SPI2_CK_PAD_IN_IDX                       53
+#define SPI2_CK_PAD_OUT_IDX                      53
+#define SPI2_Q_PAD_IN_IDX                        54
+#define SPI2_Q_PAD_OUT_IDX                       54
+#define SPI2_D_PAD_IN_IDX                        55
+#define SPI2_D_PAD_OUT_IDX                       55
+#define SPI2_HOLD_PAD_IN_IDX                     56
+#define SPI2_HOLD_PAD_OUT_IDX                    56
+#define SPI2_WP_PAD_IN_IDX                       57
+#define SPI2_WP_PAD_OUT_IDX                      57
+#define SPI2_IO4_PAD_IN_IDX                      58
+#define SPI2_IO4_PAD_OUT_IDX                     58
+#define SPI2_IO5_PAD_IN_IDX                      59
+#define SPI2_IO5_PAD_OUT_IDX                     59
+#define SPI2_IO6_PAD_IN_IDX                      60
+#define SPI2_IO6_PAD_OUT_IDX                     60
+#define SPI2_IO7_PAD_IN_IDX                      61
+#define SPI2_IO7_PAD_OUT_IDX                     61
+#define SPI2_CS_PAD_IN_IDX                       62
+#define SPI2_CS_PAD_OUT_IDX                      62
+#define PCNT_RST_PAD_IN0_IDX                     63
+#define SPI2_CS1_PAD_OUT_IDX                     63
+#define PCNT_RST_PAD_IN1_IDX                     64
+#define SPI2_CS2_PAD_OUT_IDX                     64
+#define PCNT_RST_PAD_IN2_IDX                     65
+#define SPI2_CS3_PAD_OUT_IDX                     65
+#define PCNT_RST_PAD_IN3_IDX                     66
+#define SPI2_CS4_PAD_OUT_IDX                     66
+#define SPI2_CS5_PAD_OUT_IDX                     67
+#define I2C0_SCL_PAD_IN_IDX                      68
+#define I2C0_SCL_PAD_OUT_IDX                     68
+#define I2C0_SDA_PAD_IN_IDX                      69
+#define I2C0_SDA_PAD_OUT_IDX                     69
+#define I2C1_SCL_PAD_IN_IDX                      70
+#define I2C1_SCL_PAD_OUT_IDX                     70
+#define I2C1_SDA_PAD_IN_IDX                      71
+#define I2C1_SDA_PAD_OUT_IDX                     71
+#define GPIO_SD0_OUT_IDX                         72
+#define GPIO_SD1_OUT_IDX                         73
+#define UART0_SLP_CLK_PAD_IN_IDX                 74
+#define GPIO_SD2_OUT_IDX                         74
+#define UART1_SLP_CLK_PAD_IN_IDX                 75
+#define GPIO_SD3_OUT_IDX                         75
+#define UART2_SLP_CLK_PAD_IN_IDX                 76
+#define GPIO_SD4_OUT_IDX                         76
+#define UART3_SLP_CLK_PAD_IN_IDX                 77
+#define GPIO_SD5_OUT_IDX                         77
+#define UART4_SLP_CLK_PAD_IN_IDX                 78
+#define GPIO_SD6_OUT_IDX                         78
+#define GPIO_SD7_OUT_IDX                         79
+#define TWAI0_RX_PAD_IN_IDX                      80
+#define TWAI0_TX_PAD_OUT_IDX                     80
+#define TWAI0_BUS_OFF_ON_PAD_OUT_IDX             81
+#define TWAI0_CLKOUT_PAD_OUT_IDX                 82
+#define TWAI1_RX_PAD_IN_IDX                      83
+#define TWAI1_TX_PAD_OUT_IDX                     83
+#define TWAI1_BUS_OFF_ON_PAD_OUT_IDX             84
+#define TWAI1_CLKOUT_PAD_OUT_IDX                 85
+#define TWAI2_RX_PAD_IN_IDX                      86
+#define TWAI2_TX_PAD_OUT_IDX                     86
+#define TWAI2_BUS_OFF_ON_PAD_OUT_IDX             87
+#define TWAI2_CLKOUT_PAD_OUT_IDX                 88
+#define PWM0_SYNC0_PAD_IN_IDX                    89
+#define PWM0_CH0_A_PAD_OUT_IDX                   89
+#define PWM0_SYNC1_PAD_IN_IDX                    90
+#define PWM0_CH0_B_PAD_OUT_IDX                   90
+#define PWM0_SYNC2_PAD_IN_IDX                    91
+#define PWM0_CH1_A_PAD_OUT_IDX                   91
+#define PWM0_F0_PAD_IN_IDX                       92
+#define PWM0_CH1_B_PAD_OUT_IDX                   92
+#define PWM0_F1_PAD_IN_IDX                       93
+#define PWM0_CH2_A_PAD_OUT_IDX                   93
+#define PWM0_F2_PAD_IN_IDX                       94
+#define PWM0_CH2_B_PAD_OUT_IDX                   94
+#define PWM0_CAP0_PAD_IN_IDX                     95
+#define PWM1_CH0_A_PAD_OUT_IDX                   95
+#define PWM0_CAP1_PAD_IN_IDX                     96
+#define PWM1_CH0_B_PAD_OUT_IDX                   96
+#define PWM0_CAP2_PAD_IN_IDX                     97
+#define PWM1_CH1_A_PAD_OUT_IDX                   97
+#define PWM1_SYNC0_PAD_IN_IDX                    98
+#define PWM1_CH1_B_PAD_OUT_IDX                   98
+#define PWM1_SYNC1_PAD_IN_IDX                    99
+#define PWM1_CH2_A_PAD_OUT_IDX                   99
+#define PWM1_SYNC2_PAD_IN_IDX                    100
+#define PWM1_CH2_B_PAD_OUT_IDX                   100
+#define PWM1_F0_PAD_IN_IDX                       101
+#define PWM1_F1_PAD_IN_IDX                       102
+#define PWM1_F2_PAD_IN_IDX                       103
+#define PWM1_CAP0_PAD_IN_IDX                     104
+#define PWM1_CAP1_PAD_IN_IDX                     105
+#define TWAI0_STANDBY_PAD_OUT_IDX                105
+#define PWM1_CAP2_PAD_IN_IDX                     106
+#define TWAI1_STANDBY_PAD_OUT_IDX                106
+#define GMII_MDI_PAD_IN_IDX                      107
+#define TWAI2_STANDBY_PAD_OUT_IDX                107
+#define GMAC_PHY_COL_PAD_IN_IDX                  108
+#define GMII_MDC_PAD_OUT_IDX                     108
+#define GMAC_PHY_CRS_PAD_IN_IDX                  109
+#define GMII_MDO_PAD_OUT_IDX                     109
+#define USB_OTG11_IDDIG_PAD_IN_IDX               110
+#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX          110
+#define USB_OTG11_AVALID_PAD_IN_IDX              111
+#define USB_OTG11_IDPULLUP_PAD_OUT_IDX           111
+#define USB_SRP_BVALID_PAD_IN_IDX                112
+#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX         112
+#define USB_OTG11_VBUSVALID_PAD_IN_IDX           113
+#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX         113
+#define USB_SRP_SESSEND_PAD_IN_IDX               114
+#define USB_OTG11_DRVVBUS_PAD_OUT_IDX            114
+#define USB_SRP_CHRGVBUS_PAD_OUT_IDX             115
+#define ULPI_CLK_PAD_IN_IDX                      117
+#define RNG_CHAIN_CLK_PAD_OUT_IDX                117
+#define USB_HSPHY_REFCLK_IN_IDX                  118
+#define HP_PROBE_TOP_OUT0_IDX                    118
+#define HP_PROBE_TOP_OUT1_IDX                    119
+#define HP_PROBE_TOP_OUT2_IDX                    120
+#define HP_PROBE_TOP_OUT3_IDX                    121
+#define HP_PROBE_TOP_OUT4_IDX                    122
+#define HP_PROBE_TOP_OUT5_IDX                    123
+#define HP_PROBE_TOP_OUT6_IDX                    124
+#define HP_PROBE_TOP_OUT7_IDX                    125
+#define SD_CARD_DETECT_N_1_PAD_IN_IDX            126
+#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX             126
+#define SD_CARD_DETECT_N_2_PAD_IN_IDX            127
+#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX             127
+#define SD_CARD_INT_N_1_PAD_IN_IDX               128
+#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX             128
+#define SD_CARD_INT_N_2_PAD_IN_IDX               129
+#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX             129
+#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX           130
+#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX             130
+#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX           131
+#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX             131
+#define SD_DATA_STROBE_1_PAD_IN_IDX              132
+#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX             132
+#define SD_DATA_STROBE_2_PAD_IN_IDX              133
+#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX             133
+#define I3C_MST_SCL_PAD_IN_IDX                   134
+#define I3C_MST_SCL_PAD_OUT_IDX                  134
+#define I3C_MST_SDA_PAD_IN_IDX                   135
+#define I3C_MST_SDA_PAD_OUT_IDX                  135
+#define I3C_SLV_SCL_PAD_IN_IDX                   136
+#define I3C_SLV_SCL_PAD_OUT_IDX                  136
+#define I3C_SLV_SDA_PAD_IN_IDX                   137
+#define I3C_SLV_SDA_PAD_OUT_IDX                  137
+#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX        138
+#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX        139
+#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX           140
+#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX          140
+#define PCNT_SIG_CH0_PAD_IN0_IDX                 141
+#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX          141
+#define PCNT_SIG_CH0_PAD_IN1_IDX                 142
+#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX          142
+#define PCNT_SIG_CH0_PAD_IN2_IDX                 143
+#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX         143
+#define PCNT_SIG_CH0_PAD_IN3_IDX                 144
+#define LCD_CS_PAD_OUT_IDX                       144
+#define PCNT_SIG_CH1_PAD_IN0_IDX                 145
+#define LCD_DC_PAD_OUT_IDX                       145
+#define PCNT_SIG_CH1_PAD_IN1_IDX                 146
+#define SD_RST_N_1_PAD_OUT_IDX                   146
+#define PCNT_SIG_CH1_PAD_IN2_IDX                 147
+#define SD_RST_N_2_PAD_OUT_IDX                   147
+#define PCNT_SIG_CH1_PAD_IN3_IDX                 148
+#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX       148
+#define PCNT_CTRL_CH0_PAD_IN0_IDX                149
+#define LCD_PCLK_PAD_OUT_IDX                     149
+#define PCNT_CTRL_CH0_PAD_IN1_IDX                150
+#define CAM_CLK_PAD_OUT_IDX                      150
+#define PCNT_CTRL_CH0_PAD_IN2_IDX                151
+#define LCD_H_ENABLE_PAD_OUT_IDX                 151
+#define PCNT_CTRL_CH0_PAD_IN3_IDX                152
+#define LCD_H_SYNC_PAD_OUT_IDX                   152
+#define PCNT_CTRL_CH1_PAD_IN0_IDX                153
+#define LCD_V_SYNC_PAD_OUT_IDX                   153
+#define PCNT_CTRL_CH1_PAD_IN1_IDX                154
+#define LCD_DATA_OUT_PAD_OUT0_IDX                154
+#define PCNT_CTRL_CH1_PAD_IN2_IDX                155
+#define LCD_DATA_OUT_PAD_OUT1_IDX                155
+#define PCNT_CTRL_CH1_PAD_IN3_IDX                156
+#define LCD_DATA_OUT_PAD_OUT2_IDX                156
+#define LCD_DATA_OUT_PAD_OUT3_IDX                157
+#define CAM_PCLK_PAD_IN_IDX                      158
+#define LCD_DATA_OUT_PAD_OUT4_IDX                158
+#define CAM_H_ENABLE_PAD_IN_IDX                  159
+#define LCD_DATA_OUT_PAD_OUT5_IDX                159
+#define CAM_H_SYNC_PAD_IN_IDX                    160
+#define LCD_DATA_OUT_PAD_OUT6_IDX                160
+#define CAM_V_SYNC_PAD_IN_IDX                    161
+#define LCD_DATA_OUT_PAD_OUT7_IDX                161
+#define CAM_DATA_IN_PAD_IN0_IDX                  162
+#define LCD_DATA_OUT_PAD_OUT8_IDX                162
+#define CAM_DATA_IN_PAD_IN1_IDX                  163
+#define LCD_DATA_OUT_PAD_OUT9_IDX                163
+#define CAM_DATA_IN_PAD_IN2_IDX                  164
+#define LCD_DATA_OUT_PAD_OUT10_IDX               164
+#define CAM_DATA_IN_PAD_IN3_IDX                  165
+#define LCD_DATA_OUT_PAD_OUT11_IDX               165
+#define CAM_DATA_IN_PAD_IN4_IDX                  166
+#define LCD_DATA_OUT_PAD_OUT12_IDX               166
+#define CAM_DATA_IN_PAD_IN5_IDX                  167
+#define LCD_DATA_OUT_PAD_OUT13_IDX               167
+#define CAM_DATA_IN_PAD_IN6_IDX                  168
+#define LCD_DATA_OUT_PAD_OUT14_IDX               168
+#define CAM_DATA_IN_PAD_IN7_IDX                  169
+#define LCD_DATA_OUT_PAD_OUT15_IDX               169
+#define CAM_DATA_IN_PAD_IN8_IDX                  170
+#define LCD_DATA_OUT_PAD_OUT16_IDX               170
+#define CAM_DATA_IN_PAD_IN9_IDX                  171
+#define LCD_DATA_OUT_PAD_OUT17_IDX               171
+#define CAM_DATA_IN_PAD_IN10_IDX                 172
+#define LCD_DATA_OUT_PAD_OUT18_IDX               172
+#define CAM_DATA_IN_PAD_IN11_IDX                 173
+#define LCD_DATA_OUT_PAD_OUT19_IDX               173
+#define CAM_DATA_IN_PAD_IN12_IDX                 174
+#define LCD_DATA_OUT_PAD_OUT20_IDX               174
+#define CAM_DATA_IN_PAD_IN13_IDX                 175
+#define LCD_DATA_OUT_PAD_OUT21_IDX               175
+#define CAM_DATA_IN_PAD_IN14_IDX                 176
+#define LCD_DATA_OUT_PAD_OUT22_IDX               176
+#define CAM_DATA_IN_PAD_IN15_IDX                 177
+#define LCD_DATA_OUT_PAD_OUT23_IDX               177
+#define GMAC_PHY_RXDV_PAD_IN_IDX                 178
+#define GMAC_PHY_TXEN_PAD_OUT_IDX                178
+#define GMAC_PHY_RXD0_PAD_IN_IDX                 179
+#define GMAC_PHY_TXD0_PAD_OUT_IDX                179
+#define GMAC_PHY_RXD1_PAD_IN_IDX                 180
+#define GMAC_PHY_TXD1_PAD_OUT_IDX                180
+#define GMAC_PHY_RXD2_PAD_IN_IDX                 181
+#define GMAC_PHY_TXD2_PAD_OUT_IDX                181
+#define GMAC_PHY_RXD3_PAD_IN_IDX                 182
+#define GMAC_PHY_TXD3_PAD_OUT_IDX                182
+#define GMAC_PHY_RXER_PAD_IN_IDX                 183
+#define GMAC_PHY_TXER_PAD_OUT_IDX                183
+#define GMAC_RX_CLK_PAD_IN_IDX                   184
+#define DBG_CH0_CLK_IDX                          184
+#define GMAC_TX_CLK_PAD_IN_IDX                   185
+#define DBG_CH1_CLK_IDX                          185
+#define PARLIO_RX_CLK_PAD_IN_IDX                 186
+#define PARLIO_RX_CLK_PAD_OUT_IDX                186
+#define PARLIO_TX_CLK_PAD_IN_IDX                 187
+#define PARLIO_TX_CLK_PAD_OUT_IDX                187
+#define PARLIO_RX_DATA0_PAD_IN_IDX               188
+#define PARLIO_TX_DATA0_PAD_OUT_IDX              188
+#define PARLIO_RX_DATA1_PAD_IN_IDX               189
+#define PARLIO_TX_DATA1_PAD_OUT_IDX              189
+#define PARLIO_RX_DATA2_PAD_IN_IDX               190
+#define PARLIO_TX_DATA2_PAD_OUT_IDX              190
+#define PARLIO_RX_DATA3_PAD_IN_IDX               191
+#define PARLIO_TX_DATA3_PAD_OUT_IDX              191
+#define PARLIO_RX_DATA4_PAD_IN_IDX               192
+#define PARLIO_TX_DATA4_PAD_OUT_IDX              192
+#define PARLIO_RX_DATA5_PAD_IN_IDX               193
+#define PARLIO_TX_DATA5_PAD_OUT_IDX              193
+#define PARLIO_RX_DATA6_PAD_IN_IDX               194
+#define PARLIO_TX_DATA6_PAD_OUT_IDX              194
+#define PARLIO_RX_DATA7_PAD_IN_IDX               195
+#define PARLIO_TX_DATA7_PAD_OUT_IDX              195
+#define PARLIO_RX_DATA8_PAD_IN_IDX               196
+#define PARLIO_TX_DATA8_PAD_OUT_IDX              196
+#define PARLIO_RX_DATA9_PAD_IN_IDX               197
+#define PARLIO_TX_DATA9_PAD_OUT_IDX              197
+#define PARLIO_RX_DATA10_PAD_IN_IDX              198
+#define PARLIO_TX_DATA10_PAD_OUT_IDX             198
+#define PARLIO_RX_DATA11_PAD_IN_IDX              199
+#define PARLIO_TX_DATA11_PAD_OUT_IDX             199
+#define PARLIO_RX_DATA12_PAD_IN_IDX              200
+#define PARLIO_TX_DATA12_PAD_OUT_IDX             200
+#define PARLIO_RX_DATA13_PAD_IN_IDX              201
+#define PARLIO_TX_DATA13_PAD_OUT_IDX             201
+#define PARLIO_RX_DATA14_PAD_IN_IDX              202
+#define PARLIO_TX_DATA14_PAD_OUT_IDX             202
+#define PARLIO_RX_DATA15_PAD_IN_IDX              203
+#define PARLIO_TX_DATA15_PAD_OUT_IDX             203
+#define HP_PROBE_TOP_OUT8_IDX                    204
+#define HP_PROBE_TOP_OUT9_IDX                    205
+#define HP_PROBE_TOP_OUT10_IDX                   206
+#define HP_PROBE_TOP_OUT11_IDX                   207
+#define HP_PROBE_TOP_OUT12_IDX                   208
+#define HP_PROBE_TOP_OUT13_IDX                   209
+#define HP_PROBE_TOP_OUT14_IDX                   210
+#define HP_PROBE_TOP_OUT15_IDX                   211
+#define CONSTANT0_PAD_OUT_IDX                    212
+#define CONSTANT1_PAD_OUT_IDX                    213
+#define CORE_GPIO_IN_PAD_IN0_IDX                 214
+#define CORE_GPIO_OUT_PAD_OUT0_IDX               214
+#define CORE_GPIO_IN_PAD_IN1_IDX                 215
+#define CORE_GPIO_OUT_PAD_OUT1_IDX               215
+#define CORE_GPIO_IN_PAD_IN2_IDX                 216
+#define CORE_GPIO_OUT_PAD_OUT2_IDX               216
+#define CORE_GPIO_IN_PAD_IN3_IDX                 217
+#define CORE_GPIO_OUT_PAD_OUT3_IDX               217
+#define CORE_GPIO_IN_PAD_IN4_IDX                 218
+#define CORE_GPIO_OUT_PAD_OUT4_IDX               218
+#define CORE_GPIO_IN_PAD_IN5_IDX                 219
+#define CORE_GPIO_OUT_PAD_OUT5_IDX               219
+#define CORE_GPIO_IN_PAD_IN6_IDX                 220
+#define CORE_GPIO_OUT_PAD_OUT6_IDX               220
+#define CORE_GPIO_IN_PAD_IN7_IDX                 221
+#define CORE_GPIO_OUT_PAD_OUT7_IDX               221
+#define CORE_GPIO_IN_PAD_IN8_IDX                 222
+#define CORE_GPIO_OUT_PAD_OUT8_IDX               222
+#define CORE_GPIO_IN_PAD_IN9_IDX                 223
+#define CORE_GPIO_OUT_PAD_OUT9_IDX               223
+#define CORE_GPIO_IN_PAD_IN10_IDX                224
+#define CORE_GPIO_OUT_PAD_OUT10_IDX              224
+#define CORE_GPIO_IN_PAD_IN11_IDX                225
+#define CORE_GPIO_OUT_PAD_OUT11_IDX              225
+#define CORE_GPIO_IN_PAD_IN12_IDX                226
+#define CORE_GPIO_OUT_PAD_OUT12_IDX              226
+#define CORE_GPIO_IN_PAD_IN13_IDX                227
+#define CORE_GPIO_OUT_PAD_OUT13_IDX              227
+#define CORE_GPIO_IN_PAD_IN14_IDX                228
+#define CORE_GPIO_OUT_PAD_OUT14_IDX              228
+#define CORE_GPIO_IN_PAD_IN15_IDX                229
+#define CORE_GPIO_OUT_PAD_OUT15_IDX              229
+#define CORE_GPIO_IN_PAD_IN16_IDX                230
+#define CORE_GPIO_OUT_PAD_OUT16_IDX              230
+#define CORE_GPIO_IN_PAD_IN17_IDX                231
+#define CORE_GPIO_OUT_PAD_OUT17_IDX              231
+#define CORE_GPIO_IN_PAD_IN18_IDX                232
+#define CORE_GPIO_OUT_PAD_OUT18_IDX              232
+#define CORE_GPIO_IN_PAD_IN19_IDX                233
+#define CORE_GPIO_OUT_PAD_OUT19_IDX              233
+#define CORE_GPIO_IN_PAD_IN20_IDX                234
+#define CORE_GPIO_OUT_PAD_OUT20_IDX              234
+#define CORE_GPIO_IN_PAD_IN21_IDX                235
+#define CORE_GPIO_OUT_PAD_OUT21_IDX              235
+#define CORE_GPIO_IN_PAD_IN22_IDX                236
+#define CORE_GPIO_OUT_PAD_OUT22_IDX              236
+#define CORE_GPIO_IN_PAD_IN23_IDX                237
+#define CORE_GPIO_OUT_PAD_OUT23_IDX              237
+#define CORE_GPIO_IN_PAD_IN24_IDX                238
+#define CORE_GPIO_OUT_PAD_OUT24_IDX              238
+#define CORE_GPIO_IN_PAD_IN25_IDX                239
+#define CORE_GPIO_OUT_PAD_OUT25_IDX              239
+#define CORE_GPIO_IN_PAD_IN26_IDX                240
+#define CORE_GPIO_OUT_PAD_OUT26_IDX              240
+#define CORE_GPIO_IN_PAD_IN27_IDX                241
+#define CORE_GPIO_OUT_PAD_OUT27_IDX              241
+#define CORE_GPIO_IN_PAD_IN28_IDX                242
+#define PARLIO_TX_CS_PAD_OUT_IDX                 242
+#define CORE_GPIO_IN_PAD_IN29_IDX                243
+#define EMAC_PTP_PPS_PAD_OUT_IDX                 243
+#define CORE_GPIO_IN_PAD_IN30_IDX                244
+#define ANA_COMP0_OUT_IDX                        244
+#define CORE_GPIO_IN_PAD_IN31_IDX                245
+#define ANA_COMP1_OUT_IDX                        245
+#define RMT_SIG_PAD_IN0_IDX                      246
+#define RMT_SIG_PAD_OUT0_IDX                     246
+#define RMT_SIG_PAD_IN1_IDX                      247
+#define RMT_SIG_PAD_OUT1_IDX                     247
+#define RMT_SIG_PAD_IN2_IDX                      248
+#define RMT_SIG_PAD_OUT2_IDX                     248
+#define RMT_SIG_PAD_IN3_IDX                      249
+#define RMT_SIG_PAD_OUT3_IDX                     249
+#define SIG_IN_FUNC250_IDX                       250
+#define SIG_IN_FUNC250_IDX                       250
+#define SIG_IN_FUNC251_IDX                       251
+#define SIG_IN_FUNC251_IDX                       251
+#define SIG_IN_FUNC252_IDX                       252
+#define SIG_IN_FUNC252_IDX                       252
+#define SIG_IN_FUNC253_IDX                       253
+#define SIG_IN_FUNC253_IDX                       253
+#define SIG_IN_FUNC254_IDX                       254
+#define SIG_IN_FUNC254_IDX                       254
+#define SIG_IN_FUNC255_IDX                       255
+#define SIG_IN_FUNC255_IDX                       255
+// version date 230403
+#define SIG_GPIO_OUT_IDX                        256
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/gpio_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/gpio_struct.h
new file mode 100644
index 0000000000..f986157531
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/gpio_struct.h
@@ -0,0 +1,878 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration register */
+/** Type of bt_select register
+ *  GPIO bit select register
+ */
+typedef union {
+    struct {
+        /** bt_sel : R/W; bitpos: [31:0]; default: 0;
+         *  GPIO bit select register
+         */
+        uint32_t bt_sel:32;
+    };
+    uint32_t val;
+} gpio_bt_select_reg_t;
+
+/** Type of out register
+ *  GPIO output register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+         *  GPIO output register for GPIO0-31
+         */
+        uint32_t out_data_orig:32;
+    };
+    uint32_t val;
+} gpio_out_reg_t;
+
+/** Type of out_w1ts register
+ *  GPIO output set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output set register for GPIO0-31
+         */
+        uint32_t out_w1ts:32;
+    };
+    uint32_t val;
+} gpio_out_w1ts_reg_t;
+
+/** Type of out_w1tc register
+ *  GPIO output clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output clear register for GPIO0-31
+         */
+        uint32_t out_w1tc:32;
+    };
+    uint32_t val;
+} gpio_out_w1tc_reg_t;
+
+/** Type of out1 register
+ *  GPIO output register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** out1_data_orig : R/W/SC/WTC; bitpos: [24:0]; default: 0;
+         *  GPIO output register for GPIO32-56
+         */
+        uint32_t out1_data_orig:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out1_reg_t;
+
+/** Type of out1_w1ts register
+ *  GPIO output set register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** out1_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output set register for GPIO32-56
+         */
+        uint32_t out1_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out1_w1ts_reg_t;
+
+/** Type of out1_w1tc register
+ *  GPIO output clear register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** out1_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output clear register for GPIO32-56
+         */
+        uint32_t out1_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out1_w1tc_reg_t;
+
+/** Type of enable register
+ *  GPIO output enable register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  GPIO output enable register for GPIO0-31
+         */
+        uint32_t enable_data:32;
+    };
+    uint32_t val;
+} gpio_enable_reg_t;
+
+/** Type of enable_w1ts register
+ *  GPIO output enable set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output enable set register for GPIO0-31
+         */
+        uint32_t enable_w1ts:32;
+    };
+    uint32_t val;
+} gpio_enable_w1ts_reg_t;
+
+/** Type of enable_w1tc register
+ *  GPIO output enable clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output enable clear register for GPIO0-31
+         */
+        uint32_t enable_w1tc:32;
+    };
+    uint32_t val;
+} gpio_enable_w1tc_reg_t;
+
+/** Type of enable1 register
+ *  GPIO output enable register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** enable1_data : R/W/WTC; bitpos: [24:0]; default: 0;
+         *  GPIO output enable register for GPIO32-56
+         */
+        uint32_t enable1_data:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable1_reg_t;
+
+/** Type of enable1_w1ts register
+ *  GPIO output enable set register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** enable1_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output enable set register for GPIO32-56
+         */
+        uint32_t enable1_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable1_w1ts_reg_t;
+
+/** Type of enable1_w1tc register
+ *  GPIO output enable clear register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** enable1_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output enable clear register for GPIO32-56
+         */
+        uint32_t enable1_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable1_w1tc_reg_t;
+
+/** Type of strap register
+ *  pad strapping register
+ */
+typedef union {
+    struct {
+        /** strapping : RO; bitpos: [15:0]; default: 0;
+         *  pad strapping register
+         */
+        uint32_t strapping:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpio_strap_reg_t;
+
+/** Type of in register
+ *  GPIO input register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** in_data_next : RO; bitpos: [31:0]; default: 0;
+         *  GPIO input register for GPIO0-31
+         */
+        uint32_t in_data_next:32;
+    };
+    uint32_t val;
+} gpio_in_reg_t;
+
+/** Type of in1 register
+ *  GPIO input register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** in1_data_next : RO; bitpos: [24:0]; default: 0;
+         *  GPIO input register for GPIO32-56
+         */
+        uint32_t in1_data_next:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_in1_reg_t;
+
+/** Type of status register
+ *  GPIO interrupt status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status register for GPIO0-31
+         */
+        uint32_t status_interrupt:32;
+    };
+    uint32_t val;
+} gpio_status_reg_t;
+
+/** Type of status_w1ts register
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO0-31
+         */
+        uint32_t status_w1ts:32;
+    };
+    uint32_t val;
+} gpio_status_w1ts_reg_t;
+
+/** Type of status_w1tc register
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO0-31
+         */
+        uint32_t status_w1tc:32;
+    };
+    uint32_t val;
+} gpio_status_w1tc_reg_t;
+
+/** Type of status1 register
+ *  GPIO interrupt status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status1_interrupt : R/W/WTC; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status register for GPIO32-56
+         */
+        uint32_t status1_interrupt:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status1_reg_t;
+
+/** Type of status1_w1ts register
+ *  GPIO interrupt status set register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status1_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO32-56
+         */
+        uint32_t status1_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status1_w1ts_reg_t;
+
+/** Type of status1_w1tc register
+ *  GPIO interrupt status clear register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status1_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO32-56
+         */
+        uint32_t status1_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status1_w1tc_reg_t;
+
+/** Type of intr_0 register
+ *  GPIO interrupt 0 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_0 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 0 status register for GPIO0-31
+         */
+        uint32_t int_0:32;
+    };
+    uint32_t val;
+} gpio_intr_0_reg_t;
+
+/** Type of intr1_0 register
+ *  GPIO interrupt 0 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_0 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 0 status register for GPIO32-56
+         */
+        uint32_t int1_0:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_0_reg_t;
+
+/** Type of intr_1 register
+ *  GPIO interrupt 1 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_1 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 1 status register for GPIO0-31
+         */
+        uint32_t int_1:32;
+    };
+    uint32_t val;
+} gpio_intr_1_reg_t;
+
+/** Type of intr1_1 register
+ *  GPIO interrupt 1 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_1 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 1 status register for GPIO32-56
+         */
+        uint32_t int1_1:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_1_reg_t;
+
+/** Type of status_next register
+ *  GPIO interrupt source register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt source register for GPIO0-31
+         */
+        uint32_t status_interrupt_next:32;
+    };
+    uint32_t val;
+} gpio_status_next_reg_t;
+
+/** Type of status_next1 register
+ *  GPIO interrupt source register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next1 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt source register for GPIO32-56
+         */
+        uint32_t status_interrupt_next1:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status_next1_reg_t;
+
+/** Type of pin register
+ *  GPIO pin configuration register
+ */
+typedef union {
+    struct {
+        /** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
+         *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync2_bypass:2;
+        /** pad_driver : R/W; bitpos: [2]; default: 0;
+         *  set this bit to select pad driver. 1:open-drain. 0:normal.
+         */
+        uint32_t pad_driver:1;
+        /** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
+         *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync1_bypass:2;
+        uint32_t reserved_5:2;
+        /** int_type : R/W; bitpos: [9:7]; default: 0;
+         *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+         *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+         *  at high level
+         */
+        uint32_t int_type:3;
+        /** wakeup_enable : R/W; bitpos: [10]; default: 0;
+         *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+         */
+        uint32_t wakeup_enable:1;
+        /** config : R/W; bitpos: [12:11]; default: 0;
+         *  reserved
+         */
+        uint32_t config:2;
+        /** int_ena : R/W; bitpos: [17:13]; default: 0;
+         *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+         *  interrupt.
+         */
+        uint32_t int_ena:5;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gpio_pin_reg_t;
+
+/** Type of func_in_sel_cfg register
+ *  GPIO input function configuration register
+ */
+typedef union {
+    struct {
+        /** in_sel : R/W; bitpos: [5:0]; default: 63;
+         *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+         *  high level. s=0x3E: set this port always low level.
+         */
+        uint32_t in_sel:6;
+        /** in_inv_sel : R/W; bitpos: [6]; default: 0;
+         *  set this bit to invert input signal. 1:invert. 0:not invert.
+         */
+        uint32_t in_inv_sel:1;
+        /** sig_in_sel : R/W; bitpos: [7]; default: 0;
+         *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+         */
+        uint32_t sig_in_sel:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_func_in_sel_cfg_reg_t;
+
+/** Type of func_out_sel_cfg register
+ *  GPIO output function select register
+ */
+typedef union {
+    struct {
+        /** out_sel : R/W/SC; bitpos: [8:0]; default: 256;
+         *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+         *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+         *  GPIO_OUT_REG[n].
+         */
+        uint32_t out_sel:9;
+        /** out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
+         *  set this bit to invert output signal.1:invert.0:not invert.
+         */
+        uint32_t out_inv_sel:1;
+        /** oen_sel : R/W; bitpos: [10]; default: 0;
+         *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+         *  enable signal.0:use peripheral output enable signal.
+         */
+        uint32_t oen_sel:1;
+        /** oen_inv_sel : R/W; bitpos: [11]; default: 0;
+         *  set this bit to invert output enable signal.1:invert.0:not invert.
+         */
+        uint32_t oen_inv_sel:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} gpio_func_out_sel_cfg_reg_t;
+
+/** Type of intr_2 register
+ *  GPIO interrupt 2 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_2 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 2 status register for GPIO0-31
+         */
+        uint32_t int_2:32;
+    };
+    uint32_t val;
+} gpio_intr_2_reg_t;
+
+/** Type of intr1_2 register
+ *  GPIO interrupt 2 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_2 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 2 status register for GPIO32-56
+         */
+        uint32_t int1_2:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_2_reg_t;
+
+/** Type of intr_3 register
+ *  GPIO interrupt 3 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_3 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 3 status register for GPIO0-31
+         */
+        uint32_t int_3:32;
+    };
+    uint32_t val;
+} gpio_intr_3_reg_t;
+
+/** Type of intr1_3 register
+ *  GPIO interrupt 3 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_3 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 3 status register for GPIO32-56
+         */
+        uint32_t int1_3:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_3_reg_t;
+
+/** Type of clock_gate register
+ *  GPIO clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  set this bit to enable GPIO clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} gpio_clock_gate_reg_t;
+
+/** Type of zero_det_filter_cnt register
+ *  GPIO analog comparator zero detect filter count
+ */
+typedef union {
+    struct {
+        /** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GPIO analog comparator zero detect filter count
+         */
+        uint32_t zero_det_filter_cnt:32;
+    };
+    uint32_t val;
+} gpio_zero_det_filter_cnt_reg_t;
+
+/** Type of send_seq register
+ *  High speed sdio pad bist send sequence
+ */
+typedef union {
+    struct {
+        /** send_seq : R/W; bitpos: [31:0]; default: 305419896;
+         *  High speed sdio pad bist send sequence
+         */
+        uint32_t send_seq:32;
+    };
+    uint32_t val;
+} gpio_send_seq_reg_t;
+
+/** Type of recive_seq register
+ *  High speed sdio pad bist receive sequence
+ */
+typedef union {
+    struct {
+        /** recive_seq : RO; bitpos: [31:0]; default: 0;
+         *  High speed sdio pad bist receive sequence
+         */
+        uint32_t recive_seq:32;
+    };
+    uint32_t val;
+} gpio_recive_seq_reg_t;
+
+/** Type of bistin_sel register
+ *  High speed sdio pad bist in pad sel
+ */
+typedef union {
+    struct {
+        /** bistin_sel : R/W; bitpos: [3:0]; default: 15;
+         *  High speed sdio pad bist in pad sel 0:pad39, 1: pad40...
+         */
+        uint32_t bistin_sel:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} gpio_bistin_sel_reg_t;
+
+/** Type of bist_ctrl register
+ *  High speed sdio pad bist control
+ */
+typedef union {
+    struct {
+        /** bist_pad_oe : R/W; bitpos: [0]; default: 1;
+         *  High speed sdio pad bist out pad oe
+         */
+        uint32_t bist_pad_oe:1;
+        /** bist_start : WT; bitpos: [1]; default: 0;
+         *  High speed sdio pad bist start
+         */
+        uint32_t bist_start:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} gpio_bist_ctrl_reg_t;
+
+/** Type of date register
+ *  GPIO version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2294787;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpio_date_reg_t;
+
+
+/** Group: GPIO INT RAW REG */
+/** Type of int_raw register
+ *  analog comparator interrupt raw
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  analog comparator pos edge interrupt raw
+         */
+        uint32_t comp0_neg_int_raw:1;
+        /** comp0_pos_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  analog comparator neg edge interrupt raw
+         */
+        uint32_t comp0_pos_int_raw:1;
+        /** comp0_all_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  analog comparator neg or pos edge interrupt raw
+         */
+        uint32_t comp0_all_int_raw:1;
+        /** comp1_neg_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  analog comparator pos edge interrupt raw
+         */
+        uint32_t comp1_neg_int_raw:1;
+        /** comp1_pos_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  analog comparator neg edge interrupt raw
+         */
+        uint32_t comp1_pos_int_raw:1;
+        /** comp1_all_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  analog comparator neg or pos edge interrupt raw
+         */
+        uint32_t comp1_all_int_raw:1;
+        /** bistok_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  pad bistok interrupt raw
+         */
+        uint32_t bistok_int_raw:1;
+        /** bistfail_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  pad bistfail interrupt raw
+         */
+        uint32_t bistfail_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_raw_reg_t;
+
+
+/** Group: GPIO INT ST REG */
+/** Type of int_st register
+ *  analog comparator interrupt status
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_st : RO; bitpos: [0]; default: 0;
+         *  analog comparator pos edge interrupt status
+         */
+        uint32_t comp0_neg_int_st:1;
+        /** comp0_pos_int_st : RO; bitpos: [1]; default: 0;
+         *  analog comparator neg edge interrupt status
+         */
+        uint32_t comp0_pos_int_st:1;
+        /** comp0_all_int_st : RO; bitpos: [2]; default: 0;
+         *  analog comparator neg or pos edge interrupt status
+         */
+        uint32_t comp0_all_int_st:1;
+        /** comp1_neg_int_st : RO; bitpos: [3]; default: 0;
+         *  analog comparator pos edge interrupt status
+         */
+        uint32_t comp1_neg_int_st:1;
+        /** comp1_pos_int_st : RO; bitpos: [4]; default: 0;
+         *  analog comparator neg edge interrupt status
+         */
+        uint32_t comp1_pos_int_st:1;
+        /** comp1_all_int_st : RO; bitpos: [5]; default: 0;
+         *  analog comparator neg or pos edge interrupt status
+         */
+        uint32_t comp1_all_int_st:1;
+        /** bistok_int_st : RO; bitpos: [6]; default: 0;
+         *  pad bistok interrupt status
+         */
+        uint32_t bistok_int_st:1;
+        /** bistfail_int_st : RO; bitpos: [7]; default: 0;
+         *  pad bistfail interrupt status
+         */
+        uint32_t bistfail_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_st_reg_t;
+
+
+/** Group: GPIO INT ENA REG */
+/** Type of int_ena register
+ *  analog comparator interrupt enable
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1;
+         *  analog comparator pos edge interrupt enable
+         */
+        uint32_t comp0_neg_int_ena:1;
+        /** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1;
+         *  analog comparator neg edge interrupt enable
+         */
+        uint32_t comp0_pos_int_ena:1;
+        /** comp0_all_int_ena : R/W; bitpos: [2]; default: 1;
+         *  analog comparator neg or pos edge interrupt enable
+         */
+        uint32_t comp0_all_int_ena:1;
+        /** comp1_neg_int_ena : R/W; bitpos: [3]; default: 1;
+         *  analog comparator pos edge interrupt enable
+         */
+        uint32_t comp1_neg_int_ena:1;
+        /** comp1_pos_int_ena : R/W; bitpos: [4]; default: 1;
+         *  analog comparator neg edge interrupt enable
+         */
+        uint32_t comp1_pos_int_ena:1;
+        /** comp1_all_int_ena : R/W; bitpos: [5]; default: 1;
+         *  analog comparator neg or pos edge interrupt enable
+         */
+        uint32_t comp1_all_int_ena:1;
+        /** bistok_int_ena : R/W; bitpos: [6]; default: 1;
+         *  pad bistok interrupt enable
+         */
+        uint32_t bistok_int_ena:1;
+        /** bistfail_int_ena : R/W; bitpos: [7]; default: 1;
+         *  pad bistfail interrupt enable
+         */
+        uint32_t bistfail_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_ena_reg_t;
+
+
+/** Group: GPIO INT CLR REG */
+/** Type of int_clr register
+ *  analog comparator interrupt clear
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_clr : WT; bitpos: [0]; default: 0;
+         *  analog comparator pos edge interrupt clear
+         */
+        uint32_t comp0_neg_int_clr:1;
+        /** comp0_pos_int_clr : WT; bitpos: [1]; default: 0;
+         *  analog comparator neg edge interrupt clear
+         */
+        uint32_t comp0_pos_int_clr:1;
+        /** comp0_all_int_clr : WT; bitpos: [2]; default: 0;
+         *  analog comparator neg or pos edge interrupt clear
+         */
+        uint32_t comp0_all_int_clr:1;
+        /** comp1_neg_int_clr : WT; bitpos: [3]; default: 0;
+         *  analog comparator pos edge interrupt clear
+         */
+        uint32_t comp1_neg_int_clr:1;
+        /** comp1_pos_int_clr : WT; bitpos: [4]; default: 0;
+         *  analog comparator neg edge interrupt clear
+         */
+        uint32_t comp1_pos_int_clr:1;
+        /** comp1_all_int_clr : WT; bitpos: [5]; default: 0;
+         *  analog comparator neg or pos edge interrupt clear
+         */
+        uint32_t comp1_all_int_clr:1;
+        /** bistok_int_clr : WT; bitpos: [6]; default: 0;
+         *  pad bistok interrupt enable
+         */
+        uint32_t bistok_int_clr:1;
+        /** bistfail_int_clr : WT; bitpos: [7]; default: 0;
+         *  pad bistfail interrupt enable
+         */
+        uint32_t bistfail_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_clr_reg_t;
+
+
+typedef struct gpio_dev_t {
+    volatile gpio_bt_select_reg_t bt_select;
+    volatile gpio_out_reg_t out;
+    volatile gpio_out_w1ts_reg_t out_w1ts;
+    volatile gpio_out_w1tc_reg_t out_w1tc;
+    volatile gpio_out1_reg_t out1;
+    volatile gpio_out1_w1ts_reg_t out1_w1ts;
+    volatile gpio_out1_w1tc_reg_t out1_w1tc;
+    uint32_t reserved_01c;
+    volatile gpio_enable_reg_t enable;
+    volatile gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile gpio_enable_w1tc_reg_t enable_w1tc;
+    volatile gpio_enable1_reg_t enable1;
+    volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
+    volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
+    volatile gpio_strap_reg_t strap;
+    volatile gpio_in_reg_t in;
+    volatile gpio_in1_reg_t in1;
+    volatile gpio_status_reg_t status;
+    volatile gpio_status_w1ts_reg_t status_w1ts;
+    volatile gpio_status_w1tc_reg_t status_w1tc;
+    volatile gpio_status1_reg_t status1;
+    volatile gpio_status1_w1ts_reg_t status1_w1ts;
+    volatile gpio_status1_w1tc_reg_t status1_w1tc;
+    volatile gpio_intr_0_reg_t intr_0;
+    volatile gpio_intr1_0_reg_t intr1_0;
+    volatile gpio_intr_1_reg_t intr_1;
+    volatile gpio_intr1_1_reg_t intr1_1;
+    volatile gpio_status_next_reg_t status_next;
+    volatile gpio_status_next1_reg_t status_next1;
+    volatile gpio_pin_reg_t pin[57];
+    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; /* func0-func255: reserved for func0, 46, 67, 72, 73, 79, 81, 82, 84, 85, 87, 88, 115, 116, 119-125, 157, 204-213 */
+    volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[57];
+    volatile gpio_intr_2_reg_t intr_2;
+    volatile gpio_intr1_2_reg_t intr1_2;
+    volatile gpio_intr_3_reg_t intr_3;
+    volatile gpio_intr1_3_reg_t intr1_3;
+    volatile gpio_clock_gate_reg_t clock_gate;
+    uint32_t reserved_650[44];
+    volatile gpio_int_raw_reg_t int_raw;
+    volatile gpio_int_st_reg_t int_st;
+    volatile gpio_int_ena_reg_t int_ena;
+    volatile gpio_int_clr_reg_t int_clr;
+    volatile gpio_zero_det_filter_cnt_reg_t zero_det_filter_cnt[2];
+    volatile gpio_send_seq_reg_t send_seq;
+    volatile gpio_recive_seq_reg_t recive_seq;
+    volatile gpio_bistin_sel_reg_t bistin_sel;
+    volatile gpio_bist_ctrl_reg_t bist_ctrl;
+    uint32_t reserved_728[53];
+    volatile gpio_date_reg_t date;
+} gpio_dev_t;
+
+extern gpio_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_dev_t) == 0x800, "Invalid size of gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/h264_dma_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/h264_dma_reg.h
new file mode 100644
index 0000000000..722c24a9c7
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/h264_dma_reg.h
@@ -0,0 +1,8118 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** H264_DMA_OUT_CONF0_CH0_REG register
+ *  TX CH0 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH0_REG (DR_REG_H264_DMA_BASE + 0x0)
+/** H264_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH0    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH0_M  (H264_DMA_OUT_AUTO_WRBACK_CH0_V << H264_DMA_OUT_AUTO_WRBACK_CH0_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH0_S  0
+/** H264_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH0    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH0_M  (H264_DMA_OUT_EOF_MODE_CH0_V << H264_DMA_OUT_EOF_MODE_CH0_S)
+#define H264_DMA_OUT_EOF_MODE_CH0_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH0_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH0    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH0_M  (H264_DMA_OUTDSCR_BURST_EN_CH0_V << H264_DMA_OUTDSCR_BURST_EN_CH0_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH0_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH0    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH0_M  (H264_DMA_OUT_ECC_AES_EN_CH0_V << H264_DMA_OUT_ECC_AES_EN_CH0_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH0_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH0    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH0_M  (H264_DMA_OUT_CHECK_OWNER_CH0_V << H264_DMA_OUT_CHECK_OWNER_CH0_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH0_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH0    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH0_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH0_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH0_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH0_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH0    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH0_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH0_V << H264_DMA_OUT_PAGE_BOUND_EN_CH0_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH0_S  12
+/** H264_DMA_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define H264_DMA_OUT_REORDER_EN_CH0    (BIT(16))
+#define H264_DMA_OUT_REORDER_EN_CH0_M  (H264_DMA_OUT_REORDER_EN_CH0_V << H264_DMA_OUT_REORDER_EN_CH0_S)
+#define H264_DMA_OUT_REORDER_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_REORDER_EN_CH0_S  16
+/** H264_DMA_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define H264_DMA_OUT_RST_CH0    (BIT(24))
+#define H264_DMA_OUT_RST_CH0_M  (H264_DMA_OUT_RST_CH0_V << H264_DMA_OUT_RST_CH0_S)
+#define H264_DMA_OUT_RST_CH0_V  0x00000001U
+#define H264_DMA_OUT_RST_CH0_S  24
+/** H264_DMA_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_OUT_CMD_DISABLE_CH0    (BIT(25))
+#define H264_DMA_OUT_CMD_DISABLE_CH0_M  (H264_DMA_OUT_CMD_DISABLE_CH0_V << H264_DMA_OUT_CMD_DISABLE_CH0_S)
+#define H264_DMA_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define H264_DMA_OUT_CMD_DISABLE_CH0_S  25
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH0_REG register
+ *  TX CH0  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH0_REG (DR_REG_H264_DMA_BASE + 0x4)
+/** H264_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH0_INT_RAW_M  (H264_DMA_OUT_DONE_CH0_INT_RAW_V << H264_DMA_OUT_DONE_CH0_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH0_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH0_INT_RAW_M  (H264_DMA_OUT_EOF_CH0_INT_RAW_V << H264_DMA_OUT_EOF_CH0_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH0_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH0_REG register
+ *  TX CH0  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH0_REG (DR_REG_H264_DMA_BASE + 0x8)
+/** H264_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH0_INT_ENA_M  (H264_DMA_OUT_DONE_CH0_INT_ENA_V << H264_DMA_OUT_DONE_CH0_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH0_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH0_INT_ENA_M  (H264_DMA_OUT_EOF_CH0_INT_ENA_V << H264_DMA_OUT_EOF_CH0_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH0_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH0_REG register
+ *  TX CH0  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH0_REG (DR_REG_H264_DMA_BASE + 0xc)
+/** H264_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH0_INT_ST_M  (H264_DMA_OUT_DONE_CH0_INT_ST_V << H264_DMA_OUT_DONE_CH0_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH0_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH0_INT_ST_M  (H264_DMA_OUT_EOF_CH0_INT_ST_V << H264_DMA_OUT_EOF_CH0_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH0_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH0_REG register
+ *  TX CH0  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH0_REG (DR_REG_H264_DMA_BASE + 0x10)
+/** H264_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH0_INT_CLR_M  (H264_DMA_OUT_DONE_CH0_INT_CLR_V << H264_DMA_OUT_DONE_CH0_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH0_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH0_INT_CLR_M  (H264_DMA_OUT_EOF_CH0_INT_CLR_V << H264_DMA_OUT_EOF_CH0_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH0_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH0_REG register
+ *  TX CH0 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_H264_DMA_BASE + 0x14)
+/** H264_DMA_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH0    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH0_M  (H264_DMA_OUTFIFO_FULL_L2_CH0_V << H264_DMA_OUTFIFO_FULL_L2_CH0_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH0_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH0    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH0_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH0_V << H264_DMA_OUTFIFO_EMPTY_L2_CH0_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH0_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH0    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH0_M  (H264_DMA_OUTFIFO_CNT_L2_CH0_V << H264_DMA_OUTFIFO_CNT_L2_CH0_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH0_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH0_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH0    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH0_M  (H264_DMA_OUTFIFO_FULL_L1_CH0_V << H264_DMA_OUTFIFO_FULL_L1_CH0_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH0_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH0    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH0_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH0_V << H264_DMA_OUTFIFO_EMPTY_L1_CH0_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH0_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH0    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH0_M  (H264_DMA_OUTFIFO_CNT_L1_CH0_V << H264_DMA_OUTFIFO_CNT_L1_CH0_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH0_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH0_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH0    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH0_M  (H264_DMA_OUTFIFO_FULL_L3_CH0_V << H264_DMA_OUTFIFO_FULL_L3_CH0_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH0_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH0    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH0_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH0_V << H264_DMA_OUTFIFO_EMPTY_L3_CH0_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH0_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH0    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH0_M  (H264_DMA_OUTFIFO_CNT_L3_CH0_V << H264_DMA_OUTFIFO_CNT_L3_CH0_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH0_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH0_S  18
+
+/** H264_DMA_OUT_PUSH_CH0_REG register
+ *  TX CH0 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH0_REG (DR_REG_H264_DMA_BASE + 0x18)
+/** H264_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH0    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH0_M  (H264_DMA_OUTFIFO_WDATA_CH0_V << H264_DMA_OUTFIFO_WDATA_CH0_S)
+#define H264_DMA_OUTFIFO_WDATA_CH0_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH0_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH0    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH0_M  (H264_DMA_OUTFIFO_PUSH_CH0_V << H264_DMA_OUTFIFO_PUSH_CH0_S)
+#define H264_DMA_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH0_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH0_REG register
+ *  TX CH0 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x1c)
+/** H264_DMA_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH0    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH0_M  (H264_DMA_OUTLINK_STOP_CH0_V << H264_DMA_OUTLINK_STOP_CH0_S)
+#define H264_DMA_OUTLINK_STOP_CH0_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH0_S  20
+/** H264_DMA_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH0    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH0_M  (H264_DMA_OUTLINK_START_CH0_V << H264_DMA_OUTLINK_START_CH0_S)
+#define H264_DMA_OUTLINK_START_CH0_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH0_S  21
+/** H264_DMA_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH0    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH0_M  (H264_DMA_OUTLINK_RESTART_CH0_V << H264_DMA_OUTLINK_RESTART_CH0_S)
+#define H264_DMA_OUTLINK_RESTART_CH0_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH0_S  22
+/** H264_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH0    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH0_M  (H264_DMA_OUTLINK_PARK_CH0_V << H264_DMA_OUTLINK_PARK_CH0_S)
+#define H264_DMA_OUTLINK_PARK_CH0_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH0_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH0_REG register
+ *  TX CH0 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x20)
+/** H264_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH0_M  (H264_DMA_OUTLINK_ADDR_CH0_V << H264_DMA_OUTLINK_ADDR_CH0_S)
+#define H264_DMA_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH0_S  0
+
+/** H264_DMA_OUT_STATE_CH0_REG register
+ *  TX CH0 state register
+ */
+#define H264_DMA_OUT_STATE_CH0_REG (DR_REG_H264_DMA_BASE + 0x24)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH0_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH0_V << H264_DMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH0_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH0    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH0_M  (H264_DMA_OUT_DSCR_STATE_CH0_V << H264_DMA_OUT_DSCR_STATE_CH0_S)
+#define H264_DMA_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH0_S  18
+/** H264_DMA_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH0    0x0000000FU
+#define H264_DMA_OUT_STATE_CH0_M  (H264_DMA_OUT_STATE_CH0_V << H264_DMA_OUT_STATE_CH0_S)
+#define H264_DMA_OUT_STATE_CH0_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH0_S  20
+/** H264_DMA_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_OUT_RESET_AVAIL_CH0    (BIT(24))
+#define H264_DMA_OUT_RESET_AVAIL_CH0_M  (H264_DMA_OUT_RESET_AVAIL_CH0_V << H264_DMA_OUT_RESET_AVAIL_CH0_S)
+#define H264_DMA_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define H264_DMA_OUT_RESET_AVAIL_CH0_S  24
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH0_REG register
+ *  TX CH0 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x28)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0_M  (H264_DMA_OUT_EOF_DES_ADDR_CH0_V << H264_DMA_OUT_EOF_DES_ADDR_CH0_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** H264_DMA_OUT_DSCR_CH0_REG register
+ *  TX CH0 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH0_REG (DR_REG_H264_DMA_BASE + 0x2c)
+/** H264_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH0_M  (H264_DMA_OUTLINK_DSCR_CH0_V << H264_DMA_OUTLINK_DSCR_CH0_S)
+#define H264_DMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH0_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH0_REG register
+ *  TX CH0 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_H264_DMA_BASE + 0x30)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH0_M  (H264_DMA_OUTLINK_DSCR_BF0_CH0_V << H264_DMA_OUTLINK_DSCR_BF0_CH0_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH0_REG register
+ *  TX CH0 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_H264_DMA_BASE + 0x34)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH0_M  (H264_DMA_OUTLINK_DSCR_BF1_CH0_V << H264_DMA_OUTLINK_DSCR_BF1_CH0_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** H264_DMA_OUT_ARB_CH0_REG register
+ *  TX CH0 arb register
+ */
+#define H264_DMA_OUT_ARB_CH0_REG (DR_REG_H264_DMA_BASE + 0x3c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH0_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH0_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH0_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH0_S  0
+/** H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0    0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_M  (H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_V << H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_S)
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_V  0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH0_S  4
+
+/** H264_DMA_OUT_RO_STATUS_CH0_REG register
+ *  TX CH0 reorder status register
+ */
+#define H264_DMA_OUT_RO_STATUS_CH0_REG (DR_REG_H264_DMA_BASE + 0x40)
+/** H264_DMA_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [1:0]; default: 0;
+ *  The register stores the 8byte number of the data in reorder Tx FIFO for channel 0.
+ */
+#define H264_DMA_OUTFIFO_RO_CNT_CH0    0x00000003U
+#define H264_DMA_OUTFIFO_RO_CNT_CH0_M  (H264_DMA_OUTFIFO_RO_CNT_CH0_V << H264_DMA_OUTFIFO_RO_CNT_CH0_S)
+#define H264_DMA_OUTFIFO_RO_CNT_CH0_V  0x00000003U
+#define H264_DMA_OUTFIFO_RO_CNT_CH0_S  0
+/** H264_DMA_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define H264_DMA_OUT_RO_WR_STATE_CH0    0x00000003U
+#define H264_DMA_OUT_RO_WR_STATE_CH0_M  (H264_DMA_OUT_RO_WR_STATE_CH0_V << H264_DMA_OUT_RO_WR_STATE_CH0_S)
+#define H264_DMA_OUT_RO_WR_STATE_CH0_V  0x00000003U
+#define H264_DMA_OUT_RO_WR_STATE_CH0_S  6
+/** H264_DMA_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define H264_DMA_OUT_RO_RD_STATE_CH0    0x00000003U
+#define H264_DMA_OUT_RO_RD_STATE_CH0_M  (H264_DMA_OUT_RO_RD_STATE_CH0_V << H264_DMA_OUT_RO_RD_STATE_CH0_S)
+#define H264_DMA_OUT_RO_RD_STATE_CH0_V  0x00000003U
+#define H264_DMA_OUT_RO_RD_STATE_CH0_S  8
+/** H264_DMA_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 2;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define H264_DMA_OUT_PIXEL_BYTE_CH0    0x0000000FU
+#define H264_DMA_OUT_PIXEL_BYTE_CH0_M  (H264_DMA_OUT_PIXEL_BYTE_CH0_V << H264_DMA_OUT_PIXEL_BYTE_CH0_S)
+#define H264_DMA_OUT_PIXEL_BYTE_CH0_V  0x0000000FU
+#define H264_DMA_OUT_PIXEL_BYTE_CH0_S  10
+/** H264_DMA_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define H264_DMA_OUT_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define H264_DMA_OUT_BURST_BLOCK_NUM_CH0_M  (H264_DMA_OUT_BURST_BLOCK_NUM_CH0_V << H264_DMA_OUT_BURST_BLOCK_NUM_CH0_S)
+#define H264_DMA_OUT_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define H264_DMA_OUT_BURST_BLOCK_NUM_CH0_S  14
+
+/** H264_DMA_OUT_RO_PD_CONF_CH0_REG register
+ *  TX CH0 reorder power config register
+ */
+#define H264_DMA_OUT_RO_PD_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x44)
+/** H264_DMA_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 0;
+ *  dma reorder ram power down
+ */
+#define H264_DMA_OUT_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_M  (H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_V << H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_S)
+#define H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define H264_DMA_OUT_RO_RAM_FORCE_PD_CH0_S  4
+/** H264_DMA_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 1;
+ *  dma reorder ram power up
+ */
+#define H264_DMA_OUT_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_M  (H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_V << H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_S)
+#define H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define H264_DMA_OUT_RO_RAM_FORCE_PU_CH0_S  5
+/** H264_DMA_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define H264_DMA_OUT_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define H264_DMA_OUT_RO_RAM_CLK_FO_CH0_M  (H264_DMA_OUT_RO_RAM_CLK_FO_CH0_V << H264_DMA_OUT_RO_RAM_CLK_FO_CH0_S)
+#define H264_DMA_OUT_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define H264_DMA_OUT_RO_RAM_CLK_FO_CH0_S  6
+
+/** H264_DMA_OUT_MODE_ENABLE_CH0_REG register
+ *  tx CH0 mode enable register
+ */
+#define H264_DMA_OUT_MODE_ENABLE_CH0_REG (DR_REG_H264_DMA_BASE + 0x50)
+/** H264_DMA_OUT_TEST_MODE_ENABLE_CH0 : R/W; bitpos: [0]; default: 0;
+ *  tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test
+ *  mode
+ */
+#define H264_DMA_OUT_TEST_MODE_ENABLE_CH0    (BIT(0))
+#define H264_DMA_OUT_TEST_MODE_ENABLE_CH0_M  (H264_DMA_OUT_TEST_MODE_ENABLE_CH0_V << H264_DMA_OUT_TEST_MODE_ENABLE_CH0_S)
+#define H264_DMA_OUT_TEST_MODE_ENABLE_CH0_V  0x00000001U
+#define H264_DMA_OUT_TEST_MODE_ENABLE_CH0_S  0
+
+/** H264_DMA_OUT_MODE_YUV_CH0_REG register
+ *  tx CH0 test mode yuv value register
+ */
+#define H264_DMA_OUT_MODE_YUV_CH0_REG (DR_REG_H264_DMA_BASE + 0x54)
+/** H264_DMA_OUT_TEST_Y_VALUE_CH0 : R/W; bitpos: [7:0]; default: 0;
+ *  tx CH0 test mode y value
+ */
+#define H264_DMA_OUT_TEST_Y_VALUE_CH0    0x000000FFU
+#define H264_DMA_OUT_TEST_Y_VALUE_CH0_M  (H264_DMA_OUT_TEST_Y_VALUE_CH0_V << H264_DMA_OUT_TEST_Y_VALUE_CH0_S)
+#define H264_DMA_OUT_TEST_Y_VALUE_CH0_V  0x000000FFU
+#define H264_DMA_OUT_TEST_Y_VALUE_CH0_S  0
+/** H264_DMA_OUT_TEST_U_VALUE_CH0 : R/W; bitpos: [15:8]; default: 0;
+ *  tx CH0 test mode u value
+ */
+#define H264_DMA_OUT_TEST_U_VALUE_CH0    0x000000FFU
+#define H264_DMA_OUT_TEST_U_VALUE_CH0_M  (H264_DMA_OUT_TEST_U_VALUE_CH0_V << H264_DMA_OUT_TEST_U_VALUE_CH0_S)
+#define H264_DMA_OUT_TEST_U_VALUE_CH0_V  0x000000FFU
+#define H264_DMA_OUT_TEST_U_VALUE_CH0_S  8
+/** H264_DMA_OUT_TEST_V_VALUE_CH0 : R/W; bitpos: [23:16]; default: 0;
+ *  tx CH0 test mode v value
+ */
+#define H264_DMA_OUT_TEST_V_VALUE_CH0    0x000000FFU
+#define H264_DMA_OUT_TEST_V_VALUE_CH0_M  (H264_DMA_OUT_TEST_V_VALUE_CH0_V << H264_DMA_OUT_TEST_V_VALUE_CH0_S)
+#define H264_DMA_OUT_TEST_V_VALUE_CH0_V  0x000000FFU
+#define H264_DMA_OUT_TEST_V_VALUE_CH0_S  16
+
+/** H264_DMA_OUT_ETM_CONF_CH0_REG register
+ *  TX CH0 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x68)
+/** H264_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH0    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH0_M  (H264_DMA_OUT_ETM_EN_CH0_V << H264_DMA_OUT_ETM_EN_CH0_S)
+#define H264_DMA_OUT_ETM_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH0_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH0    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH0_M  (H264_DMA_OUT_ETM_LOOP_EN_CH0_V << H264_DMA_OUT_ETM_LOOP_EN_CH0_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH0_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH0_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH0    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH0_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH0_V << H264_DMA_OUT_DSCR_TASK_MAK_CH0_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH0_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH0_REG register
+ *  tx CH0 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH0_REG (DR_REG_H264_DMA_BASE + 0x70)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH0_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH0_REG register
+ *  tx CH0 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH0_REG (DR_REG_H264_DMA_BASE + 0x74)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH0_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH0_REG register
+ *  tx CH0 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH0_REG (DR_REG_H264_DMA_BASE + 0x78)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0 : RO; bitpos: [7:0]; default: 255;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH0_S  0
+
+/** H264_DMA_OUT_XADDR_CH0_REG register
+ *  tx CH0 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x7c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH0_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH0_V << H264_DMA_OUT_CMDFIFO_XADDR_CH0_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH0_S  0
+
+/** H264_DMA_OUT_CONF0_CH1_REG register
+ *  TX CH1 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH1_REG (DR_REG_H264_DMA_BASE + 0x100)
+/** H264_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH1    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH1_M  (H264_DMA_OUT_AUTO_WRBACK_CH1_V << H264_DMA_OUT_AUTO_WRBACK_CH1_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH1_S  0
+/** H264_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH1    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH1_M  (H264_DMA_OUT_EOF_MODE_CH1_V << H264_DMA_OUT_EOF_MODE_CH1_S)
+#define H264_DMA_OUT_EOF_MODE_CH1_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH1_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH1    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH1_M  (H264_DMA_OUTDSCR_BURST_EN_CH1_V << H264_DMA_OUTDSCR_BURST_EN_CH1_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH1_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH1    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH1_M  (H264_DMA_OUT_ECC_AES_EN_CH1_V << H264_DMA_OUT_ECC_AES_EN_CH1_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH1_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH1_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH1    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH1_M  (H264_DMA_OUT_CHECK_OWNER_CH1_V << H264_DMA_OUT_CHECK_OWNER_CH1_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH1_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 64 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH1    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH1_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH1_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH1_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH1_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH1    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH1_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH1_V << H264_DMA_OUT_PAGE_BOUND_EN_CH1_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH1_S  12
+/** H264_DMA_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define H264_DMA_OUT_RST_CH1    (BIT(24))
+#define H264_DMA_OUT_RST_CH1_M  (H264_DMA_OUT_RST_CH1_V << H264_DMA_OUT_RST_CH1_S)
+#define H264_DMA_OUT_RST_CH1_V  0x00000001U
+#define H264_DMA_OUT_RST_CH1_S  24
+/** H264_DMA_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_OUT_CMD_DISABLE_CH1    (BIT(25))
+#define H264_DMA_OUT_CMD_DISABLE_CH1_M  (H264_DMA_OUT_CMD_DISABLE_CH1_V << H264_DMA_OUT_CMD_DISABLE_CH1_S)
+#define H264_DMA_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define H264_DMA_OUT_CMD_DISABLE_CH1_S  25
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH1_REG register
+ *  TX CH1  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH1_REG (DR_REG_H264_DMA_BASE + 0x104)
+/** H264_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH1_INT_RAW_M  (H264_DMA_OUT_DONE_CH1_INT_RAW_V << H264_DMA_OUT_DONE_CH1_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH1_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH1_INT_RAW_M  (H264_DMA_OUT_EOF_CH1_INT_RAW_V << H264_DMA_OUT_EOF_CH1_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH1_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH1_REG register
+ *  TX CH1  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH1_REG (DR_REG_H264_DMA_BASE + 0x108)
+/** H264_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH1_INT_ENA_M  (H264_DMA_OUT_DONE_CH1_INT_ENA_V << H264_DMA_OUT_DONE_CH1_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH1_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH1_INT_ENA_M  (H264_DMA_OUT_EOF_CH1_INT_ENA_V << H264_DMA_OUT_EOF_CH1_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH1_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH1_REG register
+ *  TX CH1  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH1_REG (DR_REG_H264_DMA_BASE + 0x10c)
+/** H264_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH1_INT_ST_M  (H264_DMA_OUT_DONE_CH1_INT_ST_V << H264_DMA_OUT_DONE_CH1_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH1_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH1_INT_ST_M  (H264_DMA_OUT_EOF_CH1_INT_ST_V << H264_DMA_OUT_EOF_CH1_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH1_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH1_REG register
+ *  TX CH1  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH1_REG (DR_REG_H264_DMA_BASE + 0x110)
+/** H264_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH1_INT_CLR_M  (H264_DMA_OUT_DONE_CH1_INT_CLR_V << H264_DMA_OUT_DONE_CH1_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH1_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH1_INT_CLR_M  (H264_DMA_OUT_EOF_CH1_INT_CLR_V << H264_DMA_OUT_EOF_CH1_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH1_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH1_REG register
+ *  TX CH1 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_H264_DMA_BASE + 0x114)
+/** H264_DMA_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH1    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH1_M  (H264_DMA_OUTFIFO_FULL_L2_CH1_V << H264_DMA_OUTFIFO_FULL_L2_CH1_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH1_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH1    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH1_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH1_V << H264_DMA_OUTFIFO_EMPTY_L2_CH1_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH1_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH1    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH1_M  (H264_DMA_OUTFIFO_CNT_L2_CH1_V << H264_DMA_OUTFIFO_CNT_L2_CH1_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH1_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH1_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH1    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH1_M  (H264_DMA_OUTFIFO_FULL_L1_CH1_V << H264_DMA_OUTFIFO_FULL_L1_CH1_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH1_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH1    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH1_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH1_V << H264_DMA_OUTFIFO_EMPTY_L1_CH1_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH1_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH1    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH1_M  (H264_DMA_OUTFIFO_CNT_L1_CH1_V << H264_DMA_OUTFIFO_CNT_L1_CH1_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH1_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH1_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH1    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH1_M  (H264_DMA_OUTFIFO_FULL_L3_CH1_V << H264_DMA_OUTFIFO_FULL_L3_CH1_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH1_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH1    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH1_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH1_V << H264_DMA_OUTFIFO_EMPTY_L3_CH1_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH1_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH1    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH1_M  (H264_DMA_OUTFIFO_CNT_L3_CH1_V << H264_DMA_OUTFIFO_CNT_L3_CH1_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH1_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH1_S  18
+
+/** H264_DMA_OUT_PUSH_CH1_REG register
+ *  TX CH1 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH1_REG (DR_REG_H264_DMA_BASE + 0x118)
+/** H264_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH1    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH1_M  (H264_DMA_OUTFIFO_WDATA_CH1_V << H264_DMA_OUTFIFO_WDATA_CH1_S)
+#define H264_DMA_OUTFIFO_WDATA_CH1_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH1_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH1    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH1_M  (H264_DMA_OUTFIFO_PUSH_CH1_V << H264_DMA_OUTFIFO_PUSH_CH1_S)
+#define H264_DMA_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH1_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH1_REG register
+ *  TX CH1 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH1_REG (DR_REG_H264_DMA_BASE + 0x11c)
+/** H264_DMA_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH1    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH1_M  (H264_DMA_OUTLINK_STOP_CH1_V << H264_DMA_OUTLINK_STOP_CH1_S)
+#define H264_DMA_OUTLINK_STOP_CH1_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH1_S  20
+/** H264_DMA_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH1    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH1_M  (H264_DMA_OUTLINK_START_CH1_V << H264_DMA_OUTLINK_START_CH1_S)
+#define H264_DMA_OUTLINK_START_CH1_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH1_S  21
+/** H264_DMA_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH1    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH1_M  (H264_DMA_OUTLINK_RESTART_CH1_V << H264_DMA_OUTLINK_RESTART_CH1_S)
+#define H264_DMA_OUTLINK_RESTART_CH1_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH1_S  22
+/** H264_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH1    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH1_M  (H264_DMA_OUTLINK_PARK_CH1_V << H264_DMA_OUTLINK_PARK_CH1_S)
+#define H264_DMA_OUTLINK_PARK_CH1_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH1_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH1_REG register
+ *  TX CH1 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x120)
+/** H264_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH1_M  (H264_DMA_OUTLINK_ADDR_CH1_V << H264_DMA_OUTLINK_ADDR_CH1_S)
+#define H264_DMA_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH1_S  0
+
+/** H264_DMA_OUT_STATE_CH1_REG register
+ *  TX CH1 state register
+ */
+#define H264_DMA_OUT_STATE_CH1_REG (DR_REG_H264_DMA_BASE + 0x124)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH1_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH1_V << H264_DMA_OUTLINK_DSCR_ADDR_CH1_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH1_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH1    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH1_M  (H264_DMA_OUT_DSCR_STATE_CH1_V << H264_DMA_OUT_DSCR_STATE_CH1_S)
+#define H264_DMA_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH1_S  18
+/** H264_DMA_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH1    0x0000000FU
+#define H264_DMA_OUT_STATE_CH1_M  (H264_DMA_OUT_STATE_CH1_V << H264_DMA_OUT_STATE_CH1_S)
+#define H264_DMA_OUT_STATE_CH1_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH1_S  20
+/** H264_DMA_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_OUT_RESET_AVAIL_CH1    (BIT(24))
+#define H264_DMA_OUT_RESET_AVAIL_CH1_M  (H264_DMA_OUT_RESET_AVAIL_CH1_V << H264_DMA_OUT_RESET_AVAIL_CH1_S)
+#define H264_DMA_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define H264_DMA_OUT_RESET_AVAIL_CH1_S  24
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH1_REG register
+ *  TX CH1 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x128)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1_M  (H264_DMA_OUT_EOF_DES_ADDR_CH1_V << H264_DMA_OUT_EOF_DES_ADDR_CH1_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** H264_DMA_OUT_DSCR_CH1_REG register
+ *  TX CH1 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH1_REG (DR_REG_H264_DMA_BASE + 0x12c)
+/** H264_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH1_M  (H264_DMA_OUTLINK_DSCR_CH1_V << H264_DMA_OUTLINK_DSCR_CH1_S)
+#define H264_DMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH1_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH1_REG register
+ *  TX CH1 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_H264_DMA_BASE + 0x130)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH1_M  (H264_DMA_OUTLINK_DSCR_BF0_CH1_V << H264_DMA_OUTLINK_DSCR_BF0_CH1_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH1_REG register
+ *  TX CH1 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_H264_DMA_BASE + 0x134)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH1_M  (H264_DMA_OUTLINK_DSCR_BF1_CH1_V << H264_DMA_OUTLINK_DSCR_BF1_CH1_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** H264_DMA_OUT_ARB_CH1_REG register
+ *  TX CH1 arb register
+ */
+#define H264_DMA_OUT_ARB_CH1_REG (DR_REG_H264_DMA_BASE + 0x13c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH1_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH1_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH1_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH1_S  0
+/** H264_DMA_INTER_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH1    (BIT(6))
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_M  (H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_V << H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_S)
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_V  0x00000001U
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH1_S  6
+
+/** H264_DMA_OUT_ETM_CONF_CH1_REG register
+ *  TX CH1 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH1_REG (DR_REG_H264_DMA_BASE + 0x168)
+/** H264_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH1    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH1_M  (H264_DMA_OUT_ETM_EN_CH1_V << H264_DMA_OUT_ETM_EN_CH1_S)
+#define H264_DMA_OUT_ETM_EN_CH1_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH1_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH1    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH1_M  (H264_DMA_OUT_ETM_LOOP_EN_CH1_V << H264_DMA_OUT_ETM_LOOP_EN_CH1_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH1_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH1_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH1    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH1_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH1_V << H264_DMA_OUT_DSCR_TASK_MAK_CH1_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH1_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH1_REG register
+ *  tx CH1 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH1_REG (DR_REG_H264_DMA_BASE + 0x170)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH1_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH1_REG register
+ *  tx CH1 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH1_REG (DR_REG_H264_DMA_BASE + 0x174)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH1_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH1_REG register
+ *  tx CH1 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH1_REG (DR_REG_H264_DMA_BASE + 0x178)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1 : RO; bitpos: [7:0]; default: 255;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH1_S  0
+
+/** H264_DMA_OUT_XADDR_CH1_REG register
+ *  tx CH1 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x17c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH1_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH1_V << H264_DMA_OUT_CMDFIFO_XADDR_CH1_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH1_S  0
+
+/** H264_DMA_OUT_CONF0_CH2_REG register
+ *  TX CH2 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH2_REG (DR_REG_H264_DMA_BASE + 0x200)
+/** H264_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH2    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH2_M  (H264_DMA_OUT_AUTO_WRBACK_CH2_V << H264_DMA_OUT_AUTO_WRBACK_CH2_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH2_S  0
+/** H264_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH2    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH2_M  (H264_DMA_OUT_EOF_MODE_CH2_V << H264_DMA_OUT_EOF_MODE_CH2_S)
+#define H264_DMA_OUT_EOF_MODE_CH2_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH2_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH2    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH2_M  (H264_DMA_OUTDSCR_BURST_EN_CH2_V << H264_DMA_OUTDSCR_BURST_EN_CH2_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH2_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH2    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH2_M  (H264_DMA_OUT_ECC_AES_EN_CH2_V << H264_DMA_OUT_ECC_AES_EN_CH2_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH2_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH2_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH2    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH2_M  (H264_DMA_OUT_CHECK_OWNER_CH2_V << H264_DMA_OUT_CHECK_OWNER_CH2_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH2_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH2    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH2_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH2_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH2_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH2_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH2    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH2_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH2_V << H264_DMA_OUT_PAGE_BOUND_EN_CH2_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH2_S  12
+/** H264_DMA_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define H264_DMA_OUT_RST_CH2    (BIT(24))
+#define H264_DMA_OUT_RST_CH2_M  (H264_DMA_OUT_RST_CH2_V << H264_DMA_OUT_RST_CH2_S)
+#define H264_DMA_OUT_RST_CH2_V  0x00000001U
+#define H264_DMA_OUT_RST_CH2_S  24
+/** H264_DMA_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_OUT_CMD_DISABLE_CH2    (BIT(25))
+#define H264_DMA_OUT_CMD_DISABLE_CH2_M  (H264_DMA_OUT_CMD_DISABLE_CH2_V << H264_DMA_OUT_CMD_DISABLE_CH2_S)
+#define H264_DMA_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define H264_DMA_OUT_CMD_DISABLE_CH2_S  25
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH2_REG register
+ *  TX CH2  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH2_REG (DR_REG_H264_DMA_BASE + 0x204)
+/** H264_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH2_INT_RAW_M  (H264_DMA_OUT_DONE_CH2_INT_RAW_V << H264_DMA_OUT_DONE_CH2_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH2_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH2_INT_RAW_M  (H264_DMA_OUT_EOF_CH2_INT_RAW_V << H264_DMA_OUT_EOF_CH2_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH2_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH2_REG register
+ *  TX CH2  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH2_REG (DR_REG_H264_DMA_BASE + 0x208)
+/** H264_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH2_INT_ENA_M  (H264_DMA_OUT_DONE_CH2_INT_ENA_V << H264_DMA_OUT_DONE_CH2_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH2_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH2_INT_ENA_M  (H264_DMA_OUT_EOF_CH2_INT_ENA_V << H264_DMA_OUT_EOF_CH2_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH2_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH2_REG register
+ *  TX CH2  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH2_REG (DR_REG_H264_DMA_BASE + 0x20c)
+/** H264_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH2_INT_ST_M  (H264_DMA_OUT_DONE_CH2_INT_ST_V << H264_DMA_OUT_DONE_CH2_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH2_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH2_INT_ST_M  (H264_DMA_OUT_EOF_CH2_INT_ST_V << H264_DMA_OUT_EOF_CH2_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH2_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH2_REG register
+ *  TX CH2  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH2_REG (DR_REG_H264_DMA_BASE + 0x210)
+/** H264_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH2_INT_CLR_M  (H264_DMA_OUT_DONE_CH2_INT_CLR_V << H264_DMA_OUT_DONE_CH2_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH2_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH2_INT_CLR_M  (H264_DMA_OUT_EOF_CH2_INT_CLR_V << H264_DMA_OUT_EOF_CH2_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH2_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH2_REG register
+ *  TX CH2 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_H264_DMA_BASE + 0x214)
+/** H264_DMA_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH2    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH2_M  (H264_DMA_OUTFIFO_FULL_L2_CH2_V << H264_DMA_OUTFIFO_FULL_L2_CH2_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH2_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH2    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH2_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH2_V << H264_DMA_OUTFIFO_EMPTY_L2_CH2_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH2_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH2    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH2_M  (H264_DMA_OUTFIFO_CNT_L2_CH2_V << H264_DMA_OUTFIFO_CNT_L2_CH2_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH2_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH2_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH2    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH2_M  (H264_DMA_OUTFIFO_FULL_L1_CH2_V << H264_DMA_OUTFIFO_FULL_L1_CH2_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH2_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH2    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH2_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH2_V << H264_DMA_OUTFIFO_EMPTY_L1_CH2_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH2_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH2    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH2_M  (H264_DMA_OUTFIFO_CNT_L1_CH2_V << H264_DMA_OUTFIFO_CNT_L1_CH2_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH2_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH2_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH2    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH2_M  (H264_DMA_OUTFIFO_FULL_L3_CH2_V << H264_DMA_OUTFIFO_FULL_L3_CH2_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH2_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH2    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH2_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH2_V << H264_DMA_OUTFIFO_EMPTY_L3_CH2_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH2_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH2    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH2_M  (H264_DMA_OUTFIFO_CNT_L3_CH2_V << H264_DMA_OUTFIFO_CNT_L3_CH2_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH2_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH2_S  18
+
+/** H264_DMA_OUT_PUSH_CH2_REG register
+ *  TX CH2 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH2_REG (DR_REG_H264_DMA_BASE + 0x218)
+/** H264_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH2    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH2_M  (H264_DMA_OUTFIFO_WDATA_CH2_V << H264_DMA_OUTFIFO_WDATA_CH2_S)
+#define H264_DMA_OUTFIFO_WDATA_CH2_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH2_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH2    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH2_M  (H264_DMA_OUTFIFO_PUSH_CH2_V << H264_DMA_OUTFIFO_PUSH_CH2_S)
+#define H264_DMA_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH2_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH2_REG register
+ *  TX CH2 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH2_REG (DR_REG_H264_DMA_BASE + 0x21c)
+/** H264_DMA_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH2    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH2_M  (H264_DMA_OUTLINK_STOP_CH2_V << H264_DMA_OUTLINK_STOP_CH2_S)
+#define H264_DMA_OUTLINK_STOP_CH2_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH2_S  20
+/** H264_DMA_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH2    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH2_M  (H264_DMA_OUTLINK_START_CH2_V << H264_DMA_OUTLINK_START_CH2_S)
+#define H264_DMA_OUTLINK_START_CH2_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH2_S  21
+/** H264_DMA_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH2    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH2_M  (H264_DMA_OUTLINK_RESTART_CH2_V << H264_DMA_OUTLINK_RESTART_CH2_S)
+#define H264_DMA_OUTLINK_RESTART_CH2_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH2_S  22
+/** H264_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH2    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH2_M  (H264_DMA_OUTLINK_PARK_CH2_V << H264_DMA_OUTLINK_PARK_CH2_S)
+#define H264_DMA_OUTLINK_PARK_CH2_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH2_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH2_REG register
+ *  TX CH2 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x220)
+/** H264_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH2_M  (H264_DMA_OUTLINK_ADDR_CH2_V << H264_DMA_OUTLINK_ADDR_CH2_S)
+#define H264_DMA_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH2_S  0
+
+/** H264_DMA_OUT_STATE_CH2_REG register
+ *  TX CH2 state register
+ */
+#define H264_DMA_OUT_STATE_CH2_REG (DR_REG_H264_DMA_BASE + 0x224)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH2_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH2_V << H264_DMA_OUTLINK_DSCR_ADDR_CH2_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH2_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH2    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH2_M  (H264_DMA_OUT_DSCR_STATE_CH2_V << H264_DMA_OUT_DSCR_STATE_CH2_S)
+#define H264_DMA_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH2_S  18
+/** H264_DMA_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH2    0x0000000FU
+#define H264_DMA_OUT_STATE_CH2_M  (H264_DMA_OUT_STATE_CH2_V << H264_DMA_OUT_STATE_CH2_S)
+#define H264_DMA_OUT_STATE_CH2_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH2_S  20
+/** H264_DMA_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_OUT_RESET_AVAIL_CH2    (BIT(24))
+#define H264_DMA_OUT_RESET_AVAIL_CH2_M  (H264_DMA_OUT_RESET_AVAIL_CH2_V << H264_DMA_OUT_RESET_AVAIL_CH2_S)
+#define H264_DMA_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define H264_DMA_OUT_RESET_AVAIL_CH2_S  24
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH2_REG register
+ *  TX CH2 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x228)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2_M  (H264_DMA_OUT_EOF_DES_ADDR_CH2_V << H264_DMA_OUT_EOF_DES_ADDR_CH2_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** H264_DMA_OUT_DSCR_CH2_REG register
+ *  TX CH2 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH2_REG (DR_REG_H264_DMA_BASE + 0x22c)
+/** H264_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH2_M  (H264_DMA_OUTLINK_DSCR_CH2_V << H264_DMA_OUTLINK_DSCR_CH2_S)
+#define H264_DMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH2_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH2_REG register
+ *  TX CH2 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_H264_DMA_BASE + 0x230)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH2_M  (H264_DMA_OUTLINK_DSCR_BF0_CH2_V << H264_DMA_OUTLINK_DSCR_BF0_CH2_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH2_REG register
+ *  TX CH2 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_H264_DMA_BASE + 0x234)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH2_M  (H264_DMA_OUTLINK_DSCR_BF1_CH2_V << H264_DMA_OUTLINK_DSCR_BF1_CH2_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** H264_DMA_OUT_ARB_CH2_REG register
+ *  TX CH2 arb register
+ */
+#define H264_DMA_OUT_ARB_CH2_REG (DR_REG_H264_DMA_BASE + 0x23c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH2_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH2_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH2_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH2_S  0
+/** H264_DMA_INTER_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH2    (BIT(6))
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_M  (H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_V << H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_S)
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_V  0x00000001U
+#define H264_DMA_INTER_OUT_ARB_PRIORITY_CH2_S  6
+
+/** H264_DMA_OUT_ETM_CONF_CH2_REG register
+ *  TX CH2 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH2_REG (DR_REG_H264_DMA_BASE + 0x268)
+/** H264_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH2    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH2_M  (H264_DMA_OUT_ETM_EN_CH2_V << H264_DMA_OUT_ETM_EN_CH2_S)
+#define H264_DMA_OUT_ETM_EN_CH2_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH2_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH2    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH2_M  (H264_DMA_OUT_ETM_LOOP_EN_CH2_V << H264_DMA_OUT_ETM_LOOP_EN_CH2_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH2_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH2_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH2    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH2_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH2_V << H264_DMA_OUT_DSCR_TASK_MAK_CH2_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH2_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH2_REG register
+ *  tx CH2 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH2_REG (DR_REG_H264_DMA_BASE + 0x270)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH2_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH2_REG register
+ *  tx CH2 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH2_REG (DR_REG_H264_DMA_BASE + 0x274)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH2_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH2_REG register
+ *  tx CH2 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH2_REG (DR_REG_H264_DMA_BASE + 0x278)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2 : RO; bitpos: [7:0]; default: 255;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH2_S  0
+
+/** H264_DMA_OUT_XADDR_CH2_REG register
+ *  tx CH2 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x27c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH2_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH2_V << H264_DMA_OUT_CMDFIFO_XADDR_CH2_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH2_S  0
+
+/** H264_DMA_OUT_CONF0_CH3_REG register
+ *  TX CH3 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH3_REG (DR_REG_H264_DMA_BASE + 0x300)
+/** H264_DMA_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH3    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH3_M  (H264_DMA_OUT_AUTO_WRBACK_CH3_V << H264_DMA_OUT_AUTO_WRBACK_CH3_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH3_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH3_S  0
+/** H264_DMA_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH3    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH3_M  (H264_DMA_OUT_EOF_MODE_CH3_V << H264_DMA_OUT_EOF_MODE_CH3_S)
+#define H264_DMA_OUT_EOF_MODE_CH3_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH3_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH3    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH3_M  (H264_DMA_OUTDSCR_BURST_EN_CH3_V << H264_DMA_OUTDSCR_BURST_EN_CH3_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH3_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH3_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH3    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH3_M  (H264_DMA_OUT_ECC_AES_EN_CH3_V << H264_DMA_OUT_ECC_AES_EN_CH3_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH3_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH3_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH3    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH3_M  (H264_DMA_OUT_CHECK_OWNER_CH3_V << H264_DMA_OUT_CHECK_OWNER_CH3_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH3_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH3_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 3. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH3    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH3_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH3_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH3_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH3_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH3_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH3    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH3_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH3_V << H264_DMA_OUT_PAGE_BOUND_EN_CH3_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH3_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH3_S  12
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH3_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH3_REG register
+ *  TX CH3  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH3_REG (DR_REG_H264_DMA_BASE + 0x304)
+/** H264_DMA_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH3_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH3_INT_RAW_M  (H264_DMA_OUT_DONE_CH3_INT_RAW_V << H264_DMA_OUT_DONE_CH3_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH3_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH3_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH3_INT_RAW_M  (H264_DMA_OUT_EOF_CH3_INT_RAW_V << H264_DMA_OUT_EOF_CH3_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH3_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH3_REG register
+ *  TX CH3  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH3_REG (DR_REG_H264_DMA_BASE + 0x308)
+/** H264_DMA_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH3_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH3_INT_ENA_M  (H264_DMA_OUT_DONE_CH3_INT_ENA_V << H264_DMA_OUT_DONE_CH3_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH3_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH3_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH3_INT_ENA_M  (H264_DMA_OUT_EOF_CH3_INT_ENA_V << H264_DMA_OUT_EOF_CH3_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH3_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH3_REG register
+ *  TX CH3  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH3_REG (DR_REG_H264_DMA_BASE + 0x30c)
+/** H264_DMA_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH3_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH3_INT_ST_M  (H264_DMA_OUT_DONE_CH3_INT_ST_V << H264_DMA_OUT_DONE_CH3_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH3_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH3_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH3_INT_ST_M  (H264_DMA_OUT_EOF_CH3_INT_ST_V << H264_DMA_OUT_EOF_CH3_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH3_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH3_REG register
+ *  TX CH3  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH3_REG (DR_REG_H264_DMA_BASE + 0x310)
+/** H264_DMA_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH3_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH3_INT_CLR_M  (H264_DMA_OUT_DONE_CH3_INT_CLR_V << H264_DMA_OUT_DONE_CH3_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH3_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH3_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH3_INT_CLR_M  (H264_DMA_OUT_EOF_CH3_INT_CLR_V << H264_DMA_OUT_EOF_CH3_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH3_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH3_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH3_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH3_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH3_REG register
+ *  TX CH3 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH3_REG (DR_REG_H264_DMA_BASE + 0x314)
+/** H264_DMA_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH3    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH3_M  (H264_DMA_OUTFIFO_FULL_L2_CH3_V << H264_DMA_OUTFIFO_FULL_L2_CH3_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH3_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH3    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH3_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH3_V << H264_DMA_OUTFIFO_EMPTY_L2_CH3_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH3_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH3    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH3_M  (H264_DMA_OUTFIFO_CNT_L2_CH3_V << H264_DMA_OUTFIFO_CNT_L2_CH3_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH3_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH3_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH3    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH3_M  (H264_DMA_OUTFIFO_FULL_L1_CH3_V << H264_DMA_OUTFIFO_FULL_L1_CH3_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH3_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH3    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH3_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH3_V << H264_DMA_OUTFIFO_EMPTY_L1_CH3_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH3_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH3    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH3_M  (H264_DMA_OUTFIFO_CNT_L1_CH3_V << H264_DMA_OUTFIFO_CNT_L1_CH3_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH3_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH3_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH3    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH3_M  (H264_DMA_OUTFIFO_FULL_L3_CH3_V << H264_DMA_OUTFIFO_FULL_L3_CH3_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH3_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH3    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH3_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH3_V << H264_DMA_OUTFIFO_EMPTY_L3_CH3_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH3_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH3    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH3_M  (H264_DMA_OUTFIFO_CNT_L3_CH3_V << H264_DMA_OUTFIFO_CNT_L3_CH3_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH3_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH3_S  18
+
+/** H264_DMA_OUT_PUSH_CH3_REG register
+ *  TX CH3 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH3_REG (DR_REG_H264_DMA_BASE + 0x318)
+/** H264_DMA_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH3    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH3_M  (H264_DMA_OUTFIFO_WDATA_CH3_V << H264_DMA_OUTFIFO_WDATA_CH3_S)
+#define H264_DMA_OUTFIFO_WDATA_CH3_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH3_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH3    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH3_M  (H264_DMA_OUTFIFO_PUSH_CH3_V << H264_DMA_OUTFIFO_PUSH_CH3_S)
+#define H264_DMA_OUTFIFO_PUSH_CH3_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH3_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH3_REG register
+ *  TX CH3 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH3_REG (DR_REG_H264_DMA_BASE + 0x31c)
+/** H264_DMA_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH3    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH3_M  (H264_DMA_OUTLINK_STOP_CH3_V << H264_DMA_OUTLINK_STOP_CH3_S)
+#define H264_DMA_OUTLINK_STOP_CH3_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH3_S  20
+/** H264_DMA_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH3    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH3_M  (H264_DMA_OUTLINK_START_CH3_V << H264_DMA_OUTLINK_START_CH3_S)
+#define H264_DMA_OUTLINK_START_CH3_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH3_S  21
+/** H264_DMA_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH3    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH3_M  (H264_DMA_OUTLINK_RESTART_CH3_V << H264_DMA_OUTLINK_RESTART_CH3_S)
+#define H264_DMA_OUTLINK_RESTART_CH3_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH3_S  22
+/** H264_DMA_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH3    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH3_M  (H264_DMA_OUTLINK_PARK_CH3_V << H264_DMA_OUTLINK_PARK_CH3_S)
+#define H264_DMA_OUTLINK_PARK_CH3_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH3_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH3_REG register
+ *  TX CH3 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x320)
+/** H264_DMA_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH3_M  (H264_DMA_OUTLINK_ADDR_CH3_V << H264_DMA_OUTLINK_ADDR_CH3_S)
+#define H264_DMA_OUTLINK_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH3_S  0
+
+/** H264_DMA_OUT_STATE_CH3_REG register
+ *  TX CH3 state register
+ */
+#define H264_DMA_OUT_STATE_CH3_REG (DR_REG_H264_DMA_BASE + 0x324)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH3    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH3_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH3_V << H264_DMA_OUTLINK_DSCR_ADDR_CH3_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH3_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH3_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH3    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH3_M  (H264_DMA_OUT_DSCR_STATE_CH3_V << H264_DMA_OUT_DSCR_STATE_CH3_S)
+#define H264_DMA_OUT_DSCR_STATE_CH3_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH3_S  18
+/** H264_DMA_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH3    0x0000000FU
+#define H264_DMA_OUT_STATE_CH3_M  (H264_DMA_OUT_STATE_CH3_V << H264_DMA_OUT_STATE_CH3_S)
+#define H264_DMA_OUT_STATE_CH3_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH3_S  20
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH3_REG register
+ *  TX CH3 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x328)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3_M  (H264_DMA_OUT_EOF_DES_ADDR_CH3_V << H264_DMA_OUT_EOF_DES_ADDR_CH3_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH3_S  0
+
+/** H264_DMA_OUT_DSCR_CH3_REG register
+ *  TX CH3 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH3_REG (DR_REG_H264_DMA_BASE + 0x32c)
+/** H264_DMA_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH3    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH3_M  (H264_DMA_OUTLINK_DSCR_CH3_V << H264_DMA_OUTLINK_DSCR_CH3_S)
+#define H264_DMA_OUTLINK_DSCR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH3_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH3_REG register
+ *  TX CH3 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH3_REG (DR_REG_H264_DMA_BASE + 0x330)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH3    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH3_M  (H264_DMA_OUTLINK_DSCR_BF0_CH3_V << H264_DMA_OUTLINK_DSCR_BF0_CH3_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH3_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH3_REG register
+ *  TX CH3 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH3_REG (DR_REG_H264_DMA_BASE + 0x334)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH3    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH3_M  (H264_DMA_OUTLINK_DSCR_BF1_CH3_V << H264_DMA_OUTLINK_DSCR_BF1_CH3_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH3_S  0
+
+/** H264_DMA_OUT_ARB_CH3_REG register
+ *  TX CH3 arb register
+ */
+#define H264_DMA_OUT_ARB_CH3_REG (DR_REG_H264_DMA_BASE + 0x33c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH3    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH3_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH3_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH3_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH3_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH3_S  0
+/** H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3    0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_M  (H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_V << H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_S)
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_V  0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH3_S  4
+
+/** H264_DMA_OUT_ETM_CONF_CH3_REG register
+ *  TX CH3 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH3_REG (DR_REG_H264_DMA_BASE + 0x368)
+/** H264_DMA_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH3    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH3_M  (H264_DMA_OUT_ETM_EN_CH3_V << H264_DMA_OUT_ETM_EN_CH3_S)
+#define H264_DMA_OUT_ETM_EN_CH3_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH3_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH3    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH3_M  (H264_DMA_OUT_ETM_LOOP_EN_CH3_V << H264_DMA_OUT_ETM_LOOP_EN_CH3_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH3_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH3_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH3    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH3_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH3_V << H264_DMA_OUT_DSCR_TASK_MAK_CH3_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH3_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH3_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH3_REG register
+ *  tx CH3 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH3_REG (DR_REG_H264_DMA_BASE + 0x370)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH3_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH3_REG register
+ *  tx CH3 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH3_REG (DR_REG_H264_DMA_BASE + 0x374)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH3_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH3_REG register
+ *  tx CH3 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH3_REG (DR_REG_H264_DMA_BASE + 0x378)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3 : RO; bitpos: [7:0]; default: 63;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH3_S  0
+
+/** H264_DMA_OUT_XADDR_CH3_REG register
+ *  tx CH3 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x37c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH3_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH3_V << H264_DMA_OUT_CMDFIFO_XADDR_CH3_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH3_S  0
+
+/** H264_DMA_OUT_BLOCK_BUF_LEN_CH3_REG register
+ *  tx CH3 block buf len register
+ */
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3_REG (DR_REG_H264_DMA_BASE + 0x380)
+/** H264_DMA_OUT_BLOCK_BUF_LEN_CH3 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3    0x0FFFFFFFU
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3_M  (H264_DMA_OUT_BLOCK_BUF_LEN_CH3_V << H264_DMA_OUT_BLOCK_BUF_LEN_CH3_S)
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3_V  0x0FFFFFFFU
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH3_S  0
+
+/** H264_DMA_OUT_CONF0_CH4_REG register
+ *  TX CH4 config0 register
+ */
+#define H264_DMA_OUT_CONF0_CH4_REG (DR_REG_H264_DMA_BASE + 0x400)
+/** H264_DMA_OUT_AUTO_WRBACK_CH4 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define H264_DMA_OUT_AUTO_WRBACK_CH4    (BIT(0))
+#define H264_DMA_OUT_AUTO_WRBACK_CH4_M  (H264_DMA_OUT_AUTO_WRBACK_CH4_V << H264_DMA_OUT_AUTO_WRBACK_CH4_S)
+#define H264_DMA_OUT_AUTO_WRBACK_CH4_V  0x00000001U
+#define H264_DMA_OUT_AUTO_WRBACK_CH4_S  0
+/** H264_DMA_OUT_EOF_MODE_CH4 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define H264_DMA_OUT_EOF_MODE_CH4    (BIT(1))
+#define H264_DMA_OUT_EOF_MODE_CH4_M  (H264_DMA_OUT_EOF_MODE_CH4_V << H264_DMA_OUT_EOF_MODE_CH4_S)
+#define H264_DMA_OUT_EOF_MODE_CH4_V  0x00000001U
+#define H264_DMA_OUT_EOF_MODE_CH4_S  1
+/** H264_DMA_OUTDSCR_BURST_EN_CH4 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define H264_DMA_OUTDSCR_BURST_EN_CH4    (BIT(2))
+#define H264_DMA_OUTDSCR_BURST_EN_CH4_M  (H264_DMA_OUTDSCR_BURST_EN_CH4_V << H264_DMA_OUTDSCR_BURST_EN_CH4_S)
+#define H264_DMA_OUTDSCR_BURST_EN_CH4_V  0x00000001U
+#define H264_DMA_OUTDSCR_BURST_EN_CH4_S  2
+/** H264_DMA_OUT_ECC_AES_EN_CH4 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_OUT_ECC_AES_EN_CH4    (BIT(3))
+#define H264_DMA_OUT_ECC_AES_EN_CH4_M  (H264_DMA_OUT_ECC_AES_EN_CH4_V << H264_DMA_OUT_ECC_AES_EN_CH4_S)
+#define H264_DMA_OUT_ECC_AES_EN_CH4_V  0x00000001U
+#define H264_DMA_OUT_ECC_AES_EN_CH4_S  3
+/** H264_DMA_OUT_CHECK_OWNER_CH4 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_OUT_CHECK_OWNER_CH4    (BIT(4))
+#define H264_DMA_OUT_CHECK_OWNER_CH4_M  (H264_DMA_OUT_CHECK_OWNER_CH4_V << H264_DMA_OUT_CHECK_OWNER_CH4_S)
+#define H264_DMA_OUT_CHECK_OWNER_CH4_V  0x00000001U
+#define H264_DMA_OUT_CHECK_OWNER_CH4_S  4
+/** H264_DMA_OUT_MEM_BURST_LENGTH_CH4 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 4. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH4    0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH4_M  (H264_DMA_OUT_MEM_BURST_LENGTH_CH4_V << H264_DMA_OUT_MEM_BURST_LENGTH_CH4_S)
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH4_V  0x00000007U
+#define H264_DMA_OUT_MEM_BURST_LENGTH_CH4_S  6
+/** H264_DMA_OUT_PAGE_BOUND_EN_CH4 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH4    (BIT(12))
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH4_M  (H264_DMA_OUT_PAGE_BOUND_EN_CH4_V << H264_DMA_OUT_PAGE_BOUND_EN_CH4_S)
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH4_V  0x00000001U
+#define H264_DMA_OUT_PAGE_BOUND_EN_CH4_S  12
+/** H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4    (BIT(26))
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_M  (H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_V << H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_S)
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_V  0x00000001U
+#define H264_DMA_OUT_ARB_WEIGHT_OPT_DIS_CH4_S  26
+
+/** H264_DMA_OUT_INT_RAW_CH4_REG register
+ *  TX CH4  interrupt raw register
+ */
+#define H264_DMA_OUT_INT_RAW_CH4_REG (DR_REG_H264_DMA_BASE + 0x404)
+/** H264_DMA_OUT_DONE_CH4_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define H264_DMA_OUT_DONE_CH4_INT_RAW    (BIT(0))
+#define H264_DMA_OUT_DONE_CH4_INT_RAW_M  (H264_DMA_OUT_DONE_CH4_INT_RAW_V << H264_DMA_OUT_DONE_CH4_INT_RAW_S)
+#define H264_DMA_OUT_DONE_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH4_INT_RAW_S  0
+/** H264_DMA_OUT_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define H264_DMA_OUT_EOF_CH4_INT_RAW    (BIT(1))
+#define H264_DMA_OUT_EOF_CH4_INT_RAW_M  (H264_DMA_OUT_EOF_CH4_INT_RAW_V << H264_DMA_OUT_EOF_CH4_INT_RAW_S)
+#define H264_DMA_OUT_EOF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH4_INT_RAW_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_M  (H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_V << H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_RAW_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_M  (H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_V << H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_M  (H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_V << H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_RAW_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_M  (H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_V << H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_RAW_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_V << H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_RAW_S  8
+
+/** H264_DMA_OUT_INT_ENA_CH4_REG register
+ *  TX CH4  interrupt ena register
+ */
+#define H264_DMA_OUT_INT_ENA_CH4_REG (DR_REG_H264_DMA_BASE + 0x408)
+/** H264_DMA_OUT_DONE_CH4_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH4_INT_ENA    (BIT(0))
+#define H264_DMA_OUT_DONE_CH4_INT_ENA_M  (H264_DMA_OUT_DONE_CH4_INT_ENA_V << H264_DMA_OUT_DONE_CH4_INT_ENA_S)
+#define H264_DMA_OUT_DONE_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH4_INT_ENA_S  0
+/** H264_DMA_OUT_EOF_CH4_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH4_INT_ENA    (BIT(1))
+#define H264_DMA_OUT_EOF_CH4_INT_ENA_M  (H264_DMA_OUT_EOF_CH4_INT_ENA_V << H264_DMA_OUT_EOF_CH4_INT_ENA_S)
+#define H264_DMA_OUT_EOF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH4_INT_ENA_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_M  (H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_V << H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ENA_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_M  (H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_V << H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_M  (H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_V << H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ENA_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_M  (H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_V << H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ENA_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_V << H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ENA_S  8
+
+/** H264_DMA_OUT_INT_ST_CH4_REG register
+ *  TX CH4  interrupt st register
+ */
+#define H264_DMA_OUT_INT_ST_CH4_REG (DR_REG_H264_DMA_BASE + 0x40c)
+/** H264_DMA_OUT_DONE_CH4_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH4_INT_ST    (BIT(0))
+#define H264_DMA_OUT_DONE_CH4_INT_ST_M  (H264_DMA_OUT_DONE_CH4_INT_ST_V << H264_DMA_OUT_DONE_CH4_INT_ST_S)
+#define H264_DMA_OUT_DONE_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH4_INT_ST_S  0
+/** H264_DMA_OUT_EOF_CH4_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH4_INT_ST    (BIT(1))
+#define H264_DMA_OUT_EOF_CH4_INT_ST_M  (H264_DMA_OUT_EOF_CH4_INT_ST_V << H264_DMA_OUT_EOF_CH4_INT_ST_S)
+#define H264_DMA_OUT_EOF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH4_INT_ST_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH4_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ST    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_M  (H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_V << H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_S)
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_ST_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_M  (H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_V << H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_ST_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_V << H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_ST_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_V << H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_ST_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_M  (H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_V << H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_ST_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_M  (H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_V << H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_ST_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_V << H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_ST_S  8
+
+/** H264_DMA_OUT_INT_CLR_CH4_REG register
+ *  TX CH4  interrupt clr register
+ */
+#define H264_DMA_OUT_INT_CLR_CH4_REG (DR_REG_H264_DMA_BASE + 0x410)
+/** H264_DMA_OUT_DONE_CH4_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DONE_CH4_INT_CLR    (BIT(0))
+#define H264_DMA_OUT_DONE_CH4_INT_CLR_M  (H264_DMA_OUT_DONE_CH4_INT_CLR_V << H264_DMA_OUT_DONE_CH4_INT_CLR_S)
+#define H264_DMA_OUT_DONE_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DONE_CH4_INT_CLR_S  0
+/** H264_DMA_OUT_EOF_CH4_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_EOF_CH4_INT_CLR    (BIT(1))
+#define H264_DMA_OUT_EOF_CH4_INT_CLR_M  (H264_DMA_OUT_EOF_CH4_INT_CLR_V << H264_DMA_OUT_EOF_CH4_INT_CLR_S)
+#define H264_DMA_OUT_EOF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_EOF_CH4_INT_CLR_S  1
+/** H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR    (BIT(2))
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_M  (H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_V << H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_ERR_CH4_INT_CLR_S  2
+/** H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR    (BIT(3))
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_M  (H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_V << H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_S)
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_S  3
+/** H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR    (BIT(4))
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_S  4
+/** H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR    (BIT(5))
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_S  5
+/** H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR    (BIT(6))
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_M  (H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_V << H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_S)
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_OVF_L2_CH4_INT_CLR_S  6
+/** H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR    (BIT(7))
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_M  (H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_V << H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_S)
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUTFIFO_UDF_L2_CH4_INT_CLR_S  7
+/** H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR    (BIT(8))
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_M  (H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_V << H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_S)
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_OUT_DSCR_TASK_OVF_CH4_INT_CLR_S  8
+
+/** H264_DMA_OUTFIFO_STATUS_CH4_REG register
+ *  TX CH4 outfifo status register
+ */
+#define H264_DMA_OUTFIFO_STATUS_CH4_REG (DR_REG_H264_DMA_BASE + 0x414)
+/** H264_DMA_OUTFIFO_FULL_L2_CH4 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L2_CH4    (BIT(0))
+#define H264_DMA_OUTFIFO_FULL_L2_CH4_M  (H264_DMA_OUTFIFO_FULL_L2_CH4_V << H264_DMA_OUTFIFO_FULL_L2_CH4_S)
+#define H264_DMA_OUTFIFO_FULL_L2_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L2_CH4_S  0
+/** H264_DMA_OUTFIFO_EMPTY_L2_CH4 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH4    (BIT(1))
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH4_M  (H264_DMA_OUTFIFO_EMPTY_L2_CH4_V << H264_DMA_OUTFIFO_EMPTY_L2_CH4_S)
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L2_CH4_S  1
+/** H264_DMA_OUTFIFO_CNT_L2_CH4 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L2_CH4    0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH4_M  (H264_DMA_OUTFIFO_CNT_L2_CH4_V << H264_DMA_OUTFIFO_CNT_L2_CH4_S)
+#define H264_DMA_OUTFIFO_CNT_L2_CH4_V  0x0000000FU
+#define H264_DMA_OUTFIFO_CNT_L2_CH4_S  2
+/** H264_DMA_OUTFIFO_FULL_L1_CH4 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L1_CH4    (BIT(6))
+#define H264_DMA_OUTFIFO_FULL_L1_CH4_M  (H264_DMA_OUTFIFO_FULL_L1_CH4_V << H264_DMA_OUTFIFO_FULL_L1_CH4_S)
+#define H264_DMA_OUTFIFO_FULL_L1_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L1_CH4_S  6
+/** H264_DMA_OUTFIFO_EMPTY_L1_CH4 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH4    (BIT(7))
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH4_M  (H264_DMA_OUTFIFO_EMPTY_L1_CH4_V << H264_DMA_OUTFIFO_EMPTY_L1_CH4_S)
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L1_CH4_S  7
+/** H264_DMA_OUTFIFO_CNT_L1_CH4 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L1_CH4    0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH4_M  (H264_DMA_OUTFIFO_CNT_L1_CH4_V << H264_DMA_OUTFIFO_CNT_L1_CH4_S)
+#define H264_DMA_OUTFIFO_CNT_L1_CH4_V  0x0000001FU
+#define H264_DMA_OUTFIFO_CNT_L1_CH4_S  8
+/** H264_DMA_OUTFIFO_FULL_L3_CH4 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_FULL_L3_CH4    (BIT(16))
+#define H264_DMA_OUTFIFO_FULL_L3_CH4_M  (H264_DMA_OUTFIFO_FULL_L3_CH4_V << H264_DMA_OUTFIFO_FULL_L3_CH4_S)
+#define H264_DMA_OUTFIFO_FULL_L3_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_FULL_L3_CH4_S  16
+/** H264_DMA_OUTFIFO_EMPTY_L3_CH4 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH4    (BIT(17))
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH4_M  (H264_DMA_OUTFIFO_EMPTY_L3_CH4_V << H264_DMA_OUTFIFO_EMPTY_L3_CH4_S)
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_EMPTY_L3_CH4_S  17
+/** H264_DMA_OUTFIFO_CNT_L3_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+ */
+#define H264_DMA_OUTFIFO_CNT_L3_CH4    0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH4_M  (H264_DMA_OUTFIFO_CNT_L3_CH4_V << H264_DMA_OUTFIFO_CNT_L3_CH4_S)
+#define H264_DMA_OUTFIFO_CNT_L3_CH4_V  0x00000003U
+#define H264_DMA_OUTFIFO_CNT_L3_CH4_S  18
+
+/** H264_DMA_OUT_PUSH_CH4_REG register
+ *  TX CH4 outfifo push register
+ */
+#define H264_DMA_OUT_PUSH_CH4_REG (DR_REG_H264_DMA_BASE + 0x418)
+/** H264_DMA_OUTFIFO_WDATA_CH4 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_WDATA_CH4    0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH4_M  (H264_DMA_OUTFIFO_WDATA_CH4_V << H264_DMA_OUTFIFO_WDATA_CH4_S)
+#define H264_DMA_OUTFIFO_WDATA_CH4_V  0x000003FFU
+#define H264_DMA_OUTFIFO_WDATA_CH4_S  0
+/** H264_DMA_OUTFIFO_PUSH_CH4 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define H264_DMA_OUTFIFO_PUSH_CH4    (BIT(10))
+#define H264_DMA_OUTFIFO_PUSH_CH4_M  (H264_DMA_OUTFIFO_PUSH_CH4_V << H264_DMA_OUTFIFO_PUSH_CH4_S)
+#define H264_DMA_OUTFIFO_PUSH_CH4_V  0x00000001U
+#define H264_DMA_OUTFIFO_PUSH_CH4_S  10
+
+/** H264_DMA_OUT_LINK_CONF_CH4_REG register
+ *  TX CH4 out_link dscr ctrl register
+ */
+#define H264_DMA_OUT_LINK_CONF_CH4_REG (DR_REG_H264_DMA_BASE + 0x41c)
+/** H264_DMA_OUTLINK_STOP_CH4 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_STOP_CH4    (BIT(20))
+#define H264_DMA_OUTLINK_STOP_CH4_M  (H264_DMA_OUTLINK_STOP_CH4_V << H264_DMA_OUTLINK_STOP_CH4_S)
+#define H264_DMA_OUTLINK_STOP_CH4_V  0x00000001U
+#define H264_DMA_OUTLINK_STOP_CH4_S  20
+/** H264_DMA_OUTLINK_START_CH4 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define H264_DMA_OUTLINK_START_CH4    (BIT(21))
+#define H264_DMA_OUTLINK_START_CH4_M  (H264_DMA_OUTLINK_START_CH4_V << H264_DMA_OUTLINK_START_CH4_S)
+#define H264_DMA_OUTLINK_START_CH4_V  0x00000001U
+#define H264_DMA_OUTLINK_START_CH4_S  21
+/** H264_DMA_OUTLINK_RESTART_CH4 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define H264_DMA_OUTLINK_RESTART_CH4    (BIT(22))
+#define H264_DMA_OUTLINK_RESTART_CH4_M  (H264_DMA_OUTLINK_RESTART_CH4_V << H264_DMA_OUTLINK_RESTART_CH4_S)
+#define H264_DMA_OUTLINK_RESTART_CH4_V  0x00000001U
+#define H264_DMA_OUTLINK_RESTART_CH4_S  22
+/** H264_DMA_OUTLINK_PARK_CH4 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define H264_DMA_OUTLINK_PARK_CH4    (BIT(23))
+#define H264_DMA_OUTLINK_PARK_CH4_M  (H264_DMA_OUTLINK_PARK_CH4_V << H264_DMA_OUTLINK_PARK_CH4_S)
+#define H264_DMA_OUTLINK_PARK_CH4_V  0x00000001U
+#define H264_DMA_OUTLINK_PARK_CH4_S  23
+
+/** H264_DMA_OUT_LINK_ADDR_CH4_REG register
+ *  TX CH4 out_link dscr addr register
+ */
+#define H264_DMA_OUT_LINK_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x420)
+/** H264_DMA_OUTLINK_ADDR_CH4 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH4_M  (H264_DMA_OUTLINK_ADDR_CH4_V << H264_DMA_OUTLINK_ADDR_CH4_S)
+#define H264_DMA_OUTLINK_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_ADDR_CH4_S  0
+
+/** H264_DMA_OUT_STATE_CH4_REG register
+ *  TX CH4 state register
+ */
+#define H264_DMA_OUT_STATE_CH4_REG (DR_REG_H264_DMA_BASE + 0x424)
+/** H264_DMA_OUTLINK_DSCR_ADDR_CH4 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH4    0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH4_M  (H264_DMA_OUTLINK_DSCR_ADDR_CH4_V << H264_DMA_OUTLINK_DSCR_ADDR_CH4_S)
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH4_V  0x0003FFFFU
+#define H264_DMA_OUTLINK_DSCR_ADDR_CH4_S  0
+/** H264_DMA_OUT_DSCR_STATE_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_OUT_DSCR_STATE_CH4    0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH4_M  (H264_DMA_OUT_DSCR_STATE_CH4_V << H264_DMA_OUT_DSCR_STATE_CH4_S)
+#define H264_DMA_OUT_DSCR_STATE_CH4_V  0x00000003U
+#define H264_DMA_OUT_DSCR_STATE_CH4_S  18
+/** H264_DMA_OUT_STATE_CH4 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_OUT_STATE_CH4    0x0000000FU
+#define H264_DMA_OUT_STATE_CH4_M  (H264_DMA_OUT_STATE_CH4_V << H264_DMA_OUT_STATE_CH4_S)
+#define H264_DMA_OUT_STATE_CH4_V  0x0000000FU
+#define H264_DMA_OUT_STATE_CH4_S  20
+
+/** H264_DMA_OUT_EOF_DES_ADDR_CH4_REG register
+ *  TX CH4 eof des addr register
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x428)
+/** H264_DMA_OUT_EOF_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4_M  (H264_DMA_OUT_EOF_DES_ADDR_CH4_V << H264_DMA_OUT_EOF_DES_ADDR_CH4_S)
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUT_EOF_DES_ADDR_CH4_S  0
+
+/** H264_DMA_OUT_DSCR_CH4_REG register
+ *  TX CH4 next dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_CH4_REG (DR_REG_H264_DMA_BASE + 0x42c)
+/** H264_DMA_OUTLINK_DSCR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define H264_DMA_OUTLINK_DSCR_CH4    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH4_M  (H264_DMA_OUTLINK_DSCR_CH4_V << H264_DMA_OUTLINK_DSCR_CH4_S)
+#define H264_DMA_OUTLINK_DSCR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_CH4_S  0
+
+/** H264_DMA_OUT_DSCR_BF0_CH4_REG register
+ *  TX CH4 last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF0_CH4_REG (DR_REG_H264_DMA_BASE + 0x430)
+/** H264_DMA_OUTLINK_DSCR_BF0_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF0_CH4    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH4_M  (H264_DMA_OUTLINK_DSCR_BF0_CH4_V << H264_DMA_OUTLINK_DSCR_BF0_CH4_S)
+#define H264_DMA_OUTLINK_DSCR_BF0_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF0_CH4_S  0
+
+/** H264_DMA_OUT_DSCR_BF1_CH4_REG register
+ *  TX CH4 second-to-last dscr addr register
+ */
+#define H264_DMA_OUT_DSCR_BF1_CH4_REG (DR_REG_H264_DMA_BASE + 0x434)
+/** H264_DMA_OUTLINK_DSCR_BF1_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define H264_DMA_OUTLINK_DSCR_BF1_CH4    0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH4_M  (H264_DMA_OUTLINK_DSCR_BF1_CH4_V << H264_DMA_OUTLINK_DSCR_BF1_CH4_S)
+#define H264_DMA_OUTLINK_DSCR_BF1_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUTLINK_DSCR_BF1_CH4_S  0
+
+/** H264_DMA_OUT_ARB_CH4_REG register
+ *  TX CH4 arb register
+ */
+#define H264_DMA_OUT_ARB_CH4_REG (DR_REG_H264_DMA_BASE + 0x43c)
+/** H264_DMA_OUT_ARB_TOKEN_NUM_CH4 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH4    0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH4_M  (H264_DMA_OUT_ARB_TOKEN_NUM_CH4_V << H264_DMA_OUT_ARB_TOKEN_NUM_CH4_S)
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH4_V  0x0000000FU
+#define H264_DMA_OUT_ARB_TOKEN_NUM_CH4_S  0
+/** H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4    0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_M  (H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_V << H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_S)
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_V  0x00000003U
+#define H264_DMA_EXTER_OUT_ARB_PRIORITY_CH4_S  4
+
+/** H264_DMA_OUT_ETM_CONF_CH4_REG register
+ *  TX CH4 ETM config register
+ */
+#define H264_DMA_OUT_ETM_CONF_CH4_REG (DR_REG_H264_DMA_BASE + 0x468)
+/** H264_DMA_OUT_ETM_EN_CH4 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_OUT_ETM_EN_CH4    (BIT(0))
+#define H264_DMA_OUT_ETM_EN_CH4_M  (H264_DMA_OUT_ETM_EN_CH4_V << H264_DMA_OUT_ETM_EN_CH4_S)
+#define H264_DMA_OUT_ETM_EN_CH4_V  0x00000001U
+#define H264_DMA_OUT_ETM_EN_CH4_S  0
+/** H264_DMA_OUT_ETM_LOOP_EN_CH4 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_OUT_ETM_LOOP_EN_CH4    (BIT(1))
+#define H264_DMA_OUT_ETM_LOOP_EN_CH4_M  (H264_DMA_OUT_ETM_LOOP_EN_CH4_V << H264_DMA_OUT_ETM_LOOP_EN_CH4_S)
+#define H264_DMA_OUT_ETM_LOOP_EN_CH4_V  0x00000001U
+#define H264_DMA_OUT_ETM_LOOP_EN_CH4_S  1
+/** H264_DMA_OUT_DSCR_TASK_MAK_CH4 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH4    0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH4_M  (H264_DMA_OUT_DSCR_TASK_MAK_CH4_V << H264_DMA_OUT_DSCR_TASK_MAK_CH4_S)
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH4_V  0x00000003U
+#define H264_DMA_OUT_DSCR_TASK_MAK_CH4_S  2
+
+/** H264_DMA_OUT_BUF_LEN_CH4_REG register
+ *  tx CH4 buf len register
+ */
+#define H264_DMA_OUT_BUF_LEN_CH4_REG (DR_REG_H264_DMA_BASE + 0x470)
+/** H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4    0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_M  (H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_V << H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_S)
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_V  0x0FFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_BUF_LEN_HB_CH4_S  0
+
+/** H264_DMA_OUT_FIFO_BCNT_CH4_REG register
+ *  tx CH4 fifo byte cnt register
+ */
+#define H264_DMA_OUT_FIFO_BCNT_CH4_REG (DR_REG_H264_DMA_BASE + 0x474)
+/** H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4    0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_M  (H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_V << H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_S)
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_V  0x000003FFU
+#define H264_DMA_OUT_CMDFIFO_OUTFIFO_BCNT_CH4_S  0
+
+/** H264_DMA_OUT_PUSH_BYTECNT_CH4_REG register
+ *  tx CH4 push byte cnt register
+ */
+#define H264_DMA_OUT_PUSH_BYTECNT_CH4_REG (DR_REG_H264_DMA_BASE + 0x478)
+/** H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4 : RO; bitpos: [7:0]; default: 63;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4    0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_M  (H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_V << H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_S)
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_V  0x000000FFU
+#define H264_DMA_OUT_CMDFIFO_PUSH_BYTECNT_CH4_S  0
+
+/** H264_DMA_OUT_XADDR_CH4_REG register
+ *  tx CH4 xaddr register
+ */
+#define H264_DMA_OUT_XADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x47c)
+/** H264_DMA_OUT_CMDFIFO_XADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH4_M  (H264_DMA_OUT_CMDFIFO_XADDR_CH4_V << H264_DMA_OUT_CMDFIFO_XADDR_CH4_S)
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CMDFIFO_XADDR_CH4_S  0
+
+/** H264_DMA_OUT_BLOCK_BUF_LEN_CH4_REG register
+ *  tx CH4 block buf len register
+ */
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4_REG (DR_REG_H264_DMA_BASE + 0x480)
+/** H264_DMA_OUT_BLOCK_BUF_LEN_CH4 : RO; bitpos: [27:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4    0x0FFFFFFFU
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4_M  (H264_DMA_OUT_BLOCK_BUF_LEN_CH4_V << H264_DMA_OUT_BLOCK_BUF_LEN_CH4_S)
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4_V  0x0FFFFFFFU
+#define H264_DMA_OUT_BLOCK_BUF_LEN_CH4_S  0
+
+/** H264_DMA_IN_CONF0_CH0_REG register
+ *  RX CH0 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH0_REG (DR_REG_H264_DMA_BASE + 0x500)
+/** H264_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH0    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH0_M  (H264_DMA_INDSCR_BURST_EN_CH0_V << H264_DMA_INDSCR_BURST_EN_CH0_S)
+#define H264_DMA_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH0_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH0    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH0_M  (H264_DMA_IN_ECC_AES_EN_CH0_V << H264_DMA_IN_ECC_AES_EN_CH0_S)
+#define H264_DMA_IN_ECC_AES_EN_CH0_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH0_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH0    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH0_M  (H264_DMA_IN_CHECK_OWNER_CH0_V << H264_DMA_IN_CHECK_OWNER_CH0_S)
+#define H264_DMA_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH0_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH0    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH0_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH0_V << H264_DMA_IN_MEM_BURST_LENGTH_CH0_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH0_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH0    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH0_M  (H264_DMA_IN_PAGE_BOUND_EN_CH0_V << H264_DMA_IN_PAGE_BOUND_EN_CH0_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH0_S  12
+/** H264_DMA_IN_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH0    (BIT(24))
+#define H264_DMA_IN_RST_CH0_M  (H264_DMA_IN_RST_CH0_V << H264_DMA_IN_RST_CH0_S)
+#define H264_DMA_IN_RST_CH0_V  0x00000001U
+#define H264_DMA_IN_RST_CH0_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH0    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH0_M  (H264_DMA_IN_CMD_DISABLE_CH0_V << H264_DMA_IN_CMD_DISABLE_CH0_S)
+#define H264_DMA_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH0_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** H264_DMA_IN_INT_RAW_CH0_REG register
+ *  RX CH0  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH0_REG (DR_REG_H264_DMA_BASE + 0x504)
+/** H264_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define H264_DMA_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH0_INT_RAW_M  (H264_DMA_IN_DONE_CH0_INT_RAW_V << H264_DMA_IN_DONE_CH0_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH0_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define H264_DMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH0_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH0_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH0_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH0_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH0_REG register
+ *  RX CH0  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH0_REG (DR_REG_H264_DMA_BASE + 0x508)
+/** H264_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH0_INT_ENA_M  (H264_DMA_IN_DONE_CH0_INT_ENA_V << H264_DMA_IN_DONE_CH0_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH0_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH0_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH0_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH0_REG register
+ *  RX CH0  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH0_REG (DR_REG_H264_DMA_BASE + 0x50c)
+/** H264_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH0_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH0_INT_ST_M  (H264_DMA_IN_DONE_CH0_INT_ST_V << H264_DMA_IN_DONE_CH0_INT_ST_S)
+#define H264_DMA_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH0_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH0_INT_ST_V << H264_DMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH0_INT_ST_V << H264_DMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH0_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH0_REG register
+ *  RX CH0  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH0_REG (DR_REG_H264_DMA_BASE + 0x510)
+/** H264_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH0_INT_CLR_M  (H264_DMA_IN_DONE_CH0_INT_CLR_V << H264_DMA_IN_DONE_CH0_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH0_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH0_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH0_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH0_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH0_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH0_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH0_REG register
+ *  RX CH0 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH0_REG (DR_REG_H264_DMA_BASE + 0x514)
+/** H264_DMA_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH0    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH0_M  (H264_DMA_INFIFO_FULL_L2_CH0_V << H264_DMA_INFIFO_FULL_L2_CH0_S)
+#define H264_DMA_INFIFO_FULL_L2_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH0_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH0    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH0_M  (H264_DMA_INFIFO_EMPTY_L2_CH0_V << H264_DMA_INFIFO_EMPTY_L2_CH0_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH0_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH0    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH0_M  (H264_DMA_INFIFO_CNT_L2_CH0_V << H264_DMA_INFIFO_CNT_L2_CH0_S)
+#define H264_DMA_INFIFO_CNT_L2_CH0_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH0_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH0 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH0    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH0_M  (H264_DMA_INFIFO_FULL_L1_CH0_V << H264_DMA_INFIFO_FULL_L1_CH0_S)
+#define H264_DMA_INFIFO_FULL_L1_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH0_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH0    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH0_M  (H264_DMA_INFIFO_EMPTY_L1_CH0_V << H264_DMA_INFIFO_EMPTY_L1_CH0_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH0_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH0 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH0    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH0_M  (H264_DMA_INFIFO_CNT_L1_CH0_V << H264_DMA_INFIFO_CNT_L1_CH0_S)
+#define H264_DMA_INFIFO_CNT_L1_CH0_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH0_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH0 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH0    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH0_M  (H264_DMA_INFIFO_FULL_L3_CH0_V << H264_DMA_INFIFO_FULL_L3_CH0_S)
+#define H264_DMA_INFIFO_FULL_L3_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH0_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH0    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH0_M  (H264_DMA_INFIFO_EMPTY_L3_CH0_V << H264_DMA_INFIFO_EMPTY_L3_CH0_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH0_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH0    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH0_M  (H264_DMA_INFIFO_CNT_L3_CH0_V << H264_DMA_INFIFO_CNT_L3_CH0_S)
+#define H264_DMA_INFIFO_CNT_L3_CH0_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH0_S  18
+
+/** H264_DMA_IN_POP_CH0_REG register
+ *  RX CH0 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH0_REG (DR_REG_H264_DMA_BASE + 0x518)
+/** H264_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH0    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH0_M  (H264_DMA_INFIFO_RDATA_CH0_V << H264_DMA_INFIFO_RDATA_CH0_S)
+#define H264_DMA_INFIFO_RDATA_CH0_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH0_S  0
+/** H264_DMA_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH0    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH0_M  (H264_DMA_INFIFO_POP_CH0_V << H264_DMA_INFIFO_POP_CH0_S)
+#define H264_DMA_INFIFO_POP_CH0_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH0_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH0_REG register
+ *  RX CH0 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x51c)
+/** H264_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH0    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH0_M  (H264_DMA_INLINK_AUTO_RET_CH0_V << H264_DMA_INLINK_AUTO_RET_CH0_S)
+#define H264_DMA_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH0_S  20
+/** H264_DMA_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH0    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH0_M  (H264_DMA_INLINK_STOP_CH0_V << H264_DMA_INLINK_STOP_CH0_S)
+#define H264_DMA_INLINK_STOP_CH0_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH0_S  21
+/** H264_DMA_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH0    (BIT(22))
+#define H264_DMA_INLINK_START_CH0_M  (H264_DMA_INLINK_START_CH0_V << H264_DMA_INLINK_START_CH0_S)
+#define H264_DMA_INLINK_START_CH0_V  0x00000001U
+#define H264_DMA_INLINK_START_CH0_S  22
+/** H264_DMA_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH0    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH0_M  (H264_DMA_INLINK_RESTART_CH0_V << H264_DMA_INLINK_RESTART_CH0_S)
+#define H264_DMA_INLINK_RESTART_CH0_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH0_S  23
+/** H264_DMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH0    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH0_M  (H264_DMA_INLINK_PARK_CH0_V << H264_DMA_INLINK_PARK_CH0_S)
+#define H264_DMA_INLINK_PARK_CH0_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH0_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH0_REG register
+ *  RX CH0 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x520)
+/** H264_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH0_M  (H264_DMA_INLINK_ADDR_CH0_V << H264_DMA_INLINK_ADDR_CH0_S)
+#define H264_DMA_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH0_S  0
+
+/** H264_DMA_IN_STATE_CH0_REG register
+ *  RX CH0 state register
+ */
+#define H264_DMA_IN_STATE_CH0_REG (DR_REG_H264_DMA_BASE + 0x524)
+/** H264_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH0_M  (H264_DMA_INLINK_DSCR_ADDR_CH0_V << H264_DMA_INLINK_DSCR_ADDR_CH0_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH0_S  0
+/** H264_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH0    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH0_M  (H264_DMA_IN_DSCR_STATE_CH0_V << H264_DMA_IN_DSCR_STATE_CH0_S)
+#define H264_DMA_IN_DSCR_STATE_CH0_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH0_S  18
+/** H264_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH0    0x00000007U
+#define H264_DMA_IN_STATE_CH0_M  (H264_DMA_IN_STATE_CH0_V << H264_DMA_IN_STATE_CH0_S)
+#define H264_DMA_IN_STATE_CH0_V  0x00000007U
+#define H264_DMA_IN_STATE_CH0_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH0    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH0_M  (H264_DMA_IN_RESET_AVAIL_CH0_V << H264_DMA_IN_RESET_AVAIL_CH0_S)
+#define H264_DMA_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH0_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  RX CH0 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x528)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  RX CH0 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x52c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** H264_DMA_IN_DSCR_CH0_REG register
+ *  RX CH0 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH0_REG (DR_REG_H264_DMA_BASE + 0x530)
+/** H264_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH0_M  (H264_DMA_INLINK_DSCR_CH0_V << H264_DMA_INLINK_DSCR_CH0_S)
+#define H264_DMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH0_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH0_REG register
+ *  RX CH0 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_H264_DMA_BASE + 0x534)
+/** H264_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH0_M  (H264_DMA_INLINK_DSCR_BF0_CH0_V << H264_DMA_INLINK_DSCR_BF0_CH0_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH0_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH0_REG register
+ *  RX CH0 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_H264_DMA_BASE + 0x538)
+/** H264_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH0_M  (H264_DMA_INLINK_DSCR_BF1_CH0_V << H264_DMA_INLINK_DSCR_BF1_CH0_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH0_S  0
+
+/** H264_DMA_IN_ARB_CH0_REG register
+ *  RX CH0 arb register
+ */
+#define H264_DMA_IN_ARB_CH0_REG (DR_REG_H264_DMA_BASE + 0x540)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH0_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH0_V << H264_DMA_IN_ARB_TOKEN_NUM_CH0_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH0_S  0
+/** H264_DMA_EXTER_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH0    0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_M  (H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_V << H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_S)
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_V  0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH0_S  4
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH0    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH0_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH0_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH0_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH0_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH0_S  6
+
+/** H264_DMA_IN_RO_PD_CONF_CH0_REG register
+ *  RX CH0 reorder power config register
+ */
+#define H264_DMA_IN_RO_PD_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x548)
+/** H264_DMA_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define H264_DMA_IN_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define H264_DMA_IN_RO_RAM_CLK_FO_CH0_M  (H264_DMA_IN_RO_RAM_CLK_FO_CH0_V << H264_DMA_IN_RO_RAM_CLK_FO_CH0_S)
+#define H264_DMA_IN_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define H264_DMA_IN_RO_RAM_CLK_FO_CH0_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH0_REG register
+ *  RX CH0 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH0_REG (DR_REG_H264_DMA_BASE + 0x56c)
+/** H264_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH0    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH0_M  (H264_DMA_IN_ETM_EN_CH0_V << H264_DMA_IN_ETM_EN_CH0_S)
+#define H264_DMA_IN_ETM_EN_CH0_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH0_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH0    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH0_M  (H264_DMA_IN_ETM_LOOP_EN_CH0_V << H264_DMA_IN_ETM_LOOP_EN_CH0_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH0_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH0_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH0    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH0_M  (H264_DMA_IN_DSCR_TASK_MAK_CH0_V << H264_DMA_IN_DSCR_TASK_MAK_CH0_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH0_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH0_REG register
+ *  rx CH0 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH0_REG (DR_REG_H264_DMA_BASE + 0x580)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH0_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH0_REG register
+ *  rx CH0 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH0_REG (DR_REG_H264_DMA_BASE + 0x584)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH0_S  0
+
+/** H264_DMA_IN_XADDR_CH0_REG register
+ *  rx CH0 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH0_REG (DR_REG_H264_DMA_BASE + 0x588)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH0    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH0_M  (H264_DMA_IN_CMDFIFO_XADDR_CH0_V << H264_DMA_IN_CMDFIFO_XADDR_CH0_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH0_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH0_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH0_REG register
+ *  rx CH0 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH0_REG (DR_REG_H264_DMA_BASE + 0x58c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH0_S  0
+
+/** H264_DMA_IN_CONF0_CH1_REG register
+ *  RX CH1 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH1_REG (DR_REG_H264_DMA_BASE + 0x600)
+/** H264_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH1    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH1_M  (H264_DMA_INDSCR_BURST_EN_CH1_V << H264_DMA_INDSCR_BURST_EN_CH1_S)
+#define H264_DMA_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH1_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH1    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH1_M  (H264_DMA_IN_ECC_AES_EN_CH1_V << H264_DMA_IN_ECC_AES_EN_CH1_S)
+#define H264_DMA_IN_ECC_AES_EN_CH1_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH1_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH1    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH1_M  (H264_DMA_IN_CHECK_OWNER_CH1_V << H264_DMA_IN_CHECK_OWNER_CH1_S)
+#define H264_DMA_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH1_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH1    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH1_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH1_V << H264_DMA_IN_MEM_BURST_LENGTH_CH1_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH1_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH1    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH1_M  (H264_DMA_IN_PAGE_BOUND_EN_CH1_V << H264_DMA_IN_PAGE_BOUND_EN_CH1_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH1_S  12
+/** H264_DMA_IN_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH1    (BIT(24))
+#define H264_DMA_IN_RST_CH1_M  (H264_DMA_IN_RST_CH1_V << H264_DMA_IN_RST_CH1_S)
+#define H264_DMA_IN_RST_CH1_V  0x00000001U
+#define H264_DMA_IN_RST_CH1_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH1    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH1_M  (H264_DMA_IN_CMD_DISABLE_CH1_V << H264_DMA_IN_CMD_DISABLE_CH1_S)
+#define H264_DMA_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH1_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** H264_DMA_IN_INT_RAW_CH1_REG register
+ *  RX CH1  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH1_REG (DR_REG_H264_DMA_BASE + 0x604)
+/** H264_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH1_INT_RAW_M  (H264_DMA_IN_DONE_CH1_INT_RAW_V << H264_DMA_IN_DONE_CH1_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH1_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH1_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH1_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH1_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH1_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH1_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH1_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 1.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH1_REG register
+ *  RX CH1  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH1_REG (DR_REG_H264_DMA_BASE + 0x608)
+/** H264_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH1_INT_ENA_M  (H264_DMA_IN_DONE_CH1_INT_ENA_V << H264_DMA_IN_DONE_CH1_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH1_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH1_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH1_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH1_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH1_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH1_REG register
+ *  RX CH1  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH1_REG (DR_REG_H264_DMA_BASE + 0x60c)
+/** H264_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH1_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH1_INT_ST_M  (H264_DMA_IN_DONE_CH1_INT_ST_V << H264_DMA_IN_DONE_CH1_INT_ST_S)
+#define H264_DMA_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH1_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH1_INT_ST_V << H264_DMA_IN_SUC_EOF_CH1_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH1_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH1_INT_ST_V << H264_DMA_IN_ERR_EOF_CH1_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH1_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH1_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH1_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH1_REG register
+ *  RX CH1  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH1_REG (DR_REG_H264_DMA_BASE + 0x610)
+/** H264_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH1_INT_CLR_M  (H264_DMA_IN_DONE_CH1_INT_CLR_V << H264_DMA_IN_DONE_CH1_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH1_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH1_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH1_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH1_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH1_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH1_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH1_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH1_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH1_REG register
+ *  RX CH1 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH1_REG (DR_REG_H264_DMA_BASE + 0x614)
+/** H264_DMA_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH1    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH1_M  (H264_DMA_INFIFO_FULL_L2_CH1_V << H264_DMA_INFIFO_FULL_L2_CH1_S)
+#define H264_DMA_INFIFO_FULL_L2_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH1_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH1    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH1_M  (H264_DMA_INFIFO_EMPTY_L2_CH1_V << H264_DMA_INFIFO_EMPTY_L2_CH1_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH1_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH1    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH1_M  (H264_DMA_INFIFO_CNT_L2_CH1_V << H264_DMA_INFIFO_CNT_L2_CH1_S)
+#define H264_DMA_INFIFO_CNT_L2_CH1_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH1_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH1 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH1    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH1_M  (H264_DMA_INFIFO_FULL_L1_CH1_V << H264_DMA_INFIFO_FULL_L1_CH1_S)
+#define H264_DMA_INFIFO_FULL_L1_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH1_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH1    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH1_M  (H264_DMA_INFIFO_EMPTY_L1_CH1_V << H264_DMA_INFIFO_EMPTY_L1_CH1_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH1_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH1 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH1    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH1_M  (H264_DMA_INFIFO_CNT_L1_CH1_V << H264_DMA_INFIFO_CNT_L1_CH1_S)
+#define H264_DMA_INFIFO_CNT_L1_CH1_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH1_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH1 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH1    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH1_M  (H264_DMA_INFIFO_FULL_L3_CH1_V << H264_DMA_INFIFO_FULL_L3_CH1_S)
+#define H264_DMA_INFIFO_FULL_L3_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH1_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH1    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH1_M  (H264_DMA_INFIFO_EMPTY_L3_CH1_V << H264_DMA_INFIFO_EMPTY_L3_CH1_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH1_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH1    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH1_M  (H264_DMA_INFIFO_CNT_L3_CH1_V << H264_DMA_INFIFO_CNT_L3_CH1_S)
+#define H264_DMA_INFIFO_CNT_L3_CH1_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH1_S  18
+
+/** H264_DMA_IN_POP_CH1_REG register
+ *  RX CH1 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH1_REG (DR_REG_H264_DMA_BASE + 0x618)
+/** H264_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH1    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH1_M  (H264_DMA_INFIFO_RDATA_CH1_V << H264_DMA_INFIFO_RDATA_CH1_S)
+#define H264_DMA_INFIFO_RDATA_CH1_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH1_S  0
+/** H264_DMA_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH1    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH1_M  (H264_DMA_INFIFO_POP_CH1_V << H264_DMA_INFIFO_POP_CH1_S)
+#define H264_DMA_INFIFO_POP_CH1_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH1_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH1_REG register
+ *  RX CH1 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH1_REG (DR_REG_H264_DMA_BASE + 0x61c)
+/** H264_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH1    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH1_M  (H264_DMA_INLINK_AUTO_RET_CH1_V << H264_DMA_INLINK_AUTO_RET_CH1_S)
+#define H264_DMA_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH1_S  20
+/** H264_DMA_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH1    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH1_M  (H264_DMA_INLINK_STOP_CH1_V << H264_DMA_INLINK_STOP_CH1_S)
+#define H264_DMA_INLINK_STOP_CH1_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH1_S  21
+/** H264_DMA_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH1    (BIT(22))
+#define H264_DMA_INLINK_START_CH1_M  (H264_DMA_INLINK_START_CH1_V << H264_DMA_INLINK_START_CH1_S)
+#define H264_DMA_INLINK_START_CH1_V  0x00000001U
+#define H264_DMA_INLINK_START_CH1_S  22
+/** H264_DMA_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH1    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH1_M  (H264_DMA_INLINK_RESTART_CH1_V << H264_DMA_INLINK_RESTART_CH1_S)
+#define H264_DMA_INLINK_RESTART_CH1_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH1_S  23
+/** H264_DMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH1    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH1_M  (H264_DMA_INLINK_PARK_CH1_V << H264_DMA_INLINK_PARK_CH1_S)
+#define H264_DMA_INLINK_PARK_CH1_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH1_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH1_REG register
+ *  RX CH1 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x620)
+/** H264_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH1_M  (H264_DMA_INLINK_ADDR_CH1_V << H264_DMA_INLINK_ADDR_CH1_S)
+#define H264_DMA_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH1_S  0
+
+/** H264_DMA_IN_STATE_CH1_REG register
+ *  RX CH1 state register
+ */
+#define H264_DMA_IN_STATE_CH1_REG (DR_REG_H264_DMA_BASE + 0x624)
+/** H264_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH1_M  (H264_DMA_INLINK_DSCR_ADDR_CH1_V << H264_DMA_INLINK_DSCR_ADDR_CH1_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH1_S  0
+/** H264_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH1    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH1_M  (H264_DMA_IN_DSCR_STATE_CH1_V << H264_DMA_IN_DSCR_STATE_CH1_S)
+#define H264_DMA_IN_DSCR_STATE_CH1_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH1_S  18
+/** H264_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH1    0x00000007U
+#define H264_DMA_IN_STATE_CH1_M  (H264_DMA_IN_STATE_CH1_V << H264_DMA_IN_STATE_CH1_S)
+#define H264_DMA_IN_STATE_CH1_V  0x00000007U
+#define H264_DMA_IN_STATE_CH1_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH1    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH1_M  (H264_DMA_IN_RESET_AVAIL_CH1_V << H264_DMA_IN_RESET_AVAIL_CH1_S)
+#define H264_DMA_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH1_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  RX CH1 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x628)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  RX CH1 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x62c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** H264_DMA_IN_DSCR_CH1_REG register
+ *  RX CH1 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH1_REG (DR_REG_H264_DMA_BASE + 0x630)
+/** H264_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH1_M  (H264_DMA_INLINK_DSCR_CH1_V << H264_DMA_INLINK_DSCR_CH1_S)
+#define H264_DMA_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH1_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH1_REG register
+ *  RX CH1 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_H264_DMA_BASE + 0x634)
+/** H264_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH1_M  (H264_DMA_INLINK_DSCR_BF0_CH1_V << H264_DMA_INLINK_DSCR_BF0_CH1_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH1_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH1_REG register
+ *  RX CH1 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_H264_DMA_BASE + 0x638)
+/** H264_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH1_M  (H264_DMA_INLINK_DSCR_BF1_CH1_V << H264_DMA_INLINK_DSCR_BF1_CH1_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH1_S  0
+
+/** H264_DMA_IN_ARB_CH1_REG register
+ *  RX CH1 arb register
+ */
+#define H264_DMA_IN_ARB_CH1_REG (DR_REG_H264_DMA_BASE + 0x640)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH1_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH1_V << H264_DMA_IN_ARB_TOKEN_NUM_CH1_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH1_S  0
+/** H264_DMA_EXTER_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH1    0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_M  (H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_V << H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_S)
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_V  0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH1_S  4
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH1    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH1_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH1_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH1_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH1_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH1_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH1_REG register
+ *  RX CH1 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH1_REG (DR_REG_H264_DMA_BASE + 0x648)
+/** H264_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH1    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH1_M  (H264_DMA_IN_ETM_EN_CH1_V << H264_DMA_IN_ETM_EN_CH1_S)
+#define H264_DMA_IN_ETM_EN_CH1_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH1_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH1    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH1_M  (H264_DMA_IN_ETM_LOOP_EN_CH1_V << H264_DMA_IN_ETM_LOOP_EN_CH1_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH1_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH1_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH1    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH1_M  (H264_DMA_IN_DSCR_TASK_MAK_CH1_V << H264_DMA_IN_DSCR_TASK_MAK_CH1_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH1_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH1_REG register
+ *  rx CH1 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH1_REG (DR_REG_H264_DMA_BASE + 0x680)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH1_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH1_REG register
+ *  rx CH1 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH1_REG (DR_REG_H264_DMA_BASE + 0x684)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH1_S  0
+
+/** H264_DMA_IN_XADDR_CH1_REG register
+ *  rx CH1 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH1_REG (DR_REG_H264_DMA_BASE + 0x688)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH1    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH1_M  (H264_DMA_IN_CMDFIFO_XADDR_CH1_V << H264_DMA_IN_CMDFIFO_XADDR_CH1_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH1_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH1_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH1_REG register
+ *  rx CH1 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH1_REG (DR_REG_H264_DMA_BASE + 0x68c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH1_S  0
+
+/** H264_DMA_IN_CONF0_CH2_REG register
+ *  RX CH2 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH2_REG (DR_REG_H264_DMA_BASE + 0x700)
+/** H264_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH2    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH2_M  (H264_DMA_INDSCR_BURST_EN_CH2_V << H264_DMA_INDSCR_BURST_EN_CH2_S)
+#define H264_DMA_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH2_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH2    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH2_M  (H264_DMA_IN_ECC_AES_EN_CH2_V << H264_DMA_IN_ECC_AES_EN_CH2_S)
+#define H264_DMA_IN_ECC_AES_EN_CH2_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH2_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH2    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH2_M  (H264_DMA_IN_CHECK_OWNER_CH2_V << H264_DMA_IN_CHECK_OWNER_CH2_S)
+#define H264_DMA_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH2_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH2    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH2_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH2_V << H264_DMA_IN_MEM_BURST_LENGTH_CH2_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH2_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH2    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH2_M  (H264_DMA_IN_PAGE_BOUND_EN_CH2_V << H264_DMA_IN_PAGE_BOUND_EN_CH2_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH2_S  12
+/** H264_DMA_IN_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH2    (BIT(24))
+#define H264_DMA_IN_RST_CH2_M  (H264_DMA_IN_RST_CH2_V << H264_DMA_IN_RST_CH2_S)
+#define H264_DMA_IN_RST_CH2_V  0x00000001U
+#define H264_DMA_IN_RST_CH2_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH2    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH2_M  (H264_DMA_IN_CMD_DISABLE_CH2_V << H264_DMA_IN_CMD_DISABLE_CH2_S)
+#define H264_DMA_IN_CMD_DISABLE_CH2_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH2_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** H264_DMA_IN_INT_RAW_CH2_REG register
+ *  RX CH2  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH2_REG (DR_REG_H264_DMA_BASE + 0x704)
+/** H264_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH2_INT_RAW_M  (H264_DMA_IN_DONE_CH2_INT_RAW_V << H264_DMA_IN_DONE_CH2_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH2_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH2_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH2_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH2_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH2_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH2_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH2_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 1.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH2_REG register
+ *  RX CH2  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH2_REG (DR_REG_H264_DMA_BASE + 0x708)
+/** H264_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH2_INT_ENA_M  (H264_DMA_IN_DONE_CH2_INT_ENA_V << H264_DMA_IN_DONE_CH2_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH2_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH2_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH2_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH2_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH2_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH2_REG register
+ *  RX CH2  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH2_REG (DR_REG_H264_DMA_BASE + 0x70c)
+/** H264_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH2_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH2_INT_ST_M  (H264_DMA_IN_DONE_CH2_INT_ST_V << H264_DMA_IN_DONE_CH2_INT_ST_S)
+#define H264_DMA_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH2_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH2_INT_ST_V << H264_DMA_IN_SUC_EOF_CH2_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH2_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH2_INT_ST_V << H264_DMA_IN_ERR_EOF_CH2_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH2_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH2_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH2_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH2_REG register
+ *  RX CH2  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH2_REG (DR_REG_H264_DMA_BASE + 0x710)
+/** H264_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH2_INT_CLR_M  (H264_DMA_IN_DONE_CH2_INT_CLR_V << H264_DMA_IN_DONE_CH2_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH2_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH2_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH2_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH2_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH2_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH2_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH2_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH2_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH2_REG register
+ *  RX CH2 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH2_REG (DR_REG_H264_DMA_BASE + 0x714)
+/** H264_DMA_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH2    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH2_M  (H264_DMA_INFIFO_FULL_L2_CH2_V << H264_DMA_INFIFO_FULL_L2_CH2_S)
+#define H264_DMA_INFIFO_FULL_L2_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH2_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH2    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH2_M  (H264_DMA_INFIFO_EMPTY_L2_CH2_V << H264_DMA_INFIFO_EMPTY_L2_CH2_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH2_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH2    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH2_M  (H264_DMA_INFIFO_CNT_L2_CH2_V << H264_DMA_INFIFO_CNT_L2_CH2_S)
+#define H264_DMA_INFIFO_CNT_L2_CH2_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH2_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH2 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH2    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH2_M  (H264_DMA_INFIFO_FULL_L1_CH2_V << H264_DMA_INFIFO_FULL_L1_CH2_S)
+#define H264_DMA_INFIFO_FULL_L1_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH2_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH2    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH2_M  (H264_DMA_INFIFO_EMPTY_L1_CH2_V << H264_DMA_INFIFO_EMPTY_L1_CH2_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH2_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH2 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH2    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH2_M  (H264_DMA_INFIFO_CNT_L1_CH2_V << H264_DMA_INFIFO_CNT_L1_CH2_S)
+#define H264_DMA_INFIFO_CNT_L1_CH2_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH2_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH2 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH2    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH2_M  (H264_DMA_INFIFO_FULL_L3_CH2_V << H264_DMA_INFIFO_FULL_L3_CH2_S)
+#define H264_DMA_INFIFO_FULL_L3_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH2_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH2    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH2_M  (H264_DMA_INFIFO_EMPTY_L3_CH2_V << H264_DMA_INFIFO_EMPTY_L3_CH2_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH2_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH2    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH2_M  (H264_DMA_INFIFO_CNT_L3_CH2_V << H264_DMA_INFIFO_CNT_L3_CH2_S)
+#define H264_DMA_INFIFO_CNT_L3_CH2_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH2_S  18
+
+/** H264_DMA_IN_POP_CH2_REG register
+ *  RX CH2 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH2_REG (DR_REG_H264_DMA_BASE + 0x718)
+/** H264_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH2    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH2_M  (H264_DMA_INFIFO_RDATA_CH2_V << H264_DMA_INFIFO_RDATA_CH2_S)
+#define H264_DMA_INFIFO_RDATA_CH2_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH2_S  0
+/** H264_DMA_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH2    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH2_M  (H264_DMA_INFIFO_POP_CH2_V << H264_DMA_INFIFO_POP_CH2_S)
+#define H264_DMA_INFIFO_POP_CH2_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH2_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH2_REG register
+ *  RX CH2 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH2_REG (DR_REG_H264_DMA_BASE + 0x71c)
+/** H264_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH2    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH2_M  (H264_DMA_INLINK_AUTO_RET_CH2_V << H264_DMA_INLINK_AUTO_RET_CH2_S)
+#define H264_DMA_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH2_S  20
+/** H264_DMA_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH2    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH2_M  (H264_DMA_INLINK_STOP_CH2_V << H264_DMA_INLINK_STOP_CH2_S)
+#define H264_DMA_INLINK_STOP_CH2_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH2_S  21
+/** H264_DMA_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH2    (BIT(22))
+#define H264_DMA_INLINK_START_CH2_M  (H264_DMA_INLINK_START_CH2_V << H264_DMA_INLINK_START_CH2_S)
+#define H264_DMA_INLINK_START_CH2_V  0x00000001U
+#define H264_DMA_INLINK_START_CH2_S  22
+/** H264_DMA_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH2    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH2_M  (H264_DMA_INLINK_RESTART_CH2_V << H264_DMA_INLINK_RESTART_CH2_S)
+#define H264_DMA_INLINK_RESTART_CH2_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH2_S  23
+/** H264_DMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH2    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH2_M  (H264_DMA_INLINK_PARK_CH2_V << H264_DMA_INLINK_PARK_CH2_S)
+#define H264_DMA_INLINK_PARK_CH2_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH2_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH2_REG register
+ *  RX CH2 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x720)
+/** H264_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH2_M  (H264_DMA_INLINK_ADDR_CH2_V << H264_DMA_INLINK_ADDR_CH2_S)
+#define H264_DMA_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH2_S  0
+
+/** H264_DMA_IN_STATE_CH2_REG register
+ *  RX CH2 state register
+ */
+#define H264_DMA_IN_STATE_CH2_REG (DR_REG_H264_DMA_BASE + 0x724)
+/** H264_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH2_M  (H264_DMA_INLINK_DSCR_ADDR_CH2_V << H264_DMA_INLINK_DSCR_ADDR_CH2_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH2_S  0
+/** H264_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH2    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH2_M  (H264_DMA_IN_DSCR_STATE_CH2_V << H264_DMA_IN_DSCR_STATE_CH2_S)
+#define H264_DMA_IN_DSCR_STATE_CH2_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH2_S  18
+/** H264_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH2    0x00000007U
+#define H264_DMA_IN_STATE_CH2_M  (H264_DMA_IN_STATE_CH2_V << H264_DMA_IN_STATE_CH2_S)
+#define H264_DMA_IN_STATE_CH2_V  0x00000007U
+#define H264_DMA_IN_STATE_CH2_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH2    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH2_M  (H264_DMA_IN_RESET_AVAIL_CH2_V << H264_DMA_IN_RESET_AVAIL_CH2_S)
+#define H264_DMA_IN_RESET_AVAIL_CH2_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH2_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  RX CH2 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x728)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  RX CH2 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x72c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** H264_DMA_IN_DSCR_CH2_REG register
+ *  RX CH2 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH2_REG (DR_REG_H264_DMA_BASE + 0x730)
+/** H264_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH2_M  (H264_DMA_INLINK_DSCR_CH2_V << H264_DMA_INLINK_DSCR_CH2_S)
+#define H264_DMA_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH2_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH2_REG register
+ *  RX CH2 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_H264_DMA_BASE + 0x734)
+/** H264_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH2_M  (H264_DMA_INLINK_DSCR_BF0_CH2_V << H264_DMA_INLINK_DSCR_BF0_CH2_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH2_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH2_REG register
+ *  RX CH2 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_H264_DMA_BASE + 0x738)
+/** H264_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH2_M  (H264_DMA_INLINK_DSCR_BF1_CH2_V << H264_DMA_INLINK_DSCR_BF1_CH2_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH2_S  0
+
+/** H264_DMA_IN_ARB_CH2_REG register
+ *  RX CH2 arb register
+ */
+#define H264_DMA_IN_ARB_CH2_REG (DR_REG_H264_DMA_BASE + 0x740)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH2_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH2_V << H264_DMA_IN_ARB_TOKEN_NUM_CH2_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH2_S  0
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH2    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH2_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH2_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH2_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH2_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH2_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH2_REG register
+ *  RX CH2 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH2_REG (DR_REG_H264_DMA_BASE + 0x748)
+/** H264_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH2    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH2_M  (H264_DMA_IN_ETM_EN_CH2_V << H264_DMA_IN_ETM_EN_CH2_S)
+#define H264_DMA_IN_ETM_EN_CH2_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH2_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH2    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH2_M  (H264_DMA_IN_ETM_LOOP_EN_CH2_V << H264_DMA_IN_ETM_LOOP_EN_CH2_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH2_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH2_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH2    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH2_M  (H264_DMA_IN_DSCR_TASK_MAK_CH2_V << H264_DMA_IN_DSCR_TASK_MAK_CH2_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH2_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH2_REG register
+ *  rx CH2 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH2_REG (DR_REG_H264_DMA_BASE + 0x780)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH2_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH2_REG register
+ *  rx CH2 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH2_REG (DR_REG_H264_DMA_BASE + 0x784)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH2_S  0
+
+/** H264_DMA_IN_XADDR_CH2_REG register
+ *  rx CH2 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH2_REG (DR_REG_H264_DMA_BASE + 0x788)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH2    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH2_M  (H264_DMA_IN_CMDFIFO_XADDR_CH2_V << H264_DMA_IN_CMDFIFO_XADDR_CH2_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH2_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH2_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH2_REG register
+ *  rx CH2 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH2_REG (DR_REG_H264_DMA_BASE + 0x78c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH2_S  0
+
+/** H264_DMA_IN_CONF0_CH3_REG register
+ *  RX CH3 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH3_REG (DR_REG_H264_DMA_BASE + 0x800)
+/** H264_DMA_INDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH3    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH3_M  (H264_DMA_INDSCR_BURST_EN_CH3_V << H264_DMA_INDSCR_BURST_EN_CH3_S)
+#define H264_DMA_INDSCR_BURST_EN_CH3_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH3_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH3    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH3_M  (H264_DMA_IN_ECC_AES_EN_CH3_V << H264_DMA_IN_ECC_AES_EN_CH3_S)
+#define H264_DMA_IN_ECC_AES_EN_CH3_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH3_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH3    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH3_M  (H264_DMA_IN_CHECK_OWNER_CH3_V << H264_DMA_IN_CHECK_OWNER_CH3_S)
+#define H264_DMA_IN_CHECK_OWNER_CH3_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH3_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH3    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH3_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH3_V << H264_DMA_IN_MEM_BURST_LENGTH_CH3_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH3_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH3_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH3    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH3_M  (H264_DMA_IN_PAGE_BOUND_EN_CH3_V << H264_DMA_IN_PAGE_BOUND_EN_CH3_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH3_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH3_S  12
+/** H264_DMA_IN_RST_CH3 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH3    (BIT(24))
+#define H264_DMA_IN_RST_CH3_M  (H264_DMA_IN_RST_CH3_V << H264_DMA_IN_RST_CH3_S)
+#define H264_DMA_IN_RST_CH3_V  0x00000001U
+#define H264_DMA_IN_RST_CH3_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH3    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH3_M  (H264_DMA_IN_CMD_DISABLE_CH3_V << H264_DMA_IN_CMD_DISABLE_CH3_S)
+#define H264_DMA_IN_CMD_DISABLE_CH3_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH3_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH3_S  26
+
+/** H264_DMA_IN_INT_RAW_CH3_REG register
+ *  RX CH3  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH3_REG (DR_REG_H264_DMA_BASE + 0x804)
+/** H264_DMA_IN_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH3_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH3_INT_RAW_M  (H264_DMA_IN_DONE_CH3_INT_RAW_V << H264_DMA_IN_DONE_CH3_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH3_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH3_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH3_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH3_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH3_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH3_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH3_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH3_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH3_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH3_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH3_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 1.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH3_REG register
+ *  RX CH3  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH3_REG (DR_REG_H264_DMA_BASE + 0x808)
+/** H264_DMA_IN_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH3_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH3_INT_ENA_M  (H264_DMA_IN_DONE_CH3_INT_ENA_V << H264_DMA_IN_DONE_CH3_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH3_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH3_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH3_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH3_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH3_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH3_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH3_REG register
+ *  RX CH3  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH3_REG (DR_REG_H264_DMA_BASE + 0x80c)
+/** H264_DMA_IN_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH3_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH3_INT_ST_M  (H264_DMA_IN_DONE_CH3_INT_ST_V << H264_DMA_IN_DONE_CH3_INT_ST_S)
+#define H264_DMA_IN_DONE_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH3_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH3_INT_ST_V << H264_DMA_IN_SUC_EOF_CH3_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH3_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH3_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH3_INT_ST_V << H264_DMA_IN_ERR_EOF_CH3_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH3_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH3_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH3_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH3_REG register
+ *  RX CH3  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH3_REG (DR_REG_H264_DMA_BASE + 0x810)
+/** H264_DMA_IN_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH3_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH3_INT_CLR_M  (H264_DMA_IN_DONE_CH3_INT_CLR_V << H264_DMA_IN_DONE_CH3_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH3_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH3_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH3_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH3_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH3_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH3_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH3_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH3_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH3_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH3_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH3_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH3_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH3_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH3_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH3_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH3_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH3_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH3_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH3_REG register
+ *  RX CH3 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH3_REG (DR_REG_H264_DMA_BASE + 0x814)
+/** H264_DMA_INFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH3    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH3_M  (H264_DMA_INFIFO_FULL_L2_CH3_V << H264_DMA_INFIFO_FULL_L2_CH3_S)
+#define H264_DMA_INFIFO_FULL_L2_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH3_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH3    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH3_M  (H264_DMA_INFIFO_EMPTY_L2_CH3_V << H264_DMA_INFIFO_EMPTY_L2_CH3_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH3_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH3    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH3_M  (H264_DMA_INFIFO_CNT_L2_CH3_V << H264_DMA_INFIFO_CNT_L2_CH3_S)
+#define H264_DMA_INFIFO_CNT_L2_CH3_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH3_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH3 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH3    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH3_M  (H264_DMA_INFIFO_FULL_L1_CH3_V << H264_DMA_INFIFO_FULL_L1_CH3_S)
+#define H264_DMA_INFIFO_FULL_L1_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH3_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH3 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH3    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH3_M  (H264_DMA_INFIFO_EMPTY_L1_CH3_V << H264_DMA_INFIFO_EMPTY_L1_CH3_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH3_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH3 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH3    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH3_M  (H264_DMA_INFIFO_CNT_L1_CH3_V << H264_DMA_INFIFO_CNT_L1_CH3_S)
+#define H264_DMA_INFIFO_CNT_L1_CH3_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH3_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH3 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH3    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH3_M  (H264_DMA_INFIFO_FULL_L3_CH3_V << H264_DMA_INFIFO_FULL_L3_CH3_S)
+#define H264_DMA_INFIFO_FULL_L3_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH3_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH3 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH3    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH3_M  (H264_DMA_INFIFO_EMPTY_L3_CH3_V << H264_DMA_INFIFO_EMPTY_L3_CH3_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH3_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH3    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH3_M  (H264_DMA_INFIFO_CNT_L3_CH3_V << H264_DMA_INFIFO_CNT_L3_CH3_S)
+#define H264_DMA_INFIFO_CNT_L3_CH3_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH3_S  18
+
+/** H264_DMA_IN_POP_CH3_REG register
+ *  RX CH3 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH3_REG (DR_REG_H264_DMA_BASE + 0x818)
+/** H264_DMA_INFIFO_RDATA_CH3 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH3    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH3_M  (H264_DMA_INFIFO_RDATA_CH3_V << H264_DMA_INFIFO_RDATA_CH3_S)
+#define H264_DMA_INFIFO_RDATA_CH3_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH3_S  0
+/** H264_DMA_INFIFO_POP_CH3 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH3    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH3_M  (H264_DMA_INFIFO_POP_CH3_V << H264_DMA_INFIFO_POP_CH3_S)
+#define H264_DMA_INFIFO_POP_CH3_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH3_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH3_REG register
+ *  RX CH3 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH3_REG (DR_REG_H264_DMA_BASE + 0x81c)
+/** H264_DMA_INLINK_AUTO_RET_CH3 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH3    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH3_M  (H264_DMA_INLINK_AUTO_RET_CH3_V << H264_DMA_INLINK_AUTO_RET_CH3_S)
+#define H264_DMA_INLINK_AUTO_RET_CH3_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH3_S  20
+/** H264_DMA_INLINK_STOP_CH3 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH3    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH3_M  (H264_DMA_INLINK_STOP_CH3_V << H264_DMA_INLINK_STOP_CH3_S)
+#define H264_DMA_INLINK_STOP_CH3_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH3_S  21
+/** H264_DMA_INLINK_START_CH3 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH3    (BIT(22))
+#define H264_DMA_INLINK_START_CH3_M  (H264_DMA_INLINK_START_CH3_V << H264_DMA_INLINK_START_CH3_S)
+#define H264_DMA_INLINK_START_CH3_V  0x00000001U
+#define H264_DMA_INLINK_START_CH3_S  22
+/** H264_DMA_INLINK_RESTART_CH3 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH3    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH3_M  (H264_DMA_INLINK_RESTART_CH3_V << H264_DMA_INLINK_RESTART_CH3_S)
+#define H264_DMA_INLINK_RESTART_CH3_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH3_S  23
+/** H264_DMA_INLINK_PARK_CH3 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH3    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH3_M  (H264_DMA_INLINK_PARK_CH3_V << H264_DMA_INLINK_PARK_CH3_S)
+#define H264_DMA_INLINK_PARK_CH3_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH3_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH3_REG register
+ *  RX CH3 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x820)
+/** H264_DMA_INLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH3_M  (H264_DMA_INLINK_ADDR_CH3_V << H264_DMA_INLINK_ADDR_CH3_S)
+#define H264_DMA_INLINK_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH3_S  0
+
+/** H264_DMA_IN_STATE_CH3_REG register
+ *  RX CH3 state register
+ */
+#define H264_DMA_IN_STATE_CH3_REG (DR_REG_H264_DMA_BASE + 0x824)
+/** H264_DMA_INLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH3    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH3_M  (H264_DMA_INLINK_DSCR_ADDR_CH3_V << H264_DMA_INLINK_DSCR_ADDR_CH3_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH3_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH3_S  0
+/** H264_DMA_IN_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH3    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH3_M  (H264_DMA_IN_DSCR_STATE_CH3_V << H264_DMA_IN_DSCR_STATE_CH3_S)
+#define H264_DMA_IN_DSCR_STATE_CH3_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH3_S  18
+/** H264_DMA_IN_STATE_CH3 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH3    0x00000007U
+#define H264_DMA_IN_STATE_CH3_M  (H264_DMA_IN_STATE_CH3_V << H264_DMA_IN_STATE_CH3_S)
+#define H264_DMA_IN_STATE_CH3_V  0x00000007U
+#define H264_DMA_IN_STATE_CH3_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH3 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH3    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH3_M  (H264_DMA_IN_RESET_AVAIL_CH3_V << H264_DMA_IN_RESET_AVAIL_CH3_S)
+#define H264_DMA_IN_RESET_AVAIL_CH3_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH3_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_REG register
+ *  RX CH3 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x828)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH3_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_REG register
+ *  RX CH3 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x82c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH3_S  0
+
+/** H264_DMA_IN_DSCR_CH3_REG register
+ *  RX CH3 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH3_REG (DR_REG_H264_DMA_BASE + 0x830)
+/** H264_DMA_INLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH3    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH3_M  (H264_DMA_INLINK_DSCR_CH3_V << H264_DMA_INLINK_DSCR_CH3_S)
+#define H264_DMA_INLINK_DSCR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH3_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH3_REG register
+ *  RX CH3 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH3_REG (DR_REG_H264_DMA_BASE + 0x834)
+/** H264_DMA_INLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH3    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH3_M  (H264_DMA_INLINK_DSCR_BF0_CH3_V << H264_DMA_INLINK_DSCR_BF0_CH3_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH3_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH3_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH3_REG register
+ *  RX CH3 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH3_REG (DR_REG_H264_DMA_BASE + 0x838)
+/** H264_DMA_INLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH3    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH3_M  (H264_DMA_INLINK_DSCR_BF1_CH3_V << H264_DMA_INLINK_DSCR_BF1_CH3_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH3_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH3_S  0
+
+/** H264_DMA_IN_ARB_CH3_REG register
+ *  RX CH3 arb register
+ */
+#define H264_DMA_IN_ARB_CH3_REG (DR_REG_H264_DMA_BASE + 0x840)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH3    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH3_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH3_V << H264_DMA_IN_ARB_TOKEN_NUM_CH3_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH3_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH3_S  0
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH3 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH3    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH3_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH3_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH3_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH3_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH3_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH3_REG register
+ *  RX CH3 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH3_REG (DR_REG_H264_DMA_BASE + 0x848)
+/** H264_DMA_IN_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH3    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH3_M  (H264_DMA_IN_ETM_EN_CH3_V << H264_DMA_IN_ETM_EN_CH3_S)
+#define H264_DMA_IN_ETM_EN_CH3_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH3_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH3    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH3_M  (H264_DMA_IN_ETM_LOOP_EN_CH3_V << H264_DMA_IN_ETM_LOOP_EN_CH3_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH3_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH3_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH3    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH3_M  (H264_DMA_IN_DSCR_TASK_MAK_CH3_V << H264_DMA_IN_DSCR_TASK_MAK_CH3_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH3_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH3_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH3_REG register
+ *  rx CH3 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH3_REG (DR_REG_H264_DMA_BASE + 0x880)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH3_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH3_REG register
+ *  rx CH3 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH3_REG (DR_REG_H264_DMA_BASE + 0x884)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH3_S  0
+
+/** H264_DMA_IN_XADDR_CH3_REG register
+ *  rx CH3 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH3_REG (DR_REG_H264_DMA_BASE + 0x888)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH3    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH3_M  (H264_DMA_IN_CMDFIFO_XADDR_CH3_V << H264_DMA_IN_CMDFIFO_XADDR_CH3_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH3_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH3_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH3_REG register
+ *  rx CH3 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH3_REG (DR_REG_H264_DMA_BASE + 0x88c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH3_S  0
+
+/** H264_DMA_IN_CONF0_CH4_REG register
+ *  RX CH4 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH4_REG (DR_REG_H264_DMA_BASE + 0x900)
+/** H264_DMA_INDSCR_BURST_EN_CH4 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define H264_DMA_INDSCR_BURST_EN_CH4    (BIT(2))
+#define H264_DMA_INDSCR_BURST_EN_CH4_M  (H264_DMA_INDSCR_BURST_EN_CH4_V << H264_DMA_INDSCR_BURST_EN_CH4_S)
+#define H264_DMA_INDSCR_BURST_EN_CH4_V  0x00000001U
+#define H264_DMA_INDSCR_BURST_EN_CH4_S  2
+/** H264_DMA_IN_ECC_AES_EN_CH4 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH4    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH4_M  (H264_DMA_IN_ECC_AES_EN_CH4_V << H264_DMA_IN_ECC_AES_EN_CH4_S)
+#define H264_DMA_IN_ECC_AES_EN_CH4_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH4_S  3
+/** H264_DMA_IN_CHECK_OWNER_CH4 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define H264_DMA_IN_CHECK_OWNER_CH4    (BIT(4))
+#define H264_DMA_IN_CHECK_OWNER_CH4_M  (H264_DMA_IN_CHECK_OWNER_CH4_V << H264_DMA_IN_CHECK_OWNER_CH4_S)
+#define H264_DMA_IN_CHECK_OWNER_CH4_V  0x00000001U
+#define H264_DMA_IN_CHECK_OWNER_CH4_S  4
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH4 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH4    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH4_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH4_V << H264_DMA_IN_MEM_BURST_LENGTH_CH4_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH4_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH4_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH4 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH4    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH4_M  (H264_DMA_IN_PAGE_BOUND_EN_CH4_V << H264_DMA_IN_PAGE_BOUND_EN_CH4_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH4_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH4_S  12
+/** H264_DMA_IN_RST_CH4 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH4    (BIT(24))
+#define H264_DMA_IN_RST_CH4_M  (H264_DMA_IN_RST_CH4_V << H264_DMA_IN_RST_CH4_S)
+#define H264_DMA_IN_RST_CH4_V  0x00000001U
+#define H264_DMA_IN_RST_CH4_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH4 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH4    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH4_M  (H264_DMA_IN_CMD_DISABLE_CH4_V << H264_DMA_IN_CMD_DISABLE_CH4_S)
+#define H264_DMA_IN_CMD_DISABLE_CH4_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH4_S  25
+/** H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4    (BIT(26))
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_M  (H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_V << H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_S)
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_V  0x00000001U
+#define H264_DMA_IN_ARB_WEIGHT_OPT_DIS_CH4_S  26
+
+/** H264_DMA_IN_INT_RAW_CH4_REG register
+ *  RX CH4  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH4_REG (DR_REG_H264_DMA_BASE + 0x904)
+/** H264_DMA_IN_DONE_CH4_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH4_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH4_INT_RAW_M  (H264_DMA_IN_DONE_CH4_INT_RAW_V << H264_DMA_IN_DONE_CH4_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH4_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH4_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH4_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH4_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH4_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH4_INT_RAW_S  1
+/** H264_DMA_IN_ERR_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define H264_DMA_IN_ERR_EOF_CH4_INT_RAW    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH4_INT_RAW_M  (H264_DMA_IN_ERR_EOF_CH4_INT_RAW_V << H264_DMA_IN_ERR_EOF_CH4_INT_RAW_S)
+#define H264_DMA_IN_ERR_EOF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH4_INT_RAW_S  2
+/** H264_DMA_IN_DSCR_ERR_CH4_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 1.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_RAW    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_M  (H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_V << H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_S)
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_RAW_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_RAW_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_RAW_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_M  (H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_V << H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_RAW_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_M  (H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_V << H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_RAW_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_M  (H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_V << H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_M  (H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_V << H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_RAW_S  9
+
+/** H264_DMA_IN_INT_ENA_CH4_REG register
+ *  RX CH4  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH4_REG (DR_REG_H264_DMA_BASE + 0x908)
+/** H264_DMA_IN_DONE_CH4_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH4_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH4_INT_ENA_M  (H264_DMA_IN_DONE_CH4_INT_ENA_V << H264_DMA_IN_DONE_CH4_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH4_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH4_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH4_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH4_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ENA_S  1
+/** H264_DMA_IN_ERR_EOF_CH4_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ENA    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ENA_M  (H264_DMA_IN_ERR_EOF_CH4_INT_ENA_V << H264_DMA_IN_ERR_EOF_CH4_INT_ENA_S)
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ENA_S  2
+/** H264_DMA_IN_DSCR_ERR_CH4_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ENA    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_M  (H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_V << H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_S)
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ENA_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ENA_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ENA_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_M  (H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_V << H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ENA_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_M  (H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_V << H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ENA_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_M  (H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_V << H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_M  (H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_V << H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ENA_S  9
+
+/** H264_DMA_IN_INT_ST_CH4_REG register
+ *  RX CH4  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH4_REG (DR_REG_H264_DMA_BASE + 0x90c)
+/** H264_DMA_IN_DONE_CH4_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH4_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH4_INT_ST_M  (H264_DMA_IN_DONE_CH4_INT_ST_V << H264_DMA_IN_DONE_CH4_INT_ST_S)
+#define H264_DMA_IN_DONE_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH4_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH4_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH4_INT_ST_V << H264_DMA_IN_SUC_EOF_CH4_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH4_INT_ST_S  1
+/** H264_DMA_IN_ERR_EOF_CH4_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ST    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ST_M  (H264_DMA_IN_ERR_EOF_CH4_INT_ST_V << H264_DMA_IN_ERR_EOF_CH4_INT_ST_S)
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH4_INT_ST_S  2
+/** H264_DMA_IN_DSCR_ERR_CH4_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ST    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ST_M  (H264_DMA_IN_DSCR_ERR_CH4_INT_ST_V << H264_DMA_IN_DSCR_ERR_CH4_INT_ST_S)
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_ST_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ST    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_ST_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH4_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ST    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_ST_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH4_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ST    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_M  (H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_V << H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_ST_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH4_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ST    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_M  (H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_V << H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_ST_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_M  (H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_V << H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_ST_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_M  (H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_V << H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_ST_S  9
+
+/** H264_DMA_IN_INT_CLR_CH4_REG register
+ *  RX CH4  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH4_REG (DR_REG_H264_DMA_BASE + 0x910)
+/** H264_DMA_IN_DONE_CH4_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH4_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH4_INT_CLR_M  (H264_DMA_IN_DONE_CH4_INT_CLR_V << H264_DMA_IN_DONE_CH4_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH4_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH4_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH4_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH4_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH4_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH4_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH4_INT_CLR_S  1
+/** H264_DMA_IN_ERR_EOF_CH4_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_ERR_EOF_CH4_INT_CLR    (BIT(2))
+#define H264_DMA_IN_ERR_EOF_CH4_INT_CLR_M  (H264_DMA_IN_ERR_EOF_CH4_INT_CLR_V << H264_DMA_IN_ERR_EOF_CH4_INT_CLR_S)
+#define H264_DMA_IN_ERR_EOF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_ERR_EOF_CH4_INT_CLR_S  2
+/** H264_DMA_IN_DSCR_ERR_CH4_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_CLR    (BIT(3))
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_M  (H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_V << H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_S)
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_ERR_CH4_INT_CLR_S  3
+/** H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR    (BIT(4))
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH4_INT_CLR_S  4
+/** H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR    (BIT(5))
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH4_INT_CLR_S  5
+/** H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR    (BIT(6))
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_M  (H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_V << H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L2_CH4_INT_CLR_S  6
+/** H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR    (BIT(7))
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_M  (H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_V << H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L2_CH4_INT_CLR_S  7
+/** H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR    (BIT(8))
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_M  (H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_V << H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_S)
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_S  8
+/** H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR    (BIT(9))
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_M  (H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_V << H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_S)
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DSCR_TASK_OVF_CH4_INT_CLR_S  9
+
+/** H264_DMA_INFIFO_STATUS_CH4_REG register
+ *  RX CH4 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH4_REG (DR_REG_H264_DMA_BASE + 0x914)
+/** H264_DMA_INFIFO_FULL_L2_CH4 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_FULL_L2_CH4    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L2_CH4_M  (H264_DMA_INFIFO_FULL_L2_CH4_V << H264_DMA_INFIFO_FULL_L2_CH4_S)
+#define H264_DMA_INFIFO_FULL_L2_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L2_CH4_S  0
+/** H264_DMA_INFIFO_EMPTY_L2_CH4 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define H264_DMA_INFIFO_EMPTY_L2_CH4    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L2_CH4_M  (H264_DMA_INFIFO_EMPTY_L2_CH4_V << H264_DMA_INFIFO_EMPTY_L2_CH4_S)
+#define H264_DMA_INFIFO_EMPTY_L2_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L2_CH4_S  1
+/** H264_DMA_INFIFO_CNT_L2_CH4 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define H264_DMA_INFIFO_CNT_L2_CH4    0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH4_M  (H264_DMA_INFIFO_CNT_L2_CH4_V << H264_DMA_INFIFO_CNT_L2_CH4_S)
+#define H264_DMA_INFIFO_CNT_L2_CH4_V  0x0000000FU
+#define H264_DMA_INFIFO_CNT_L2_CH4_S  2
+/** H264_DMA_INFIFO_FULL_L1_CH4 : RO; bitpos: [6]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH4    (BIT(6))
+#define H264_DMA_INFIFO_FULL_L1_CH4_M  (H264_DMA_INFIFO_FULL_L1_CH4_V << H264_DMA_INFIFO_FULL_L1_CH4_S)
+#define H264_DMA_INFIFO_FULL_L1_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH4_S  6
+/** H264_DMA_INFIFO_EMPTY_L1_CH4 : RO; bitpos: [7]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH4    (BIT(7))
+#define H264_DMA_INFIFO_EMPTY_L1_CH4_M  (H264_DMA_INFIFO_EMPTY_L1_CH4_V << H264_DMA_INFIFO_EMPTY_L1_CH4_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH4_S  7
+/** H264_DMA_INFIFO_CNT_L1_CH4 : RO; bitpos: [12:8]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH4    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH4_M  (H264_DMA_INFIFO_CNT_L1_CH4_V << H264_DMA_INFIFO_CNT_L1_CH4_S)
+#define H264_DMA_INFIFO_CNT_L1_CH4_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH4_S  8
+/** H264_DMA_INFIFO_FULL_L3_CH4 : RO; bitpos: [16]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L3_CH4    (BIT(16))
+#define H264_DMA_INFIFO_FULL_L3_CH4_M  (H264_DMA_INFIFO_FULL_L3_CH4_V << H264_DMA_INFIFO_FULL_L3_CH4_S)
+#define H264_DMA_INFIFO_FULL_L3_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L3_CH4_S  16
+/** H264_DMA_INFIFO_EMPTY_L3_CH4 : RO; bitpos: [17]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L3_CH4    (BIT(17))
+#define H264_DMA_INFIFO_EMPTY_L3_CH4_M  (H264_DMA_INFIFO_EMPTY_L3_CH4_V << H264_DMA_INFIFO_EMPTY_L3_CH4_S)
+#define H264_DMA_INFIFO_EMPTY_L3_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L3_CH4_S  17
+/** H264_DMA_INFIFO_CNT_L3_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L3_CH4    0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH4_M  (H264_DMA_INFIFO_CNT_L3_CH4_V << H264_DMA_INFIFO_CNT_L3_CH4_S)
+#define H264_DMA_INFIFO_CNT_L3_CH4_V  0x00000003U
+#define H264_DMA_INFIFO_CNT_L3_CH4_S  18
+
+/** H264_DMA_IN_POP_CH4_REG register
+ *  RX CH4 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH4_REG (DR_REG_H264_DMA_BASE + 0x918)
+/** H264_DMA_INFIFO_RDATA_CH4 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH4    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH4_M  (H264_DMA_INFIFO_RDATA_CH4_V << H264_DMA_INFIFO_RDATA_CH4_S)
+#define H264_DMA_INFIFO_RDATA_CH4_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH4_S  0
+/** H264_DMA_INFIFO_POP_CH4 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH4    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH4_M  (H264_DMA_INFIFO_POP_CH4_V << H264_DMA_INFIFO_POP_CH4_S)
+#define H264_DMA_INFIFO_POP_CH4_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH4_S  11
+
+/** H264_DMA_IN_LINK_CONF_CH4_REG register
+ *  RX CH4 in_link dscr ctrl register
+ */
+#define H264_DMA_IN_LINK_CONF_CH4_REG (DR_REG_H264_DMA_BASE + 0x91c)
+/** H264_DMA_INLINK_AUTO_RET_CH4 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_INLINK_AUTO_RET_CH4    (BIT(20))
+#define H264_DMA_INLINK_AUTO_RET_CH4_M  (H264_DMA_INLINK_AUTO_RET_CH4_V << H264_DMA_INLINK_AUTO_RET_CH4_S)
+#define H264_DMA_INLINK_AUTO_RET_CH4_V  0x00000001U
+#define H264_DMA_INLINK_AUTO_RET_CH4_S  20
+/** H264_DMA_INLINK_STOP_CH4 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_STOP_CH4    (BIT(21))
+#define H264_DMA_INLINK_STOP_CH4_M  (H264_DMA_INLINK_STOP_CH4_V << H264_DMA_INLINK_STOP_CH4_S)
+#define H264_DMA_INLINK_STOP_CH4_V  0x00000001U
+#define H264_DMA_INLINK_STOP_CH4_S  21
+/** H264_DMA_INLINK_START_CH4 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define H264_DMA_INLINK_START_CH4    (BIT(22))
+#define H264_DMA_INLINK_START_CH4_M  (H264_DMA_INLINK_START_CH4_V << H264_DMA_INLINK_START_CH4_S)
+#define H264_DMA_INLINK_START_CH4_V  0x00000001U
+#define H264_DMA_INLINK_START_CH4_S  22
+/** H264_DMA_INLINK_RESTART_CH4 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define H264_DMA_INLINK_RESTART_CH4    (BIT(23))
+#define H264_DMA_INLINK_RESTART_CH4_M  (H264_DMA_INLINK_RESTART_CH4_V << H264_DMA_INLINK_RESTART_CH4_S)
+#define H264_DMA_INLINK_RESTART_CH4_V  0x00000001U
+#define H264_DMA_INLINK_RESTART_CH4_S  23
+/** H264_DMA_INLINK_PARK_CH4 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define H264_DMA_INLINK_PARK_CH4    (BIT(24))
+#define H264_DMA_INLINK_PARK_CH4_M  (H264_DMA_INLINK_PARK_CH4_V << H264_DMA_INLINK_PARK_CH4_S)
+#define H264_DMA_INLINK_PARK_CH4_V  0x00000001U
+#define H264_DMA_INLINK_PARK_CH4_S  24
+
+/** H264_DMA_IN_LINK_ADDR_CH4_REG register
+ *  RX CH4 in_link dscr addr register
+ */
+#define H264_DMA_IN_LINK_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x920)
+/** H264_DMA_INLINK_ADDR_CH4 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH4_M  (H264_DMA_INLINK_ADDR_CH4_V << H264_DMA_INLINK_ADDR_CH4_S)
+#define H264_DMA_INLINK_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_ADDR_CH4_S  0
+
+/** H264_DMA_IN_STATE_CH4_REG register
+ *  RX CH4 state register
+ */
+#define H264_DMA_IN_STATE_CH4_REG (DR_REG_H264_DMA_BASE + 0x924)
+/** H264_DMA_INLINK_DSCR_ADDR_CH4 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define H264_DMA_INLINK_DSCR_ADDR_CH4    0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH4_M  (H264_DMA_INLINK_DSCR_ADDR_CH4_V << H264_DMA_INLINK_DSCR_ADDR_CH4_S)
+#define H264_DMA_INLINK_DSCR_ADDR_CH4_V  0x0003FFFFU
+#define H264_DMA_INLINK_DSCR_ADDR_CH4_S  0
+/** H264_DMA_IN_DSCR_STATE_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define H264_DMA_IN_DSCR_STATE_CH4    0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH4_M  (H264_DMA_IN_DSCR_STATE_CH4_V << H264_DMA_IN_DSCR_STATE_CH4_S)
+#define H264_DMA_IN_DSCR_STATE_CH4_V  0x00000003U
+#define H264_DMA_IN_DSCR_STATE_CH4_S  18
+/** H264_DMA_IN_STATE_CH4 : RO; bitpos: [22:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH4    0x00000007U
+#define H264_DMA_IN_STATE_CH4_M  (H264_DMA_IN_STATE_CH4_V << H264_DMA_IN_STATE_CH4_S)
+#define H264_DMA_IN_STATE_CH4_V  0x00000007U
+#define H264_DMA_IN_STATE_CH4_S  20
+/** H264_DMA_IN_RESET_AVAIL_CH4 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH4    (BIT(23))
+#define H264_DMA_IN_RESET_AVAIL_CH4_M  (H264_DMA_IN_RESET_AVAIL_CH4_V << H264_DMA_IN_RESET_AVAIL_CH4_S)
+#define H264_DMA_IN_RESET_AVAIL_CH4_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH4_S  23
+
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_REG register
+ *  RX CH4 eof des addr register
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x928)
+/** H264_DMA_IN_SUC_EOF_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_M  (H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_V << H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_S)
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_IN_SUC_EOF_DES_ADDR_CH4_S  0
+
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_REG register
+ *  RX CH4 err eof des addr register
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x92c)
+/** H264_DMA_IN_ERR_EOF_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_M  (H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_V << H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_S)
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_IN_ERR_EOF_DES_ADDR_CH4_S  0
+
+/** H264_DMA_IN_DSCR_CH4_REG register
+ *  RX CH4 next dscr addr register
+ */
+#define H264_DMA_IN_DSCR_CH4_REG (DR_REG_H264_DMA_BASE + 0x930)
+/** H264_DMA_INLINK_DSCR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define H264_DMA_INLINK_DSCR_CH4    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH4_M  (H264_DMA_INLINK_DSCR_CH4_V << H264_DMA_INLINK_DSCR_CH4_S)
+#define H264_DMA_INLINK_DSCR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_CH4_S  0
+
+/** H264_DMA_IN_DSCR_BF0_CH4_REG register
+ *  RX CH4 last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF0_CH4_REG (DR_REG_H264_DMA_BASE + 0x934)
+/** H264_DMA_INLINK_DSCR_BF0_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define H264_DMA_INLINK_DSCR_BF0_CH4    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH4_M  (H264_DMA_INLINK_DSCR_BF0_CH4_V << H264_DMA_INLINK_DSCR_BF0_CH4_S)
+#define H264_DMA_INLINK_DSCR_BF0_CH4_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF0_CH4_S  0
+
+/** H264_DMA_IN_DSCR_BF1_CH4_REG register
+ *  RX CH4 second-to-last dscr addr register
+ */
+#define H264_DMA_IN_DSCR_BF1_CH4_REG (DR_REG_H264_DMA_BASE + 0x938)
+/** H264_DMA_INLINK_DSCR_BF1_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define H264_DMA_INLINK_DSCR_BF1_CH4    0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH4_M  (H264_DMA_INLINK_DSCR_BF1_CH4_V << H264_DMA_INLINK_DSCR_BF1_CH4_S)
+#define H264_DMA_INLINK_DSCR_BF1_CH4_V  0xFFFFFFFFU
+#define H264_DMA_INLINK_DSCR_BF1_CH4_S  0
+
+/** H264_DMA_IN_ARB_CH4_REG register
+ *  RX CH4 arb register
+ */
+#define H264_DMA_IN_ARB_CH4_REG (DR_REG_H264_DMA_BASE + 0x940)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH4 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH4    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH4_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH4_V << H264_DMA_IN_ARB_TOKEN_NUM_CH4_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH4_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH4_S  0
+/** H264_DMA_EXTER_IN_ARB_PRIORITY_CH4 : R/W; bitpos: [5:4]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH4    0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_M  (H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_V << H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_S)
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_V  0x00000003U
+#define H264_DMA_EXTER_IN_ARB_PRIORITY_CH4_S  4
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH4 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH4    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH4_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH4_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH4_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH4_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH4_S  6
+
+/** H264_DMA_IN_ETM_CONF_CH4_REG register
+ *  RX CH4 ETM config register
+ */
+#define H264_DMA_IN_ETM_CONF_CH4_REG (DR_REG_H264_DMA_BASE + 0x948)
+/** H264_DMA_IN_ETM_EN_CH4 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to 1 to enable ETM task function
+ */
+#define H264_DMA_IN_ETM_EN_CH4    (BIT(0))
+#define H264_DMA_IN_ETM_EN_CH4_M  (H264_DMA_IN_ETM_EN_CH4_V << H264_DMA_IN_ETM_EN_CH4_S)
+#define H264_DMA_IN_ETM_EN_CH4_V  0x00000001U
+#define H264_DMA_IN_ETM_EN_CH4_S  0
+/** H264_DMA_IN_ETM_LOOP_EN_CH4 : R/W; bitpos: [1]; default: 0;
+ *  when this bit is 1, dscr can be processed after receiving a task
+ */
+#define H264_DMA_IN_ETM_LOOP_EN_CH4    (BIT(1))
+#define H264_DMA_IN_ETM_LOOP_EN_CH4_M  (H264_DMA_IN_ETM_LOOP_EN_CH4_V << H264_DMA_IN_ETM_LOOP_EN_CH4_S)
+#define H264_DMA_IN_ETM_LOOP_EN_CH4_V  0x00000001U
+#define H264_DMA_IN_ETM_LOOP_EN_CH4_S  1
+/** H264_DMA_IN_DSCR_TASK_MAK_CH4 : R/W; bitpos: [3:2]; default: 1;
+ *  ETM dscr_ready maximum cache numbers
+ */
+#define H264_DMA_IN_DSCR_TASK_MAK_CH4    0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH4_M  (H264_DMA_IN_DSCR_TASK_MAK_CH4_V << H264_DMA_IN_DSCR_TASK_MAK_CH4_S)
+#define H264_DMA_IN_DSCR_TASK_MAK_CH4_V  0x00000003U
+#define H264_DMA_IN_DSCR_TASK_MAK_CH4_S  2
+
+/** H264_DMA_IN_FIFO_CNT_CH4_REG register
+ *  rx CH4 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH4_REG (DR_REG_H264_DMA_BASE + 0x980)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH4_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH4_REG register
+ *  rx CH4 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH4_REG (DR_REG_H264_DMA_BASE + 0x984)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4 : RO; bitpos: [7:0]; default: 7;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH4_S  0
+
+/** H264_DMA_IN_XADDR_CH4_REG register
+ *  rx CH4 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH4_REG (DR_REG_H264_DMA_BASE + 0x988)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH4    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH4_M  (H264_DMA_IN_CMDFIFO_XADDR_CH4_V << H264_DMA_IN_CMDFIFO_XADDR_CH4_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH4_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH4_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH4_REG register
+ *  rx CH4 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH4_REG (DR_REG_H264_DMA_BASE + 0x98c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH4_S  0
+
+/** H264_DMA_IN_CONF0_CH5_REG register
+ *  RX CH5 config0 register
+ */
+#define H264_DMA_IN_CONF0_CH5_REG (DR_REG_H264_DMA_BASE + 0xa00)
+/** H264_DMA_IN_ECC_AES_EN_CH5 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define H264_DMA_IN_ECC_AES_EN_CH5    (BIT(3))
+#define H264_DMA_IN_ECC_AES_EN_CH5_M  (H264_DMA_IN_ECC_AES_EN_CH5_V << H264_DMA_IN_ECC_AES_EN_CH5_S)
+#define H264_DMA_IN_ECC_AES_EN_CH5_V  0x00000001U
+#define H264_DMA_IN_ECC_AES_EN_CH5_S  3
+/** H264_DMA_IN_MEM_BURST_LENGTH_CH5 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH5    0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH5_M  (H264_DMA_IN_MEM_BURST_LENGTH_CH5_V << H264_DMA_IN_MEM_BURST_LENGTH_CH5_S)
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH5_V  0x00000007U
+#define H264_DMA_IN_MEM_BURST_LENGTH_CH5_S  6
+/** H264_DMA_IN_PAGE_BOUND_EN_CH5 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define H264_DMA_IN_PAGE_BOUND_EN_CH5    (BIT(12))
+#define H264_DMA_IN_PAGE_BOUND_EN_CH5_M  (H264_DMA_IN_PAGE_BOUND_EN_CH5_V << H264_DMA_IN_PAGE_BOUND_EN_CH5_S)
+#define H264_DMA_IN_PAGE_BOUND_EN_CH5_V  0x00000001U
+#define H264_DMA_IN_PAGE_BOUND_EN_CH5_S  12
+/** H264_DMA_IN_RST_CH5 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define H264_DMA_IN_RST_CH5    (BIT(24))
+#define H264_DMA_IN_RST_CH5_M  (H264_DMA_IN_RST_CH5_V << H264_DMA_IN_RST_CH5_S)
+#define H264_DMA_IN_RST_CH5_V  0x00000001U
+#define H264_DMA_IN_RST_CH5_S  24
+/** H264_DMA_IN_CMD_DISABLE_CH5 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define H264_DMA_IN_CMD_DISABLE_CH5    (BIT(25))
+#define H264_DMA_IN_CMD_DISABLE_CH5_M  (H264_DMA_IN_CMD_DISABLE_CH5_V << H264_DMA_IN_CMD_DISABLE_CH5_S)
+#define H264_DMA_IN_CMD_DISABLE_CH5_V  0x00000001U
+#define H264_DMA_IN_CMD_DISABLE_CH5_S  25
+
+/** H264_DMA_IN_CONF1_CH5_REG register
+ *  RX CH5 config1 register
+ */
+#define H264_DMA_IN_CONF1_CH5_REG (DR_REG_H264_DMA_BASE + 0xa04)
+/** H264_DMA_BLOCK_START_ADDR_CH5 : R/W; bitpos: [31:0]; default: 0;
+ *  RX Channel 5 destination start address
+ */
+#define H264_DMA_BLOCK_START_ADDR_CH5    0xFFFFFFFFU
+#define H264_DMA_BLOCK_START_ADDR_CH5_M  (H264_DMA_BLOCK_START_ADDR_CH5_V << H264_DMA_BLOCK_START_ADDR_CH5_S)
+#define H264_DMA_BLOCK_START_ADDR_CH5_V  0xFFFFFFFFU
+#define H264_DMA_BLOCK_START_ADDR_CH5_S  0
+
+/** H264_DMA_IN_CONF2_CH5_REG register
+ *  RX CH5 config2 register
+ */
+#define H264_DMA_IN_CONF2_CH5_REG (DR_REG_H264_DMA_BASE + 0xa08)
+/** H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5 : R/W; bitpos: [15:0]; default: 30720;
+ *  The number of bytes contained in a row block 12line in RX channel 5
+ */
+#define H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5    0x0000FFFFU
+#define H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_M  (H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_V << H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_S)
+#define H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_V  0x0000FFFFU
+#define H264_DMA_BLOCK_ROW_LENGTH_12LINE_CH5_S  0
+/** H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5 : R/W; bitpos: [31:16]; default: 15360;
+ *  The number of bytes contained in a row block 4line in RX channel 5
+ */
+#define H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5    0x0000FFFFU
+#define H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_M  (H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_V << H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_S)
+#define H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_V  0x0000FFFFU
+#define H264_DMA_BLOCK_ROW_LENGTH_4LINE_CH5_S  16
+
+/** H264_DMA_IN_CONF3_CH5_REG register
+ *  RX CH5 config3 register
+ */
+#define H264_DMA_IN_CONF3_CH5_REG (DR_REG_H264_DMA_BASE + 0xa0c)
+/** H264_DMA_BLOCK_LENGTH_12LINE_CH5 : R/W; bitpos: [13:0]; default: 256;
+ *  The number of bytes contained in a block 12line
+ */
+#define H264_DMA_BLOCK_LENGTH_12LINE_CH5    0x00003FFFU
+#define H264_DMA_BLOCK_LENGTH_12LINE_CH5_M  (H264_DMA_BLOCK_LENGTH_12LINE_CH5_V << H264_DMA_BLOCK_LENGTH_12LINE_CH5_S)
+#define H264_DMA_BLOCK_LENGTH_12LINE_CH5_V  0x00003FFFU
+#define H264_DMA_BLOCK_LENGTH_12LINE_CH5_S  0
+/** H264_DMA_BLOCK_LENGTH_4LINE_CH5 : R/W; bitpos: [27:14]; default: 128;
+ *  The number of bytes contained in a block 4line
+ */
+#define H264_DMA_BLOCK_LENGTH_4LINE_CH5    0x00003FFFU
+#define H264_DMA_BLOCK_LENGTH_4LINE_CH5_M  (H264_DMA_BLOCK_LENGTH_4LINE_CH5_V << H264_DMA_BLOCK_LENGTH_4LINE_CH5_S)
+#define H264_DMA_BLOCK_LENGTH_4LINE_CH5_V  0x00003FFFU
+#define H264_DMA_BLOCK_LENGTH_4LINE_CH5_S  14
+
+/** H264_DMA_IN_INT_RAW_CH5_REG register
+ *  RX CH5  interrupt raw register
+ */
+#define H264_DMA_IN_INT_RAW_CH5_REG (DR_REG_H264_DMA_BASE + 0xa10)
+/** H264_DMA_IN_DONE_CH5_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 1.
+ */
+#define H264_DMA_IN_DONE_CH5_INT_RAW    (BIT(0))
+#define H264_DMA_IN_DONE_CH5_INT_RAW_M  (H264_DMA_IN_DONE_CH5_INT_RAW_V << H264_DMA_IN_DONE_CH5_INT_RAW_S)
+#define H264_DMA_IN_DONE_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_DONE_CH5_INT_RAW_S  0
+/** H264_DMA_IN_SUC_EOF_CH5_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 1.
+ */
+#define H264_DMA_IN_SUC_EOF_CH5_INT_RAW    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH5_INT_RAW_M  (H264_DMA_IN_SUC_EOF_CH5_INT_RAW_V << H264_DMA_IN_SUC_EOF_CH5_INT_RAW_S)
+#define H264_DMA_IN_SUC_EOF_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH5_INT_RAW_S  1
+/** H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW    (BIT(2))
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_M  (H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_V << H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_S)
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_RAW_S  2
+/** H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW    (BIT(3))
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_M  (H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_V << H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_S)
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_RAW_S  3
+/** H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW    (BIT(4))
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_M  (H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_V << H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_S)
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_V  0x00000001U
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_RAW_S  4
+
+/** H264_DMA_IN_INT_ENA_CH5_REG register
+ *  RX CH5  interrupt ena register
+ */
+#define H264_DMA_IN_INT_ENA_CH5_REG (DR_REG_H264_DMA_BASE + 0xa14)
+/** H264_DMA_IN_DONE_CH5_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH5_INT_ENA    (BIT(0))
+#define H264_DMA_IN_DONE_CH5_INT_ENA_M  (H264_DMA_IN_DONE_CH5_INT_ENA_V << H264_DMA_IN_DONE_CH5_INT_ENA_S)
+#define H264_DMA_IN_DONE_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_DONE_CH5_INT_ENA_S  0
+/** H264_DMA_IN_SUC_EOF_CH5_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ENA    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ENA_M  (H264_DMA_IN_SUC_EOF_CH5_INT_ENA_V << H264_DMA_IN_SUC_EOF_CH5_INT_ENA_S)
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ENA_S  1
+/** H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA    (BIT(2))
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_M  (H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_V << H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_S)
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ENA_S  2
+/** H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA    (BIT(3))
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_M  (H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_V << H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_S)
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ENA_S  3
+/** H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA    (BIT(4))
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_M  (H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_V << H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_S)
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_V  0x00000001U
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ENA_S  4
+
+/** H264_DMA_IN_INT_ST_CH5_REG register
+ *  RX CH5  interrupt st register
+ */
+#define H264_DMA_IN_INT_ST_CH5_REG (DR_REG_H264_DMA_BASE + 0xa18)
+/** H264_DMA_IN_DONE_CH5_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH5_INT_ST    (BIT(0))
+#define H264_DMA_IN_DONE_CH5_INT_ST_M  (H264_DMA_IN_DONE_CH5_INT_ST_V << H264_DMA_IN_DONE_CH5_INT_ST_S)
+#define H264_DMA_IN_DONE_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_IN_DONE_CH5_INT_ST_S  0
+/** H264_DMA_IN_SUC_EOF_CH5_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ST    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ST_M  (H264_DMA_IN_SUC_EOF_CH5_INT_ST_V << H264_DMA_IN_SUC_EOF_CH5_INT_ST_S)
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH5_INT_ST_S  1
+/** H264_DMA_INFIFO_OVF_L1_CH5_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ST    (BIT(2))
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_M  (H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_V << H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_S)
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_ST_S  2
+/** H264_DMA_INFIFO_UDF_L1_CH5_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ST    (BIT(3))
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_M  (H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_V << H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_S)
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_ST_S  3
+/** H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST    (BIT(4))
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_M  (H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_V << H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_S)
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_V  0x00000001U
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_ST_S  4
+
+/** H264_DMA_IN_INT_CLR_CH5_REG register
+ *  RX CH5  interrupt clr register
+ */
+#define H264_DMA_IN_INT_CLR_CH5_REG (DR_REG_H264_DMA_BASE + 0xa1c)
+/** H264_DMA_IN_DONE_CH5_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define H264_DMA_IN_DONE_CH5_INT_CLR    (BIT(0))
+#define H264_DMA_IN_DONE_CH5_INT_CLR_M  (H264_DMA_IN_DONE_CH5_INT_CLR_V << H264_DMA_IN_DONE_CH5_INT_CLR_S)
+#define H264_DMA_IN_DONE_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_DONE_CH5_INT_CLR_S  0
+/** H264_DMA_IN_SUC_EOF_CH5_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define H264_DMA_IN_SUC_EOF_CH5_INT_CLR    (BIT(1))
+#define H264_DMA_IN_SUC_EOF_CH5_INT_CLR_M  (H264_DMA_IN_SUC_EOF_CH5_INT_CLR_V << H264_DMA_IN_SUC_EOF_CH5_INT_CLR_S)
+#define H264_DMA_IN_SUC_EOF_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_IN_SUC_EOF_CH5_INT_CLR_S  1
+/** H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR    (BIT(2))
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_M  (H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_V << H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_S)
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_OVF_L1_CH5_INT_CLR_S  2
+/** H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR    (BIT(3))
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_M  (H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_V << H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_S)
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_INFIFO_UDF_L1_CH5_INT_CLR_S  3
+/** H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR    (BIT(4))
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_M  (H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_V << H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_S)
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_V  0x00000001U
+#define H264_DMA_FETCH_MB_COL_CNT_OVF_CH5_INT_CLR_S  4
+
+/** H264_DMA_INFIFO_STATUS_CH5_REG register
+ *  RX CH5 INFIFO status register
+ */
+#define H264_DMA_INFIFO_STATUS_CH5_REG (DR_REG_H264_DMA_BASE + 0xa20)
+/** H264_DMA_INFIFO_FULL_L1_CH5 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_FULL_L1_CH5    (BIT(0))
+#define H264_DMA_INFIFO_FULL_L1_CH5_M  (H264_DMA_INFIFO_FULL_L1_CH5_V << H264_DMA_INFIFO_FULL_L1_CH5_S)
+#define H264_DMA_INFIFO_FULL_L1_CH5_V  0x00000001U
+#define H264_DMA_INFIFO_FULL_L1_CH5_S  0
+/** H264_DMA_INFIFO_EMPTY_L1_CH5 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_EMPTY_L1_CH5    (BIT(1))
+#define H264_DMA_INFIFO_EMPTY_L1_CH5_M  (H264_DMA_INFIFO_EMPTY_L1_CH5_V << H264_DMA_INFIFO_EMPTY_L1_CH5_S)
+#define H264_DMA_INFIFO_EMPTY_L1_CH5_V  0x00000001U
+#define H264_DMA_INFIFO_EMPTY_L1_CH5_S  1
+/** H264_DMA_INFIFO_CNT_L1_CH5 : RO; bitpos: [6:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+ */
+#define H264_DMA_INFIFO_CNT_L1_CH5    0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH5_M  (H264_DMA_INFIFO_CNT_L1_CH5_V << H264_DMA_INFIFO_CNT_L1_CH5_S)
+#define H264_DMA_INFIFO_CNT_L1_CH5_V  0x0000001FU
+#define H264_DMA_INFIFO_CNT_L1_CH5_S  2
+
+/** H264_DMA_IN_POP_CH5_REG register
+ *  RX CH5 INFIFO pop register
+ */
+#define H264_DMA_IN_POP_CH5_REG (DR_REG_H264_DMA_BASE + 0xa24)
+/** H264_DMA_INFIFO_RDATA_CH5 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_RDATA_CH5    0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH5_M  (H264_DMA_INFIFO_RDATA_CH5_V << H264_DMA_INFIFO_RDATA_CH5_S)
+#define H264_DMA_INFIFO_RDATA_CH5_V  0x000007FFU
+#define H264_DMA_INFIFO_RDATA_CH5_S  0
+/** H264_DMA_INFIFO_POP_CH5 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define H264_DMA_INFIFO_POP_CH5    (BIT(11))
+#define H264_DMA_INFIFO_POP_CH5_M  (H264_DMA_INFIFO_POP_CH5_V << H264_DMA_INFIFO_POP_CH5_S)
+#define H264_DMA_INFIFO_POP_CH5_V  0x00000001U
+#define H264_DMA_INFIFO_POP_CH5_S  11
+
+/** H264_DMA_IN_STATE_CH5_REG register
+ *  RX CH5 state register
+ */
+#define H264_DMA_IN_STATE_CH5_REG (DR_REG_H264_DMA_BASE + 0xa28)
+/** H264_DMA_IN_STATE_CH5 : RO; bitpos: [2:0]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define H264_DMA_IN_STATE_CH5    0x00000007U
+#define H264_DMA_IN_STATE_CH5_M  (H264_DMA_IN_STATE_CH5_V << H264_DMA_IN_STATE_CH5_S)
+#define H264_DMA_IN_STATE_CH5_V  0x00000007U
+#define H264_DMA_IN_STATE_CH5_S  0
+/** H264_DMA_IN_RESET_AVAIL_CH5 : RO; bitpos: [3]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define H264_DMA_IN_RESET_AVAIL_CH5    (BIT(3))
+#define H264_DMA_IN_RESET_AVAIL_CH5_M  (H264_DMA_IN_RESET_AVAIL_CH5_V << H264_DMA_IN_RESET_AVAIL_CH5_S)
+#define H264_DMA_IN_RESET_AVAIL_CH5_V  0x00000001U
+#define H264_DMA_IN_RESET_AVAIL_CH5_S  3
+
+/** H264_DMA_IN_ARB_CH5_REG register
+ *  RX CH5 arb register
+ */
+#define H264_DMA_IN_ARB_CH5_REG (DR_REG_H264_DMA_BASE + 0xa40)
+/** H264_DMA_IN_ARB_TOKEN_NUM_CH5 : R/W; bitpos: [3:0]; default: 1;
+ *  Set the max number of token count of arbiter
+ */
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH5    0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH5_M  (H264_DMA_IN_ARB_TOKEN_NUM_CH5_V << H264_DMA_IN_ARB_TOKEN_NUM_CH5_S)
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH5_V  0x0000000FU
+#define H264_DMA_IN_ARB_TOKEN_NUM_CH5_S  0
+/** H264_DMA_INTER_IN_ARB_PRIORITY_CH5 : R/W; bitpos: [8:6]; default: 1;
+ *  Set the priority of channel
+ */
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH5    0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH5_M  (H264_DMA_INTER_IN_ARB_PRIORITY_CH5_V << H264_DMA_INTER_IN_ARB_PRIORITY_CH5_S)
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH5_V  0x00000007U
+#define H264_DMA_INTER_IN_ARB_PRIORITY_CH5_S  6
+
+/** H264_DMA_IN_FIFO_CNT_CH5_REG register
+ *  rx CH5 fifo cnt register
+ */
+#define H264_DMA_IN_FIFO_CNT_CH5_REG (DR_REG_H264_DMA_BASE + 0xa80)
+/** H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5 : RO; bitpos: [9:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5    0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_M  (H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_V << H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_S)
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_V  0x000003FFU
+#define H264_DMA_IN_CMDFIFO_INFIFO_CNT_CH5_S  0
+
+/** H264_DMA_IN_POP_DATA_CNT_CH5_REG register
+ *  rx CH5 pop data cnt register
+ */
+#define H264_DMA_IN_POP_DATA_CNT_CH5_REG (DR_REG_H264_DMA_BASE + 0xa84)
+/** H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5 : RO; bitpos: [7:0]; default: 255;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5    0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_M  (H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_V << H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_S)
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_V  0x000000FFU
+#define H264_DMA_IN_CMDFIFO_POP_DATA_CNT_CH5_S  0
+
+/** H264_DMA_IN_XADDR_CH5_REG register
+ *  rx CH5 xaddr register
+ */
+#define H264_DMA_IN_XADDR_CH5_REG (DR_REG_H264_DMA_BASE + 0xa88)
+/** H264_DMA_IN_CMDFIFO_XADDR_CH5 : RO; bitpos: [31:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_XADDR_CH5    0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH5_M  (H264_DMA_IN_CMDFIFO_XADDR_CH5_V << H264_DMA_IN_CMDFIFO_XADDR_CH5_S)
+#define H264_DMA_IN_CMDFIFO_XADDR_CH5_V  0xFFFFFFFFU
+#define H264_DMA_IN_CMDFIFO_XADDR_CH5_S  0
+
+/** H264_DMA_IN_BUF_HB_RCV_CH5_REG register
+ *  rx CH5 buf len hb rcv register
+ */
+#define H264_DMA_IN_BUF_HB_RCV_CH5_REG (DR_REG_H264_DMA_BASE + 0xa8c)
+/** H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5 : RO; bitpos: [28:0]; default: 0;
+ *  only for debug
+ */
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5    0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_M  (H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_V << H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_S)
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_V  0x1FFFFFFFU
+#define H264_DMA_IN_CMDFIFO_BUF_HB_RCV_CH5_S  0
+
+/** H264_DMA_INTER_AXI_ERR_REG register
+ *  inter memory axi err register
+ */
+#define H264_DMA_INTER_AXI_ERR_REG (DR_REG_H264_DMA_BASE + 0xb00)
+/** H264_DMA_INTER_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0;
+ *  AXI read id err cnt
+ */
+#define H264_DMA_INTER_RID_ERR_CNT    0x0000000FU
+#define H264_DMA_INTER_RID_ERR_CNT_M  (H264_DMA_INTER_RID_ERR_CNT_V << H264_DMA_INTER_RID_ERR_CNT_S)
+#define H264_DMA_INTER_RID_ERR_CNT_V  0x0000000FU
+#define H264_DMA_INTER_RID_ERR_CNT_S  0
+/** H264_DMA_INTER_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0;
+ *  AXI read resp err cnt
+ */
+#define H264_DMA_INTER_RRESP_ERR_CNT    0x0000000FU
+#define H264_DMA_INTER_RRESP_ERR_CNT_M  (H264_DMA_INTER_RRESP_ERR_CNT_V << H264_DMA_INTER_RRESP_ERR_CNT_S)
+#define H264_DMA_INTER_RRESP_ERR_CNT_V  0x0000000FU
+#define H264_DMA_INTER_RRESP_ERR_CNT_S  4
+/** H264_DMA_INTER_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0;
+ *  AXI write resp err cnt
+ */
+#define H264_DMA_INTER_WRESP_ERR_CNT    0x0000000FU
+#define H264_DMA_INTER_WRESP_ERR_CNT_M  (H264_DMA_INTER_WRESP_ERR_CNT_V << H264_DMA_INTER_WRESP_ERR_CNT_S)
+#define H264_DMA_INTER_WRESP_ERR_CNT_V  0x0000000FU
+#define H264_DMA_INTER_WRESP_ERR_CNT_S  8
+/** H264_DMA_INTER_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0;
+ *  AXI read cmd fifo remain cmd count
+ */
+#define H264_DMA_INTER_RD_FIFO_CNT    0x00000007U
+#define H264_DMA_INTER_RD_FIFO_CNT_M  (H264_DMA_INTER_RD_FIFO_CNT_V << H264_DMA_INTER_RD_FIFO_CNT_S)
+#define H264_DMA_INTER_RD_FIFO_CNT_V  0x00000007U
+#define H264_DMA_INTER_RD_FIFO_CNT_S  12
+/** H264_DMA_INTER_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0;
+ *  AXI read backup cmd fifo remain cmd count
+ */
+#define H264_DMA_INTER_RD_BAK_FIFO_CNT    0x0000000FU
+#define H264_DMA_INTER_RD_BAK_FIFO_CNT_M  (H264_DMA_INTER_RD_BAK_FIFO_CNT_V << H264_DMA_INTER_RD_BAK_FIFO_CNT_S)
+#define H264_DMA_INTER_RD_BAK_FIFO_CNT_V  0x0000000FU
+#define H264_DMA_INTER_RD_BAK_FIFO_CNT_S  15
+/** H264_DMA_INTER_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0;
+ *  AXI write cmd fifo remain cmd count
+ */
+#define H264_DMA_INTER_WR_FIFO_CNT    0x00000007U
+#define H264_DMA_INTER_WR_FIFO_CNT_M  (H264_DMA_INTER_WR_FIFO_CNT_V << H264_DMA_INTER_WR_FIFO_CNT_S)
+#define H264_DMA_INTER_WR_FIFO_CNT_V  0x00000007U
+#define H264_DMA_INTER_WR_FIFO_CNT_S  19
+/** H264_DMA_INTER_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0;
+ *  AXI write backup cmd fifo remain cmd count
+ */
+#define H264_DMA_INTER_WR_BAK_FIFO_CNT    0x0000000FU
+#define H264_DMA_INTER_WR_BAK_FIFO_CNT_M  (H264_DMA_INTER_WR_BAK_FIFO_CNT_V << H264_DMA_INTER_WR_BAK_FIFO_CNT_S)
+#define H264_DMA_INTER_WR_BAK_FIFO_CNT_V  0x0000000FU
+#define H264_DMA_INTER_WR_BAK_FIFO_CNT_S  22
+
+/** H264_DMA_EXTER_AXI_ERR_REG register
+ *  exter memory axi err register
+ */
+#define H264_DMA_EXTER_AXI_ERR_REG (DR_REG_H264_DMA_BASE + 0xb04)
+/** H264_DMA_EXTER_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0;
+ *  AXI read id err cnt
+ */
+#define H264_DMA_EXTER_RID_ERR_CNT    0x0000000FU
+#define H264_DMA_EXTER_RID_ERR_CNT_M  (H264_DMA_EXTER_RID_ERR_CNT_V << H264_DMA_EXTER_RID_ERR_CNT_S)
+#define H264_DMA_EXTER_RID_ERR_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_RID_ERR_CNT_S  0
+/** H264_DMA_EXTER_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0;
+ *  AXI read resp err cnt
+ */
+#define H264_DMA_EXTER_RRESP_ERR_CNT    0x0000000FU
+#define H264_DMA_EXTER_RRESP_ERR_CNT_M  (H264_DMA_EXTER_RRESP_ERR_CNT_V << H264_DMA_EXTER_RRESP_ERR_CNT_S)
+#define H264_DMA_EXTER_RRESP_ERR_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_RRESP_ERR_CNT_S  4
+/** H264_DMA_EXTER_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0;
+ *  AXI write resp err cnt
+ */
+#define H264_DMA_EXTER_WRESP_ERR_CNT    0x0000000FU
+#define H264_DMA_EXTER_WRESP_ERR_CNT_M  (H264_DMA_EXTER_WRESP_ERR_CNT_V << H264_DMA_EXTER_WRESP_ERR_CNT_S)
+#define H264_DMA_EXTER_WRESP_ERR_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_WRESP_ERR_CNT_S  8
+/** H264_DMA_EXTER_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0;
+ *  AXI read cmd fifo remain cmd count
+ */
+#define H264_DMA_EXTER_RD_FIFO_CNT    0x00000007U
+#define H264_DMA_EXTER_RD_FIFO_CNT_M  (H264_DMA_EXTER_RD_FIFO_CNT_V << H264_DMA_EXTER_RD_FIFO_CNT_S)
+#define H264_DMA_EXTER_RD_FIFO_CNT_V  0x00000007U
+#define H264_DMA_EXTER_RD_FIFO_CNT_S  12
+/** H264_DMA_EXTER_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0;
+ *  AXI read backup cmd fifo remain cmd count
+ */
+#define H264_DMA_EXTER_RD_BAK_FIFO_CNT    0x0000000FU
+#define H264_DMA_EXTER_RD_BAK_FIFO_CNT_M  (H264_DMA_EXTER_RD_BAK_FIFO_CNT_V << H264_DMA_EXTER_RD_BAK_FIFO_CNT_S)
+#define H264_DMA_EXTER_RD_BAK_FIFO_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_RD_BAK_FIFO_CNT_S  15
+/** H264_DMA_EXTER_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0;
+ *  AXI write cmd fifo remain cmd count
+ */
+#define H264_DMA_EXTER_WR_FIFO_CNT    0x00000007U
+#define H264_DMA_EXTER_WR_FIFO_CNT_M  (H264_DMA_EXTER_WR_FIFO_CNT_V << H264_DMA_EXTER_WR_FIFO_CNT_S)
+#define H264_DMA_EXTER_WR_FIFO_CNT_V  0x00000007U
+#define H264_DMA_EXTER_WR_FIFO_CNT_S  19
+/** H264_DMA_EXTER_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0;
+ *  AXI write backup cmd fifo remain cmd count
+ */
+#define H264_DMA_EXTER_WR_BAK_FIFO_CNT    0x0000000FU
+#define H264_DMA_EXTER_WR_BAK_FIFO_CNT_M  (H264_DMA_EXTER_WR_BAK_FIFO_CNT_V << H264_DMA_EXTER_WR_BAK_FIFO_CNT_S)
+#define H264_DMA_EXTER_WR_BAK_FIFO_CNT_V  0x0000000FU
+#define H264_DMA_EXTER_WR_BAK_FIFO_CNT_S  22
+
+/** H264_DMA_RST_CONF_REG register
+ *  axi reset config register
+ */
+#define H264_DMA_RST_CONF_REG (DR_REG_H264_DMA_BASE + 0xb08)
+/** H264_DMA_INTER_AXIM_RD_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+ */
+#define H264_DMA_INTER_AXIM_RD_RST    (BIT(0))
+#define H264_DMA_INTER_AXIM_RD_RST_M  (H264_DMA_INTER_AXIM_RD_RST_V << H264_DMA_INTER_AXIM_RD_RST_S)
+#define H264_DMA_INTER_AXIM_RD_RST_V  0x00000001U
+#define H264_DMA_INTER_AXIM_RD_RST_S  0
+/** H264_DMA_INTER_AXIM_WR_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+ */
+#define H264_DMA_INTER_AXIM_WR_RST    (BIT(1))
+#define H264_DMA_INTER_AXIM_WR_RST_M  (H264_DMA_INTER_AXIM_WR_RST_V << H264_DMA_INTER_AXIM_WR_RST_S)
+#define H264_DMA_INTER_AXIM_WR_RST_V  0x00000001U
+#define H264_DMA_INTER_AXIM_WR_RST_S  1
+/** H264_DMA_EXTER_AXIM_RD_RST : R/W; bitpos: [2]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+ */
+#define H264_DMA_EXTER_AXIM_RD_RST    (BIT(2))
+#define H264_DMA_EXTER_AXIM_RD_RST_M  (H264_DMA_EXTER_AXIM_RD_RST_V << H264_DMA_EXTER_AXIM_RD_RST_S)
+#define H264_DMA_EXTER_AXIM_RD_RST_V  0x00000001U
+#define H264_DMA_EXTER_AXIM_RD_RST_S  2
+/** H264_DMA_EXTER_AXIM_WR_RST : R/W; bitpos: [3]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+ */
+#define H264_DMA_EXTER_AXIM_WR_RST    (BIT(3))
+#define H264_DMA_EXTER_AXIM_WR_RST_M  (H264_DMA_EXTER_AXIM_WR_RST_V << H264_DMA_EXTER_AXIM_WR_RST_S)
+#define H264_DMA_EXTER_AXIM_WR_RST_V  0x00000001U
+#define H264_DMA_EXTER_AXIM_WR_RST_S  3
+/** H264_DMA_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define H264_DMA_CLK_EN    (BIT(4))
+#define H264_DMA_CLK_EN_M  (H264_DMA_CLK_EN_V << H264_DMA_CLK_EN_S)
+#define H264_DMA_CLK_EN_V  0x00000001U
+#define H264_DMA_CLK_EN_S  4
+
+/** H264_DMA_INTER_MEM_START_ADDR0_REG register
+ *  Start address of inter memory range0 register
+ */
+#define H264_DMA_INTER_MEM_START_ADDR0_REG (DR_REG_H264_DMA_BASE + 0xb0c)
+/** H264_DMA_ACCESS_INTER_MEM_START_ADDR0 : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR0    0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR0_M  (H264_DMA_ACCESS_INTER_MEM_START_ADDR0_V << H264_DMA_ACCESS_INTER_MEM_START_ADDR0_S)
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR0_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR0_S  0
+
+/** H264_DMA_INTER_MEM_END_ADDR0_REG register
+ *  end address of inter memory range0 register
+ */
+#define H264_DMA_INTER_MEM_END_ADDR0_REG (DR_REG_H264_DMA_BASE + 0xb10)
+/** H264_DMA_ACCESS_INTER_MEM_END_ADDR0 : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR0    0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR0_M  (H264_DMA_ACCESS_INTER_MEM_END_ADDR0_V << H264_DMA_ACCESS_INTER_MEM_END_ADDR0_S)
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR0_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR0_S  0
+
+/** H264_DMA_INTER_MEM_START_ADDR1_REG register
+ *  Start address of inter memory range1 register
+ */
+#define H264_DMA_INTER_MEM_START_ADDR1_REG (DR_REG_H264_DMA_BASE + 0xb14)
+/** H264_DMA_ACCESS_INTER_MEM_START_ADDR1 : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR1    0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR1_M  (H264_DMA_ACCESS_INTER_MEM_START_ADDR1_V << H264_DMA_ACCESS_INTER_MEM_START_ADDR1_S)
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR1_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_START_ADDR1_S  0
+
+/** H264_DMA_INTER_MEM_END_ADDR1_REG register
+ *  end address of inter memory range1 register
+ */
+#define H264_DMA_INTER_MEM_END_ADDR1_REG (DR_REG_H264_DMA_BASE + 0xb18)
+/** H264_DMA_ACCESS_INTER_MEM_END_ADDR1 : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR1    0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR1_M  (H264_DMA_ACCESS_INTER_MEM_END_ADDR1_V << H264_DMA_ACCESS_INTER_MEM_END_ADDR1_S)
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR1_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_INTER_MEM_END_ADDR1_S  0
+
+/** H264_DMA_EXTER_MEM_START_ADDR0_REG register
+ *  Start address of exter memory range0 register
+ */
+#define H264_DMA_EXTER_MEM_START_ADDR0_REG (DR_REG_H264_DMA_BASE + 0xb20)
+/** H264_DMA_ACCESS_EXTER_MEM_START_ADDR0 : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR0    0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_M  (H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_V << H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_S)
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR0_S  0
+
+/** H264_DMA_EXTER_MEM_END_ADDR0_REG register
+ *  end address of exter memory range0 register
+ */
+#define H264_DMA_EXTER_MEM_END_ADDR0_REG (DR_REG_H264_DMA_BASE + 0xb24)
+/** H264_DMA_ACCESS_EXTER_MEM_END_ADDR0 : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR0    0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_M  (H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_V << H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_S)
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR0_S  0
+
+/** H264_DMA_EXTER_MEM_START_ADDR1_REG register
+ *  Start address of exter memory range1 register
+ */
+#define H264_DMA_EXTER_MEM_START_ADDR1_REG (DR_REG_H264_DMA_BASE + 0xb28)
+/** H264_DMA_ACCESS_EXTER_MEM_START_ADDR1 : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR1    0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_M  (H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_V << H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_S)
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_START_ADDR1_S  0
+
+/** H264_DMA_EXTER_MEM_END_ADDR1_REG register
+ *  end address of exter memory range1 register
+ */
+#define H264_DMA_EXTER_MEM_END_ADDR1_REG (DR_REG_H264_DMA_BASE + 0xb2c)
+/** H264_DMA_ACCESS_EXTER_MEM_END_ADDR1 : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR1    0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_M  (H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_V << H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_S)
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_V  0xFFFFFFFFU
+#define H264_DMA_ACCESS_EXTER_MEM_END_ADDR1_S  0
+
+/** H264_DMA_OUT_ARB_CONFIG_REG register
+ *  reserved
+ */
+#define H264_DMA_OUT_ARB_CONFIG_REG (DR_REG_H264_DMA_BASE + 0xb30)
+/** H264_DMA_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define H264_DMA_OUT_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define H264_DMA_OUT_ARB_TIMEOUT_NUM_M  (H264_DMA_OUT_ARB_TIMEOUT_NUM_V << H264_DMA_OUT_ARB_TIMEOUT_NUM_S)
+#define H264_DMA_OUT_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define H264_DMA_OUT_ARB_TIMEOUT_NUM_S  0
+/** H264_DMA_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define H264_DMA_OUT_WEIGHT_EN    (BIT(16))
+#define H264_DMA_OUT_WEIGHT_EN_M  (H264_DMA_OUT_WEIGHT_EN_V << H264_DMA_OUT_WEIGHT_EN_S)
+#define H264_DMA_OUT_WEIGHT_EN_V  0x00000001U
+#define H264_DMA_OUT_WEIGHT_EN_S  16
+
+/** H264_DMA_IN_ARB_CONFIG_REG register
+ *  reserved
+ */
+#define H264_DMA_IN_ARB_CONFIG_REG (DR_REG_H264_DMA_BASE + 0xb34)
+/** H264_DMA_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define H264_DMA_IN_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define H264_DMA_IN_ARB_TIMEOUT_NUM_M  (H264_DMA_IN_ARB_TIMEOUT_NUM_V << H264_DMA_IN_ARB_TIMEOUT_NUM_S)
+#define H264_DMA_IN_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define H264_DMA_IN_ARB_TIMEOUT_NUM_S  0
+/** H264_DMA_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define H264_DMA_IN_WEIGHT_EN    (BIT(16))
+#define H264_DMA_IN_WEIGHT_EN_M  (H264_DMA_IN_WEIGHT_EN_V << H264_DMA_IN_WEIGHT_EN_S)
+#define H264_DMA_IN_WEIGHT_EN_V  0x00000001U
+#define H264_DMA_IN_WEIGHT_EN_S  16
+
+/** H264_DMA_DATE_REG register
+ *  reserved
+ */
+#define H264_DMA_DATE_REG (DR_REG_H264_DMA_BASE + 0xb3c)
+/** H264_DMA_DATE : R/W; bitpos: [31:0]; default: 539165699;
+ *  register version.
+ */
+#define H264_DMA_DATE    0xFFFFFFFFU
+#define H264_DMA_DATE_M  (H264_DMA_DATE_V << H264_DMA_DATE_S)
+#define H264_DMA_DATE_V  0xFFFFFFFFU
+#define H264_DMA_DATE_S  0
+
+/** H264_DMA_COUNTER_RST_REG register
+ *  counter reset register
+ */
+#define H264_DMA_COUNTER_RST_REG (DR_REG_H264_DMA_BASE + 0xb50)
+/** H264_DMA_RX_CH0_EXTER_COUNTER_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0 to this bit to reset rx ch0 counter.
+ */
+#define H264_DMA_RX_CH0_EXTER_COUNTER_RST    (BIT(0))
+#define H264_DMA_RX_CH0_EXTER_COUNTER_RST_M  (H264_DMA_RX_CH0_EXTER_COUNTER_RST_V << H264_DMA_RX_CH0_EXTER_COUNTER_RST_S)
+#define H264_DMA_RX_CH0_EXTER_COUNTER_RST_V  0x00000001U
+#define H264_DMA_RX_CH0_EXTER_COUNTER_RST_S  0
+/** H264_DMA_RX_CH1_EXTER_COUNTER_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0 to this bit to reset rx ch1 counter.
+ */
+#define H264_DMA_RX_CH1_EXTER_COUNTER_RST    (BIT(1))
+#define H264_DMA_RX_CH1_EXTER_COUNTER_RST_M  (H264_DMA_RX_CH1_EXTER_COUNTER_RST_V << H264_DMA_RX_CH1_EXTER_COUNTER_RST_S)
+#define H264_DMA_RX_CH1_EXTER_COUNTER_RST_V  0x00000001U
+#define H264_DMA_RX_CH1_EXTER_COUNTER_RST_S  1
+/** H264_DMA_RX_CH2_INTER_COUNTER_RST : R/W; bitpos: [2]; default: 0;
+ *  Write 1 then write 0 to this bit to reset rx ch2 counter.
+ */
+#define H264_DMA_RX_CH2_INTER_COUNTER_RST    (BIT(2))
+#define H264_DMA_RX_CH2_INTER_COUNTER_RST_M  (H264_DMA_RX_CH2_INTER_COUNTER_RST_V << H264_DMA_RX_CH2_INTER_COUNTER_RST_S)
+#define H264_DMA_RX_CH2_INTER_COUNTER_RST_V  0x00000001U
+#define H264_DMA_RX_CH2_INTER_COUNTER_RST_S  2
+/** H264_DMA_RX_CH5_INTER_COUNTER_RST : R/W; bitpos: [3]; default: 0;
+ *  Write 1 then write 0 to this bit to reset rx ch5 counter.
+ */
+#define H264_DMA_RX_CH5_INTER_COUNTER_RST    (BIT(3))
+#define H264_DMA_RX_CH5_INTER_COUNTER_RST_M  (H264_DMA_RX_CH5_INTER_COUNTER_RST_V << H264_DMA_RX_CH5_INTER_COUNTER_RST_S)
+#define H264_DMA_RX_CH5_INTER_COUNTER_RST_V  0x00000001U
+#define H264_DMA_RX_CH5_INTER_COUNTER_RST_S  3
+
+/** H264_DMA_RX_CH0_COUNTER_REG register
+ *  rx ch0 counter register
+ */
+#define H264_DMA_RX_CH0_COUNTER_REG (DR_REG_H264_DMA_BASE + 0xb54)
+/** H264_DMA_RX_CH0_CNT : RO; bitpos: [22:0]; default: 0;
+ *  rx ch0 counter register
+ */
+#define H264_DMA_RX_CH0_CNT    0x007FFFFFU
+#define H264_DMA_RX_CH0_CNT_M  (H264_DMA_RX_CH0_CNT_V << H264_DMA_RX_CH0_CNT_S)
+#define H264_DMA_RX_CH0_CNT_V  0x007FFFFFU
+#define H264_DMA_RX_CH0_CNT_S  0
+
+/** H264_DMA_RX_CH1_COUNTER_REG register
+ *  rx ch1 counter register
+ */
+#define H264_DMA_RX_CH1_COUNTER_REG (DR_REG_H264_DMA_BASE + 0xb58)
+/** H264_DMA_RX_CH1_CNT : RO; bitpos: [20:0]; default: 0;
+ *  rx ch1 counter register
+ */
+#define H264_DMA_RX_CH1_CNT    0x001FFFFFU
+#define H264_DMA_RX_CH1_CNT_M  (H264_DMA_RX_CH1_CNT_V << H264_DMA_RX_CH1_CNT_S)
+#define H264_DMA_RX_CH1_CNT_V  0x001FFFFFU
+#define H264_DMA_RX_CH1_CNT_S  0
+
+/** H264_DMA_RX_CH2_COUNTER_REG register
+ *  rx ch2 counter register
+ */
+#define H264_DMA_RX_CH2_COUNTER_REG (DR_REG_H264_DMA_BASE + 0xb5c)
+/** H264_DMA_RX_CH2_CNT : RO; bitpos: [10:0]; default: 0;
+ *  rx ch2 counter register
+ */
+#define H264_DMA_RX_CH2_CNT    0x000007FFU
+#define H264_DMA_RX_CH2_CNT_M  (H264_DMA_RX_CH2_CNT_V << H264_DMA_RX_CH2_CNT_S)
+#define H264_DMA_RX_CH2_CNT_V  0x000007FFU
+#define H264_DMA_RX_CH2_CNT_S  0
+
+/** H264_DMA_RX_CH5_COUNTER_REG register
+ *  rx ch5 counter register
+ */
+#define H264_DMA_RX_CH5_COUNTER_REG (DR_REG_H264_DMA_BASE + 0xb60)
+/** H264_DMA_RX_CH5_CNT : RO; bitpos: [16:0]; default: 0;
+ *  rx ch5 counter register
+ */
+#define H264_DMA_RX_CH5_CNT    0x0001FFFFU
+#define H264_DMA_RX_CH5_CNT_M  (H264_DMA_RX_CH5_CNT_V << H264_DMA_RX_CH5_CNT_S)
+#define H264_DMA_RX_CH5_CNT_V  0x0001FFFFU
+#define H264_DMA_RX_CH5_CNT_S  0
+
+/** H264_DMA_PBYTE_REG register
+ *  image pbyte register
+ */
+#define H264_DMA_PBYTE_REG (DR_REG_H264_DMA_BASE + 0xb64)
+/** H264_DMA_ORI_PBYTE : R/W; bitpos: [3:0]; default: 2;
+ *  configures bytes per pixel for ori img. 0: 0.5byte/pix, 1: 1byte/pix, 2:
+ *  1.5byte/pix, 3: 2byte/pix, 4: 3byte/pix
+ */
+#define H264_DMA_ORI_PBYTE    0x0000000FU
+#define H264_DMA_ORI_PBYTE_M  (H264_DMA_ORI_PBYTE_V << H264_DMA_ORI_PBYTE_S)
+#define H264_DMA_ORI_PBYTE_V  0x0000000FU
+#define H264_DMA_ORI_PBYTE_S  0
+
+/** H264_DMA_CH_DBG_EN_REG register
+ *  channel debug enable register
+ */
+#define H264_DMA_CH_DBG_EN_REG (DR_REG_H264_DMA_BASE + 0xb68)
+/** H264_DMA_OUT_CH0_DBG_EN : R/W; bitpos: [0]; default: 0;
+ *  configures whether to enable out channel 0 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH0_DBG_EN    (BIT(0))
+#define H264_DMA_OUT_CH0_DBG_EN_M  (H264_DMA_OUT_CH0_DBG_EN_V << H264_DMA_OUT_CH0_DBG_EN_S)
+#define H264_DMA_OUT_CH0_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH0_DBG_EN_S  0
+/** H264_DMA_OUT_CH1_DBG_EN : R/W; bitpos: [1]; default: 0;
+ *  configures whether to enable out channel 1 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH1_DBG_EN    (BIT(1))
+#define H264_DMA_OUT_CH1_DBG_EN_M  (H264_DMA_OUT_CH1_DBG_EN_V << H264_DMA_OUT_CH1_DBG_EN_S)
+#define H264_DMA_OUT_CH1_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH1_DBG_EN_S  1
+/** H264_DMA_OUT_CH2_DBG_EN : R/W; bitpos: [2]; default: 0;
+ *  configures whether to enable out channel 2 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH2_DBG_EN    (BIT(2))
+#define H264_DMA_OUT_CH2_DBG_EN_M  (H264_DMA_OUT_CH2_DBG_EN_V << H264_DMA_OUT_CH2_DBG_EN_S)
+#define H264_DMA_OUT_CH2_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH2_DBG_EN_S  2
+/** H264_DMA_OUT_CH3_DBG_EN : R/W; bitpos: [3]; default: 0;
+ *  configures whether to enable out channel 3 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH3_DBG_EN    (BIT(3))
+#define H264_DMA_OUT_CH3_DBG_EN_M  (H264_DMA_OUT_CH3_DBG_EN_V << H264_DMA_OUT_CH3_DBG_EN_S)
+#define H264_DMA_OUT_CH3_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH3_DBG_EN_S  3
+/** H264_DMA_OUT_CH4_DBG_EN : R/W; bitpos: [4]; default: 0;
+ *  configures whether to enable out channel 4 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_OUT_CH4_DBG_EN    (BIT(4))
+#define H264_DMA_OUT_CH4_DBG_EN_M  (H264_DMA_OUT_CH4_DBG_EN_V << H264_DMA_OUT_CH4_DBG_EN_S)
+#define H264_DMA_OUT_CH4_DBG_EN_V  0x00000001U
+#define H264_DMA_OUT_CH4_DBG_EN_S  4
+/** H264_DMA_IN_CH0_DBG_EN : R/W; bitpos: [16]; default: 0;
+ *  configures whether to enable in channel 0 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH0_DBG_EN    (BIT(16))
+#define H264_DMA_IN_CH0_DBG_EN_M  (H264_DMA_IN_CH0_DBG_EN_V << H264_DMA_IN_CH0_DBG_EN_S)
+#define H264_DMA_IN_CH0_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH0_DBG_EN_S  16
+/** H264_DMA_IN_CH1_DBG_EN : R/W; bitpos: [17]; default: 0;
+ *  configures whether to enable in channel 1 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH1_DBG_EN    (BIT(17))
+#define H264_DMA_IN_CH1_DBG_EN_M  (H264_DMA_IN_CH1_DBG_EN_V << H264_DMA_IN_CH1_DBG_EN_S)
+#define H264_DMA_IN_CH1_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH1_DBG_EN_S  17
+/** H264_DMA_IN_CH2_DBG_EN : R/W; bitpos: [18]; default: 0;
+ *  configures whether to enable in channel 2 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH2_DBG_EN    (BIT(18))
+#define H264_DMA_IN_CH2_DBG_EN_M  (H264_DMA_IN_CH2_DBG_EN_V << H264_DMA_IN_CH2_DBG_EN_S)
+#define H264_DMA_IN_CH2_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH2_DBG_EN_S  18
+/** H264_DMA_IN_CH3_DBG_EN : R/W; bitpos: [19]; default: 0;
+ *  configures whether to enable in channel 3 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH3_DBG_EN    (BIT(19))
+#define H264_DMA_IN_CH3_DBG_EN_M  (H264_DMA_IN_CH3_DBG_EN_V << H264_DMA_IN_CH3_DBG_EN_S)
+#define H264_DMA_IN_CH3_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH3_DBG_EN_S  19
+/** H264_DMA_IN_CH4_DBG_EN : R/W; bitpos: [20]; default: 0;
+ *  configures whether to enable in channel 4 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH4_DBG_EN    (BIT(20))
+#define H264_DMA_IN_CH4_DBG_EN_M  (H264_DMA_IN_CH4_DBG_EN_V << H264_DMA_IN_CH4_DBG_EN_S)
+#define H264_DMA_IN_CH4_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH4_DBG_EN_S  20
+/** H264_DMA_IN_CH5_DBG_EN : R/W; bitpos: [21]; default: 0;
+ *  configures whether to enable in channel 5 debug. 0: disable, 1: enable
+ */
+#define H264_DMA_IN_CH5_DBG_EN    (BIT(21))
+#define H264_DMA_IN_CH5_DBG_EN_M  (H264_DMA_IN_CH5_DBG_EN_V << H264_DMA_IN_CH5_DBG_EN_S)
+#define H264_DMA_IN_CH5_DBG_EN_V  0x00000001U
+#define H264_DMA_IN_CH5_DBG_EN_S  21
+
+/** H264_DMA_OUT_CH0_DBG_DATA_L_REG register
+ *  out channel 0 debug data register
+ */
+#define H264_DMA_OUT_CH0_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb6c)
+/** H264_DMA_OUT_CH0_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 0 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH0_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH0_DBG_DATA_L_M  (H264_DMA_OUT_CH0_DBG_DATA_L_V << H264_DMA_OUT_CH0_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH0_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH0_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH0_DBG_DATA_H_REG register
+ *  out channel 0 debug data register
+ */
+#define H264_DMA_OUT_CH0_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb70)
+/** H264_DMA_OUT_CH0_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 0 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH0_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH0_DBG_DATA_H_M  (H264_DMA_OUT_CH0_DBG_DATA_H_V << H264_DMA_OUT_CH0_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH0_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH0_DBG_DATA_H_S  0
+
+/** H264_DMA_OUT_CH1_DBG_DATA_L_REG register
+ *  out channel 1 debug data register
+ */
+#define H264_DMA_OUT_CH1_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb74)
+/** H264_DMA_OUT_CH1_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 1 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH1_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH1_DBG_DATA_L_M  (H264_DMA_OUT_CH1_DBG_DATA_L_V << H264_DMA_OUT_CH1_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH1_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH1_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH1_DBG_DATA_H_REG register
+ *  out channel 1 debug data register
+ */
+#define H264_DMA_OUT_CH1_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb78)
+/** H264_DMA_OUT_CH1_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 1 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH1_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH1_DBG_DATA_H_M  (H264_DMA_OUT_CH1_DBG_DATA_H_V << H264_DMA_OUT_CH1_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH1_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH1_DBG_DATA_H_S  0
+
+/** H264_DMA_OUT_CH2_DBG_DATA_L_REG register
+ *  out channel 2 debug data register
+ */
+#define H264_DMA_OUT_CH2_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb7c)
+/** H264_DMA_OUT_CH2_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 2 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH2_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH2_DBG_DATA_L_M  (H264_DMA_OUT_CH2_DBG_DATA_L_V << H264_DMA_OUT_CH2_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH2_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH2_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH2_DBG_DATA_H_REG register
+ *  out channel 2 debug data register
+ */
+#define H264_DMA_OUT_CH2_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb80)
+/** H264_DMA_OUT_CH2_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 2 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH2_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH2_DBG_DATA_H_M  (H264_DMA_OUT_CH2_DBG_DATA_H_V << H264_DMA_OUT_CH2_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH2_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH2_DBG_DATA_H_S  0
+
+/** H264_DMA_OUT_CH3_DBG_DATA_L_REG register
+ *  out channel 3 debug data register
+ */
+#define H264_DMA_OUT_CH3_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb84)
+/** H264_DMA_OUT_CH3_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 3 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH3_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH3_DBG_DATA_L_M  (H264_DMA_OUT_CH3_DBG_DATA_L_V << H264_DMA_OUT_CH3_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH3_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH3_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH3_DBG_DATA_H_REG register
+ *  out channel 3 debug data register
+ */
+#define H264_DMA_OUT_CH3_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb88)
+/** H264_DMA_OUT_CH3_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 3 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH3_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH3_DBG_DATA_H_M  (H264_DMA_OUT_CH3_DBG_DATA_H_V << H264_DMA_OUT_CH3_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH3_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH3_DBG_DATA_H_S  0
+
+/** H264_DMA_OUT_CH4_DBG_DATA_L_REG register
+ *  out channel 4 debug data register
+ */
+#define H264_DMA_OUT_CH4_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb8c)
+/** H264_DMA_OUT_CH4_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 4 debug data bit 31-0
+ */
+#define H264_DMA_OUT_CH4_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_OUT_CH4_DBG_DATA_L_M  (H264_DMA_OUT_CH4_DBG_DATA_L_V << H264_DMA_OUT_CH4_DBG_DATA_L_S)
+#define H264_DMA_OUT_CH4_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH4_DBG_DATA_L_S  0
+
+/** H264_DMA_OUT_CH4_DBG_DATA_H_REG register
+ *  out channel 4 debug data register
+ */
+#define H264_DMA_OUT_CH4_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb90)
+/** H264_DMA_OUT_CH4_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures out channel 4 debug data bit 63-32
+ */
+#define H264_DMA_OUT_CH4_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_OUT_CH4_DBG_DATA_H_M  (H264_DMA_OUT_CH4_DBG_DATA_H_V << H264_DMA_OUT_CH4_DBG_DATA_H_S)
+#define H264_DMA_OUT_CH4_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_OUT_CH4_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH0_DBG_DATA_L_REG register
+ *  in channel 0 debug data register
+ */
+#define H264_DMA_IN_CH0_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb94)
+/** H264_DMA_IN_CH0_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 0 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH0_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH0_DBG_DATA_L_M  (H264_DMA_IN_CH0_DBG_DATA_L_V << H264_DMA_IN_CH0_DBG_DATA_L_S)
+#define H264_DMA_IN_CH0_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH0_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH0_DBG_DATA_H_REG register
+ *  in channel 0 debug data register
+ */
+#define H264_DMA_IN_CH0_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xb98)
+/** H264_DMA_IN_CH0_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 0 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH0_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH0_DBG_DATA_H_M  (H264_DMA_IN_CH0_DBG_DATA_H_V << H264_DMA_IN_CH0_DBG_DATA_H_S)
+#define H264_DMA_IN_CH0_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH0_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH1_DBG_DATA_L_REG register
+ *  in channel 1 debug data register
+ */
+#define H264_DMA_IN_CH1_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xb9c)
+/** H264_DMA_IN_CH1_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 1 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH1_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH1_DBG_DATA_L_M  (H264_DMA_IN_CH1_DBG_DATA_L_V << H264_DMA_IN_CH1_DBG_DATA_L_S)
+#define H264_DMA_IN_CH1_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH1_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH1_DBG_DATA_H_REG register
+ *  in channel 1 debug data register
+ */
+#define H264_DMA_IN_CH1_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xba0)
+/** H264_DMA_IN_CH1_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 1 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH1_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH1_DBG_DATA_H_M  (H264_DMA_IN_CH1_DBG_DATA_H_V << H264_DMA_IN_CH1_DBG_DATA_H_S)
+#define H264_DMA_IN_CH1_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH1_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH2_DBG_DATA_L_REG register
+ *  in channel 2 debug data register
+ */
+#define H264_DMA_IN_CH2_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xba4)
+/** H264_DMA_IN_CH2_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 2 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH2_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH2_DBG_DATA_L_M  (H264_DMA_IN_CH2_DBG_DATA_L_V << H264_DMA_IN_CH2_DBG_DATA_L_S)
+#define H264_DMA_IN_CH2_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH2_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH2_DBG_DATA_H_REG register
+ *  in channel 2 debug data register
+ */
+#define H264_DMA_IN_CH2_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xba8)
+/** H264_DMA_IN_CH2_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 2 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH2_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH2_DBG_DATA_H_M  (H264_DMA_IN_CH2_DBG_DATA_H_V << H264_DMA_IN_CH2_DBG_DATA_H_S)
+#define H264_DMA_IN_CH2_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH2_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH3_DBG_DATA_L_REG register
+ *  in channel 3 debug data register
+ */
+#define H264_DMA_IN_CH3_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xbac)
+/** H264_DMA_IN_CH3_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 3 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH3_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH3_DBG_DATA_L_M  (H264_DMA_IN_CH3_DBG_DATA_L_V << H264_DMA_IN_CH3_DBG_DATA_L_S)
+#define H264_DMA_IN_CH3_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH3_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH3_DBG_DATA_H_REG register
+ *  in channel 3 debug data register
+ */
+#define H264_DMA_IN_CH3_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xbb0)
+/** H264_DMA_IN_CH3_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 3 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH3_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH3_DBG_DATA_H_M  (H264_DMA_IN_CH3_DBG_DATA_H_V << H264_DMA_IN_CH3_DBG_DATA_H_S)
+#define H264_DMA_IN_CH3_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH3_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH4_DBG_DATA_L_REG register
+ *  in channel 4 debug data register
+ */
+#define H264_DMA_IN_CH4_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xbb4)
+/** H264_DMA_IN_CH4_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 4 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH4_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH4_DBG_DATA_L_M  (H264_DMA_IN_CH4_DBG_DATA_L_V << H264_DMA_IN_CH4_DBG_DATA_L_S)
+#define H264_DMA_IN_CH4_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH4_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH4_DBG_DATA_H_REG register
+ *  in channel 4 debug data register
+ */
+#define H264_DMA_IN_CH4_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xbb8)
+/** H264_DMA_IN_CH4_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 4 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH4_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH4_DBG_DATA_H_M  (H264_DMA_IN_CH4_DBG_DATA_H_V << H264_DMA_IN_CH4_DBG_DATA_H_S)
+#define H264_DMA_IN_CH4_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH4_DBG_DATA_H_S  0
+
+/** H264_DMA_IN_CH5_DBG_DATA_L_REG register
+ *  in channel 5 debug data register
+ */
+#define H264_DMA_IN_CH5_DBG_DATA_L_REG (DR_REG_H264_DMA_BASE + 0xbbc)
+/** H264_DMA_IN_CH5_DBG_DATA_L : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 5 debug data bit 31-0
+ */
+#define H264_DMA_IN_CH5_DBG_DATA_L    0xFFFFFFFFU
+#define H264_DMA_IN_CH5_DBG_DATA_L_M  (H264_DMA_IN_CH5_DBG_DATA_L_V << H264_DMA_IN_CH5_DBG_DATA_L_S)
+#define H264_DMA_IN_CH5_DBG_DATA_L_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH5_DBG_DATA_L_S  0
+
+/** H264_DMA_IN_CH5_DBG_DATA_H_REG register
+ *  in channel 5 debug data register
+ */
+#define H264_DMA_IN_CH5_DBG_DATA_H_REG (DR_REG_H264_DMA_BASE + 0xbc0)
+/** H264_DMA_IN_CH5_DBG_DATA_H : R/W; bitpos: [31:0]; default: 0;
+ *  configures in channel 5 debug data bit 63-32
+ */
+#define H264_DMA_IN_CH5_DBG_DATA_H    0xFFFFFFFFU
+#define H264_DMA_IN_CH5_DBG_DATA_H_M  (H264_DMA_IN_CH5_DBG_DATA_H_V << H264_DMA_IN_CH5_DBG_DATA_H_S)
+#define H264_DMA_IN_CH5_DBG_DATA_H_V  0xFFFFFFFFU
+#define H264_DMA_IN_CH5_DBG_DATA_H_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/h264_dma_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/h264_dma_struct.h
new file mode 100644
index 0000000000..66197170e9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/h264_dma_struct.h
@@ -0,0 +1,7076 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of out_conf0_ch0 register
+ *  TX CH0 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch0:1;
+        /** out_eof_mode_ch0 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch0:1;
+        /** outdscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch0:1;
+        /** out_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch0:1;
+        /** out_check_owner_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch0:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_ch0:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch0:1;
+        uint32_t reserved_13:3;
+        /** out_reorder_en_ch0 : R/W; bitpos: [16]; default: 0;
+         *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t out_reorder_en_ch0:1;
+        uint32_t reserved_17:7;
+        /** out_rst_ch0 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_ch0:1;
+        /** out_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_ch0:1;
+        /** out_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch0:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch0_reg_t;
+
+/** Type of out_push_ch0 register
+ *  TX CH0 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch0 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch0:10;
+        /** outfifo_push_ch0 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch0:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch0_reg_t;
+
+/** Type of out_link_conf_ch0 register
+ *  TX CH0 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch0 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch0:1;
+        /** outlink_start_ch0 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch0:1;
+        /** outlink_restart_ch0 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch0:1;
+        /** outlink_park_ch0 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch0:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch0_reg_t;
+
+/** Type of out_ro_pd_conf_ch0 register
+ *  TX CH0 reorder power config register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** out_ro_ram_force_pd_ch0 : R/W; bitpos: [4]; default: 0;
+         *  dma reorder ram power down
+         */
+        uint32_t out_ro_ram_force_pd_ch0:1;
+        /** out_ro_ram_force_pu_ch0 : R/W; bitpos: [5]; default: 1;
+         *  dma reorder ram power up
+         */
+        uint32_t out_ro_ram_force_pu_ch0:1;
+        /** out_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t out_ro_ram_clk_fo_ch0:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_out_ro_pd_conf_ch0_reg_t;
+
+/** Type of out_push_ch1 register
+ *  TX CH1 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch1 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch1:10;
+        /** outfifo_push_ch1 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch1:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch1_reg_t;
+
+/** Type of out_link_conf_ch1 register
+ *  TX CH1 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch1 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch1:1;
+        /** outlink_start_ch1 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch1:1;
+        /** outlink_restart_ch1 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch1:1;
+        /** outlink_park_ch1 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch1:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch1_reg_t;
+
+/** Type of out_push_ch2 register
+ *  TX CH2 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch2 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch2:10;
+        /** outfifo_push_ch2 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch2:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch2_reg_t;
+
+/** Type of out_link_conf_ch2 register
+ *  TX CH2 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch2 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch2:1;
+        /** outlink_start_ch2 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch2:1;
+        /** outlink_restart_ch2 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch2:1;
+        /** outlink_park_ch2 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch2:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch2_reg_t;
+
+/** Type of out_push_ch3 register
+ *  TX CH3 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch3 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch3:10;
+        /** outfifo_push_ch3 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch3:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch3_reg_t;
+
+/** Type of out_link_conf_ch3 register
+ *  TX CH3 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch3 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch3:1;
+        /** outlink_start_ch3 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch3:1;
+        /** outlink_restart_ch3 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch3:1;
+        /** outlink_park_ch3 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch3:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch3_reg_t;
+
+/** Type of out_push_ch4 register
+ *  TX CH4 outfifo push register
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_ch4 : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_ch4:10;
+        /** outfifo_push_ch4 : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_ch4:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_out_push_ch4_reg_t;
+
+/** Type of out_link_conf_ch4 register
+ *  TX CH4 out_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_ch4 : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_ch4:1;
+        /** outlink_start_ch4 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_ch4:1;
+        /** outlink_restart_ch4 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_ch4:1;
+        /** outlink_park_ch4 : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_ch4:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_link_conf_ch4_reg_t;
+
+/** Type of in_conf0_ch0 register
+ *  RX CH0 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch0:1;
+        /** in_ecc_aes_en_ch0 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch0:1;
+        /** in_check_owner_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch0:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch0 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch0:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch0 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch0:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch0 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch0:1;
+        /** in_cmd_disable_ch0 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch0:1;
+        /** in_arb_weight_opt_dis_ch0 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch0:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch0_reg_t;
+
+/** Type of in_pop_ch0 register
+ *  RX CH0 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch0 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch0:11;
+        /** infifo_pop_ch0 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch0:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch0_reg_t;
+
+/** Type of in_link_conf_ch0 register
+ *  RX CH0 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch0 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch0:1;
+        /** inlink_stop_ch0 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch0:1;
+        /** inlink_start_ch0 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch0:1;
+        /** inlink_restart_ch0 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch0:1;
+        /** inlink_park_ch0 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch0:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch0_reg_t;
+
+/** Type of in_ro_pd_conf_ch0 register
+ *  RX CH0 reorder power config register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** in_ro_ram_clk_fo_ch0 : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t in_ro_ram_clk_fo_ch0:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_in_ro_pd_conf_ch0_reg_t;
+
+/** Type of in_conf0_ch1 register
+ *  RX CH1 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch1:1;
+        /** in_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch1:1;
+        /** in_check_owner_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch1:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch1:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch1:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch1 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch1:1;
+        /** in_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch1:1;
+        /** in_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch1:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch1_reg_t;
+
+/** Type of in_pop_ch1 register
+ *  RX CH1 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch1 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch1:11;
+        /** infifo_pop_ch1 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch1:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch1_reg_t;
+
+/** Type of in_link_conf_ch1 register
+ *  RX CH1 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch1 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch1:1;
+        /** inlink_stop_ch1 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch1:1;
+        /** inlink_start_ch1 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch1:1;
+        /** inlink_restart_ch1 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch1:1;
+        /** inlink_park_ch1 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch1:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch1_reg_t;
+
+/** Type of in_conf0_ch2 register
+ *  RX CH2 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch2:1;
+        /** in_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch2:1;
+        /** in_check_owner_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch2:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch2:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch2:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch2 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch2:1;
+        /** in_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch2:1;
+        /** in_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch2:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch2_reg_t;
+
+/** Type of in_pop_ch2 register
+ *  RX CH2 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch2 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch2:11;
+        /** infifo_pop_ch2 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch2:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch2_reg_t;
+
+/** Type of in_link_conf_ch2 register
+ *  RX CH2 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch2 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch2:1;
+        /** inlink_stop_ch2 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch2:1;
+        /** inlink_start_ch2 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch2:1;
+        /** inlink_restart_ch2 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch2:1;
+        /** inlink_park_ch2 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch2:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch2_reg_t;
+
+/** Type of in_conf0_ch3 register
+ *  RX CH3 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch3:1;
+        /** in_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch3:1;
+        /** in_check_owner_ch3 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch3:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch3:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch3:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch3 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch3:1;
+        /** in_cmd_disable_ch3 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch3:1;
+        /** in_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch3:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch3_reg_t;
+
+/** Type of in_pop_ch3 register
+ *  RX CH3 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch3 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch3:11;
+        /** infifo_pop_ch3 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch3:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch3_reg_t;
+
+/** Type of in_link_conf_ch3 register
+ *  RX CH3 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch3 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch3:1;
+        /** inlink_stop_ch3 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch3:1;
+        /** inlink_start_ch3 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch3:1;
+        /** inlink_restart_ch3 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch3:1;
+        /** inlink_park_ch3 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch3:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch3_reg_t;
+
+/** Type of in_conf0_ch4 register
+ *  RX CH4 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** indscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_ch4:1;
+        /** in_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch4:1;
+        /** in_check_owner_ch4 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_ch4:1;
+        uint32_t reserved_5:1;
+        /** in_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch4:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch4:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch4 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch4:1;
+        /** in_cmd_disable_ch4 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch4:1;
+        /** in_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_ch4:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch4_reg_t;
+
+/** Type of in_pop_ch4 register
+ *  RX CH4 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch4 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch4:11;
+        /** infifo_pop_ch4 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch4:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch4_reg_t;
+
+/** Type of in_link_conf_ch4 register
+ *  RX CH4 in_link dscr ctrl register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_ch4 : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_ch4:1;
+        /** inlink_stop_ch4 : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_ch4:1;
+        /** inlink_start_ch4 : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_ch4:1;
+        /** inlink_restart_ch4 : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_ch4:1;
+        /** inlink_park_ch4 : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_ch4:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_in_link_conf_ch4_reg_t;
+
+/** Type of in_conf0_ch5 register
+ *  RX CH5 config0 register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** in_ecc_aes_en_ch5 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_ch5:1;
+        uint32_t reserved_4:2;
+        /** in_mem_burst_length_ch5 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_ch5:3;
+        uint32_t reserved_9:3;
+        /** in_page_bound_en_ch5 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_ch5:1;
+        uint32_t reserved_13:11;
+        /** in_rst_ch5 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_ch5:1;
+        /** in_cmd_disable_ch5 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_ch5:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} h264_dma_in_conf0_ch5_reg_t;
+
+/** Type of in_pop_ch5 register
+ *  RX CH5 INFIFO pop register
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_ch5 : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_ch5:11;
+        /** infifo_pop_ch5 : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_ch5:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} h264_dma_in_pop_ch5_reg_t;
+
+/** Type of rst_conf register
+ *  axi reset config register
+ */
+typedef union {
+    struct {
+        /** inter_axim_rd_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+         */
+        uint32_t inter_axim_rd_rst:1;
+        /** inter_axim_wr_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+         */
+        uint32_t inter_axim_wr_rst:1;
+        /** exter_axim_rd_rst : R/W; bitpos: [2]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+         */
+        uint32_t exter_axim_rd_rst:1;
+        /** exter_axim_wr_rst : R/W; bitpos: [3]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+         */
+        uint32_t exter_axim_wr_rst:1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_rst_conf_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of out_int_raw_ch0 register
+ *  TX CH0  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch0_int_raw:1;
+        /** out_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch0_int_raw:1;
+        /** out_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch0_int_raw:1;
+        /** out_total_eof_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch0_int_raw:1;
+        /** outfifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch0_int_raw:1;
+        /** outfifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch0_int_raw:1;
+        /** outfifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch0_int_raw:1;
+        /** outfifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch0_int_raw:1;
+        /** out_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch0_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch0_reg_t;
+
+/** Type of out_int_ena_ch0 register
+ *  TX CH0  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch0_int_ena:1;
+        /** out_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch0_int_ena:1;
+        /** out_dscr_err_ch0_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch0_int_ena:1;
+        /** out_total_eof_ch0_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch0_int_ena:1;
+        /** outfifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch0_int_ena:1;
+        /** outfifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch0_int_ena:1;
+        /** outfifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch0_int_ena:1;
+        /** outfifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch0_int_ena:1;
+        /** out_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch0_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch0_reg_t;
+
+/** Type of out_int_st_ch0 register
+ *  TX CH0  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch0_int_st:1;
+        /** out_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch0_int_st:1;
+        /** out_dscr_err_ch0_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch0_int_st:1;
+        /** out_total_eof_ch0_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch0_int_st:1;
+        /** outfifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch0_int_st:1;
+        /** outfifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch0_int_st:1;
+        /** outfifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch0_int_st:1;
+        /** outfifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch0_int_st:1;
+        /** out_dscr_task_ovf_ch0_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch0_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch0_reg_t;
+
+/** Type of out_int_clr_ch0 register
+ *  TX CH0  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch0_int_clr:1;
+        /** out_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch0_int_clr:1;
+        /** out_dscr_err_ch0_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch0_int_clr:1;
+        /** out_total_eof_ch0_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch0_int_clr:1;
+        /** outfifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch0_int_clr:1;
+        /** outfifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch0_int_clr:1;
+        /** outfifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch0_int_clr:1;
+        /** outfifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch0_int_clr:1;
+        /** out_dscr_task_ovf_ch0_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch0_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch0_reg_t;
+
+/** Type of out_int_raw_ch1 register
+ *  TX CH1  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch1_int_raw:1;
+        /** out_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch1_int_raw:1;
+        /** out_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch1_int_raw:1;
+        /** out_total_eof_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch1_int_raw:1;
+        /** outfifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch1_int_raw:1;
+        /** outfifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch1_int_raw:1;
+        /** outfifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch1_int_raw:1;
+        /** outfifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch1_int_raw:1;
+        /** out_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch1_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch1_reg_t;
+
+/** Type of out_int_ena_ch1 register
+ *  TX CH1  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch1_int_ena:1;
+        /** out_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch1_int_ena:1;
+        /** out_dscr_err_ch1_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch1_int_ena:1;
+        /** out_total_eof_ch1_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch1_int_ena:1;
+        /** outfifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch1_int_ena:1;
+        /** outfifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch1_int_ena:1;
+        /** outfifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch1_int_ena:1;
+        /** outfifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch1_int_ena:1;
+        /** out_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch1_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch1_reg_t;
+
+/** Type of out_int_st_ch1 register
+ *  TX CH1  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch1_int_st:1;
+        /** out_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch1_int_st:1;
+        /** out_dscr_err_ch1_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch1_int_st:1;
+        /** out_total_eof_ch1_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch1_int_st:1;
+        /** outfifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch1_int_st:1;
+        /** outfifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch1_int_st:1;
+        /** outfifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch1_int_st:1;
+        /** outfifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch1_int_st:1;
+        /** out_dscr_task_ovf_ch1_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch1_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch1_reg_t;
+
+/** Type of out_int_clr_ch1 register
+ *  TX CH1  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch1_int_clr:1;
+        /** out_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch1_int_clr:1;
+        /** out_dscr_err_ch1_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch1_int_clr:1;
+        /** out_total_eof_ch1_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch1_int_clr:1;
+        /** outfifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch1_int_clr:1;
+        /** outfifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch1_int_clr:1;
+        /** outfifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch1_int_clr:1;
+        /** outfifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch1_int_clr:1;
+        /** out_dscr_task_ovf_ch1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch1_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch1_reg_t;
+
+/** Type of out_int_raw_ch2 register
+ *  TX CH2  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch2_int_raw:1;
+        /** out_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch2_int_raw:1;
+        /** out_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch2_int_raw:1;
+        /** out_total_eof_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch2_int_raw:1;
+        /** outfifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch2_int_raw:1;
+        /** outfifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch2_int_raw:1;
+        /** outfifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch2_int_raw:1;
+        /** outfifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch2_int_raw:1;
+        /** out_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch2_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch2_reg_t;
+
+/** Type of out_int_ena_ch2 register
+ *  TX CH2  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch2_int_ena:1;
+        /** out_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch2_int_ena:1;
+        /** out_dscr_err_ch2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch2_int_ena:1;
+        /** out_total_eof_ch2_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch2_int_ena:1;
+        /** outfifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch2_int_ena:1;
+        /** outfifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch2_int_ena:1;
+        /** outfifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch2_int_ena:1;
+        /** outfifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch2_int_ena:1;
+        /** out_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch2_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch2_reg_t;
+
+/** Type of out_int_st_ch2 register
+ *  TX CH2  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch2_int_st:1;
+        /** out_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch2_int_st:1;
+        /** out_dscr_err_ch2_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch2_int_st:1;
+        /** out_total_eof_ch2_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch2_int_st:1;
+        /** outfifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch2_int_st:1;
+        /** outfifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch2_int_st:1;
+        /** outfifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch2_int_st:1;
+        /** outfifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch2_int_st:1;
+        /** out_dscr_task_ovf_ch2_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch2_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch2_reg_t;
+
+/** Type of out_int_clr_ch2 register
+ *  TX CH2  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch2_int_clr:1;
+        /** out_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch2_int_clr:1;
+        /** out_dscr_err_ch2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch2_int_clr:1;
+        /** out_total_eof_ch2_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch2_int_clr:1;
+        /** outfifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch2_int_clr:1;
+        /** outfifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch2_int_clr:1;
+        /** outfifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch2_int_clr:1;
+        /** outfifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch2_int_clr:1;
+        /** out_dscr_task_ovf_ch2_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch2_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch2_reg_t;
+
+/** Type of out_int_raw_ch3 register
+ *  TX CH3  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch3_int_raw:1;
+        /** out_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch3_int_raw:1;
+        /** out_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch3_int_raw:1;
+        /** out_total_eof_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch3_int_raw:1;
+        /** outfifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch3_int_raw:1;
+        /** outfifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch3_int_raw:1;
+        /** outfifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch3_int_raw:1;
+        /** outfifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch3_int_raw:1;
+        /** out_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch3_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch3_reg_t;
+
+/** Type of out_int_ena_ch3 register
+ *  TX CH3  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch3_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch3_int_ena:1;
+        /** out_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch3_int_ena:1;
+        /** out_dscr_err_ch3_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch3_int_ena:1;
+        /** out_total_eof_ch3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch3_int_ena:1;
+        /** outfifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch3_int_ena:1;
+        /** outfifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch3_int_ena:1;
+        /** outfifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch3_int_ena:1;
+        /** outfifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch3_int_ena:1;
+        /** out_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch3_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch3_reg_t;
+
+/** Type of out_int_st_ch3 register
+ *  TX CH3  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch3_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch3_int_st:1;
+        /** out_eof_ch3_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch3_int_st:1;
+        /** out_dscr_err_ch3_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch3_int_st:1;
+        /** out_total_eof_ch3_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch3_int_st:1;
+        /** outfifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch3_int_st:1;
+        /** outfifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch3_int_st:1;
+        /** outfifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch3_int_st:1;
+        /** outfifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch3_int_st:1;
+        /** out_dscr_task_ovf_ch3_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch3_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch3_reg_t;
+
+/** Type of out_int_clr_ch3 register
+ *  TX CH3  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch3_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch3_int_clr:1;
+        /** out_eof_ch3_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch3_int_clr:1;
+        /** out_dscr_err_ch3_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch3_int_clr:1;
+        /** out_total_eof_ch3_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch3_int_clr:1;
+        /** outfifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch3_int_clr:1;
+        /** outfifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch3_int_clr:1;
+        /** outfifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch3_int_clr:1;
+        /** outfifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch3_int_clr:1;
+        /** out_dscr_task_ovf_ch3_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch3_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch3_reg_t;
+
+/** Type of out_int_raw_ch4 register
+ *  TX CH4  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** out_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_ch4_int_raw:1;
+        /** out_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_ch4_int_raw:1;
+        /** out_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_ch4_int_raw:1;
+        /** out_total_eof_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_ch4_int_raw:1;
+        /** outfifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_ch4_int_raw:1;
+        /** outfifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_ch4_int_raw:1;
+        /** outfifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_ch4_int_raw:1;
+        /** outfifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_ch4_int_raw:1;
+        /** out_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_ch4_int_raw:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_raw_ch4_reg_t;
+
+/** Type of out_int_ena_ch4 register
+ *  TX CH4  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** out_done_ch4_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch4_int_ena:1;
+        /** out_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch4_int_ena:1;
+        /** out_dscr_err_ch4_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch4_int_ena:1;
+        /** out_total_eof_ch4_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch4_int_ena:1;
+        /** outfifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch4_int_ena:1;
+        /** outfifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch4_int_ena:1;
+        /** outfifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch4_int_ena:1;
+        /** outfifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch4_int_ena:1;
+        /** out_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch4_int_ena:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_ena_ch4_reg_t;
+
+/** Type of out_int_st_ch4 register
+ *  TX CH4  interrupt st register
+ */
+typedef union {
+    struct {
+        /** out_done_ch4_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch4_int_st:1;
+        /** out_eof_ch4_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch4_int_st:1;
+        /** out_dscr_err_ch4_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch4_int_st:1;
+        /** out_total_eof_ch4_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch4_int_st:1;
+        /** outfifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch4_int_st:1;
+        /** outfifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch4_int_st:1;
+        /** outfifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch4_int_st:1;
+        /** outfifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch4_int_st:1;
+        /** out_dscr_task_ovf_ch4_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch4_int_st:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_st_ch4_reg_t;
+
+/** Type of out_int_clr_ch4 register
+ *  TX CH4  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** out_done_ch4_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_ch4_int_clr:1;
+        /** out_eof_ch4_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_ch4_int_clr:1;
+        /** out_dscr_err_ch4_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_ch4_int_clr:1;
+        /** out_total_eof_ch4_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_ch4_int_clr:1;
+        /** outfifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_ch4_int_clr:1;
+        /** outfifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_ch4_int_clr:1;
+        /** outfifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_ch4_int_clr:1;
+        /** outfifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_ch4_int_clr:1;
+        /** out_dscr_task_ovf_ch4_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_ch4_int_clr:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_out_int_clr_ch4_reg_t;
+
+/** Type of in_int_raw_ch0 register
+ *  RX CH0  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 0.
+         */
+        uint32_t in_done_ch0_int_raw:1;
+        /** in_suc_eof_ch0_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_ch0_int_raw:1;
+        /** in_err_eof_ch0_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch0_int_raw:1;
+        /** in_dscr_err_ch0_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 0.
+         */
+        uint32_t in_dscr_err_ch0_int_raw:1;
+        /** infifo_ovf_l1_ch0_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch0_int_raw:1;
+        /** infifo_udf_l1_ch0_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch0_int_raw:1;
+        /** infifo_ovf_l2_ch0_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch0_int_raw:1;
+        /** infifo_udf_l2_ch0_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch0_int_raw:1;
+        /** in_dscr_empty_ch0_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch0_int_raw:1;
+        /** in_dscr_task_ovf_ch0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch0_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch0_reg_t;
+
+/** Type of in_int_ena_ch0 register
+ *  RX CH0  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch0_int_ena:1;
+        /** in_suc_eof_ch0_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch0_int_ena:1;
+        /** in_err_eof_ch0_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch0_int_ena:1;
+        /** in_dscr_err_ch0_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch0_int_ena:1;
+        /** infifo_ovf_l1_ch0_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch0_int_ena:1;
+        /** infifo_udf_l1_ch0_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch0_int_ena:1;
+        /** infifo_ovf_l2_ch0_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch0_int_ena:1;
+        /** infifo_udf_l2_ch0_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch0_int_ena:1;
+        /** in_dscr_empty_ch0_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch0_int_ena:1;
+        /** in_dscr_task_ovf_ch0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch0_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch0_reg_t;
+
+/** Type of in_int_st_ch0 register
+ *  RX CH0  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch0_int_st:1;
+        /** in_suc_eof_ch0_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch0_int_st:1;
+        /** in_err_eof_ch0_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch0_int_st:1;
+        /** in_dscr_err_ch0_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch0_int_st:1;
+        /** infifo_ovf_l1_ch0_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch0_int_st:1;
+        /** infifo_udf_l1_ch0_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch0_int_st:1;
+        /** infifo_ovf_l2_ch0_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch0_int_st:1;
+        /** infifo_udf_l2_ch0_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch0_int_st:1;
+        /** in_dscr_empty_ch0_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch0_int_st:1;
+        /** in_dscr_task_ovf_ch0_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch0_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch0_reg_t;
+
+/** Type of in_int_clr_ch0 register
+ *  RX CH0  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch0_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch0_int_clr:1;
+        /** in_suc_eof_ch0_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch0_int_clr:1;
+        /** in_err_eof_ch0_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch0_int_clr:1;
+        /** in_dscr_err_ch0_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch0_int_clr:1;
+        /** infifo_ovf_l1_ch0_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch0_int_clr:1;
+        /** infifo_udf_l1_ch0_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch0_int_clr:1;
+        /** infifo_ovf_l2_ch0_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch0_int_clr:1;
+        /** infifo_udf_l2_ch0_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch0_int_clr:1;
+        /** in_dscr_empty_ch0_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch0_int_clr:1;
+        /** in_dscr_task_ovf_ch0_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch0_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch0_reg_t;
+
+/** Type of in_int_raw_ch1 register
+ *  RX CH1  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch1_int_raw:1;
+        /** in_suc_eof_ch1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch1_int_raw:1;
+        /** in_err_eof_ch1_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch1_int_raw:1;
+        /** in_dscr_err_ch1_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 1.
+         */
+        uint32_t in_dscr_err_ch1_int_raw:1;
+        /** infifo_ovf_l1_ch1_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch1_int_raw:1;
+        /** infifo_udf_l1_ch1_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch1_int_raw:1;
+        /** infifo_ovf_l2_ch1_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch1_int_raw:1;
+        /** infifo_udf_l2_ch1_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch1_int_raw:1;
+        /** in_dscr_empty_ch1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch1_int_raw:1;
+        /** in_dscr_task_ovf_ch1_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch1_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch1_reg_t;
+
+/** Type of in_int_ena_ch1 register
+ *  RX CH1  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch1_int_ena:1;
+        /** in_suc_eof_ch1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch1_int_ena:1;
+        /** in_err_eof_ch1_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch1_int_ena:1;
+        /** in_dscr_err_ch1_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch1_int_ena:1;
+        /** infifo_ovf_l1_ch1_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch1_int_ena:1;
+        /** infifo_udf_l1_ch1_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch1_int_ena:1;
+        /** infifo_ovf_l2_ch1_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch1_int_ena:1;
+        /** infifo_udf_l2_ch1_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch1_int_ena:1;
+        /** in_dscr_empty_ch1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch1_int_ena:1;
+        /** in_dscr_task_ovf_ch1_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch1_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch1_reg_t;
+
+/** Type of in_int_st_ch1 register
+ *  RX CH1  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch1_int_st:1;
+        /** in_suc_eof_ch1_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch1_int_st:1;
+        /** in_err_eof_ch1_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch1_int_st:1;
+        /** in_dscr_err_ch1_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch1_int_st:1;
+        /** infifo_ovf_l1_ch1_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch1_int_st:1;
+        /** infifo_udf_l1_ch1_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch1_int_st:1;
+        /** infifo_ovf_l2_ch1_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch1_int_st:1;
+        /** infifo_udf_l2_ch1_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch1_int_st:1;
+        /** in_dscr_empty_ch1_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch1_int_st:1;
+        /** in_dscr_task_ovf_ch1_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch1_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch1_reg_t;
+
+/** Type of in_int_clr_ch1 register
+ *  RX CH1  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch1_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch1_int_clr:1;
+        /** in_suc_eof_ch1_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch1_int_clr:1;
+        /** in_err_eof_ch1_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch1_int_clr:1;
+        /** in_dscr_err_ch1_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch1_int_clr:1;
+        /** infifo_ovf_l1_ch1_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch1_int_clr:1;
+        /** infifo_udf_l1_ch1_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch1_int_clr:1;
+        /** infifo_ovf_l2_ch1_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch1_int_clr:1;
+        /** infifo_udf_l2_ch1_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch1_int_clr:1;
+        /** in_dscr_empty_ch1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch1_int_clr:1;
+        /** in_dscr_task_ovf_ch1_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch1_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch1_reg_t;
+
+/** Type of in_int_raw_ch2 register
+ *  RX CH2  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch2_int_raw:1;
+        /** in_suc_eof_ch2_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch2_int_raw:1;
+        /** in_err_eof_ch2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch2_int_raw:1;
+        /** in_dscr_err_ch2_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 1.
+         */
+        uint32_t in_dscr_err_ch2_int_raw:1;
+        /** infifo_ovf_l1_ch2_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch2_int_raw:1;
+        /** infifo_udf_l1_ch2_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch2_int_raw:1;
+        /** infifo_ovf_l2_ch2_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch2_int_raw:1;
+        /** infifo_udf_l2_ch2_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch2_int_raw:1;
+        /** in_dscr_empty_ch2_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch2_int_raw:1;
+        /** in_dscr_task_ovf_ch2_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch2_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch2_reg_t;
+
+/** Type of in_int_ena_ch2 register
+ *  RX CH2  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch2_int_ena:1;
+        /** in_suc_eof_ch2_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch2_int_ena:1;
+        /** in_err_eof_ch2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch2_int_ena:1;
+        /** in_dscr_err_ch2_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch2_int_ena:1;
+        /** infifo_ovf_l1_ch2_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch2_int_ena:1;
+        /** infifo_udf_l1_ch2_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch2_int_ena:1;
+        /** infifo_ovf_l2_ch2_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch2_int_ena:1;
+        /** infifo_udf_l2_ch2_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch2_int_ena:1;
+        /** in_dscr_empty_ch2_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch2_int_ena:1;
+        /** in_dscr_task_ovf_ch2_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch2_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch2_reg_t;
+
+/** Type of in_int_st_ch2 register
+ *  RX CH2  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch2_int_st:1;
+        /** in_suc_eof_ch2_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch2_int_st:1;
+        /** in_err_eof_ch2_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch2_int_st:1;
+        /** in_dscr_err_ch2_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch2_int_st:1;
+        /** infifo_ovf_l1_ch2_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch2_int_st:1;
+        /** infifo_udf_l1_ch2_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch2_int_st:1;
+        /** infifo_ovf_l2_ch2_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch2_int_st:1;
+        /** infifo_udf_l2_ch2_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch2_int_st:1;
+        /** in_dscr_empty_ch2_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch2_int_st:1;
+        /** in_dscr_task_ovf_ch2_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch2_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch2_reg_t;
+
+/** Type of in_int_clr_ch2 register
+ *  RX CH2  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch2_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch2_int_clr:1;
+        /** in_suc_eof_ch2_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch2_int_clr:1;
+        /** in_err_eof_ch2_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch2_int_clr:1;
+        /** in_dscr_err_ch2_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch2_int_clr:1;
+        /** infifo_ovf_l1_ch2_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch2_int_clr:1;
+        /** infifo_udf_l1_ch2_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch2_int_clr:1;
+        /** infifo_ovf_l2_ch2_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch2_int_clr:1;
+        /** infifo_udf_l2_ch2_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch2_int_clr:1;
+        /** in_dscr_empty_ch2_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch2_int_clr:1;
+        /** in_dscr_task_ovf_ch2_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch2_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch2_reg_t;
+
+/** Type of in_int_raw_ch3 register
+ *  RX CH3  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch3_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch3_int_raw:1;
+        /** in_suc_eof_ch3_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch3_int_raw:1;
+        /** in_err_eof_ch3_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch3_int_raw:1;
+        /** in_dscr_err_ch3_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 1.
+         */
+        uint32_t in_dscr_err_ch3_int_raw:1;
+        /** infifo_ovf_l1_ch3_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch3_int_raw:1;
+        /** infifo_udf_l1_ch3_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch3_int_raw:1;
+        /** infifo_ovf_l2_ch3_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch3_int_raw:1;
+        /** infifo_udf_l2_ch3_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch3_int_raw:1;
+        /** in_dscr_empty_ch3_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch3_int_raw:1;
+        /** in_dscr_task_ovf_ch3_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch3_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch3_reg_t;
+
+/** Type of in_int_ena_ch3 register
+ *  RX CH3  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch3_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch3_int_ena:1;
+        /** in_suc_eof_ch3_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch3_int_ena:1;
+        /** in_err_eof_ch3_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch3_int_ena:1;
+        /** in_dscr_err_ch3_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch3_int_ena:1;
+        /** infifo_ovf_l1_ch3_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch3_int_ena:1;
+        /** infifo_udf_l1_ch3_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch3_int_ena:1;
+        /** infifo_ovf_l2_ch3_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch3_int_ena:1;
+        /** infifo_udf_l2_ch3_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch3_int_ena:1;
+        /** in_dscr_empty_ch3_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch3_int_ena:1;
+        /** in_dscr_task_ovf_ch3_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch3_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch3_reg_t;
+
+/** Type of in_int_st_ch3 register
+ *  RX CH3  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch3_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch3_int_st:1;
+        /** in_suc_eof_ch3_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch3_int_st:1;
+        /** in_err_eof_ch3_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch3_int_st:1;
+        /** in_dscr_err_ch3_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch3_int_st:1;
+        /** infifo_ovf_l1_ch3_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch3_int_st:1;
+        /** infifo_udf_l1_ch3_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch3_int_st:1;
+        /** infifo_ovf_l2_ch3_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch3_int_st:1;
+        /** infifo_udf_l2_ch3_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch3_int_st:1;
+        /** in_dscr_empty_ch3_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch3_int_st:1;
+        /** in_dscr_task_ovf_ch3_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch3_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch3_reg_t;
+
+/** Type of in_int_clr_ch3 register
+ *  RX CH3  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch3_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch3_int_clr:1;
+        /** in_suc_eof_ch3_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch3_int_clr:1;
+        /** in_err_eof_ch3_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch3_int_clr:1;
+        /** in_dscr_err_ch3_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch3_int_clr:1;
+        /** infifo_ovf_l1_ch3_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch3_int_clr:1;
+        /** infifo_udf_l1_ch3_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch3_int_clr:1;
+        /** infifo_ovf_l2_ch3_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch3_int_clr:1;
+        /** infifo_udf_l2_ch3_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch3_int_clr:1;
+        /** in_dscr_empty_ch3_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch3_int_clr:1;
+        /** in_dscr_task_ovf_ch3_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch3_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch3_reg_t;
+
+/** Type of in_int_raw_ch4 register
+ *  RX CH4  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch4_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch4_int_raw:1;
+        /** in_suc_eof_ch4_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch4_int_raw:1;
+        /** in_err_eof_ch4_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_ch4_int_raw:1;
+        /** in_dscr_err_ch4_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 1.
+         */
+        uint32_t in_dscr_err_ch4_int_raw:1;
+        /** infifo_ovf_l1_ch4_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch4_int_raw:1;
+        /** infifo_udf_l1_ch4_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch4_int_raw:1;
+        /** infifo_ovf_l2_ch4_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_ch4_int_raw:1;
+        /** infifo_udf_l2_ch4_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_ch4_int_raw:1;
+        /** in_dscr_empty_ch4_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_ch4_int_raw:1;
+        /** in_dscr_task_ovf_ch4_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_ch4_int_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch4_reg_t;
+
+/** Type of in_int_ena_ch4 register
+ *  RX CH4  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch4_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch4_int_ena:1;
+        /** in_suc_eof_ch4_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch4_int_ena:1;
+        /** in_err_eof_ch4_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch4_int_ena:1;
+        /** in_dscr_err_ch4_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch4_int_ena:1;
+        /** infifo_ovf_l1_ch4_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch4_int_ena:1;
+        /** infifo_udf_l1_ch4_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch4_int_ena:1;
+        /** infifo_ovf_l2_ch4_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch4_int_ena:1;
+        /** infifo_udf_l2_ch4_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch4_int_ena:1;
+        /** in_dscr_empty_ch4_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch4_int_ena:1;
+        /** in_dscr_task_ovf_ch4_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch4_int_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch4_reg_t;
+
+/** Type of in_int_st_ch4 register
+ *  RX CH4  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch4_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch4_int_st:1;
+        /** in_suc_eof_ch4_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch4_int_st:1;
+        /** in_err_eof_ch4_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch4_int_st:1;
+        /** in_dscr_err_ch4_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch4_int_st:1;
+        /** infifo_ovf_l1_ch4_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch4_int_st:1;
+        /** infifo_udf_l1_ch4_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch4_int_st:1;
+        /** infifo_ovf_l2_ch4_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch4_int_st:1;
+        /** infifo_udf_l2_ch4_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch4_int_st:1;
+        /** in_dscr_empty_ch4_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch4_int_st:1;
+        /** in_dscr_task_ovf_ch4_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch4_int_st:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch4_reg_t;
+
+/** Type of in_int_clr_ch4 register
+ *  RX CH4  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch4_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch4_int_clr:1;
+        /** in_suc_eof_ch4_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch4_int_clr:1;
+        /** in_err_eof_ch4_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_ch4_int_clr:1;
+        /** in_dscr_err_ch4_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_ch4_int_clr:1;
+        /** infifo_ovf_l1_ch4_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch4_int_clr:1;
+        /** infifo_udf_l1_ch4_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch4_int_clr:1;
+        /** infifo_ovf_l2_ch4_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_ch4_int_clr:1;
+        /** infifo_udf_l2_ch4_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_ch4_int_clr:1;
+        /** in_dscr_empty_ch4_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_ch4_int_clr:1;
+        /** in_dscr_task_ovf_ch4_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_ch4_int_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch4_reg_t;
+
+/** Type of in_int_raw_ch5 register
+ *  RX CH5  interrupt raw register
+ */
+typedef union {
+    struct {
+        /** in_done_ch5_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 1.
+         */
+        uint32_t in_done_ch5_int_raw:1;
+        /** in_suc_eof_ch5_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 1.
+         */
+        uint32_t in_suc_eof_ch5_int_raw:1;
+        /** infifo_ovf_l1_ch5_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_ch5_int_raw:1;
+        /** infifo_udf_l1_ch5_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_ch5_int_raw:1;
+        /** fetch_mb_col_cnt_ovf_ch5_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t fetch_mb_col_cnt_ovf_ch5_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_in_int_raw_ch5_reg_t;
+
+/** Type of in_int_ena_ch5 register
+ *  RX CH5  interrupt ena register
+ */
+typedef union {
+    struct {
+        /** in_done_ch5_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch5_int_ena:1;
+        /** in_suc_eof_ch5_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch5_int_ena:1;
+        /** infifo_ovf_l1_ch5_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch5_int_ena:1;
+        /** infifo_udf_l1_ch5_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch5_int_ena:1;
+        /** fetch_mb_col_cnt_ovf_ch5_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t fetch_mb_col_cnt_ovf_ch5_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_in_int_ena_ch5_reg_t;
+
+/** Type of in_int_st_ch5 register
+ *  RX CH5  interrupt st register
+ */
+typedef union {
+    struct {
+        /** in_done_ch5_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch5_int_st:1;
+        /** in_suc_eof_ch5_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch5_int_st:1;
+        /** infifo_ovf_l1_ch5_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch5_int_st:1;
+        /** infifo_udf_l1_ch5_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch5_int_st:1;
+        /** fetch_mb_col_cnt_ovf_ch5_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t fetch_mb_col_cnt_ovf_ch5_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_in_int_st_ch5_reg_t;
+
+/** Type of in_int_clr_ch5 register
+ *  RX CH5  interrupt clr register
+ */
+typedef union {
+    struct {
+        /** in_done_ch5_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_ch5_int_clr:1;
+        /** in_suc_eof_ch5_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_ch5_int_clr:1;
+        /** infifo_ovf_l1_ch5_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_ch5_int_clr:1;
+        /** infifo_udf_l1_ch5_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_ch5_int_clr:1;
+        /** fetch_mb_col_cnt_ovf_ch5_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t fetch_mb_col_cnt_ovf_ch5_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_dma_in_int_clr_ch5_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of outfifo_status_ch0 register
+ *  TX CH0 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch0 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l2_ch0:1;
+        /** outfifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l2_ch0:1;
+        /** outfifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l2_ch0:4;
+        /** outfifo_full_l1_ch0 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l1_ch0:1;
+        /** outfifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l1_ch0:1;
+        /** outfifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l1_ch0:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch0 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l3_ch0:1;
+        /** outfifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l3_ch0:1;
+        /** outfifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l3_ch0:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch0_reg_t;
+
+/** Type of out_state_ch0 register
+ *  TX CH0 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch0:18;
+        /** out_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch0:2;
+        /** out_state_ch0 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch0:4;
+        /** out_reset_avail_ch0 : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_ch0:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch0_reg_t;
+
+/** Type of out_eof_des_addr_ch0 register
+ *  TX CH0 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch0_reg_t;
+
+/** Type of out_dscr_ch0 register
+ *  TX CH0 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch0_reg_t;
+
+/** Type of out_dscr_bf0_ch0 register
+ *  TX CH0 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch0_reg_t;
+
+/** Type of out_dscr_bf1_ch0 register
+ *  TX CH0 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch0_reg_t;
+
+/** Type of out_ro_status_ch0 register
+ *  TX CH0 reorder status register
+ */
+typedef union {
+    struct {
+        /** outfifo_ro_cnt_ch0 : RO; bitpos: [1:0]; default: 0;
+         *  The register stores the 8byte number of the data in reorder Tx FIFO for channel 0.
+         */
+        uint32_t outfifo_ro_cnt_ch0:2;
+        uint32_t reserved_2:4;
+        /** out_ro_wr_state_ch0 : RO; bitpos: [7:6]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t out_ro_wr_state_ch0:2;
+        /** out_ro_rd_state_ch0 : RO; bitpos: [9:8]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t out_ro_rd_state_ch0:2;
+        /** out_pixel_byte_ch0 : RO; bitpos: [13:10]; default: 2;
+         *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t out_pixel_byte_ch0:4;
+        /** out_burst_block_num_ch0 : RO; bitpos: [17:14]; default: 0;
+         *  the number of macro blocks contained in a burst of data at TX channel
+         */
+        uint32_t out_burst_block_num_ch0:4;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} h264_dma_out_ro_status_ch0_reg_t;
+
+/** Type of outfifo_status_ch1 register
+ *  TX CH1 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch1 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t outfifo_full_l2_ch1:1;
+        /** outfifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t outfifo_empty_l2_ch1:1;
+        /** outfifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t outfifo_cnt_l2_ch1:4;
+        /** outfifo_full_l1_ch1 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t outfifo_full_l1_ch1:1;
+        /** outfifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t outfifo_empty_l1_ch1:1;
+        /** outfifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t outfifo_cnt_l1_ch1:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch1 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t outfifo_full_l3_ch1:1;
+        /** outfifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t outfifo_empty_l3_ch1:1;
+        /** outfifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t outfifo_cnt_l3_ch1:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch1_reg_t;
+
+/** Type of out_state_ch1 register
+ *  TX CH1 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch1:18;
+        /** out_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch1:2;
+        /** out_state_ch1 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch1:4;
+        /** out_reset_avail_ch1 : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_ch1:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch1_reg_t;
+
+/** Type of out_eof_des_addr_ch1 register
+ *  TX CH1 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch1_reg_t;
+
+/** Type of out_dscr_ch1 register
+ *  TX CH1 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch1_reg_t;
+
+/** Type of out_dscr_bf0_ch1 register
+ *  TX CH1 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch1_reg_t;
+
+/** Type of out_dscr_bf1_ch1 register
+ *  TX CH1 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch1_reg_t;
+
+/** Type of outfifo_status_ch2 register
+ *  TX CH2 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch2 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l2_ch2:1;
+        /** outfifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l2_ch2:1;
+        /** outfifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l2_ch2:4;
+        /** outfifo_full_l1_ch2 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l1_ch2:1;
+        /** outfifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l1_ch2:1;
+        /** outfifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l1_ch2:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch2 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l3_ch2:1;
+        /** outfifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l3_ch2:1;
+        /** outfifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l3_ch2:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch2_reg_t;
+
+/** Type of out_state_ch2 register
+ *  TX CH2 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch2:18;
+        /** out_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch2:2;
+        /** out_state_ch2 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch2:4;
+        /** out_reset_avail_ch2 : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_ch2:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch2_reg_t;
+
+/** Type of out_eof_des_addr_ch2 register
+ *  TX CH2 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch2_reg_t;
+
+/** Type of out_dscr_ch2 register
+ *  TX CH2 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch2_reg_t;
+
+/** Type of out_dscr_bf0_ch2 register
+ *  TX CH2 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch2_reg_t;
+
+/** Type of out_dscr_bf1_ch2 register
+ *  TX CH2 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch2_reg_t;
+
+/** Type of outfifo_status_ch3 register
+ *  TX CH3 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch3 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l2_ch3:1;
+        /** outfifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l2_ch3:1;
+        /** outfifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l2_ch3:4;
+        /** outfifo_full_l1_ch3 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l1_ch3:1;
+        /** outfifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l1_ch3:1;
+        /** outfifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l1_ch3:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch3 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l3_ch3:1;
+        /** outfifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l3_ch3:1;
+        /** outfifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l3_ch3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch3_reg_t;
+
+/** Type of out_state_ch3 register
+ *  TX CH3 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch3:18;
+        /** out_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch3:2;
+        /** out_state_ch3 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch3:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch3_reg_t;
+
+/** Type of out_eof_des_addr_ch3 register
+ *  TX CH3 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch3_reg_t;
+
+/** Type of out_dscr_ch3 register
+ *  TX CH3 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch3_reg_t;
+
+/** Type of out_dscr_bf0_ch3 register
+ *  TX CH3 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch3_reg_t;
+
+/** Type of out_dscr_bf1_ch3 register
+ *  TX CH3 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch3_reg_t;
+
+/** Type of outfifo_status_ch4 register
+ *  TX CH4 outfifo status register
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_ch4 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l2_ch4:1;
+        /** outfifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l2_ch4:1;
+        /** outfifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l2_ch4:4;
+        /** outfifo_full_l1_ch4 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l1_ch4:1;
+        /** outfifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l1_ch4:1;
+        /** outfifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l1_ch4:5;
+        uint32_t reserved_13:3;
+        /** outfifo_full_l3_ch4 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 2.
+         */
+        uint32_t outfifo_full_l3_ch4:1;
+        /** outfifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 2.
+         */
+        uint32_t outfifo_empty_l3_ch4:1;
+        /** outfifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 2.
+         */
+        uint32_t outfifo_cnt_l3_ch4:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_outfifo_status_ch4_reg_t;
+
+/** Type of out_state_ch4 register
+ *  TX CH4 state register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_ch4:18;
+        /** out_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_ch4:2;
+        /** out_state_ch4 : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_ch4:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_state_ch4_reg_t;
+
+/** Type of out_eof_des_addr_ch4 register
+ *  TX CH4 eof des addr register
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_eof_des_addr_ch4_reg_t;
+
+/** Type of out_dscr_ch4 register
+ *  TX CH4 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_ch4_reg_t;
+
+/** Type of out_dscr_bf0_ch4 register
+ *  TX CH4 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf0_ch4_reg_t;
+
+/** Type of out_dscr_bf1_ch4 register
+ *  TX CH4 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_dscr_bf1_ch4_reg_t;
+
+/** Type of infifo_status_ch0 register
+ *  RX CH0 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch0 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch0:1;
+        /** infifo_empty_l2_ch0 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch0:1;
+        /** infifo_cnt_l2_ch0 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch0:4;
+        /** infifo_full_l1_ch0 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l1_ch0:1;
+        /** infifo_empty_l1_ch0 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l1_ch0:1;
+        /** infifo_cnt_l1_ch0 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l1_ch0:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch0 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t infifo_full_l3_ch0:1;
+        /** infifo_empty_l3_ch0 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t infifo_empty_l3_ch0:1;
+        /** infifo_cnt_l3_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the 8byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t infifo_cnt_l3_ch0:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch0_reg_t;
+
+/** Type of in_state_ch0 register
+ *  RX CH0 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch0 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch0:18;
+        /** in_dscr_state_ch0 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch0:2;
+        /** in_state_ch0 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch0:3;
+        /** in_reset_avail_ch0 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch0:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch0_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch0 register
+ *  RX CH0 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch0_reg_t;
+
+/** Type of in_err_eof_des_addr_ch0 register
+ *  RX CH0 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch0_reg_t;
+
+/** Type of in_dscr_ch0 register
+ *  RX CH0 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch0_reg_t;
+
+/** Type of in_dscr_bf0_ch0 register
+ *  RX CH0 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch0_reg_t;
+
+/** Type of in_dscr_bf1_ch0 register
+ *  RX CH0 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch0_reg_t;
+
+/** Type of infifo_status_ch1 register
+ *  RX CH1 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch1 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch1:1;
+        /** infifo_empty_l2_ch1 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch1:1;
+        /** infifo_cnt_l2_ch1 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch1:4;
+        /** infifo_full_l1_ch1 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch1:1;
+        /** infifo_empty_l1_ch1 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch1:1;
+        /** infifo_cnt_l1_ch1 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch1:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch1 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l3_ch1:1;
+        /** infifo_empty_l3_ch1 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l3_ch1:1;
+        /** infifo_cnt_l3_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l3_ch1:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch1_reg_t;
+
+/** Type of in_state_ch1 register
+ *  RX CH1 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch1 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch1:18;
+        /** in_dscr_state_ch1 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch1:2;
+        /** in_state_ch1 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch1:3;
+        /** in_reset_avail_ch1 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch1:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch1_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch1 register
+ *  RX CH1 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch1_reg_t;
+
+/** Type of in_err_eof_des_addr_ch1 register
+ *  RX CH1 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch1_reg_t;
+
+/** Type of in_dscr_ch1 register
+ *  RX CH1 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch1_reg_t;
+
+/** Type of in_dscr_bf0_ch1 register
+ *  RX CH1 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch1_reg_t;
+
+/** Type of in_dscr_bf1_ch1 register
+ *  RX CH1 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch1_reg_t;
+
+/** Type of infifo_status_ch2 register
+ *  RX CH2 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch2 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch2:1;
+        /** infifo_empty_l2_ch2 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch2:1;
+        /** infifo_cnt_l2_ch2 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch2:4;
+        /** infifo_full_l1_ch2 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch2:1;
+        /** infifo_empty_l1_ch2 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch2:1;
+        /** infifo_cnt_l1_ch2 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch2:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch2 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l3_ch2:1;
+        /** infifo_empty_l3_ch2 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l3_ch2:1;
+        /** infifo_cnt_l3_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l3_ch2:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch2_reg_t;
+
+/** Type of in_state_ch2 register
+ *  RX CH2 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch2 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch2:18;
+        /** in_dscr_state_ch2 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch2:2;
+        /** in_state_ch2 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch2:3;
+        /** in_reset_avail_ch2 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch2:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch2_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch2 register
+ *  RX CH2 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch2_reg_t;
+
+/** Type of in_err_eof_des_addr_ch2 register
+ *  RX CH2 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch2_reg_t;
+
+/** Type of in_dscr_ch2 register
+ *  RX CH2 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch2_reg_t;
+
+/** Type of in_dscr_bf0_ch2 register
+ *  RX CH2 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch2_reg_t;
+
+/** Type of in_dscr_bf1_ch2 register
+ *  RX CH2 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch2_reg_t;
+
+/** Type of infifo_status_ch3 register
+ *  RX CH3 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch3 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch3:1;
+        /** infifo_empty_l2_ch3 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch3:1;
+        /** infifo_cnt_l2_ch3 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch3:4;
+        /** infifo_full_l1_ch3 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch3:1;
+        /** infifo_empty_l1_ch3 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch3:1;
+        /** infifo_cnt_l1_ch3 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch3:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch3 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l3_ch3:1;
+        /** infifo_empty_l3_ch3 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l3_ch3:1;
+        /** infifo_cnt_l3_ch3 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l3_ch3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch3_reg_t;
+
+/** Type of in_state_ch3 register
+ *  RX CH3 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch3 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch3:18;
+        /** in_dscr_state_ch3 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch3:2;
+        /** in_state_ch3 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch3:3;
+        /** in_reset_avail_ch3 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch3:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch3_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch3 register
+ *  RX CH3 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch3_reg_t;
+
+/** Type of in_err_eof_des_addr_ch3 register
+ *  RX CH3 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch3_reg_t;
+
+/** Type of in_dscr_ch3 register
+ *  RX CH3 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch3_reg_t;
+
+/** Type of in_dscr_bf0_ch3 register
+ *  RX CH3 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch3_reg_t;
+
+/** Type of in_dscr_bf1_ch3 register
+ *  RX CH3 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch3_reg_t;
+
+/** Type of infifo_status_ch4 register
+ *  RX CH4 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_ch4 : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_ch4:1;
+        /** infifo_empty_l2_ch4 : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_ch4:1;
+        /** infifo_cnt_l2_ch4 : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_ch4:4;
+        /** infifo_full_l1_ch4 : RO; bitpos: [6]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch4:1;
+        /** infifo_empty_l1_ch4 : RO; bitpos: [7]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch4:1;
+        /** infifo_cnt_l1_ch4 : RO; bitpos: [12:8]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch4:5;
+        uint32_t reserved_13:3;
+        /** infifo_full_l3_ch4 : RO; bitpos: [16]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l3_ch4:1;
+        /** infifo_empty_l3_ch4 : RO; bitpos: [17]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l3_ch4:1;
+        /** infifo_cnt_l3_ch4 : RO; bitpos: [19:18]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l3_ch4:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch4_reg_t;
+
+/** Type of in_state_ch4 register
+ *  RX CH4 state register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_ch4 : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_ch4:18;
+        /** in_dscr_state_ch4 : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t in_dscr_state_ch4:2;
+        /** in_state_ch4 : RO; bitpos: [22:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch4:3;
+        /** in_reset_avail_ch4 : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch4:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch4_reg_t;
+
+/** Type of in_suc_eof_des_addr_ch4 register
+ *  RX CH4 eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_suc_eof_des_addr_ch4_reg_t;
+
+/** Type of in_err_eof_des_addr_ch4 register
+ *  RX CH4 err eof des addr register
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_err_eof_des_addr_ch4_reg_t;
+
+/** Type of in_dscr_ch4 register
+ *  RX CH4 next dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_ch4_reg_t;
+
+/** Type of in_dscr_bf0_ch4 register
+ *  RX CH4 last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf0_ch4_reg_t;
+
+/** Type of in_dscr_bf1_ch4 register
+ *  RX CH4 second-to-last dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_dscr_bf1_ch4_reg_t;
+
+/** Type of infifo_status_ch5 register
+ *  RX CH5 INFIFO status register
+ */
+typedef union {
+    struct {
+        /** infifo_full_l1_ch5 : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 1.
+         */
+        uint32_t infifo_full_l1_ch5:1;
+        /** infifo_empty_l1_ch5 : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 1.
+         */
+        uint32_t infifo_empty_l1_ch5:1;
+        /** infifo_cnt_l1_ch5 : RO; bitpos: [6:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 1.
+         */
+        uint32_t infifo_cnt_l1_ch5:5;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_infifo_status_ch5_reg_t;
+
+/** Type of in_state_ch5 register
+ *  RX CH5 state register
+ */
+typedef union {
+    struct {
+        /** in_state_ch5 : RO; bitpos: [2:0]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t in_state_ch5:3;
+        /** in_reset_avail_ch5 : RO; bitpos: [3]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_ch5:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_state_ch5_reg_t;
+
+
+/** Group: out_link addr register */
+/** Type of out_link_addr_ch0 register
+ *  TX CH0 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch0_reg_t;
+
+
+/** Group: tx ch0 arb register */
+/** Type of out_arb_ch0 register
+ *  TX CH0 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch0:4;
+        /** exter_out_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_out_arb_priority_ch0:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch0_reg_t;
+
+
+/** Group: TX CH0 test mode register */
+/** Type of out_mode_enable_ch0 register
+ *  tx CH0 mode enable register
+ */
+typedef union {
+    struct {
+        /** out_test_mode_enable_ch0 : R/W; bitpos: [0]; default: 0;
+         *  tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test
+         *  mode
+         */
+        uint32_t out_test_mode_enable_ch0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} h264_dma_out_mode_enable_ch0_reg_t;
+
+/** Type of out_mode_yuv_ch0 register
+ *  tx CH0 test mode yuv value register
+ */
+typedef union {
+    struct {
+        /** out_test_y_value_ch0 : R/W; bitpos: [7:0]; default: 0;
+         *  tx CH0 test mode y value
+         */
+        uint32_t out_test_y_value_ch0:8;
+        /** out_test_u_value_ch0 : R/W; bitpos: [15:8]; default: 0;
+         *  tx CH0 test mode u value
+         */
+        uint32_t out_test_u_value_ch0:8;
+        /** out_test_v_value_ch0 : R/W; bitpos: [23:16]; default: 0;
+         *  tx CH0 test mode v value
+         */
+        uint32_t out_test_v_value_ch0:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_dma_out_mode_yuv_ch0_reg_t;
+
+
+/** Group: ETM config register */
+/** Type of out_etm_conf_ch0 register
+ *  TX CH0 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch0:1;
+        /** out_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch0:1;
+        /** out_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch0:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch0_reg_t;
+
+
+/** Group: TX CH0 debug info */
+/** Type of out_buf_len_ch0 register
+ *  tx CH0 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch0 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch0:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch0_reg_t;
+
+/** Type of out_fifo_bcnt_ch0 register
+ *  tx CH0 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch0 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch0:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch0_reg_t;
+
+/** Type of out_push_bytecnt_ch0 register
+ *  tx CH0 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch0 : RO; bitpos: [7:0]; default: 255;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch0_reg_t;
+
+/** Type of out_xaddr_ch0 register
+ *  tx CH0 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch0_reg_t;
+
+
+/** Group: TX CH1 config0 register */
+/** Type of out_conf0_ch1 register
+ *  TX CH1 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch1:1;
+        /** out_eof_mode_ch1 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch1:1;
+        /** outdscr_burst_en_ch1 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch1:1;
+        /** out_ecc_aes_en_ch1 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch1:1;
+        /** out_check_owner_ch1 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch1:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch1 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 1. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 64 bytes
+         */
+        uint32_t out_mem_burst_length_ch1:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch1 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch1:1;
+        uint32_t reserved_13:11;
+        /** out_rst_ch1 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_ch1:1;
+        /** out_cmd_disable_ch1 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_ch1:1;
+        /** out_arb_weight_opt_dis_ch1 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch1:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch1_reg_t;
+
+
+/** Group: TX CH1 out_link dscr addr register */
+/** Type of out_link_addr_ch1 register
+ *  TX CH1 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch1_reg_t;
+
+
+/** Group: TX CH1 arb register */
+/** Type of out_arb_ch1 register
+ *  TX CH1 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch1:4;
+        uint32_t reserved_4:2;
+        /** inter_out_arb_priority_ch1 : R/W; bitpos: [6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_out_arb_priority_ch1:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch1_reg_t;
+
+
+/** Group: TX CH1 ETM config register */
+/** Type of out_etm_conf_ch1 register
+ *  TX CH1 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch1:1;
+        /** out_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch1:1;
+        /** out_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch1:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch1_reg_t;
+
+
+/** Group: TX CH1 debug info */
+/** Type of out_buf_len_ch1 register
+ *  tx CH1 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch1 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch1:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch1_reg_t;
+
+/** Type of out_fifo_bcnt_ch1 register
+ *  tx CH1 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch1 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch1:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch1_reg_t;
+
+/** Type of out_push_bytecnt_ch1 register
+ *  tx CH1 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch1 : RO; bitpos: [7:0]; default: 255;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch1_reg_t;
+
+/** Type of out_xaddr_ch1 register
+ *  tx CH1 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch1_reg_t;
+
+
+/** Group: TX CH2 config0 register */
+/** Type of out_conf0_ch2 register
+ *  TX CH2 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch2:1;
+        /** out_eof_mode_ch2 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch2:1;
+        /** outdscr_burst_en_ch2 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch2:1;
+        /** out_ecc_aes_en_ch2 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch2:1;
+        /** out_check_owner_ch2 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch2:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch2 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 2. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_ch2:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch2 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch2:1;
+        uint32_t reserved_13:11;
+        /** out_rst_ch2 : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_ch2:1;
+        /** out_cmd_disable_ch2 : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_ch2:1;
+        /** out_arb_weight_opt_dis_ch2 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch2:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch2_reg_t;
+
+
+/** Group: TX CH2 out_link dscr addr register */
+/** Type of out_link_addr_ch2 register
+ *  TX CH2 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch2_reg_t;
+
+
+/** Group: TX CH2 arb register */
+/** Type of out_arb_ch2 register
+ *  TX CH2 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch2:4;
+        uint32_t reserved_4:2;
+        /** inter_out_arb_priority_ch2 : R/W; bitpos: [6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_out_arb_priority_ch2:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch2_reg_t;
+
+
+/** Group: TX CH2 ETM config register */
+/** Type of out_etm_conf_ch2 register
+ *  TX CH2 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch2:1;
+        /** out_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch2:1;
+        /** out_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch2:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch2_reg_t;
+
+
+/** Group: TX CH2 debug info */
+/** Type of out_buf_len_ch2 register
+ *  tx CH2 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch2 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch2:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch2_reg_t;
+
+/** Type of out_fifo_bcnt_ch2 register
+ *  tx CH2 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch2 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch2:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch2_reg_t;
+
+/** Type of out_push_bytecnt_ch2 register
+ *  tx CH2 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch2 : RO; bitpos: [7:0]; default: 255;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch2_reg_t;
+
+/** Type of out_xaddr_ch2 register
+ *  tx CH2 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch2_reg_t;
+
+
+/** Group: TX CH3 config0 register */
+/** Type of out_conf0_ch3 register
+ *  TX CH3 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch3 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch3:1;
+        /** out_eof_mode_ch3 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch3:1;
+        /** outdscr_burst_en_ch3 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch3:1;
+        /** out_ecc_aes_en_ch3 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch3:1;
+        /** out_check_owner_ch3 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch3:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch3 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 3. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_ch3:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch3 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch3:1;
+        uint32_t reserved_13:13;
+        /** out_arb_weight_opt_dis_ch3 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch3:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch3_reg_t;
+
+
+/** Group: TX CH3 out_link dscr addr register */
+/** Type of out_link_addr_ch3 register
+ *  TX CH3 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch3_reg_t;
+
+
+/** Group: TX CH3 arb register */
+/** Type of out_arb_ch3 register
+ *  TX CH3 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch3:4;
+        /** exter_out_arb_priority_ch3 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_out_arb_priority_ch3:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch3_reg_t;
+
+
+/** Group: TX CH3 ETM config register */
+/** Type of out_etm_conf_ch3 register
+ *  TX CH3 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch3 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch3:1;
+        /** out_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch3:1;
+        /** out_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch3:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch3_reg_t;
+
+
+/** Group: TX CH3 debug info */
+/** Type of out_buf_len_ch3 register
+ *  tx CH3 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch3 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch3:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch3_reg_t;
+
+/** Type of out_fifo_bcnt_ch3 register
+ *  tx CH3 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch3 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch3:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch3_reg_t;
+
+/** Type of out_push_bytecnt_ch3 register
+ *  tx CH3 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch3 : RO; bitpos: [7:0]; default: 63;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch3_reg_t;
+
+/** Type of out_xaddr_ch3 register
+ *  tx CH3 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch3_reg_t;
+
+/** Type of out_block_buf_len_ch3 register
+ *  tx CH3 block buf len register
+ */
+typedef union {
+    struct {
+        /** out_block_buf_len_ch3 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_block_buf_len_ch3:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_block_buf_len_ch3_reg_t;
+
+
+/** Group: TX CH4 config0 register */
+/** Type of out_conf0_ch4 register
+ *  TX CH4 config0 register
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_ch4 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_ch4:1;
+        /** out_eof_mode_ch4 : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_ch4:1;
+        /** outdscr_burst_en_ch4 : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_ch4:1;
+        /** out_ecc_aes_en_ch4 : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_ch4:1;
+        /** out_check_owner_ch4 : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_ch4:1;
+        uint32_t reserved_5:1;
+        /** out_mem_burst_length_ch4 : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 4. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_ch4:3;
+        uint32_t reserved_9:3;
+        /** out_page_bound_en_ch4 : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_ch4:1;
+        uint32_t reserved_13:13;
+        /** out_arb_weight_opt_dis_ch4 : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_ch4:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_dma_out_conf0_ch4_reg_t;
+
+
+/** Group: TX CH4 out_link dscr addr register */
+/** Type of out_link_addr_ch4 register
+ *  TX CH4 out_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** outlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_link_addr_ch4_reg_t;
+
+
+/** Group: TX CH4 arb register */
+/** Type of out_arb_ch4 register
+ *  TX CH4 arb register
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_ch4:4;
+        /** exter_out_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_out_arb_priority_ch4:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} h264_dma_out_arb_ch4_reg_t;
+
+
+/** Group: TX CH4 ETM config register */
+/** Type of out_etm_conf_ch4 register
+ *  TX CH4 ETM config register
+ */
+typedef union {
+    struct {
+        /** out_etm_en_ch4 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t out_etm_en_ch4:1;
+        /** out_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t out_etm_loop_en_ch4:1;
+        /** out_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t out_dscr_task_mak_ch4:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_out_etm_conf_ch4_reg_t;
+
+
+/** Group: TX CH4 debug info */
+/** Type of out_buf_len_ch4 register
+ *  tx CH4 buf len register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_buf_len_hb_ch4 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_buf_len_hb_ch4:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_buf_len_ch4_reg_t;
+
+/** Type of out_fifo_bcnt_ch4 register
+ *  tx CH4 fifo byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_outfifo_bcnt_ch4 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_outfifo_bcnt_ch4:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_out_fifo_bcnt_ch4_reg_t;
+
+/** Type of out_push_bytecnt_ch4 register
+ *  tx CH4 push byte cnt register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_push_bytecnt_ch4 : RO; bitpos: [7:0]; default: 63;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_push_bytecnt_ch4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_out_push_bytecnt_ch4_reg_t;
+
+/** Type of out_xaddr_ch4 register
+ *  tx CH4 xaddr register
+ */
+typedef union {
+    struct {
+        /** out_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_cmdfifo_xaddr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_out_xaddr_ch4_reg_t;
+
+/** Type of out_block_buf_len_ch4 register
+ *  tx CH4 block buf len register
+ */
+typedef union {
+    struct {
+        /** out_block_buf_len_ch4 : RO; bitpos: [27:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t out_block_buf_len_ch4:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_out_block_buf_len_ch4_reg_t;
+
+
+/** Group: RX CH0 in_link dscr addr register */
+/** Type of in_link_addr_ch0 register
+ *  RX CH0 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch0 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch0_reg_t;
+
+
+/** Group: RX CH0 arb register */
+/** Type of in_arb_ch0 register
+ *  RX CH0 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch0 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch0:4;
+        /** exter_in_arb_priority_ch0 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_in_arb_priority_ch0:2;
+        /** inter_in_arb_priority_ch0 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch0:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch0_reg_t;
+
+
+/** Group: RX CH0 ETM config register */
+/** Type of in_etm_conf_ch0 register
+ *  RX CH0 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch0:1;
+        /** in_etm_loop_en_ch0 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch0:1;
+        /** in_dscr_task_mak_ch0 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch0:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch0_reg_t;
+
+
+/** Group: RX CH0 debug info */
+/** Type of in_fifo_cnt_ch0 register
+ *  rx CH0 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch0 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch0:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch0_reg_t;
+
+/** Type of in_pop_data_cnt_ch0 register
+ *  rx CH0 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch0 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch0_reg_t;
+
+/** Type of in_xaddr_ch0 register
+ *  rx CH0 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch0 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch0:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch0_reg_t;
+
+/** Type of in_buf_hb_rcv_ch0 register
+ *  rx CH0 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch0 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch0:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch0_reg_t;
+
+
+/** Group: RX CH1 in_link dscr addr register */
+/** Type of in_link_addr_ch1 register
+ *  RX CH1 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch1 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch1_reg_t;
+
+
+/** Group: RX CH1 arb register */
+/** Type of in_arb_ch1 register
+ *  RX CH1 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch1 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch1:4;
+        /** exter_in_arb_priority_ch1 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_in_arb_priority_ch1:2;
+        /** inter_in_arb_priority_ch1 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch1:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch1_reg_t;
+
+
+/** Group: RX CH1 ETM config register */
+/** Type of in_etm_conf_ch1 register
+ *  RX CH1 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch1 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch1:1;
+        /** in_etm_loop_en_ch1 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch1:1;
+        /** in_dscr_task_mak_ch1 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch1:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch1_reg_t;
+
+
+/** Group: RX CH1 debug info */
+/** Type of in_fifo_cnt_ch1 register
+ *  rx CH1 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch1 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch1:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch1_reg_t;
+
+/** Type of in_pop_data_cnt_ch1 register
+ *  rx CH1 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch1 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch1_reg_t;
+
+/** Type of in_xaddr_ch1 register
+ *  rx CH1 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch1 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch1:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch1_reg_t;
+
+/** Type of in_buf_hb_rcv_ch1 register
+ *  rx CH1 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch1 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch1:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch1_reg_t;
+
+
+/** Group: RX CH2 in_link dscr addr register */
+/** Type of in_link_addr_ch2 register
+ *  RX CH2 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch2 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch2_reg_t;
+
+
+/** Group: RX CH2 arb register */
+/** Type of in_arb_ch2 register
+ *  RX CH2 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch2 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch2:4;
+        uint32_t reserved_4:2;
+        /** inter_in_arb_priority_ch2 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch2:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch2_reg_t;
+
+
+/** Group: RX CH2 ETM config register */
+/** Type of in_etm_conf_ch2 register
+ *  RX CH2 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch2 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch2:1;
+        /** in_etm_loop_en_ch2 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch2:1;
+        /** in_dscr_task_mak_ch2 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch2:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch2_reg_t;
+
+
+/** Group: RX CH2 debug info */
+/** Type of in_fifo_cnt_ch2 register
+ *  rx CH2 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch2 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch2:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch2_reg_t;
+
+/** Type of in_pop_data_cnt_ch2 register
+ *  rx CH2 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch2 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch2_reg_t;
+
+/** Type of in_xaddr_ch2 register
+ *  rx CH2 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch2 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch2:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch2_reg_t;
+
+/** Type of in_buf_hb_rcv_ch2 register
+ *  rx CH2 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch2 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch2:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch2_reg_t;
+
+
+/** Group: RX CH3 in_link dscr addr register */
+/** Type of in_link_addr_ch3 register
+ *  RX CH3 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch3 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch3_reg_t;
+
+
+/** Group: RX CH3 arb register */
+/** Type of in_arb_ch3 register
+ *  RX CH3 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch3 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch3:4;
+        uint32_t reserved_4:2;
+        /** inter_in_arb_priority_ch3 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch3:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch3_reg_t;
+
+
+/** Group: RX CH3 ETM config register */
+/** Type of in_etm_conf_ch3 register
+ *  RX CH3 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch3 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch3:1;
+        /** in_etm_loop_en_ch3 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch3:1;
+        /** in_dscr_task_mak_ch3 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch3:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch3_reg_t;
+
+
+/** Group: RX CH3 debug info */
+/** Type of in_fifo_cnt_ch3 register
+ *  rx CH3 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch3 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch3:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch3_reg_t;
+
+/** Type of in_pop_data_cnt_ch3 register
+ *  rx CH3 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch3 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch3_reg_t;
+
+/** Type of in_xaddr_ch3 register
+ *  rx CH3 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch3 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch3:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch3_reg_t;
+
+/** Type of in_buf_hb_rcv_ch3 register
+ *  rx CH3 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch3 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch3:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch3_reg_t;
+
+
+/** Group: RX CH4 in_link dscr addr register */
+/** Type of in_link_addr_ch4 register
+ *  RX CH4 in_link dscr addr register
+ */
+typedef union {
+    struct {
+        /** inlink_addr_ch4 : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_link_addr_ch4_reg_t;
+
+
+/** Group: RX CH4 arb register */
+/** Type of in_arb_ch4 register
+ *  RX CH4 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch4 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch4:4;
+        /** exter_in_arb_priority_ch4 : R/W; bitpos: [5:4]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t exter_in_arb_priority_ch4:2;
+        /** inter_in_arb_priority_ch4 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch4:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch4_reg_t;
+
+
+/** Group: RX CH4 ETM config register */
+/** Type of in_etm_conf_ch4 register
+ *  RX CH4 ETM config register
+ */
+typedef union {
+    struct {
+        /** in_etm_en_ch4 : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to 1 to enable ETM task function
+         */
+        uint32_t in_etm_en_ch4:1;
+        /** in_etm_loop_en_ch4 : R/W; bitpos: [1]; default: 0;
+         *  when this bit is 1, dscr can be processed after receiving a task
+         */
+        uint32_t in_etm_loop_en_ch4:1;
+        /** in_dscr_task_mak_ch4 : R/W; bitpos: [3:2]; default: 1;
+         *  ETM dscr_ready maximum cache numbers
+         */
+        uint32_t in_dscr_task_mak_ch4:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_in_etm_conf_ch4_reg_t;
+
+
+/** Group: RX CH4 debug info */
+/** Type of in_fifo_cnt_ch4 register
+ *  rx CH4 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch4 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch4:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch4_reg_t;
+
+/** Type of in_pop_data_cnt_ch4 register
+ *  rx CH4 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch4 : RO; bitpos: [7:0]; default: 7;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch4_reg_t;
+
+/** Type of in_xaddr_ch4 register
+ *  rx CH4 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch4 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch4:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch4_reg_t;
+
+/** Type of in_buf_hb_rcv_ch4 register
+ *  rx CH4 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch4 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch4:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch4_reg_t;
+
+
+/** Group: RX CH5 config1 register */
+/** Type of in_conf1_ch5 register
+ *  RX CH5 config1 register
+ */
+typedef union {
+    struct {
+        /** block_start_addr_ch5 : R/W; bitpos: [31:0]; default: 0;
+         *  RX Channel 5 destination start address
+         */
+        uint32_t block_start_addr_ch5:32;
+    };
+    uint32_t val;
+} h264_dma_in_conf1_ch5_reg_t;
+
+
+/** Group: RX CH5 config2 register */
+/** Type of in_conf2_ch5 register
+ *  RX CH5 config2 register
+ */
+typedef union {
+    struct {
+        /** block_row_length_12line_ch5 : R/W; bitpos: [15:0]; default: 30720;
+         *  The number of bytes contained in a row block 12line in RX channel 5
+         */
+        uint32_t block_row_length_12line_ch5:16;
+        /** block_row_length_4line_ch5 : R/W; bitpos: [31:16]; default: 15360;
+         *  The number of bytes contained in a row block 4line in RX channel 5
+         */
+        uint32_t block_row_length_4line_ch5:16;
+    };
+    uint32_t val;
+} h264_dma_in_conf2_ch5_reg_t;
+
+
+/** Group: RX CH5 config3 register */
+/** Type of in_conf3_ch5 register
+ *  RX CH5 config3 register
+ */
+typedef union {
+    struct {
+        /** block_length_12line_ch5 : R/W; bitpos: [13:0]; default: 256;
+         *  The number of bytes contained in a block 12line
+         */
+        uint32_t block_length_12line_ch5:14;
+        /** block_length_4line_ch5 : R/W; bitpos: [27:14]; default: 128;
+         *  The number of bytes contained in a block 4line
+         */
+        uint32_t block_length_4line_ch5:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_dma_in_conf3_ch5_reg_t;
+
+
+/** Group: RX CH5 arb register */
+/** Type of in_arb_ch5 register
+ *  RX CH5 arb register
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_ch5 : R/W; bitpos: [3:0]; default: 1;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_ch5:4;
+        uint32_t reserved_4:2;
+        /** inter_in_arb_priority_ch5 : R/W; bitpos: [8:6]; default: 1;
+         *  Set the priority of channel
+         */
+        uint32_t inter_in_arb_priority_ch5:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_dma_in_arb_ch5_reg_t;
+
+
+/** Group: RX CH5 debug info */
+/** Type of in_fifo_cnt_ch5 register
+ *  rx CH5 fifo cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_infifo_cnt_ch5 : RO; bitpos: [9:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_infifo_cnt_ch5:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} h264_dma_in_fifo_cnt_ch5_reg_t;
+
+/** Type of in_pop_data_cnt_ch5 register
+ *  rx CH5 pop data cnt register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_pop_data_cnt_ch5 : RO; bitpos: [7:0]; default: 255;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_pop_data_cnt_ch5:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_dma_in_pop_data_cnt_ch5_reg_t;
+
+/** Type of in_xaddr_ch5 register
+ *  rx CH5 xaddr register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_xaddr_ch5 : RO; bitpos: [31:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_xaddr_ch5:32;
+    };
+    uint32_t val;
+} h264_dma_in_xaddr_ch5_reg_t;
+
+/** Type of in_buf_hb_rcv_ch5 register
+ *  rx CH5 buf len hb rcv register
+ */
+typedef union {
+    struct {
+        /** in_cmdfifo_buf_hb_rcv_ch5 : RO; bitpos: [28:0]; default: 0;
+         *  only for debug
+         */
+        uint32_t in_cmdfifo_buf_hb_rcv_ch5:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_dma_in_buf_hb_rcv_ch5_reg_t;
+
+
+/** Group: inter axi err */
+/** Type of inter_axi_err register
+ *  inter memory axi err register
+ */
+typedef union {
+    struct {
+        /** inter_rid_err_cnt : RO; bitpos: [3:0]; default: 0;
+         *  AXI read id err cnt
+         */
+        uint32_t inter_rid_err_cnt:4;
+        /** inter_rresp_err_cnt : RO; bitpos: [7:4]; default: 0;
+         *  AXI read resp err cnt
+         */
+        uint32_t inter_rresp_err_cnt:4;
+        /** inter_wresp_err_cnt : RO; bitpos: [11:8]; default: 0;
+         *  AXI write resp err cnt
+         */
+        uint32_t inter_wresp_err_cnt:4;
+        /** inter_rd_fifo_cnt : RO; bitpos: [14:12]; default: 0;
+         *  AXI read cmd fifo remain cmd count
+         */
+        uint32_t inter_rd_fifo_cnt:3;
+        /** inter_rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0;
+         *  AXI read backup cmd fifo remain cmd count
+         */
+        uint32_t inter_rd_bak_fifo_cnt:4;
+        /** inter_wr_fifo_cnt : RO; bitpos: [21:19]; default: 0;
+         *  AXI write cmd fifo remain cmd count
+         */
+        uint32_t inter_wr_fifo_cnt:3;
+        /** inter_wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0;
+         *  AXI write backup cmd fifo remain cmd count
+         */
+        uint32_t inter_wr_bak_fifo_cnt:4;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} h264_dma_inter_axi_err_reg_t;
+
+
+/** Group: exter axi err */
+/** Type of exter_axi_err register
+ *  exter memory axi err register
+ */
+typedef union {
+    struct {
+        /** exter_rid_err_cnt : RO; bitpos: [3:0]; default: 0;
+         *  AXI read id err cnt
+         */
+        uint32_t exter_rid_err_cnt:4;
+        /** exter_rresp_err_cnt : RO; bitpos: [7:4]; default: 0;
+         *  AXI read resp err cnt
+         */
+        uint32_t exter_rresp_err_cnt:4;
+        /** exter_wresp_err_cnt : RO; bitpos: [11:8]; default: 0;
+         *  AXI write resp err cnt
+         */
+        uint32_t exter_wresp_err_cnt:4;
+        /** exter_rd_fifo_cnt : RO; bitpos: [14:12]; default: 0;
+         *  AXI read cmd fifo remain cmd count
+         */
+        uint32_t exter_rd_fifo_cnt:3;
+        /** exter_rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0;
+         *  AXI read backup cmd fifo remain cmd count
+         */
+        uint32_t exter_rd_bak_fifo_cnt:4;
+        /** exter_wr_fifo_cnt : RO; bitpos: [21:19]; default: 0;
+         *  AXI write cmd fifo remain cmd count
+         */
+        uint32_t exter_wr_fifo_cnt:3;
+        /** exter_wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0;
+         *  AXI write backup cmd fifo remain cmd count
+         */
+        uint32_t exter_wr_bak_fifo_cnt:4;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} h264_dma_exter_axi_err_reg_t;
+
+
+/** Group: dscr addr range register */
+/** Type of inter_mem_start_addr0 register
+ *  Start address of inter memory range0 register
+ */
+typedef union {
+    struct {
+        /** access_inter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_inter_mem_start_addr0:32;
+    };
+    uint32_t val;
+} h264_dma_inter_mem_start_addr0_reg_t;
+
+/** Type of inter_mem_end_addr0 register
+ *  end address of inter memory range0 register
+ */
+typedef union {
+    struct {
+        /** access_inter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_inter_mem_end_addr0:32;
+    };
+    uint32_t val;
+} h264_dma_inter_mem_end_addr0_reg_t;
+
+/** Type of inter_mem_start_addr1 register
+ *  Start address of inter memory range1 register
+ */
+typedef union {
+    struct {
+        /** access_inter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_inter_mem_start_addr1:32;
+    };
+    uint32_t val;
+} h264_dma_inter_mem_start_addr1_reg_t;
+
+/** Type of inter_mem_end_addr1 register
+ *  end address of inter memory range1 register
+ */
+typedef union {
+    struct {
+        /** access_inter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_inter_mem_end_addr1:32;
+    };
+    uint32_t val;
+} h264_dma_inter_mem_end_addr1_reg_t;
+
+/** Type of exter_mem_start_addr0 register
+ *  Start address of exter memory range0 register
+ */
+typedef union {
+    struct {
+        /** access_exter_mem_start_addr0 : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_exter_mem_start_addr0:32;
+    };
+    uint32_t val;
+} h264_dma_exter_mem_start_addr0_reg_t;
+
+/** Type of exter_mem_end_addr0 register
+ *  end address of exter memory range0 register
+ */
+typedef union {
+    struct {
+        /** access_exter_mem_end_addr0 : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_exter_mem_end_addr0:32;
+    };
+    uint32_t val;
+} h264_dma_exter_mem_end_addr0_reg_t;
+
+/** Type of exter_mem_start_addr1 register
+ *  Start address of exter memory range1 register
+ */
+typedef union {
+    struct {
+        /** access_exter_mem_start_addr1 : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_exter_mem_start_addr1:32;
+    };
+    uint32_t val;
+} h264_dma_exter_mem_start_addr1_reg_t;
+
+/** Type of exter_mem_end_addr1 register
+ *  end address of exter memory range1 register
+ */
+typedef union {
+    struct {
+        /** access_exter_mem_end_addr1 : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_exter_mem_end_addr1:32;
+    };
+    uint32_t val;
+} h264_dma_exter_mem_end_addr1_reg_t;
+
+
+/** Group: out arb config register */
+/** Type of out_arb_config register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t out_arb_timeout_num:16;
+        /** out_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t out_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} h264_dma_out_arb_config_reg_t;
+
+
+/** Group: in arb config register */
+/** Type of in_arb_config register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t in_arb_timeout_num:16;
+        /** in_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t in_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} h264_dma_in_arb_config_reg_t;
+
+
+/** Group: date register */
+/** Type of date register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 539165699;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} h264_dma_date_reg_t;
+
+
+/** Group: counter rst register */
+/** Type of counter_rst register
+ *  counter reset register
+ */
+typedef union {
+    struct {
+        /** rx_ch0_exter_counter_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0 to this bit to reset rx ch0 counter.
+         */
+        uint32_t rx_ch0_exter_counter_rst:1;
+        /** rx_ch1_exter_counter_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0 to this bit to reset rx ch1 counter.
+         */
+        uint32_t rx_ch1_exter_counter_rst:1;
+        /** rx_ch2_inter_counter_rst : R/W; bitpos: [2]; default: 0;
+         *  Write 1 then write 0 to this bit to reset rx ch2 counter.
+         */
+        uint32_t rx_ch2_inter_counter_rst:1;
+        /** rx_ch5_inter_counter_rst : R/W; bitpos: [3]; default: 0;
+         *  Write 1 then write 0 to this bit to reset rx ch5 counter.
+         */
+        uint32_t rx_ch5_inter_counter_rst:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_counter_rst_reg_t;
+
+
+/** Group: counter register */
+/** Type of rx_ch0_counter register
+ *  rx ch0 counter register
+ */
+typedef union {
+    struct {
+        /** rx_ch0_cnt : RO; bitpos: [22:0]; default: 0;
+         *  rx ch0 counter register
+         */
+        uint32_t rx_ch0_cnt:23;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} h264_dma_rx_ch0_counter_reg_t;
+
+/** Type of rx_ch1_counter register
+ *  rx ch1 counter register
+ */
+typedef union {
+    struct {
+        /** rx_ch1_cnt : RO; bitpos: [20:0]; default: 0;
+         *  rx ch1 counter register
+         */
+        uint32_t rx_ch1_cnt:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} h264_dma_rx_ch1_counter_reg_t;
+
+/** Type of rx_ch2_counter register
+ *  rx ch2 counter register
+ */
+typedef union {
+    struct {
+        /** rx_ch2_cnt : RO; bitpos: [10:0]; default: 0;
+         *  rx ch2 counter register
+         */
+        uint32_t rx_ch2_cnt:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_dma_rx_ch2_counter_reg_t;
+
+/** Type of rx_ch5_counter register
+ *  rx ch5 counter register
+ */
+typedef union {
+    struct {
+        /** rx_ch5_cnt : RO; bitpos: [16:0]; default: 0;
+         *  rx ch5 counter register
+         */
+        uint32_t rx_ch5_cnt:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} h264_dma_rx_ch5_counter_reg_t;
+
+
+/** Group: pbyte register */
+/** Type of pbyte register
+ *  image pbyte register
+ */
+typedef union {
+    struct {
+        /** ori_pbyte : R/W; bitpos: [3:0]; default: 2;
+         *  configures bytes per pixel for ori img. 0: 0.5byte/pix, 1: 1byte/pix, 2:
+         *  1.5byte/pix, 3: 2byte/pix, 4: 3byte/pix
+         */
+        uint32_t ori_pbyte:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_dma_pbyte_reg_t;
+
+
+/** Group: debug register */
+/** Type of ch_dbg_en register
+ *  channel debug enable register
+ */
+typedef union {
+    struct {
+        /** out_ch0_dbg_en : R/W; bitpos: [0]; default: 0;
+         *  configures whether to enable out channel 0 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch0_dbg_en:1;
+        /** out_ch1_dbg_en : R/W; bitpos: [1]; default: 0;
+         *  configures whether to enable out channel 1 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch1_dbg_en:1;
+        /** out_ch2_dbg_en : R/W; bitpos: [2]; default: 0;
+         *  configures whether to enable out channel 2 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch2_dbg_en:1;
+        /** out_ch3_dbg_en : R/W; bitpos: [3]; default: 0;
+         *  configures whether to enable out channel 3 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch3_dbg_en:1;
+        /** out_ch4_dbg_en : R/W; bitpos: [4]; default: 0;
+         *  configures whether to enable out channel 4 debug. 0: disable, 1: enable
+         */
+        uint32_t out_ch4_dbg_en:1;
+        uint32_t reserved_5:11;
+        /** in_ch0_dbg_en : R/W; bitpos: [16]; default: 0;
+         *  configures whether to enable in channel 0 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch0_dbg_en:1;
+        /** in_ch1_dbg_en : R/W; bitpos: [17]; default: 0;
+         *  configures whether to enable in channel 1 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch1_dbg_en:1;
+        /** in_ch2_dbg_en : R/W; bitpos: [18]; default: 0;
+         *  configures whether to enable in channel 2 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch2_dbg_en:1;
+        /** in_ch3_dbg_en : R/W; bitpos: [19]; default: 0;
+         *  configures whether to enable in channel 3 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch3_dbg_en:1;
+        /** in_ch4_dbg_en : R/W; bitpos: [20]; default: 0;
+         *  configures whether to enable in channel 4 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch4_dbg_en:1;
+        /** in_ch5_dbg_en : R/W; bitpos: [21]; default: 0;
+         *  configures whether to enable in channel 5 debug. 0: disable, 1: enable
+         */
+        uint32_t in_ch5_dbg_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} h264_dma_ch_dbg_en_reg_t;
+
+/** Type of out_ch0_dbg_data_l register
+ *  out channel 0 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch0_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 0 debug data bit 31-0
+         */
+        uint32_t out_ch0_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch0_dbg_data_l_reg_t;
+
+/** Type of out_ch0_dbg_data_h register
+ *  out channel 0 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch0_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 0 debug data bit 63-32
+         */
+        uint32_t out_ch0_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch0_dbg_data_h_reg_t;
+
+/** Type of out_ch1_dbg_data_l register
+ *  out channel 1 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch1_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 1 debug data bit 31-0
+         */
+        uint32_t out_ch1_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch1_dbg_data_l_reg_t;
+
+/** Type of out_ch1_dbg_data_h register
+ *  out channel 1 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch1_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 1 debug data bit 63-32
+         */
+        uint32_t out_ch1_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch1_dbg_data_h_reg_t;
+
+/** Type of out_ch2_dbg_data_l register
+ *  out channel 2 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch2_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 2 debug data bit 31-0
+         */
+        uint32_t out_ch2_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch2_dbg_data_l_reg_t;
+
+/** Type of out_ch2_dbg_data_h register
+ *  out channel 2 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch2_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 2 debug data bit 63-32
+         */
+        uint32_t out_ch2_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch2_dbg_data_h_reg_t;
+
+/** Type of out_ch3_dbg_data_l register
+ *  out channel 3 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch3_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 3 debug data bit 31-0
+         */
+        uint32_t out_ch3_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch3_dbg_data_l_reg_t;
+
+/** Type of out_ch3_dbg_data_h register
+ *  out channel 3 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch3_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 3 debug data bit 63-32
+         */
+        uint32_t out_ch3_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch3_dbg_data_h_reg_t;
+
+/** Type of out_ch4_dbg_data_l register
+ *  out channel 4 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch4_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 4 debug data bit 31-0
+         */
+        uint32_t out_ch4_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch4_dbg_data_l_reg_t;
+
+/** Type of out_ch4_dbg_data_h register
+ *  out channel 4 debug data register
+ */
+typedef union {
+    struct {
+        /** out_ch4_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures out channel 4 debug data bit 63-32
+         */
+        uint32_t out_ch4_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_out_ch4_dbg_data_h_reg_t;
+
+/** Type of in_ch0_dbg_data_l register
+ *  in channel 0 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch0_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 0 debug data bit 31-0
+         */
+        uint32_t in_ch0_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch0_dbg_data_l_reg_t;
+
+/** Type of in_ch0_dbg_data_h register
+ *  in channel 0 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch0_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 0 debug data bit 63-32
+         */
+        uint32_t in_ch0_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch0_dbg_data_h_reg_t;
+
+/** Type of in_ch1_dbg_data_l register
+ *  in channel 1 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch1_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 1 debug data bit 31-0
+         */
+        uint32_t in_ch1_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch1_dbg_data_l_reg_t;
+
+/** Type of in_ch1_dbg_data_h register
+ *  in channel 1 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch1_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 1 debug data bit 63-32
+         */
+        uint32_t in_ch1_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch1_dbg_data_h_reg_t;
+
+/** Type of in_ch2_dbg_data_l register
+ *  in channel 2 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch2_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 2 debug data bit 31-0
+         */
+        uint32_t in_ch2_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch2_dbg_data_l_reg_t;
+
+/** Type of in_ch2_dbg_data_h register
+ *  in channel 2 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch2_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 2 debug data bit 63-32
+         */
+        uint32_t in_ch2_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch2_dbg_data_h_reg_t;
+
+/** Type of in_ch3_dbg_data_l register
+ *  in channel 3 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch3_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 3 debug data bit 31-0
+         */
+        uint32_t in_ch3_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch3_dbg_data_l_reg_t;
+
+/** Type of in_ch3_dbg_data_h register
+ *  in channel 3 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch3_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 3 debug data bit 63-32
+         */
+        uint32_t in_ch3_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch3_dbg_data_h_reg_t;
+
+/** Type of in_ch4_dbg_data_l register
+ *  in channel 4 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch4_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 4 debug data bit 31-0
+         */
+        uint32_t in_ch4_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch4_dbg_data_l_reg_t;
+
+/** Type of in_ch4_dbg_data_h register
+ *  in channel 4 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch4_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 4 debug data bit 63-32
+         */
+        uint32_t in_ch4_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch4_dbg_data_h_reg_t;
+
+/** Type of in_ch5_dbg_data_l register
+ *  in channel 5 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch5_dbg_data_l : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 5 debug data bit 31-0
+         */
+        uint32_t in_ch5_dbg_data_l:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch5_dbg_data_l_reg_t;
+
+/** Type of in_ch5_dbg_data_h register
+ *  in channel 5 debug data register
+ */
+typedef union {
+    struct {
+        /** in_ch5_dbg_data_h : R/W; bitpos: [31:0]; default: 0;
+         *  configures in channel 5 debug data bit 63-32
+         */
+        uint32_t in_ch5_dbg_data_h:32;
+    };
+    uint32_t val;
+} h264_dma_in_ch5_dbg_data_h_reg_t;
+
+
+typedef struct {
+    volatile h264_dma_out_conf0_ch0_reg_t out_conf0_ch0;
+    volatile h264_dma_out_int_raw_ch0_reg_t out_int_raw_ch0;
+    volatile h264_dma_out_int_ena_ch0_reg_t out_int_ena_ch0;
+    volatile h264_dma_out_int_st_ch0_reg_t out_int_st_ch0;
+    volatile h264_dma_out_int_clr_ch0_reg_t out_int_clr_ch0;
+    volatile h264_dma_outfifo_status_ch0_reg_t outfifo_status_ch0;
+    volatile h264_dma_out_push_ch0_reg_t out_push_ch0;
+    volatile h264_dma_out_link_conf_ch0_reg_t out_link_conf_ch0;
+    volatile h264_dma_out_link_addr_ch0_reg_t out_link_addr_ch0;
+    volatile h264_dma_out_state_ch0_reg_t out_state_ch0;
+    volatile h264_dma_out_eof_des_addr_ch0_reg_t out_eof_des_addr_ch0;
+    volatile h264_dma_out_dscr_ch0_reg_t out_dscr_ch0;
+    volatile h264_dma_out_dscr_bf0_ch0_reg_t out_dscr_bf0_ch0;
+    volatile h264_dma_out_dscr_bf1_ch0_reg_t out_dscr_bf1_ch0;
+    uint32_t reserved_038;
+    volatile h264_dma_out_arb_ch0_reg_t out_arb_ch0;
+    volatile h264_dma_out_ro_status_ch0_reg_t out_ro_status_ch0;
+    volatile h264_dma_out_ro_pd_conf_ch0_reg_t out_ro_pd_conf_ch0;
+    uint32_t reserved_048[2];
+    volatile h264_dma_out_mode_enable_ch0_reg_t out_mode_enable_ch0;
+    volatile h264_dma_out_mode_yuv_ch0_reg_t out_mode_yuv_ch0;
+    uint32_t reserved_058[4];
+    volatile h264_dma_out_etm_conf_ch0_reg_t out_etm_conf_ch0;
+    uint32_t reserved_06c;
+    volatile h264_dma_out_buf_len_ch0_reg_t out_buf_len_ch0;
+    volatile h264_dma_out_fifo_bcnt_ch0_reg_t out_fifo_bcnt_ch0;
+    volatile h264_dma_out_push_bytecnt_ch0_reg_t out_push_bytecnt_ch0;
+    volatile h264_dma_out_xaddr_ch0_reg_t out_xaddr_ch0;
+    uint32_t reserved_080[32];
+    volatile h264_dma_out_conf0_ch1_reg_t out_conf0_ch1;
+    volatile h264_dma_out_int_raw_ch1_reg_t out_int_raw_ch1;
+    volatile h264_dma_out_int_ena_ch1_reg_t out_int_ena_ch1;
+    volatile h264_dma_out_int_st_ch1_reg_t out_int_st_ch1;
+    volatile h264_dma_out_int_clr_ch1_reg_t out_int_clr_ch1;
+    volatile h264_dma_outfifo_status_ch1_reg_t outfifo_status_ch1;
+    volatile h264_dma_out_push_ch1_reg_t out_push_ch1;
+    volatile h264_dma_out_link_conf_ch1_reg_t out_link_conf_ch1;
+    volatile h264_dma_out_link_addr_ch1_reg_t out_link_addr_ch1;
+    volatile h264_dma_out_state_ch1_reg_t out_state_ch1;
+    volatile h264_dma_out_eof_des_addr_ch1_reg_t out_eof_des_addr_ch1;
+    volatile h264_dma_out_dscr_ch1_reg_t out_dscr_ch1;
+    volatile h264_dma_out_dscr_bf0_ch1_reg_t out_dscr_bf0_ch1;
+    volatile h264_dma_out_dscr_bf1_ch1_reg_t out_dscr_bf1_ch1;
+    uint32_t reserved_138;
+    volatile h264_dma_out_arb_ch1_reg_t out_arb_ch1;
+    uint32_t reserved_140[10];
+    volatile h264_dma_out_etm_conf_ch1_reg_t out_etm_conf_ch1;
+    uint32_t reserved_16c;
+    volatile h264_dma_out_buf_len_ch1_reg_t out_buf_len_ch1;
+    volatile h264_dma_out_fifo_bcnt_ch1_reg_t out_fifo_bcnt_ch1;
+    volatile h264_dma_out_push_bytecnt_ch1_reg_t out_push_bytecnt_ch1;
+    volatile h264_dma_out_xaddr_ch1_reg_t out_xaddr_ch1;
+    uint32_t reserved_180[32];
+    volatile h264_dma_out_conf0_ch2_reg_t out_conf0_ch2;
+    volatile h264_dma_out_int_raw_ch2_reg_t out_int_raw_ch2;
+    volatile h264_dma_out_int_ena_ch2_reg_t out_int_ena_ch2;
+    volatile h264_dma_out_int_st_ch2_reg_t out_int_st_ch2;
+    volatile h264_dma_out_int_clr_ch2_reg_t out_int_clr_ch2;
+    volatile h264_dma_outfifo_status_ch2_reg_t outfifo_status_ch2;
+    volatile h264_dma_out_push_ch2_reg_t out_push_ch2;
+    volatile h264_dma_out_link_conf_ch2_reg_t out_link_conf_ch2;
+    volatile h264_dma_out_link_addr_ch2_reg_t out_link_addr_ch2;
+    volatile h264_dma_out_state_ch2_reg_t out_state_ch2;
+    volatile h264_dma_out_eof_des_addr_ch2_reg_t out_eof_des_addr_ch2;
+    volatile h264_dma_out_dscr_ch2_reg_t out_dscr_ch2;
+    volatile h264_dma_out_dscr_bf0_ch2_reg_t out_dscr_bf0_ch2;
+    volatile h264_dma_out_dscr_bf1_ch2_reg_t out_dscr_bf1_ch2;
+    uint32_t reserved_238;
+    volatile h264_dma_out_arb_ch2_reg_t out_arb_ch2;
+    uint32_t reserved_240[10];
+    volatile h264_dma_out_etm_conf_ch2_reg_t out_etm_conf_ch2;
+    uint32_t reserved_26c;
+    volatile h264_dma_out_buf_len_ch2_reg_t out_buf_len_ch2;
+    volatile h264_dma_out_fifo_bcnt_ch2_reg_t out_fifo_bcnt_ch2;
+    volatile h264_dma_out_push_bytecnt_ch2_reg_t out_push_bytecnt_ch2;
+    volatile h264_dma_out_xaddr_ch2_reg_t out_xaddr_ch2;
+    uint32_t reserved_280[32];
+    volatile h264_dma_out_conf0_ch3_reg_t out_conf0_ch3;
+    volatile h264_dma_out_int_raw_ch3_reg_t out_int_raw_ch3;
+    volatile h264_dma_out_int_ena_ch3_reg_t out_int_ena_ch3;
+    volatile h264_dma_out_int_st_ch3_reg_t out_int_st_ch3;
+    volatile h264_dma_out_int_clr_ch3_reg_t out_int_clr_ch3;
+    volatile h264_dma_outfifo_status_ch3_reg_t outfifo_status_ch3;
+    volatile h264_dma_out_push_ch3_reg_t out_push_ch3;
+    volatile h264_dma_out_link_conf_ch3_reg_t out_link_conf_ch3;
+    volatile h264_dma_out_link_addr_ch3_reg_t out_link_addr_ch3;
+    volatile h264_dma_out_state_ch3_reg_t out_state_ch3;
+    volatile h264_dma_out_eof_des_addr_ch3_reg_t out_eof_des_addr_ch3;
+    volatile h264_dma_out_dscr_ch3_reg_t out_dscr_ch3;
+    volatile h264_dma_out_dscr_bf0_ch3_reg_t out_dscr_bf0_ch3;
+    volatile h264_dma_out_dscr_bf1_ch3_reg_t out_dscr_bf1_ch3;
+    uint32_t reserved_338;
+    volatile h264_dma_out_arb_ch3_reg_t out_arb_ch3;
+    uint32_t reserved_340[10];
+    volatile h264_dma_out_etm_conf_ch3_reg_t out_etm_conf_ch3;
+    uint32_t reserved_36c;
+    volatile h264_dma_out_buf_len_ch3_reg_t out_buf_len_ch3;
+    volatile h264_dma_out_fifo_bcnt_ch3_reg_t out_fifo_bcnt_ch3;
+    volatile h264_dma_out_push_bytecnt_ch3_reg_t out_push_bytecnt_ch3;
+    volatile h264_dma_out_xaddr_ch3_reg_t out_xaddr_ch3;
+    volatile h264_dma_out_block_buf_len_ch3_reg_t out_block_buf_len_ch3;
+    uint32_t reserved_384[31];
+    volatile h264_dma_out_conf0_ch4_reg_t out_conf0_ch4;
+    volatile h264_dma_out_int_raw_ch4_reg_t out_int_raw_ch4;
+    volatile h264_dma_out_int_ena_ch4_reg_t out_int_ena_ch4;
+    volatile h264_dma_out_int_st_ch4_reg_t out_int_st_ch4;
+    volatile h264_dma_out_int_clr_ch4_reg_t out_int_clr_ch4;
+    volatile h264_dma_outfifo_status_ch4_reg_t outfifo_status_ch4;
+    volatile h264_dma_out_push_ch4_reg_t out_push_ch4;
+    volatile h264_dma_out_link_conf_ch4_reg_t out_link_conf_ch4;
+    volatile h264_dma_out_link_addr_ch4_reg_t out_link_addr_ch4;
+    volatile h264_dma_out_state_ch4_reg_t out_state_ch4;
+    volatile h264_dma_out_eof_des_addr_ch4_reg_t out_eof_des_addr_ch4;
+    volatile h264_dma_out_dscr_ch4_reg_t out_dscr_ch4;
+    volatile h264_dma_out_dscr_bf0_ch4_reg_t out_dscr_bf0_ch4;
+    volatile h264_dma_out_dscr_bf1_ch4_reg_t out_dscr_bf1_ch4;
+    uint32_t reserved_438;
+    volatile h264_dma_out_arb_ch4_reg_t out_arb_ch4;
+    uint32_t reserved_440[10];
+    volatile h264_dma_out_etm_conf_ch4_reg_t out_etm_conf_ch4;
+    uint32_t reserved_46c;
+    volatile h264_dma_out_buf_len_ch4_reg_t out_buf_len_ch4;
+    volatile h264_dma_out_fifo_bcnt_ch4_reg_t out_fifo_bcnt_ch4;
+    volatile h264_dma_out_push_bytecnt_ch4_reg_t out_push_bytecnt_ch4;
+    volatile h264_dma_out_xaddr_ch4_reg_t out_xaddr_ch4;
+    volatile h264_dma_out_block_buf_len_ch4_reg_t out_block_buf_len_ch4;
+    uint32_t reserved_484[31];
+    volatile h264_dma_in_conf0_ch0_reg_t in_conf0_ch0;
+    volatile h264_dma_in_int_raw_ch0_reg_t in_int_raw_ch0;
+    volatile h264_dma_in_int_ena_ch0_reg_t in_int_ena_ch0;
+    volatile h264_dma_in_int_st_ch0_reg_t in_int_st_ch0;
+    volatile h264_dma_in_int_clr_ch0_reg_t in_int_clr_ch0;
+    volatile h264_dma_infifo_status_ch0_reg_t infifo_status_ch0;
+    volatile h264_dma_in_pop_ch0_reg_t in_pop_ch0;
+    volatile h264_dma_in_link_conf_ch0_reg_t in_link_conf_ch0;
+    volatile h264_dma_in_link_addr_ch0_reg_t in_link_addr_ch0;
+    volatile h264_dma_in_state_ch0_reg_t in_state_ch0;
+    volatile h264_dma_in_suc_eof_des_addr_ch0_reg_t in_suc_eof_des_addr_ch0;
+    volatile h264_dma_in_err_eof_des_addr_ch0_reg_t in_err_eof_des_addr_ch0;
+    volatile h264_dma_in_dscr_ch0_reg_t in_dscr_ch0;
+    volatile h264_dma_in_dscr_bf0_ch0_reg_t in_dscr_bf0_ch0;
+    volatile h264_dma_in_dscr_bf1_ch0_reg_t in_dscr_bf1_ch0;
+    uint32_t reserved_53c;
+    volatile h264_dma_in_arb_ch0_reg_t in_arb_ch0;
+    uint32_t reserved_544;
+    volatile h264_dma_in_ro_pd_conf_ch0_reg_t in_ro_pd_conf_ch0;
+    uint32_t reserved_54c[8];
+    volatile h264_dma_in_etm_conf_ch0_reg_t in_etm_conf_ch0;
+    uint32_t reserved_570[4];
+    volatile h264_dma_in_fifo_cnt_ch0_reg_t in_fifo_cnt_ch0;
+    volatile h264_dma_in_pop_data_cnt_ch0_reg_t in_pop_data_cnt_ch0;
+    volatile h264_dma_in_xaddr_ch0_reg_t in_xaddr_ch0;
+    volatile h264_dma_in_buf_hb_rcv_ch0_reg_t in_buf_hb_rcv_ch0;
+    uint32_t reserved_590[28];
+    volatile h264_dma_in_conf0_ch1_reg_t in_conf0_ch1;
+    volatile h264_dma_in_int_raw_ch1_reg_t in_int_raw_ch1;
+    volatile h264_dma_in_int_ena_ch1_reg_t in_int_ena_ch1;
+    volatile h264_dma_in_int_st_ch1_reg_t in_int_st_ch1;
+    volatile h264_dma_in_int_clr_ch1_reg_t in_int_clr_ch1;
+    volatile h264_dma_infifo_status_ch1_reg_t infifo_status_ch1;
+    volatile h264_dma_in_pop_ch1_reg_t in_pop_ch1;
+    volatile h264_dma_in_link_conf_ch1_reg_t in_link_conf_ch1;
+    volatile h264_dma_in_link_addr_ch1_reg_t in_link_addr_ch1;
+    volatile h264_dma_in_state_ch1_reg_t in_state_ch1;
+    volatile h264_dma_in_suc_eof_des_addr_ch1_reg_t in_suc_eof_des_addr_ch1;
+    volatile h264_dma_in_err_eof_des_addr_ch1_reg_t in_err_eof_des_addr_ch1;
+    volatile h264_dma_in_dscr_ch1_reg_t in_dscr_ch1;
+    volatile h264_dma_in_dscr_bf0_ch1_reg_t in_dscr_bf0_ch1;
+    volatile h264_dma_in_dscr_bf1_ch1_reg_t in_dscr_bf1_ch1;
+    uint32_t reserved_63c;
+    volatile h264_dma_in_arb_ch1_reg_t in_arb_ch1;
+    uint32_t reserved_644;
+    volatile h264_dma_in_etm_conf_ch1_reg_t in_etm_conf_ch1;
+    uint32_t reserved_64c[13];
+    volatile h264_dma_in_fifo_cnt_ch1_reg_t in_fifo_cnt_ch1;
+    volatile h264_dma_in_pop_data_cnt_ch1_reg_t in_pop_data_cnt_ch1;
+    volatile h264_dma_in_xaddr_ch1_reg_t in_xaddr_ch1;
+    volatile h264_dma_in_buf_hb_rcv_ch1_reg_t in_buf_hb_rcv_ch1;
+    uint32_t reserved_690[28];
+    volatile h264_dma_in_conf0_ch2_reg_t in_conf0_ch2;
+    volatile h264_dma_in_int_raw_ch2_reg_t in_int_raw_ch2;
+    volatile h264_dma_in_int_ena_ch2_reg_t in_int_ena_ch2;
+    volatile h264_dma_in_int_st_ch2_reg_t in_int_st_ch2;
+    volatile h264_dma_in_int_clr_ch2_reg_t in_int_clr_ch2;
+    volatile h264_dma_infifo_status_ch2_reg_t infifo_status_ch2;
+    volatile h264_dma_in_pop_ch2_reg_t in_pop_ch2;
+    volatile h264_dma_in_link_conf_ch2_reg_t in_link_conf_ch2;
+    volatile h264_dma_in_link_addr_ch2_reg_t in_link_addr_ch2;
+    volatile h264_dma_in_state_ch2_reg_t in_state_ch2;
+    volatile h264_dma_in_suc_eof_des_addr_ch2_reg_t in_suc_eof_des_addr_ch2;
+    volatile h264_dma_in_err_eof_des_addr_ch2_reg_t in_err_eof_des_addr_ch2;
+    volatile h264_dma_in_dscr_ch2_reg_t in_dscr_ch2;
+    volatile h264_dma_in_dscr_bf0_ch2_reg_t in_dscr_bf0_ch2;
+    volatile h264_dma_in_dscr_bf1_ch2_reg_t in_dscr_bf1_ch2;
+    uint32_t reserved_73c;
+    volatile h264_dma_in_arb_ch2_reg_t in_arb_ch2;
+    uint32_t reserved_744;
+    volatile h264_dma_in_etm_conf_ch2_reg_t in_etm_conf_ch2;
+    uint32_t reserved_74c[13];
+    volatile h264_dma_in_fifo_cnt_ch2_reg_t in_fifo_cnt_ch2;
+    volatile h264_dma_in_pop_data_cnt_ch2_reg_t in_pop_data_cnt_ch2;
+    volatile h264_dma_in_xaddr_ch2_reg_t in_xaddr_ch2;
+    volatile h264_dma_in_buf_hb_rcv_ch2_reg_t in_buf_hb_rcv_ch2;
+    uint32_t reserved_790[28];
+    volatile h264_dma_in_conf0_ch3_reg_t in_conf0_ch3;
+    volatile h264_dma_in_int_raw_ch3_reg_t in_int_raw_ch3;
+    volatile h264_dma_in_int_ena_ch3_reg_t in_int_ena_ch3;
+    volatile h264_dma_in_int_st_ch3_reg_t in_int_st_ch3;
+    volatile h264_dma_in_int_clr_ch3_reg_t in_int_clr_ch3;
+    volatile h264_dma_infifo_status_ch3_reg_t infifo_status_ch3;
+    volatile h264_dma_in_pop_ch3_reg_t in_pop_ch3;
+    volatile h264_dma_in_link_conf_ch3_reg_t in_link_conf_ch3;
+    volatile h264_dma_in_link_addr_ch3_reg_t in_link_addr_ch3;
+    volatile h264_dma_in_state_ch3_reg_t in_state_ch3;
+    volatile h264_dma_in_suc_eof_des_addr_ch3_reg_t in_suc_eof_des_addr_ch3;
+    volatile h264_dma_in_err_eof_des_addr_ch3_reg_t in_err_eof_des_addr_ch3;
+    volatile h264_dma_in_dscr_ch3_reg_t in_dscr_ch3;
+    volatile h264_dma_in_dscr_bf0_ch3_reg_t in_dscr_bf0_ch3;
+    volatile h264_dma_in_dscr_bf1_ch3_reg_t in_dscr_bf1_ch3;
+    uint32_t reserved_83c;
+    volatile h264_dma_in_arb_ch3_reg_t in_arb_ch3;
+    uint32_t reserved_844;
+    volatile h264_dma_in_etm_conf_ch3_reg_t in_etm_conf_ch3;
+    uint32_t reserved_84c[13];
+    volatile h264_dma_in_fifo_cnt_ch3_reg_t in_fifo_cnt_ch3;
+    volatile h264_dma_in_pop_data_cnt_ch3_reg_t in_pop_data_cnt_ch3;
+    volatile h264_dma_in_xaddr_ch3_reg_t in_xaddr_ch3;
+    volatile h264_dma_in_buf_hb_rcv_ch3_reg_t in_buf_hb_rcv_ch3;
+    uint32_t reserved_890[28];
+    volatile h264_dma_in_conf0_ch4_reg_t in_conf0_ch4;
+    volatile h264_dma_in_int_raw_ch4_reg_t in_int_raw_ch4;
+    volatile h264_dma_in_int_ena_ch4_reg_t in_int_ena_ch4;
+    volatile h264_dma_in_int_st_ch4_reg_t in_int_st_ch4;
+    volatile h264_dma_in_int_clr_ch4_reg_t in_int_clr_ch4;
+    volatile h264_dma_infifo_status_ch4_reg_t infifo_status_ch4;
+    volatile h264_dma_in_pop_ch4_reg_t in_pop_ch4;
+    volatile h264_dma_in_link_conf_ch4_reg_t in_link_conf_ch4;
+    volatile h264_dma_in_link_addr_ch4_reg_t in_link_addr_ch4;
+    volatile h264_dma_in_state_ch4_reg_t in_state_ch4;
+    volatile h264_dma_in_suc_eof_des_addr_ch4_reg_t in_suc_eof_des_addr_ch4;
+    volatile h264_dma_in_err_eof_des_addr_ch4_reg_t in_err_eof_des_addr_ch4;
+    volatile h264_dma_in_dscr_ch4_reg_t in_dscr_ch4;
+    volatile h264_dma_in_dscr_bf0_ch4_reg_t in_dscr_bf0_ch4;
+    volatile h264_dma_in_dscr_bf1_ch4_reg_t in_dscr_bf1_ch4;
+    uint32_t reserved_93c;
+    volatile h264_dma_in_arb_ch4_reg_t in_arb_ch4;
+    uint32_t reserved_944;
+    volatile h264_dma_in_etm_conf_ch4_reg_t in_etm_conf_ch4;
+    uint32_t reserved_94c[13];
+    volatile h264_dma_in_fifo_cnt_ch4_reg_t in_fifo_cnt_ch4;
+    volatile h264_dma_in_pop_data_cnt_ch4_reg_t in_pop_data_cnt_ch4;
+    volatile h264_dma_in_xaddr_ch4_reg_t in_xaddr_ch4;
+    volatile h264_dma_in_buf_hb_rcv_ch4_reg_t in_buf_hb_rcv_ch4;
+    uint32_t reserved_990[28];
+    volatile h264_dma_in_conf0_ch5_reg_t in_conf0_ch5;
+    volatile h264_dma_in_conf1_ch5_reg_t in_conf1_ch5;
+    volatile h264_dma_in_conf2_ch5_reg_t in_conf2_ch5;
+    volatile h264_dma_in_conf3_ch5_reg_t in_conf3_ch5;
+    volatile h264_dma_in_int_raw_ch5_reg_t in_int_raw_ch5;
+    volatile h264_dma_in_int_ena_ch5_reg_t in_int_ena_ch5;
+    volatile h264_dma_in_int_st_ch5_reg_t in_int_st_ch5;
+    volatile h264_dma_in_int_clr_ch5_reg_t in_int_clr_ch5;
+    volatile h264_dma_infifo_status_ch5_reg_t infifo_status_ch5;
+    volatile h264_dma_in_pop_ch5_reg_t in_pop_ch5;
+    volatile h264_dma_in_state_ch5_reg_t in_state_ch5;
+    uint32_t reserved_a2c[5];
+    volatile h264_dma_in_arb_ch5_reg_t in_arb_ch5;
+    uint32_t reserved_a44[15];
+    volatile h264_dma_in_fifo_cnt_ch5_reg_t in_fifo_cnt_ch5;
+    volatile h264_dma_in_pop_data_cnt_ch5_reg_t in_pop_data_cnt_ch5;
+    volatile h264_dma_in_xaddr_ch5_reg_t in_xaddr_ch5;
+    volatile h264_dma_in_buf_hb_rcv_ch5_reg_t in_buf_hb_rcv_ch5;
+    uint32_t reserved_a90[28];
+    volatile h264_dma_inter_axi_err_reg_t inter_axi_err;
+    volatile h264_dma_exter_axi_err_reg_t exter_axi_err;
+    volatile h264_dma_rst_conf_reg_t rst_conf;
+    volatile h264_dma_inter_mem_start_addr0_reg_t inter_mem_start_addr0;
+    volatile h264_dma_inter_mem_end_addr0_reg_t inter_mem_end_addr0;
+    volatile h264_dma_inter_mem_start_addr1_reg_t inter_mem_start_addr1;
+    volatile h264_dma_inter_mem_end_addr1_reg_t inter_mem_end_addr1;
+    uint32_t reserved_b1c;
+    volatile h264_dma_exter_mem_start_addr0_reg_t exter_mem_start_addr0;
+    volatile h264_dma_exter_mem_end_addr0_reg_t exter_mem_end_addr0;
+    volatile h264_dma_exter_mem_start_addr1_reg_t exter_mem_start_addr1;
+    volatile h264_dma_exter_mem_end_addr1_reg_t exter_mem_end_addr1;
+    volatile h264_dma_out_arb_config_reg_t out_arb_config;
+    volatile h264_dma_in_arb_config_reg_t in_arb_config;
+    uint32_t reserved_b38;
+    volatile h264_dma_date_reg_t date;
+    uint32_t reserved_b40[4];
+    volatile h264_dma_counter_rst_reg_t counter_rst;
+    volatile h264_dma_rx_ch0_counter_reg_t rx_ch0_counter;
+    volatile h264_dma_rx_ch1_counter_reg_t rx_ch1_counter;
+    volatile h264_dma_rx_ch2_counter_reg_t rx_ch2_counter;
+    volatile h264_dma_rx_ch5_counter_reg_t rx_ch5_counter;
+    volatile h264_dma_pbyte_reg_t pbyte;
+    volatile h264_dma_ch_dbg_en_reg_t ch_dbg_en;
+    volatile h264_dma_out_ch0_dbg_data_l_reg_t out_ch0_dbg_data_l;
+    volatile h264_dma_out_ch0_dbg_data_h_reg_t out_ch0_dbg_data_h;
+    volatile h264_dma_out_ch1_dbg_data_l_reg_t out_ch1_dbg_data_l;
+    volatile h264_dma_out_ch1_dbg_data_h_reg_t out_ch1_dbg_data_h;
+    volatile h264_dma_out_ch2_dbg_data_l_reg_t out_ch2_dbg_data_l;
+    volatile h264_dma_out_ch2_dbg_data_h_reg_t out_ch2_dbg_data_h;
+    volatile h264_dma_out_ch3_dbg_data_l_reg_t out_ch3_dbg_data_l;
+    volatile h264_dma_out_ch3_dbg_data_h_reg_t out_ch3_dbg_data_h;
+    volatile h264_dma_out_ch4_dbg_data_l_reg_t out_ch4_dbg_data_l;
+    volatile h264_dma_out_ch4_dbg_data_h_reg_t out_ch4_dbg_data_h;
+    volatile h264_dma_in_ch0_dbg_data_l_reg_t in_ch0_dbg_data_l;
+    volatile h264_dma_in_ch0_dbg_data_h_reg_t in_ch0_dbg_data_h;
+    volatile h264_dma_in_ch1_dbg_data_l_reg_t in_ch1_dbg_data_l;
+    volatile h264_dma_in_ch1_dbg_data_h_reg_t in_ch1_dbg_data_h;
+    volatile h264_dma_in_ch2_dbg_data_l_reg_t in_ch2_dbg_data_l;
+    volatile h264_dma_in_ch2_dbg_data_h_reg_t in_ch2_dbg_data_h;
+    volatile h264_dma_in_ch3_dbg_data_l_reg_t in_ch3_dbg_data_l;
+    volatile h264_dma_in_ch3_dbg_data_h_reg_t in_ch3_dbg_data_h;
+    volatile h264_dma_in_ch4_dbg_data_l_reg_t in_ch4_dbg_data_l;
+    volatile h264_dma_in_ch4_dbg_data_h_reg_t in_ch4_dbg_data_h;
+    volatile h264_dma_in_ch5_dbg_data_l_reg_t in_ch5_dbg_data_l;
+    volatile h264_dma_in_ch5_dbg_data_h_reg_t in_ch5_dbg_data_h;
+} h264_dma_dev_t;
+
+extern h264_dma_dev_t H264_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(h264_dma_dev_t) == 0xbc4, "Invalid size of h264_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/h264_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/h264_reg.h
new file mode 100644
index 0000000000..9e6dbad249
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/h264_reg.h
@@ -0,0 +1,2488 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** H264_SYS_CTRL_REG register
+ *  H264 system level control register.
+ */
+#define H264_SYS_CTRL_REG (DR_REG_H264_BASE + 0x0)
+/** H264_FRAME_START : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to start encoding one frame.
+ *  0: Invalid. No effect
+ *  1: Start encoding one frame
+ */
+#define H264_FRAME_START    (BIT(0))
+#define H264_FRAME_START_M  (H264_FRAME_START_V << H264_FRAME_START_S)
+#define H264_FRAME_START_V  0x00000001U
+#define H264_FRAME_START_S  0
+/** H264_DMA_MOVE_START : WT; bitpos: [1]; default: 0;
+ *  Configures whether or not to start moving reference data from external mem.
+ *  0: Invalid. No effect
+ *  1: H264 start moving two MB lines of reference frame from external mem to internal
+ *  mem
+ */
+#define H264_DMA_MOVE_START    (BIT(1))
+#define H264_DMA_MOVE_START_M  (H264_DMA_MOVE_START_V << H264_DMA_MOVE_START_S)
+#define H264_DMA_MOVE_START_V  0x00000001U
+#define H264_DMA_MOVE_START_S  1
+/** H264_FRAME_MODE : R/W; bitpos: [2]; default: 0;
+ *  Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this
+ *  field must be set to 1 too.
+ *  0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA
+ *  1: Frame mode. Before every frame start, need reconfig reference frame DMA
+ */
+#define H264_FRAME_MODE    (BIT(2))
+#define H264_FRAME_MODE_M  (H264_FRAME_MODE_V << H264_FRAME_MODE_S)
+#define H264_FRAME_MODE_V  0x00000001U
+#define H264_FRAME_MODE_S  2
+/** H264_SYS_RST_PULSE : WT; bitpos: [3]; default: 0;
+ *  Configures whether or not to reset H264 ip.
+ *  0: Invalid. No effect
+ *  1: Reset H264 ip
+ */
+#define H264_SYS_RST_PULSE    (BIT(3))
+#define H264_SYS_RST_PULSE_M  (H264_SYS_RST_PULSE_V << H264_SYS_RST_PULSE_S)
+#define H264_SYS_RST_PULSE_V  0x00000001U
+#define H264_SYS_RST_PULSE_S  3
+
+/** H264_GOP_CONF_REG register
+ *  GOP related configuration register.
+ */
+#define H264_GOP_CONF_REG (DR_REG_H264_BASE + 0x4)
+/** H264_DUAL_STREAM_MODE : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable dual stream mode. When this field is set to 1,
+ *  H264_FRAME_MODE field must be set to 1 too.
+ *  0: Normal mode
+ *  1: Dual stream mode
+ */
+#define H264_DUAL_STREAM_MODE    (BIT(0))
+#define H264_DUAL_STREAM_MODE_M  (H264_DUAL_STREAM_MODE_V << H264_DUAL_STREAM_MODE_S)
+#define H264_DUAL_STREAM_MODE_V  0x00000001U
+#define H264_DUAL_STREAM_MODE_S  0
+/** H264_GOP_NUM : R/W; bitpos: [8:1]; default: 0;
+ *  Configures the frame number of one GOP.
+ *  0: The frame number of one GOP is infinite
+ *  Others: Actual frame number of one GOP
+ */
+#define H264_GOP_NUM    0x000000FFU
+#define H264_GOP_NUM_M  (H264_GOP_NUM_V << H264_GOP_NUM_S)
+#define H264_GOP_NUM_V  0x000000FFU
+#define H264_GOP_NUM_S  1
+
+/** H264_A_SYS_MB_RES_REG register
+ *  Video A horizontal and vertical MB resolution register.
+ */
+#define H264_A_SYS_MB_RES_REG (DR_REG_H264_BASE + 0x8)
+/** H264_A_SYS_TOTAL_MB_Y : R/W; bitpos: [6:0]; default: 0;
+ *  Configures video A vertical MB resolution.
+ */
+#define H264_A_SYS_TOTAL_MB_Y    0x0000007FU
+#define H264_A_SYS_TOTAL_MB_Y_M  (H264_A_SYS_TOTAL_MB_Y_V << H264_A_SYS_TOTAL_MB_Y_S)
+#define H264_A_SYS_TOTAL_MB_Y_V  0x0000007FU
+#define H264_A_SYS_TOTAL_MB_Y_S  0
+/** H264_A_SYS_TOTAL_MB_X : R/W; bitpos: [13:7]; default: 0;
+ *  Configures video A horizontal MB resolution.
+ */
+#define H264_A_SYS_TOTAL_MB_X    0x0000007FU
+#define H264_A_SYS_TOTAL_MB_X_M  (H264_A_SYS_TOTAL_MB_X_V << H264_A_SYS_TOTAL_MB_X_S)
+#define H264_A_SYS_TOTAL_MB_X_V  0x0000007FU
+#define H264_A_SYS_TOTAL_MB_X_S  7
+
+/** H264_A_SYS_CONF_REG register
+ *  Video A system level configuration register.
+ */
+#define H264_A_SYS_CONF_REG (DR_REG_H264_BASE + 0xc)
+/** H264_A_DB_TMP_READY_TRIGGER_MB_NUM : R/W; bitpos: [6:0]; default: 3;
+ *  Configures when to trigger  video A H264_DB_TMP_READY_INT. When the (MB number of
+ *  written db temp+1) is greater than this filed in first MB line, trigger
+ *  H264_DB_TMP_READY_INT. Min is 3.
+ */
+#define H264_A_DB_TMP_READY_TRIGGER_MB_NUM    0x0000007FU
+#define H264_A_DB_TMP_READY_TRIGGER_MB_NUM_M  (H264_A_DB_TMP_READY_TRIGGER_MB_NUM_V << H264_A_DB_TMP_READY_TRIGGER_MB_NUM_S)
+#define H264_A_DB_TMP_READY_TRIGGER_MB_NUM_V  0x0000007FU
+#define H264_A_DB_TMP_READY_TRIGGER_MB_NUM_S  0
+/** H264_A_REC_READY_TRIGGER_MB_LINES : R/W; bitpos: [13:7]; default: 4;
+ *  Configures when to trigger  video A H264_REC_READY_INT. When the MB line number of
+ *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
+ *  Min is 4.
+ */
+#define H264_A_REC_READY_TRIGGER_MB_LINES    0x0000007FU
+#define H264_A_REC_READY_TRIGGER_MB_LINES_M  (H264_A_REC_READY_TRIGGER_MB_LINES_V << H264_A_REC_READY_TRIGGER_MB_LINES_S)
+#define H264_A_REC_READY_TRIGGER_MB_LINES_V  0x0000007FU
+#define H264_A_REC_READY_TRIGGER_MB_LINES_S  7
+/** H264_A_INTRA_COST_CMP_OFFSET : R/W; bitpos: [29:14]; default: 0;
+ *  Configures video A intra cost offset when I MB compared with P MB.
+ */
+#define H264_A_INTRA_COST_CMP_OFFSET    0x0000FFFFU
+#define H264_A_INTRA_COST_CMP_OFFSET_M  (H264_A_INTRA_COST_CMP_OFFSET_V << H264_A_INTRA_COST_CMP_OFFSET_S)
+#define H264_A_INTRA_COST_CMP_OFFSET_V  0x0000FFFFU
+#define H264_A_INTRA_COST_CMP_OFFSET_S  14
+
+/** H264_A_DECI_SCORE_REG register
+ *  Video A luma and chroma MB decimate score Register.
+ */
+#define H264_A_DECI_SCORE_REG (DR_REG_H264_BASE + 0x10)
+/** H264_A_C_DECI_SCORE : R/W; bitpos: [9:0]; default: 0;
+ *  Configures video A chroma MB decimate score. When chroma score is smaller than it,
+ *  chroma decimate will be enable.
+ */
+#define H264_A_C_DECI_SCORE    0x000003FFU
+#define H264_A_C_DECI_SCORE_M  (H264_A_C_DECI_SCORE_V << H264_A_C_DECI_SCORE_S)
+#define H264_A_C_DECI_SCORE_V  0x000003FFU
+#define H264_A_C_DECI_SCORE_S  0
+/** H264_A_L_DECI_SCORE : R/W; bitpos: [19:10]; default: 0;
+ *  Configures video A luma MB decimate score. When luma score is smaller than it, luma
+ *  decimate will be enable.
+ */
+#define H264_A_L_DECI_SCORE    0x000003FFU
+#define H264_A_L_DECI_SCORE_M  (H264_A_L_DECI_SCORE_V << H264_A_L_DECI_SCORE_S)
+#define H264_A_L_DECI_SCORE_V  0x000003FFU
+#define H264_A_L_DECI_SCORE_S  10
+
+/** H264_A_DECI_SCORE_OFFSET_REG register
+ *  Video A luma and chroma MB decimate score offset Register.
+ */
+#define H264_A_DECI_SCORE_OFFSET_REG (DR_REG_H264_BASE + 0x14)
+/** H264_A_I16X16_DECI_SCORE_OFFSET : R/W; bitpos: [5:0]; default: 0;
+ *  Configures video A i16x16 MB decimate score offset. This offset will be added to
+ *  i16x16 MB score.
+ */
+#define H264_A_I16X16_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_A_I16X16_DECI_SCORE_OFFSET_M  (H264_A_I16X16_DECI_SCORE_OFFSET_V << H264_A_I16X16_DECI_SCORE_OFFSET_S)
+#define H264_A_I16X16_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_A_I16X16_DECI_SCORE_OFFSET_S  0
+/** H264_A_I_CHROMA_DECI_SCORE_OFFSET : R/W; bitpos: [11:6]; default: 0;
+ *  Configures video A I chroma MB decimate score offset. This offset will be added to
+ *  I chroma MB score.
+ */
+#define H264_A_I_CHROMA_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_A_I_CHROMA_DECI_SCORE_OFFSET_M  (H264_A_I_CHROMA_DECI_SCORE_OFFSET_V << H264_A_I_CHROMA_DECI_SCORE_OFFSET_S)
+#define H264_A_I_CHROMA_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_A_I_CHROMA_DECI_SCORE_OFFSET_S  6
+/** H264_A_P16X16_DECI_SCORE_OFFSET : R/W; bitpos: [17:12]; default: 0;
+ *  Configures video A p16x16 MB decimate score offset. This offset will be added to
+ *  p16x16 MB score.
+ */
+#define H264_A_P16X16_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_A_P16X16_DECI_SCORE_OFFSET_M  (H264_A_P16X16_DECI_SCORE_OFFSET_V << H264_A_P16X16_DECI_SCORE_OFFSET_S)
+#define H264_A_P16X16_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_A_P16X16_DECI_SCORE_OFFSET_S  12
+/** H264_A_P_CHROMA_DECI_SCORE_OFFSET : R/W; bitpos: [23:18]; default: 0;
+ *  Configures video A p chroma MB decimate score offset. This offset will be added to
+ *  p chroma MB score.
+ */
+#define H264_A_P_CHROMA_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_A_P_CHROMA_DECI_SCORE_OFFSET_M  (H264_A_P_CHROMA_DECI_SCORE_OFFSET_V << H264_A_P_CHROMA_DECI_SCORE_OFFSET_S)
+#define H264_A_P_CHROMA_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_A_P_CHROMA_DECI_SCORE_OFFSET_S  18
+
+/** H264_A_RC_CONF0_REG register
+ *  Video A rate control configuration register0.
+ */
+#define H264_A_RC_CONF0_REG (DR_REG_H264_BASE + 0x18)
+/** H264_A_QP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures video A frame level initial luma QP value.
+ */
+#define H264_A_QP    0x0000003FU
+#define H264_A_QP_M  (H264_A_QP_V << H264_A_QP_S)
+#define H264_A_QP_V  0x0000003FU
+#define H264_A_QP_S  0
+/** H264_A_RATE_CTRL_U : R/W; bitpos: [21:6]; default: 0;
+ *  Configures video A parameter U value. U = int((float) u << 8).
+ */
+#define H264_A_RATE_CTRL_U    0x0000FFFFU
+#define H264_A_RATE_CTRL_U_M  (H264_A_RATE_CTRL_U_V << H264_A_RATE_CTRL_U_S)
+#define H264_A_RATE_CTRL_U_V  0x0000FFFFU
+#define H264_A_RATE_CTRL_U_S  6
+/** H264_A_MB_RATE_CTRL_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures video A whether or not to open macro block rate ctrl.
+ *  1:Open the macro block rate ctrl
+ *  1:Close the macro block rate ctrl.
+ */
+#define H264_A_MB_RATE_CTRL_EN    (BIT(22))
+#define H264_A_MB_RATE_CTRL_EN_M  (H264_A_MB_RATE_CTRL_EN_V << H264_A_MB_RATE_CTRL_EN_S)
+#define H264_A_MB_RATE_CTRL_EN_V  0x00000001U
+#define H264_A_MB_RATE_CTRL_EN_S  22
+
+/** H264_A_RC_CONF1_REG register
+ *  Video A rate control configuration register1.
+ */
+#define H264_A_RC_CONF1_REG (DR_REG_H264_BASE + 0x1c)
+/** H264_A_CHROMA_DC_QP_DELTA : R/W; bitpos: [2:0]; default: 0;
+ *  Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
+ *  QP(after map) + reg_chroma_dc_qp_delta.
+ */
+#define H264_A_CHROMA_DC_QP_DELTA    0x00000007U
+#define H264_A_CHROMA_DC_QP_DELTA_M  (H264_A_CHROMA_DC_QP_DELTA_V << H264_A_CHROMA_DC_QP_DELTA_S)
+#define H264_A_CHROMA_DC_QP_DELTA_V  0x00000007U
+#define H264_A_CHROMA_DC_QP_DELTA_S  0
+/** H264_A_CHROMA_QP_DELTA : R/W; bitpos: [6:3]; default: 0;
+ *  Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma
+ *  QP + reg_chroma_qp_delta.
+ */
+#define H264_A_CHROMA_QP_DELTA    0x0000000FU
+#define H264_A_CHROMA_QP_DELTA_M  (H264_A_CHROMA_QP_DELTA_V << H264_A_CHROMA_QP_DELTA_S)
+#define H264_A_CHROMA_QP_DELTA_V  0x0000000FU
+#define H264_A_CHROMA_QP_DELTA_S  3
+/** H264_A_QP_MIN : R/W; bitpos: [12:7]; default: 0;
+ *  Configures video A allowed luma QP min value.
+ */
+#define H264_A_QP_MIN    0x0000003FU
+#define H264_A_QP_MIN_M  (H264_A_QP_MIN_V << H264_A_QP_MIN_S)
+#define H264_A_QP_MIN_V  0x0000003FU
+#define H264_A_QP_MIN_S  7
+/** H264_A_QP_MAX : R/W; bitpos: [18:13]; default: 0;
+ *  Configures video A allowed luma QP max value.
+ */
+#define H264_A_QP_MAX    0x0000003FU
+#define H264_A_QP_MAX_M  (H264_A_QP_MAX_V << H264_A_QP_MAX_S)
+#define H264_A_QP_MAX_V  0x0000003FU
+#define H264_A_QP_MAX_S  13
+/** H264_A_MAD_FRAME_PRED : R/W; bitpos: [30:19]; default: 0;
+ *  Configures vdieo A frame level predicted MB MAD value.
+ */
+#define H264_A_MAD_FRAME_PRED    0x00000FFFU
+#define H264_A_MAD_FRAME_PRED_M  (H264_A_MAD_FRAME_PRED_V << H264_A_MAD_FRAME_PRED_S)
+#define H264_A_MAD_FRAME_PRED_V  0x00000FFFU
+#define H264_A_MAD_FRAME_PRED_S  19
+
+/** H264_A_DB_BYPASS_REG register
+ *  Video A Deblocking bypass register
+ */
+#define H264_A_DB_BYPASS_REG (DR_REG_H264_BASE + 0x20)
+/** H264_A_BYPASS_DB_FILTER : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to bypass video A deblcoking filter.
+ *  0: Open the deblock filter
+ *  1: Close the deblock filter
+ */
+#define H264_A_BYPASS_DB_FILTER    (BIT(0))
+#define H264_A_BYPASS_DB_FILTER_M  (H264_A_BYPASS_DB_FILTER_V << H264_A_BYPASS_DB_FILTER_S)
+#define H264_A_BYPASS_DB_FILTER_V  0x00000001U
+#define H264_A_BYPASS_DB_FILTER_S  0
+
+/** H264_A_ROI_REGION0_REG register
+ *  Video A H264 ROI region0 range configure register.
+ */
+#define H264_A_ROI_REGION0_REG (DR_REG_H264_BASE + 0x24)
+/** H264_A_ROI_REGION0_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 0 in Video A.
+ */
+#define H264_A_ROI_REGION0_X    0x0000007FU
+#define H264_A_ROI_REGION0_X_M  (H264_A_ROI_REGION0_X_V << H264_A_ROI_REGION0_X_S)
+#define H264_A_ROI_REGION0_X_V  0x0000007FU
+#define H264_A_ROI_REGION0_X_S  0
+/** H264_A_ROI_REGION0_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 0 in Video A.
+ */
+#define H264_A_ROI_REGION0_Y    0x0000007FU
+#define H264_A_ROI_REGION0_Y_M  (H264_A_ROI_REGION0_Y_V << H264_A_ROI_REGION0_Y_S)
+#define H264_A_ROI_REGION0_Y_V  0x0000007FU
+#define H264_A_ROI_REGION0_Y_S  7
+/** H264_A_ROI_REGION0_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION0_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION0_X_LEN_M  (H264_A_ROI_REGION0_X_LEN_V << H264_A_ROI_REGION0_X_LEN_S)
+#define H264_A_ROI_REGION0_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION0_X_LEN_S  14
+/** H264_A_ROI_REGION0_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 0 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION0_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION0_Y_LEN_M  (H264_A_ROI_REGION0_Y_LEN_V << H264_A_ROI_REGION0_Y_LEN_S)
+#define H264_A_ROI_REGION0_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION0_Y_LEN_S  21
+/** H264_A_ROI_REGION0_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 0 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION0_EN    (BIT(28))
+#define H264_A_ROI_REGION0_EN_M  (H264_A_ROI_REGION0_EN_V << H264_A_ROI_REGION0_EN_S)
+#define H264_A_ROI_REGION0_EN_V  0x00000001U
+#define H264_A_ROI_REGION0_EN_S  28
+
+/** H264_A_ROI_REGION1_REG register
+ *  Video A H264 ROI region1 range configure register.
+ */
+#define H264_A_ROI_REGION1_REG (DR_REG_H264_BASE + 0x28)
+/** H264_A_ROI_REGION1_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 1 in Video A.
+ */
+#define H264_A_ROI_REGION1_X    0x0000007FU
+#define H264_A_ROI_REGION1_X_M  (H264_A_ROI_REGION1_X_V << H264_A_ROI_REGION1_X_S)
+#define H264_A_ROI_REGION1_X_V  0x0000007FU
+#define H264_A_ROI_REGION1_X_S  0
+/** H264_A_ROI_REGION1_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 1 in Video A.
+ */
+#define H264_A_ROI_REGION1_Y    0x0000007FU
+#define H264_A_ROI_REGION1_Y_M  (H264_A_ROI_REGION1_Y_V << H264_A_ROI_REGION1_Y_S)
+#define H264_A_ROI_REGION1_Y_V  0x0000007FU
+#define H264_A_ROI_REGION1_Y_S  7
+/** H264_A_ROI_REGION1_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION1_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION1_X_LEN_M  (H264_A_ROI_REGION1_X_LEN_V << H264_A_ROI_REGION1_X_LEN_S)
+#define H264_A_ROI_REGION1_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION1_X_LEN_S  14
+/** H264_A_ROI_REGION1_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 1 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION1_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION1_Y_LEN_M  (H264_A_ROI_REGION1_Y_LEN_V << H264_A_ROI_REGION1_Y_LEN_S)
+#define H264_A_ROI_REGION1_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION1_Y_LEN_S  21
+/** H264_A_ROI_REGION1_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 1 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION1_EN    (BIT(28))
+#define H264_A_ROI_REGION1_EN_M  (H264_A_ROI_REGION1_EN_V << H264_A_ROI_REGION1_EN_S)
+#define H264_A_ROI_REGION1_EN_V  0x00000001U
+#define H264_A_ROI_REGION1_EN_S  28
+
+/** H264_A_ROI_REGION2_REG register
+ *  Video A H264 ROI region2 range configure register.
+ */
+#define H264_A_ROI_REGION2_REG (DR_REG_H264_BASE + 0x2c)
+/** H264_A_ROI_REGION2_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 2 in Video A.
+ */
+#define H264_A_ROI_REGION2_X    0x0000007FU
+#define H264_A_ROI_REGION2_X_M  (H264_A_ROI_REGION2_X_V << H264_A_ROI_REGION2_X_S)
+#define H264_A_ROI_REGION2_X_V  0x0000007FU
+#define H264_A_ROI_REGION2_X_S  0
+/** H264_A_ROI_REGION2_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 2 in Video A.
+ */
+#define H264_A_ROI_REGION2_Y    0x0000007FU
+#define H264_A_ROI_REGION2_Y_M  (H264_A_ROI_REGION2_Y_V << H264_A_ROI_REGION2_Y_S)
+#define H264_A_ROI_REGION2_Y_V  0x0000007FU
+#define H264_A_ROI_REGION2_Y_S  7
+/** H264_A_ROI_REGION2_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION2_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION2_X_LEN_M  (H264_A_ROI_REGION2_X_LEN_V << H264_A_ROI_REGION2_X_LEN_S)
+#define H264_A_ROI_REGION2_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION2_X_LEN_S  14
+/** H264_A_ROI_REGION2_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 2 in
+ *  Video A.
+ */
+#define H264_A_ROI_REGION2_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION2_Y_LEN_M  (H264_A_ROI_REGION2_Y_LEN_V << H264_A_ROI_REGION2_Y_LEN_S)
+#define H264_A_ROI_REGION2_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION2_Y_LEN_S  21
+/** H264_A_ROI_REGION2_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 2 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION2_EN    (BIT(28))
+#define H264_A_ROI_REGION2_EN_M  (H264_A_ROI_REGION2_EN_V << H264_A_ROI_REGION2_EN_S)
+#define H264_A_ROI_REGION2_EN_V  0x00000001U
+#define H264_A_ROI_REGION2_EN_S  28
+
+/** H264_A_ROI_REGION3_REG register
+ *  Video A H264 ROI region3 range configure register.
+ */
+#define H264_A_ROI_REGION3_REG (DR_REG_H264_BASE + 0x30)
+/** H264_A_ROI_REGION3_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 3 in Video A.
+ */
+#define H264_A_ROI_REGION3_X    0x0000007FU
+#define H264_A_ROI_REGION3_X_M  (H264_A_ROI_REGION3_X_V << H264_A_ROI_REGION3_X_S)
+#define H264_A_ROI_REGION3_X_V  0x0000007FU
+#define H264_A_ROI_REGION3_X_S  0
+/** H264_A_ROI_REGION3_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 3 in Video A.
+ */
+#define H264_A_ROI_REGION3_Y    0x0000007FU
+#define H264_A_ROI_REGION3_Y_M  (H264_A_ROI_REGION3_Y_V << H264_A_ROI_REGION3_Y_S)
+#define H264_A_ROI_REGION3_Y_V  0x0000007FU
+#define H264_A_ROI_REGION3_Y_S  7
+/** H264_A_ROI_REGION3_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION3_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION3_X_LEN_M  (H264_A_ROI_REGION3_X_LEN_V << H264_A_ROI_REGION3_X_LEN_S)
+#define H264_A_ROI_REGION3_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION3_X_LEN_S  14
+/** H264_A_ROI_REGION3_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 3 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION3_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION3_Y_LEN_M  (H264_A_ROI_REGION3_Y_LEN_V << H264_A_ROI_REGION3_Y_LEN_S)
+#define H264_A_ROI_REGION3_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION3_Y_LEN_S  21
+/** H264_A_ROI_REGION3_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 3 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION3_EN    (BIT(28))
+#define H264_A_ROI_REGION3_EN_M  (H264_A_ROI_REGION3_EN_V << H264_A_ROI_REGION3_EN_S)
+#define H264_A_ROI_REGION3_EN_V  0x00000001U
+#define H264_A_ROI_REGION3_EN_S  28
+
+/** H264_A_ROI_REGION4_REG register
+ *  Video A H264 ROI region4 range configure register.
+ */
+#define H264_A_ROI_REGION4_REG (DR_REG_H264_BASE + 0x34)
+/** H264_A_ROI_REGION4_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 4 in Video A.
+ */
+#define H264_A_ROI_REGION4_X    0x0000007FU
+#define H264_A_ROI_REGION4_X_M  (H264_A_ROI_REGION4_X_V << H264_A_ROI_REGION4_X_S)
+#define H264_A_ROI_REGION4_X_V  0x0000007FU
+#define H264_A_ROI_REGION4_X_S  0
+/** H264_A_ROI_REGION4_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 4 in Video A.
+ */
+#define H264_A_ROI_REGION4_Y    0x0000007FU
+#define H264_A_ROI_REGION4_Y_M  (H264_A_ROI_REGION4_Y_V << H264_A_ROI_REGION4_Y_S)
+#define H264_A_ROI_REGION4_Y_V  0x0000007FU
+#define H264_A_ROI_REGION4_Y_S  7
+/** H264_A_ROI_REGION4_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION4_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION4_X_LEN_M  (H264_A_ROI_REGION4_X_LEN_V << H264_A_ROI_REGION4_X_LEN_S)
+#define H264_A_ROI_REGION4_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION4_X_LEN_S  14
+/** H264_A_ROI_REGION4_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 4 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION4_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION4_Y_LEN_M  (H264_A_ROI_REGION4_Y_LEN_V << H264_A_ROI_REGION4_Y_LEN_S)
+#define H264_A_ROI_REGION4_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION4_Y_LEN_S  21
+/** H264_A_ROI_REGION4_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 4 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION4_EN    (BIT(28))
+#define H264_A_ROI_REGION4_EN_M  (H264_A_ROI_REGION4_EN_V << H264_A_ROI_REGION4_EN_S)
+#define H264_A_ROI_REGION4_EN_V  0x00000001U
+#define H264_A_ROI_REGION4_EN_S  28
+
+/** H264_A_ROI_REGION5_REG register
+ *  Video A H264 ROI region5 range configure register.
+ */
+#define H264_A_ROI_REGION5_REG (DR_REG_H264_BASE + 0x38)
+/** H264_A_ROI_REGION5_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontial start macroblocks of region 5 video A.
+ */
+#define H264_A_ROI_REGION5_X    0x0000007FU
+#define H264_A_ROI_REGION5_X_M  (H264_A_ROI_REGION5_X_V << H264_A_ROI_REGION5_X_S)
+#define H264_A_ROI_REGION5_X_V  0x0000007FU
+#define H264_A_ROI_REGION5_X_S  0
+/** H264_A_ROI_REGION5_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 5 video A.
+ */
+#define H264_A_ROI_REGION5_Y    0x0000007FU
+#define H264_A_ROI_REGION5_Y_M  (H264_A_ROI_REGION5_Y_V << H264_A_ROI_REGION5_Y_S)
+#define H264_A_ROI_REGION5_Y_V  0x0000007FU
+#define H264_A_ROI_REGION5_Y_S  7
+/** H264_A_ROI_REGION5_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 5
+ *  video A.
+ */
+#define H264_A_ROI_REGION5_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION5_X_LEN_M  (H264_A_ROI_REGION5_X_LEN_V << H264_A_ROI_REGION5_X_LEN_S)
+#define H264_A_ROI_REGION5_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION5_X_LEN_S  14
+/** H264_A_ROI_REGION5_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 5 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION5_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION5_Y_LEN_M  (H264_A_ROI_REGION5_Y_LEN_V << H264_A_ROI_REGION5_Y_LEN_S)
+#define H264_A_ROI_REGION5_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION5_Y_LEN_S  21
+/** H264_A_ROI_REGION5_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 5 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION5_EN    (BIT(28))
+#define H264_A_ROI_REGION5_EN_M  (H264_A_ROI_REGION5_EN_V << H264_A_ROI_REGION5_EN_S)
+#define H264_A_ROI_REGION5_EN_V  0x00000001U
+#define H264_A_ROI_REGION5_EN_S  28
+
+/** H264_A_ROI_REGION6_REG register
+ *  Video A H264 ROI region6 range configure register.
+ */
+#define H264_A_ROI_REGION6_REG (DR_REG_H264_BASE + 0x3c)
+/** H264_A_ROI_REGION6_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontial start macroblocks of region 6 video A.
+ */
+#define H264_A_ROI_REGION6_X    0x0000007FU
+#define H264_A_ROI_REGION6_X_M  (H264_A_ROI_REGION6_X_V << H264_A_ROI_REGION6_X_S)
+#define H264_A_ROI_REGION6_X_V  0x0000007FU
+#define H264_A_ROI_REGION6_X_S  0
+/** H264_A_ROI_REGION6_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 6 in video A.
+ */
+#define H264_A_ROI_REGION6_Y    0x0000007FU
+#define H264_A_ROI_REGION6_Y_M  (H264_A_ROI_REGION6_Y_V << H264_A_ROI_REGION6_Y_S)
+#define H264_A_ROI_REGION6_Y_V  0x0000007FU
+#define H264_A_ROI_REGION6_Y_S  7
+/** H264_A_ROI_REGION6_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION6_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION6_X_LEN_M  (H264_A_ROI_REGION6_X_LEN_V << H264_A_ROI_REGION6_X_LEN_S)
+#define H264_A_ROI_REGION6_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION6_X_LEN_S  14
+/** H264_A_ROI_REGION6_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 6 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION6_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION6_Y_LEN_M  (H264_A_ROI_REGION6_Y_LEN_V << H264_A_ROI_REGION6_Y_LEN_S)
+#define H264_A_ROI_REGION6_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION6_Y_LEN_S  21
+/** H264_A_ROI_REGION6_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 6 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION6_EN    (BIT(28))
+#define H264_A_ROI_REGION6_EN_M  (H264_A_ROI_REGION6_EN_V << H264_A_ROI_REGION6_EN_S)
+#define H264_A_ROI_REGION6_EN_V  0x00000001U
+#define H264_A_ROI_REGION6_EN_S  28
+
+/** H264_A_ROI_REGION7_REG register
+ *  Video A H264 ROI region7 range configure register.
+ */
+#define H264_A_ROI_REGION7_REG (DR_REG_H264_BASE + 0x40)
+/** H264_A_ROI_REGION7_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 7 in video A.
+ */
+#define H264_A_ROI_REGION7_X    0x0000007FU
+#define H264_A_ROI_REGION7_X_M  (H264_A_ROI_REGION7_X_V << H264_A_ROI_REGION7_X_S)
+#define H264_A_ROI_REGION7_X_V  0x0000007FU
+#define H264_A_ROI_REGION7_X_S  0
+/** H264_A_ROI_REGION7_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 7 in video A.
+ */
+#define H264_A_ROI_REGION7_Y    0x0000007FU
+#define H264_A_ROI_REGION7_Y_M  (H264_A_ROI_REGION7_Y_V << H264_A_ROI_REGION7_Y_S)
+#define H264_A_ROI_REGION7_Y_V  0x0000007FU
+#define H264_A_ROI_REGION7_Y_S  7
+/** H264_A_ROI_REGION7_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION7_X_LEN    0x0000007FU
+#define H264_A_ROI_REGION7_X_LEN_M  (H264_A_ROI_REGION7_X_LEN_V << H264_A_ROI_REGION7_X_LEN_S)
+#define H264_A_ROI_REGION7_X_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION7_X_LEN_S  14
+/** H264_A_ROI_REGION7_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 7 in
+ *  video A.
+ */
+#define H264_A_ROI_REGION7_Y_LEN    0x0000007FU
+#define H264_A_ROI_REGION7_Y_LEN_M  (H264_A_ROI_REGION7_Y_LEN_V << H264_A_ROI_REGION7_Y_LEN_S)
+#define H264_A_ROI_REGION7_Y_LEN_V  0x0000007FU
+#define H264_A_ROI_REGION7_Y_LEN_S  21
+/** H264_A_ROI_REGION7_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video A ROI of region 7 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_A_ROI_REGION7_EN    (BIT(28))
+#define H264_A_ROI_REGION7_EN_M  (H264_A_ROI_REGION7_EN_V << H264_A_ROI_REGION7_EN_S)
+#define H264_A_ROI_REGION7_EN_V  0x00000001U
+#define H264_A_ROI_REGION7_EN_S  28
+
+/** H264_A_ROI_REGION0_3_QP_REG register
+ *  Video A H264 ROI region0, region1,region2,region3 QP register.
+ */
+#define H264_A_ROI_REGION0_3_QP_REG (DR_REG_H264_BASE + 0x44)
+/** H264_A_ROI_REGION0_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 ROI region0 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION0_QP    0x0000007FU
+#define H264_A_ROI_REGION0_QP_M  (H264_A_ROI_REGION0_QP_V << H264_A_ROI_REGION0_QP_S)
+#define H264_A_ROI_REGION0_QP_V  0x0000007FU
+#define H264_A_ROI_REGION0_QP_S  0
+/** H264_A_ROI_REGION1_QP : R/W; bitpos: [13:7]; default: 0;
+ *  Configure H264 ROI region1 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION1_QP    0x0000007FU
+#define H264_A_ROI_REGION1_QP_M  (H264_A_ROI_REGION1_QP_V << H264_A_ROI_REGION1_QP_S)
+#define H264_A_ROI_REGION1_QP_V  0x0000007FU
+#define H264_A_ROI_REGION1_QP_S  7
+/** H264_A_ROI_REGION2_QP : R/W; bitpos: [20:14]; default: 0;
+ *  Configure H264 ROI region2 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION2_QP    0x0000007FU
+#define H264_A_ROI_REGION2_QP_M  (H264_A_ROI_REGION2_QP_V << H264_A_ROI_REGION2_QP_S)
+#define H264_A_ROI_REGION2_QP_V  0x0000007FU
+#define H264_A_ROI_REGION2_QP_S  14
+/** H264_A_ROI_REGION3_QP : R/W; bitpos: [27:21]; default: 0;
+ *  Configure H264 ROI region3 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION3_QP    0x0000007FU
+#define H264_A_ROI_REGION3_QP_M  (H264_A_ROI_REGION3_QP_V << H264_A_ROI_REGION3_QP_S)
+#define H264_A_ROI_REGION3_QP_V  0x0000007FU
+#define H264_A_ROI_REGION3_QP_S  21
+
+/** H264_A_ROI_REGION4_7_QP_REG register
+ *  Video A H264 ROI region4, region5,region6,region7 QP register.
+ */
+#define H264_A_ROI_REGION4_7_QP_REG (DR_REG_H264_BASE + 0x48)
+/** H264_A_ROI_REGION4_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 ROI region4 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION4_QP    0x0000007FU
+#define H264_A_ROI_REGION4_QP_M  (H264_A_ROI_REGION4_QP_V << H264_A_ROI_REGION4_QP_S)
+#define H264_A_ROI_REGION4_QP_V  0x0000007FU
+#define H264_A_ROI_REGION4_QP_S  0
+/** H264_A_ROI_REGION5_QP : R/W; bitpos: [13:7]; default: 0;
+ *  Configure H264 ROI region5 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION5_QP    0x0000007FU
+#define H264_A_ROI_REGION5_QP_M  (H264_A_ROI_REGION5_QP_V << H264_A_ROI_REGION5_QP_S)
+#define H264_A_ROI_REGION5_QP_V  0x0000007FU
+#define H264_A_ROI_REGION5_QP_S  7
+/** H264_A_ROI_REGION6_QP : R/W; bitpos: [20:14]; default: 0;
+ *  Configure H264 ROI region6 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION6_QP    0x0000007FU
+#define H264_A_ROI_REGION6_QP_M  (H264_A_ROI_REGION6_QP_V << H264_A_ROI_REGION6_QP_S)
+#define H264_A_ROI_REGION6_QP_V  0x0000007FU
+#define H264_A_ROI_REGION6_QP_S  14
+/** H264_A_ROI_REGION7_QP : R/W; bitpos: [27:21]; default: 0;
+ *  Configure H264 ROI region7 qp in video A,fixed qp or delta qp.
+ */
+#define H264_A_ROI_REGION7_QP    0x0000007FU
+#define H264_A_ROI_REGION7_QP_M  (H264_A_ROI_REGION7_QP_V << H264_A_ROI_REGION7_QP_S)
+#define H264_A_ROI_REGION7_QP_V  0x0000007FU
+#define H264_A_ROI_REGION7_QP_S  21
+
+/** H264_A_NO_ROI_REGION_QP_OFFSET_REG register
+ *  Video A H264 no roi region QP register.
+ */
+#define H264_A_NO_ROI_REGION_QP_OFFSET_REG (DR_REG_H264_BASE + 0x4c)
+/** H264_A_NO_ROI_REGION_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 no region qp in video A, delta qp.
+ */
+#define H264_A_NO_ROI_REGION_QP    0x0000007FU
+#define H264_A_NO_ROI_REGION_QP_M  (H264_A_NO_ROI_REGION_QP_V << H264_A_NO_ROI_REGION_QP_S)
+#define H264_A_NO_ROI_REGION_QP_V  0x0000007FU
+#define H264_A_NO_ROI_REGION_QP_S  0
+
+/** H264_A_ROI_CONFIG_REG register
+ *  Video A H264 ROI configure register.
+ */
+#define H264_A_ROI_CONFIG_REG (DR_REG_H264_BASE + 0x50)
+/** H264_A_ROI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not to enable ROI in video A.
+ *  0:not enable ROI
+ *  1:enable ROI.
+ */
+#define H264_A_ROI_EN    (BIT(0))
+#define H264_A_ROI_EN_M  (H264_A_ROI_EN_V << H264_A_ROI_EN_S)
+#define H264_A_ROI_EN_V  0x00000001U
+#define H264_A_ROI_EN_S  0
+/** H264_A_ROI_MODE : R/W; bitpos: [1]; default: 0;
+ *  Configure the mode of ROI in video A.
+ *  0:fixed qp
+ *  1:delta qp.
+ */
+#define H264_A_ROI_MODE    (BIT(1))
+#define H264_A_ROI_MODE_M  (H264_A_ROI_MODE_V << H264_A_ROI_MODE_S)
+#define H264_A_ROI_MODE_V  0x00000001U
+#define H264_A_ROI_MODE_S  1
+
+/** H264_B_SYS_MB_RES_REG register
+ *  Video B horizontal and vertical MB resolution register.
+ */
+#define H264_B_SYS_MB_RES_REG (DR_REG_H264_BASE + 0x54)
+/** H264_B_SYS_TOTAL_MB_Y : R/W; bitpos: [6:0]; default: 0;
+ *  Configures video B vertical MB resolution.
+ */
+#define H264_B_SYS_TOTAL_MB_Y    0x0000007FU
+#define H264_B_SYS_TOTAL_MB_Y_M  (H264_B_SYS_TOTAL_MB_Y_V << H264_B_SYS_TOTAL_MB_Y_S)
+#define H264_B_SYS_TOTAL_MB_Y_V  0x0000007FU
+#define H264_B_SYS_TOTAL_MB_Y_S  0
+/** H264_B_SYS_TOTAL_MB_X : R/W; bitpos: [13:7]; default: 0;
+ *  Configures video B horizontal MB resolution.
+ */
+#define H264_B_SYS_TOTAL_MB_X    0x0000007FU
+#define H264_B_SYS_TOTAL_MB_X_M  (H264_B_SYS_TOTAL_MB_X_V << H264_B_SYS_TOTAL_MB_X_S)
+#define H264_B_SYS_TOTAL_MB_X_V  0x0000007FU
+#define H264_B_SYS_TOTAL_MB_X_S  7
+
+/** H264_B_SYS_CONF_REG register
+ *  Video B system level configuration register.
+ */
+#define H264_B_SYS_CONF_REG (DR_REG_H264_BASE + 0x58)
+/** H264_B_DB_TMP_READY_TRIGGER_MB_NUM : R/W; bitpos: [6:0]; default: 3;
+ *  Configures when to trigger  video B H264_DB_TMP_READY_INT. When the (MB number of
+ *  written db temp+1) is greater than this filed in first MB line, trigger
+ *  H264_DB_TMP_READY_INT. Min is 3.
+ */
+#define H264_B_DB_TMP_READY_TRIGGER_MB_NUM    0x0000007FU
+#define H264_B_DB_TMP_READY_TRIGGER_MB_NUM_M  (H264_B_DB_TMP_READY_TRIGGER_MB_NUM_V << H264_B_DB_TMP_READY_TRIGGER_MB_NUM_S)
+#define H264_B_DB_TMP_READY_TRIGGER_MB_NUM_V  0x0000007FU
+#define H264_B_DB_TMP_READY_TRIGGER_MB_NUM_S  0
+/** H264_B_REC_READY_TRIGGER_MB_LINES : R/W; bitpos: [13:7]; default: 4;
+ *  Configures when to trigger  video B H264_REC_READY_INT. When the MB line number of
+ *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
+ *  Min is 4.
+ */
+#define H264_B_REC_READY_TRIGGER_MB_LINES    0x0000007FU
+#define H264_B_REC_READY_TRIGGER_MB_LINES_M  (H264_B_REC_READY_TRIGGER_MB_LINES_V << H264_B_REC_READY_TRIGGER_MB_LINES_S)
+#define H264_B_REC_READY_TRIGGER_MB_LINES_V  0x0000007FU
+#define H264_B_REC_READY_TRIGGER_MB_LINES_S  7
+/** H264_B_INTRA_COST_CMP_OFFSET : R/W; bitpos: [29:14]; default: 0;
+ *  Configures video B intra cost offset when I MB compared with P MB.
+ */
+#define H264_B_INTRA_COST_CMP_OFFSET    0x0000FFFFU
+#define H264_B_INTRA_COST_CMP_OFFSET_M  (H264_B_INTRA_COST_CMP_OFFSET_V << H264_B_INTRA_COST_CMP_OFFSET_S)
+#define H264_B_INTRA_COST_CMP_OFFSET_V  0x0000FFFFU
+#define H264_B_INTRA_COST_CMP_OFFSET_S  14
+
+/** H264_B_DECI_SCORE_REG register
+ *  Video B luma and chroma MB decimate score Register.
+ */
+#define H264_B_DECI_SCORE_REG (DR_REG_H264_BASE + 0x5c)
+/** H264_B_C_DECI_SCORE : R/W; bitpos: [9:0]; default: 0;
+ *  Configures video B chroma MB decimate score. When chroma score is smaller than it,
+ *  chroma decimate will be enable.
+ */
+#define H264_B_C_DECI_SCORE    0x000003FFU
+#define H264_B_C_DECI_SCORE_M  (H264_B_C_DECI_SCORE_V << H264_B_C_DECI_SCORE_S)
+#define H264_B_C_DECI_SCORE_V  0x000003FFU
+#define H264_B_C_DECI_SCORE_S  0
+/** H264_B_L_DECI_SCORE : R/W; bitpos: [19:10]; default: 0;
+ *  Configures video B luma MB decimate score. When luma score is smaller than it, luma
+ *  decimate will be enable.
+ */
+#define H264_B_L_DECI_SCORE    0x000003FFU
+#define H264_B_L_DECI_SCORE_M  (H264_B_L_DECI_SCORE_V << H264_B_L_DECI_SCORE_S)
+#define H264_B_L_DECI_SCORE_V  0x000003FFU
+#define H264_B_L_DECI_SCORE_S  10
+
+/** H264_B_DECI_SCORE_OFFSET_REG register
+ *  Video B luma and chroma MB decimate score offset Register.
+ */
+#define H264_B_DECI_SCORE_OFFSET_REG (DR_REG_H264_BASE + 0x60)
+/** H264_B_I16X16_DECI_SCORE_OFFSET : R/W; bitpos: [5:0]; default: 0;
+ *  Configures video B i16x16 MB decimate score offset. This offset will be added to
+ *  i16x16 MB score.
+ */
+#define H264_B_I16X16_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_B_I16X16_DECI_SCORE_OFFSET_M  (H264_B_I16X16_DECI_SCORE_OFFSET_V << H264_B_I16X16_DECI_SCORE_OFFSET_S)
+#define H264_B_I16X16_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_B_I16X16_DECI_SCORE_OFFSET_S  0
+/** H264_B_I_CHROMA_DECI_SCORE_OFFSET : R/W; bitpos: [11:6]; default: 0;
+ *  Configures video B I chroma MB decimate score offset. This offset will be added to
+ *  I chroma MB score.
+ */
+#define H264_B_I_CHROMA_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_B_I_CHROMA_DECI_SCORE_OFFSET_M  (H264_B_I_CHROMA_DECI_SCORE_OFFSET_V << H264_B_I_CHROMA_DECI_SCORE_OFFSET_S)
+#define H264_B_I_CHROMA_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_B_I_CHROMA_DECI_SCORE_OFFSET_S  6
+/** H264_B_P16X16_DECI_SCORE_OFFSET : R/W; bitpos: [17:12]; default: 0;
+ *  Configures video B p16x16 MB decimate score offset. This offset will be added to
+ *  p16x16 MB score.
+ */
+#define H264_B_P16X16_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_B_P16X16_DECI_SCORE_OFFSET_M  (H264_B_P16X16_DECI_SCORE_OFFSET_V << H264_B_P16X16_DECI_SCORE_OFFSET_S)
+#define H264_B_P16X16_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_B_P16X16_DECI_SCORE_OFFSET_S  12
+/** H264_B_P_CHROMA_DECI_SCORE_OFFSET : R/W; bitpos: [23:18]; default: 0;
+ *  Configures video B p chroma MB decimate score offset. This offset will be added to
+ *  p chroma MB score.
+ */
+#define H264_B_P_CHROMA_DECI_SCORE_OFFSET    0x0000003FU
+#define H264_B_P_CHROMA_DECI_SCORE_OFFSET_M  (H264_B_P_CHROMA_DECI_SCORE_OFFSET_V << H264_B_P_CHROMA_DECI_SCORE_OFFSET_S)
+#define H264_B_P_CHROMA_DECI_SCORE_OFFSET_V  0x0000003FU
+#define H264_B_P_CHROMA_DECI_SCORE_OFFSET_S  18
+
+/** H264_B_RC_CONF0_REG register
+ *  Video B rate control configuration register0.
+ */
+#define H264_B_RC_CONF0_REG (DR_REG_H264_BASE + 0x64)
+/** H264_B_QP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures video B frame level initial luma QP value.
+ */
+#define H264_B_QP    0x0000003FU
+#define H264_B_QP_M  (H264_B_QP_V << H264_B_QP_S)
+#define H264_B_QP_V  0x0000003FU
+#define H264_B_QP_S  0
+/** H264_B_RATE_CTRL_U : R/W; bitpos: [21:6]; default: 0;
+ *  Configures video B parameter U value. U = int((float) u << 8).
+ */
+#define H264_B_RATE_CTRL_U    0x0000FFFFU
+#define H264_B_RATE_CTRL_U_M  (H264_B_RATE_CTRL_U_V << H264_B_RATE_CTRL_U_S)
+#define H264_B_RATE_CTRL_U_V  0x0000FFFFU
+#define H264_B_RATE_CTRL_U_S  6
+/** H264_B_MB_RATE_CTRL_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures video A whether or not to open macro block rate ctrl.
+ *  1:Open the macro block rate ctrl
+ *  1:Close the macro block rate ctrl.
+ */
+#define H264_B_MB_RATE_CTRL_EN    (BIT(22))
+#define H264_B_MB_RATE_CTRL_EN_M  (H264_B_MB_RATE_CTRL_EN_V << H264_B_MB_RATE_CTRL_EN_S)
+#define H264_B_MB_RATE_CTRL_EN_V  0x00000001U
+#define H264_B_MB_RATE_CTRL_EN_S  22
+
+/** H264_B_RC_CONF1_REG register
+ *  Video B rate control configuration register1.
+ */
+#define H264_B_RC_CONF1_REG (DR_REG_H264_BASE + 0x68)
+/** H264_B_CHROMA_DC_QP_DELTA : R/W; bitpos: [2:0]; default: 0;
+ *  Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
+ *  QP(after map) + reg_chroma_dc_qp_delta.
+ */
+#define H264_B_CHROMA_DC_QP_DELTA    0x00000007U
+#define H264_B_CHROMA_DC_QP_DELTA_M  (H264_B_CHROMA_DC_QP_DELTA_V << H264_B_CHROMA_DC_QP_DELTA_S)
+#define H264_B_CHROMA_DC_QP_DELTA_V  0x00000007U
+#define H264_B_CHROMA_DC_QP_DELTA_S  0
+/** H264_B_CHROMA_QP_DELTA : R/W; bitpos: [6:3]; default: 0;
+ *  Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma
+ *  QP + reg_chroma_qp_delta.
+ */
+#define H264_B_CHROMA_QP_DELTA    0x0000000FU
+#define H264_B_CHROMA_QP_DELTA_M  (H264_B_CHROMA_QP_DELTA_V << H264_B_CHROMA_QP_DELTA_S)
+#define H264_B_CHROMA_QP_DELTA_V  0x0000000FU
+#define H264_B_CHROMA_QP_DELTA_S  3
+/** H264_B_QP_MIN : R/W; bitpos: [12:7]; default: 0;
+ *  Configures video B allowed luma QP min value.
+ */
+#define H264_B_QP_MIN    0x0000003FU
+#define H264_B_QP_MIN_M  (H264_B_QP_MIN_V << H264_B_QP_MIN_S)
+#define H264_B_QP_MIN_V  0x0000003FU
+#define H264_B_QP_MIN_S  7
+/** H264_B_QP_MAX : R/W; bitpos: [18:13]; default: 0;
+ *  Configures video B allowed luma QP max value.
+ */
+#define H264_B_QP_MAX    0x0000003FU
+#define H264_B_QP_MAX_M  (H264_B_QP_MAX_V << H264_B_QP_MAX_S)
+#define H264_B_QP_MAX_V  0x0000003FU
+#define H264_B_QP_MAX_S  13
+/** H264_B_MAD_FRAME_PRED : R/W; bitpos: [30:19]; default: 0;
+ *  Configures vdieo B frame level predicted MB MAD value.
+ */
+#define H264_B_MAD_FRAME_PRED    0x00000FFFU
+#define H264_B_MAD_FRAME_PRED_M  (H264_B_MAD_FRAME_PRED_V << H264_B_MAD_FRAME_PRED_S)
+#define H264_B_MAD_FRAME_PRED_V  0x00000FFFU
+#define H264_B_MAD_FRAME_PRED_S  19
+
+/** H264_B_DB_BYPASS_REG register
+ *  Video B Deblocking bypass register
+ */
+#define H264_B_DB_BYPASS_REG (DR_REG_H264_BASE + 0x6c)
+/** H264_B_BYPASS_DB_FILTER : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to bypass video B deblcoking filter.
+ *  0: Open the deblock filter
+ *  1: Close the deblock filter
+ */
+#define H264_B_BYPASS_DB_FILTER    (BIT(0))
+#define H264_B_BYPASS_DB_FILTER_M  (H264_B_BYPASS_DB_FILTER_V << H264_B_BYPASS_DB_FILTER_S)
+#define H264_B_BYPASS_DB_FILTER_V  0x00000001U
+#define H264_B_BYPASS_DB_FILTER_S  0
+
+/** H264_B_ROI_REGION0_REG register
+ *  Video B H264 ROI region0 range configure register.
+ */
+#define H264_B_ROI_REGION0_REG (DR_REG_H264_BASE + 0x70)
+/** H264_B_ROI_REGION0_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 0 in Video B.
+ */
+#define H264_B_ROI_REGION0_X    0x0000007FU
+#define H264_B_ROI_REGION0_X_M  (H264_B_ROI_REGION0_X_V << H264_B_ROI_REGION0_X_S)
+#define H264_B_ROI_REGION0_X_V  0x0000007FU
+#define H264_B_ROI_REGION0_X_S  0
+/** H264_B_ROI_REGION0_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 0 in Video B.
+ */
+#define H264_B_ROI_REGION0_Y    0x0000007FU
+#define H264_B_ROI_REGION0_Y_M  (H264_B_ROI_REGION0_Y_V << H264_B_ROI_REGION0_Y_S)
+#define H264_B_ROI_REGION0_Y_V  0x0000007FU
+#define H264_B_ROI_REGION0_Y_S  7
+/** H264_B_ROI_REGION0_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION0_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION0_X_LEN_M  (H264_B_ROI_REGION0_X_LEN_V << H264_B_ROI_REGION0_X_LEN_S)
+#define H264_B_ROI_REGION0_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION0_X_LEN_S  14
+/** H264_B_ROI_REGION0_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 0 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION0_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION0_Y_LEN_M  (H264_B_ROI_REGION0_Y_LEN_V << H264_B_ROI_REGION0_Y_LEN_S)
+#define H264_B_ROI_REGION0_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION0_Y_LEN_S  21
+/** H264_B_ROI_REGION0_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 0 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION0_EN    (BIT(28))
+#define H264_B_ROI_REGION0_EN_M  (H264_B_ROI_REGION0_EN_V << H264_B_ROI_REGION0_EN_S)
+#define H264_B_ROI_REGION0_EN_V  0x00000001U
+#define H264_B_ROI_REGION0_EN_S  28
+
+/** H264_B_ROI_REGION1_REG register
+ *  Video B H264 ROI region1 range configure register.
+ */
+#define H264_B_ROI_REGION1_REG (DR_REG_H264_BASE + 0x74)
+/** H264_B_ROI_REGION1_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 1 in Video B.
+ */
+#define H264_B_ROI_REGION1_X    0x0000007FU
+#define H264_B_ROI_REGION1_X_M  (H264_B_ROI_REGION1_X_V << H264_B_ROI_REGION1_X_S)
+#define H264_B_ROI_REGION1_X_V  0x0000007FU
+#define H264_B_ROI_REGION1_X_S  0
+/** H264_B_ROI_REGION1_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 1 in Video B.
+ */
+#define H264_B_ROI_REGION1_Y    0x0000007FU
+#define H264_B_ROI_REGION1_Y_M  (H264_B_ROI_REGION1_Y_V << H264_B_ROI_REGION1_Y_S)
+#define H264_B_ROI_REGION1_Y_V  0x0000007FU
+#define H264_B_ROI_REGION1_Y_S  7
+/** H264_B_ROI_REGION1_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION1_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION1_X_LEN_M  (H264_B_ROI_REGION1_X_LEN_V << H264_B_ROI_REGION1_X_LEN_S)
+#define H264_B_ROI_REGION1_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION1_X_LEN_S  14
+/** H264_B_ROI_REGION1_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 1 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION1_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION1_Y_LEN_M  (H264_B_ROI_REGION1_Y_LEN_V << H264_B_ROI_REGION1_Y_LEN_S)
+#define H264_B_ROI_REGION1_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION1_Y_LEN_S  21
+/** H264_B_ROI_REGION1_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 1 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION1_EN    (BIT(28))
+#define H264_B_ROI_REGION1_EN_M  (H264_B_ROI_REGION1_EN_V << H264_B_ROI_REGION1_EN_S)
+#define H264_B_ROI_REGION1_EN_V  0x00000001U
+#define H264_B_ROI_REGION1_EN_S  28
+
+/** H264_B_ROI_REGION2_REG register
+ *  Video B H264 ROI region2 range configure register.
+ */
+#define H264_B_ROI_REGION2_REG (DR_REG_H264_BASE + 0x78)
+/** H264_B_ROI_REGION2_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 2 in Video B.
+ */
+#define H264_B_ROI_REGION2_X    0x0000007FU
+#define H264_B_ROI_REGION2_X_M  (H264_B_ROI_REGION2_X_V << H264_B_ROI_REGION2_X_S)
+#define H264_B_ROI_REGION2_X_V  0x0000007FU
+#define H264_B_ROI_REGION2_X_S  0
+/** H264_B_ROI_REGION2_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 2 in Video B.
+ */
+#define H264_B_ROI_REGION2_Y    0x0000007FU
+#define H264_B_ROI_REGION2_Y_M  (H264_B_ROI_REGION2_Y_V << H264_B_ROI_REGION2_Y_S)
+#define H264_B_ROI_REGION2_Y_V  0x0000007FU
+#define H264_B_ROI_REGION2_Y_S  7
+/** H264_B_ROI_REGION2_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION2_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION2_X_LEN_M  (H264_B_ROI_REGION2_X_LEN_V << H264_B_ROI_REGION2_X_LEN_S)
+#define H264_B_ROI_REGION2_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION2_X_LEN_S  14
+/** H264_B_ROI_REGION2_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 2 in
+ *  Video B.
+ */
+#define H264_B_ROI_REGION2_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION2_Y_LEN_M  (H264_B_ROI_REGION2_Y_LEN_V << H264_B_ROI_REGION2_Y_LEN_S)
+#define H264_B_ROI_REGION2_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION2_Y_LEN_S  21
+/** H264_B_ROI_REGION2_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 2 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION2_EN    (BIT(28))
+#define H264_B_ROI_REGION2_EN_M  (H264_B_ROI_REGION2_EN_V << H264_B_ROI_REGION2_EN_S)
+#define H264_B_ROI_REGION2_EN_V  0x00000001U
+#define H264_B_ROI_REGION2_EN_S  28
+
+/** H264_B_ROI_REGION3_REG register
+ *  Video B H264 ROI region3 range configure register.
+ */
+#define H264_B_ROI_REGION3_REG (DR_REG_H264_BASE + 0x7c)
+/** H264_B_ROI_REGION3_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 3 in Video B.
+ */
+#define H264_B_ROI_REGION3_X    0x0000007FU
+#define H264_B_ROI_REGION3_X_M  (H264_B_ROI_REGION3_X_V << H264_B_ROI_REGION3_X_S)
+#define H264_B_ROI_REGION3_X_V  0x0000007FU
+#define H264_B_ROI_REGION3_X_S  0
+/** H264_B_ROI_REGION3_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 3 in Video B.
+ */
+#define H264_B_ROI_REGION3_Y    0x0000007FU
+#define H264_B_ROI_REGION3_Y_M  (H264_B_ROI_REGION3_Y_V << H264_B_ROI_REGION3_Y_S)
+#define H264_B_ROI_REGION3_Y_V  0x0000007FU
+#define H264_B_ROI_REGION3_Y_S  7
+/** H264_B_ROI_REGION3_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION3_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION3_X_LEN_M  (H264_B_ROI_REGION3_X_LEN_V << H264_B_ROI_REGION3_X_LEN_S)
+#define H264_B_ROI_REGION3_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION3_X_LEN_S  14
+/** H264_B_ROI_REGION3_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 3 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION3_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION3_Y_LEN_M  (H264_B_ROI_REGION3_Y_LEN_V << H264_B_ROI_REGION3_Y_LEN_S)
+#define H264_B_ROI_REGION3_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION3_Y_LEN_S  21
+/** H264_B_ROI_REGION3_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 3 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION3_EN    (BIT(28))
+#define H264_B_ROI_REGION3_EN_M  (H264_B_ROI_REGION3_EN_V << H264_B_ROI_REGION3_EN_S)
+#define H264_B_ROI_REGION3_EN_V  0x00000001U
+#define H264_B_ROI_REGION3_EN_S  28
+
+/** H264_B_ROI_REGION4_REG register
+ *  Video B H264 ROI region4 range configure register.
+ */
+#define H264_B_ROI_REGION4_REG (DR_REG_H264_BASE + 0x80)
+/** H264_B_ROI_REGION4_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 4 in Video B.
+ */
+#define H264_B_ROI_REGION4_X    0x0000007FU
+#define H264_B_ROI_REGION4_X_M  (H264_B_ROI_REGION4_X_V << H264_B_ROI_REGION4_X_S)
+#define H264_B_ROI_REGION4_X_V  0x0000007FU
+#define H264_B_ROI_REGION4_X_S  0
+/** H264_B_ROI_REGION4_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 4 in Video B.
+ */
+#define H264_B_ROI_REGION4_Y    0x0000007FU
+#define H264_B_ROI_REGION4_Y_M  (H264_B_ROI_REGION4_Y_V << H264_B_ROI_REGION4_Y_S)
+#define H264_B_ROI_REGION4_Y_V  0x0000007FU
+#define H264_B_ROI_REGION4_Y_S  7
+/** H264_B_ROI_REGION4_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION4_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION4_X_LEN_M  (H264_B_ROI_REGION4_X_LEN_V << H264_B_ROI_REGION4_X_LEN_S)
+#define H264_B_ROI_REGION4_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION4_X_LEN_S  14
+/** H264_B_ROI_REGION4_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 4 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION4_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION4_Y_LEN_M  (H264_B_ROI_REGION4_Y_LEN_V << H264_B_ROI_REGION4_Y_LEN_S)
+#define H264_B_ROI_REGION4_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION4_Y_LEN_S  21
+/** H264_B_ROI_REGION4_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 4 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION4_EN    (BIT(28))
+#define H264_B_ROI_REGION4_EN_M  (H264_B_ROI_REGION4_EN_V << H264_B_ROI_REGION4_EN_S)
+#define H264_B_ROI_REGION4_EN_V  0x00000001U
+#define H264_B_ROI_REGION4_EN_S  28
+
+/** H264_B_ROI_REGION5_REG register
+ *  Video B H264 ROI region5 range configure register.
+ */
+#define H264_B_ROI_REGION5_REG (DR_REG_H264_BASE + 0x84)
+/** H264_B_ROI_REGION5_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontial start macroblocks of region 5 video B.
+ */
+#define H264_B_ROI_REGION5_X    0x0000007FU
+#define H264_B_ROI_REGION5_X_M  (H264_B_ROI_REGION5_X_V << H264_B_ROI_REGION5_X_S)
+#define H264_B_ROI_REGION5_X_V  0x0000007FU
+#define H264_B_ROI_REGION5_X_S  0
+/** H264_B_ROI_REGION5_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 5 video B.
+ */
+#define H264_B_ROI_REGION5_Y    0x0000007FU
+#define H264_B_ROI_REGION5_Y_M  (H264_B_ROI_REGION5_Y_V << H264_B_ROI_REGION5_Y_S)
+#define H264_B_ROI_REGION5_Y_V  0x0000007FU
+#define H264_B_ROI_REGION5_Y_S  7
+/** H264_B_ROI_REGION5_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 5
+ *  video B.
+ */
+#define H264_B_ROI_REGION5_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION5_X_LEN_M  (H264_B_ROI_REGION5_X_LEN_V << H264_B_ROI_REGION5_X_LEN_S)
+#define H264_B_ROI_REGION5_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION5_X_LEN_S  14
+/** H264_B_ROI_REGION5_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 5 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION5_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION5_Y_LEN_M  (H264_B_ROI_REGION5_Y_LEN_V << H264_B_ROI_REGION5_Y_LEN_S)
+#define H264_B_ROI_REGION5_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION5_Y_LEN_S  21
+/** H264_B_ROI_REGION5_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 5 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION5_EN    (BIT(28))
+#define H264_B_ROI_REGION5_EN_M  (H264_B_ROI_REGION5_EN_V << H264_B_ROI_REGION5_EN_S)
+#define H264_B_ROI_REGION5_EN_V  0x00000001U
+#define H264_B_ROI_REGION5_EN_S  28
+
+/** H264_B_ROI_REGION6_REG register
+ *  Video B H264 ROI region6 range configure register.
+ */
+#define H264_B_ROI_REGION6_REG (DR_REG_H264_BASE + 0x88)
+/** H264_B_ROI_REGION6_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontial start macroblocks of region 6 video B.
+ */
+#define H264_B_ROI_REGION6_X    0x0000007FU
+#define H264_B_ROI_REGION6_X_M  (H264_B_ROI_REGION6_X_V << H264_B_ROI_REGION6_X_S)
+#define H264_B_ROI_REGION6_X_V  0x0000007FU
+#define H264_B_ROI_REGION6_X_S  0
+/** H264_B_ROI_REGION6_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 6 in video B.
+ */
+#define H264_B_ROI_REGION6_Y    0x0000007FU
+#define H264_B_ROI_REGION6_Y_M  (H264_B_ROI_REGION6_Y_V << H264_B_ROI_REGION6_Y_S)
+#define H264_B_ROI_REGION6_Y_V  0x0000007FU
+#define H264_B_ROI_REGION6_Y_S  7
+/** H264_B_ROI_REGION6_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION6_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION6_X_LEN_M  (H264_B_ROI_REGION6_X_LEN_V << H264_B_ROI_REGION6_X_LEN_S)
+#define H264_B_ROI_REGION6_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION6_X_LEN_S  14
+/** H264_B_ROI_REGION6_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 6 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION6_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION6_Y_LEN_M  (H264_B_ROI_REGION6_Y_LEN_V << H264_B_ROI_REGION6_Y_LEN_S)
+#define H264_B_ROI_REGION6_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION6_Y_LEN_S  21
+/** H264_B_ROI_REGION6_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 6 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION6_EN    (BIT(28))
+#define H264_B_ROI_REGION6_EN_M  (H264_B_ROI_REGION6_EN_V << H264_B_ROI_REGION6_EN_S)
+#define H264_B_ROI_REGION6_EN_V  0x00000001U
+#define H264_B_ROI_REGION6_EN_S  28
+
+/** H264_B_ROI_REGION7_REG register
+ *  Video B H264 ROI region7 range configure register.
+ */
+#define H264_B_ROI_REGION7_REG (DR_REG_H264_BASE + 0x8c)
+/** H264_B_ROI_REGION7_X : R/W; bitpos: [6:0]; default: 0;
+ *  Configures the horizontal start macroblocks of region 7 in video B.
+ */
+#define H264_B_ROI_REGION7_X    0x0000007FU
+#define H264_B_ROI_REGION7_X_M  (H264_B_ROI_REGION7_X_V << H264_B_ROI_REGION7_X_S)
+#define H264_B_ROI_REGION7_X_V  0x0000007FU
+#define H264_B_ROI_REGION7_X_S  0
+/** H264_B_ROI_REGION7_Y : R/W; bitpos: [13:7]; default: 0;
+ *  Configures the  vertical start macroblocks of region 7 in video B.
+ */
+#define H264_B_ROI_REGION7_Y    0x0000007FU
+#define H264_B_ROI_REGION7_Y_M  (H264_B_ROI_REGION7_Y_V << H264_B_ROI_REGION7_Y_S)
+#define H264_B_ROI_REGION7_Y_V  0x0000007FU
+#define H264_B_ROI_REGION7_Y_S  7
+/** H264_B_ROI_REGION7_X_LEN : R/W; bitpos: [20:14]; default: 0;
+ *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION7_X_LEN    0x0000007FU
+#define H264_B_ROI_REGION7_X_LEN_M  (H264_B_ROI_REGION7_X_LEN_V << H264_B_ROI_REGION7_X_LEN_S)
+#define H264_B_ROI_REGION7_X_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION7_X_LEN_S  14
+/** H264_B_ROI_REGION7_Y_LEN : R/W; bitpos: [27:21]; default: 0;
+ *  Configures the number of  macroblocks in vertical direction of  the region 7 in
+ *  video B.
+ */
+#define H264_B_ROI_REGION7_Y_LEN    0x0000007FU
+#define H264_B_ROI_REGION7_Y_LEN_M  (H264_B_ROI_REGION7_Y_LEN_V << H264_B_ROI_REGION7_Y_LEN_S)
+#define H264_B_ROI_REGION7_Y_LEN_V  0x0000007FU
+#define H264_B_ROI_REGION7_Y_LEN_S  21
+/** H264_B_ROI_REGION7_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to open Video B ROI of region 7 .
+ *  0:Close ROI
+ *  1:Open ROI.
+ */
+#define H264_B_ROI_REGION7_EN    (BIT(28))
+#define H264_B_ROI_REGION7_EN_M  (H264_B_ROI_REGION7_EN_V << H264_B_ROI_REGION7_EN_S)
+#define H264_B_ROI_REGION7_EN_V  0x00000001U
+#define H264_B_ROI_REGION7_EN_S  28
+
+/** H264_B_ROI_REGION0_3_QP_REG register
+ *  Video B H264 ROI region0, region1,region2,region3 QP register.
+ */
+#define H264_B_ROI_REGION0_3_QP_REG (DR_REG_H264_BASE + 0x90)
+/** H264_B_ROI_REGION0_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 ROI region0 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION0_QP    0x0000007FU
+#define H264_B_ROI_REGION0_QP_M  (H264_B_ROI_REGION0_QP_V << H264_B_ROI_REGION0_QP_S)
+#define H264_B_ROI_REGION0_QP_V  0x0000007FU
+#define H264_B_ROI_REGION0_QP_S  0
+/** H264_B_ROI_REGION1_QP : R/W; bitpos: [13:7]; default: 0;
+ *  Configure H264 ROI region1 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION1_QP    0x0000007FU
+#define H264_B_ROI_REGION1_QP_M  (H264_B_ROI_REGION1_QP_V << H264_B_ROI_REGION1_QP_S)
+#define H264_B_ROI_REGION1_QP_V  0x0000007FU
+#define H264_B_ROI_REGION1_QP_S  7
+/** H264_B_ROI_REGION2_QP : R/W; bitpos: [20:14]; default: 0;
+ *  Configure H264 ROI region2 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION2_QP    0x0000007FU
+#define H264_B_ROI_REGION2_QP_M  (H264_B_ROI_REGION2_QP_V << H264_B_ROI_REGION2_QP_S)
+#define H264_B_ROI_REGION2_QP_V  0x0000007FU
+#define H264_B_ROI_REGION2_QP_S  14
+/** H264_B_ROI_REGION3_QP : R/W; bitpos: [27:21]; default: 0;
+ *  Configure H264 ROI region3 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION3_QP    0x0000007FU
+#define H264_B_ROI_REGION3_QP_M  (H264_B_ROI_REGION3_QP_V << H264_B_ROI_REGION3_QP_S)
+#define H264_B_ROI_REGION3_QP_V  0x0000007FU
+#define H264_B_ROI_REGION3_QP_S  21
+
+/** H264_B_ROI_REGION4_7_QP_REG register
+ *  Video B H264 ROI region4, region5,region6,region7 QP register.
+ */
+#define H264_B_ROI_REGION4_7_QP_REG (DR_REG_H264_BASE + 0x94)
+/** H264_B_ROI_REGION4_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 ROI region4 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION4_QP    0x0000007FU
+#define H264_B_ROI_REGION4_QP_M  (H264_B_ROI_REGION4_QP_V << H264_B_ROI_REGION4_QP_S)
+#define H264_B_ROI_REGION4_QP_V  0x0000007FU
+#define H264_B_ROI_REGION4_QP_S  0
+/** H264_B_ROI_REGION5_QP : R/W; bitpos: [13:7]; default: 0;
+ *  Configure H264 ROI region5 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION5_QP    0x0000007FU
+#define H264_B_ROI_REGION5_QP_M  (H264_B_ROI_REGION5_QP_V << H264_B_ROI_REGION5_QP_S)
+#define H264_B_ROI_REGION5_QP_V  0x0000007FU
+#define H264_B_ROI_REGION5_QP_S  7
+/** H264_B_ROI_REGION6_QP : R/W; bitpos: [20:14]; default: 0;
+ *  Configure H264 ROI region6 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION6_QP    0x0000007FU
+#define H264_B_ROI_REGION6_QP_M  (H264_B_ROI_REGION6_QP_V << H264_B_ROI_REGION6_QP_S)
+#define H264_B_ROI_REGION6_QP_V  0x0000007FU
+#define H264_B_ROI_REGION6_QP_S  14
+/** H264_B_ROI_REGION7_QP : R/W; bitpos: [27:21]; default: 0;
+ *  Configure H264 ROI region7 qp in video B,fixed qp or delta qp.
+ */
+#define H264_B_ROI_REGION7_QP    0x0000007FU
+#define H264_B_ROI_REGION7_QP_M  (H264_B_ROI_REGION7_QP_V << H264_B_ROI_REGION7_QP_S)
+#define H264_B_ROI_REGION7_QP_V  0x0000007FU
+#define H264_B_ROI_REGION7_QP_S  21
+
+/** H264_B_NO_ROI_REGION_QP_OFFSET_REG register
+ *  Video B H264 no roi region QP register.
+ */
+#define H264_B_NO_ROI_REGION_QP_OFFSET_REG (DR_REG_H264_BASE + 0x98)
+/** H264_B_NO_ROI_REGION_QP : R/W; bitpos: [6:0]; default: 0;
+ *  Configure H264 no region qp in video B, delta qp.
+ */
+#define H264_B_NO_ROI_REGION_QP    0x0000007FU
+#define H264_B_NO_ROI_REGION_QP_M  (H264_B_NO_ROI_REGION_QP_V << H264_B_NO_ROI_REGION_QP_S)
+#define H264_B_NO_ROI_REGION_QP_V  0x0000007FU
+#define H264_B_NO_ROI_REGION_QP_S  0
+
+/** H264_B_ROI_CONFIG_REG register
+ *  Video B H264 ROI configure register.
+ */
+#define H264_B_ROI_CONFIG_REG (DR_REG_H264_BASE + 0x9c)
+/** H264_B_ROI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether or not to enable ROI in video B.
+ *  0:not enable ROI
+ *  1:enable ROI.
+ */
+#define H264_B_ROI_EN    (BIT(0))
+#define H264_B_ROI_EN_M  (H264_B_ROI_EN_V << H264_B_ROI_EN_S)
+#define H264_B_ROI_EN_V  0x00000001U
+#define H264_B_ROI_EN_S  0
+/** H264_B_ROI_MODE : R/W; bitpos: [1]; default: 0;
+ *  Configure the mode of ROI in video B.
+ *  0:fixed qp
+ *  1:delta qp.
+ */
+#define H264_B_ROI_MODE    (BIT(1))
+#define H264_B_ROI_MODE_M  (H264_B_ROI_MODE_V << H264_B_ROI_MODE_S)
+#define H264_B_ROI_MODE_V  0x00000001U
+#define H264_B_ROI_MODE_S  1
+
+/** H264_RC_STATUS0_REG register
+ *  Rate control status register0.
+ */
+#define H264_RC_STATUS0_REG (DR_REG_H264_BASE + 0xa0)
+/** H264_FRAME_MAD_SUM : RO; bitpos: [20:0]; default: 0;
+ *  Represents all MB actual MAD sum value of one frame.
+ */
+#define H264_FRAME_MAD_SUM    0x001FFFFFU
+#define H264_FRAME_MAD_SUM_M  (H264_FRAME_MAD_SUM_V << H264_FRAME_MAD_SUM_S)
+#define H264_FRAME_MAD_SUM_V  0x001FFFFFU
+#define H264_FRAME_MAD_SUM_S  0
+
+/** H264_RC_STATUS1_REG register
+ *  Rate control status register1.
+ */
+#define H264_RC_STATUS1_REG (DR_REG_H264_BASE + 0xa4)
+/** H264_FRAME_ENC_BITS : RO; bitpos: [26:0]; default: 0;
+ *  Represents all MB actual encoding bits sum value of one frame.
+ */
+#define H264_FRAME_ENC_BITS    0x07FFFFFFU
+#define H264_FRAME_ENC_BITS_M  (H264_FRAME_ENC_BITS_V << H264_FRAME_ENC_BITS_S)
+#define H264_FRAME_ENC_BITS_V  0x07FFFFFFU
+#define H264_FRAME_ENC_BITS_S  0
+
+/** H264_RC_STATUS2_REG register
+ *  Rate control status register2.
+ */
+#define H264_RC_STATUS2_REG (DR_REG_H264_BASE + 0xa8)
+/** H264_FRAME_QP_SUM : RO; bitpos: [18:0]; default: 0;
+ *  Represents all MB actual luma QP sum value of one frame.
+ */
+#define H264_FRAME_QP_SUM    0x0007FFFFU
+#define H264_FRAME_QP_SUM_M  (H264_FRAME_QP_SUM_V << H264_FRAME_QP_SUM_S)
+#define H264_FRAME_QP_SUM_V  0x0007FFFFU
+#define H264_FRAME_QP_SUM_S  0
+
+/** H264_SLICE_HEADER_REMAIN_REG register
+ *  Frame Slice Header remain bit register.
+ */
+#define H264_SLICE_HEADER_REMAIN_REG (DR_REG_H264_BASE + 0xac)
+/** H264_SLICE_REMAIN_BITLENGTH : R/W; bitpos: [2:0]; default: 0;
+ *  Configures Slice Header remain bit number
+ */
+#define H264_SLICE_REMAIN_BITLENGTH    0x00000007U
+#define H264_SLICE_REMAIN_BITLENGTH_M  (H264_SLICE_REMAIN_BITLENGTH_V << H264_SLICE_REMAIN_BITLENGTH_S)
+#define H264_SLICE_REMAIN_BITLENGTH_V  0x00000007U
+#define H264_SLICE_REMAIN_BITLENGTH_S  0
+/** H264_SLICE_REMAIN_BIT : R/W; bitpos: [10:3]; default: 0;
+ *  Configures Slice Header remain bit
+ */
+#define H264_SLICE_REMAIN_BIT    0x000000FFU
+#define H264_SLICE_REMAIN_BIT_M  (H264_SLICE_REMAIN_BIT_V << H264_SLICE_REMAIN_BIT_S)
+#define H264_SLICE_REMAIN_BIT_V  0x000000FFU
+#define H264_SLICE_REMAIN_BIT_S  3
+
+/** H264_SLICE_HEADER_BYTE_LENGTH_REG register
+ *  Frame Slice Header byte length register.
+ */
+#define H264_SLICE_HEADER_BYTE_LENGTH_REG (DR_REG_H264_BASE + 0xb0)
+/** H264_SLICE_BYTE_LENGTH : R/W; bitpos: [3:0]; default: 0;
+ *  Configures Slice Header byte number
+ */
+#define H264_SLICE_BYTE_LENGTH    0x0000000FU
+#define H264_SLICE_BYTE_LENGTH_M  (H264_SLICE_BYTE_LENGTH_V << H264_SLICE_BYTE_LENGTH_S)
+#define H264_SLICE_BYTE_LENGTH_V  0x0000000FU
+#define H264_SLICE_BYTE_LENGTH_S  0
+
+/** H264_BS_THRESHOLD_REG register
+ *  Bitstream buffer overflow threshold register
+ */
+#define H264_BS_THRESHOLD_REG (DR_REG_H264_BASE + 0xb4)
+/** H264_BS_BUFFER_THRESHOLD : R/W; bitpos: [6:0]; default: 48;
+ *  Configures bitstream buffer overflow threshold. This value should be bigger than
+ *  the encode bytes of one 4x4 submb.
+ */
+#define H264_BS_BUFFER_THRESHOLD    0x0000007FU
+#define H264_BS_BUFFER_THRESHOLD_M  (H264_BS_BUFFER_THRESHOLD_V << H264_BS_BUFFER_THRESHOLD_S)
+#define H264_BS_BUFFER_THRESHOLD_V  0x0000007FU
+#define H264_BS_BUFFER_THRESHOLD_S  0
+
+/** H264_SLICE_HEADER_BYTE0_REG register
+ *  Frame Slice Header byte low 32 bit  register.
+ */
+#define H264_SLICE_HEADER_BYTE0_REG (DR_REG_H264_BASE + 0xb8)
+/** H264_SLICE_BYTE_LSB : R/W; bitpos: [31:0]; default: 0;
+ *  Configures Slice Header low 32 bit
+ */
+#define H264_SLICE_BYTE_LSB    0xFFFFFFFFU
+#define H264_SLICE_BYTE_LSB_M  (H264_SLICE_BYTE_LSB_V << H264_SLICE_BYTE_LSB_S)
+#define H264_SLICE_BYTE_LSB_V  0xFFFFFFFFU
+#define H264_SLICE_BYTE_LSB_S  0
+
+/** H264_SLICE_HEADER_BYTE1_REG register
+ *  Frame Slice Header byte high 32 bit  register.
+ */
+#define H264_SLICE_HEADER_BYTE1_REG (DR_REG_H264_BASE + 0xbc)
+/** H264_SLICE_BYTE_MSB : R/W; bitpos: [31:0]; default: 0;
+ *  Configures Slice Header high 32 bit
+ */
+#define H264_SLICE_BYTE_MSB    0xFFFFFFFFU
+#define H264_SLICE_BYTE_MSB_M  (H264_SLICE_BYTE_MSB_V << H264_SLICE_BYTE_MSB_S)
+#define H264_SLICE_BYTE_MSB_V  0xFFFFFFFFU
+#define H264_SLICE_BYTE_MSB_S  0
+
+/** H264_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define H264_INT_RAW_REG (DR_REG_H264_BASE + 0xc0)
+/** H264_DB_TMP_READY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Raw status bit: The raw interrupt status of  H264_DB_TMP_READY_INT. Triggered when
+ *  H264 written enough db tmp pixel.
+ */
+#define H264_DB_TMP_READY_INT_RAW    (BIT(0))
+#define H264_DB_TMP_READY_INT_RAW_M  (H264_DB_TMP_READY_INT_RAW_V << H264_DB_TMP_READY_INT_RAW_S)
+#define H264_DB_TMP_READY_INT_RAW_V  0x00000001U
+#define H264_DB_TMP_READY_INT_RAW_S  0
+/** H264_REC_READY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Raw status bit: The raw interrupt status of  H264_REC_READY_INT. Triggered when
+ *  H264 encoding enough reconstruct pixel.
+ */
+#define H264_REC_READY_INT_RAW    (BIT(1))
+#define H264_REC_READY_INT_RAW_M  (H264_REC_READY_INT_RAW_V << H264_REC_READY_INT_RAW_S)
+#define H264_REC_READY_INT_RAW_V  0x00000001U
+#define H264_REC_READY_INT_RAW_S  1
+/** H264_FRAME_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Raw status bit: The raw interrupt status of  H264_FRAME_DONE_INT. Triggered when
+ *  H264 encoding one frame done.
+ */
+#define H264_FRAME_DONE_INT_RAW    (BIT(2))
+#define H264_FRAME_DONE_INT_RAW_M  (H264_FRAME_DONE_INT_RAW_V << H264_FRAME_DONE_INT_RAW_S)
+#define H264_FRAME_DONE_INT_RAW_V  0x00000001U
+#define H264_FRAME_DONE_INT_RAW_S  2
+/** H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT.
+ *  Triggered when H264 move two MB lines of reference frame from external mem to
+ *  internal mem done.
+ */
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW    (BIT(3))
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_M  (H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_V << H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_S)
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_V  0x00000001U
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_RAW_S  3
+/** H264_BS_BUFFER_OVERFLOW_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Raw status bit: The raw interrupt status of H264_BS_BUFFER_OVERFLOW_INT. Triggered
+ *  when H264 bit stream buffer overflow.
+ */
+#define H264_BS_BUFFER_OVERFLOW_INT_RAW    (BIT(4))
+#define H264_BS_BUFFER_OVERFLOW_INT_RAW_M  (H264_BS_BUFFER_OVERFLOW_INT_RAW_V << H264_BS_BUFFER_OVERFLOW_INT_RAW_S)
+#define H264_BS_BUFFER_OVERFLOW_INT_RAW_V  0x00000001U
+#define H264_BS_BUFFER_OVERFLOW_INT_RAW_S  4
+
+/** H264_INT_ST_REG register
+ *  Interrupt masked status register
+ */
+#define H264_INT_ST_REG (DR_REG_H264_BASE + 0xc4)
+/** H264_DB_TMP_READY_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_DB_TMP_READY_INT. Valid only
+ *  when the H264_DB_TMP_READY_INT_ENA is set to 1.
+ */
+#define H264_DB_TMP_READY_INT_ST    (BIT(0))
+#define H264_DB_TMP_READY_INT_ST_M  (H264_DB_TMP_READY_INT_ST_V << H264_DB_TMP_READY_INT_ST_S)
+#define H264_DB_TMP_READY_INT_ST_V  0x00000001U
+#define H264_DB_TMP_READY_INT_ST_S  0
+/** H264_REC_READY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_REC_READY_INT. Valid only
+ *  when the H264_REC_READY_INT_ENA is set to 1.
+ */
+#define H264_REC_READY_INT_ST    (BIT(1))
+#define H264_REC_READY_INT_ST_M  (H264_REC_READY_INT_ST_V << H264_REC_READY_INT_ST_S)
+#define H264_REC_READY_INT_ST_V  0x00000001U
+#define H264_REC_READY_INT_ST_S  1
+/** H264_FRAME_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_FRAME_DONE_INT. Valid only
+ *  when the H264_FRAME_DONE_INT_ENA is set to 1.
+ */
+#define H264_FRAME_DONE_INT_ST    (BIT(2))
+#define H264_FRAME_DONE_INT_ST_M  (H264_FRAME_DONE_INT_ST_V << H264_FRAME_DONE_INT_ST_S)
+#define H264_FRAME_DONE_INT_ST_V  0x00000001U
+#define H264_FRAME_DONE_INT_ST_S  2
+/** H264_DMA_MOVE_2MB_LINE_DONE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT.
+ *  Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1.
+ */
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ST    (BIT(3))
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_M  (H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_V << H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_S)
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_V  0x00000001U
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ST_S  3
+/** H264_BS_BUFFER_OVERFLOW_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Masked status bit: The masked interrupt status of H264_BS_BUFFER_OVERFLOW_INT.
+ *  Valid only when the H264_BS_BUFFER_OVERFLOW_INT_ENA is set to 1.
+ */
+#define H264_BS_BUFFER_OVERFLOW_INT_ST    (BIT(4))
+#define H264_BS_BUFFER_OVERFLOW_INT_ST_M  (H264_BS_BUFFER_OVERFLOW_INT_ST_V << H264_BS_BUFFER_OVERFLOW_INT_ST_S)
+#define H264_BS_BUFFER_OVERFLOW_INT_ST_V  0x00000001U
+#define H264_BS_BUFFER_OVERFLOW_INT_ST_S  4
+
+/** H264_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define H264_INT_ENA_REG (DR_REG_H264_BASE + 0xc8)
+/** H264_DB_TMP_READY_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable bit: Write 1 to enable H264_DB_TMP_READY_INT.
+ */
+#define H264_DB_TMP_READY_INT_ENA    (BIT(0))
+#define H264_DB_TMP_READY_INT_ENA_M  (H264_DB_TMP_READY_INT_ENA_V << H264_DB_TMP_READY_INT_ENA_S)
+#define H264_DB_TMP_READY_INT_ENA_V  0x00000001U
+#define H264_DB_TMP_READY_INT_ENA_S  0
+/** H264_REC_READY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Enable bit: Write 1 to enable H264_REC_READY_INT.
+ */
+#define H264_REC_READY_INT_ENA    (BIT(1))
+#define H264_REC_READY_INT_ENA_M  (H264_REC_READY_INT_ENA_V << H264_REC_READY_INT_ENA_S)
+#define H264_REC_READY_INT_ENA_V  0x00000001U
+#define H264_REC_READY_INT_ENA_S  1
+/** H264_FRAME_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Enable bit: Write 1 to enable H264_FRAME_DONE_INT.
+ */
+#define H264_FRAME_DONE_INT_ENA    (BIT(2))
+#define H264_FRAME_DONE_INT_ENA_M  (H264_FRAME_DONE_INT_ENA_V << H264_FRAME_DONE_INT_ENA_S)
+#define H264_FRAME_DONE_INT_ENA_V  0x00000001U
+#define H264_FRAME_DONE_INT_ENA_S  2
+/** H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT.
+ */
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA    (BIT(3))
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_M  (H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_V << H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_S)
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_V  0x00000001U
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA_S  3
+/** H264_BS_BUFFER_OVERFLOW_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Enable bit: Write 1 to enable H264_BS_BUFFER_OVERFLOW_INT.
+ */
+#define H264_BS_BUFFER_OVERFLOW_INT_ENA    (BIT(4))
+#define H264_BS_BUFFER_OVERFLOW_INT_ENA_M  (H264_BS_BUFFER_OVERFLOW_INT_ENA_V << H264_BS_BUFFER_OVERFLOW_INT_ENA_S)
+#define H264_BS_BUFFER_OVERFLOW_INT_ENA_V  0x00000001U
+#define H264_BS_BUFFER_OVERFLOW_INT_ENA_S  4
+
+/** H264_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define H264_INT_CLR_REG (DR_REG_H264_BASE + 0xcc)
+/** H264_DB_TMP_READY_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear bit: Write 1 to clear H264_DB_TMP_READY_INT.
+ */
+#define H264_DB_TMP_READY_INT_CLR    (BIT(0))
+#define H264_DB_TMP_READY_INT_CLR_M  (H264_DB_TMP_READY_INT_CLR_V << H264_DB_TMP_READY_INT_CLR_S)
+#define H264_DB_TMP_READY_INT_CLR_V  0x00000001U
+#define H264_DB_TMP_READY_INT_CLR_S  0
+/** H264_REC_READY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Clear bit: Write 1 to clear H264_REC_READY_INT.
+ */
+#define H264_REC_READY_INT_CLR    (BIT(1))
+#define H264_REC_READY_INT_CLR_M  (H264_REC_READY_INT_CLR_V << H264_REC_READY_INT_CLR_S)
+#define H264_REC_READY_INT_CLR_V  0x00000001U
+#define H264_REC_READY_INT_CLR_S  1
+/** H264_FRAME_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Clear bit: Write 1 to clear H264_FRAME_DONE_INT.
+ */
+#define H264_FRAME_DONE_INT_CLR    (BIT(2))
+#define H264_FRAME_DONE_INT_CLR_M  (H264_FRAME_DONE_INT_CLR_V << H264_FRAME_DONE_INT_CLR_S)
+#define H264_FRAME_DONE_INT_CLR_V  0x00000001U
+#define H264_FRAME_DONE_INT_CLR_S  2
+/** H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT.
+ */
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR    (BIT(3))
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_M  (H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_V << H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_S)
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_V  0x00000001U
+#define H264_DMA_MOVE_2MB_LINE_DONE_INT_CLR_S  3
+/** H264_BS_BUFFER_OVERFLOW_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Clear bit: Write 1 to clear H264_BS_BUFFER_OVERFLOW_INT.
+ */
+#define H264_BS_BUFFER_OVERFLOW_INT_CLR    (BIT(4))
+#define H264_BS_BUFFER_OVERFLOW_INT_CLR_M  (H264_BS_BUFFER_OVERFLOW_INT_CLR_V << H264_BS_BUFFER_OVERFLOW_INT_CLR_S)
+#define H264_BS_BUFFER_OVERFLOW_INT_CLR_V  0x00000001U
+#define H264_BS_BUFFER_OVERFLOW_INT_CLR_S  4
+
+/** H264_CONF_REG register
+ *  General configuration register.
+ */
+#define H264_CONF_REG (DR_REG_H264_BASE + 0xd0)
+/** H264_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to open register clock gate.
+ *  0: Open the clock gate only when application writes registers
+ *  1: Force open the clock gate for register
+ */
+#define H264_CLK_EN    (BIT(0))
+#define H264_CLK_EN_M  (H264_CLK_EN_V << H264_CLK_EN_S)
+#define H264_CLK_EN_V  0x00000001U
+#define H264_CLK_EN_S  0
+/** H264_REC_RAM_CLK_EN2 : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to open the clock gate for rec ram2.
+ *  0: Open the clock gate only when application writes or reads rec ram2
+ *  1: Force open the clock gate for rec ram2
+ */
+#define H264_REC_RAM_CLK_EN2    (BIT(1))
+#define H264_REC_RAM_CLK_EN2_M  (H264_REC_RAM_CLK_EN2_V << H264_REC_RAM_CLK_EN2_S)
+#define H264_REC_RAM_CLK_EN2_V  0x00000001U
+#define H264_REC_RAM_CLK_EN2_S  1
+/** H264_REC_RAM_CLK_EN1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to open the clock gate for rec ram1.
+ *  0: Open the clock gate only when application writes or reads rec ram1
+ *  1: Force open the clock gate for rec ram1
+ */
+#define H264_REC_RAM_CLK_EN1    (BIT(2))
+#define H264_REC_RAM_CLK_EN1_M  (H264_REC_RAM_CLK_EN1_V << H264_REC_RAM_CLK_EN1_S)
+#define H264_REC_RAM_CLK_EN1_V  0x00000001U
+#define H264_REC_RAM_CLK_EN1_S  2
+/** H264_QUANT_RAM_CLK_EN2 : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to open the clock gate for quant ram2.
+ *  0: Open the clock gate only when application writes or reads quant ram2
+ *  1: Force open the clock gate for quant ram2
+ */
+#define H264_QUANT_RAM_CLK_EN2    (BIT(3))
+#define H264_QUANT_RAM_CLK_EN2_M  (H264_QUANT_RAM_CLK_EN2_V << H264_QUANT_RAM_CLK_EN2_S)
+#define H264_QUANT_RAM_CLK_EN2_V  0x00000001U
+#define H264_QUANT_RAM_CLK_EN2_S  3
+/** H264_QUANT_RAM_CLK_EN1 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to open the clock gate for quant ram1.
+ *  0: Open the clock gate only when application writes or reads quant ram1
+ *  1: Force open the clock gate for quant ram1
+ */
+#define H264_QUANT_RAM_CLK_EN1    (BIT(4))
+#define H264_QUANT_RAM_CLK_EN1_M  (H264_QUANT_RAM_CLK_EN1_V << H264_QUANT_RAM_CLK_EN1_S)
+#define H264_QUANT_RAM_CLK_EN1_V  0x00000001U
+#define H264_QUANT_RAM_CLK_EN1_S  4
+/** H264_PRE_RAM_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to open the clock gate for pre ram.
+ *  0: Open the clock gate only when application writes or reads pre ram
+ *  1: Force open the clock gate for pre ram
+ */
+#define H264_PRE_RAM_CLK_EN    (BIT(5))
+#define H264_PRE_RAM_CLK_EN_M  (H264_PRE_RAM_CLK_EN_V << H264_PRE_RAM_CLK_EN_S)
+#define H264_PRE_RAM_CLK_EN_V  0x00000001U
+#define H264_PRE_RAM_CLK_EN_S  5
+/** H264_MVD_RAM_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to open the clock gate for mvd ram.
+ *  0: Open the clock gate only when application writes or reads mvd ram
+ *  1: Force open the clock gate for mvd ram
+ */
+#define H264_MVD_RAM_CLK_EN    (BIT(6))
+#define H264_MVD_RAM_CLK_EN_M  (H264_MVD_RAM_CLK_EN_V << H264_MVD_RAM_CLK_EN_S)
+#define H264_MVD_RAM_CLK_EN_V  0x00000001U
+#define H264_MVD_RAM_CLK_EN_S  6
+/** H264_MC_RAM_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to open the clock gate for mc ram.
+ *  0: Open the clock gate only when application writes or reads mc ram
+ *  1: Force open the clock gate for mc ram
+ */
+#define H264_MC_RAM_CLK_EN    (BIT(7))
+#define H264_MC_RAM_CLK_EN_M  (H264_MC_RAM_CLK_EN_V << H264_MC_RAM_CLK_EN_S)
+#define H264_MC_RAM_CLK_EN_V  0x00000001U
+#define H264_MC_RAM_CLK_EN_S  7
+/** H264_REF_RAM_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to open the clock gate for ref ram.
+ *  0: Open the clock gate only when application writes or reads ref ram
+ *  1: Force open the clock gate for ref ram
+ */
+#define H264_REF_RAM_CLK_EN    (BIT(8))
+#define H264_REF_RAM_CLK_EN_M  (H264_REF_RAM_CLK_EN_V << H264_REF_RAM_CLK_EN_S)
+#define H264_REF_RAM_CLK_EN_V  0x00000001U
+#define H264_REF_RAM_CLK_EN_S  8
+/** H264_I4X4_REF_RAM_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to open the clock gate for i4x4_mode ram.
+ *  0: Open the clock gate only when application writes or reads i4x4_mode ram
+ *  1: Force open the clock gate for i4x4_mode ram
+ */
+#define H264_I4X4_REF_RAM_CLK_EN    (BIT(9))
+#define H264_I4X4_REF_RAM_CLK_EN_M  (H264_I4X4_REF_RAM_CLK_EN_V << H264_I4X4_REF_RAM_CLK_EN_S)
+#define H264_I4X4_REF_RAM_CLK_EN_V  0x00000001U
+#define H264_I4X4_REF_RAM_CLK_EN_S  9
+/** H264_IME_RAM_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to open the clock gate for ime ram.
+ *  0: Open the clock gate only when application writes or reads ime ram
+ *  1: Force open the clock gate for ime ram
+ */
+#define H264_IME_RAM_CLK_EN    (BIT(10))
+#define H264_IME_RAM_CLK_EN_M  (H264_IME_RAM_CLK_EN_V << H264_IME_RAM_CLK_EN_S)
+#define H264_IME_RAM_CLK_EN_V  0x00000001U
+#define H264_IME_RAM_CLK_EN_S  10
+/** H264_FME_RAM_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to open the clock gate for fme ram.
+ *  0: Open the clock gate only when application writes or readsfme ram
+ *  1: Force open the clock gate for fme ram
+ */
+#define H264_FME_RAM_CLK_EN    (BIT(11))
+#define H264_FME_RAM_CLK_EN_M  (H264_FME_RAM_CLK_EN_V << H264_FME_RAM_CLK_EN_S)
+#define H264_FME_RAM_CLK_EN_V  0x00000001U
+#define H264_FME_RAM_CLK_EN_S  11
+/** H264_FETCH_RAM_CLK_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to open the clock gate for fetch ram.
+ *  0: Open the clock gate only when application writes or reads fetch ram
+ *  1: Force open the clock gate for fetch ram
+ */
+#define H264_FETCH_RAM_CLK_EN    (BIT(12))
+#define H264_FETCH_RAM_CLK_EN_M  (H264_FETCH_RAM_CLK_EN_V << H264_FETCH_RAM_CLK_EN_S)
+#define H264_FETCH_RAM_CLK_EN_V  0x00000001U
+#define H264_FETCH_RAM_CLK_EN_S  12
+/** H264_DB_RAM_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to open the clock gate for db ram.
+ *  0: Open the clock gate only when application writes or reads db ram
+ *  1: Force open the clock gate for db ram
+ */
+#define H264_DB_RAM_CLK_EN    (BIT(13))
+#define H264_DB_RAM_CLK_EN_M  (H264_DB_RAM_CLK_EN_V << H264_DB_RAM_CLK_EN_S)
+#define H264_DB_RAM_CLK_EN_V  0x00000001U
+#define H264_DB_RAM_CLK_EN_S  13
+/** H264_CUR_MB_RAM_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to open the clock gate for cur_mb ram.
+ *  0: Open the clock gate only when application writes or reads cur_mb ram
+ *  1: Force open the clock gate for cur_mb ram
+ */
+#define H264_CUR_MB_RAM_CLK_EN    (BIT(14))
+#define H264_CUR_MB_RAM_CLK_EN_M  (H264_CUR_MB_RAM_CLK_EN_V << H264_CUR_MB_RAM_CLK_EN_S)
+#define H264_CUR_MB_RAM_CLK_EN_V  0x00000001U
+#define H264_CUR_MB_RAM_CLK_EN_S  14
+/** H264_CAVLC_RAM_CLK_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to open the clock gate for cavlc ram.
+ *  0: Open the clock gate only when application writes or reads cavlc ram
+ *  1: Force open the clock gate for cavlc ram
+ */
+#define H264_CAVLC_RAM_CLK_EN    (BIT(15))
+#define H264_CAVLC_RAM_CLK_EN_M  (H264_CAVLC_RAM_CLK_EN_V << H264_CAVLC_RAM_CLK_EN_S)
+#define H264_CAVLC_RAM_CLK_EN_V  0x00000001U
+#define H264_CAVLC_RAM_CLK_EN_S  15
+/** H264_IME_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to open the clock gate for ime.
+ *  0: Open the clock gate only when ime work
+ *  1: Force open the clock gate for ime
+ */
+#define H264_IME_CLK_EN    (BIT(16))
+#define H264_IME_CLK_EN_M  (H264_IME_CLK_EN_V << H264_IME_CLK_EN_S)
+#define H264_IME_CLK_EN_V  0x00000001U
+#define H264_IME_CLK_EN_S  16
+/** H264_FME_CLK_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to open the clock gate for fme.
+ *  0: Open the clock gate only when fme work
+ *  1: Force open the clock gate for fme
+ */
+#define H264_FME_CLK_EN    (BIT(17))
+#define H264_FME_CLK_EN_M  (H264_FME_CLK_EN_V << H264_FME_CLK_EN_S)
+#define H264_FME_CLK_EN_V  0x00000001U
+#define H264_FME_CLK_EN_S  17
+/** H264_MC_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to open the clock gate for mc.
+ *  0: Open the clock gate only when mc work
+ *  1: Force open the clock gate for mc
+ */
+#define H264_MC_CLK_EN    (BIT(18))
+#define H264_MC_CLK_EN_M  (H264_MC_CLK_EN_V << H264_MC_CLK_EN_S)
+#define H264_MC_CLK_EN_V  0x00000001U
+#define H264_MC_CLK_EN_S  18
+/** H264_INTERPOLATOR_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to open the clock gate for interpolator.
+ *  0: Open the clock gate only when interpolator work
+ *  1: Force open the clock gate for interpolator
+ */
+#define H264_INTERPOLATOR_CLK_EN    (BIT(19))
+#define H264_INTERPOLATOR_CLK_EN_M  (H264_INTERPOLATOR_CLK_EN_V << H264_INTERPOLATOR_CLK_EN_S)
+#define H264_INTERPOLATOR_CLK_EN_V  0x00000001U
+#define H264_INTERPOLATOR_CLK_EN_S  19
+/** H264_DB_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to open the clock gate for deblocking filter.
+ *  0: Open the clock gate only when deblocking filter work
+ *  1: Force open the clock gate for deblocking filter
+ */
+#define H264_DB_CLK_EN    (BIT(20))
+#define H264_DB_CLK_EN_M  (H264_DB_CLK_EN_V << H264_DB_CLK_EN_S)
+#define H264_DB_CLK_EN_V  0x00000001U
+#define H264_DB_CLK_EN_S  20
+/** H264_CLAVLC_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to open the clock gate for cavlc.
+ *  0: Open the clock gate only when cavlc work
+ *  1: Force open the clock gate for cavlc
+ */
+#define H264_CLAVLC_CLK_EN    (BIT(21))
+#define H264_CLAVLC_CLK_EN_M  (H264_CLAVLC_CLK_EN_V << H264_CLAVLC_CLK_EN_S)
+#define H264_CLAVLC_CLK_EN_V  0x00000001U
+#define H264_CLAVLC_CLK_EN_S  21
+/** H264_INTRA_CLK_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to open the clock gate for intra.
+ *  0: Open the clock gate only when intra work
+ *  1: Force open the clock gate for intra
+ */
+#define H264_INTRA_CLK_EN    (BIT(22))
+#define H264_INTRA_CLK_EN_M  (H264_INTRA_CLK_EN_V << H264_INTRA_CLK_EN_S)
+#define H264_INTRA_CLK_EN_V  0x00000001U
+#define H264_INTRA_CLK_EN_S  22
+/** H264_DECI_CLK_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to open the clock gate for decimate.
+ *  0: Open the clock gate only when decimate work
+ *  1: Force open the clock gate for decimate
+ */
+#define H264_DECI_CLK_EN    (BIT(23))
+#define H264_DECI_CLK_EN_M  (H264_DECI_CLK_EN_V << H264_DECI_CLK_EN_S)
+#define H264_DECI_CLK_EN_V  0x00000001U
+#define H264_DECI_CLK_EN_S  23
+/** H264_BS_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to open the clock gate for bs buffer.
+ *  0: Open the clock gate only when bs buffer work
+ *  1: Force open the clock gate for bs buffer
+ */
+#define H264_BS_CLK_EN    (BIT(24))
+#define H264_BS_CLK_EN_M  (H264_BS_CLK_EN_V << H264_BS_CLK_EN_S)
+#define H264_BS_CLK_EN_V  0x00000001U
+#define H264_BS_CLK_EN_S  24
+/** H264_MV_MERGE_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to open the clock gate for mv merge.
+ *  0: Open the clock gate only when mv merge work
+ *  1: Force open the clock gate for mv merge
+ */
+#define H264_MV_MERGE_CLK_EN    (BIT(25))
+#define H264_MV_MERGE_CLK_EN_M  (H264_MV_MERGE_CLK_EN_V << H264_MV_MERGE_CLK_EN_S)
+#define H264_MV_MERGE_CLK_EN_V  0x00000001U
+#define H264_MV_MERGE_CLK_EN_S  25
+/** H264_CUR_MB_RDCMB_CLK_EN : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to open the clock gate for cur_mb read macroblock.
+ *  0: Open the clock gate only when cur_mb read macroblock work
+ *  1: Force open the clock gate for  cur_mb read macroblock
+ */
+#define H264_CUR_MB_RDCMB_CLK_EN    (BIT(26))
+#define H264_CUR_MB_RDCMB_CLK_EN_M  (H264_CUR_MB_RDCMB_CLK_EN_V << H264_CUR_MB_RDCMB_CLK_EN_S)
+#define H264_CUR_MB_RDCMB_CLK_EN_V  0x00000001U
+#define H264_CUR_MB_RDCMB_CLK_EN_S  26
+/** H264_CUR_MB_REFRESH_REGGROUP_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to open the clock gate for cur_mb refresh register group.
+ *  0: Open the clock gate only when cur_mb refresh register group work
+ *  1: Force open the clock gate for  cur_mb  refresh register group
+ */
+#define H264_CUR_MB_REFRESH_REGGROUP_CLK_EN    (BIT(27))
+#define H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_M  (H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_V << H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_S)
+#define H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_V  0x00000001U
+#define H264_CUR_MB_REFRESH_REGGROUP_CLK_EN_S  27
+
+/** H264_MV_MERGE_CONFIG_REG register
+ *  Mv merge configuration register.
+ */
+#define H264_MV_MERGE_CONFIG_REG (DR_REG_H264_BASE + 0xd4)
+/** H264_MV_MERGE_TYPE : R/W; bitpos: [1:0]; default: 0;
+ *  Configure mv merge type.
+ *  0: merge p16x16 mv
+ *  1: merge min mv
+ *  2: merge max mv
+ *  3: not valid.
+ */
+#define H264_MV_MERGE_TYPE    0x00000003U
+#define H264_MV_MERGE_TYPE_M  (H264_MV_MERGE_TYPE_V << H264_MV_MERGE_TYPE_S)
+#define H264_MV_MERGE_TYPE_V  0x00000003U
+#define H264_MV_MERGE_TYPE_S  0
+/** H264_INT_MV_OUT_EN : R/W; bitpos: [2]; default: 0;
+ *  Configure mv merge output integer part not zero mv or all part not zero mv.
+ *  0: output all part not zero mv
+ *  1: output integer part not zero mv.
+ */
+#define H264_INT_MV_OUT_EN    (BIT(2))
+#define H264_INT_MV_OUT_EN_M  (H264_INT_MV_OUT_EN_V << H264_INT_MV_OUT_EN_S)
+#define H264_INT_MV_OUT_EN_V  0x00000001U
+#define H264_INT_MV_OUT_EN_S  2
+/** H264_A_MV_MERGE_EN : R/W; bitpos: [3]; default: 0;
+ *  Configure whether or not to enable video A mv merge.
+ *  0: disable
+ *  1: enable.
+ */
+#define H264_A_MV_MERGE_EN    (BIT(3))
+#define H264_A_MV_MERGE_EN_M  (H264_A_MV_MERGE_EN_V << H264_A_MV_MERGE_EN_S)
+#define H264_A_MV_MERGE_EN_V  0x00000001U
+#define H264_A_MV_MERGE_EN_S  3
+/** H264_B_MV_MERGE_EN : R/W; bitpos: [4]; default: 0;
+ *  Configure whether or not to enable video B mv merge.
+ *  0: disable
+ *  1: enable.
+ */
+#define H264_B_MV_MERGE_EN    (BIT(4))
+#define H264_B_MV_MERGE_EN_M  (H264_B_MV_MERGE_EN_V << H264_B_MV_MERGE_EN_S)
+#define H264_B_MV_MERGE_EN_V  0x00000001U
+#define H264_B_MV_MERGE_EN_S  4
+/** H264_MB_VALID_NUM : RO; bitpos: [17:5]; default: 0;
+ *  Represents the valid mb number of mv merge output.
+ */
+#define H264_MB_VALID_NUM    0x00001FFFU
+#define H264_MB_VALID_NUM_M  (H264_MB_VALID_NUM_V << H264_MB_VALID_NUM_S)
+#define H264_MB_VALID_NUM_V  0x00001FFFU
+#define H264_MB_VALID_NUM_S  5
+
+/** H264_DEBUG_DMA_SEL_REG register
+ *  Debug H264 DMA select register
+ */
+#define H264_DEBUG_DMA_SEL_REG (DR_REG_H264_BASE + 0xd8)
+/** H264_DBG_DMA_SEL : R/W; bitpos: [7:0]; default: 0;
+ *  Every bit represents a dma in h264
+ */
+#define H264_DBG_DMA_SEL    0x000000FFU
+#define H264_DBG_DMA_SEL_M  (H264_DBG_DMA_SEL_V << H264_DBG_DMA_SEL_S)
+#define H264_DBG_DMA_SEL_V  0x000000FFU
+#define H264_DBG_DMA_SEL_S  0
+
+/** H264_SYS_STATUS_REG register
+ *  System status register.
+ */
+#define H264_SYS_STATUS_REG (DR_REG_H264_BASE + 0xdc)
+/** H264_FRAME_NUM : RO; bitpos: [8:0]; default: 0;
+ *  Represents current frame number.
+ */
+#define H264_FRAME_NUM    0x000001FFU
+#define H264_FRAME_NUM_M  (H264_FRAME_NUM_V << H264_FRAME_NUM_S)
+#define H264_FRAME_NUM_V  0x000001FFU
+#define H264_FRAME_NUM_S  0
+/** H264_DUAL_STREAM_SEL : RO; bitpos: [9]; default: 0;
+ *  Represents which register group is used for cur frame.
+ *  0: Register group A is used
+ *  1: Register group B is used.
+ */
+#define H264_DUAL_STREAM_SEL    (BIT(9))
+#define H264_DUAL_STREAM_SEL_M  (H264_DUAL_STREAM_SEL_V << H264_DUAL_STREAM_SEL_S)
+#define H264_DUAL_STREAM_SEL_V  0x00000001U
+#define H264_DUAL_STREAM_SEL_S  9
+/** H264_INTRA_FLAG : RO; bitpos: [10]; default: 0;
+ *  Represents the type of current encoding frame.
+ *  0: P frame
+ *  1: I frame.
+ */
+#define H264_INTRA_FLAG    (BIT(10))
+#define H264_INTRA_FLAG_M  (H264_INTRA_FLAG_V << H264_INTRA_FLAG_S)
+#define H264_INTRA_FLAG_V  0x00000001U
+#define H264_INTRA_FLAG_S  10
+
+/** H264_FRAME_CODE_LENGTH_REG register
+ *  Frame code byte length register.
+ */
+#define H264_FRAME_CODE_LENGTH_REG (DR_REG_H264_BASE + 0xe0)
+/** H264_FRAME_CODE_LENGTH : RO; bitpos: [23:0]; default: 0;
+ *  Represents current frame code byte length.
+ */
+#define H264_FRAME_CODE_LENGTH    0x00FFFFFFU
+#define H264_FRAME_CODE_LENGTH_M  (H264_FRAME_CODE_LENGTH_V << H264_FRAME_CODE_LENGTH_S)
+#define H264_FRAME_CODE_LENGTH_V  0x00FFFFFFU
+#define H264_FRAME_CODE_LENGTH_S  0
+
+/** H264_DEBUG_INFO0_REG register
+ *  Debug information register0.
+ */
+#define H264_DEBUG_INFO0_REG (DR_REG_H264_BASE + 0xe4)
+/** H264_TOP_CTRL_INTER_DEBUG_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Represents top_ctrl_inter module FSM info.
+ */
+#define H264_TOP_CTRL_INTER_DEBUG_STATE    0x0000000FU
+#define H264_TOP_CTRL_INTER_DEBUG_STATE_M  (H264_TOP_CTRL_INTER_DEBUG_STATE_V << H264_TOP_CTRL_INTER_DEBUG_STATE_S)
+#define H264_TOP_CTRL_INTER_DEBUG_STATE_V  0x0000000FU
+#define H264_TOP_CTRL_INTER_DEBUG_STATE_S  0
+/** H264_TOP_CTRL_INTRA_DEBUG_STATE : RO; bitpos: [6:4]; default: 0;
+ *  Represents top_ctrl_intra module FSM info.
+ */
+#define H264_TOP_CTRL_INTRA_DEBUG_STATE    0x00000007U
+#define H264_TOP_CTRL_INTRA_DEBUG_STATE_M  (H264_TOP_CTRL_INTRA_DEBUG_STATE_V << H264_TOP_CTRL_INTRA_DEBUG_STATE_S)
+#define H264_TOP_CTRL_INTRA_DEBUG_STATE_V  0x00000007U
+#define H264_TOP_CTRL_INTRA_DEBUG_STATE_S  4
+/** H264_P_I_CMP_DEBUG_STATE : RO; bitpos: [9:7]; default: 0;
+ *  Represents p_i_cmp module FSM info.
+ */
+#define H264_P_I_CMP_DEBUG_STATE    0x00000007U
+#define H264_P_I_CMP_DEBUG_STATE_M  (H264_P_I_CMP_DEBUG_STATE_V << H264_P_I_CMP_DEBUG_STATE_S)
+#define H264_P_I_CMP_DEBUG_STATE_V  0x00000007U
+#define H264_P_I_CMP_DEBUG_STATE_S  7
+/** H264_MVD_DEBUG_STATE : RO; bitpos: [12:10]; default: 0;
+ *  Represents mvd module FSM info.
+ */
+#define H264_MVD_DEBUG_STATE    0x00000007U
+#define H264_MVD_DEBUG_STATE_M  (H264_MVD_DEBUG_STATE_V << H264_MVD_DEBUG_STATE_S)
+#define H264_MVD_DEBUG_STATE_V  0x00000007U
+#define H264_MVD_DEBUG_STATE_S  10
+/** H264_MC_CHROMA_IP_DEBUG_STATE : RO; bitpos: [13]; default: 0;
+ *  Represents mc_chroma_ip module FSM info.
+ */
+#define H264_MC_CHROMA_IP_DEBUG_STATE    (BIT(13))
+#define H264_MC_CHROMA_IP_DEBUG_STATE_M  (H264_MC_CHROMA_IP_DEBUG_STATE_V << H264_MC_CHROMA_IP_DEBUG_STATE_S)
+#define H264_MC_CHROMA_IP_DEBUG_STATE_V  0x00000001U
+#define H264_MC_CHROMA_IP_DEBUG_STATE_S  13
+/** H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE : RO; bitpos: [17:14]; default: 0;
+ *  Represents intra_16x16_chroma_ctrl module FSM info.
+ */
+#define H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE    0x0000000FU
+#define H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_M  (H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_V << H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_S)
+#define H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_V  0x0000000FU
+#define H264_INTRA_16X16_CHROMA_CTRL_DEBUG_STATE_S  14
+/** H264_INTRA_4X4_CTRL_DEBUG_STATE : RO; bitpos: [21:18]; default: 0;
+ *  Represents intra_4x4_ctrl module FSM info.
+ */
+#define H264_INTRA_4X4_CTRL_DEBUG_STATE    0x0000000FU
+#define H264_INTRA_4X4_CTRL_DEBUG_STATE_M  (H264_INTRA_4X4_CTRL_DEBUG_STATE_V << H264_INTRA_4X4_CTRL_DEBUG_STATE_S)
+#define H264_INTRA_4X4_CTRL_DEBUG_STATE_V  0x0000000FU
+#define H264_INTRA_4X4_CTRL_DEBUG_STATE_S  18
+/** H264_INTRA_TOP_CTRL_DEBUG_STATE : RO; bitpos: [24:22]; default: 0;
+ *  Represents intra_top_ctrl module FSM info.
+ */
+#define H264_INTRA_TOP_CTRL_DEBUG_STATE    0x00000007U
+#define H264_INTRA_TOP_CTRL_DEBUG_STATE_M  (H264_INTRA_TOP_CTRL_DEBUG_STATE_V << H264_INTRA_TOP_CTRL_DEBUG_STATE_S)
+#define H264_INTRA_TOP_CTRL_DEBUG_STATE_V  0x00000007U
+#define H264_INTRA_TOP_CTRL_DEBUG_STATE_S  22
+/** H264_IME_CTRL_DEBUG_STATE : RO; bitpos: [27:25]; default: 0;
+ *  Represents ime_ctrl module FSM info.
+ */
+#define H264_IME_CTRL_DEBUG_STATE    0x00000007U
+#define H264_IME_CTRL_DEBUG_STATE_M  (H264_IME_CTRL_DEBUG_STATE_V << H264_IME_CTRL_DEBUG_STATE_S)
+#define H264_IME_CTRL_DEBUG_STATE_V  0x00000007U
+#define H264_IME_CTRL_DEBUG_STATE_S  25
+
+/** H264_DEBUG_INFO1_REG register
+ *  Debug information register1.
+ */
+#define H264_DEBUG_INFO1_REG (DR_REG_H264_BASE + 0xe8)
+/** H264_FME_CTRL_DEBUG_STATE : RO; bitpos: [2:0]; default: 0;
+ *  Represents fme_ctrl module FSM info.
+ */
+#define H264_FME_CTRL_DEBUG_STATE    0x00000007U
+#define H264_FME_CTRL_DEBUG_STATE_M  (H264_FME_CTRL_DEBUG_STATE_V << H264_FME_CTRL_DEBUG_STATE_S)
+#define H264_FME_CTRL_DEBUG_STATE_V  0x00000007U
+#define H264_FME_CTRL_DEBUG_STATE_S  0
+/** H264_DECI_CALC_DEBUG_STATE : RO; bitpos: [4:3]; default: 0;
+ *  Represents deci_calc module's FSM info. DEV use only.
+ */
+#define H264_DECI_CALC_DEBUG_STATE    0x00000003U
+#define H264_DECI_CALC_DEBUG_STATE_M  (H264_DECI_CALC_DEBUG_STATE_V << H264_DECI_CALC_DEBUG_STATE_S)
+#define H264_DECI_CALC_DEBUG_STATE_V  0x00000003U
+#define H264_DECI_CALC_DEBUG_STATE_S  3
+/** H264_DB_DEBUG_STATE : RO; bitpos: [7:5]; default: 0;
+ *  Represents db module FSM info.
+ */
+#define H264_DB_DEBUG_STATE    0x00000007U
+#define H264_DB_DEBUG_STATE_M  (H264_DB_DEBUG_STATE_V << H264_DB_DEBUG_STATE_S)
+#define H264_DB_DEBUG_STATE_V  0x00000007U
+#define H264_DB_DEBUG_STATE_S  5
+/** H264_CAVLC_ENC_DEBUG_STATE : RO; bitpos: [11:8]; default: 0;
+ *  Represents cavlc module enc FSM info.
+ */
+#define H264_CAVLC_ENC_DEBUG_STATE    0x0000000FU
+#define H264_CAVLC_ENC_DEBUG_STATE_M  (H264_CAVLC_ENC_DEBUG_STATE_V << H264_CAVLC_ENC_DEBUG_STATE_S)
+#define H264_CAVLC_ENC_DEBUG_STATE_V  0x0000000FU
+#define H264_CAVLC_ENC_DEBUG_STATE_S  8
+/** H264_CAVLC_SCAN_DEBUG_STATE : RO; bitpos: [15:12]; default: 0;
+ *  Represents cavlc module scan FSM info.
+ */
+#define H264_CAVLC_SCAN_DEBUG_STATE    0x0000000FU
+#define H264_CAVLC_SCAN_DEBUG_STATE_M  (H264_CAVLC_SCAN_DEBUG_STATE_V << H264_CAVLC_SCAN_DEBUG_STATE_S)
+#define H264_CAVLC_SCAN_DEBUG_STATE_V  0x0000000FU
+#define H264_CAVLC_SCAN_DEBUG_STATE_S  12
+/** H264_CAVLC_CTRL_DEBUG_STATE : RO; bitpos: [17:16]; default: 0;
+ *  Represents cavlc module ctrl FSM info.
+ */
+#define H264_CAVLC_CTRL_DEBUG_STATE    0x00000003U
+#define H264_CAVLC_CTRL_DEBUG_STATE_M  (H264_CAVLC_CTRL_DEBUG_STATE_V << H264_CAVLC_CTRL_DEBUG_STATE_S)
+#define H264_CAVLC_CTRL_DEBUG_STATE_V  0x00000003U
+#define H264_CAVLC_CTRL_DEBUG_STATE_S  16
+
+/** H264_DEBUG_INFO2_REG register
+ *  Debug information register2.
+ */
+#define H264_DEBUG_INFO2_REG (DR_REG_H264_BASE + 0xec)
+/** H264_P_RC_DONE_DEBUG_FLAG : RO; bitpos: [0]; default: 0;
+ *  Represents p rate ctrl done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_RC_DONE_DEBUG_FLAG    (BIT(0))
+#define H264_P_RC_DONE_DEBUG_FLAG_M  (H264_P_RC_DONE_DEBUG_FLAG_V << H264_P_RC_DONE_DEBUG_FLAG_S)
+#define H264_P_RC_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_RC_DONE_DEBUG_FLAG_S  0
+/** H264_P_P_I_CMP_DONE_DEBUG_FLAG : RO; bitpos: [1]; default: 0;
+ *  Represents p p_i_cmp done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_P_I_CMP_DONE_DEBUG_FLAG    (BIT(1))
+#define H264_P_P_I_CMP_DONE_DEBUG_FLAG_M  (H264_P_P_I_CMP_DONE_DEBUG_FLAG_V << H264_P_P_I_CMP_DONE_DEBUG_FLAG_S)
+#define H264_P_P_I_CMP_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_P_I_CMP_DONE_DEBUG_FLAG_S  1
+/** H264_P_MV_MERGE_DONE_DEBUG_FLAG : RO; bitpos: [2]; default: 0;
+ *  Represents p mv merge done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_MV_MERGE_DONE_DEBUG_FLAG    (BIT(2))
+#define H264_P_MV_MERGE_DONE_DEBUG_FLAG_M  (H264_P_MV_MERGE_DONE_DEBUG_FLAG_V << H264_P_MV_MERGE_DONE_DEBUG_FLAG_S)
+#define H264_P_MV_MERGE_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_MV_MERGE_DONE_DEBUG_FLAG_S  2
+/** H264_P_MOVE_ORI_DONE_DEBUG_FLAG : RO; bitpos: [3]; default: 0;
+ *  Represents p move origin done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_MOVE_ORI_DONE_DEBUG_FLAG    (BIT(3))
+#define H264_P_MOVE_ORI_DONE_DEBUG_FLAG_M  (H264_P_MOVE_ORI_DONE_DEBUG_FLAG_V << H264_P_MOVE_ORI_DONE_DEBUG_FLAG_S)
+#define H264_P_MOVE_ORI_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_MOVE_ORI_DONE_DEBUG_FLAG_S  3
+/** H264_P_MC_DONE_DEBUG_FLAG : RO; bitpos: [4]; default: 0;
+ *  Represents p mc done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_MC_DONE_DEBUG_FLAG    (BIT(4))
+#define H264_P_MC_DONE_DEBUG_FLAG_M  (H264_P_MC_DONE_DEBUG_FLAG_V << H264_P_MC_DONE_DEBUG_FLAG_S)
+#define H264_P_MC_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_MC_DONE_DEBUG_FLAG_S  4
+/** H264_P_IME_DONE_DEBUG_FLAG : RO; bitpos: [5]; default: 0;
+ *  Represents p ime done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_IME_DONE_DEBUG_FLAG    (BIT(5))
+#define H264_P_IME_DONE_DEBUG_FLAG_M  (H264_P_IME_DONE_DEBUG_FLAG_V << H264_P_IME_DONE_DEBUG_FLAG_S)
+#define H264_P_IME_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_IME_DONE_DEBUG_FLAG_S  5
+/** H264_P_GET_ORI_DONE_DEBUG_FLAG : RO; bitpos: [6]; default: 0;
+ *  Represents p get origin done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_GET_ORI_DONE_DEBUG_FLAG    (BIT(6))
+#define H264_P_GET_ORI_DONE_DEBUG_FLAG_M  (H264_P_GET_ORI_DONE_DEBUG_FLAG_V << H264_P_GET_ORI_DONE_DEBUG_FLAG_S)
+#define H264_P_GET_ORI_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_GET_ORI_DONE_DEBUG_FLAG_S  6
+/** H264_P_FME_DONE_DEBUG_FLAG : RO; bitpos: [7]; default: 0;
+ *  Represents p fme done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_FME_DONE_DEBUG_FLAG    (BIT(7))
+#define H264_P_FME_DONE_DEBUG_FLAG_M  (H264_P_FME_DONE_DEBUG_FLAG_V << H264_P_FME_DONE_DEBUG_FLAG_S)
+#define H264_P_FME_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_FME_DONE_DEBUG_FLAG_S  7
+/** H264_P_FETCH_DONE_DEBUG_FLAG : RO; bitpos: [8]; default: 0;
+ *  Represents p fetch done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_FETCH_DONE_DEBUG_FLAG    (BIT(8))
+#define H264_P_FETCH_DONE_DEBUG_FLAG_M  (H264_P_FETCH_DONE_DEBUG_FLAG_V << H264_P_FETCH_DONE_DEBUG_FLAG_S)
+#define H264_P_FETCH_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_FETCH_DONE_DEBUG_FLAG_S  8
+/** H264_P_DB_DONE_DEBUG_FLAG : RO; bitpos: [9]; default: 0;
+ *  Represents p deblocking done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_DB_DONE_DEBUG_FLAG    (BIT(9))
+#define H264_P_DB_DONE_DEBUG_FLAG_M  (H264_P_DB_DONE_DEBUG_FLAG_V << H264_P_DB_DONE_DEBUG_FLAG_S)
+#define H264_P_DB_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_DB_DONE_DEBUG_FLAG_S  9
+/** H264_P_BS_BUF_DONE_DEBUG_FLAG : RO; bitpos: [10]; default: 0;
+ *  Represents p bitstream buffer done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_P_BS_BUF_DONE_DEBUG_FLAG    (BIT(10))
+#define H264_P_BS_BUF_DONE_DEBUG_FLAG_M  (H264_P_BS_BUF_DONE_DEBUG_FLAG_V << H264_P_BS_BUF_DONE_DEBUG_FLAG_S)
+#define H264_P_BS_BUF_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_P_BS_BUF_DONE_DEBUG_FLAG_S  10
+/** H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG : RO; bitpos: [11]; default: 0;
+ *  Represents dma move 2 ref mb line done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG    (BIT(11))
+#define H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_M  (H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_V << H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_S)
+#define H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG_S  11
+/** H264_I_P_I_CMP_DONE_DEBUG_FLAG : RO; bitpos: [12]; default: 0;
+ *  Represents I p_i_cmp done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_P_I_CMP_DONE_DEBUG_FLAG    (BIT(12))
+#define H264_I_P_I_CMP_DONE_DEBUG_FLAG_M  (H264_I_P_I_CMP_DONE_DEBUG_FLAG_V << H264_I_P_I_CMP_DONE_DEBUG_FLAG_S)
+#define H264_I_P_I_CMP_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_P_I_CMP_DONE_DEBUG_FLAG_S  12
+/** H264_I_MOVE_ORI_DONE_DEBUG_FLAG : RO; bitpos: [13]; default: 0;
+ *  Represents I move origin done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_MOVE_ORI_DONE_DEBUG_FLAG    (BIT(13))
+#define H264_I_MOVE_ORI_DONE_DEBUG_FLAG_M  (H264_I_MOVE_ORI_DONE_DEBUG_FLAG_V << H264_I_MOVE_ORI_DONE_DEBUG_FLAG_S)
+#define H264_I_MOVE_ORI_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_MOVE_ORI_DONE_DEBUG_FLAG_S  13
+/** H264_I_GET_ORI_DONE_DEBUG_FLAG : RO; bitpos: [14]; default: 0;
+ *  Represents I get origin done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_GET_ORI_DONE_DEBUG_FLAG    (BIT(14))
+#define H264_I_GET_ORI_DONE_DEBUG_FLAG_M  (H264_I_GET_ORI_DONE_DEBUG_FLAG_V << H264_I_GET_ORI_DONE_DEBUG_FLAG_S)
+#define H264_I_GET_ORI_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_GET_ORI_DONE_DEBUG_FLAG_S  14
+/** H264_I_EC_DONE_DEBUG_FLAG : RO; bitpos: [15]; default: 0;
+ *  Represents I encoder done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_EC_DONE_DEBUG_FLAG    (BIT(15))
+#define H264_I_EC_DONE_DEBUG_FLAG_M  (H264_I_EC_DONE_DEBUG_FLAG_V << H264_I_EC_DONE_DEBUG_FLAG_S)
+#define H264_I_EC_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_EC_DONE_DEBUG_FLAG_S  15
+/** H264_I_DB_DONE_DEBUG_FLAG : RO; bitpos: [16]; default: 0;
+ *  Represents I deblocking done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_DB_DONE_DEBUG_FLAG    (BIT(16))
+#define H264_I_DB_DONE_DEBUG_FLAG_M  (H264_I_DB_DONE_DEBUG_FLAG_V << H264_I_DB_DONE_DEBUG_FLAG_S)
+#define H264_I_DB_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_DB_DONE_DEBUG_FLAG_S  16
+/** H264_I_BS_BUF_DONE_DEBUG_FLAG : RO; bitpos: [17]; default: 0;
+ *  Represents I bitstream buffer done status.
+ *  0: not done
+ *  1: done.
+ */
+#define H264_I_BS_BUF_DONE_DEBUG_FLAG    (BIT(17))
+#define H264_I_BS_BUF_DONE_DEBUG_FLAG_M  (H264_I_BS_BUF_DONE_DEBUG_FLAG_V << H264_I_BS_BUF_DONE_DEBUG_FLAG_S)
+#define H264_I_BS_BUF_DONE_DEBUG_FLAG_V  0x00000001U
+#define H264_I_BS_BUF_DONE_DEBUG_FLAG_S  17
+
+/** H264_DATE_REG register
+ *  Version control register
+ */
+#define H264_DATE_REG (DR_REG_H264_BASE + 0xf0)
+/** H264_DATE : R/W; bitpos: [27:0]; default: 37823232;
+ *  Configures the version.
+ */
+#define H264_DATE    0x0FFFFFFFU
+#define H264_DATE_M  (H264_DATE_V << H264_DATE_S)
+#define H264_DATE_V  0x0FFFFFFFU
+#define H264_DATE_S  0
+
+/** H264_A_ORI_CONF_REG register
+ *  Video A original picture configuration register.
+ */
+#define H264_A_ORI_CONF_REG (DR_REG_H264_BASE + 0xf4)
+/** H264_A_ORI_COLOR_SPACE : R/W; bitpos: [2:0]; default: 4;
+ *  Configures video A original picture color space.
+ *  0: RGB888
+ *  1: RGB565
+ *  2: YUV444
+ *  3: YUV422
+ *  4: YUV420
+ *  5: GRAY
+ *  Others: Invalid
+ */
+#define H264_A_ORI_COLOR_SPACE    0x00000007U
+#define H264_A_ORI_COLOR_SPACE_M  (H264_A_ORI_COLOR_SPACE_V << H264_A_ORI_COLOR_SPACE_S)
+#define H264_A_ORI_COLOR_SPACE_V  0x00000007U
+#define H264_A_ORI_COLOR_SPACE_S  0
+
+/** H264_B_ORI_CONF_REG register
+ *  Video B original picture configuration register.
+ */
+#define H264_B_ORI_CONF_REG (DR_REG_H264_BASE + 0xf8)
+/** H264_B_ORI_COLOR_SPACE : R/W; bitpos: [2:0]; default: 4;
+ *  Configures video B original picture color space.
+ *  0: RGB888
+ *  1: RGB565
+ *  2: YUV444
+ *  3: YUV422
+ *  4: YUV420
+ *  5: GRAY
+ *  Others: Invalid
+ */
+#define H264_B_ORI_COLOR_SPACE    0x00000007U
+#define H264_B_ORI_COLOR_SPACE_M  (H264_B_ORI_COLOR_SPACE_V << H264_B_ORI_COLOR_SPACE_S)
+#define H264_B_ORI_COLOR_SPACE_V  0x00000007U
+#define H264_B_ORI_COLOR_SPACE_S  0
+
+/** H264_ORI_DEBUG_CONF_REG register
+ *  Original picture debug configuration register.
+ */
+#define H264_ORI_DEBUG_CONF_REG (DR_REG_H264_BASE + 0xfc)
+/** H264_DBG_REPLACE_ORI_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to replace original picture pixels.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_ORI_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_ORI_DATA_EN_M  (H264_DBG_REPLACE_ORI_DATA_EN_V << H264_DBG_REPLACE_ORI_DATA_EN_S)
+#define H264_DBG_REPLACE_ORI_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_ORI_DATA_EN_S  0
+/** H264_DBG_REPLACE_ORI_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configures original picture pixels to be replaced. When the original picture color
+ *  space is RGB, byte0~2 is BGR. When the original picture color space is YUV, byte0~2
+ *  is VUY. When the original picture color space is GRAY, byte0 is GRAY.
+ */
+#define H264_DBG_REPLACE_ORI_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_ORI_DATA_M  (H264_DBG_REPLACE_ORI_DATA_V << H264_DBG_REPLACE_ORI_DATA_S)
+#define H264_DBG_REPLACE_ORI_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_ORI_DATA_S  1
+
+/** H264_MV_MERGE_DEBUG_CONF_REG register
+ *  Original picture debug configuration register.
+ */
+#define H264_MV_MERGE_DEBUG_CONF_REG (DR_REG_H264_BASE + 0x100)
+/** H264_DBG_REPLACE_MV_MERGE_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to replace mv merge data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_MV_MERGE_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_MV_MERGE_DATA_EN_M  (H264_DBG_REPLACE_MV_MERGE_DATA_EN_V << H264_DBG_REPLACE_MV_MERGE_DATA_EN_S)
+#define H264_DBG_REPLACE_MV_MERGE_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_MV_MERGE_DATA_EN_S  0
+/** H264_DBG_REPLACE_MV_MERGE_DATA : R/W; bitpos: [8:1]; default: 0;
+ *  Configures mv merge data to be replaced.
+ */
+#define H264_DBG_REPLACE_MV_MERGE_DATA    0x000000FFU
+#define H264_DBG_REPLACE_MV_MERGE_DATA_M  (H264_DBG_REPLACE_MV_MERGE_DATA_V << H264_DBG_REPLACE_MV_MERGE_DATA_S)
+#define H264_DBG_REPLACE_MV_MERGE_DATA_V  0x000000FFU
+#define H264_DBG_REPLACE_MV_MERGE_DATA_S  1
+
+/** H264_BS_DEBUG_CONG_REG register
+ *  Encode bitstream debug configuration register
+ */
+#define H264_BS_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x104)
+/** H264_DBG_REPLACE_WR_BS_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to replace bs data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_WR_BS_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_WR_BS_DATA_EN_M  (H264_DBG_REPLACE_WR_BS_DATA_EN_V << H264_DBG_REPLACE_WR_BS_DATA_EN_S)
+#define H264_DBG_REPLACE_WR_BS_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_WR_BS_DATA_EN_S  0
+/** H264_DBG_REPLACE_WR_BS_DATA : R/W; bitpos: [8:1]; default: 0;
+ *  Configures bs data to be replaced
+ */
+#define H264_DBG_REPLACE_WR_BS_DATA    0x000000FFU
+#define H264_DBG_REPLACE_WR_BS_DATA_M  (H264_DBG_REPLACE_WR_BS_DATA_V << H264_DBG_REPLACE_WR_BS_DATA_S)
+#define H264_DBG_REPLACE_WR_BS_DATA_V  0x000000FFU
+#define H264_DBG_REPLACE_WR_BS_DATA_S  1
+
+/** H264_DB_WR_TEMP_DEBUG_CONG_REG register
+ *  Deblocking filter write temp debug configuration register
+ */
+#define H264_DB_WR_TEMP_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x108)
+/** H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure deblocking filter whether or not to replace write temp data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_M  (H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_V << H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_S)
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_EN_S  0
+/** H264_DBG_REPLACE_WR_DB_TEMP_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configure deblocking filter write temp data to be replaced.byte0~2 is VUY
+ */
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_M  (H264_DBG_REPLACE_WR_DB_TEMP_DATA_V << H264_DBG_REPLACE_WR_DB_TEMP_DATA_S)
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_WR_DB_TEMP_DATA_S  1
+
+/** H264_DB_RD_TEMP_DEBUG_CONG_REG register
+ *  Deblocking filter read temp debug configuration register
+ */
+#define H264_DB_RD_TEMP_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x10c)
+/** H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure deblocking filter whether or not to replace read temp data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_M  (H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_V << H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_S)
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_EN_S  0
+/** H264_DBG_REPLACE_RD_DB_TEMP_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configure deblocking filter read temp data to be replaced.byte0~2 is VUY
+ */
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_M  (H264_DBG_REPLACE_RD_DB_TEMP_DATA_V << H264_DBG_REPLACE_RD_DB_TEMP_DATA_S)
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_RD_DB_TEMP_DATA_S  1
+
+/** H264_DB_WR_DEBUG_CONG_REG register
+ *  Deblocking filter final data debug configuration register
+ */
+#define H264_DB_WR_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x110)
+/** H264_DBG_REPLACE_WR_DB_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure deblocking filter whether or not to replace write data.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_WR_DB_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_WR_DB_DATA_EN_M  (H264_DBG_REPLACE_WR_DB_DATA_EN_V << H264_DBG_REPLACE_WR_DB_DATA_EN_S)
+#define H264_DBG_REPLACE_WR_DB_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_WR_DB_DATA_EN_S  0
+/** H264_DBG_REPLACE_WR_DB_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configure deblocking filter write data to be replaced.byte0~2 is VUY
+ */
+#define H264_DBG_REPLACE_WR_DB_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_WR_DB_DATA_M  (H264_DBG_REPLACE_WR_DB_DATA_V << H264_DBG_REPLACE_WR_DB_DATA_S)
+#define H264_DBG_REPLACE_WR_DB_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_WR_DB_DATA_S  1
+
+/** H264_REF_DEBUG_CONG_REG register
+ *  Deblocking filter final data debug configuration register
+ */
+#define H264_REF_DEBUG_CONG_REG (DR_REG_H264_BASE + 0x114)
+/** H264_DBG_REPLACE_REF_DATA_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether to replace reference picture pixels.
+ *  0: not replace
+ *  1: replace
+ */
+#define H264_DBG_REPLACE_REF_DATA_EN    (BIT(0))
+#define H264_DBG_REPLACE_REF_DATA_EN_M  (H264_DBG_REPLACE_REF_DATA_EN_V << H264_DBG_REPLACE_REF_DATA_EN_S)
+#define H264_DBG_REPLACE_REF_DATA_EN_V  0x00000001U
+#define H264_DBG_REPLACE_REF_DATA_EN_S  0
+/** H264_DBG_REPLACE_REF_DATA : R/W; bitpos: [24:1]; default: 0;
+ *  Configure reference picture pixels to be replaced.byte0~2 is VUY
+ */
+#define H264_DBG_REPLACE_REF_DATA    0x00FFFFFFU
+#define H264_DBG_REPLACE_REF_DATA_M  (H264_DBG_REPLACE_REF_DATA_V << H264_DBG_REPLACE_REF_DATA_S)
+#define H264_DBG_REPLACE_REF_DATA_V  0x00FFFFFFU
+#define H264_DBG_REPLACE_REF_DATA_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/h264_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/h264_struct.h
new file mode 100644
index 0000000000..81d4832dec
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/h264_struct.h
@@ -0,0 +1,2127 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of sys_ctrl register
+ *  H264 system level control register.
+ */
+typedef union {
+    struct {
+        /** frame_start : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to start encoding one frame.
+         *  0: Invalid. No effect
+         *  1: Start encoding one frame
+         */
+        uint32_t frame_start:1;
+        /** dma_move_start : WT; bitpos: [1]; default: 0;
+         *  Configures whether or not to start moving reference data from external mem.
+         *  0: Invalid. No effect
+         *  1: H264 start moving two MB lines of reference frame from external mem to internal
+         *  mem
+         */
+        uint32_t dma_move_start:1;
+        /** frame_mode : R/W; bitpos: [2]; default: 0;
+         *  Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this
+         *  field must be set to 1 too.
+         *  0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA
+         *  1: Frame mode. Before every frame start, need reconfig reference frame DMA
+         */
+        uint32_t frame_mode:1;
+        /** sys_rst_pulse : WT; bitpos: [3]; default: 0;
+         *  Configures whether or not to reset H264 ip.
+         *  0: Invalid. No effect
+         *  1: Reset H264 ip
+         */
+        uint32_t sys_rst_pulse:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_sys_ctrl_reg_t;
+
+/** Type of gop_conf register
+ *  GOP related configuration register.
+ */
+typedef union {
+    struct {
+        /** dual_stream_mode : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable dual stream mode. When this field is set to 1,
+         *  H264_FRAME_MODE field must be set to 1 too.
+         *  0: Normal mode
+         *  1: Dual stream mode
+         */
+        uint32_t dual_stream_mode:1;
+        /** gop_num : R/W; bitpos: [8:1]; default: 0;
+         *  Configures the frame number of one GOP.
+         *  0: The frame number of one GOP is infinite
+         *  Others: Actual frame number of one GOP
+         */
+        uint32_t gop_num:8;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_gop_conf_reg_t;
+
+/** Type of a_sys_mb_res register
+ *  Video A horizontal and vertical MB resolution register.
+ */
+typedef union {
+    struct {
+        /** a_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0;
+         *  Configures video A vertical MB resolution.
+         */
+        uint32_t a_sys_total_mb_y:7;
+        /** a_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0;
+         *  Configures video A horizontal MB resolution.
+         */
+        uint32_t a_sys_total_mb_x:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} h264_a_sys_mb_res_reg_t;
+
+/** Type of a_sys_conf register
+ *  Video A system level configuration register.
+ */
+typedef union {
+    struct {
+        /** a_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3;
+         *  Configures when to trigger  video A H264_DB_TMP_READY_INT. When the (MB number of
+         *  written db temp+1) is greater than this filed in first MB line, trigger
+         *  H264_DB_TMP_READY_INT. Min is 3.
+         */
+        uint32_t a_db_tmp_ready_trigger_mb_num:7;
+        /** a_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4;
+         *  Configures when to trigger  video A H264_REC_READY_INT. When the MB line number of
+         *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
+         *  Min is 4.
+         */
+        uint32_t a_rec_ready_trigger_mb_lines:7;
+        /** a_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0;
+         *  Configures video A intra cost offset when I MB compared with P MB.
+         */
+        uint32_t a_intra_cost_cmp_offset:16;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} h264_a_sys_conf_reg_t;
+
+/** Type of a_deci_score register
+ *  Video A luma and chroma MB decimate score Register.
+ */
+typedef union {
+    struct {
+        /** a_c_deci_score : R/W; bitpos: [9:0]; default: 0;
+         *  Configures video A chroma MB decimate score. When chroma score is smaller than it,
+         *  chroma decimate will be enable.
+         */
+        uint32_t a_c_deci_score:10;
+        /** a_l_deci_score : R/W; bitpos: [19:10]; default: 0;
+         *  Configures video A luma MB decimate score. When luma score is smaller than it, luma
+         *  decimate will be enable.
+         */
+        uint32_t a_l_deci_score:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_a_deci_score_reg_t;
+
+/** Type of a_deci_score_offset register
+ *  Video A luma and chroma MB decimate score offset Register.
+ */
+typedef union {
+    struct {
+        /** a_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0;
+         *  Configures video A i16x16 MB decimate score offset. This offset will be added to
+         *  i16x16 MB score.
+         */
+        uint32_t a_i16x16_deci_score_offset:6;
+        /** a_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0;
+         *  Configures video A I chroma MB decimate score offset. This offset will be added to
+         *  I chroma MB score.
+         */
+        uint32_t a_i_chroma_deci_score_offset:6;
+        /** a_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0;
+         *  Configures video A p16x16 MB decimate score offset. This offset will be added to
+         *  p16x16 MB score.
+         */
+        uint32_t a_p16x16_deci_score_offset:6;
+        /** a_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0;
+         *  Configures video A p chroma MB decimate score offset. This offset will be added to
+         *  p chroma MB score.
+         */
+        uint32_t a_p_chroma_deci_score_offset:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_a_deci_score_offset_reg_t;
+
+/** Type of a_rc_conf0 register
+ *  Video A rate control configuration register0.
+ */
+typedef union {
+    struct {
+        /** a_qp : R/W; bitpos: [5:0]; default: 0;
+         *  Configures video A frame level initial luma QP value.
+         */
+        uint32_t a_qp:6;
+        /** a_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0;
+         *  Configures video A parameter U value. U = int((float) u << 8).
+         */
+        uint32_t a_rate_ctrl_u:16;
+        /** a_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0;
+         *  Configures video A whether or not to open macro block rate ctrl.
+         *  1:Open the macro block rate ctrl
+         *  1:Close the macro block rate ctrl.
+         */
+        uint32_t a_mb_rate_ctrl_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} h264_a_rc_conf0_reg_t;
+
+/** Type of a_rc_conf1 register
+ *  Video A rate control configuration register1.
+ */
+typedef union {
+    struct {
+        /** a_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0;
+         *  Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
+         *  QP(after map) + reg_chroma_dc_qp_delta.
+         */
+        uint32_t a_chroma_dc_qp_delta:3;
+        /** a_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0;
+         *  Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma
+         *  QP + reg_chroma_qp_delta.
+         */
+        uint32_t a_chroma_qp_delta:4;
+        /** a_qp_min : R/W; bitpos: [12:7]; default: 0;
+         *  Configures video A allowed luma QP min value.
+         */
+        uint32_t a_qp_min:6;
+        /** a_qp_max : R/W; bitpos: [18:13]; default: 0;
+         *  Configures video A allowed luma QP max value.
+         */
+        uint32_t a_qp_max:6;
+        /** a_mad_frame_pred : R/W; bitpos: [30:19]; default: 0;
+         *  Configures vdieo A frame level predicted MB MAD value.
+         */
+        uint32_t a_mad_frame_pred:12;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} h264_a_rc_conf1_reg_t;
+
+/** Type of a_db_bypass register
+ *  Video A Deblocking bypass register
+ */
+typedef union {
+    struct {
+        /** a_bypass_db_filter : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to bypass video A deblcoking filter.
+         *  0: Open the deblock filter
+         *  1: Close the deblock filter
+         */
+        uint32_t a_bypass_db_filter:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} h264_a_db_bypass_reg_t;
+
+/** Type of a_roi_region0 register
+ *  Video A H264 ROI region0 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region0_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 0 in Video A.
+         */
+        uint32_t a_roi_region0_x:7;
+        /** a_roi_region0_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 0 in Video A.
+         */
+        uint32_t a_roi_region0_y:7;
+        /** a_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
+         *  Video A.
+         */
+        uint32_t a_roi_region0_x_len:7;
+        /** a_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 0 in
+         *  Video A.
+         */
+        uint32_t a_roi_region0_y_len:7;
+        /** a_roi_region0_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 0 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region0_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region0_reg_t;
+
+/** Type of a_roi_region1 register
+ *  Video A H264 ROI region1 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region1_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 1 in Video A.
+         */
+        uint32_t a_roi_region1_x:7;
+        /** a_roi_region1_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 1 in Video A.
+         */
+        uint32_t a_roi_region1_y:7;
+        /** a_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
+         *  Video A.
+         */
+        uint32_t a_roi_region1_x_len:7;
+        /** a_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 1 in
+         *  Video A.
+         */
+        uint32_t a_roi_region1_y_len:7;
+        /** a_roi_region1_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 1 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region1_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region1_reg_t;
+
+/** Type of a_roi_region2 register
+ *  Video A H264 ROI region2 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region2_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 2 in Video A.
+         */
+        uint32_t a_roi_region2_x:7;
+        /** a_roi_region2_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 2 in Video A.
+         */
+        uint32_t a_roi_region2_y:7;
+        /** a_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
+         *  Video A.
+         */
+        uint32_t a_roi_region2_x_len:7;
+        /** a_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 2 in
+         *  Video A.
+         */
+        uint32_t a_roi_region2_y_len:7;
+        /** a_roi_region2_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 2 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region2_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region2_reg_t;
+
+/** Type of a_roi_region3 register
+ *  Video A H264 ROI region3 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region3_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 3 in Video A.
+         */
+        uint32_t a_roi_region3_x:7;
+        /** a_roi_region3_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 3 in Video A.
+         */
+        uint32_t a_roi_region3_y:7;
+        /** a_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
+         *  video A.
+         */
+        uint32_t a_roi_region3_x_len:7;
+        /** a_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 3 in
+         *  video A.
+         */
+        uint32_t a_roi_region3_y_len:7;
+        /** a_roi_region3_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 3 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region3_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region3_reg_t;
+
+/** Type of a_roi_region4 register
+ *  Video A H264 ROI region4 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region4_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 4 in Video A.
+         */
+        uint32_t a_roi_region4_x:7;
+        /** a_roi_region4_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 4 in Video A.
+         */
+        uint32_t a_roi_region4_y:7;
+        /** a_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
+         *  video A.
+         */
+        uint32_t a_roi_region4_x_len:7;
+        /** a_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 4 in
+         *  video A.
+         */
+        uint32_t a_roi_region4_y_len:7;
+        /** a_roi_region4_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 4 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region4_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region4_reg_t;
+
+/** Type of a_roi_region5 register
+ *  Video A H264 ROI region5 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region5_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontial start macroblocks of region 5 video A.
+         */
+        uint32_t a_roi_region5_x:7;
+        /** a_roi_region5_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 5 video A.
+         */
+        uint32_t a_roi_region5_y:7;
+        /** a_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 5
+         *  video A.
+         */
+        uint32_t a_roi_region5_x_len:7;
+        /** a_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 5 in
+         *  video A.
+         */
+        uint32_t a_roi_region5_y_len:7;
+        /** a_roi_region5_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 5 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region5_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region5_reg_t;
+
+/** Type of a_roi_region6 register
+ *  Video A H264 ROI region6 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region6_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontial start macroblocks of region 6 video A.
+         */
+        uint32_t a_roi_region6_x:7;
+        /** a_roi_region6_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 6 in video A.
+         */
+        uint32_t a_roi_region6_y:7;
+        /** a_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
+         *  video A.
+         */
+        uint32_t a_roi_region6_x_len:7;
+        /** a_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 6 in
+         *  video A.
+         */
+        uint32_t a_roi_region6_y_len:7;
+        /** a_roi_region6_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 6 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region6_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region6_reg_t;
+
+/** Type of a_roi_region7 register
+ *  Video A H264 ROI region7 range configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region7_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 7 in video A.
+         */
+        uint32_t a_roi_region7_x:7;
+        /** a_roi_region7_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 7 in video A.
+         */
+        uint32_t a_roi_region7_y:7;
+        /** a_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
+         *  video A.
+         */
+        uint32_t a_roi_region7_x_len:7;
+        /** a_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 7 in
+         *  video A.
+         */
+        uint32_t a_roi_region7_y_len:7;
+        /** a_roi_region7_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video A ROI of region 7 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t a_roi_region7_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_a_roi_region7_reg_t;
+
+/** Type of a_roi_region0_3_qp register
+ *  Video A H264 ROI region0, region1,region2,region3 QP register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region0_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 ROI region0 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region0_qp:7;
+        /** a_roi_region1_qp : R/W; bitpos: [13:7]; default: 0;
+         *  Configure H264 ROI region1 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region1_qp:7;
+        /** a_roi_region2_qp : R/W; bitpos: [20:14]; default: 0;
+         *  Configure H264 ROI region2 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region2_qp:7;
+        /** a_roi_region3_qp : R/W; bitpos: [27:21]; default: 0;
+         *  Configure H264 ROI region3 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region3_qp:7;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_a_roi_region0_3_qp_reg_t;
+
+/** Type of a_roi_region4_7_qp register
+ *  Video A H264 ROI region4, region5,region6,region7 QP register.
+ */
+typedef union {
+    struct {
+        /** a_roi_region4_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 ROI region4 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region4_qp:7;
+        /** a_roi_region5_qp : R/W; bitpos: [13:7]; default: 0;
+         *  Configure H264 ROI region5 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region5_qp:7;
+        /** a_roi_region6_qp : R/W; bitpos: [20:14]; default: 0;
+         *  Configure H264 ROI region6 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region6_qp:7;
+        /** a_roi_region7_qp : R/W; bitpos: [27:21]; default: 0;
+         *  Configure H264 ROI region7 qp in video A,fixed qp or delta qp.
+         */
+        uint32_t a_roi_region7_qp:7;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_a_roi_region4_7_qp_reg_t;
+
+/** Type of a_no_roi_region_qp_offset register
+ *  Video A H264 no roi region QP register.
+ */
+typedef union {
+    struct {
+        /** a_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 no region qp in video A, delta qp.
+         */
+        uint32_t a_no_roi_region_qp:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_a_no_roi_region_qp_offset_reg_t;
+
+/** Type of a_roi_config register
+ *  Video A H264 ROI configure register.
+ */
+typedef union {
+    struct {
+        /** a_roi_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not to enable ROI in video A.
+         *  0:not enable ROI
+         *  1:enable ROI.
+         */
+        uint32_t a_roi_en:1;
+        /** a_roi_mode : R/W; bitpos: [1]; default: 0;
+         *  Configure the mode of ROI in video A.
+         *  0:fixed qp
+         *  1:delta qp.
+         */
+        uint32_t a_roi_mode:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} h264_a_roi_config_reg_t;
+
+/** Type of b_sys_mb_res register
+ *  Video B horizontal and vertical MB resolution register.
+ */
+typedef union {
+    struct {
+        /** b_sys_total_mb_y : R/W; bitpos: [6:0]; default: 0;
+         *  Configures video B vertical MB resolution.
+         */
+        uint32_t b_sys_total_mb_y:7;
+        /** b_sys_total_mb_x : R/W; bitpos: [13:7]; default: 0;
+         *  Configures video B horizontal MB resolution.
+         */
+        uint32_t b_sys_total_mb_x:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} h264_b_sys_mb_res_reg_t;
+
+/** Type of b_sys_conf register
+ *  Video B system level configuration register.
+ */
+typedef union {
+    struct {
+        /** b_db_tmp_ready_trigger_mb_num : R/W; bitpos: [6:0]; default: 3;
+         *  Configures when to trigger  video B H264_DB_TMP_READY_INT. When the (MB number of
+         *  written db temp+1) is greater than this filed in first MB line, trigger
+         *  H264_DB_TMP_READY_INT. Min is 3.
+         */
+        uint32_t b_db_tmp_ready_trigger_mb_num:7;
+        /** b_rec_ready_trigger_mb_lines : R/W; bitpos: [13:7]; default: 4;
+         *  Configures when to trigger  video B H264_REC_READY_INT. When the MB line number of
+         *  generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT.
+         *  Min is 4.
+         */
+        uint32_t b_rec_ready_trigger_mb_lines:7;
+        /** b_intra_cost_cmp_offset : R/W; bitpos: [29:14]; default: 0;
+         *  Configures video B intra cost offset when I MB compared with P MB.
+         */
+        uint32_t b_intra_cost_cmp_offset:16;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} h264_b_sys_conf_reg_t;
+
+/** Type of b_deci_score register
+ *  Video B luma and chroma MB decimate score Register.
+ */
+typedef union {
+    struct {
+        /** b_c_deci_score : R/W; bitpos: [9:0]; default: 0;
+         *  Configures video B chroma MB decimate score. When chroma score is smaller than it,
+         *  chroma decimate will be enable.
+         */
+        uint32_t b_c_deci_score:10;
+        /** b_l_deci_score : R/W; bitpos: [19:10]; default: 0;
+         *  Configures video B luma MB decimate score. When luma score is smaller than it, luma
+         *  decimate will be enable.
+         */
+        uint32_t b_l_deci_score:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} h264_b_deci_score_reg_t;
+
+/** Type of b_deci_score_offset register
+ *  Video B luma and chroma MB decimate score offset Register.
+ */
+typedef union {
+    struct {
+        /** b_i16x16_deci_score_offset : R/W; bitpos: [5:0]; default: 0;
+         *  Configures video B i16x16 MB decimate score offset. This offset will be added to
+         *  i16x16 MB score.
+         */
+        uint32_t b_i16x16_deci_score_offset:6;
+        /** b_i_chroma_deci_score_offset : R/W; bitpos: [11:6]; default: 0;
+         *  Configures video B I chroma MB decimate score offset. This offset will be added to
+         *  I chroma MB score.
+         */
+        uint32_t b_i_chroma_deci_score_offset:6;
+        /** b_p16x16_deci_score_offset : R/W; bitpos: [17:12]; default: 0;
+         *  Configures video B p16x16 MB decimate score offset. This offset will be added to
+         *  p16x16 MB score.
+         */
+        uint32_t b_p16x16_deci_score_offset:6;
+        /** b_p_chroma_deci_score_offset : R/W; bitpos: [23:18]; default: 0;
+         *  Configures video B p chroma MB decimate score offset. This offset will be added to
+         *  p chroma MB score.
+         */
+        uint32_t b_p_chroma_deci_score_offset:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_b_deci_score_offset_reg_t;
+
+/** Type of b_rc_conf0 register
+ *  Video B rate control configuration register0.
+ */
+typedef union {
+    struct {
+        /** b_qp : R/W; bitpos: [5:0]; default: 0;
+         *  Configures video B frame level initial luma QP value.
+         */
+        uint32_t b_qp:6;
+        /** b_rate_ctrl_u : R/W; bitpos: [21:6]; default: 0;
+         *  Configures video B parameter U value. U = int((float) u << 8).
+         */
+        uint32_t b_rate_ctrl_u:16;
+        /** b_mb_rate_ctrl_en : R/W; bitpos: [22]; default: 0;
+         *  Configures video A whether or not to open macro block rate ctrl.
+         *  1:Open the macro block rate ctrl
+         *  1:Close the macro block rate ctrl.
+         */
+        uint32_t b_mb_rate_ctrl_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} h264_b_rc_conf0_reg_t;
+
+/** Type of b_rc_conf1 register
+ *  Video B rate control configuration register1.
+ */
+typedef union {
+    struct {
+        /** b_chroma_dc_qp_delta : R/W; bitpos: [2:0]; default: 0;
+         *  Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma
+         *  QP(after map) + reg_chroma_dc_qp_delta.
+         */
+        uint32_t b_chroma_dc_qp_delta:3;
+        /** b_chroma_qp_delta : R/W; bitpos: [6:3]; default: 0;
+         *  Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma
+         *  QP + reg_chroma_qp_delta.
+         */
+        uint32_t b_chroma_qp_delta:4;
+        /** b_qp_min : R/W; bitpos: [12:7]; default: 0;
+         *  Configures video B allowed luma QP min value.
+         */
+        uint32_t b_qp_min:6;
+        /** b_qp_max : R/W; bitpos: [18:13]; default: 0;
+         *  Configures video B allowed luma QP max value.
+         */
+        uint32_t b_qp_max:6;
+        /** b_mad_frame_pred : R/W; bitpos: [30:19]; default: 0;
+         *  Configures vdieo B frame level predicted MB MAD value.
+         */
+        uint32_t b_mad_frame_pred:12;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} h264_b_rc_conf1_reg_t;
+
+/** Type of b_db_bypass register
+ *  Video B Deblocking bypass register
+ */
+typedef union {
+    struct {
+        /** b_bypass_db_filter : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to bypass video B deblcoking filter.
+         *  0: Open the deblock filter
+         *  1: Close the deblock filter
+         */
+        uint32_t b_bypass_db_filter:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} h264_b_db_bypass_reg_t;
+
+/** Type of b_roi_region0 register
+ *  Video B H264 ROI region0 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region0_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 0 in Video B.
+         */
+        uint32_t b_roi_region0_x:7;
+        /** b_roi_region0_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 0 in Video B.
+         */
+        uint32_t b_roi_region0_y:7;
+        /** b_roi_region0_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 0 in
+         *  Video B.
+         */
+        uint32_t b_roi_region0_x_len:7;
+        /** b_roi_region0_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 0 in
+         *  Video B.
+         */
+        uint32_t b_roi_region0_y_len:7;
+        /** b_roi_region0_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 0 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region0_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region0_reg_t;
+
+/** Type of b_roi_region1 register
+ *  Video B H264 ROI region1 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region1_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 1 in Video B.
+         */
+        uint32_t b_roi_region1_x:7;
+        /** b_roi_region1_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 1 in Video B.
+         */
+        uint32_t b_roi_region1_y:7;
+        /** b_roi_region1_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 1 in
+         *  Video B.
+         */
+        uint32_t b_roi_region1_x_len:7;
+        /** b_roi_region1_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 1 in
+         *  Video B.
+         */
+        uint32_t b_roi_region1_y_len:7;
+        /** b_roi_region1_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 1 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region1_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region1_reg_t;
+
+/** Type of b_roi_region2 register
+ *  Video B H264 ROI region2 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region2_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 2 in Video B.
+         */
+        uint32_t b_roi_region2_x:7;
+        /** b_roi_region2_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 2 in Video B.
+         */
+        uint32_t b_roi_region2_y:7;
+        /** b_roi_region2_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 2 in
+         *  Video B.
+         */
+        uint32_t b_roi_region2_x_len:7;
+        /** b_roi_region2_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 2 in
+         *  Video B.
+         */
+        uint32_t b_roi_region2_y_len:7;
+        /** b_roi_region2_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 2 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region2_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region2_reg_t;
+
+/** Type of b_roi_region3 register
+ *  Video B H264 ROI region3 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region3_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 3 in Video B.
+         */
+        uint32_t b_roi_region3_x:7;
+        /** b_roi_region3_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 3 in Video B.
+         */
+        uint32_t b_roi_region3_y:7;
+        /** b_roi_region3_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 3 in
+         *  video B.
+         */
+        uint32_t b_roi_region3_x_len:7;
+        /** b_roi_region3_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 3 in
+         *  video B.
+         */
+        uint32_t b_roi_region3_y_len:7;
+        /** b_roi_region3_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 3 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region3_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region3_reg_t;
+
+/** Type of b_roi_region4 register
+ *  Video B H264 ROI region4 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region4_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 4 in Video B.
+         */
+        uint32_t b_roi_region4_x:7;
+        /** b_roi_region4_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 4 in Video B.
+         */
+        uint32_t b_roi_region4_y:7;
+        /** b_roi_region4_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 4 in
+         *  video B.
+         */
+        uint32_t b_roi_region4_x_len:7;
+        /** b_roi_region4_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 4 in
+         *  video B.
+         */
+        uint32_t b_roi_region4_y_len:7;
+        /** b_roi_region4_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 4 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region4_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region4_reg_t;
+
+/** Type of b_roi_region5 register
+ *  Video B H264 ROI region5 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region5_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontial start macroblocks of region 5 video B.
+         */
+        uint32_t b_roi_region5_x:7;
+        /** b_roi_region5_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 5 video B.
+         */
+        uint32_t b_roi_region5_y:7;
+        /** b_roi_region5_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 5
+         *  video B.
+         */
+        uint32_t b_roi_region5_x_len:7;
+        /** b_roi_region5_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 5 in
+         *  video B.
+         */
+        uint32_t b_roi_region5_y_len:7;
+        /** b_roi_region5_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 5 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region5_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region5_reg_t;
+
+/** Type of b_roi_region6 register
+ *  Video B H264 ROI region6 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region6_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontial start macroblocks of region 6 video B.
+         */
+        uint32_t b_roi_region6_x:7;
+        /** b_roi_region6_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 6 in video B.
+         */
+        uint32_t b_roi_region6_y:7;
+        /** b_roi_region6_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 6 in
+         *  video B.
+         */
+        uint32_t b_roi_region6_x_len:7;
+        /** b_roi_region6_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 6 in
+         *  video B.
+         */
+        uint32_t b_roi_region6_y_len:7;
+        /** b_roi_region6_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 6 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region6_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region6_reg_t;
+
+/** Type of b_roi_region7 register
+ *  Video B H264 ROI region7 range configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region7_x : R/W; bitpos: [6:0]; default: 0;
+         *  Configures the horizontal start macroblocks of region 7 in video B.
+         */
+        uint32_t b_roi_region7_x:7;
+        /** b_roi_region7_y : R/W; bitpos: [13:7]; default: 0;
+         *  Configures the  vertical start macroblocks of region 7 in video B.
+         */
+        uint32_t b_roi_region7_y:7;
+        /** b_roi_region7_x_len : R/W; bitpos: [20:14]; default: 0;
+         *  Configures the number of  macroblocks in horizontal direction of  the region 7 in
+         *  video B.
+         */
+        uint32_t b_roi_region7_x_len:7;
+        /** b_roi_region7_y_len : R/W; bitpos: [27:21]; default: 0;
+         *  Configures the number of  macroblocks in vertical direction of  the region 7 in
+         *  video B.
+         */
+        uint32_t b_roi_region7_y_len:7;
+        /** b_roi_region7_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to open Video B ROI of region 7 .
+         *  0:Close ROI
+         *  1:Open ROI.
+         */
+        uint32_t b_roi_region7_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} h264_b_roi_region7_reg_t;
+
+/** Type of b_roi_region0_3_qp register
+ *  Video B H264 ROI region0, region1,region2,region3 QP register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region0_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 ROI region0 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region0_qp:7;
+        /** b_roi_region1_qp : R/W; bitpos: [13:7]; default: 0;
+         *  Configure H264 ROI region1 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region1_qp:7;
+        /** b_roi_region2_qp : R/W; bitpos: [20:14]; default: 0;
+         *  Configure H264 ROI region2 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region2_qp:7;
+        /** b_roi_region3_qp : R/W; bitpos: [27:21]; default: 0;
+         *  Configure H264 ROI region3 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region3_qp:7;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_b_roi_region0_3_qp_reg_t;
+
+/** Type of b_roi_region4_7_qp register
+ *  Video B H264 ROI region4, region5,region6,region7 QP register.
+ */
+typedef union {
+    struct {
+        /** b_roi_region4_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 ROI region4 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region4_qp:7;
+        /** b_roi_region5_qp : R/W; bitpos: [13:7]; default: 0;
+         *  Configure H264 ROI region5 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region5_qp:7;
+        /** b_roi_region6_qp : R/W; bitpos: [20:14]; default: 0;
+         *  Configure H264 ROI region6 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region6_qp:7;
+        /** b_roi_region7_qp : R/W; bitpos: [27:21]; default: 0;
+         *  Configure H264 ROI region7 qp in video B,fixed qp or delta qp.
+         */
+        uint32_t b_roi_region7_qp:7;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_b_roi_region4_7_qp_reg_t;
+
+/** Type of b_no_roi_region_qp_offset register
+ *  Video B H264 no roi region QP register.
+ */
+typedef union {
+    struct {
+        /** b_no_roi_region_qp : R/W; bitpos: [6:0]; default: 0;
+         *  Configure H264 no region qp in video B, delta qp.
+         */
+        uint32_t b_no_roi_region_qp:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_b_no_roi_region_qp_offset_reg_t;
+
+/** Type of b_roi_config register
+ *  Video B H264 ROI configure register.
+ */
+typedef union {
+    struct {
+        /** b_roi_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether or not to enable ROI in video B.
+         *  0:not enable ROI
+         *  1:enable ROI.
+         */
+        uint32_t b_roi_en:1;
+        /** b_roi_mode : R/W; bitpos: [1]; default: 0;
+         *  Configure the mode of ROI in video B.
+         *  0:fixed qp
+         *  1:delta qp.
+         */
+        uint32_t b_roi_mode:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} h264_b_roi_config_reg_t;
+
+/** Type of slice_header_remain register
+ *  Frame Slice Header remain bit register.
+ */
+typedef union {
+    struct {
+        /** slice_remain_bitlength : R/W; bitpos: [2:0]; default: 0;
+         *  Configures Slice Header remain bit number
+         */
+        uint32_t slice_remain_bitlength:3;
+        /** slice_remain_bit : R/W; bitpos: [10:3]; default: 0;
+         *  Configures Slice Header remain bit
+         */
+        uint32_t slice_remain_bit:8;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_slice_header_remain_reg_t;
+
+/** Type of slice_header_byte_length register
+ *  Frame Slice Header byte length register.
+ */
+typedef union {
+    struct {
+        /** slice_byte_length : R/W; bitpos: [3:0]; default: 0;
+         *  Configures Slice Header byte number
+         */
+        uint32_t slice_byte_length:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} h264_slice_header_byte_length_reg_t;
+
+/** Type of bs_threshold register
+ *  Bitstream buffer overflow threshold register
+ */
+typedef union {
+    struct {
+        /** bs_buffer_threshold : R/W; bitpos: [6:0]; default: 48;
+         *  Configures bitstream buffer overflow threshold. This value should be bigger than
+         *  the encode bytes of one 4x4 submb.
+         */
+        uint32_t bs_buffer_threshold:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} h264_bs_threshold_reg_t;
+
+/** Type of slice_header_byte0 register
+ *  Frame Slice Header byte low 32 bit  register.
+ */
+typedef union {
+    struct {
+        /** slice_byte_lsb : R/W; bitpos: [31:0]; default: 0;
+         *  Configures Slice Header low 32 bit
+         */
+        uint32_t slice_byte_lsb:32;
+    };
+    uint32_t val;
+} h264_slice_header_byte0_reg_t;
+
+/** Type of slice_header_byte1 register
+ *  Frame Slice Header byte high 32 bit  register.
+ */
+typedef union {
+    struct {
+        /** slice_byte_msb : R/W; bitpos: [31:0]; default: 0;
+         *  Configures Slice Header high 32 bit
+         */
+        uint32_t slice_byte_msb:32;
+    };
+    uint32_t val;
+} h264_slice_header_byte1_reg_t;
+
+/** Type of conf register
+ *  General configuration register.
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to open register clock gate.
+         *  0: Open the clock gate only when application writes registers
+         *  1: Force open the clock gate for register
+         */
+        uint32_t clk_en:1;
+        /** rec_ram_clk_en2 : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to open the clock gate for rec ram2.
+         *  0: Open the clock gate only when application writes or reads rec ram2
+         *  1: Force open the clock gate for rec ram2
+         */
+        uint32_t rec_ram_clk_en2:1;
+        /** rec_ram_clk_en1 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to open the clock gate for rec ram1.
+         *  0: Open the clock gate only when application writes or reads rec ram1
+         *  1: Force open the clock gate for rec ram1
+         */
+        uint32_t rec_ram_clk_en1:1;
+        /** quant_ram_clk_en2 : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to open the clock gate for quant ram2.
+         *  0: Open the clock gate only when application writes or reads quant ram2
+         *  1: Force open the clock gate for quant ram2
+         */
+        uint32_t quant_ram_clk_en2:1;
+        /** quant_ram_clk_en1 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to open the clock gate for quant ram1.
+         *  0: Open the clock gate only when application writes or reads quant ram1
+         *  1: Force open the clock gate for quant ram1
+         */
+        uint32_t quant_ram_clk_en1:1;
+        /** pre_ram_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to open the clock gate for pre ram.
+         *  0: Open the clock gate only when application writes or reads pre ram
+         *  1: Force open the clock gate for pre ram
+         */
+        uint32_t pre_ram_clk_en:1;
+        /** mvd_ram_clk_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to open the clock gate for mvd ram.
+         *  0: Open the clock gate only when application writes or reads mvd ram
+         *  1: Force open the clock gate for mvd ram
+         */
+        uint32_t mvd_ram_clk_en:1;
+        /** mc_ram_clk_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to open the clock gate for mc ram.
+         *  0: Open the clock gate only when application writes or reads mc ram
+         *  1: Force open the clock gate for mc ram
+         */
+        uint32_t mc_ram_clk_en:1;
+        /** ref_ram_clk_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to open the clock gate for ref ram.
+         *  0: Open the clock gate only when application writes or reads ref ram
+         *  1: Force open the clock gate for ref ram
+         */
+        uint32_t ref_ram_clk_en:1;
+        /** i4x4_ref_ram_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to open the clock gate for i4x4_mode ram.
+         *  0: Open the clock gate only when application writes or reads i4x4_mode ram
+         *  1: Force open the clock gate for i4x4_mode ram
+         */
+        uint32_t i4x4_ref_ram_clk_en:1;
+        /** ime_ram_clk_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to open the clock gate for ime ram.
+         *  0: Open the clock gate only when application writes or reads ime ram
+         *  1: Force open the clock gate for ime ram
+         */
+        uint32_t ime_ram_clk_en:1;
+        /** fme_ram_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to open the clock gate for fme ram.
+         *  0: Open the clock gate only when application writes or readsfme ram
+         *  1: Force open the clock gate for fme ram
+         */
+        uint32_t fme_ram_clk_en:1;
+        /** fetch_ram_clk_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to open the clock gate for fetch ram.
+         *  0: Open the clock gate only when application writes or reads fetch ram
+         *  1: Force open the clock gate for fetch ram
+         */
+        uint32_t fetch_ram_clk_en:1;
+        /** db_ram_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to open the clock gate for db ram.
+         *  0: Open the clock gate only when application writes or reads db ram
+         *  1: Force open the clock gate for db ram
+         */
+        uint32_t db_ram_clk_en:1;
+        /** cur_mb_ram_clk_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to open the clock gate for cur_mb ram.
+         *  0: Open the clock gate only when application writes or reads cur_mb ram
+         *  1: Force open the clock gate for cur_mb ram
+         */
+        uint32_t cur_mb_ram_clk_en:1;
+        /** cavlc_ram_clk_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to open the clock gate for cavlc ram.
+         *  0: Open the clock gate only when application writes or reads cavlc ram
+         *  1: Force open the clock gate for cavlc ram
+         */
+        uint32_t cavlc_ram_clk_en:1;
+        /** ime_clk_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to open the clock gate for ime.
+         *  0: Open the clock gate only when ime work
+         *  1: Force open the clock gate for ime
+         */
+        uint32_t ime_clk_en:1;
+        /** fme_clk_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to open the clock gate for fme.
+         *  0: Open the clock gate only when fme work
+         *  1: Force open the clock gate for fme
+         */
+        uint32_t fme_clk_en:1;
+        /** mc_clk_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to open the clock gate for mc.
+         *  0: Open the clock gate only when mc work
+         *  1: Force open the clock gate for mc
+         */
+        uint32_t mc_clk_en:1;
+        /** interpolator_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to open the clock gate for interpolator.
+         *  0: Open the clock gate only when interpolator work
+         *  1: Force open the clock gate for interpolator
+         */
+        uint32_t interpolator_clk_en:1;
+        /** db_clk_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to open the clock gate for deblocking filter.
+         *  0: Open the clock gate only when deblocking filter work
+         *  1: Force open the clock gate for deblocking filter
+         */
+        uint32_t db_clk_en:1;
+        /** clavlc_clk_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to open the clock gate for cavlc.
+         *  0: Open the clock gate only when cavlc work
+         *  1: Force open the clock gate for cavlc
+         */
+        uint32_t clavlc_clk_en:1;
+        /** intra_clk_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to open the clock gate for intra.
+         *  0: Open the clock gate only when intra work
+         *  1: Force open the clock gate for intra
+         */
+        uint32_t intra_clk_en:1;
+        /** deci_clk_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to open the clock gate for decimate.
+         *  0: Open the clock gate only when decimate work
+         *  1: Force open the clock gate for decimate
+         */
+        uint32_t deci_clk_en:1;
+        /** bs_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to open the clock gate for bs buffer.
+         *  0: Open the clock gate only when bs buffer work
+         *  1: Force open the clock gate for bs buffer
+         */
+        uint32_t bs_clk_en:1;
+        /** mv_merge_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to open the clock gate for mv merge.
+         *  0: Open the clock gate only when mv merge work
+         *  1: Force open the clock gate for mv merge
+         */
+        uint32_t mv_merge_clk_en:1;
+        /** cur_mb_rdcmb_clk_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to open the clock gate for cur_mb read macroblock.
+         *  0: Open the clock gate only when cur_mb read macroblock work
+         *  1: Force open the clock gate for  cur_mb read macroblock
+         */
+        uint32_t cur_mb_rdcmb_clk_en:1;
+        /** cur_mb_refresh_reggroup_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to open the clock gate for cur_mb refresh register group.
+         *  0: Open the clock gate only when cur_mb refresh register group work
+         *  1: Force open the clock gate for  cur_mb  refresh register group
+         */
+        uint32_t cur_mb_refresh_reggroup_clk_en:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_conf_reg_t;
+
+/** Type of mv_merge_config register
+ *  Mv merge configuration register.
+ */
+typedef union {
+    struct {
+        /** mv_merge_type : R/W; bitpos: [1:0]; default: 0;
+         *  Configure mv merge type.
+         *  0: merge p16x16 mv
+         *  1: merge min mv
+         *  2: merge max mv
+         *  3: not valid.
+         */
+        uint32_t mv_merge_type:2;
+        /** int_mv_out_en : R/W; bitpos: [2]; default: 0;
+         *  Configure mv merge output integer part not zero mv or all part not zero mv.
+         *  0: output all part not zero mv
+         *  1: output integer part not zero mv.
+         */
+        uint32_t int_mv_out_en:1;
+        /** a_mv_merge_en : R/W; bitpos: [3]; default: 0;
+         *  Configure whether or not to enable video A mv merge.
+         *  0: disable
+         *  1: enable.
+         */
+        uint32_t a_mv_merge_en:1;
+        /** b_mv_merge_en : R/W; bitpos: [4]; default: 0;
+         *  Configure whether or not to enable video B mv merge.
+         *  0: disable
+         *  1: enable.
+         */
+        uint32_t b_mv_merge_en:1;
+        /** mb_valid_num : RO; bitpos: [17:5]; default: 0;
+         *  Represents the valid mb number of mv merge output.
+         */
+        uint32_t mb_valid_num:13;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} h264_mv_merge_config_reg_t;
+
+/** Type of debug_dma_sel register
+ *  Debug H264 DMA select register
+ */
+typedef union {
+    struct {
+        /** dbg_dma_sel : R/W; bitpos: [7:0]; default: 0;
+         *  Every bit represents a dma in h264
+         */
+        uint32_t dbg_dma_sel:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} h264_debug_dma_sel_reg_t;
+
+/** Type of a_ori_conf register
+ *  Video A original picture configuration register.
+ */
+typedef union {
+    struct {
+        /** a_ori_color_space : R/W; bitpos: [2:0]; default: 4;
+         *  Configures video A original picture color space.
+         *  0: RGB888
+         *  1: RGB565
+         *  2: YUV444
+         *  3: YUV422
+         *  4: YUV420
+         *  5: GRAY
+         *  Others: Invalid
+         */
+        uint32_t a_ori_color_space:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} h264_a_ori_conf_reg_t;
+
+/** Type of b_ori_conf register
+ *  Video B original picture configuration register.
+ */
+typedef union {
+    struct {
+        /** b_ori_color_space : R/W; bitpos: [2:0]; default: 4;
+         *  Configures video B original picture color space.
+         *  0: RGB888
+         *  1: RGB565
+         *  2: YUV444
+         *  3: YUV422
+         *  4: YUV420
+         *  5: GRAY
+         *  Others: Invalid
+         */
+        uint32_t b_ori_color_space:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} h264_b_ori_conf_reg_t;
+
+/** Type of ori_debug_conf register
+ *  Original picture debug configuration register.
+ */
+typedef union {
+    struct {
+        /** dbg_replace_ori_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to replace original picture pixels.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_ori_data_en:1;
+        /** dbg_replace_ori_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configures original picture pixels to be replaced. When the original picture color
+         *  space is RGB, byte0~2 is BGR. When the original picture color space is YUV, byte0~2
+         *  is VUY. When the original picture color space is GRAY, byte0 is GRAY.
+         */
+        uint32_t dbg_replace_ori_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_ori_debug_conf_reg_t;
+
+/** Type of mv_merge_debug_conf register
+ *  Original picture debug configuration register.
+ */
+typedef union {
+    struct {
+        /** dbg_replace_mv_merge_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to replace mv merge data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_mv_merge_data_en:1;
+        /** dbg_replace_mv_merge_data : R/W; bitpos: [8:1]; default: 0;
+         *  Configures mv merge data to be replaced.
+         */
+        uint32_t dbg_replace_mv_merge_data:8;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_mv_merge_debug_conf_reg_t;
+
+/** Type of bs_debug_cong register
+ *  Encode bitstream debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_wr_bs_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to replace bs data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_wr_bs_data_en:1;
+        /** dbg_replace_wr_bs_data : R/W; bitpos: [8:1]; default: 0;
+         *  Configures bs data to be replaced
+         */
+        uint32_t dbg_replace_wr_bs_data:8;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} h264_bs_debug_cong_reg_t;
+
+/** Type of db_wr_temp_debug_cong register
+ *  Deblocking filter write temp debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_wr_db_temp_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configure deblocking filter whether or not to replace write temp data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_wr_db_temp_data_en:1;
+        /** dbg_replace_wr_db_temp_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configure deblocking filter write temp data to be replaced.byte0~2 is VUY
+         */
+        uint32_t dbg_replace_wr_db_temp_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_db_wr_temp_debug_cong_reg_t;
+
+/** Type of db_rd_temp_debug_cong register
+ *  Deblocking filter read temp debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_rd_db_temp_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configure deblocking filter whether or not to replace read temp data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_rd_db_temp_data_en:1;
+        /** dbg_replace_rd_db_temp_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configure deblocking filter read temp data to be replaced.byte0~2 is VUY
+         */
+        uint32_t dbg_replace_rd_db_temp_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_db_rd_temp_debug_cong_reg_t;
+
+/** Type of db_wr_debug_cong register
+ *  Deblocking filter final data debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_wr_db_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configure deblocking filter whether or not to replace write data.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_wr_db_data_en:1;
+        /** dbg_replace_wr_db_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configure deblocking filter write data to be replaced.byte0~2 is VUY
+         */
+        uint32_t dbg_replace_wr_db_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_db_wr_debug_cong_reg_t;
+
+/** Type of ref_debug_cong register
+ *  Deblocking filter final data debug configuration register
+ */
+typedef union {
+    struct {
+        /** dbg_replace_ref_data_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether to replace reference picture pixels.
+         *  0: not replace
+         *  1: replace
+         */
+        uint32_t dbg_replace_ref_data_en:1;
+        /** dbg_replace_ref_data : R/W; bitpos: [24:1]; default: 0;
+         *  Configure reference picture pixels to be replaced.byte0~2 is VUY
+         */
+        uint32_t dbg_replace_ref_data:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} h264_ref_debug_cong_reg_t;
+
+
+/** Group: Status Register */
+/** Type of rc_status0 register
+ *  Rate control status register0.
+ */
+typedef union {
+    struct {
+        /** frame_mad_sum : RO; bitpos: [20:0]; default: 0;
+         *  Represents all MB actual MAD sum value of one frame.
+         */
+        uint32_t frame_mad_sum:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} h264_rc_status0_reg_t;
+
+/** Type of rc_status1 register
+ *  Rate control status register1.
+ */
+typedef union {
+    struct {
+        /** frame_enc_bits : RO; bitpos: [26:0]; default: 0;
+         *  Represents all MB actual encoding bits sum value of one frame.
+         */
+        uint32_t frame_enc_bits:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} h264_rc_status1_reg_t;
+
+/** Type of rc_status2 register
+ *  Rate control status register2.
+ */
+typedef union {
+    struct {
+        /** frame_qp_sum : RO; bitpos: [18:0]; default: 0;
+         *  Represents all MB actual luma QP sum value of one frame.
+         */
+        uint32_t frame_qp_sum:19;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} h264_rc_status2_reg_t;
+
+/** Type of sys_status register
+ *  System status register.
+ */
+typedef union {
+    struct {
+        /** frame_num : RO; bitpos: [8:0]; default: 0;
+         *  Represents current frame number.
+         */
+        uint32_t frame_num:9;
+        /** dual_stream_sel : RO; bitpos: [9]; default: 0;
+         *  Represents which register group is used for cur frame.
+         *  0: Register group A is used
+         *  1: Register group B is used.
+         */
+        uint32_t dual_stream_sel:1;
+        /** intra_flag : RO; bitpos: [10]; default: 0;
+         *  Represents the type of current encoding frame.
+         *  0: P frame
+         *  1: I frame.
+         */
+        uint32_t intra_flag:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} h264_sys_status_reg_t;
+
+/** Type of frame_code_length register
+ *  Frame code byte length register.
+ */
+typedef union {
+    struct {
+        /** frame_code_length : RO; bitpos: [23:0]; default: 0;
+         *  Represents current frame code byte length.
+         */
+        uint32_t frame_code_length:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} h264_frame_code_length_reg_t;
+
+/** Type of debug_info0 register
+ *  Debug information register0.
+ */
+typedef union {
+    struct {
+        /** top_ctrl_inter_debug_state : RO; bitpos: [3:0]; default: 0;
+         *  Represents top_ctrl_inter module FSM info.
+         */
+        uint32_t top_ctrl_inter_debug_state:4;
+        /** top_ctrl_intra_debug_state : RO; bitpos: [6:4]; default: 0;
+         *  Represents top_ctrl_intra module FSM info.
+         */
+        uint32_t top_ctrl_intra_debug_state:3;
+        /** p_i_cmp_debug_state : RO; bitpos: [9:7]; default: 0;
+         *  Represents p_i_cmp module FSM info.
+         */
+        uint32_t p_i_cmp_debug_state:3;
+        /** mvd_debug_state : RO; bitpos: [12:10]; default: 0;
+         *  Represents mvd module FSM info.
+         */
+        uint32_t mvd_debug_state:3;
+        /** mc_chroma_ip_debug_state : RO; bitpos: [13]; default: 0;
+         *  Represents mc_chroma_ip module FSM info.
+         */
+        uint32_t mc_chroma_ip_debug_state:1;
+        /** intra_16x16_chroma_ctrl_debug_state : RO; bitpos: [17:14]; default: 0;
+         *  Represents intra_16x16_chroma_ctrl module FSM info.
+         */
+        uint32_t intra_16x16_chroma_ctrl_debug_state:4;
+        /** intra_4x4_ctrl_debug_state : RO; bitpos: [21:18]; default: 0;
+         *  Represents intra_4x4_ctrl module FSM info.
+         */
+        uint32_t intra_4x4_ctrl_debug_state:4;
+        /** intra_top_ctrl_debug_state : RO; bitpos: [24:22]; default: 0;
+         *  Represents intra_top_ctrl module FSM info.
+         */
+        uint32_t intra_top_ctrl_debug_state:3;
+        /** ime_ctrl_debug_state : RO; bitpos: [27:25]; default: 0;
+         *  Represents ime_ctrl module FSM info.
+         */
+        uint32_t ime_ctrl_debug_state:3;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_debug_info0_reg_t;
+
+/** Type of debug_info1 register
+ *  Debug information register1.
+ */
+typedef union {
+    struct {
+        /** fme_ctrl_debug_state : RO; bitpos: [2:0]; default: 0;
+         *  Represents fme_ctrl module FSM info.
+         */
+        uint32_t fme_ctrl_debug_state:3;
+        /** deci_calc_debug_state : RO; bitpos: [4:3]; default: 0;
+         *  Represents deci_calc module's FSM info. DEV use only.
+         */
+        uint32_t deci_calc_debug_state:2;
+        /** db_debug_state : RO; bitpos: [7:5]; default: 0;
+         *  Represents db module FSM info.
+         */
+        uint32_t db_debug_state:3;
+        /** cavlc_enc_debug_state : RO; bitpos: [11:8]; default: 0;
+         *  Represents cavlc module enc FSM info.
+         */
+        uint32_t cavlc_enc_debug_state:4;
+        /** cavlc_scan_debug_state : RO; bitpos: [15:12]; default: 0;
+         *  Represents cavlc module scan FSM info.
+         */
+        uint32_t cavlc_scan_debug_state:4;
+        /** cavlc_ctrl_debug_state : RO; bitpos: [17:16]; default: 0;
+         *  Represents cavlc module ctrl FSM info.
+         */
+        uint32_t cavlc_ctrl_debug_state:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} h264_debug_info1_reg_t;
+
+/** Type of debug_info2 register
+ *  Debug information register2.
+ */
+typedef union {
+    struct {
+        /** p_rc_done_debug_flag : RO; bitpos: [0]; default: 0;
+         *  Represents p rate ctrl done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_rc_done_debug_flag:1;
+        /** p_p_i_cmp_done_debug_flag : RO; bitpos: [1]; default: 0;
+         *  Represents p p_i_cmp done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_p_i_cmp_done_debug_flag:1;
+        /** p_mv_merge_done_debug_flag : RO; bitpos: [2]; default: 0;
+         *  Represents p mv merge done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_mv_merge_done_debug_flag:1;
+        /** p_move_ori_done_debug_flag : RO; bitpos: [3]; default: 0;
+         *  Represents p move origin done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_move_ori_done_debug_flag:1;
+        /** p_mc_done_debug_flag : RO; bitpos: [4]; default: 0;
+         *  Represents p mc done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_mc_done_debug_flag:1;
+        /** p_ime_done_debug_flag : RO; bitpos: [5]; default: 0;
+         *  Represents p ime done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_ime_done_debug_flag:1;
+        /** p_get_ori_done_debug_flag : RO; bitpos: [6]; default: 0;
+         *  Represents p get origin done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_get_ori_done_debug_flag:1;
+        /** p_fme_done_debug_flag : RO; bitpos: [7]; default: 0;
+         *  Represents p fme done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_fme_done_debug_flag:1;
+        /** p_fetch_done_debug_flag : RO; bitpos: [8]; default: 0;
+         *  Represents p fetch done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_fetch_done_debug_flag:1;
+        /** p_db_done_debug_flag : RO; bitpos: [9]; default: 0;
+         *  Represents p deblocking done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_db_done_debug_flag:1;
+        /** p_bs_buf_done_debug_flag : RO; bitpos: [10]; default: 0;
+         *  Represents p bitstream buffer done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t p_bs_buf_done_debug_flag:1;
+        /** ref_move_2mb_line_done_debug_flag : RO; bitpos: [11]; default: 0;
+         *  Represents dma move 2 ref mb line done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t ref_move_2mb_line_done_debug_flag:1;
+        /** i_p_i_cmp_done_debug_flag : RO; bitpos: [12]; default: 0;
+         *  Represents I p_i_cmp done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_p_i_cmp_done_debug_flag:1;
+        /** i_move_ori_done_debug_flag : RO; bitpos: [13]; default: 0;
+         *  Represents I move origin done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_move_ori_done_debug_flag:1;
+        /** i_get_ori_done_debug_flag : RO; bitpos: [14]; default: 0;
+         *  Represents I get origin done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_get_ori_done_debug_flag:1;
+        /** i_ec_done_debug_flag : RO; bitpos: [15]; default: 0;
+         *  Represents I encoder done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_ec_done_debug_flag:1;
+        /** i_db_done_debug_flag : RO; bitpos: [16]; default: 0;
+         *  Represents I deblocking done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_db_done_debug_flag:1;
+        /** i_bs_buf_done_debug_flag : RO; bitpos: [17]; default: 0;
+         *  Represents I bitstream buffer done status.
+         *  0: not done
+         *  1: done.
+         */
+        uint32_t i_bs_buf_done_debug_flag:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} h264_debug_info2_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** db_tmp_ready_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Raw status bit: The raw interrupt status of  H264_DB_TMP_READY_INT. Triggered when
+         *  H264 written enough db tmp pixel.
+         */
+        uint32_t db_tmp_ready_int_raw:1;
+        /** rec_ready_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Raw status bit: The raw interrupt status of  H264_REC_READY_INT. Triggered when
+         *  H264 encoding enough reconstruct pixel.
+         */
+        uint32_t rec_ready_int_raw:1;
+        /** frame_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Raw status bit: The raw interrupt status of  H264_FRAME_DONE_INT. Triggered when
+         *  H264 encoding one frame done.
+         */
+        uint32_t frame_done_int_raw:1;
+        /** dma_move_2mb_line_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT.
+         *  Triggered when H264 move two MB lines of reference frame from external mem to
+         *  internal mem done.
+         */
+        uint32_t dma_move_2mb_line_done_int_raw:1;
+        /** bs_buffer_overflow_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Raw status bit: The raw interrupt status of H264_BS_BUFFER_OVERFLOW_INT. Triggered
+         *  when H264 bit stream buffer overflow.
+         */
+        uint32_t bs_buffer_overflow_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt masked status register
+ */
+typedef union {
+    struct {
+        /** db_tmp_ready_int_st : RO; bitpos: [0]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_DB_TMP_READY_INT. Valid only
+         *  when the H264_DB_TMP_READY_INT_ENA is set to 1.
+         */
+        uint32_t db_tmp_ready_int_st:1;
+        /** rec_ready_int_st : RO; bitpos: [1]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_REC_READY_INT. Valid only
+         *  when the H264_REC_READY_INT_ENA is set to 1.
+         */
+        uint32_t rec_ready_int_st:1;
+        /** frame_done_int_st : RO; bitpos: [2]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_FRAME_DONE_INT. Valid only
+         *  when the H264_FRAME_DONE_INT_ENA is set to 1.
+         */
+        uint32_t frame_done_int_st:1;
+        /** dma_move_2mb_line_done_int_st : RO; bitpos: [3]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT.
+         *  Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1.
+         */
+        uint32_t dma_move_2mb_line_done_int_st:1;
+        /** bs_buffer_overflow_int_st : RO; bitpos: [4]; default: 0;
+         *  Masked status bit: The masked interrupt status of H264_BS_BUFFER_OVERFLOW_INT.
+         *  Valid only when the H264_BS_BUFFER_OVERFLOW_INT_ENA is set to 1.
+         */
+        uint32_t bs_buffer_overflow_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** db_tmp_ready_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable bit: Write 1 to enable H264_DB_TMP_READY_INT.
+         */
+        uint32_t db_tmp_ready_int_ena:1;
+        /** rec_ready_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Enable bit: Write 1 to enable H264_REC_READY_INT.
+         */
+        uint32_t rec_ready_int_ena:1;
+        /** frame_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Enable bit: Write 1 to enable H264_FRAME_DONE_INT.
+         */
+        uint32_t frame_done_int_ena:1;
+        /** dma_move_2mb_line_done_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT.
+         */
+        uint32_t dma_move_2mb_line_done_int_ena:1;
+        /** bs_buffer_overflow_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Enable bit: Write 1 to enable H264_BS_BUFFER_OVERFLOW_INT.
+         */
+        uint32_t bs_buffer_overflow_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** db_tmp_ready_int_clr : WT; bitpos: [0]; default: 0;
+         *  Clear bit: Write 1 to clear H264_DB_TMP_READY_INT.
+         */
+        uint32_t db_tmp_ready_int_clr:1;
+        /** rec_ready_int_clr : WT; bitpos: [1]; default: 0;
+         *  Clear bit: Write 1 to clear H264_REC_READY_INT.
+         */
+        uint32_t rec_ready_int_clr:1;
+        /** frame_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Clear bit: Write 1 to clear H264_FRAME_DONE_INT.
+         */
+        uint32_t frame_done_int_clr:1;
+        /** dma_move_2mb_line_done_int_clr : WT; bitpos: [3]; default: 0;
+         *  Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT.
+         */
+        uint32_t dma_move_2mb_line_done_int_clr:1;
+        /** bs_buffer_overflow_int_clr : WT; bitpos: [4]; default: 0;
+         *  Clear bit: Write 1 to clear H264_BS_BUFFER_OVERFLOW_INT.
+         */
+        uint32_t bs_buffer_overflow_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} h264_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37823232;
+         *  Configures the version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} h264_date_reg_t;
+
+
+typedef struct {
+    volatile h264_sys_ctrl_reg_t sys_ctrl;
+    volatile h264_gop_conf_reg_t gop_conf;
+    volatile h264_a_sys_mb_res_reg_t a_sys_mb_res;
+    volatile h264_a_sys_conf_reg_t a_sys_conf;
+    volatile h264_a_deci_score_reg_t a_deci_score;
+    volatile h264_a_deci_score_offset_reg_t a_deci_score_offset;
+    volatile h264_a_rc_conf0_reg_t a_rc_conf0;
+    volatile h264_a_rc_conf1_reg_t a_rc_conf1;
+    volatile h264_a_db_bypass_reg_t a_db_bypass;
+    volatile h264_a_roi_region0_reg_t a_roi_region0;
+    volatile h264_a_roi_region1_reg_t a_roi_region1;
+    volatile h264_a_roi_region2_reg_t a_roi_region2;
+    volatile h264_a_roi_region3_reg_t a_roi_region3;
+    volatile h264_a_roi_region4_reg_t a_roi_region4;
+    volatile h264_a_roi_region5_reg_t a_roi_region5;
+    volatile h264_a_roi_region6_reg_t a_roi_region6;
+    volatile h264_a_roi_region7_reg_t a_roi_region7;
+    volatile h264_a_roi_region0_3_qp_reg_t a_roi_region0_3_qp;
+    volatile h264_a_roi_region4_7_qp_reg_t a_roi_region4_7_qp;
+    volatile h264_a_no_roi_region_qp_offset_reg_t a_no_roi_region_qp_offset;
+    volatile h264_a_roi_config_reg_t a_roi_config;
+    volatile h264_b_sys_mb_res_reg_t b_sys_mb_res;
+    volatile h264_b_sys_conf_reg_t b_sys_conf;
+    volatile h264_b_deci_score_reg_t b_deci_score;
+    volatile h264_b_deci_score_offset_reg_t b_deci_score_offset;
+    volatile h264_b_rc_conf0_reg_t b_rc_conf0;
+    volatile h264_b_rc_conf1_reg_t b_rc_conf1;
+    volatile h264_b_db_bypass_reg_t b_db_bypass;
+    volatile h264_b_roi_region0_reg_t b_roi_region0;
+    volatile h264_b_roi_region1_reg_t b_roi_region1;
+    volatile h264_b_roi_region2_reg_t b_roi_region2;
+    volatile h264_b_roi_region3_reg_t b_roi_region3;
+    volatile h264_b_roi_region4_reg_t b_roi_region4;
+    volatile h264_b_roi_region5_reg_t b_roi_region5;
+    volatile h264_b_roi_region6_reg_t b_roi_region6;
+    volatile h264_b_roi_region7_reg_t b_roi_region7;
+    volatile h264_b_roi_region0_3_qp_reg_t b_roi_region0_3_qp;
+    volatile h264_b_roi_region4_7_qp_reg_t b_roi_region4_7_qp;
+    volatile h264_b_no_roi_region_qp_offset_reg_t b_no_roi_region_qp_offset;
+    volatile h264_b_roi_config_reg_t b_roi_config;
+    volatile h264_rc_status0_reg_t rc_status0;
+    volatile h264_rc_status1_reg_t rc_status1;
+    volatile h264_rc_status2_reg_t rc_status2;
+    volatile h264_slice_header_remain_reg_t slice_header_remain;
+    volatile h264_slice_header_byte_length_reg_t slice_header_byte_length;
+    volatile h264_bs_threshold_reg_t bs_threshold;
+    volatile h264_slice_header_byte0_reg_t slice_header_byte0;
+    volatile h264_slice_header_byte1_reg_t slice_header_byte1;
+    volatile h264_int_raw_reg_t int_raw;
+    volatile h264_int_st_reg_t int_st;
+    volatile h264_int_ena_reg_t int_ena;
+    volatile h264_int_clr_reg_t int_clr;
+    volatile h264_conf_reg_t conf;
+    volatile h264_mv_merge_config_reg_t mv_merge_config;
+    volatile h264_debug_dma_sel_reg_t debug_dma_sel;
+    volatile h264_sys_status_reg_t sys_status;
+    volatile h264_frame_code_length_reg_t frame_code_length;
+    volatile h264_debug_info0_reg_t debug_info0;
+    volatile h264_debug_info1_reg_t debug_info1;
+    volatile h264_debug_info2_reg_t debug_info2;
+    volatile h264_date_reg_t date;
+    volatile h264_a_ori_conf_reg_t a_ori_conf;
+    volatile h264_b_ori_conf_reg_t b_ori_conf;
+    volatile h264_ori_debug_conf_reg_t ori_debug_conf;
+    volatile h264_mv_merge_debug_conf_reg_t mv_merge_debug_conf;
+    volatile h264_bs_debug_cong_reg_t bs_debug_cong;
+    volatile h264_db_wr_temp_debug_cong_reg_t db_wr_temp_debug_cong;
+    volatile h264_db_rd_temp_debug_cong_reg_t db_rd_temp_debug_cong;
+    volatile h264_db_wr_debug_cong_reg_t db_wr_debug_cong;
+    volatile h264_ref_debug_cong_reg_t ref_debug_cong;
+} h264_dev_t;
+
+extern h264_dev_t H264;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(h264_dev_t) == 0x118, "Invalid size of h264_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hmac_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/hmac_reg.h
new file mode 100644
index 0000000000..bba02c8bb6
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hmac_reg.h
@@ -0,0 +1,282 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HMAC_SET_START_REG register
+ *  HMAC start control register
+ */
+#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
+/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable HMAC.
+ *
+ *  0: Disable HMAC
+ *
+ *  1: Enable HMAC
+ */
+#define HMAC_SET_START    (BIT(0))
+#define HMAC_SET_START_M  (HMAC_SET_START_V << HMAC_SET_START_S)
+#define HMAC_SET_START_V  0x00000001U
+#define HMAC_SET_START_S  0
+
+/** HMAC_SET_PARA_PURPOSE_REG register
+ *  HMAC parameter configuration register
+ */
+#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
+/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
+ *  Configures the HMAC purpose, refer to the Table . "
+ */
+#define HMAC_PURPOSE_SET    0x0000000FU
+#define HMAC_PURPOSE_SET_M  (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
+#define HMAC_PURPOSE_SET_V  0x0000000FU
+#define HMAC_PURPOSE_SET_S  0
+
+/** HMAC_SET_PARA_KEY_REG register
+ *  HMAC parameters configuration register
+ */
+#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
+/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
+ *  Configures HMAC key. There are six keys with index 0~5. Write the index of the
+ *  selected key to this field.
+ */
+#define HMAC_KEY_SET    0x00000007U
+#define HMAC_KEY_SET_M  (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
+#define HMAC_KEY_SET_V  0x00000007U
+#define HMAC_KEY_SET_S  0
+
+/** HMAC_SET_PARA_FINISH_REG register
+ *  HMAC configuration completion register
+ */
+#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
+/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
+ *  Configures whether to finish HMAC configuration.
+ *
+ *  0: No effect
+ *
+ *  1: Finish configuration
+ */
+#define HMAC_SET_PARA_END    (BIT(0))
+#define HMAC_SET_PARA_END_M  (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
+#define HMAC_SET_PARA_END_V  0x00000001U
+#define HMAC_SET_PARA_END_S  0
+
+/** HMAC_SET_MESSAGE_ONE_REG register
+ *  HMAC message control register
+ */
+#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
+/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
+ *  Calls SHA to calculate one message block.
+ */
+#define HMAC_SET_TEXT_ONE    (BIT(0))
+#define HMAC_SET_TEXT_ONE_M  (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
+#define HMAC_SET_TEXT_ONE_V  0x00000001U
+#define HMAC_SET_TEXT_ONE_S  0
+
+/** HMAC_SET_MESSAGE_ING_REG register
+ *  HMAC message continue register
+ */
+#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
+/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not there are unprocessed message blocks.
+ *
+ *  0: No unprocessed message block
+ *
+ *  1: There are still some message blocks to be processed.
+ */
+#define HMAC_SET_TEXT_ING    (BIT(0))
+#define HMAC_SET_TEXT_ING_M  (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
+#define HMAC_SET_TEXT_ING_V  0x00000001U
+#define HMAC_SET_TEXT_ING_S  0
+
+/** HMAC_SET_MESSAGE_END_REG register
+ *  HMAC message end register
+ */
+#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
+/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
+ *  Configures whether to start hardware padding.
+ *
+ *  0: No effect
+ *
+ *  1: Start hardware padding
+ */
+#define HMAC_SET_TEXT_END    (BIT(0))
+#define HMAC_SET_TEXT_END_M  (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
+#define HMAC_SET_TEXT_END_V  0x00000001U
+#define HMAC_SET_TEXT_END_S  0
+
+/** HMAC_SET_RESULT_FINISH_REG register
+ *  HMAC result reading finish register
+ */
+#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
+/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
+ *  Configures whether to exit upstream mode and clear calculation results.
+ *
+ *  0: Not exit
+ *
+ *  1: Exit upstream mode and clear calculation results.
+ */
+#define HMAC_SET_RESULT_END    (BIT(0))
+#define HMAC_SET_RESULT_END_M  (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
+#define HMAC_SET_RESULT_END_V  0x00000001U
+#define HMAC_SET_RESULT_END_S  0
+
+/** HMAC_SET_INVALIDATE_JTAG_REG register
+ *  Invalidate JTAG result register
+ */
+#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
+/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear calculation results when re-enabling JTAG in
+ *  downstream mode.
+ *
+ *  0: Not clear
+ *
+ *  1: Clear calculation results
+ */
+#define HMAC_SET_INVALIDATE_JTAG    (BIT(0))
+#define HMAC_SET_INVALIDATE_JTAG_M  (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
+#define HMAC_SET_INVALIDATE_JTAG_V  0x00000001U
+#define HMAC_SET_INVALIDATE_JTAG_S  0
+
+/** HMAC_SET_INVALIDATE_DS_REG register
+ *  Invalidate digital signature result register
+ */
+#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
+/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear calculation results of the DS module in
+ *  downstream mode.
+ *
+ *  0: Not clear
+ *
+ *  1: Clear calculation results
+ */
+#define HMAC_SET_INVALIDATE_DS    (BIT(0))
+#define HMAC_SET_INVALIDATE_DS_M  (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
+#define HMAC_SET_INVALIDATE_DS_V  0x00000001U
+#define HMAC_SET_INVALIDATE_DS_S  0
+
+/** HMAC_QUERY_ERROR_REG register
+ *  Stores matching results between keys generated by users and corresponding purposes
+ */
+#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
+/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an HMAC key matches the purpose.
+ *
+ *  0: Match
+ *
+ *  1: Error
+ */
+#define HMAC_QUREY_CHECK    (BIT(0))
+#define HMAC_QUREY_CHECK_M  (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
+#define HMAC_QUREY_CHECK_V  0x00000001U
+#define HMAC_QUREY_CHECK_S  0
+
+/** HMAC_QUERY_BUSY_REG register
+ *  Busy state of HMAC module
+ */
+#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
+/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
+ *  make sure HMAC is in an IDLE state.
+ *
+ *  0: Idle
+ *
+ *  1: HMAC is still working on the calculation
+ */
+#define HMAC_BUSY_STATE    (BIT(0))
+#define HMAC_BUSY_STATE_M  (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
+#define HMAC_BUSY_STATE_V  0x00000001U
+#define HMAC_BUSY_STATE_S  0
+
+/** HMAC_WR_MESSAGE_MEM register
+ *  Message block memory.
+ */
+#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
+#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
+
+/** HMAC_RD_RESULT_MEM register
+ *  Result from upstream.
+ */
+#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
+#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
+
+/** HMAC_SET_MESSAGE_PAD_REG register
+ *  Software padding register
+ */
+#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
+/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
+ *  Configures whether or not the padding is applied by software.
+ *
+ *  0: Not applied by software
+ *
+ *  1: Applied by software
+ */
+#define HMAC_SET_TEXT_PAD    (BIT(0))
+#define HMAC_SET_TEXT_PAD_M  (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
+#define HMAC_SET_TEXT_PAD_V  0x00000001U
+#define HMAC_SET_TEXT_PAD_S  0
+
+/** HMAC_ONE_BLOCK_REG register
+ *  One block message register
+ */
+#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
+/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
+ *  Write 1 to indicate there is only one block which already contains padding bits and
+ *  there is no need for padding.
+ */
+#define HMAC_SET_ONE_BLOCK    (BIT(0))
+#define HMAC_SET_ONE_BLOCK_M  (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
+#define HMAC_SET_ONE_BLOCK_V  0x00000001U
+#define HMAC_SET_ONE_BLOCK_S  0
+
+/** HMAC_SOFT_JTAG_CTRL_REG register
+ *  Jtag register 0.
+ */
+#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
+/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable JTAG authentication mode.
+ *
+ *  0: Disable
+ *
+ *  1: Enable
+ *
+ */
+#define HMAC_SOFT_JTAG_CTRL    (BIT(0))
+#define HMAC_SOFT_JTAG_CTRL_M  (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
+#define HMAC_SOFT_JTAG_CTRL_V  0x00000001U
+#define HMAC_SOFT_JTAG_CTRL_S  0
+
+/** HMAC_WR_JTAG_REG register
+ *  Re-enable JTAG register 1
+ */
+#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
+/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
+ *  Writes the comparing input used for re-enabling JTAG.
+ */
+#define HMAC_WR_JTAG    0xFFFFFFFFU
+#define HMAC_WR_JTAG_M  (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
+#define HMAC_WR_JTAG_V  0xFFFFFFFFU
+#define HMAC_WR_JTAG_S  0
+
+/** HMAC_DATE_REG register
+ *  Version control register
+ */
+#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
+/** HMAC_DATE : R/W; bitpos: [29:0]; default: 539166977;
+ *  Hmac date information/ hmac version information.
+ */
+#define HMAC_DATE    0x3FFFFFFFU
+#define HMAC_DATE_M  (HMAC_DATE_V << HMAC_DATE_S)
+#define HMAC_DATE_V  0x3FFFFFFFU
+#define HMAC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hmac_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/hmac_struct.h
new file mode 100644
index 0000000000..9003f4d58f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hmac_struct.h
@@ -0,0 +1,344 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control/Status Registers */
+/** Type of set_start register
+ *  HMAC start control register
+ */
+typedef union {
+    struct {
+        /** set_start : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable HMAC.
+         *
+         *  0: Disable HMAC
+         *
+         *  1: Enable HMAC
+         */
+        uint32_t set_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_start_reg_t;
+
+/** Type of set_para_finish register
+ *  HMAC configuration completion register
+ */
+typedef union {
+    struct {
+        /** set_para_end : WS; bitpos: [0]; default: 0;
+         *  Configures whether to finish HMAC configuration.
+         *
+         *  0: No effect
+         *
+         *  1: Finish configuration
+         */
+        uint32_t set_para_end:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_para_finish_reg_t;
+
+/** Type of set_message_one register
+ *  HMAC message control register
+ */
+typedef union {
+    struct {
+        /** set_text_one : WS; bitpos: [0]; default: 0;
+         *  Calls SHA to calculate one message block.
+         */
+        uint32_t set_text_one:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_one_reg_t;
+
+/** Type of set_message_ing register
+ *  HMAC message continue register
+ */
+typedef union {
+    struct {
+        /** set_text_ing : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not there are unprocessed message blocks.
+         *
+         *  0: No unprocessed message block
+         *
+         *  1: There are still some message blocks to be processed.
+         */
+        uint32_t set_text_ing:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_ing_reg_t;
+
+/** Type of set_message_end register
+ *  HMAC message end register
+ */
+typedef union {
+    struct {
+        /** set_text_end : WS; bitpos: [0]; default: 0;
+         *  Configures whether to start hardware padding.
+         *
+         *  0: No effect
+         *
+         *  1: Start hardware padding
+         */
+        uint32_t set_text_end:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_end_reg_t;
+
+/** Type of set_result_finish register
+ *  HMAC result reading finish register
+ */
+typedef union {
+    struct {
+        /** set_result_end : WS; bitpos: [0]; default: 0;
+         *  Configures whether to exit upstream mode and clear calculation results.
+         *
+         *  0: Not exit
+         *
+         *  1: Exit upstream mode and clear calculation results.
+         */
+        uint32_t set_result_end:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_result_finish_reg_t;
+
+/** Type of set_invalidate_jtag register
+ *  Invalidate JTAG result register
+ */
+typedef union {
+    struct {
+        /** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear calculation results when re-enabling JTAG in
+         *  downstream mode.
+         *
+         *  0: Not clear
+         *
+         *  1: Clear calculation results
+         */
+        uint32_t set_invalidate_jtag:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_invalidate_jtag_reg_t;
+
+/** Type of set_invalidate_ds register
+ *  Invalidate digital signature result register
+ */
+typedef union {
+    struct {
+        /** set_invalidate_ds : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear calculation results of the DS module in
+         *  downstream mode.
+         *
+         *  0: Not clear
+         *
+         *  1: Clear calculation results
+         */
+        uint32_t set_invalidate_ds:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_invalidate_ds_reg_t;
+
+/** Type of query_error register
+ *  Stores matching results between keys generated by users and corresponding purposes
+ */
+typedef union {
+    struct {
+        /** qurey_check : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not an HMAC key matches the purpose.
+         *
+         *  0: Match
+         *
+         *  1: Error
+         */
+        uint32_t qurey_check:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_query_error_reg_t;
+
+/** Type of query_busy register
+ *  Busy state of HMAC module
+ */
+typedef union {
+    struct {
+        /** busy_state : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
+         *  make sure HMAC is in an IDLE state.
+         *
+         *  0: Idle
+         *
+         *  1: HMAC is still working on the calculation
+         */
+        uint32_t busy_state:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_query_busy_reg_t;
+
+/** Type of set_message_pad register
+ *  Software padding register
+ */
+typedef union {
+    struct {
+        /** set_text_pad : WO; bitpos: [0]; default: 0;
+         *  Configures whether or not the padding is applied by software.
+         *
+         *  0: Not applied by software
+         *
+         *  1: Applied by software
+         */
+        uint32_t set_text_pad:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_pad_reg_t;
+
+/** Type of one_block register
+ *  One block message register
+ */
+typedef union {
+    struct {
+        /** set_one_block : WS; bitpos: [0]; default: 0;
+         *  Write 1 to indicate there is only one block which already contains padding bits and
+         *  there is no need for padding.
+         */
+        uint32_t set_one_block:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_one_block_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of set_para_purpose register
+ *  HMAC parameter configuration register
+ */
+typedef union {
+    struct {
+        /** purpose_set : WO; bitpos: [3:0]; default: 0;
+         *  Configures the HMAC purpose, refer to the Table . "
+         */
+        uint32_t purpose_set:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hmac_set_para_purpose_reg_t;
+
+/** Type of set_para_key register
+ *  HMAC parameters configuration register
+ */
+typedef union {
+    struct {
+        /** key_set : WO; bitpos: [2:0]; default: 0;
+         *  Configures HMAC key. There are six keys with index 0~5. Write the index of the
+         *  selected key to this field.
+         */
+        uint32_t key_set:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hmac_set_para_key_reg_t;
+
+/** Type of wr_jtag register
+ *  Re-enable JTAG register 1
+ */
+typedef union {
+    struct {
+        /** wr_jtag : WO; bitpos: [31:0]; default: 0;
+         *  Writes the comparing input used for re-enabling JTAG.
+         */
+        uint32_t wr_jtag:32;
+    };
+    uint32_t val;
+} hmac_wr_jtag_reg_t;
+
+
+/** Group: Memory Type */
+
+/** Group: Configuration Register */
+/** Type of soft_jtag_ctrl register
+ *  Jtag register 0.
+ */
+typedef union {
+    struct {
+        /** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable JTAG authentication mode.
+         *
+         *  0: Disable
+         *
+         *  1: Enable
+         *
+         */
+        uint32_t soft_jtag_ctrl:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_soft_jtag_ctrl_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 539166977;
+         *  Hmac date information/ hmac version information.
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hmac_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[16];
+    volatile hmac_set_start_reg_t set_start;
+    volatile hmac_set_para_purpose_reg_t set_para_purpose;
+    volatile hmac_set_para_key_reg_t set_para_key;
+    volatile hmac_set_para_finish_reg_t set_para_finish;
+    volatile hmac_set_message_one_reg_t set_message_one;
+    volatile hmac_set_message_ing_reg_t set_message_ing;
+    volatile hmac_set_message_end_reg_t set_message_end;
+    volatile hmac_set_result_finish_reg_t set_result_finish;
+    volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
+    volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
+    volatile hmac_query_error_reg_t query_error;
+    volatile hmac_query_busy_reg_t query_busy;
+    uint32_t reserved_070[4];
+    volatile uint32_t wr_message[16];
+    volatile uint32_t rd_result[8];
+    uint32_t reserved_0e0[4];
+    volatile hmac_set_message_pad_reg_t set_message_pad;
+    volatile hmac_one_block_reg_t one_block;
+    volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
+    volatile hmac_wr_jtag_reg_t wr_jtag;
+    uint32_t reserved_100[63];
+    volatile hmac_date_reg_t date;
+} hmac_dev_t;
+
+extern hmac_dev_t HMAC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_eco5_reg.h
new file mode 100644
index 0000000000..8f08a8e399
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_eco5_reg.h
@@ -0,0 +1,779 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_HP2LP_TEE_PMS_DATE_REG register
+ *  NA
+ */
+#define TEE_HP2LP_TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
+/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
+ *  NA
+ */
+#define TEE_TEE_DATE    0xFFFFFFFFU
+#define TEE_TEE_DATE_M  (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
+#define TEE_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_TEE_DATE_S  0
+
+/** TEE_PMS_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
+/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CLK_EN    (BIT(0))
+#define TEE_REG_CLK_EN_M  (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
+#define TEE_REG_CLK_EN_V  0x00000001U
+#define TEE_REG_CLK_EN_S  0
+
+/** TEE_HP_CORE0_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_HP_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
+/** TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_PMU_ALLOW_S  4
+/** TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_WDT_ALLOW_S  5
+/** TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_RTC_ALLOW_S  7
+/** TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_UART_ALLOW_S  9
+/** TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_I2C_ALLOW_S  10
+/** TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_SPI_ALLOW_S  11
+/** TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_I2S_ALLOW_S  13
+/** TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_ADC_ALLOW_S  14
+/** TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_INTR_ALLOW_S  17
+/** TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_PMS_ALLOW_S  19
+/** TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_M  (TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_HUK_ALLOW_S  22
+/** TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_M  (TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S)
+#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_MM_LP_TRNG_ALLOW_S  24
+
+/** TEE_HP_CORE0_UM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_HP_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0xc)
+/** TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_PMU_ALLOW_S  4
+/** TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_WDT_ALLOW_S  5
+/** TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_RTC_ALLOW_S  7
+/** TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_UART_ALLOW_S  9
+/** TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_I2C_ALLOW_S  10
+/** TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_SPI_ALLOW_S  11
+/** TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_I2S_ALLOW_S  13
+/** TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_ADC_ALLOW_S  14
+/** TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_INTR_ALLOW_S  17
+/** TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_PMS_ALLOW_S  19
+/** TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_M  (TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_HUK_ALLOW_S  22
+/** TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_M  (TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S)
+#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE0_UM_LP_TRNG_ALLOW_S  24
+
+/** TEE_HP_CORE1_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_HP_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x10)
+/** TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_PMU_ALLOW_S  4
+/** TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_WDT_ALLOW_S  5
+/** TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_RTC_ALLOW_S  7
+/** TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_UART_ALLOW_S  9
+/** TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_I2C_ALLOW_S  10
+/** TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_SPI_ALLOW_S  11
+/** TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_I2S_ALLOW_S  13
+/** TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_ADC_ALLOW_S  14
+/** TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_INTR_ALLOW_S  17
+/** TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_PMS_ALLOW_S  19
+/** TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_M  (TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_HUK_ALLOW_S  22
+/** TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_M  (TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S)
+#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_MM_LP_TRNG_ALLOW_S  24
+
+/** TEE_HP_CORE1_UM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_HP_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x14)
+/** TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW    (BIT(0))
+#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_SYSREG_ALLOW_S  0
+/** TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S  1
+/** TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW    (BIT(2))
+#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TIMER_ALLOW_S  2
+/** TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW    (BIT(3))
+#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_ANAPERI_ALLOW_S  3
+/** TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW    (BIT(4))
+#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_PMU_ALLOW_S  4
+/** TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW    (BIT(5))
+#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_WDT_ALLOW_S  5
+/** TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW    (BIT(6))
+#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_MAILBOX_ALLOW_S  6
+/** TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW    (BIT(7))
+#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_RTC_ALLOW_S  7
+/** TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S  8
+/** TEE_REG_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW    (BIT(9))
+#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_UART_ALLOW_S  9
+/** TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW    (BIT(10))
+#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_I2C_ALLOW_S  10
+/** TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW    (BIT(11))
+#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_SPI_ALLOW_S  11
+/** TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW    (BIT(12))
+#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_I2CMST_ALLOW_S  12
+/** TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW    (BIT(13))
+#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_I2S_ALLOW_S  13
+/** TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW    (BIT(14))
+#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_ADC_ALLOW_S  14
+/** TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW    (BIT(15))
+#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TOUCH_ALLOW_S  15
+/** TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW    (BIT(16))
+#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_IOMUX_ALLOW_S  16
+/** TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW    (BIT(17))
+#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_INTR_ALLOW_S  17
+/** TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW    (BIT(18))
+#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_EFUSE_ALLOW_S  18
+/** TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW    (BIT(19))
+#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_PMS_ALLOW_S  19
+/** TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW    (BIT(20))
+#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_M  (TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_HP2LP_PMS_ALLOW_S  20
+/** TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW    (BIT(21))
+#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TSENS_ALLOW_S  21
+/** TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW    (BIT(22))
+#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_HUK_ALLOW_S  22
+/** TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW    (BIT(23))
+#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TCM_RAM_ALLOW_S  23
+/** TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW    (BIT(24))
+#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_M  (TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V << TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S)
+#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_V  0x00000001U
+#define TEE_REG_HP_CORE1_UM_LP_TRNG_ALLOW_S  24
+
+/** TEE_REGDMA_PERI_PMS_REG register
+ *  NA
+ */
+#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x18)
+/** TEE_REG_REGDMA_PERI_LP_RAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW    (BIT(0))
+#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_M  (TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V << TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S)
+#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_V  0x00000001U
+#define TEE_REG_REGDMA_PERI_LP_RAM_ALLOW_S  0
+/** TEE_REG_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW    (BIT(1))
+#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_M  (TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S)
+#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_V  0x00000001U
+#define TEE_REG_REGDMA_PERI_LP_PERI_ALLOW_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_reg.h
new file mode 100644
index 0000000000..3bebeb4ce4
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_reg.h
@@ -0,0 +1,969 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_HP2LP_PERI_PMS_DATE_REG register
+ *  Version control register
+ */
+#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x0)
+/** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
+ *  Version control register
+ */
+#define PMS_HP2LP_PERI_PMS_DATE    0xFFFFFFFFU
+#define PMS_HP2LP_PERI_PMS_DATE_M  (PMS_HP2LP_PERI_PMS_DATE_V << PMS_HP2LP_PERI_PMS_DATE_S)
+#define PMS_HP2LP_PERI_PMS_DATE_V  0xFFFFFFFFU
+#define PMS_HP2LP_PERI_PMS_DATE_S  0
+
+/** PMS_HP2LP_PERI_PMS_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_HP2LP_PERI_PMS_CLK_EN_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x4)
+/** PMS_HP2LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating
+ *  1: Keep the clock always on
+ */
+#define PMS_HP2LP_PERI_PMS_CLK_EN    (BIT(0))
+#define PMS_HP2LP_PERI_PMS_CLK_EN_M  (PMS_HP2LP_PERI_PMS_CLK_EN_V << PMS_HP2LP_PERI_PMS_CLK_EN_S)
+#define PMS_HP2LP_PERI_PMS_CLK_EN_V  0x00000001U
+#define PMS_HP2LP_PERI_PMS_CLK_EN_S  0
+
+/** PMS_HP_CORE0_MM_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU0 in machine mode
+ */
+#define PMS_HP_CORE0_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x8)
+/** PMS_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP System
+ *  Registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_M  (PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_V << PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_SYSREG_ALLOW_S  0
+/** PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP_AONCLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_M  (PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_HP_CORE0_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW_M  (PMS_HP_CORE0_MM_LP_TIMER_ALLOW_V << PMS_HP_CORE0_MM_LP_TIMER_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_TIMER_ALLOW_S  2
+/** PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP ANAPERI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_M  (PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_ANAPERI_ALLOW_S  3
+/** PMS_HP_CORE0_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP PMU.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_HP_CORE0_MM_LP_PMU_ALLOW_M  (PMS_HP_CORE0_MM_LP_PMU_ALLOW_V << PMS_HP_CORE0_MM_LP_PMU_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_PMU_ALLOW_S  4
+/** PMS_HP_CORE0_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP WDT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_HP_CORE0_MM_LP_WDT_ALLOW_M  (PMS_HP_CORE0_MM_LP_WDT_ALLOW_V << PMS_HP_CORE0_MM_LP_WDT_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_WDT_ALLOW_S  5
+/** PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_M  (PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_MAILBOX_ALLOW_S  6
+/** PMS_HP_CORE0_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE0_MM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_HP_CORE0_MM_LP_RTC_ALLOW_M  (PMS_HP_CORE0_MM_LP_RTC_ALLOW_V << PMS_HP_CORE0_MM_LP_RTC_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_RTC_ALLOW_S  7
+/** PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP PERICLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_M  (PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_HP_CORE0_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_UART_ALLOW    (BIT(9))
+#define PMS_HP_CORE0_MM_LP_UART_ALLOW_M  (PMS_HP_CORE0_MM_LP_UART_ALLOW_V << PMS_HP_CORE0_MM_LP_UART_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_UART_ALLOW_S  9
+/** PMS_HP_CORE0_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP I2C.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_HP_CORE0_MM_LP_I2C_ALLOW_M  (PMS_HP_CORE0_MM_LP_I2C_ALLOW_V << PMS_HP_CORE0_MM_LP_I2C_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_I2C_ALLOW_S  10
+/** PMS_HP_CORE0_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_HP_CORE0_MM_LP_SPI_ALLOW_M  (PMS_HP_CORE0_MM_LP_SPI_ALLOW_V << PMS_HP_CORE0_MM_LP_SPI_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_SPI_ALLOW_S  11
+/** PMS_HP_CORE0_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_M  (PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_V << PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_I2CMST_ALLOW_S  12
+/** PMS_HP_CORE0_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_HP_CORE0_MM_LP_I2S_ALLOW_M  (PMS_HP_CORE0_MM_LP_I2S_ALLOW_V << PMS_HP_CORE0_MM_LP_I2S_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_I2S_ALLOW_S  13
+/** PMS_HP_CORE0_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_HP_CORE0_MM_LP_ADC_ALLOW_M  (PMS_HP_CORE0_MM_LP_ADC_ALLOW_V << PMS_HP_CORE0_MM_LP_ADC_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_ADC_ALLOW_S  14
+/** PMS_HP_CORE0_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP touch
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_M  (PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_V << PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_TOUCH_ALLOW_S  15
+/** PMS_HP_CORE0_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_M  (PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_V << PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_IOMUX_ALLOW_S  16
+/** PMS_HP_CORE0_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP INTR.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_HP_CORE0_MM_LP_INTR_ALLOW_M  (PMS_HP_CORE0_MM_LP_INTR_ALLOW_V << PMS_HP_CORE0_MM_LP_INTR_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_INTR_ALLOW_S  17
+/** PMS_HP_CORE0_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_M  (PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_V << PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_EFUSE_ALLOW_S  18
+/** PMS_HP_CORE0_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access
+ *  LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_HP_CORE0_MM_LP_PMS_ALLOW_M  (PMS_HP_CORE0_MM_LP_PMS_ALLOW_V << PMS_HP_CORE0_MM_LP_PMS_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_PMS_ALLOW_S  19
+/** PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_M  (PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_S)
+#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_HP2LP_PMS_ALLOW_S  20
+/** PMS_HP_CORE0_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW_M  (PMS_HP_CORE0_MM_LP_TSENS_ALLOW_V << PMS_HP_CORE0_MM_LP_TSENS_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_TSENS_ALLOW_S  21
+/** PMS_HP_CORE0_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to LP HUK.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_HP_CORE0_MM_LP_HUK_ALLOW_M  (PMS_HP_CORE0_MM_LP_HUK_ALLOW_V << PMS_HP_CORE0_MM_LP_HUK_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_HUK_ALLOW_S  22
+/** PMS_HP_CORE0_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_M  (PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S)
+#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_MM_LP_SRAM_ALLOW_S  23
+
+/** PMS_HP_CORE0_UM_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU0 in user mode
+ */
+#define PMS_HP_CORE0_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0xc)
+/** PMS_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP System
+ *  Registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_M  (PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_V << PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_SYSREG_ALLOW_S  0
+/** PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP_AONCLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_M  (PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_HP_CORE0_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW_M  (PMS_HP_CORE0_UM_LP_TIMER_ALLOW_V << PMS_HP_CORE0_UM_LP_TIMER_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_TIMER_ALLOW_S  2
+/** PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP ANAPERI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_M  (PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_ANAPERI_ALLOW_S  3
+/** PMS_HP_CORE0_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP PMU.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_HP_CORE0_UM_LP_PMU_ALLOW_M  (PMS_HP_CORE0_UM_LP_PMU_ALLOW_V << PMS_HP_CORE0_UM_LP_PMU_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_PMU_ALLOW_S  4
+/** PMS_HP_CORE0_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP WDT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_HP_CORE0_UM_LP_WDT_ALLOW_M  (PMS_HP_CORE0_UM_LP_WDT_ALLOW_V << PMS_HP_CORE0_UM_LP_WDT_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_WDT_ALLOW_S  5
+/** PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_M  (PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_MAILBOX_ALLOW_S  6
+/** PMS_HP_CORE0_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE0_UM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_HP_CORE0_UM_LP_RTC_ALLOW_M  (PMS_HP_CORE0_UM_LP_RTC_ALLOW_V << PMS_HP_CORE0_UM_LP_RTC_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_RTC_ALLOW_S  7
+/** PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP PERICLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_M  (PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_HP_CORE0_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_UART_ALLOW    (BIT(9))
+#define PMS_HP_CORE0_UM_LP_UART_ALLOW_M  (PMS_HP_CORE0_UM_LP_UART_ALLOW_V << PMS_HP_CORE0_UM_LP_UART_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_UART_ALLOW_S  9
+/** PMS_HP_CORE0_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP I2C.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_HP_CORE0_UM_LP_I2C_ALLOW_M  (PMS_HP_CORE0_UM_LP_I2C_ALLOW_V << PMS_HP_CORE0_UM_LP_I2C_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_I2C_ALLOW_S  10
+/** PMS_HP_CORE0_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_HP_CORE0_UM_LP_SPI_ALLOW_M  (PMS_HP_CORE0_UM_LP_SPI_ALLOW_V << PMS_HP_CORE0_UM_LP_SPI_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_SPI_ALLOW_S  11
+/** PMS_HP_CORE0_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_M  (PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_V << PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_I2CMST_ALLOW_S  12
+/** PMS_HP_CORE0_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_HP_CORE0_UM_LP_I2S_ALLOW_M  (PMS_HP_CORE0_UM_LP_I2S_ALLOW_V << PMS_HP_CORE0_UM_LP_I2S_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_I2S_ALLOW_S  13
+/** PMS_HP_CORE0_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_HP_CORE0_UM_LP_ADC_ALLOW_M  (PMS_HP_CORE0_UM_LP_ADC_ALLOW_V << PMS_HP_CORE0_UM_LP_ADC_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_ADC_ALLOW_S  14
+/** PMS_HP_CORE0_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP touch sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_M  (PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_V << PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_TOUCH_ALLOW_S  15
+/** PMS_HP_CORE0_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_M  (PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_V << PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_IOMUX_ALLOW_S  16
+/** PMS_HP_CORE0_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP INTR.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_HP_CORE0_UM_LP_INTR_ALLOW_M  (PMS_HP_CORE0_UM_LP_INTR_ALLOW_V << PMS_HP_CORE0_UM_LP_INTR_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_INTR_ALLOW_S  17
+/** PMS_HP_CORE0_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_M  (PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_V << PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_EFUSE_ALLOW_S  18
+/** PMS_HP_CORE0_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_HP_CORE0_UM_LP_PMS_ALLOW_M  (PMS_HP_CORE0_UM_LP_PMS_ALLOW_V << PMS_HP_CORE0_UM_LP_PMS_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_PMS_ALLOW_S  19
+/** PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_M  (PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_S)
+#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_HP2LP_PMS_ALLOW_S  20
+/** PMS_HP_CORE0_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW_M  (PMS_HP_CORE0_UM_LP_TSENS_ALLOW_V << PMS_HP_CORE0_UM_LP_TSENS_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_TSENS_ALLOW_S  21
+/** PMS_HP_CORE0_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to LP HUK.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_HP_CORE0_UM_LP_HUK_ALLOW_M  (PMS_HP_CORE0_UM_LP_HUK_ALLOW_V << PMS_HP_CORE0_UM_LP_HUK_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_HUK_ALLOW_S  22
+/** PMS_HP_CORE0_UM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_M  (PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S)
+#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_HP_CORE0_UM_LP_SRAM_ALLOW_S  23
+
+/** PMS_HP_CORE1_MM_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU1 in machine mode
+ */
+#define PMS_HP_CORE1_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x10)
+/** PMS_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP System
+ *  Registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_M  (PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_V << PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_SYSREG_ALLOW_S  0
+/** PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP_AONCLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_M  (PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_HP_CORE1_MM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW_M  (PMS_HP_CORE1_MM_LP_TIMER_ALLOW_V << PMS_HP_CORE1_MM_LP_TIMER_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_TIMER_ALLOW_S  2
+/** PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP ANAPERI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_M  (PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_ANAPERI_ALLOW_S  3
+/** PMS_HP_CORE1_MM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP PMU.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_HP_CORE1_MM_LP_PMU_ALLOW_M  (PMS_HP_CORE1_MM_LP_PMU_ALLOW_V << PMS_HP_CORE1_MM_LP_PMU_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_PMU_ALLOW_S  4
+/** PMS_HP_CORE1_MM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP WDT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_HP_CORE1_MM_LP_WDT_ALLOW_M  (PMS_HP_CORE1_MM_LP_WDT_ALLOW_V << PMS_HP_CORE1_MM_LP_WDT_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_WDT_ALLOW_S  5
+/** PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_M  (PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_MAILBOX_ALLOW_S  6
+/** PMS_HP_CORE1_MM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE1_MM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_HP_CORE1_MM_LP_RTC_ALLOW_M  (PMS_HP_CORE1_MM_LP_RTC_ALLOW_V << PMS_HP_CORE1_MM_LP_RTC_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_RTC_ALLOW_S  7
+/** PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP PERICLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_M  (PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_HP_CORE1_MM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_UART_ALLOW    (BIT(9))
+#define PMS_HP_CORE1_MM_LP_UART_ALLOW_M  (PMS_HP_CORE1_MM_LP_UART_ALLOW_V << PMS_HP_CORE1_MM_LP_UART_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_UART_ALLOW_S  9
+/** PMS_HP_CORE1_MM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP I2C.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_HP_CORE1_MM_LP_I2C_ALLOW_M  (PMS_HP_CORE1_MM_LP_I2C_ALLOW_V << PMS_HP_CORE1_MM_LP_I2C_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_I2C_ALLOW_S  10
+/** PMS_HP_CORE1_MM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_HP_CORE1_MM_LP_SPI_ALLOW_M  (PMS_HP_CORE1_MM_LP_SPI_ALLOW_V << PMS_HP_CORE1_MM_LP_SPI_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_SPI_ALLOW_S  11
+/** PMS_HP_CORE1_MM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_M  (PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_V << PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_I2CMST_ALLOW_S  12
+/** PMS_HP_CORE1_MM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_HP_CORE1_MM_LP_I2S_ALLOW_M  (PMS_HP_CORE1_MM_LP_I2S_ALLOW_V << PMS_HP_CORE1_MM_LP_I2S_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_I2S_ALLOW_S  13
+/** PMS_HP_CORE1_MM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_HP_CORE1_MM_LP_ADC_ALLOW_M  (PMS_HP_CORE1_MM_LP_ADC_ALLOW_V << PMS_HP_CORE1_MM_LP_ADC_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_ADC_ALLOW_S  14
+/** PMS_HP_CORE1_MM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP touch
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_M  (PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_V << PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_TOUCH_ALLOW_S  15
+/** PMS_HP_CORE1_MM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_M  (PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_V << PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_IOMUX_ALLOW_S  16
+/** PMS_HP_CORE1_MM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP INTR.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_HP_CORE1_MM_LP_INTR_ALLOW_M  (PMS_HP_CORE1_MM_LP_INTR_ALLOW_V << PMS_HP_CORE1_MM_LP_INTR_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_INTR_ALLOW_S  17
+/** PMS_HP_CORE1_MM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_M  (PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_V << PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_EFUSE_ALLOW_S  18
+/** PMS_HP_CORE1_MM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access
+ *  LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_HP_CORE1_MM_LP_PMS_ALLOW_M  (PMS_HP_CORE1_MM_LP_PMS_ALLOW_V << PMS_HP_CORE1_MM_LP_PMS_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_PMS_ALLOW_S  19
+/** PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_M  (PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_S)
+#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_HP2LP_PMS_ALLOW_S  20
+/** PMS_HP_CORE1_MM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW_M  (PMS_HP_CORE1_MM_LP_TSENS_ALLOW_V << PMS_HP_CORE1_MM_LP_TSENS_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_TSENS_ALLOW_S  21
+/** PMS_HP_CORE1_MM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to LP HUK.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_HP_CORE1_MM_LP_HUK_ALLOW_M  (PMS_HP_CORE1_MM_LP_HUK_ALLOW_V << PMS_HP_CORE1_MM_LP_HUK_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_HUK_ALLOW_S  22
+/** PMS_HP_CORE1_MM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_M  (PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S)
+#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_MM_LP_SRAM_ALLOW_S  23
+
+/** PMS_HP_CORE1_UM_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU1 in user mode
+ */
+#define PMS_HP_CORE1_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x14)
+/** PMS_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP System
+ *  Registers.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW    (BIT(0))
+#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_M  (PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_V << PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_SYSREG_ALLOW_S  0
+/** PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP_AONCLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW    (BIT(1))
+#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_M  (PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V << PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_AONCLKRST_ALLOW_S  1
+/** PMS_HP_CORE1_UM_LP_TIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW    (BIT(2))
+#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW_M  (PMS_HP_CORE1_UM_LP_TIMER_ALLOW_V << PMS_HP_CORE1_UM_LP_TIMER_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_TIMER_ALLOW_S  2
+/** PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP ANAPERI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW    (BIT(3))
+#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_M  (PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_V << PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_ANAPERI_ALLOW_S  3
+/** PMS_HP_CORE1_UM_LP_PMU_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP PMU.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_PMU_ALLOW    (BIT(4))
+#define PMS_HP_CORE1_UM_LP_PMU_ALLOW_M  (PMS_HP_CORE1_UM_LP_PMU_ALLOW_V << PMS_HP_CORE1_UM_LP_PMU_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_PMU_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_PMU_ALLOW_S  4
+/** PMS_HP_CORE1_UM_LP_WDT_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP WDT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_WDT_ALLOW    (BIT(5))
+#define PMS_HP_CORE1_UM_LP_WDT_ALLOW_M  (PMS_HP_CORE1_UM_LP_WDT_ALLOW_V << PMS_HP_CORE1_UM_LP_WDT_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_WDT_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_WDT_ALLOW_S  5
+/** PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP Mailbox
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW    (BIT(6))
+#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_M  (PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_V << PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_MAILBOX_ALLOW_S  6
+/** PMS_HP_CORE1_UM_LP_RTC_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP RTC.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_HP_CORE1_UM_LP_RTC_ALLOW    (BIT(7))
+#define PMS_HP_CORE1_UM_LP_RTC_ALLOW_M  (PMS_HP_CORE1_UM_LP_RTC_ALLOW_V << PMS_HP_CORE1_UM_LP_RTC_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_RTC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_RTC_ALLOW_S  7
+/** PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP PERICLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW    (BIT(8))
+#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_M  (PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V << PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_PERICLKRST_ALLOW_S  8
+/** PMS_HP_CORE1_UM_LP_UART_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP UART.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_UART_ALLOW    (BIT(9))
+#define PMS_HP_CORE1_UM_LP_UART_ALLOW_M  (PMS_HP_CORE1_UM_LP_UART_ALLOW_V << PMS_HP_CORE1_UM_LP_UART_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_UART_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_UART_ALLOW_S  9
+/** PMS_HP_CORE1_UM_LP_I2C_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP I2C.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_I2C_ALLOW    (BIT(10))
+#define PMS_HP_CORE1_UM_LP_I2C_ALLOW_M  (PMS_HP_CORE1_UM_LP_I2C_ALLOW_V << PMS_HP_CORE1_UM_LP_I2C_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_I2C_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_I2C_ALLOW_S  10
+/** PMS_HP_CORE1_UM_LP_SPI_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP SPI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_SPI_ALLOW    (BIT(11))
+#define PMS_HP_CORE1_UM_LP_SPI_ALLOW_M  (PMS_HP_CORE1_UM_LP_SPI_ALLOW_V << PMS_HP_CORE1_UM_LP_SPI_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_SPI_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_SPI_ALLOW_S  11
+/** PMS_HP_CORE1_UM_LP_I2CMST_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP I2C master.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW    (BIT(12))
+#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_M  (PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_V << PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_I2CMST_ALLOW_S  12
+/** PMS_HP_CORE1_UM_LP_I2S_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP I2S.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_I2S_ALLOW    (BIT(13))
+#define PMS_HP_CORE1_UM_LP_I2S_ALLOW_M  (PMS_HP_CORE1_UM_LP_I2S_ALLOW_V << PMS_HP_CORE1_UM_LP_I2S_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_I2S_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_I2S_ALLOW_S  13
+/** PMS_HP_CORE1_UM_LP_ADC_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_ADC_ALLOW    (BIT(14))
+#define PMS_HP_CORE1_UM_LP_ADC_ALLOW_M  (PMS_HP_CORE1_UM_LP_ADC_ALLOW_V << PMS_HP_CORE1_UM_LP_ADC_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_ADC_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_ADC_ALLOW_S  14
+/** PMS_HP_CORE1_UM_LP_TOUCH_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP touch sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW    (BIT(15))
+#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_M  (PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_V << PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_TOUCH_ALLOW_S  15
+/** PMS_HP_CORE1_UM_LP_IOMUX_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW    (BIT(16))
+#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_M  (PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_V << PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_IOMUX_ALLOW_S  16
+/** PMS_HP_CORE1_UM_LP_INTR_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP INTR.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_INTR_ALLOW    (BIT(17))
+#define PMS_HP_CORE1_UM_LP_INTR_ALLOW_M  (PMS_HP_CORE1_UM_LP_INTR_ALLOW_V << PMS_HP_CORE1_UM_LP_INTR_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_INTR_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_INTR_ALLOW_S  17
+/** PMS_HP_CORE1_UM_LP_EFUSE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP eFuse.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW    (BIT(18))
+#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_M  (PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_V << PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_EFUSE_ALLOW_S  18
+/** PMS_HP_CORE1_UM_LP_PMS_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_PMS_ALLOW    (BIT(19))
+#define PMS_HP_CORE1_UM_LP_PMS_ALLOW_M  (PMS_HP_CORE1_UM_LP_PMS_ALLOW_V << PMS_HP_CORE1_UM_LP_PMS_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_PMS_ALLOW_S  19
+/** PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access
+ *  HP2LP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW    (BIT(20))
+#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_M  (PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_V << PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_S)
+#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_HP2LP_PMS_ALLOW_S  20
+/** PMS_HP_CORE1_UM_LP_TSENS_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP temperature
+ *  sensor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW    (BIT(21))
+#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW_M  (PMS_HP_CORE1_UM_LP_TSENS_ALLOW_V << PMS_HP_CORE1_UM_LP_TSENS_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_TSENS_ALLOW_S  21
+/** PMS_HP_CORE1_UM_LP_HUK_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to LP HUK.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_HUK_ALLOW    (BIT(22))
+#define PMS_HP_CORE1_UM_LP_HUK_ALLOW_M  (PMS_HP_CORE1_UM_LP_HUK_ALLOW_V << PMS_HP_CORE1_UM_LP_HUK_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_HUK_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_HUK_ALLOW_S  22
+/** PMS_HP_CORE1_UM_LP_SRAM_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW    (BIT(23))
+#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_M  (PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V << PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S)
+#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_HP_CORE1_UM_LP_SRAM_ALLOW_S  23
+
+/** PMS_REGDMA_LP_PERI_PMS_REG register
+ *  LP Peripheral Permission register for REGDMA
+ */
+#define PMS_REGDMA_LP_PERI_PMS_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x18)
+/** PMS_REGDMA_PERI_LP_SRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether REGDMA has permission to access LP SRAM.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_REGDMA_PERI_LP_SRAM_ALLOW    (BIT(0))
+#define PMS_REGDMA_PERI_LP_SRAM_ALLOW_M  (PMS_REGDMA_PERI_LP_SRAM_ALLOW_V << PMS_REGDMA_PERI_LP_SRAM_ALLOW_S)
+#define PMS_REGDMA_PERI_LP_SRAM_ALLOW_V  0x00000001U
+#define PMS_REGDMA_PERI_LP_SRAM_ALLOW_S  0
+/** PMS_REGDMA_PERI_LP_PERI_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether REGDMA has permission to access  all LP peripherals.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_REGDMA_PERI_LP_PERI_ALLOW    (BIT(1))
+#define PMS_REGDMA_PERI_LP_PERI_ALLOW_M  (PMS_REGDMA_PERI_LP_PERI_ALLOW_V << PMS_REGDMA_PERI_LP_PERI_ALLOW_S)
+#define PMS_REGDMA_PERI_LP_PERI_ALLOW_V  0x00000001U
+#define PMS_REGDMA_PERI_LP_PERI_ALLOW_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_struct.h
new file mode 100644
index 0000000000..7ec7f73652
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp2lp_peri_pms_struct.h
@@ -0,0 +1,530 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: TEE HP2LP TEE PMS DATE REG */
+/** Type of hp2lp_tee_pms_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 2363943;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_hp2lp_tee_pms_date_reg_t;
+
+
+/** Group: TEE PMS CLK EN REG */
+/** Type of pms_clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_pms_clk_en_reg_t;
+
+
+/** Group: TEE HP CORE0 MM PMS REG0 REG */
+/** Type of hp_core0_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_core0_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_sysreg_allow:1;
+        /** reg_hp_core0_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_aonclkrst_allow:1;
+        /** reg_hp_core0_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_timer_allow:1;
+        /** reg_hp_core0_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_anaperi_allow:1;
+        /** reg_hp_core0_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_pmu_allow:1;
+        /** reg_hp_core0_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_wdt_allow:1;
+        /** reg_hp_core0_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_mailbox_allow:1;
+        /** reg_hp_core0_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_rtc_allow:1;
+        /** reg_hp_core0_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_periclkrst_allow:1;
+        /** reg_hp_core0_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_uart_allow:1;
+        /** reg_hp_core0_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_i2c_allow:1;
+        /** reg_hp_core0_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_spi_allow:1;
+        /** reg_hp_core0_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_i2cmst_allow:1;
+        /** reg_hp_core0_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_i2s_allow:1;
+        /** reg_hp_core0_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_adc_allow:1;
+        /** reg_hp_core0_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_touch_allow:1;
+        /** reg_hp_core0_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_iomux_allow:1;
+        /** reg_hp_core0_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_intr_allow:1;
+        /** reg_hp_core0_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_efuse_allow:1;
+        /** reg_hp_core0_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_pms_allow:1;
+        /** reg_hp_core0_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_hp2lp_pms_allow:1;
+        /** reg_hp_core0_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_tsens_allow:1;
+        /** reg_hp_core0_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_huk_allow:1;
+        /** reg_hp_core0_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_tcm_ram_allow:1;
+        /** reg_hp_core0_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_mm_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_hp_core0_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE HP CORE0 UM PMS REG0 REG */
+/** Type of hp_core0_um_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_core0_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_sysreg_allow:1;
+        /** reg_hp_core0_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_aonclkrst_allow:1;
+        /** reg_hp_core0_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_timer_allow:1;
+        /** reg_hp_core0_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_anaperi_allow:1;
+        /** reg_hp_core0_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_pmu_allow:1;
+        /** reg_hp_core0_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_wdt_allow:1;
+        /** reg_hp_core0_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_mailbox_allow:1;
+        /** reg_hp_core0_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_rtc_allow:1;
+        /** reg_hp_core0_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_periclkrst_allow:1;
+        /** reg_hp_core0_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_uart_allow:1;
+        /** reg_hp_core0_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_i2c_allow:1;
+        /** reg_hp_core0_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_spi_allow:1;
+        /** reg_hp_core0_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_i2cmst_allow:1;
+        /** reg_hp_core0_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_i2s_allow:1;
+        /** reg_hp_core0_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_adc_allow:1;
+        /** reg_hp_core0_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_touch_allow:1;
+        /** reg_hp_core0_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_iomux_allow:1;
+        /** reg_hp_core0_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_intr_allow:1;
+        /** reg_hp_core0_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_efuse_allow:1;
+        /** reg_hp_core0_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_pms_allow:1;
+        /** reg_hp_core0_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_hp2lp_pms_allow:1;
+        /** reg_hp_core0_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_tsens_allow:1;
+        /** reg_hp_core0_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_huk_allow:1;
+        /** reg_hp_core0_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_tcm_ram_allow:1;
+        /** reg_hp_core0_um_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core0_um_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_hp_core0_um_pms_reg0_reg_t;
+
+
+/** Group: TEE HP CORE1 MM PMS REG0 REG */
+/** Type of hp_core1_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_core1_mm_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_sysreg_allow:1;
+        /** reg_hp_core1_mm_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_aonclkrst_allow:1;
+        /** reg_hp_core1_mm_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_timer_allow:1;
+        /** reg_hp_core1_mm_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_anaperi_allow:1;
+        /** reg_hp_core1_mm_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_pmu_allow:1;
+        /** reg_hp_core1_mm_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_wdt_allow:1;
+        /** reg_hp_core1_mm_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_mailbox_allow:1;
+        /** reg_hp_core1_mm_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_rtc_allow:1;
+        /** reg_hp_core1_mm_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_periclkrst_allow:1;
+        /** reg_hp_core1_mm_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_uart_allow:1;
+        /** reg_hp_core1_mm_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_i2c_allow:1;
+        /** reg_hp_core1_mm_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_spi_allow:1;
+        /** reg_hp_core1_mm_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_i2cmst_allow:1;
+        /** reg_hp_core1_mm_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_i2s_allow:1;
+        /** reg_hp_core1_mm_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_adc_allow:1;
+        /** reg_hp_core1_mm_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_touch_allow:1;
+        /** reg_hp_core1_mm_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_iomux_allow:1;
+        /** reg_hp_core1_mm_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_intr_allow:1;
+        /** reg_hp_core1_mm_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_efuse_allow:1;
+        /** reg_hp_core1_mm_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_pms_allow:1;
+        /** reg_hp_core1_mm_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_hp2lp_pms_allow:1;
+        /** reg_hp_core1_mm_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_tsens_allow:1;
+        /** reg_hp_core1_mm_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_huk_allow:1;
+        /** reg_hp_core1_mm_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_tcm_ram_allow:1;
+        /** reg_hp_core1_mm_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_mm_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_hp_core1_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE HP CORE1 UM PMS REG0 REG */
+/** Type of hp_core1_um_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_core1_um_lp_sysreg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_sysreg_allow:1;
+        /** reg_hp_core1_um_lp_aonclkrst_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_aonclkrst_allow:1;
+        /** reg_hp_core1_um_lp_timer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_timer_allow:1;
+        /** reg_hp_core1_um_lp_anaperi_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_anaperi_allow:1;
+        /** reg_hp_core1_um_lp_pmu_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_pmu_allow:1;
+        /** reg_hp_core1_um_lp_wdt_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_wdt_allow:1;
+        /** reg_hp_core1_um_lp_mailbox_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_mailbox_allow:1;
+        /** reg_hp_core1_um_lp_rtc_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_rtc_allow:1;
+        /** reg_hp_core1_um_lp_periclkrst_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_periclkrst_allow:1;
+        /** reg_hp_core1_um_lp_uart_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_uart_allow:1;
+        /** reg_hp_core1_um_lp_i2c_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_i2c_allow:1;
+        /** reg_hp_core1_um_lp_spi_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_spi_allow:1;
+        /** reg_hp_core1_um_lp_i2cmst_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_i2cmst_allow:1;
+        /** reg_hp_core1_um_lp_i2s_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_i2s_allow:1;
+        /** reg_hp_core1_um_lp_adc_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_adc_allow:1;
+        /** reg_hp_core1_um_lp_touch_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_touch_allow:1;
+        /** reg_hp_core1_um_lp_iomux_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_iomux_allow:1;
+        /** reg_hp_core1_um_lp_intr_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_intr_allow:1;
+        /** reg_hp_core1_um_lp_efuse_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_efuse_allow:1;
+        /** reg_hp_core1_um_lp_pms_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_pms_allow:1;
+        /** reg_hp_core1_um_hp2lp_pms_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_hp2lp_pms_allow:1;
+        /** reg_hp_core1_um_lp_tsens_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_tsens_allow:1;
+        /** reg_hp_core1_um_lp_huk_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_huk_allow:1;
+        /** reg_hp_core1_um_lp_tcm_ram_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_tcm_ram_allow:1;
+        /** reg_hp_core1_um_lp_trng_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_hp_core1_um_lp_trng_allow:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} tee_hp_core1_um_pms_reg0_reg_t;
+
+
+/** Group: TEE REGDMA PERI PMS REG */
+/** Type of regdma_peri_pms register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_regdma_peri_lp_ram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_regdma_peri_lp_ram_allow:1;
+        /** reg_regdma_peri_lp_peri_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_regdma_peri_lp_peri_allow:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} tee_regdma_peri_pms_reg_t;
+
+
+typedef struct {
+    volatile tee_hp2lp_tee_pms_date_reg_t hp2lp_tee_pms_date;
+    volatile tee_pms_clk_en_reg_t pms_clk_en;
+    volatile tee_hp_core0_mm_pms_reg0_reg_t hp_core0_mm_pms_reg0;
+    volatile tee_hp_core0_um_pms_reg0_reg_t hp_core0_um_pms_reg0;
+    volatile tee_hp_core1_mm_pms_reg0_reg_t hp_core1_mm_pms_reg0;
+    volatile tee_hp_core1_um_pms_reg0_reg_t hp_core1_um_pms_reg0;
+    volatile tee_regdma_peri_pms_reg_t regdma_peri_pms;
+} tee_dev_t;
+
+extern tee_dev_t HP2LP_PERI_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dev_t) == 0x1c, "Invalid size of tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_eco5_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_eco5_reg.h
new file mode 100644
index 0000000000..cc55fc066c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_eco5_reg.h
@@ -0,0 +1,2232 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TEE_PMS_DATE_REG register
+ *  NA
+ */
+#define TEE_PMS_DATE_REG (DR_REG_TEE_BASE + 0x0)
+/** TEE_TEE_DATE : R/W; bitpos: [31:0]; default: 2363943;
+ *  NA
+ */
+#define TEE_TEE_DATE    0xFFFFFFFFU
+#define TEE_TEE_DATE_M  (TEE_TEE_DATE_V << TEE_TEE_DATE_S)
+#define TEE_TEE_DATE_V  0xFFFFFFFFU
+#define TEE_TEE_DATE_S  0
+
+/** TEE_PMS_CLK_EN_REG register
+ *  NA
+ */
+#define TEE_PMS_CLK_EN_REG (DR_REG_TEE_BASE + 0x4)
+/** TEE_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CLK_EN    (BIT(0))
+#define TEE_REG_CLK_EN_M  (TEE_REG_CLK_EN_V << TEE_REG_CLK_EN_S)
+#define TEE_REG_CLK_EN_V  0x00000001U
+#define TEE_REG_CLK_EN_S  0
+
+/** TEE_CORE0_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_CORE0_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x8)
+/** TEE_REG_CORE0_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_MM_PSRAM_ALLOW_M  (TEE_REG_CORE0_MM_PSRAM_ALLOW_V << TEE_REG_CORE0_MM_PSRAM_ALLOW_S)
+#define TEE_REG_CORE0_MM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_PSRAM_ALLOW_S  0
+/** TEE_REG_CORE0_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_MM_FLASH_ALLOW_M  (TEE_REG_CORE0_MM_FLASH_ALLOW_V << TEE_REG_CORE0_MM_FLASH_ALLOW_S)
+#define TEE_REG_CORE0_MM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_FLASH_ALLOW_S  1
+/** TEE_REG_CORE0_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_MM_L2MEM_ALLOW_M  (TEE_REG_CORE0_MM_L2MEM_ALLOW_V << TEE_REG_CORE0_MM_L2MEM_ALLOW_S)
+#define TEE_REG_CORE0_MM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_L2MEM_ALLOW_S  2
+/** TEE_REG_CORE0_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_MM_L2ROM_ALLOW_M  (TEE_REG_CORE0_MM_L2ROM_ALLOW_V << TEE_REG_CORE0_MM_L2ROM_ALLOW_S)
+#define TEE_REG_CORE0_MM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_L2ROM_ALLOW_S  3
+/** TEE_REG_CORE0_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_MM_TRACE0_ALLOW_M  (TEE_REG_CORE0_MM_TRACE0_ALLOW_V << TEE_REG_CORE0_MM_TRACE0_ALLOW_S)
+#define TEE_REG_CORE0_MM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_TRACE0_ALLOW_S  6
+/** TEE_REG_CORE0_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_MM_TRACE1_ALLOW_M  (TEE_REG_CORE0_MM_TRACE1_ALLOW_V << TEE_REG_CORE0_MM_TRACE1_ALLOW_S)
+#define TEE_REG_CORE0_MM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_TRACE1_ALLOW_S  7
+/** TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_M  (TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_CORE0_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_M  (TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_V << TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_CORE0_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_MM_TCM_MON_ALLOW_M  (TEE_REG_CORE0_MM_TCM_MON_ALLOW_V << TEE_REG_CORE0_MM_TCM_MON_ALLOW_S)
+#define TEE_REG_CORE0_MM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_TCM_MON_ALLOW_S  10
+/** TEE_REG_CORE0_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_MM_CACHE_ALLOW_M  (TEE_REG_CORE0_MM_CACHE_ALLOW_V << TEE_REG_CORE0_MM_CACHE_ALLOW_S)
+#define TEE_REG_CORE0_MM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_CACHE_ALLOW_S  11
+
+/** TEE_CORE0_MM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_CORE0_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0xc)
+/** TEE_REG_CORE0_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_M  (TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_V << TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_M  (TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_CORE0_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW_M  (TEE_REG_CORE0_MM_HP_GDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_GDMA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_CORE0_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_M  (TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_M  (TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_V << TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_CORE0_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW_M  (TEE_REG_CORE0_MM_HP_JPEG_ALLOW_V << TEE_REG_CORE0_MM_HP_JPEG_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_CORE0_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_MM_HP_PPA_ALLOW_M  (TEE_REG_CORE0_MM_HP_PPA_ALLOW_V << TEE_REG_CORE0_MM_HP_PPA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PPA_ALLOW_S  8
+/** TEE_REG_CORE0_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_M  (TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_V << TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_CORE0_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW_M  (TEE_REG_CORE0_MM_HP_FLASH_ALLOW_V << TEE_REG_CORE0_MM_HP_FLASH_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_CORE0_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_M  (TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_V << TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_M  (TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_CORE0_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW_M  (TEE_REG_CORE0_MM_HP_GMAC_ALLOW_V << TEE_REG_CORE0_MM_HP_GMAC_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_M  (TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_CORE0_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_CORE0_MM_HP_PVT_ALLOW_M  (TEE_REG_CORE0_MM_HP_PVT_ALLOW_V << TEE_REG_CORE0_MM_HP_PVT_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PVT_ALLOW_S  17
+/** TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_M  (TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_M  (TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_CORE0_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_CORE0_MM_HP_ISP_ALLOW_M  (TEE_REG_CORE0_MM_HP_ISP_ALLOW_V << TEE_REG_CORE0_MM_HP_ISP_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_ISP_ALLOW_S  20
+/** TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_M  (TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_CORE0_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_CORE0_MM_HP_RMT_ALLOW_M  (TEE_REG_CORE0_MM_HP_RMT_ALLOW_V << TEE_REG_CORE0_MM_HP_RMT_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_RMT_ALLOW_S  22
+/** TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_M  (TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_CORE0_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW_M  (TEE_REG_CORE0_MM_DMA_PMS_ALLOW_V << TEE_REG_CORE0_MM_DMA_PMS_ALLOW_S)
+#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_M  (TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_CORE0_MM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_CORE0_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x10)
+/** TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_M  (TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_M  (TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_CORE0_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2C0_ALLOW_V << TEE_REG_CORE0_MM_HP_I2C0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_CORE0_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2C1_ALLOW_V << TEE_REG_CORE0_MM_HP_I2C1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_CORE0_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2S0_ALLOW_V << TEE_REG_CORE0_MM_HP_I2S0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_CORE0_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2S1_ALLOW_V << TEE_REG_CORE0_MM_HP_I2S1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_CORE0_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW_M  (TEE_REG_CORE0_MM_HP_I2S2_ALLOW_V << TEE_REG_CORE0_MM_HP_I2S2_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_CORE0_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW_M  (TEE_REG_CORE0_MM_HP_PCNT_ALLOW_V << TEE_REG_CORE0_MM_HP_PCNT_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_CORE0_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_MM_HP_UART0_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART0_ALLOW_V << TEE_REG_CORE0_MM_HP_UART0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART0_ALLOW_S  10
+/** TEE_REG_CORE0_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_MM_HP_UART1_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART1_ALLOW_V << TEE_REG_CORE0_MM_HP_UART1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART1_ALLOW_S  11
+/** TEE_REG_CORE0_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_CORE0_MM_HP_UART2_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART2_ALLOW_V << TEE_REG_CORE0_MM_HP_UART2_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART2_ALLOW_S  12
+/** TEE_REG_CORE0_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_CORE0_MM_HP_UART3_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART3_ALLOW_V << TEE_REG_CORE0_MM_HP_UART3_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART3_ALLOW_S  13
+/** TEE_REG_CORE0_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_CORE0_MM_HP_UART4_ALLOW_M  (TEE_REG_CORE0_MM_HP_UART4_ALLOW_V << TEE_REG_CORE0_MM_HP_UART4_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UART4_ALLOW_S  14
+/** TEE_REG_CORE0_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_M  (TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_V << TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_M  (TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_M  (TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_M  (TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_CORE0_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW_M  (TEE_REG_CORE0_MM_HP_LEDC_ALLOW_V << TEE_REG_CORE0_MM_HP_LEDC_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_CORE0_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_CORE0_MM_HP_ETM_ALLOW_M  (TEE_REG_CORE0_MM_HP_ETM_ALLOW_V << TEE_REG_CORE0_MM_HP_ETM_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_ETM_ALLOW_S  21
+/** TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_M  (TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_CORE0_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_M  (TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_V << TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_CORE0_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_M  (TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_V << TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_CORE0_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_M  (TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_V << TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_M  (TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_M  (TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_M  (TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_CORE0_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_CORE0_MM_HP_ADC_ALLOW_M  (TEE_REG_CORE0_MM_HP_ADC_ALLOW_V << TEE_REG_CORE0_MM_HP_ADC_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_ADC_ALLOW_S  30
+/** TEE_REG_CORE0_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW_M  (TEE_REG_CORE0_MM_HP_UHCI_ALLOW_V << TEE_REG_CORE0_MM_HP_UHCI_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_UHCI_ALLOW_S  31
+
+/** TEE_CORE0_MM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_CORE0_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x14)
+/** TEE_REG_CORE0_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW_M  (TEE_REG_CORE0_MM_HP_GPIO_ALLOW_V << TEE_REG_CORE0_MM_HP_GPIO_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_CORE0_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_M  (TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_V << TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_M  (TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_M  (TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_CORE0_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_M  (TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_V << TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_MM_HP_CLKRST_ALLOW_S  4
+
+/** TEE_CORE0_UM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_CORE0_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x18)
+/** TEE_REG_CORE0_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_UM_PSRAM_ALLOW_M  (TEE_REG_CORE0_UM_PSRAM_ALLOW_V << TEE_REG_CORE0_UM_PSRAM_ALLOW_S)
+#define TEE_REG_CORE0_UM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_PSRAM_ALLOW_S  0
+/** TEE_REG_CORE0_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_UM_FLASH_ALLOW_M  (TEE_REG_CORE0_UM_FLASH_ALLOW_V << TEE_REG_CORE0_UM_FLASH_ALLOW_S)
+#define TEE_REG_CORE0_UM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_FLASH_ALLOW_S  1
+/** TEE_REG_CORE0_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_UM_L2MEM_ALLOW_M  (TEE_REG_CORE0_UM_L2MEM_ALLOW_V << TEE_REG_CORE0_UM_L2MEM_ALLOW_S)
+#define TEE_REG_CORE0_UM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_L2MEM_ALLOW_S  2
+/** TEE_REG_CORE0_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_UM_L2ROM_ALLOW_M  (TEE_REG_CORE0_UM_L2ROM_ALLOW_V << TEE_REG_CORE0_UM_L2ROM_ALLOW_S)
+#define TEE_REG_CORE0_UM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_L2ROM_ALLOW_S  3
+/** TEE_REG_CORE0_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_UM_TRACE0_ALLOW_M  (TEE_REG_CORE0_UM_TRACE0_ALLOW_V << TEE_REG_CORE0_UM_TRACE0_ALLOW_S)
+#define TEE_REG_CORE0_UM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_TRACE0_ALLOW_S  6
+/** TEE_REG_CORE0_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_UM_TRACE1_ALLOW_M  (TEE_REG_CORE0_UM_TRACE1_ALLOW_V << TEE_REG_CORE0_UM_TRACE1_ALLOW_S)
+#define TEE_REG_CORE0_UM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_TRACE1_ALLOW_S  7
+/** TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_M  (TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_CORE0_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_M  (TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_V << TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_CORE0_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_UM_TCM_MON_ALLOW_M  (TEE_REG_CORE0_UM_TCM_MON_ALLOW_V << TEE_REG_CORE0_UM_TCM_MON_ALLOW_S)
+#define TEE_REG_CORE0_UM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_TCM_MON_ALLOW_S  10
+/** TEE_REG_CORE0_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_UM_CACHE_ALLOW_M  (TEE_REG_CORE0_UM_CACHE_ALLOW_V << TEE_REG_CORE0_UM_CACHE_ALLOW_S)
+#define TEE_REG_CORE0_UM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_CACHE_ALLOW_S  11
+
+/** TEE_CORE0_UM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_CORE0_UM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x1c)
+/** TEE_REG_CORE0_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_M  (TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_V << TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_M  (TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_CORE0_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW_M  (TEE_REG_CORE0_UM_HP_GDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_GDMA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_CORE0_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_M  (TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_M  (TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_V << TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_CORE0_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW_M  (TEE_REG_CORE0_UM_HP_JPEG_ALLOW_V << TEE_REG_CORE0_UM_HP_JPEG_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_CORE0_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_UM_HP_PPA_ALLOW_M  (TEE_REG_CORE0_UM_HP_PPA_ALLOW_V << TEE_REG_CORE0_UM_HP_PPA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PPA_ALLOW_S  8
+/** TEE_REG_CORE0_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_M  (TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_V << TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_CORE0_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW_M  (TEE_REG_CORE0_UM_HP_FLASH_ALLOW_V << TEE_REG_CORE0_UM_HP_FLASH_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_CORE0_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_M  (TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_V << TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_M  (TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_CORE0_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW_M  (TEE_REG_CORE0_UM_HP_GMAC_ALLOW_V << TEE_REG_CORE0_UM_HP_GMAC_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_M  (TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_CORE0_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_CORE0_UM_HP_PVT_ALLOW_M  (TEE_REG_CORE0_UM_HP_PVT_ALLOW_V << TEE_REG_CORE0_UM_HP_PVT_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PVT_ALLOW_S  17
+/** TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_M  (TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_M  (TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_CORE0_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_CORE0_UM_HP_ISP_ALLOW_M  (TEE_REG_CORE0_UM_HP_ISP_ALLOW_V << TEE_REG_CORE0_UM_HP_ISP_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_ISP_ALLOW_S  20
+/** TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_M  (TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_CORE0_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_CORE0_UM_HP_RMT_ALLOW_M  (TEE_REG_CORE0_UM_HP_RMT_ALLOW_V << TEE_REG_CORE0_UM_HP_RMT_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_RMT_ALLOW_S  22
+/** TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_M  (TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_CORE0_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW_M  (TEE_REG_CORE0_UM_DMA_PMS_ALLOW_V << TEE_REG_CORE0_UM_DMA_PMS_ALLOW_S)
+#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_M  (TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_CORE0_UM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_CORE0_UM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x20)
+/** TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_M  (TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_M  (TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_CORE0_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2C0_ALLOW_V << TEE_REG_CORE0_UM_HP_I2C0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_CORE0_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2C1_ALLOW_V << TEE_REG_CORE0_UM_HP_I2C1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_CORE0_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2S0_ALLOW_V << TEE_REG_CORE0_UM_HP_I2S0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_CORE0_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2S1_ALLOW_V << TEE_REG_CORE0_UM_HP_I2S1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_CORE0_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW_M  (TEE_REG_CORE0_UM_HP_I2S2_ALLOW_V << TEE_REG_CORE0_UM_HP_I2S2_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_CORE0_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW_M  (TEE_REG_CORE0_UM_HP_PCNT_ALLOW_V << TEE_REG_CORE0_UM_HP_PCNT_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_CORE0_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_CORE0_UM_HP_UART0_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART0_ALLOW_V << TEE_REG_CORE0_UM_HP_UART0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART0_ALLOW_S  10
+/** TEE_REG_CORE0_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_CORE0_UM_HP_UART1_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART1_ALLOW_V << TEE_REG_CORE0_UM_HP_UART1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART1_ALLOW_S  11
+/** TEE_REG_CORE0_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_CORE0_UM_HP_UART2_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART2_ALLOW_V << TEE_REG_CORE0_UM_HP_UART2_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART2_ALLOW_S  12
+/** TEE_REG_CORE0_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_CORE0_UM_HP_UART3_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART3_ALLOW_V << TEE_REG_CORE0_UM_HP_UART3_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART3_ALLOW_S  13
+/** TEE_REG_CORE0_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_CORE0_UM_HP_UART4_ALLOW_M  (TEE_REG_CORE0_UM_HP_UART4_ALLOW_V << TEE_REG_CORE0_UM_HP_UART4_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UART4_ALLOW_S  14
+/** TEE_REG_CORE0_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_M  (TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_V << TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_M  (TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_M  (TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_M  (TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_CORE0_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW_M  (TEE_REG_CORE0_UM_HP_LEDC_ALLOW_V << TEE_REG_CORE0_UM_HP_LEDC_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_CORE0_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_CORE0_UM_HP_ETM_ALLOW_M  (TEE_REG_CORE0_UM_HP_ETM_ALLOW_V << TEE_REG_CORE0_UM_HP_ETM_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_ETM_ALLOW_S  21
+/** TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_M  (TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_CORE0_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_M  (TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_V << TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_CORE0_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_M  (TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_V << TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_CORE0_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_M  (TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_V << TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_M  (TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_M  (TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_M  (TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_CORE0_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_CORE0_UM_HP_ADC_ALLOW_M  (TEE_REG_CORE0_UM_HP_ADC_ALLOW_V << TEE_REG_CORE0_UM_HP_ADC_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_ADC_ALLOW_S  30
+/** TEE_REG_CORE0_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW_M  (TEE_REG_CORE0_UM_HP_UHCI_ALLOW_V << TEE_REG_CORE0_UM_HP_UHCI_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_UHCI_ALLOW_S  31
+
+/** TEE_CORE0_UM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_CORE0_UM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x24)
+/** TEE_REG_CORE0_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW_M  (TEE_REG_CORE0_UM_HP_GPIO_ALLOW_V << TEE_REG_CORE0_UM_HP_GPIO_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_CORE0_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_M  (TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_V << TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_M  (TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_M  (TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_CORE0_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_M  (TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_V << TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE0_UM_HP_CLKRST_ALLOW_S  4
+
+/** TEE_CORE1_MM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_CORE1_MM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x28)
+/** TEE_REG_CORE1_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_MM_PSRAM_ALLOW_M  (TEE_REG_CORE1_MM_PSRAM_ALLOW_V << TEE_REG_CORE1_MM_PSRAM_ALLOW_S)
+#define TEE_REG_CORE1_MM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_PSRAM_ALLOW_S  0
+/** TEE_REG_CORE1_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_MM_FLASH_ALLOW_M  (TEE_REG_CORE1_MM_FLASH_ALLOW_V << TEE_REG_CORE1_MM_FLASH_ALLOW_S)
+#define TEE_REG_CORE1_MM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_FLASH_ALLOW_S  1
+/** TEE_REG_CORE1_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_MM_L2MEM_ALLOW_M  (TEE_REG_CORE1_MM_L2MEM_ALLOW_V << TEE_REG_CORE1_MM_L2MEM_ALLOW_S)
+#define TEE_REG_CORE1_MM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_L2MEM_ALLOW_S  2
+/** TEE_REG_CORE1_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_MM_L2ROM_ALLOW_M  (TEE_REG_CORE1_MM_L2ROM_ALLOW_V << TEE_REG_CORE1_MM_L2ROM_ALLOW_S)
+#define TEE_REG_CORE1_MM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_L2ROM_ALLOW_S  3
+/** TEE_REG_CORE1_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_MM_TRACE0_ALLOW_M  (TEE_REG_CORE1_MM_TRACE0_ALLOW_V << TEE_REG_CORE1_MM_TRACE0_ALLOW_S)
+#define TEE_REG_CORE1_MM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_TRACE0_ALLOW_S  6
+/** TEE_REG_CORE1_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_MM_TRACE1_ALLOW_M  (TEE_REG_CORE1_MM_TRACE1_ALLOW_V << TEE_REG_CORE1_MM_TRACE1_ALLOW_S)
+#define TEE_REG_CORE1_MM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_TRACE1_ALLOW_S  7
+/** TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_M  (TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_CORE1_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_M  (TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_V << TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_CORE1_MM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_MM_TCM_MON_ALLOW_M  (TEE_REG_CORE1_MM_TCM_MON_ALLOW_V << TEE_REG_CORE1_MM_TCM_MON_ALLOW_S)
+#define TEE_REG_CORE1_MM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_TCM_MON_ALLOW_S  10
+/** TEE_REG_CORE1_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_MM_CACHE_ALLOW_M  (TEE_REG_CORE1_MM_CACHE_ALLOW_V << TEE_REG_CORE1_MM_CACHE_ALLOW_S)
+#define TEE_REG_CORE1_MM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_CACHE_ALLOW_S  11
+
+/** TEE_CORE1_MM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_CORE1_MM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x2c)
+/** TEE_REG_CORE1_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_M  (TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_V << TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_M  (TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_CORE1_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW_M  (TEE_REG_CORE1_MM_HP_GDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_GDMA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_CORE1_MM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_M  (TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_M  (TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_V << TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_CORE1_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW_M  (TEE_REG_CORE1_MM_HP_JPEG_ALLOW_V << TEE_REG_CORE1_MM_HP_JPEG_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_CORE1_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_MM_HP_PPA_ALLOW_M  (TEE_REG_CORE1_MM_HP_PPA_ALLOW_V << TEE_REG_CORE1_MM_HP_PPA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PPA_ALLOW_S  8
+/** TEE_REG_CORE1_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_M  (TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_V << TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_CORE1_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW_M  (TEE_REG_CORE1_MM_HP_FLASH_ALLOW_V << TEE_REG_CORE1_MM_HP_FLASH_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_CORE1_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_M  (TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_V << TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_M  (TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_CORE1_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW_M  (TEE_REG_CORE1_MM_HP_GMAC_ALLOW_V << TEE_REG_CORE1_MM_HP_GMAC_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_M  (TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_CORE1_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_CORE1_MM_HP_PVT_ALLOW_M  (TEE_REG_CORE1_MM_HP_PVT_ALLOW_V << TEE_REG_CORE1_MM_HP_PVT_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PVT_ALLOW_S  17
+/** TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_M  (TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_M  (TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_CORE1_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_CORE1_MM_HP_ISP_ALLOW_M  (TEE_REG_CORE1_MM_HP_ISP_ALLOW_V << TEE_REG_CORE1_MM_HP_ISP_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_ISP_ALLOW_S  20
+/** TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_M  (TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_CORE1_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_CORE1_MM_HP_RMT_ALLOW_M  (TEE_REG_CORE1_MM_HP_RMT_ALLOW_V << TEE_REG_CORE1_MM_HP_RMT_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_RMT_ALLOW_S  22
+/** TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_M  (TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_CORE1_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW_M  (TEE_REG_CORE1_MM_DMA_PMS_ALLOW_V << TEE_REG_CORE1_MM_DMA_PMS_ALLOW_S)
+#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_M  (TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_CORE1_MM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_CORE1_MM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x30)
+/** TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_M  (TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_M  (TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_CORE1_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2C0_ALLOW_V << TEE_REG_CORE1_MM_HP_I2C0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_CORE1_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2C1_ALLOW_V << TEE_REG_CORE1_MM_HP_I2C1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_CORE1_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2S0_ALLOW_V << TEE_REG_CORE1_MM_HP_I2S0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_CORE1_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2S1_ALLOW_V << TEE_REG_CORE1_MM_HP_I2S1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_CORE1_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW_M  (TEE_REG_CORE1_MM_HP_I2S2_ALLOW_V << TEE_REG_CORE1_MM_HP_I2S2_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_CORE1_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW_M  (TEE_REG_CORE1_MM_HP_PCNT_ALLOW_V << TEE_REG_CORE1_MM_HP_PCNT_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_CORE1_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_MM_HP_UART0_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART0_ALLOW_V << TEE_REG_CORE1_MM_HP_UART0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART0_ALLOW_S  10
+/** TEE_REG_CORE1_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_MM_HP_UART1_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART1_ALLOW_V << TEE_REG_CORE1_MM_HP_UART1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART1_ALLOW_S  11
+/** TEE_REG_CORE1_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_CORE1_MM_HP_UART2_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART2_ALLOW_V << TEE_REG_CORE1_MM_HP_UART2_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART2_ALLOW_S  12
+/** TEE_REG_CORE1_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_CORE1_MM_HP_UART3_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART3_ALLOW_V << TEE_REG_CORE1_MM_HP_UART3_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART3_ALLOW_S  13
+/** TEE_REG_CORE1_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_CORE1_MM_HP_UART4_ALLOW_M  (TEE_REG_CORE1_MM_HP_UART4_ALLOW_V << TEE_REG_CORE1_MM_HP_UART4_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UART4_ALLOW_S  14
+/** TEE_REG_CORE1_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_M  (TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_V << TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_M  (TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_M  (TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_M  (TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_CORE1_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW_M  (TEE_REG_CORE1_MM_HP_LEDC_ALLOW_V << TEE_REG_CORE1_MM_HP_LEDC_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_CORE1_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_CORE1_MM_HP_ETM_ALLOW_M  (TEE_REG_CORE1_MM_HP_ETM_ALLOW_V << TEE_REG_CORE1_MM_HP_ETM_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_ETM_ALLOW_S  21
+/** TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_M  (TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_CORE1_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_M  (TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_V << TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_CORE1_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_M  (TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_V << TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_CORE1_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_M  (TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_V << TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_M  (TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_M  (TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_M  (TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_CORE1_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_CORE1_MM_HP_ADC_ALLOW_M  (TEE_REG_CORE1_MM_HP_ADC_ALLOW_V << TEE_REG_CORE1_MM_HP_ADC_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_ADC_ALLOW_S  30
+/** TEE_REG_CORE1_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW_M  (TEE_REG_CORE1_MM_HP_UHCI_ALLOW_V << TEE_REG_CORE1_MM_HP_UHCI_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_UHCI_ALLOW_S  31
+
+/** TEE_CORE1_MM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_CORE1_MM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x34)
+/** TEE_REG_CORE1_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW_M  (TEE_REG_CORE1_MM_HP_GPIO_ALLOW_V << TEE_REG_CORE1_MM_HP_GPIO_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_CORE1_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_M  (TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_V << TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_M  (TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_M  (TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_CORE1_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_M  (TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_V << TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_MM_HP_CLKRST_ALLOW_S  4
+
+/** TEE_CORE1_UM_PMS_REG0_REG register
+ *  NA
+ */
+#define TEE_CORE1_UM_PMS_REG0_REG (DR_REG_TEE_BASE + 0x38)
+/** TEE_REG_CORE1_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_PSRAM_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_UM_PSRAM_ALLOW_M  (TEE_REG_CORE1_UM_PSRAM_ALLOW_V << TEE_REG_CORE1_UM_PSRAM_ALLOW_S)
+#define TEE_REG_CORE1_UM_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_PSRAM_ALLOW_S  0
+/** TEE_REG_CORE1_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_FLASH_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_UM_FLASH_ALLOW_M  (TEE_REG_CORE1_UM_FLASH_ALLOW_V << TEE_REG_CORE1_UM_FLASH_ALLOW_S)
+#define TEE_REG_CORE1_UM_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_FLASH_ALLOW_S  1
+/** TEE_REG_CORE1_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_L2MEM_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_UM_L2MEM_ALLOW_M  (TEE_REG_CORE1_UM_L2MEM_ALLOW_V << TEE_REG_CORE1_UM_L2MEM_ALLOW_S)
+#define TEE_REG_CORE1_UM_L2MEM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_L2MEM_ALLOW_S  2
+/** TEE_REG_CORE1_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_L2ROM_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_UM_L2ROM_ALLOW_M  (TEE_REG_CORE1_UM_L2ROM_ALLOW_V << TEE_REG_CORE1_UM_L2ROM_ALLOW_S)
+#define TEE_REG_CORE1_UM_L2ROM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_L2ROM_ALLOW_S  3
+/** TEE_REG_CORE1_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_TRACE0_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_UM_TRACE0_ALLOW_M  (TEE_REG_CORE1_UM_TRACE0_ALLOW_V << TEE_REG_CORE1_UM_TRACE0_ALLOW_S)
+#define TEE_REG_CORE1_UM_TRACE0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_TRACE0_ALLOW_S  6
+/** TEE_REG_CORE1_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_TRACE1_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_UM_TRACE1_ALLOW_M  (TEE_REG_CORE1_UM_TRACE1_ALLOW_V << TEE_REG_CORE1_UM_TRACE1_ALLOW_S)
+#define TEE_REG_CORE1_UM_TRACE1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_TRACE1_ALLOW_S  7
+/** TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_M  (TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_V << TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_S)
+#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_CPU_BUS_MON_ALLOW_S  8
+/** TEE_REG_CORE1_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_M  (TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_V << TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_S)
+#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_L2MEM_MON_ALLOW_S  9
+/** TEE_REG_CORE1_UM_TCM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_TCM_MON_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_UM_TCM_MON_ALLOW_M  (TEE_REG_CORE1_UM_TCM_MON_ALLOW_V << TEE_REG_CORE1_UM_TCM_MON_ALLOW_S)
+#define TEE_REG_CORE1_UM_TCM_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_TCM_MON_ALLOW_S  10
+/** TEE_REG_CORE1_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_CACHE_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_UM_CACHE_ALLOW_M  (TEE_REG_CORE1_UM_CACHE_ALLOW_V << TEE_REG_CORE1_UM_CACHE_ALLOW_S)
+#define TEE_REG_CORE1_UM_CACHE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_CACHE_ALLOW_S  11
+
+/** TEE_CORE1_UM_PMS_REG1_REG register
+ *  NA
+ */
+#define TEE_CORE1_UM_PMS_REG1_REG (DR_REG_TEE_BASE + 0x3c)
+/** TEE_REG_CORE1_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_M  (TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_V << TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USBOTG_ALLOW_S  0
+/** TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_M  (TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_V << TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USBOTG11_ALLOW_S  1
+/** TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_M  (TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V << TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** TEE_REG_CORE1_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW_M  (TEE_REG_CORE1_UM_HP_GDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_GDMA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GDMA_ALLOW_S  3
+/** TEE_REG_CORE1_UM_HP_REGDMA_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_M  (TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_REGDMA_ALLOW_S  4
+/** TEE_REG_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW    (BIT(5))
+#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_M  (TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_V << TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_SDMMC_ALLOW_S  5
+/** TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_M  (TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_AHB_PDMA_ALLOW_S  6
+/** TEE_REG_CORE1_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW_M  (TEE_REG_CORE1_UM_HP_JPEG_ALLOW_V << TEE_REG_CORE1_UM_HP_JPEG_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_JPEG_ALLOW_S  7
+/** TEE_REG_CORE1_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PPA_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_UM_HP_PPA_ALLOW_M  (TEE_REG_CORE1_UM_HP_PPA_ALLOW_V << TEE_REG_CORE1_UM_HP_PPA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PPA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PPA_ALLOW_S  8
+/** TEE_REG_CORE1_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_M  (TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_V << TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_DMA2D_ALLOW_S  9
+/** TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_M  (TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_V << TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_KEY_MANAGER_ALLOW_S  10
+/** TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_M  (TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_V << TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_AXI_PDMA_ALLOW_S  11
+/** TEE_REG_CORE1_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW    (BIT(12))
+#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW_M  (TEE_REG_CORE1_UM_HP_FLASH_ALLOW_V << TEE_REG_CORE1_UM_HP_FLASH_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_FLASH_ALLOW_S  12
+/** TEE_REG_CORE1_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW    (BIT(13))
+#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_M  (TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_V << TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PSRAM_ALLOW_S  13
+/** TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW    (BIT(14))
+#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_M  (TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_V << TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_CRYPTO_ALLOW_S  14
+/** TEE_REG_CORE1_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW    (BIT(15))
+#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW_M  (TEE_REG_CORE1_UM_HP_GMAC_ALLOW_V << TEE_REG_CORE1_UM_HP_GMAC_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GMAC_ALLOW_S  15
+/** TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW    (BIT(16))
+#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_M  (TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_V << TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USB_PHY_ALLOW_S  16
+/** TEE_REG_CORE1_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PVT_ALLOW    (BIT(17))
+#define TEE_REG_CORE1_UM_HP_PVT_ALLOW_M  (TEE_REG_CORE1_UM_HP_PVT_ALLOW_V << TEE_REG_CORE1_UM_HP_PVT_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PVT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PVT_ALLOW_S  17
+/** TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_M  (TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_V << TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_CSI_HOST_ALLOW_S  18
+/** TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_M  (TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_V << TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_DSI_HOST_ALLOW_S  19
+/** TEE_REG_CORE1_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_ISP_ALLOW    (BIT(20))
+#define TEE_REG_CORE1_UM_HP_ISP_ALLOW_M  (TEE_REG_CORE1_UM_HP_ISP_ALLOW_V << TEE_REG_CORE1_UM_HP_ISP_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_ISP_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_ISP_ALLOW_S  20
+/** TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW    (BIT(21))
+#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_M  (TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_V << TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_H264_CORE_ALLOW_S  21
+/** TEE_REG_CORE1_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_RMT_ALLOW    (BIT(22))
+#define TEE_REG_CORE1_UM_HP_RMT_ALLOW_M  (TEE_REG_CORE1_UM_HP_RMT_ALLOW_V << TEE_REG_CORE1_UM_HP_RMT_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_RMT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_RMT_ALLOW_S  22
+/** TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_M  (TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_V << TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_BITSRAMBLER_ALLOW_S  23
+/** TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_M  (TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_V << TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_AXI_ICM_ALLOW_S  24
+/** TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PERI_PMS_ALLOW_S  25
+/** TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_M  (TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V << TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S)
+#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S  26
+/** TEE_REG_CORE1_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW    (BIT(27))
+#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW_M  (TEE_REG_CORE1_UM_DMA_PMS_ALLOW_V << TEE_REG_CORE1_UM_DMA_PMS_ALLOW_S)
+#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_DMA_PMS_ALLOW_S  27
+/** TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_M  (TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_V << TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_H264_DMA2D_ALLOW_S  28
+/** TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW : R/W; bitpos: [29]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW    (BIT(29))
+#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_M  (TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_V << TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_S)
+#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_AXI_PERF_MON_ALLOW_S  29
+
+/** TEE_CORE1_UM_PMS_REG2_REG register
+ *  NA
+ */
+#define TEE_CORE1_UM_PMS_REG2_REG (DR_REG_TEE_BASE + 0x40)
+/** TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_M  (TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_V << TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_MCPWM0_ALLOW_S  0
+/** TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_M  (TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_V << TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_MCPWM1_ALLOW_S  1
+/** TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_M  (TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V << TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S  2
+/** TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_M  (TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V << TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S  3
+/** TEE_REG_CORE1_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2C0_ALLOW_V << TEE_REG_CORE1_UM_HP_I2C0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2C0_ALLOW_S  4
+/** TEE_REG_CORE1_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW    (BIT(5))
+#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2C1_ALLOW_V << TEE_REG_CORE1_UM_HP_I2C1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2C1_ALLOW_S  5
+/** TEE_REG_CORE1_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW    (BIT(6))
+#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2S0_ALLOW_V << TEE_REG_CORE1_UM_HP_I2S0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2S0_ALLOW_S  6
+/** TEE_REG_CORE1_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW    (BIT(7))
+#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2S1_ALLOW_V << TEE_REG_CORE1_UM_HP_I2S1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2S1_ALLOW_S  7
+/** TEE_REG_CORE1_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW    (BIT(8))
+#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW_M  (TEE_REG_CORE1_UM_HP_I2S2_ALLOW_V << TEE_REG_CORE1_UM_HP_I2S2_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I2S2_ALLOW_S  8
+/** TEE_REG_CORE1_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW    (BIT(9))
+#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW_M  (TEE_REG_CORE1_UM_HP_PCNT_ALLOW_V << TEE_REG_CORE1_UM_HP_PCNT_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PCNT_ALLOW_S  9
+/** TEE_REG_CORE1_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART0_ALLOW    (BIT(10))
+#define TEE_REG_CORE1_UM_HP_UART0_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART0_ALLOW_V << TEE_REG_CORE1_UM_HP_UART0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART0_ALLOW_S  10
+/** TEE_REG_CORE1_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART1_ALLOW    (BIT(11))
+#define TEE_REG_CORE1_UM_HP_UART1_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART1_ALLOW_V << TEE_REG_CORE1_UM_HP_UART1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART1_ALLOW_S  11
+/** TEE_REG_CORE1_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART2_ALLOW    (BIT(12))
+#define TEE_REG_CORE1_UM_HP_UART2_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART2_ALLOW_V << TEE_REG_CORE1_UM_HP_UART2_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART2_ALLOW_S  12
+/** TEE_REG_CORE1_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART3_ALLOW    (BIT(13))
+#define TEE_REG_CORE1_UM_HP_UART3_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART3_ALLOW_V << TEE_REG_CORE1_UM_HP_UART3_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART3_ALLOW_S  13
+/** TEE_REG_CORE1_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UART4_ALLOW    (BIT(14))
+#define TEE_REG_CORE1_UM_HP_UART4_ALLOW_M  (TEE_REG_CORE1_UM_HP_UART4_ALLOW_V << TEE_REG_CORE1_UM_HP_UART4_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UART4_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UART4_ALLOW_S  14
+/** TEE_REG_CORE1_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW    (BIT(15))
+#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_M  (TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_V << TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_PARLIO_ALLOW_S  15
+/** TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW    (BIT(16))
+#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_M  (TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_V << TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GPSPI2_ALLOW_S  16
+/** TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW    (BIT(17))
+#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_M  (TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_V << TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GPSPI3_ALLOW_S  17
+/** TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_M  (TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_V << TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_USBDEVICE_ALLOW_S  18
+/** TEE_REG_CORE1_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW    (BIT(19))
+#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW_M  (TEE_REG_CORE1_UM_HP_LEDC_ALLOW_V << TEE_REG_CORE1_UM_HP_LEDC_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_LEDC_ALLOW_S  19
+/** TEE_REG_CORE1_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_ETM_ALLOW    (BIT(21))
+#define TEE_REG_CORE1_UM_HP_ETM_ALLOW_M  (TEE_REG_CORE1_UM_HP_ETM_ALLOW_V << TEE_REG_CORE1_UM_HP_ETM_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_ETM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_ETM_ALLOW_S  21
+/** TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW    (BIT(22))
+#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_M  (TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_V << TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_INTRMTX_ALLOW_S  22
+/** TEE_REG_CORE1_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW    (BIT(23))
+#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_M  (TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_V << TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TWAI0_ALLOW_S  23
+/** TEE_REG_CORE1_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW    (BIT(24))
+#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_M  (TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_V << TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TWAI1_ALLOW_S  24
+/** TEE_REG_CORE1_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW    (BIT(25))
+#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_M  (TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_V << TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_TWAI2_ALLOW_S  25
+/** TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW    (BIT(26))
+#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_M  (TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_V << TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I3C_MST_ALLOW_S  26
+/** TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_M  (TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_V << TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_I3C_SLV_ALLOW_S  27
+/** TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW    (BIT(28))
+#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_M  (TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_V << TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_LCDCAM_ALLOW_S  28
+/** TEE_REG_CORE1_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_ADC_ALLOW    (BIT(30))
+#define TEE_REG_CORE1_UM_HP_ADC_ALLOW_M  (TEE_REG_CORE1_UM_HP_ADC_ALLOW_V << TEE_REG_CORE1_UM_HP_ADC_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_ADC_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_ADC_ALLOW_S  30
+/** TEE_REG_CORE1_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW    (BIT(31))
+#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW_M  (TEE_REG_CORE1_UM_HP_UHCI_ALLOW_V << TEE_REG_CORE1_UM_HP_UHCI_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_UHCI_ALLOW_S  31
+
+/** TEE_CORE1_UM_PMS_REG3_REG register
+ *  NA
+ */
+#define TEE_CORE1_UM_PMS_REG3_REG (DR_REG_TEE_BASE + 0x44)
+/** TEE_REG_CORE1_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW    (BIT(0))
+#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW_M  (TEE_REG_CORE1_UM_HP_GPIO_ALLOW_V << TEE_REG_CORE1_UM_HP_GPIO_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_GPIO_ALLOW_S  0
+/** TEE_REG_CORE1_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW    (BIT(1))
+#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_M  (TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_V << TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_IOMUX_ALLOW_S  1
+/** TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_M  (TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_V << TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_SYSTIMER_ALLOW_S  2
+/** TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW    (BIT(3))
+#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_M  (TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_V << TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_SYS_REG_ALLOW_S  3
+/** TEE_REG_CORE1_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW    (BIT(4))
+#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_M  (TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_V << TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_S)
+#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_V  0x00000001U
+#define TEE_REG_CORE1_UM_HP_CLKRST_ALLOW_S  4
+
+/** TEE_REGDMA_PERI_PMS_REG register
+ *  NA
+ */
+#define TEE_REGDMA_PERI_PMS_REG (DR_REG_TEE_BASE + 0x48)
+/** TEE_REG_REGDMA_PERI_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define TEE_REG_REGDMA_PERI_ALLOW    (BIT(0))
+#define TEE_REG_REGDMA_PERI_ALLOW_M  (TEE_REG_REGDMA_PERI_ALLOW_V << TEE_REG_REGDMA_PERI_ALLOW_S)
+#define TEE_REG_REGDMA_PERI_ALLOW_V  0x00000001U
+#define TEE_REG_REGDMA_PERI_ALLOW_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_reg.h
new file mode 100644
index 0000000000..96d629ea2f
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_reg.h
@@ -0,0 +1,2840 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PMS_HP_PERI_PMS_DATE_REG register
+ *  Version control register
+ */
+#define PMS_HP_PERI_PMS_DATE_REG (DR_REG_HP_PERI_PMS_BASE + 0x0)
+/** PMS_HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
+ *  Version control register.
+ */
+#define PMS_HP_PERI_PMS_DATE    0xFFFFFFFFU
+#define PMS_HP_PERI_PMS_DATE_M  (PMS_HP_PERI_PMS_DATE_V << PMS_HP_PERI_PMS_DATE_S)
+#define PMS_HP_PERI_PMS_DATE_V  0xFFFFFFFFU
+#define PMS_HP_PERI_PMS_DATE_S  0
+
+/** PMS_HP_PERI_PMS_CLK_EN_REG register
+ *  Clock gating register
+ */
+#define PMS_HP_PERI_PMS_CLK_EN_REG (DR_REG_HP_PERI_PMS_BASE + 0x4)
+/** PMS_HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: Enable automatic clock gating
+ *  1: Keep the clock always on
+ */
+#define PMS_HP_PERI_PMS_CLK_EN    (BIT(0))
+#define PMS_HP_PERI_PMS_CLK_EN_M  (PMS_HP_PERI_PMS_CLK_EN_V << PMS_HP_PERI_PMS_CLK_EN_S)
+#define PMS_HP_PERI_PMS_CLK_EN_V  0x00000001U
+#define PMS_HP_PERI_PMS_CLK_EN_S  0
+
+/** PMS_CORE0_MM_HP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU0 in machine mode
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x8)
+/** PMS_CORE0_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_PSRAM_ALLOW    (BIT(0))
+#define PMS_CORE0_MM_PSRAM_ALLOW_M  (PMS_CORE0_MM_PSRAM_ALLOW_V << PMS_CORE0_MM_PSRAM_ALLOW_S)
+#define PMS_CORE0_MM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_PSRAM_ALLOW_S  0
+/** PMS_CORE0_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access external flash
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_FLASH_ALLOW    (BIT(1))
+#define PMS_CORE0_MM_FLASH_ALLOW_M  (PMS_CORE0_MM_FLASH_ALLOW_V << PMS_CORE0_MM_FLASH_ALLOW_S)
+#define PMS_CORE0_MM_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_FLASH_ALLOW_S  1
+/** PMS_CORE0_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP L2MEM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_L2MEM_ALLOW    (BIT(2))
+#define PMS_CORE0_MM_L2MEM_ALLOW_M  (PMS_CORE0_MM_L2MEM_ALLOW_V << PMS_CORE0_MM_L2MEM_ALLOW_S)
+#define PMS_CORE0_MM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_L2MEM_ALLOW_S  2
+/** PMS_CORE0_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP ROM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_L2ROM_ALLOW    (BIT(3))
+#define PMS_CORE0_MM_L2ROM_ALLOW_M  (PMS_CORE0_MM_L2ROM_ALLOW_V << PMS_CORE0_MM_L2ROM_ALLOW_S)
+#define PMS_CORE0_MM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_L2ROM_ALLOW_S  3
+/** PMS_CORE0_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_TRACE0_ALLOW    (BIT(6))
+#define PMS_CORE0_MM_TRACE0_ALLOW_M  (PMS_CORE0_MM_TRACE0_ALLOW_V << PMS_CORE0_MM_TRACE0_ALLOW_S)
+#define PMS_CORE0_MM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_TRACE0_ALLOW_S  6
+/** PMS_CORE0_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_TRACE1_ALLOW    (BIT(7))
+#define PMS_CORE0_MM_TRACE1_ALLOW_M  (PMS_CORE0_MM_TRACE1_ALLOW_V << PMS_CORE0_MM_TRACE1_ALLOW_S)
+#define PMS_CORE0_MM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_TRACE1_ALLOW_S  7
+/** PMS_CORE0_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access CPU bus
+ *  monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_CORE0_MM_CPU_BUS_MON_ALLOW_M  (PMS_CORE0_MM_CPU_BUS_MON_ALLOW_V << PMS_CORE0_MM_CPU_BUS_MON_ALLOW_S)
+#define PMS_CORE0_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_CORE0_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access L2MEM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_CORE0_MM_L2MEM_MON_ALLOW_M  (PMS_CORE0_MM_L2MEM_MON_ALLOW_V << PMS_CORE0_MM_L2MEM_MON_ALLOW_S)
+#define PMS_CORE0_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_L2MEM_MON_ALLOW_S  9
+/** PMS_CORE0_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_CORE0_MM_SPM_MON_ALLOW_M  (PMS_CORE0_MM_SPM_MON_ALLOW_V << PMS_CORE0_MM_SPM_MON_ALLOW_S)
+#define PMS_CORE0_MM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_SPM_MON_ALLOW_S  10
+/** PMS_CORE0_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_CACHE_ALLOW    (BIT(11))
+#define PMS_CORE0_MM_CACHE_ALLOW_M  (PMS_CORE0_MM_CACHE_ALLOW_V << PMS_CORE0_MM_CACHE_ALLOW_S)
+#define PMS_CORE0_MM_CACHE_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_CACHE_ALLOW_S  11
+
+/** PMS_CORE0_MM_HP_PERI_PMS_REG1_REG register
+ *  Permission control register1 for HP CPU0 in machine mode
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0xc)
+/** PMS_CORE0_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP high-speed
+ *  USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_CORE0_MM_HP_USBOTG_ALLOW_M  (PMS_CORE0_MM_HP_USBOTG_ALLOW_V << PMS_CORE0_MM_HP_USBOTG_ALLOW_S)
+#define PMS_CORE0_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USBOTG_ALLOW_S  0
+/** PMS_CORE0_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP full-speed
+ *  USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_CORE0_MM_HP_USBOTG11_ALLOW_M  (PMS_CORE0_MM_HP_USBOTG11_ALLOW_V << PMS_CORE0_MM_HP_USBOTG11_ALLOW_S)
+#define PMS_CORE0_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USBOTG11_ALLOW_S  1
+/** PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP full-speed
+ *  USB 2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V << PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_CORE0_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_CORE0_MM_HP_GDMA_ALLOW_M  (PMS_CORE0_MM_HP_GDMA_ALLOW_V << PMS_CORE0_MM_HP_GDMA_ALLOW_S)
+#define PMS_CORE0_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GDMA_ALLOW_S  3
+/** PMS_CORE0_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_CORE0_MM_HP_SDMMC_ALLOW_M  (PMS_CORE0_MM_HP_SDMMC_ALLOW_V << PMS_CORE0_MM_HP_SDMMC_ALLOW_S)
+#define PMS_CORE0_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_SDMMC_ALLOW_S  5
+/** PMS_CORE0_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_M  (PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_V << PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_CORE0_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_CORE0_MM_HP_JPEG_ALLOW_M  (PMS_CORE0_MM_HP_JPEG_ALLOW_V << PMS_CORE0_MM_HP_JPEG_ALLOW_S)
+#define PMS_CORE0_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_JPEG_ALLOW_S  7
+/** PMS_CORE0_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_CORE0_MM_HP_PPA_ALLOW_M  (PMS_CORE0_MM_HP_PPA_ALLOW_V << PMS_CORE0_MM_HP_PPA_ALLOW_S)
+#define PMS_CORE0_MM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PPA_ALLOW_S  8
+/** PMS_CORE0_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_CORE0_MM_HP_DMA2D_ALLOW_M  (PMS_CORE0_MM_HP_DMA2D_ALLOW_V << PMS_CORE0_MM_HP_DMA2D_ALLOW_S)
+#define PMS_CORE0_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_DMA2D_ALLOW_S  9
+/** PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP key manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_M  (PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_V << PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_CORE0_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_M  (PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_V << PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_CORE0_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP flash MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_CORE0_MM_HP_FLASH_ALLOW_M  (PMS_CORE0_MM_HP_FLASH_ALLOW_V << PMS_CORE0_MM_HP_FLASH_ALLOW_S)
+#define PMS_CORE0_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_FLASH_ALLOW_S  12
+/** PMS_CORE0_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PSRAM MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_CORE0_MM_HP_PSRAM_ALLOW_M  (PMS_CORE0_MM_HP_PSRAM_ALLOW_V << PMS_CORE0_MM_HP_PSRAM_ALLOW_S)
+#define PMS_CORE0_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PSRAM_ALLOW_S  13
+/** PMS_CORE0_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP CRYPTO
+ *  (including AES/SHA/RSA/HMAC Accelerators).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_CORE0_MM_HP_CRYPTO_ALLOW_M  (PMS_CORE0_MM_HP_CRYPTO_ALLOW_V << PMS_CORE0_MM_HP_CRYPTO_ALLOW_S)
+#define PMS_CORE0_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_CRYPTO_ALLOW_S  14
+/** PMS_CORE0_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_CORE0_MM_HP_GMAC_ALLOW_M  (PMS_CORE0_MM_HP_GMAC_ALLOW_V << PMS_CORE0_MM_HP_GMAC_ALLOW_S)
+#define PMS_CORE0_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GMAC_ALLOW_S  15
+/** PMS_CORE0_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP high-speed
+ *  USB 2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_CORE0_MM_HP_USB_PHY_ALLOW_M  (PMS_CORE0_MM_HP_USB_PHY_ALLOW_V << PMS_CORE0_MM_HP_USB_PHY_ALLOW_S)
+#define PMS_CORE0_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USB_PHY_ALLOW_S  16
+/** PMS_CORE0_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_CORE0_MM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_CORE0_MM_HP_PVT_ALLOW_M  (PMS_CORE0_MM_HP_PVT_ALLOW_V << PMS_CORE0_MM_HP_PVT_ALLOW_S)
+#define PMS_CORE0_MM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PVT_ALLOW_S  17
+/** PMS_CORE0_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP MIPI CSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_CORE0_MM_HP_CSI_HOST_ALLOW_M  (PMS_CORE0_MM_HP_CSI_HOST_ALLOW_V << PMS_CORE0_MM_HP_CSI_HOST_ALLOW_S)
+#define PMS_CORE0_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_CORE0_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP MIPI DSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_CORE0_MM_HP_DSI_HOST_ALLOW_M  (PMS_CORE0_MM_HP_DSI_HOST_ALLOW_V << PMS_CORE0_MM_HP_DSI_HOST_ALLOW_S)
+#define PMS_CORE0_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_CORE0_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP ISP (Image
+ *  Signal Processor).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_CORE0_MM_HP_ISP_ALLOW_M  (PMS_CORE0_MM_HP_ISP_ALLOW_V << PMS_CORE0_MM_HP_ISP_ALLOW_S)
+#define PMS_CORE0_MM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_ISP_ALLOW_S  20
+/** PMS_CORE0_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP H264
+ *  Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_CORE0_MM_HP_H264_CORE_ALLOW_M  (PMS_CORE0_MM_HP_H264_CORE_ALLOW_V << PMS_CORE0_MM_HP_H264_CORE_ALLOW_S)
+#define PMS_CORE0_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_H264_CORE_ALLOW_S  21
+/** PMS_CORE0_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_CORE0_MM_HP_RMT_ALLOW_M  (PMS_CORE0_MM_HP_RMT_ALLOW_V << PMS_CORE0_MM_HP_RMT_ALLOW_S)
+#define PMS_CORE0_MM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_RMT_ALLOW_S  22
+/** PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP bit
+ *  scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_M  (PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_CORE0_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_CORE0_MM_HP_AXI_ICM_ALLOW_M  (PMS_CORE0_MM_HP_AXI_ICM_ALLOW_V << PMS_CORE0_MM_HP_AXI_ICM_ALLOW_S)
+#define PMS_CORE0_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_CORE0_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access
+ *  HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_CORE0_MM_HP_PERI_PMS_ALLOW_M  (PMS_CORE0_MM_HP_PERI_PMS_ALLOW_V << PMS_CORE0_MM_HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE0_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_M  (PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V << PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_CORE0_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_CORE0_MM_DMA_PMS_ALLOW_M  (PMS_CORE0_MM_DMA_PMS_ALLOW_V << PMS_CORE0_MM_DMA_PMS_ALLOW_S)
+#define PMS_CORE0_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_DMA_PMS_ALLOW_S  27
+/** PMS_CORE0_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_M  (PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_V << PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_CORE0_MM_HP_PERI_PMS_REG2_REG register
+ *  Permission control register2 for HP CPU0 in machine mode
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x10)
+/** PMS_CORE0_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_CORE0_MM_HP_MCPWM0_ALLOW_M  (PMS_CORE0_MM_HP_MCPWM0_ALLOW_V << PMS_CORE0_MM_HP_MCPWM0_ALLOW_S)
+#define PMS_CORE0_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_MCPWM0_ALLOW_S  0
+/** PMS_CORE0_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_CORE0_MM_HP_MCPWM1_ALLOW_M  (PMS_CORE0_MM_HP_MCPWM1_ALLOW_V << PMS_CORE0_MM_HP_MCPWM1_ALLOW_S)
+#define PMS_CORE0_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_MCPWM1_ALLOW_S  1
+/** PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP timer
+ *  group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_M  (PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V << PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP timer group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_M  (PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V << PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_CORE0_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_CORE0_MM_HP_I2C0_ALLOW_M  (PMS_CORE0_MM_HP_I2C0_ALLOW_V << PMS_CORE0_MM_HP_I2C0_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2C0_ALLOW_S  4
+/** PMS_CORE0_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_CORE0_MM_HP_I2C1_ALLOW_M  (PMS_CORE0_MM_HP_I2C1_ALLOW_V << PMS_CORE0_MM_HP_I2C1_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2C1_ALLOW_S  5
+/** PMS_CORE0_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_CORE0_MM_HP_I2S0_ALLOW_M  (PMS_CORE0_MM_HP_I2S0_ALLOW_V << PMS_CORE0_MM_HP_I2S0_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2S0_ALLOW_S  6
+/** PMS_CORE0_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_CORE0_MM_HP_I2S1_ALLOW_M  (PMS_CORE0_MM_HP_I2S1_ALLOW_V << PMS_CORE0_MM_HP_I2S1_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2S1_ALLOW_S  7
+/** PMS_CORE0_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_CORE0_MM_HP_I2S2_ALLOW_M  (PMS_CORE0_MM_HP_I2S2_ALLOW_V << PMS_CORE0_MM_HP_I2S2_ALLOW_S)
+#define PMS_CORE0_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I2S2_ALLOW_S  8
+/** PMS_CORE0_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_CORE0_MM_HP_PCNT_ALLOW_M  (PMS_CORE0_MM_HP_PCNT_ALLOW_V << PMS_CORE0_MM_HP_PCNT_ALLOW_S)
+#define PMS_CORE0_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PCNT_ALLOW_S  9
+/** PMS_CORE0_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_CORE0_MM_HP_UART0_ALLOW_M  (PMS_CORE0_MM_HP_UART0_ALLOW_V << PMS_CORE0_MM_HP_UART0_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART0_ALLOW_S  10
+/** PMS_CORE0_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_CORE0_MM_HP_UART1_ALLOW_M  (PMS_CORE0_MM_HP_UART1_ALLOW_V << PMS_CORE0_MM_HP_UART1_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART1_ALLOW_S  11
+/** PMS_CORE0_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_CORE0_MM_HP_UART2_ALLOW_M  (PMS_CORE0_MM_HP_UART2_ALLOW_V << PMS_CORE0_MM_HP_UART2_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART2_ALLOW_S  12
+/** PMS_CORE0_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_CORE0_MM_HP_UART3_ALLOW_M  (PMS_CORE0_MM_HP_UART3_ALLOW_V << PMS_CORE0_MM_HP_UART3_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART3_ALLOW_S  13
+/** PMS_CORE0_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_CORE0_MM_HP_UART4_ALLOW_M  (PMS_CORE0_MM_HP_UART4_ALLOW_V << PMS_CORE0_MM_HP_UART4_ALLOW_S)
+#define PMS_CORE0_MM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UART4_ALLOW_S  14
+/** PMS_CORE0_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_CORE0_MM_HP_PARLIO_ALLOW_M  (PMS_CORE0_MM_HP_PARLIO_ALLOW_V << PMS_CORE0_MM_HP_PARLIO_ALLOW_S)
+#define PMS_CORE0_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_PARLIO_ALLOW_S  15
+/** PMS_CORE0_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_CORE0_MM_HP_GPSPI2_ALLOW_M  (PMS_CORE0_MM_HP_GPSPI2_ALLOW_V << PMS_CORE0_MM_HP_GPSPI2_ALLOW_S)
+#define PMS_CORE0_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GPSPI2_ALLOW_S  16
+/** PMS_CORE0_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_CORE0_MM_HP_GPSPI3_ALLOW_M  (PMS_CORE0_MM_HP_GPSPI3_ALLOW_V << PMS_CORE0_MM_HP_GPSPI3_ALLOW_S)
+#define PMS_CORE0_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GPSPI3_ALLOW_S  17
+/** PMS_CORE0_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP USB
+ *  Serial/JTAG Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_CORE0_MM_HP_USBDEVICE_ALLOW_M  (PMS_CORE0_MM_HP_USBDEVICE_ALLOW_V << PMS_CORE0_MM_HP_USBDEVICE_ALLOW_S)
+#define PMS_CORE0_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_CORE0_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_CORE0_MM_HP_LEDC_ALLOW_M  (PMS_CORE0_MM_HP_LEDC_ALLOW_V << PMS_CORE0_MM_HP_LEDC_ALLOW_S)
+#define PMS_CORE0_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_LEDC_ALLOW_S  19
+/** PMS_CORE0_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP ETM (Event
+ *  Task Matrix).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_CORE0_MM_HP_ETM_ALLOW_M  (PMS_CORE0_MM_HP_ETM_ALLOW_V << PMS_CORE0_MM_HP_ETM_ALLOW_S)
+#define PMS_CORE0_MM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_ETM_ALLOW_S  21
+/** PMS_CORE0_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_CORE0_MM_HP_INTRMTX_ALLOW_M  (PMS_CORE0_MM_HP_INTRMTX_ALLOW_V << PMS_CORE0_MM_HP_INTRMTX_ALLOW_S)
+#define PMS_CORE0_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_INTRMTX_ALLOW_S  22
+/** PMS_CORE0_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_CORE0_MM_HP_TWAI0_ALLOW_M  (PMS_CORE0_MM_HP_TWAI0_ALLOW_V << PMS_CORE0_MM_HP_TWAI0_ALLOW_S)
+#define PMS_CORE0_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TWAI0_ALLOW_S  23
+/** PMS_CORE0_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_CORE0_MM_HP_TWAI1_ALLOW_M  (PMS_CORE0_MM_HP_TWAI1_ALLOW_V << PMS_CORE0_MM_HP_TWAI1_ALLOW_S)
+#define PMS_CORE0_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TWAI1_ALLOW_S  24
+/** PMS_CORE0_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_CORE0_MM_HP_TWAI2_ALLOW_M  (PMS_CORE0_MM_HP_TWAI2_ALLOW_V << PMS_CORE0_MM_HP_TWAI2_ALLOW_S)
+#define PMS_CORE0_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_TWAI2_ALLOW_S  25
+/** PMS_CORE0_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I3C master
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_CORE0_MM_HP_I3C_MST_ALLOW_M  (PMS_CORE0_MM_HP_I3C_MST_ALLOW_V << PMS_CORE0_MM_HP_I3C_MST_ALLOW_S)
+#define PMS_CORE0_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I3C_MST_ALLOW_S  26
+/** PMS_CORE0_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_CORE0_MM_HP_I3C_SLV_ALLOW_M  (PMS_CORE0_MM_HP_I3C_SLV_ALLOW_V << PMS_CORE0_MM_HP_I3C_SLV_ALLOW_S)
+#define PMS_CORE0_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_CORE0_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_CORE0_MM_HP_LCDCAM_ALLOW_M  (PMS_CORE0_MM_HP_LCDCAM_ALLOW_V << PMS_CORE0_MM_HP_LCDCAM_ALLOW_S)
+#define PMS_CORE0_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_LCDCAM_ALLOW_S  28
+/** PMS_CORE0_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_CORE0_MM_HP_ADC_ALLOW_M  (PMS_CORE0_MM_HP_ADC_ALLOW_V << PMS_CORE0_MM_HP_ADC_ALLOW_S)
+#define PMS_CORE0_MM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_ADC_ALLOW_S  30
+/** PMS_CORE0_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_CORE0_MM_HP_UHCI_ALLOW_M  (PMS_CORE0_MM_HP_UHCI_ALLOW_V << PMS_CORE0_MM_HP_UHCI_ALLOW_S)
+#define PMS_CORE0_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_UHCI_ALLOW_S  31
+
+/** PMS_CORE0_MM_HP_PERI_PMS_REG3_REG register
+ *  Permission control register3 for HP CPU0 in machine mode
+ */
+#define PMS_CORE0_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x14)
+/** PMS_CORE0_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP GPIO Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_CORE0_MM_HP_GPIO_ALLOW_M  (PMS_CORE0_MM_HP_GPIO_ALLOW_V << PMS_CORE0_MM_HP_GPIO_ALLOW_S)
+#define PMS_CORE0_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_GPIO_ALLOW_S  0
+/** PMS_CORE0_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_CORE0_MM_HP_IOMUX_ALLOW_M  (PMS_CORE0_MM_HP_IOMUX_ALLOW_V << PMS_CORE0_MM_HP_IOMUX_ALLOW_S)
+#define PMS_CORE0_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_IOMUX_ALLOW_S  1
+/** PMS_CORE0_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP system
+ *  timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_CORE0_MM_HP_SYSTIMER_ALLOW_M  (PMS_CORE0_MM_HP_SYSTIMER_ALLOW_V << PMS_CORE0_MM_HP_SYSTIMER_ALLOW_S)
+#define PMS_CORE0_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_CORE0_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_CORE0_MM_HP_SYS_REG_ALLOW_M  (PMS_CORE0_MM_HP_SYS_REG_ALLOW_V << PMS_CORE0_MM_HP_SYS_REG_ALLOW_S)
+#define PMS_CORE0_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_SYS_REG_ALLOW_S  3
+/** PMS_CORE0_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in machine mode has permission to access HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_CORE0_MM_HP_CLKRST_ALLOW_M  (PMS_CORE0_MM_HP_CLKRST_ALLOW_V << PMS_CORE0_MM_HP_CLKRST_ALLOW_S)
+#define PMS_CORE0_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_CORE0_MM_HP_CLKRST_ALLOW_S  4
+
+/** PMS_CORE0_UM_HP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU0 in user mode
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x18)
+/** PMS_CORE0_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_PSRAM_ALLOW    (BIT(0))
+#define PMS_CORE0_UM_PSRAM_ALLOW_M  (PMS_CORE0_UM_PSRAM_ALLOW_V << PMS_CORE0_UM_PSRAM_ALLOW_S)
+#define PMS_CORE0_UM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_PSRAM_ALLOW_S  0
+/** PMS_CORE0_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access external flash
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_FLASH_ALLOW    (BIT(1))
+#define PMS_CORE0_UM_FLASH_ALLOW_M  (PMS_CORE0_UM_FLASH_ALLOW_V << PMS_CORE0_UM_FLASH_ALLOW_S)
+#define PMS_CORE0_UM_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_FLASH_ALLOW_S  1
+/** PMS_CORE0_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP L2MEM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_L2MEM_ALLOW    (BIT(2))
+#define PMS_CORE0_UM_L2MEM_ALLOW_M  (PMS_CORE0_UM_L2MEM_ALLOW_V << PMS_CORE0_UM_L2MEM_ALLOW_S)
+#define PMS_CORE0_UM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_L2MEM_ALLOW_S  2
+/** PMS_CORE0_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP ROM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_L2ROM_ALLOW    (BIT(3))
+#define PMS_CORE0_UM_L2ROM_ALLOW_M  (PMS_CORE0_UM_L2ROM_ALLOW_V << PMS_CORE0_UM_L2ROM_ALLOW_S)
+#define PMS_CORE0_UM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_L2ROM_ALLOW_S  3
+/** PMS_CORE0_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_TRACE0_ALLOW    (BIT(6))
+#define PMS_CORE0_UM_TRACE0_ALLOW_M  (PMS_CORE0_UM_TRACE0_ALLOW_V << PMS_CORE0_UM_TRACE0_ALLOW_S)
+#define PMS_CORE0_UM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_TRACE0_ALLOW_S  6
+/** PMS_CORE0_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_TRACE1_ALLOW    (BIT(7))
+#define PMS_CORE0_UM_TRACE1_ALLOW_M  (PMS_CORE0_UM_TRACE1_ALLOW_V << PMS_CORE0_UM_TRACE1_ALLOW_S)
+#define PMS_CORE0_UM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_TRACE1_ALLOW_S  7
+/** PMS_CORE0_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access CPU bus monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_CORE0_UM_CPU_BUS_MON_ALLOW_M  (PMS_CORE0_UM_CPU_BUS_MON_ALLOW_V << PMS_CORE0_UM_CPU_BUS_MON_ALLOW_S)
+#define PMS_CORE0_UM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_CORE0_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access L2MEM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_CORE0_UM_L2MEM_MON_ALLOW_M  (PMS_CORE0_UM_L2MEM_MON_ALLOW_V << PMS_CORE0_UM_L2MEM_MON_ALLOW_S)
+#define PMS_CORE0_UM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_L2MEM_MON_ALLOW_S  9
+/** PMS_CORE0_UM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_CORE0_UM_SPM_MON_ALLOW_M  (PMS_CORE0_UM_SPM_MON_ALLOW_V << PMS_CORE0_UM_SPM_MON_ALLOW_S)
+#define PMS_CORE0_UM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_SPM_MON_ALLOW_S  10
+/** PMS_CORE0_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_CACHE_ALLOW    (BIT(11))
+#define PMS_CORE0_UM_CACHE_ALLOW_M  (PMS_CORE0_UM_CACHE_ALLOW_V << PMS_CORE0_UM_CACHE_ALLOW_S)
+#define PMS_CORE0_UM_CACHE_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_CACHE_ALLOW_S  11
+
+/** PMS_CORE0_UM_HP_PERI_PMS_REG1_REG register
+ *  Permission control register1 for HP CPU0 in user mode
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x1c)
+/** PMS_CORE0_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP high-speed USB
+ *  2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_CORE0_UM_HP_USBOTG_ALLOW_M  (PMS_CORE0_UM_HP_USBOTG_ALLOW_V << PMS_CORE0_UM_HP_USBOTG_ALLOW_S)
+#define PMS_CORE0_UM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USBOTG_ALLOW_S  0
+/** PMS_CORE0_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP full-speed USB
+ *  2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_CORE0_UM_HP_USBOTG11_ALLOW_M  (PMS_CORE0_UM_HP_USBOTG11_ALLOW_V << PMS_CORE0_UM_HP_USBOTG11_ALLOW_S)
+#define PMS_CORE0_UM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USBOTG11_ALLOW_S  1
+/** PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP full-speed USB
+ *  2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V << PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_CORE0_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_CORE0_UM_HP_GDMA_ALLOW_M  (PMS_CORE0_UM_HP_GDMA_ALLOW_V << PMS_CORE0_UM_HP_GDMA_ALLOW_S)
+#define PMS_CORE0_UM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GDMA_ALLOW_S  3
+/** PMS_CORE0_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_CORE0_UM_HP_SDMMC_ALLOW_M  (PMS_CORE0_UM_HP_SDMMC_ALLOW_V << PMS_CORE0_UM_HP_SDMMC_ALLOW_S)
+#define PMS_CORE0_UM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_SDMMC_ALLOW_S  5
+/** PMS_CORE0_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_M  (PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_V << PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_CORE0_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_CORE0_UM_HP_JPEG_ALLOW_M  (PMS_CORE0_UM_HP_JPEG_ALLOW_V << PMS_CORE0_UM_HP_JPEG_ALLOW_S)
+#define PMS_CORE0_UM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_JPEG_ALLOW_S  7
+/** PMS_CORE0_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_CORE0_UM_HP_PPA_ALLOW_M  (PMS_CORE0_UM_HP_PPA_ALLOW_V << PMS_CORE0_UM_HP_PPA_ALLOW_S)
+#define PMS_CORE0_UM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PPA_ALLOW_S  8
+/** PMS_CORE0_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_CORE0_UM_HP_DMA2D_ALLOW_M  (PMS_CORE0_UM_HP_DMA2D_ALLOW_V << PMS_CORE0_UM_HP_DMA2D_ALLOW_S)
+#define PMS_CORE0_UM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_DMA2D_ALLOW_S  9
+/** PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP key manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_M  (PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_V << PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_CORE0_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_M  (PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_V << PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_CORE0_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP flash MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_CORE0_UM_HP_FLASH_ALLOW_M  (PMS_CORE0_UM_HP_FLASH_ALLOW_V << PMS_CORE0_UM_HP_FLASH_ALLOW_S)
+#define PMS_CORE0_UM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_FLASH_ALLOW_S  12
+/** PMS_CORE0_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PSRAM MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_CORE0_UM_HP_PSRAM_ALLOW_M  (PMS_CORE0_UM_HP_PSRAM_ALLOW_V << PMS_CORE0_UM_HP_PSRAM_ALLOW_S)
+#define PMS_CORE0_UM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PSRAM_ALLOW_S  13
+/** PMS_CORE0_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP CRYPTO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_CORE0_UM_HP_CRYPTO_ALLOW_M  (PMS_CORE0_UM_HP_CRYPTO_ALLOW_V << PMS_CORE0_UM_HP_CRYPTO_ALLOW_S)
+#define PMS_CORE0_UM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_CRYPTO_ALLOW_S  14
+/** PMS_CORE0_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_CORE0_UM_HP_GMAC_ALLOW_M  (PMS_CORE0_UM_HP_GMAC_ALLOW_V << PMS_CORE0_UM_HP_GMAC_ALLOW_S)
+#define PMS_CORE0_UM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GMAC_ALLOW_S  15
+/** PMS_CORE0_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP high-speed USB
+ *  2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_CORE0_UM_HP_USB_PHY_ALLOW_M  (PMS_CORE0_UM_HP_USB_PHY_ALLOW_V << PMS_CORE0_UM_HP_USB_PHY_ALLOW_S)
+#define PMS_CORE0_UM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USB_PHY_ALLOW_S  16
+/** PMS_CORE0_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_CORE0_UM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_CORE0_UM_HP_PVT_ALLOW_M  (PMS_CORE0_UM_HP_PVT_ALLOW_V << PMS_CORE0_UM_HP_PVT_ALLOW_S)
+#define PMS_CORE0_UM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PVT_ALLOW_S  17
+/** PMS_CORE0_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP MIPI CSI host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_CORE0_UM_HP_CSI_HOST_ALLOW_M  (PMS_CORE0_UM_HP_CSI_HOST_ALLOW_V << PMS_CORE0_UM_HP_CSI_HOST_ALLOW_S)
+#define PMS_CORE0_UM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_CORE0_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP MIPI DSI host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_CORE0_UM_HP_DSI_HOST_ALLOW_M  (PMS_CORE0_UM_HP_DSI_HOST_ALLOW_V << PMS_CORE0_UM_HP_DSI_HOST_ALLOW_S)
+#define PMS_CORE0_UM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_CORE0_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP ISP.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_CORE0_UM_HP_ISP_ALLOW_M  (PMS_CORE0_UM_HP_ISP_ALLOW_V << PMS_CORE0_UM_HP_ISP_ALLOW_S)
+#define PMS_CORE0_UM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_ISP_ALLOW_S  20
+/** PMS_CORE0_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP H264 Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_CORE0_UM_HP_H264_CORE_ALLOW_M  (PMS_CORE0_UM_HP_H264_CORE_ALLOW_V << PMS_CORE0_UM_HP_H264_CORE_ALLOW_S)
+#define PMS_CORE0_UM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_H264_CORE_ALLOW_S  21
+/** PMS_CORE0_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_CORE0_UM_HP_RMT_ALLOW_M  (PMS_CORE0_UM_HP_RMT_ALLOW_V << PMS_CORE0_UM_HP_RMT_ALLOW_S)
+#define PMS_CORE0_UM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_RMT_ALLOW_S  22
+/** PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP bit scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_M  (PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_CORE0_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_CORE0_UM_HP_AXI_ICM_ALLOW_M  (PMS_CORE0_UM_HP_AXI_ICM_ALLOW_V << PMS_CORE0_UM_HP_AXI_ICM_ALLOW_S)
+#define PMS_CORE0_UM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_CORE0_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_CORE0_UM_HP_PERI_PMS_ALLOW_M  (PMS_CORE0_UM_HP_PERI_PMS_ALLOW_V << PMS_CORE0_UM_HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE0_UM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_M  (PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V << PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_CORE0_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_CORE0_UM_DMA_PMS_ALLOW_M  (PMS_CORE0_UM_DMA_PMS_ALLOW_V << PMS_CORE0_UM_DMA_PMS_ALLOW_S)
+#define PMS_CORE0_UM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_DMA_PMS_ALLOW_S  27
+/** PMS_CORE0_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_M  (PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_V << PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_CORE0_UM_HP_PERI_PMS_REG2_REG register
+ *  Permission control register2 for HP CPU0 in user mode
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x20)
+/** PMS_CORE0_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_CORE0_UM_HP_MCPWM0_ALLOW_M  (PMS_CORE0_UM_HP_MCPWM0_ALLOW_V << PMS_CORE0_UM_HP_MCPWM0_ALLOW_S)
+#define PMS_CORE0_UM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_MCPWM0_ALLOW_S  0
+/** PMS_CORE0_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_CORE0_UM_HP_MCPWM1_ALLOW_M  (PMS_CORE0_UM_HP_MCPWM1_ALLOW_V << PMS_CORE0_UM_HP_MCPWM1_ALLOW_S)
+#define PMS_CORE0_UM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_MCPWM1_ALLOW_S  1
+/** PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP timer group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_M  (PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V << PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP timer group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_M  (PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V << PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_CORE0_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_CORE0_UM_HP_I2C0_ALLOW_M  (PMS_CORE0_UM_HP_I2C0_ALLOW_V << PMS_CORE0_UM_HP_I2C0_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2C0_ALLOW_S  4
+/** PMS_CORE0_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_CORE0_UM_HP_I2C1_ALLOW_M  (PMS_CORE0_UM_HP_I2C1_ALLOW_V << PMS_CORE0_UM_HP_I2C1_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2C1_ALLOW_S  5
+/** PMS_CORE0_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_CORE0_UM_HP_I2S0_ALLOW_M  (PMS_CORE0_UM_HP_I2S0_ALLOW_V << PMS_CORE0_UM_HP_I2S0_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2S0_ALLOW_S  6
+/** PMS_CORE0_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_CORE0_UM_HP_I2S1_ALLOW_M  (PMS_CORE0_UM_HP_I2S1_ALLOW_V << PMS_CORE0_UM_HP_I2S1_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2S1_ALLOW_S  7
+/** PMS_CORE0_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_CORE0_UM_HP_I2S2_ALLOW_M  (PMS_CORE0_UM_HP_I2S2_ALLOW_V << PMS_CORE0_UM_HP_I2S2_ALLOW_S)
+#define PMS_CORE0_UM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I2S2_ALLOW_S  8
+/** PMS_CORE0_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_CORE0_UM_HP_PCNT_ALLOW_M  (PMS_CORE0_UM_HP_PCNT_ALLOW_V << PMS_CORE0_UM_HP_PCNT_ALLOW_S)
+#define PMS_CORE0_UM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PCNT_ALLOW_S  9
+/** PMS_CORE0_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_CORE0_UM_HP_UART0_ALLOW_M  (PMS_CORE0_UM_HP_UART0_ALLOW_V << PMS_CORE0_UM_HP_UART0_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART0_ALLOW_S  10
+/** PMS_CORE0_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_CORE0_UM_HP_UART1_ALLOW_M  (PMS_CORE0_UM_HP_UART1_ALLOW_V << PMS_CORE0_UM_HP_UART1_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART1_ALLOW_S  11
+/** PMS_CORE0_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_CORE0_UM_HP_UART2_ALLOW_M  (PMS_CORE0_UM_HP_UART2_ALLOW_V << PMS_CORE0_UM_HP_UART2_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART2_ALLOW_S  12
+/** PMS_CORE0_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_CORE0_UM_HP_UART3_ALLOW_M  (PMS_CORE0_UM_HP_UART3_ALLOW_V << PMS_CORE0_UM_HP_UART3_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART3_ALLOW_S  13
+/** PMS_CORE0_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_CORE0_UM_HP_UART4_ALLOW_M  (PMS_CORE0_UM_HP_UART4_ALLOW_V << PMS_CORE0_UM_HP_UART4_ALLOW_S)
+#define PMS_CORE0_UM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UART4_ALLOW_S  14
+/** PMS_CORE0_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_CORE0_UM_HP_PARLIO_ALLOW_M  (PMS_CORE0_UM_HP_PARLIO_ALLOW_V << PMS_CORE0_UM_HP_PARLIO_ALLOW_S)
+#define PMS_CORE0_UM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_PARLIO_ALLOW_S  15
+/** PMS_CORE0_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_CORE0_UM_HP_GPSPI2_ALLOW_M  (PMS_CORE0_UM_HP_GPSPI2_ALLOW_V << PMS_CORE0_UM_HP_GPSPI2_ALLOW_S)
+#define PMS_CORE0_UM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GPSPI2_ALLOW_S  16
+/** PMS_CORE0_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_CORE0_UM_HP_GPSPI3_ALLOW_M  (PMS_CORE0_UM_HP_GPSPI3_ALLOW_V << PMS_CORE0_UM_HP_GPSPI3_ALLOW_S)
+#define PMS_CORE0_UM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GPSPI3_ALLOW_S  17
+/** PMS_CORE0_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP USB/Serial JTAG
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_CORE0_UM_HP_USBDEVICE_ALLOW_M  (PMS_CORE0_UM_HP_USBDEVICE_ALLOW_V << PMS_CORE0_UM_HP_USBDEVICE_ALLOW_S)
+#define PMS_CORE0_UM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_CORE0_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_CORE0_UM_HP_LEDC_ALLOW_M  (PMS_CORE0_UM_HP_LEDC_ALLOW_V << PMS_CORE0_UM_HP_LEDC_ALLOW_S)
+#define PMS_CORE0_UM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_LEDC_ALLOW_S  19
+/** PMS_CORE0_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP ETM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_CORE0_UM_HP_ETM_ALLOW_M  (PMS_CORE0_UM_HP_ETM_ALLOW_V << PMS_CORE0_UM_HP_ETM_ALLOW_S)
+#define PMS_CORE0_UM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_ETM_ALLOW_S  21
+/** PMS_CORE0_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_CORE0_UM_HP_INTRMTX_ALLOW_M  (PMS_CORE0_UM_HP_INTRMTX_ALLOW_V << PMS_CORE0_UM_HP_INTRMTX_ALLOW_S)
+#define PMS_CORE0_UM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_INTRMTX_ALLOW_S  22
+/** PMS_CORE0_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_CORE0_UM_HP_TWAI0_ALLOW_M  (PMS_CORE0_UM_HP_TWAI0_ALLOW_V << PMS_CORE0_UM_HP_TWAI0_ALLOW_S)
+#define PMS_CORE0_UM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TWAI0_ALLOW_S  23
+/** PMS_CORE0_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_CORE0_UM_HP_TWAI1_ALLOW_M  (PMS_CORE0_UM_HP_TWAI1_ALLOW_V << PMS_CORE0_UM_HP_TWAI1_ALLOW_S)
+#define PMS_CORE0_UM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TWAI1_ALLOW_S  24
+/** PMS_CORE0_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_CORE0_UM_HP_TWAI2_ALLOW_M  (PMS_CORE0_UM_HP_TWAI2_ALLOW_V << PMS_CORE0_UM_HP_TWAI2_ALLOW_S)
+#define PMS_CORE0_UM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_TWAI2_ALLOW_S  25
+/** PMS_CORE0_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I3C master
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_CORE0_UM_HP_I3C_MST_ALLOW_M  (PMS_CORE0_UM_HP_I3C_MST_ALLOW_V << PMS_CORE0_UM_HP_I3C_MST_ALLOW_S)
+#define PMS_CORE0_UM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I3C_MST_ALLOW_S  26
+/** PMS_CORE0_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_CORE0_UM_HP_I3C_SLV_ALLOW_M  (PMS_CORE0_UM_HP_I3C_SLV_ALLOW_V << PMS_CORE0_UM_HP_I3C_SLV_ALLOW_S)
+#define PMS_CORE0_UM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_CORE0_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_CORE0_UM_HP_LCDCAM_ALLOW_M  (PMS_CORE0_UM_HP_LCDCAM_ALLOW_V << PMS_CORE0_UM_HP_LCDCAM_ALLOW_S)
+#define PMS_CORE0_UM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_LCDCAM_ALLOW_S  28
+/** PMS_CORE0_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_CORE0_UM_HP_ADC_ALLOW_M  (PMS_CORE0_UM_HP_ADC_ALLOW_V << PMS_CORE0_UM_HP_ADC_ALLOW_S)
+#define PMS_CORE0_UM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_ADC_ALLOW_S  30
+/** PMS_CORE0_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_CORE0_UM_HP_UHCI_ALLOW_M  (PMS_CORE0_UM_HP_UHCI_ALLOW_V << PMS_CORE0_UM_HP_UHCI_ALLOW_S)
+#define PMS_CORE0_UM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_UHCI_ALLOW_S  31
+
+/** PMS_CORE0_UM_HP_PERI_PMS_REG3_REG register
+ *  Permission control register3 for HP CPU0 in user mode
+ */
+#define PMS_CORE0_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x24)
+/** PMS_CORE0_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP GPIO Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_CORE0_UM_HP_GPIO_ALLOW_M  (PMS_CORE0_UM_HP_GPIO_ALLOW_V << PMS_CORE0_UM_HP_GPIO_ALLOW_S)
+#define PMS_CORE0_UM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_GPIO_ALLOW_S  0
+/** PMS_CORE0_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_CORE0_UM_HP_IOMUX_ALLOW_M  (PMS_CORE0_UM_HP_IOMUX_ALLOW_V << PMS_CORE0_UM_HP_IOMUX_ALLOW_S)
+#define PMS_CORE0_UM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_IOMUX_ALLOW_S  1
+/** PMS_CORE0_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP system timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_CORE0_UM_HP_SYSTIMER_ALLOW_M  (PMS_CORE0_UM_HP_SYSTIMER_ALLOW_V << PMS_CORE0_UM_HP_SYSTIMER_ALLOW_S)
+#define PMS_CORE0_UM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_CORE0_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_CORE0_UM_HP_SYS_REG_ALLOW_M  (PMS_CORE0_UM_HP_SYS_REG_ALLOW_V << PMS_CORE0_UM_HP_SYS_REG_ALLOW_S)
+#define PMS_CORE0_UM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_SYS_REG_ALLOW_S  3
+/** PMS_CORE0_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU0 in user mode has permission to access HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE0_UM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_CORE0_UM_HP_CLKRST_ALLOW_M  (PMS_CORE0_UM_HP_CLKRST_ALLOW_V << PMS_CORE0_UM_HP_CLKRST_ALLOW_S)
+#define PMS_CORE0_UM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_CORE0_UM_HP_CLKRST_ALLOW_S  4
+
+/** PMS_CORE1_MM_HP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU1 in machine mode
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x28)
+/** PMS_CORE1_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_PSRAM_ALLOW    (BIT(0))
+#define PMS_CORE1_MM_PSRAM_ALLOW_M  (PMS_CORE1_MM_PSRAM_ALLOW_V << PMS_CORE1_MM_PSRAM_ALLOW_S)
+#define PMS_CORE1_MM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_PSRAM_ALLOW_S  0
+/** PMS_CORE1_MM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access external flash
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_FLASH_ALLOW    (BIT(1))
+#define PMS_CORE1_MM_FLASH_ALLOW_M  (PMS_CORE1_MM_FLASH_ALLOW_V << PMS_CORE1_MM_FLASH_ALLOW_S)
+#define PMS_CORE1_MM_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_FLASH_ALLOW_S  1
+/** PMS_CORE1_MM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP L2MEM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_L2MEM_ALLOW    (BIT(2))
+#define PMS_CORE1_MM_L2MEM_ALLOW_M  (PMS_CORE1_MM_L2MEM_ALLOW_V << PMS_CORE1_MM_L2MEM_ALLOW_S)
+#define PMS_CORE1_MM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_L2MEM_ALLOW_S  2
+/** PMS_CORE1_MM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP ROM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_L2ROM_ALLOW    (BIT(3))
+#define PMS_CORE1_MM_L2ROM_ALLOW_M  (PMS_CORE1_MM_L2ROM_ALLOW_V << PMS_CORE1_MM_L2ROM_ALLOW_S)
+#define PMS_CORE1_MM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_L2ROM_ALLOW_S  3
+/** PMS_CORE1_MM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_TRACE0_ALLOW    (BIT(6))
+#define PMS_CORE1_MM_TRACE0_ALLOW_M  (PMS_CORE1_MM_TRACE0_ALLOW_V << PMS_CORE1_MM_TRACE0_ALLOW_S)
+#define PMS_CORE1_MM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_TRACE0_ALLOW_S  6
+/** PMS_CORE1_MM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_TRACE1_ALLOW    (BIT(7))
+#define PMS_CORE1_MM_TRACE1_ALLOW_M  (PMS_CORE1_MM_TRACE1_ALLOW_V << PMS_CORE1_MM_TRACE1_ALLOW_S)
+#define PMS_CORE1_MM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_TRACE1_ALLOW_S  7
+/** PMS_CORE1_MM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access CPU bus
+ *  monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_CORE1_MM_CPU_BUS_MON_ALLOW_M  (PMS_CORE1_MM_CPU_BUS_MON_ALLOW_V << PMS_CORE1_MM_CPU_BUS_MON_ALLOW_S)
+#define PMS_CORE1_MM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_CORE1_MM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access L2MEM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_CORE1_MM_L2MEM_MON_ALLOW_M  (PMS_CORE1_MM_L2MEM_MON_ALLOW_V << PMS_CORE1_MM_L2MEM_MON_ALLOW_S)
+#define PMS_CORE1_MM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_L2MEM_MON_ALLOW_S  9
+/** PMS_CORE1_MM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_CORE1_MM_SPM_MON_ALLOW_M  (PMS_CORE1_MM_SPM_MON_ALLOW_V << PMS_CORE1_MM_SPM_MON_ALLOW_S)
+#define PMS_CORE1_MM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_SPM_MON_ALLOW_S  10
+/** PMS_CORE1_MM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_CACHE_ALLOW    (BIT(11))
+#define PMS_CORE1_MM_CACHE_ALLOW_M  (PMS_CORE1_MM_CACHE_ALLOW_V << PMS_CORE1_MM_CACHE_ALLOW_S)
+#define PMS_CORE1_MM_CACHE_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_CACHE_ALLOW_S  11
+
+/** PMS_CORE1_MM_HP_PERI_PMS_REG1_REG register
+ *  Permission control register1 for HP CPU1 in machine mode
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x2c)
+/** PMS_CORE1_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP high-speed
+ *  USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_CORE1_MM_HP_USBOTG_ALLOW_M  (PMS_CORE1_MM_HP_USBOTG_ALLOW_V << PMS_CORE1_MM_HP_USBOTG_ALLOW_S)
+#define PMS_CORE1_MM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USBOTG_ALLOW_S  0
+/** PMS_CORE1_MM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP full-speed
+ *  USB 2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_CORE1_MM_HP_USBOTG11_ALLOW_M  (PMS_CORE1_MM_HP_USBOTG11_ALLOW_V << PMS_CORE1_MM_HP_USBOTG11_ALLOW_S)
+#define PMS_CORE1_MM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USBOTG11_ALLOW_S  1
+/** PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP full-speed
+ *  USB 2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V << PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_CORE1_MM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_CORE1_MM_HP_GDMA_ALLOW_M  (PMS_CORE1_MM_HP_GDMA_ALLOW_V << PMS_CORE1_MM_HP_GDMA_ALLOW_S)
+#define PMS_CORE1_MM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GDMA_ALLOW_S  3
+/** PMS_CORE1_MM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_CORE1_MM_HP_SDMMC_ALLOW_M  (PMS_CORE1_MM_HP_SDMMC_ALLOW_V << PMS_CORE1_MM_HP_SDMMC_ALLOW_S)
+#define PMS_CORE1_MM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_SDMMC_ALLOW_S  5
+/** PMS_CORE1_MM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_M  (PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_V << PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_CORE1_MM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_CORE1_MM_HP_JPEG_ALLOW_M  (PMS_CORE1_MM_HP_JPEG_ALLOW_V << PMS_CORE1_MM_HP_JPEG_ALLOW_S)
+#define PMS_CORE1_MM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_JPEG_ALLOW_S  7
+/** PMS_CORE1_MM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_CORE1_MM_HP_PPA_ALLOW_M  (PMS_CORE1_MM_HP_PPA_ALLOW_V << PMS_CORE1_MM_HP_PPA_ALLOW_S)
+#define PMS_CORE1_MM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PPA_ALLOW_S  8
+/** PMS_CORE1_MM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_CORE1_MM_HP_DMA2D_ALLOW_M  (PMS_CORE1_MM_HP_DMA2D_ALLOW_V << PMS_CORE1_MM_HP_DMA2D_ALLOW_S)
+#define PMS_CORE1_MM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_DMA2D_ALLOW_S  9
+/** PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP key manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_M  (PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_V << PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_CORE1_MM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_M  (PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_V << PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_CORE1_MM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP flash MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_CORE1_MM_HP_FLASH_ALLOW_M  (PMS_CORE1_MM_HP_FLASH_ALLOW_V << PMS_CORE1_MM_HP_FLASH_ALLOW_S)
+#define PMS_CORE1_MM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_FLASH_ALLOW_S  12
+/** PMS_CORE1_MM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PSRAM MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_CORE1_MM_HP_PSRAM_ALLOW_M  (PMS_CORE1_MM_HP_PSRAM_ALLOW_V << PMS_CORE1_MM_HP_PSRAM_ALLOW_S)
+#define PMS_CORE1_MM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PSRAM_ALLOW_S  13
+/** PMS_CORE1_MM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP CRYPTO
+ *  (including AES/SHA/RSA/HMAC Accelerators).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_CORE1_MM_HP_CRYPTO_ALLOW_M  (PMS_CORE1_MM_HP_CRYPTO_ALLOW_V << PMS_CORE1_MM_HP_CRYPTO_ALLOW_S)
+#define PMS_CORE1_MM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_CRYPTO_ALLOW_S  14
+/** PMS_CORE1_MM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_CORE1_MM_HP_GMAC_ALLOW_M  (PMS_CORE1_MM_HP_GMAC_ALLOW_V << PMS_CORE1_MM_HP_GMAC_ALLOW_S)
+#define PMS_CORE1_MM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GMAC_ALLOW_S  15
+/** PMS_CORE1_MM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP high-speed
+ *  USB 2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_CORE1_MM_HP_USB_PHY_ALLOW_M  (PMS_CORE1_MM_HP_USB_PHY_ALLOW_V << PMS_CORE1_MM_HP_USB_PHY_ALLOW_S)
+#define PMS_CORE1_MM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USB_PHY_ALLOW_S  16
+/** PMS_CORE1_MM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_CORE1_MM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_CORE1_MM_HP_PVT_ALLOW_M  (PMS_CORE1_MM_HP_PVT_ALLOW_V << PMS_CORE1_MM_HP_PVT_ALLOW_S)
+#define PMS_CORE1_MM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PVT_ALLOW_S  17
+/** PMS_CORE1_MM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP MIPI CSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_CORE1_MM_HP_CSI_HOST_ALLOW_M  (PMS_CORE1_MM_HP_CSI_HOST_ALLOW_V << PMS_CORE1_MM_HP_CSI_HOST_ALLOW_S)
+#define PMS_CORE1_MM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_CORE1_MM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP MIPI DSI
+ *  host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_CORE1_MM_HP_DSI_HOST_ALLOW_M  (PMS_CORE1_MM_HP_DSI_HOST_ALLOW_V << PMS_CORE1_MM_HP_DSI_HOST_ALLOW_S)
+#define PMS_CORE1_MM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_CORE1_MM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP ISP (Image
+ *  Signal Processor).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_CORE1_MM_HP_ISP_ALLOW_M  (PMS_CORE1_MM_HP_ISP_ALLOW_V << PMS_CORE1_MM_HP_ISP_ALLOW_S)
+#define PMS_CORE1_MM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_ISP_ALLOW_S  20
+/** PMS_CORE1_MM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP H264
+ *  Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_CORE1_MM_HP_H264_CORE_ALLOW_M  (PMS_CORE1_MM_HP_H264_CORE_ALLOW_V << PMS_CORE1_MM_HP_H264_CORE_ALLOW_S)
+#define PMS_CORE1_MM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_H264_CORE_ALLOW_S  21
+/** PMS_CORE1_MM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_CORE1_MM_HP_RMT_ALLOW_M  (PMS_CORE1_MM_HP_RMT_ALLOW_V << PMS_CORE1_MM_HP_RMT_ALLOW_S)
+#define PMS_CORE1_MM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_RMT_ALLOW_S  22
+/** PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP bit
+ *  scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_M  (PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_CORE1_MM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_CORE1_MM_HP_AXI_ICM_ALLOW_M  (PMS_CORE1_MM_HP_AXI_ICM_ALLOW_V << PMS_CORE1_MM_HP_AXI_ICM_ALLOW_S)
+#define PMS_CORE1_MM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_CORE1_MM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access
+ *  HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_CORE1_MM_HP_PERI_PMS_ALLOW_M  (PMS_CORE1_MM_HP_PERI_PMS_ALLOW_V << PMS_CORE1_MM_HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE1_MM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_M  (PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V << PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_CORE1_MM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_CORE1_MM_DMA_PMS_ALLOW_M  (PMS_CORE1_MM_DMA_PMS_ALLOW_V << PMS_CORE1_MM_DMA_PMS_ALLOW_S)
+#define PMS_CORE1_MM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_DMA_PMS_ALLOW_S  27
+/** PMS_CORE1_MM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_M  (PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_V << PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_CORE1_MM_HP_PERI_PMS_REG2_REG register
+ *  Permission control register2 for HP CPU1 in machine mode
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x30)
+/** PMS_CORE1_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_CORE1_MM_HP_MCPWM0_ALLOW_M  (PMS_CORE1_MM_HP_MCPWM0_ALLOW_V << PMS_CORE1_MM_HP_MCPWM0_ALLOW_S)
+#define PMS_CORE1_MM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_MCPWM0_ALLOW_S  0
+/** PMS_CORE1_MM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_CORE1_MM_HP_MCPWM1_ALLOW_M  (PMS_CORE1_MM_HP_MCPWM1_ALLOW_V << PMS_CORE1_MM_HP_MCPWM1_ALLOW_S)
+#define PMS_CORE1_MM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_MCPWM1_ALLOW_S  1
+/** PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP timer
+ *  group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_M  (PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V << PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP timer group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_M  (PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V << PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_CORE1_MM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_CORE1_MM_HP_I2C0_ALLOW_M  (PMS_CORE1_MM_HP_I2C0_ALLOW_V << PMS_CORE1_MM_HP_I2C0_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2C0_ALLOW_S  4
+/** PMS_CORE1_MM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_CORE1_MM_HP_I2C1_ALLOW_M  (PMS_CORE1_MM_HP_I2C1_ALLOW_V << PMS_CORE1_MM_HP_I2C1_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2C1_ALLOW_S  5
+/** PMS_CORE1_MM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_CORE1_MM_HP_I2S0_ALLOW_M  (PMS_CORE1_MM_HP_I2S0_ALLOW_V << PMS_CORE1_MM_HP_I2S0_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2S0_ALLOW_S  6
+/** PMS_CORE1_MM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_CORE1_MM_HP_I2S1_ALLOW_M  (PMS_CORE1_MM_HP_I2S1_ALLOW_V << PMS_CORE1_MM_HP_I2S1_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2S1_ALLOW_S  7
+/** PMS_CORE1_MM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_CORE1_MM_HP_I2S2_ALLOW_M  (PMS_CORE1_MM_HP_I2S2_ALLOW_V << PMS_CORE1_MM_HP_I2S2_ALLOW_S)
+#define PMS_CORE1_MM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I2S2_ALLOW_S  8
+/** PMS_CORE1_MM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_CORE1_MM_HP_PCNT_ALLOW_M  (PMS_CORE1_MM_HP_PCNT_ALLOW_V << PMS_CORE1_MM_HP_PCNT_ALLOW_S)
+#define PMS_CORE1_MM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PCNT_ALLOW_S  9
+/** PMS_CORE1_MM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_CORE1_MM_HP_UART0_ALLOW_M  (PMS_CORE1_MM_HP_UART0_ALLOW_V << PMS_CORE1_MM_HP_UART0_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART0_ALLOW_S  10
+/** PMS_CORE1_MM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_CORE1_MM_HP_UART1_ALLOW_M  (PMS_CORE1_MM_HP_UART1_ALLOW_V << PMS_CORE1_MM_HP_UART1_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART1_ALLOW_S  11
+/** PMS_CORE1_MM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_CORE1_MM_HP_UART2_ALLOW_M  (PMS_CORE1_MM_HP_UART2_ALLOW_V << PMS_CORE1_MM_HP_UART2_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART2_ALLOW_S  12
+/** PMS_CORE1_MM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_CORE1_MM_HP_UART3_ALLOW_M  (PMS_CORE1_MM_HP_UART3_ALLOW_V << PMS_CORE1_MM_HP_UART3_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART3_ALLOW_S  13
+/** PMS_CORE1_MM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_CORE1_MM_HP_UART4_ALLOW_M  (PMS_CORE1_MM_HP_UART4_ALLOW_V << PMS_CORE1_MM_HP_UART4_ALLOW_S)
+#define PMS_CORE1_MM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UART4_ALLOW_S  14
+/** PMS_CORE1_MM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_CORE1_MM_HP_PARLIO_ALLOW_M  (PMS_CORE1_MM_HP_PARLIO_ALLOW_V << PMS_CORE1_MM_HP_PARLIO_ALLOW_S)
+#define PMS_CORE1_MM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_PARLIO_ALLOW_S  15
+/** PMS_CORE1_MM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_CORE1_MM_HP_GPSPI2_ALLOW_M  (PMS_CORE1_MM_HP_GPSPI2_ALLOW_V << PMS_CORE1_MM_HP_GPSPI2_ALLOW_S)
+#define PMS_CORE1_MM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GPSPI2_ALLOW_S  16
+/** PMS_CORE1_MM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_CORE1_MM_HP_GPSPI3_ALLOW_M  (PMS_CORE1_MM_HP_GPSPI3_ALLOW_V << PMS_CORE1_MM_HP_GPSPI3_ALLOW_S)
+#define PMS_CORE1_MM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GPSPI3_ALLOW_S  17
+/** PMS_CORE1_MM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP USB
+ *  Serial/JTAG Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_CORE1_MM_HP_USBDEVICE_ALLOW_M  (PMS_CORE1_MM_HP_USBDEVICE_ALLOW_V << PMS_CORE1_MM_HP_USBDEVICE_ALLOW_S)
+#define PMS_CORE1_MM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_CORE1_MM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_CORE1_MM_HP_LEDC_ALLOW_M  (PMS_CORE1_MM_HP_LEDC_ALLOW_V << PMS_CORE1_MM_HP_LEDC_ALLOW_S)
+#define PMS_CORE1_MM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_LEDC_ALLOW_S  19
+/** PMS_CORE1_MM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP ETM (Event
+ *  Task Matrix).
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_CORE1_MM_HP_ETM_ALLOW_M  (PMS_CORE1_MM_HP_ETM_ALLOW_V << PMS_CORE1_MM_HP_ETM_ALLOW_S)
+#define PMS_CORE1_MM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_ETM_ALLOW_S  21
+/** PMS_CORE1_MM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_CORE1_MM_HP_INTRMTX_ALLOW_M  (PMS_CORE1_MM_HP_INTRMTX_ALLOW_V << PMS_CORE1_MM_HP_INTRMTX_ALLOW_S)
+#define PMS_CORE1_MM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_INTRMTX_ALLOW_S  22
+/** PMS_CORE1_MM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_CORE1_MM_HP_TWAI0_ALLOW_M  (PMS_CORE1_MM_HP_TWAI0_ALLOW_V << PMS_CORE1_MM_HP_TWAI0_ALLOW_S)
+#define PMS_CORE1_MM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TWAI0_ALLOW_S  23
+/** PMS_CORE1_MM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_CORE1_MM_HP_TWAI1_ALLOW_M  (PMS_CORE1_MM_HP_TWAI1_ALLOW_V << PMS_CORE1_MM_HP_TWAI1_ALLOW_S)
+#define PMS_CORE1_MM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TWAI1_ALLOW_S  24
+/** PMS_CORE1_MM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_CORE1_MM_HP_TWAI2_ALLOW_M  (PMS_CORE1_MM_HP_TWAI2_ALLOW_V << PMS_CORE1_MM_HP_TWAI2_ALLOW_S)
+#define PMS_CORE1_MM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_TWAI2_ALLOW_S  25
+/** PMS_CORE1_MM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I3C master
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_CORE1_MM_HP_I3C_MST_ALLOW_M  (PMS_CORE1_MM_HP_I3C_MST_ALLOW_V << PMS_CORE1_MM_HP_I3C_MST_ALLOW_S)
+#define PMS_CORE1_MM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I3C_MST_ALLOW_S  26
+/** PMS_CORE1_MM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_CORE1_MM_HP_I3C_SLV_ALLOW_M  (PMS_CORE1_MM_HP_I3C_SLV_ALLOW_V << PMS_CORE1_MM_HP_I3C_SLV_ALLOW_S)
+#define PMS_CORE1_MM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_CORE1_MM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_CORE1_MM_HP_LCDCAM_ALLOW_M  (PMS_CORE1_MM_HP_LCDCAM_ALLOW_V << PMS_CORE1_MM_HP_LCDCAM_ALLOW_S)
+#define PMS_CORE1_MM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_LCDCAM_ALLOW_S  28
+/** PMS_CORE1_MM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_CORE1_MM_HP_ADC_ALLOW_M  (PMS_CORE1_MM_HP_ADC_ALLOW_V << PMS_CORE1_MM_HP_ADC_ALLOW_S)
+#define PMS_CORE1_MM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_ADC_ALLOW_S  30
+/** PMS_CORE1_MM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_CORE1_MM_HP_UHCI_ALLOW_M  (PMS_CORE1_MM_HP_UHCI_ALLOW_V << PMS_CORE1_MM_HP_UHCI_ALLOW_S)
+#define PMS_CORE1_MM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_UHCI_ALLOW_S  31
+
+/** PMS_CORE1_MM_HP_PERI_PMS_REG3_REG register
+ *  Permission control register3 for HP CPU1 in machine mode
+ */
+#define PMS_CORE1_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x34)
+/** PMS_CORE1_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP GPIO Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_CORE1_MM_HP_GPIO_ALLOW_M  (PMS_CORE1_MM_HP_GPIO_ALLOW_V << PMS_CORE1_MM_HP_GPIO_ALLOW_S)
+#define PMS_CORE1_MM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_GPIO_ALLOW_S  0
+/** PMS_CORE1_MM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_CORE1_MM_HP_IOMUX_ALLOW_M  (PMS_CORE1_MM_HP_IOMUX_ALLOW_V << PMS_CORE1_MM_HP_IOMUX_ALLOW_S)
+#define PMS_CORE1_MM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_IOMUX_ALLOW_S  1
+/** PMS_CORE1_MM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP system
+ *  timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_CORE1_MM_HP_SYSTIMER_ALLOW_M  (PMS_CORE1_MM_HP_SYSTIMER_ALLOW_V << PMS_CORE1_MM_HP_SYSTIMER_ALLOW_S)
+#define PMS_CORE1_MM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_CORE1_MM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_CORE1_MM_HP_SYS_REG_ALLOW_M  (PMS_CORE1_MM_HP_SYS_REG_ALLOW_V << PMS_CORE1_MM_HP_SYS_REG_ALLOW_S)
+#define PMS_CORE1_MM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_SYS_REG_ALLOW_S  3
+/** PMS_CORE1_MM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in machine mode has permission to access HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_MM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_CORE1_MM_HP_CLKRST_ALLOW_M  (PMS_CORE1_MM_HP_CLKRST_ALLOW_V << PMS_CORE1_MM_HP_CLKRST_ALLOW_S)
+#define PMS_CORE1_MM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_CORE1_MM_HP_CLKRST_ALLOW_S  4
+
+/** PMS_CORE1_UM_HP_PERI_PMS_REG0_REG register
+ *  Permission control register0 for HP CPU1 in user mode
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x38)
+/** PMS_CORE1_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access external RAM
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_PSRAM_ALLOW    (BIT(0))
+#define PMS_CORE1_UM_PSRAM_ALLOW_M  (PMS_CORE1_UM_PSRAM_ALLOW_V << PMS_CORE1_UM_PSRAM_ALLOW_S)
+#define PMS_CORE1_UM_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_PSRAM_ALLOW_S  0
+/** PMS_CORE1_UM_FLASH_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access external flash
+ *  without going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_FLASH_ALLOW    (BIT(1))
+#define PMS_CORE1_UM_FLASH_ALLOW_M  (PMS_CORE1_UM_FLASH_ALLOW_V << PMS_CORE1_UM_FLASH_ALLOW_S)
+#define PMS_CORE1_UM_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_FLASH_ALLOW_S  1
+/** PMS_CORE1_UM_L2MEM_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP L2MEM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_L2MEM_ALLOW    (BIT(2))
+#define PMS_CORE1_UM_L2MEM_ALLOW_M  (PMS_CORE1_UM_L2MEM_ALLOW_V << PMS_CORE1_UM_L2MEM_ALLOW_S)
+#define PMS_CORE1_UM_L2MEM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_L2MEM_ALLOW_S  2
+/** PMS_CORE1_UM_L2ROM_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP ROM without
+ *  going through cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_L2ROM_ALLOW    (BIT(3))
+#define PMS_CORE1_UM_L2ROM_ALLOW_M  (PMS_CORE1_UM_L2ROM_ALLOW_V << PMS_CORE1_UM_L2ROM_ALLOW_S)
+#define PMS_CORE1_UM_L2ROM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_L2ROM_ALLOW_S  3
+/** PMS_CORE1_UM_TRACE0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access TRACE0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_TRACE0_ALLOW    (BIT(6))
+#define PMS_CORE1_UM_TRACE0_ALLOW_M  (PMS_CORE1_UM_TRACE0_ALLOW_V << PMS_CORE1_UM_TRACE0_ALLOW_S)
+#define PMS_CORE1_UM_TRACE0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_TRACE0_ALLOW_S  6
+/** PMS_CORE1_UM_TRACE1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access TRACE1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_TRACE1_ALLOW    (BIT(7))
+#define PMS_CORE1_UM_TRACE1_ALLOW_M  (PMS_CORE1_UM_TRACE1_ALLOW_V << PMS_CORE1_UM_TRACE1_ALLOW_S)
+#define PMS_CORE1_UM_TRACE1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_TRACE1_ALLOW_S  7
+/** PMS_CORE1_UM_CPU_BUS_MON_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access CPU bus monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_CPU_BUS_MON_ALLOW    (BIT(8))
+#define PMS_CORE1_UM_CPU_BUS_MON_ALLOW_M  (PMS_CORE1_UM_CPU_BUS_MON_ALLOW_V << PMS_CORE1_UM_CPU_BUS_MON_ALLOW_S)
+#define PMS_CORE1_UM_CPU_BUS_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_CPU_BUS_MON_ALLOW_S  8
+/** PMS_CORE1_UM_L2MEM_MON_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access L2MEM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_L2MEM_MON_ALLOW    (BIT(9))
+#define PMS_CORE1_UM_L2MEM_MON_ALLOW_M  (PMS_CORE1_UM_L2MEM_MON_ALLOW_V << PMS_CORE1_UM_L2MEM_MON_ALLOW_S)
+#define PMS_CORE1_UM_L2MEM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_L2MEM_MON_ALLOW_S  9
+/** PMS_CORE1_UM_SPM_MON_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access SPM monitor.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_SPM_MON_ALLOW    (BIT(10))
+#define PMS_CORE1_UM_SPM_MON_ALLOW_M  (PMS_CORE1_UM_SPM_MON_ALLOW_V << PMS_CORE1_UM_SPM_MON_ALLOW_S)
+#define PMS_CORE1_UM_SPM_MON_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_SPM_MON_ALLOW_S  10
+/** PMS_CORE1_UM_CACHE_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access cache.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_CACHE_ALLOW    (BIT(11))
+#define PMS_CORE1_UM_CACHE_ALLOW_M  (PMS_CORE1_UM_CACHE_ALLOW_V << PMS_CORE1_UM_CACHE_ALLOW_S)
+#define PMS_CORE1_UM_CACHE_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_CACHE_ALLOW_S  11
+
+/** PMS_CORE1_UM_HP_PERI_PMS_REG1_REG register
+ *  Permission control register1 for HP CPU1 in user mode
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x3c)
+/** PMS_CORE1_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP high-speed USB
+ *  2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USBOTG_ALLOW    (BIT(0))
+#define PMS_CORE1_UM_HP_USBOTG_ALLOW_M  (PMS_CORE1_UM_HP_USBOTG_ALLOW_V << PMS_CORE1_UM_HP_USBOTG_ALLOW_S)
+#define PMS_CORE1_UM_HP_USBOTG_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USBOTG_ALLOW_S  0
+/** PMS_CORE1_UM_HP_USBOTG11_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP full-speed USB
+ *  2.0 OTG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USBOTG11_ALLOW    (BIT(1))
+#define PMS_CORE1_UM_HP_USBOTG11_ALLOW_M  (PMS_CORE1_UM_HP_USBOTG11_ALLOW_V << PMS_CORE1_UM_HP_USBOTG11_ALLOW_S)
+#define PMS_CORE1_UM_HP_USBOTG11_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USBOTG11_ALLOW_S  1
+/** PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP full-speed USB
+ *  2.0 OTG's wrap.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW    (BIT(2))
+#define PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_M  (PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V << PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S)
+#define PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USBOTG11_WRAP_ALLOW_S  2
+/** PMS_CORE1_UM_HP_GDMA_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP DW-GDMA.
+ *  0: Not allowed
+ *  1: Allowed
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GDMA_ALLOW    (BIT(3))
+#define PMS_CORE1_UM_HP_GDMA_ALLOW_M  (PMS_CORE1_UM_HP_GDMA_ALLOW_V << PMS_CORE1_UM_HP_GDMA_ALLOW_S)
+#define PMS_CORE1_UM_HP_GDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GDMA_ALLOW_S  3
+/** PMS_CORE1_UM_HP_SDMMC_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP SDMMC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_SDMMC_ALLOW    (BIT(5))
+#define PMS_CORE1_UM_HP_SDMMC_ALLOW_M  (PMS_CORE1_UM_HP_SDMMC_ALLOW_V << PMS_CORE1_UM_HP_SDMMC_ALLOW_S)
+#define PMS_CORE1_UM_HP_SDMMC_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_SDMMC_ALLOW_S  5
+/** PMS_CORE1_UM_HP_AHB_PDMA_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access GDMA-AHB.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_AHB_PDMA_ALLOW    (BIT(6))
+#define PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_M  (PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_V << PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_S)
+#define PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_AHB_PDMA_ALLOW_S  6
+/** PMS_CORE1_UM_HP_JPEG_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP JPEG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_JPEG_ALLOW    (BIT(7))
+#define PMS_CORE1_UM_HP_JPEG_ALLOW_M  (PMS_CORE1_UM_HP_JPEG_ALLOW_V << PMS_CORE1_UM_HP_JPEG_ALLOW_S)
+#define PMS_CORE1_UM_HP_JPEG_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_JPEG_ALLOW_S  7
+/** PMS_CORE1_UM_HP_PPA_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PPA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PPA_ALLOW    (BIT(8))
+#define PMS_CORE1_UM_HP_PPA_ALLOW_M  (PMS_CORE1_UM_HP_PPA_ALLOW_V << PMS_CORE1_UM_HP_PPA_ALLOW_S)
+#define PMS_CORE1_UM_HP_PPA_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PPA_ALLOW_S  8
+/** PMS_CORE1_UM_HP_DMA2D_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_DMA2D_ALLOW    (BIT(9))
+#define PMS_CORE1_UM_HP_DMA2D_ALLOW_M  (PMS_CORE1_UM_HP_DMA2D_ALLOW_V << PMS_CORE1_UM_HP_DMA2D_ALLOW_S)
+#define PMS_CORE1_UM_HP_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_DMA2D_ALLOW_S  9
+/** PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP key manager.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW    (BIT(10))
+#define PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_M  (PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_V << PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_S)
+#define PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_KEY_MANAGER_ALLOW_S  10
+/** PMS_CORE1_UM_HP_AXI_PDMA_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP GDMA-AXI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_AXI_PDMA_ALLOW    (BIT(11))
+#define PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_M  (PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_V << PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_S)
+#define PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_AXI_PDMA_ALLOW_S  11
+/** PMS_CORE1_UM_HP_FLASH_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP flash MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_FLASH_ALLOW    (BIT(12))
+#define PMS_CORE1_UM_HP_FLASH_ALLOW_M  (PMS_CORE1_UM_HP_FLASH_ALLOW_V << PMS_CORE1_UM_HP_FLASH_ALLOW_S)
+#define PMS_CORE1_UM_HP_FLASH_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_FLASH_ALLOW_S  12
+/** PMS_CORE1_UM_HP_PSRAM_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PSRAM MSPI
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PSRAM_ALLOW    (BIT(13))
+#define PMS_CORE1_UM_HP_PSRAM_ALLOW_M  (PMS_CORE1_UM_HP_PSRAM_ALLOW_V << PMS_CORE1_UM_HP_PSRAM_ALLOW_S)
+#define PMS_CORE1_UM_HP_PSRAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PSRAM_ALLOW_S  13
+/** PMS_CORE1_UM_HP_CRYPTO_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP CRYPTO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_CRYPTO_ALLOW    (BIT(14))
+#define PMS_CORE1_UM_HP_CRYPTO_ALLOW_M  (PMS_CORE1_UM_HP_CRYPTO_ALLOW_V << PMS_CORE1_UM_HP_CRYPTO_ALLOW_S)
+#define PMS_CORE1_UM_HP_CRYPTO_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_CRYPTO_ALLOW_S  14
+/** PMS_CORE1_UM_HP_GMAC_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP EMAC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GMAC_ALLOW    (BIT(15))
+#define PMS_CORE1_UM_HP_GMAC_ALLOW_M  (PMS_CORE1_UM_HP_GMAC_ALLOW_V << PMS_CORE1_UM_HP_GMAC_ALLOW_S)
+#define PMS_CORE1_UM_HP_GMAC_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GMAC_ALLOW_S  15
+/** PMS_CORE1_UM_HP_USB_PHY_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP high-speed USB
+ *  2.0 OTG PHY.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USB_PHY_ALLOW    (BIT(16))
+#define PMS_CORE1_UM_HP_USB_PHY_ALLOW_M  (PMS_CORE1_UM_HP_USB_PHY_ALLOW_V << PMS_CORE1_UM_HP_USB_PHY_ALLOW_S)
+#define PMS_CORE1_UM_HP_USB_PHY_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USB_PHY_ALLOW_S  16
+/** PMS_CORE1_UM_HP_PVT_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PVT.
+ *  0: Not allowed
+ *  1: Allow
+ */
+#define PMS_CORE1_UM_HP_PVT_ALLOW    (BIT(17))
+#define PMS_CORE1_UM_HP_PVT_ALLOW_M  (PMS_CORE1_UM_HP_PVT_ALLOW_V << PMS_CORE1_UM_HP_PVT_ALLOW_S)
+#define PMS_CORE1_UM_HP_PVT_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PVT_ALLOW_S  17
+/** PMS_CORE1_UM_HP_CSI_HOST_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP MIPI CSI host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_CSI_HOST_ALLOW    (BIT(18))
+#define PMS_CORE1_UM_HP_CSI_HOST_ALLOW_M  (PMS_CORE1_UM_HP_CSI_HOST_ALLOW_V << PMS_CORE1_UM_HP_CSI_HOST_ALLOW_S)
+#define PMS_CORE1_UM_HP_CSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_CSI_HOST_ALLOW_S  18
+/** PMS_CORE1_UM_HP_DSI_HOST_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP MIPI DSI host.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_DSI_HOST_ALLOW    (BIT(19))
+#define PMS_CORE1_UM_HP_DSI_HOST_ALLOW_M  (PMS_CORE1_UM_HP_DSI_HOST_ALLOW_V << PMS_CORE1_UM_HP_DSI_HOST_ALLOW_S)
+#define PMS_CORE1_UM_HP_DSI_HOST_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_DSI_HOST_ALLOW_S  19
+/** PMS_CORE1_UM_HP_ISP_ALLOW : R/W; bitpos: [20]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP ISP.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_ISP_ALLOW    (BIT(20))
+#define PMS_CORE1_UM_HP_ISP_ALLOW_M  (PMS_CORE1_UM_HP_ISP_ALLOW_V << PMS_CORE1_UM_HP_ISP_ALLOW_S)
+#define PMS_CORE1_UM_HP_ISP_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_ISP_ALLOW_S  20
+/** PMS_CORE1_UM_HP_H264_CORE_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP H264 Encoder.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_H264_CORE_ALLOW    (BIT(21))
+#define PMS_CORE1_UM_HP_H264_CORE_ALLOW_M  (PMS_CORE1_UM_HP_H264_CORE_ALLOW_V << PMS_CORE1_UM_HP_H264_CORE_ALLOW_S)
+#define PMS_CORE1_UM_HP_H264_CORE_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_H264_CORE_ALLOW_S  21
+/** PMS_CORE1_UM_HP_RMT_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP RMT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_RMT_ALLOW    (BIT(22))
+#define PMS_CORE1_UM_HP_RMT_ALLOW_M  (PMS_CORE1_UM_HP_RMT_ALLOW_V << PMS_CORE1_UM_HP_RMT_ALLOW_S)
+#define PMS_CORE1_UM_HP_RMT_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_RMT_ALLOW_S  22
+/** PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP bit scrambler.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW    (BIT(23))
+#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_M  (PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_V << PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_S)
+#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_BITSRAMBLER_ALLOW_S  23
+/** PMS_CORE1_UM_HP_AXI_ICM_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP AXI ICM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_AXI_ICM_ALLOW    (BIT(24))
+#define PMS_CORE1_UM_HP_AXI_ICM_ALLOW_M  (PMS_CORE1_UM_HP_AXI_ICM_ALLOW_V << PMS_CORE1_UM_HP_AXI_ICM_ALLOW_S)
+#define PMS_CORE1_UM_HP_AXI_ICM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_AXI_ICM_ALLOW_S  24
+/** PMS_CORE1_UM_HP_PERI_PMS_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_ALLOW    (BIT(25))
+#define PMS_CORE1_UM_HP_PERI_PMS_ALLOW_M  (PMS_CORE1_UM_HP_PERI_PMS_ALLOW_V << PMS_CORE1_UM_HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE1_UM_HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PERI_PMS_ALLOW_S  25
+/** PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access
+ *  LP2HP_PERI_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW    (BIT(26))
+#define PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_M  (PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V << PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S)
+#define PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_LP2HP_PERI_PMS_ALLOW_S  26
+/** PMS_CORE1_UM_DMA_PMS_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP_DMA_PMS_REG.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_DMA_PMS_ALLOW    (BIT(27))
+#define PMS_CORE1_UM_DMA_PMS_ALLOW_M  (PMS_CORE1_UM_DMA_PMS_ALLOW_V << PMS_CORE1_UM_DMA_PMS_ALLOW_S)
+#define PMS_CORE1_UM_DMA_PMS_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_DMA_PMS_ALLOW_S  27
+/** PMS_CORE1_UM_HP_H264_DMA2D_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access 2D-DMA.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW    (BIT(28))
+#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_M  (PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_V << PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_S)
+#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_H264_DMA2D_ALLOW_S  28
+
+/** PMS_CORE1_UM_HP_PERI_PMS_REG2_REG register
+ *  Permission control register2 for HP CPU1 in user mode
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x40)
+/** PMS_CORE1_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP MCPWM0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_MCPWM0_ALLOW    (BIT(0))
+#define PMS_CORE1_UM_HP_MCPWM0_ALLOW_M  (PMS_CORE1_UM_HP_MCPWM0_ALLOW_V << PMS_CORE1_UM_HP_MCPWM0_ALLOW_S)
+#define PMS_CORE1_UM_HP_MCPWM0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_MCPWM0_ALLOW_S  0
+/** PMS_CORE1_UM_HP_MCPWM1_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP MCPWM1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_MCPWM1_ALLOW    (BIT(1))
+#define PMS_CORE1_UM_HP_MCPWM1_ALLOW_M  (PMS_CORE1_UM_HP_MCPWM1_ALLOW_V << PMS_CORE1_UM_HP_MCPWM1_ALLOW_S)
+#define PMS_CORE1_UM_HP_MCPWM1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_MCPWM1_ALLOW_S  1
+/** PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP timer group0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW    (BIT(2))
+#define PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_M  (PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V << PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S)
+#define PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TIMER_GROUP0_ALLOW_S  2
+/** PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP timer group1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW    (BIT(3))
+#define PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_M  (PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V << PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S)
+#define PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TIMER_GROUP1_ALLOW_S  3
+/** PMS_CORE1_UM_HP_I2C0_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2C0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2C0_ALLOW    (BIT(4))
+#define PMS_CORE1_UM_HP_I2C0_ALLOW_M  (PMS_CORE1_UM_HP_I2C0_ALLOW_V << PMS_CORE1_UM_HP_I2C0_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2C0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2C0_ALLOW_S  4
+/** PMS_CORE1_UM_HP_I2C1_ALLOW : R/W; bitpos: [5]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2C1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2C1_ALLOW    (BIT(5))
+#define PMS_CORE1_UM_HP_I2C1_ALLOW_M  (PMS_CORE1_UM_HP_I2C1_ALLOW_V << PMS_CORE1_UM_HP_I2C1_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2C1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2C1_ALLOW_S  5
+/** PMS_CORE1_UM_HP_I2S0_ALLOW : R/W; bitpos: [6]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2S0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2S0_ALLOW    (BIT(6))
+#define PMS_CORE1_UM_HP_I2S0_ALLOW_M  (PMS_CORE1_UM_HP_I2S0_ALLOW_V << PMS_CORE1_UM_HP_I2S0_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2S0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2S0_ALLOW_S  6
+/** PMS_CORE1_UM_HP_I2S1_ALLOW : R/W; bitpos: [7]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2S1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2S1_ALLOW    (BIT(7))
+#define PMS_CORE1_UM_HP_I2S1_ALLOW_M  (PMS_CORE1_UM_HP_I2S1_ALLOW_V << PMS_CORE1_UM_HP_I2S1_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2S1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2S1_ALLOW_S  7
+/** PMS_CORE1_UM_HP_I2S2_ALLOW : R/W; bitpos: [8]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I2S2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I2S2_ALLOW    (BIT(8))
+#define PMS_CORE1_UM_HP_I2S2_ALLOW_M  (PMS_CORE1_UM_HP_I2S2_ALLOW_V << PMS_CORE1_UM_HP_I2S2_ALLOW_S)
+#define PMS_CORE1_UM_HP_I2S2_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I2S2_ALLOW_S  8
+/** PMS_CORE1_UM_HP_PCNT_ALLOW : R/W; bitpos: [9]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PCNT.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PCNT_ALLOW    (BIT(9))
+#define PMS_CORE1_UM_HP_PCNT_ALLOW_M  (PMS_CORE1_UM_HP_PCNT_ALLOW_V << PMS_CORE1_UM_HP_PCNT_ALLOW_S)
+#define PMS_CORE1_UM_HP_PCNT_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PCNT_ALLOW_S  9
+/** PMS_CORE1_UM_HP_UART0_ALLOW : R/W; bitpos: [10]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART0_ALLOW    (BIT(10))
+#define PMS_CORE1_UM_HP_UART0_ALLOW_M  (PMS_CORE1_UM_HP_UART0_ALLOW_V << PMS_CORE1_UM_HP_UART0_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART0_ALLOW_S  10
+/** PMS_CORE1_UM_HP_UART1_ALLOW : R/W; bitpos: [11]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART1_ALLOW    (BIT(11))
+#define PMS_CORE1_UM_HP_UART1_ALLOW_M  (PMS_CORE1_UM_HP_UART1_ALLOW_V << PMS_CORE1_UM_HP_UART1_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART1_ALLOW_S  11
+/** PMS_CORE1_UM_HP_UART2_ALLOW : R/W; bitpos: [12]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART2_ALLOW    (BIT(12))
+#define PMS_CORE1_UM_HP_UART2_ALLOW_M  (PMS_CORE1_UM_HP_UART2_ALLOW_V << PMS_CORE1_UM_HP_UART2_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART2_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART2_ALLOW_S  12
+/** PMS_CORE1_UM_HP_UART3_ALLOW : R/W; bitpos: [13]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART3_ALLOW    (BIT(13))
+#define PMS_CORE1_UM_HP_UART3_ALLOW_M  (PMS_CORE1_UM_HP_UART3_ALLOW_V << PMS_CORE1_UM_HP_UART3_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART3_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART3_ALLOW_S  13
+/** PMS_CORE1_UM_HP_UART4_ALLOW : R/W; bitpos: [14]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UART4.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UART4_ALLOW    (BIT(14))
+#define PMS_CORE1_UM_HP_UART4_ALLOW_M  (PMS_CORE1_UM_HP_UART4_ALLOW_V << PMS_CORE1_UM_HP_UART4_ALLOW_S)
+#define PMS_CORE1_UM_HP_UART4_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UART4_ALLOW_S  14
+/** PMS_CORE1_UM_HP_PARLIO_ALLOW : R/W; bitpos: [15]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP PARLIO.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_PARLIO_ALLOW    (BIT(15))
+#define PMS_CORE1_UM_HP_PARLIO_ALLOW_M  (PMS_CORE1_UM_HP_PARLIO_ALLOW_V << PMS_CORE1_UM_HP_PARLIO_ALLOW_S)
+#define PMS_CORE1_UM_HP_PARLIO_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_PARLIO_ALLOW_S  15
+/** PMS_CORE1_UM_HP_GPSPI2_ALLOW : R/W; bitpos: [16]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP GP-SPI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GPSPI2_ALLOW    (BIT(16))
+#define PMS_CORE1_UM_HP_GPSPI2_ALLOW_M  (PMS_CORE1_UM_HP_GPSPI2_ALLOW_V << PMS_CORE1_UM_HP_GPSPI2_ALLOW_S)
+#define PMS_CORE1_UM_HP_GPSPI2_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GPSPI2_ALLOW_S  16
+/** PMS_CORE1_UM_HP_GPSPI3_ALLOW : R/W; bitpos: [17]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP GP-SPI3.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GPSPI3_ALLOW    (BIT(17))
+#define PMS_CORE1_UM_HP_GPSPI3_ALLOW_M  (PMS_CORE1_UM_HP_GPSPI3_ALLOW_V << PMS_CORE1_UM_HP_GPSPI3_ALLOW_S)
+#define PMS_CORE1_UM_HP_GPSPI3_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GPSPI3_ALLOW_S  17
+/** PMS_CORE1_UM_HP_USBDEVICE_ALLOW : R/W; bitpos: [18]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP USB/Serial JTAG
+ *  Controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_USBDEVICE_ALLOW    (BIT(18))
+#define PMS_CORE1_UM_HP_USBDEVICE_ALLOW_M  (PMS_CORE1_UM_HP_USBDEVICE_ALLOW_V << PMS_CORE1_UM_HP_USBDEVICE_ALLOW_S)
+#define PMS_CORE1_UM_HP_USBDEVICE_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_USBDEVICE_ALLOW_S  18
+/** PMS_CORE1_UM_HP_LEDC_ALLOW : R/W; bitpos: [19]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP LEDC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_LEDC_ALLOW    (BIT(19))
+#define PMS_CORE1_UM_HP_LEDC_ALLOW_M  (PMS_CORE1_UM_HP_LEDC_ALLOW_V << PMS_CORE1_UM_HP_LEDC_ALLOW_S)
+#define PMS_CORE1_UM_HP_LEDC_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_LEDC_ALLOW_S  19
+/** PMS_CORE1_UM_HP_ETM_ALLOW : R/W; bitpos: [21]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP ETM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_ETM_ALLOW    (BIT(21))
+#define PMS_CORE1_UM_HP_ETM_ALLOW_M  (PMS_CORE1_UM_HP_ETM_ALLOW_V << PMS_CORE1_UM_HP_ETM_ALLOW_S)
+#define PMS_CORE1_UM_HP_ETM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_ETM_ALLOW_S  21
+/** PMS_CORE1_UM_HP_INTRMTX_ALLOW : R/W; bitpos: [22]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP interrupt
+ *  matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_INTRMTX_ALLOW    (BIT(22))
+#define PMS_CORE1_UM_HP_INTRMTX_ALLOW_M  (PMS_CORE1_UM_HP_INTRMTX_ALLOW_V << PMS_CORE1_UM_HP_INTRMTX_ALLOW_S)
+#define PMS_CORE1_UM_HP_INTRMTX_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_INTRMTX_ALLOW_S  22
+/** PMS_CORE1_UM_HP_TWAI0_ALLOW : R/W; bitpos: [23]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP TWAI0.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TWAI0_ALLOW    (BIT(23))
+#define PMS_CORE1_UM_HP_TWAI0_ALLOW_M  (PMS_CORE1_UM_HP_TWAI0_ALLOW_V << PMS_CORE1_UM_HP_TWAI0_ALLOW_S)
+#define PMS_CORE1_UM_HP_TWAI0_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TWAI0_ALLOW_S  23
+/** PMS_CORE1_UM_HP_TWAI1_ALLOW : R/W; bitpos: [24]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP TWAI1.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TWAI1_ALLOW    (BIT(24))
+#define PMS_CORE1_UM_HP_TWAI1_ALLOW_M  (PMS_CORE1_UM_HP_TWAI1_ALLOW_V << PMS_CORE1_UM_HP_TWAI1_ALLOW_S)
+#define PMS_CORE1_UM_HP_TWAI1_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TWAI1_ALLOW_S  24
+/** PMS_CORE1_UM_HP_TWAI2_ALLOW : R/W; bitpos: [25]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP TWAI2.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_TWAI2_ALLOW    (BIT(25))
+#define PMS_CORE1_UM_HP_TWAI2_ALLOW_M  (PMS_CORE1_UM_HP_TWAI2_ALLOW_V << PMS_CORE1_UM_HP_TWAI2_ALLOW_S)
+#define PMS_CORE1_UM_HP_TWAI2_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_TWAI2_ALLOW_S  25
+/** PMS_CORE1_UM_HP_I3C_MST_ALLOW : R/W; bitpos: [26]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I3C master
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I3C_MST_ALLOW    (BIT(26))
+#define PMS_CORE1_UM_HP_I3C_MST_ALLOW_M  (PMS_CORE1_UM_HP_I3C_MST_ALLOW_V << PMS_CORE1_UM_HP_I3C_MST_ALLOW_S)
+#define PMS_CORE1_UM_HP_I3C_MST_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I3C_MST_ALLOW_S  26
+/** PMS_CORE1_UM_HP_I3C_SLV_ALLOW : R/W; bitpos: [27]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP I3C slave
+ *  controller.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_I3C_SLV_ALLOW    (BIT(27))
+#define PMS_CORE1_UM_HP_I3C_SLV_ALLOW_M  (PMS_CORE1_UM_HP_I3C_SLV_ALLOW_V << PMS_CORE1_UM_HP_I3C_SLV_ALLOW_S)
+#define PMS_CORE1_UM_HP_I3C_SLV_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_I3C_SLV_ALLOW_S  27
+/** PMS_CORE1_UM_HP_LCDCAM_ALLOW : R/W; bitpos: [28]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP LCD_CAM.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_LCDCAM_ALLOW    (BIT(28))
+#define PMS_CORE1_UM_HP_LCDCAM_ALLOW_M  (PMS_CORE1_UM_HP_LCDCAM_ALLOW_V << PMS_CORE1_UM_HP_LCDCAM_ALLOW_S)
+#define PMS_CORE1_UM_HP_LCDCAM_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_LCDCAM_ALLOW_S  28
+/** PMS_CORE1_UM_HP_ADC_ALLOW : R/W; bitpos: [30]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP ADC.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_ADC_ALLOW    (BIT(30))
+#define PMS_CORE1_UM_HP_ADC_ALLOW_M  (PMS_CORE1_UM_HP_ADC_ALLOW_V << PMS_CORE1_UM_HP_ADC_ALLOW_S)
+#define PMS_CORE1_UM_HP_ADC_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_ADC_ALLOW_S  30
+/** PMS_CORE1_UM_HP_UHCI_ALLOW : R/W; bitpos: [31]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP UHCI.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_UHCI_ALLOW    (BIT(31))
+#define PMS_CORE1_UM_HP_UHCI_ALLOW_M  (PMS_CORE1_UM_HP_UHCI_ALLOW_V << PMS_CORE1_UM_HP_UHCI_ALLOW_S)
+#define PMS_CORE1_UM_HP_UHCI_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_UHCI_ALLOW_S  31
+
+/** PMS_CORE1_UM_HP_PERI_PMS_REG3_REG register
+ *  Permission control register3 for HP CPU1 in user mode
+ */
+#define PMS_CORE1_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x44)
+/** PMS_CORE1_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP GPIO Matrix.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_GPIO_ALLOW    (BIT(0))
+#define PMS_CORE1_UM_HP_GPIO_ALLOW_M  (PMS_CORE1_UM_HP_GPIO_ALLOW_V << PMS_CORE1_UM_HP_GPIO_ALLOW_S)
+#define PMS_CORE1_UM_HP_GPIO_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_GPIO_ALLOW_S  0
+/** PMS_CORE1_UM_HP_IOMUX_ALLOW : R/W; bitpos: [1]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP IO MUX.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_IOMUX_ALLOW    (BIT(1))
+#define PMS_CORE1_UM_HP_IOMUX_ALLOW_M  (PMS_CORE1_UM_HP_IOMUX_ALLOW_V << PMS_CORE1_UM_HP_IOMUX_ALLOW_S)
+#define PMS_CORE1_UM_HP_IOMUX_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_IOMUX_ALLOW_S  1
+/** PMS_CORE1_UM_HP_SYSTIMER_ALLOW : R/W; bitpos: [2]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP system timer.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_SYSTIMER_ALLOW    (BIT(2))
+#define PMS_CORE1_UM_HP_SYSTIMER_ALLOW_M  (PMS_CORE1_UM_HP_SYSTIMER_ALLOW_V << PMS_CORE1_UM_HP_SYSTIMER_ALLOW_S)
+#define PMS_CORE1_UM_HP_SYSTIMER_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_SYSTIMER_ALLOW_S  2
+/** PMS_CORE1_UM_HP_SYS_REG_ALLOW : R/W; bitpos: [3]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP system
+ *  register.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_SYS_REG_ALLOW    (BIT(3))
+#define PMS_CORE1_UM_HP_SYS_REG_ALLOW_M  (PMS_CORE1_UM_HP_SYS_REG_ALLOW_V << PMS_CORE1_UM_HP_SYS_REG_ALLOW_S)
+#define PMS_CORE1_UM_HP_SYS_REG_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_SYS_REG_ALLOW_S  3
+/** PMS_CORE1_UM_HP_CLKRST_ALLOW : R/W; bitpos: [4]; default: 1;
+ *  Configures whether HP CPU1 in user mode has permission to access HP_SYS_CLKRST.
+ *  0: Not allowed
+ *  1: Allowed
+ */
+#define PMS_CORE1_UM_HP_CLKRST_ALLOW    (BIT(4))
+#define PMS_CORE1_UM_HP_CLKRST_ALLOW_M  (PMS_CORE1_UM_HP_CLKRST_ALLOW_V << PMS_CORE1_UM_HP_CLKRST_ALLOW_S)
+#define PMS_CORE1_UM_HP_CLKRST_ALLOW_V  0x00000001U
+#define PMS_CORE1_UM_HP_CLKRST_ALLOW_S  4
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_struct.h
new file mode 100644
index 0000000000..64ad594c4c
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp_peri_pms_struct.h
@@ -0,0 +1,1490 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: TEE PMS DATE REG */
+/** Type of pms_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tee_date : R/W; bitpos: [31:0]; default: 2363943;
+         *  NA
+         */
+        uint32_t tee_date:32;
+    };
+    uint32_t val;
+} tee_pms_date_reg_t;
+
+
+/** Group: TEE PMS CLK EN REG */
+/** Type of pms_clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_pms_clk_en_reg_t;
+
+
+/** Group: TEE CORE0 MM PMS REG0 REG */
+/** Type of core0_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_mm_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_psram_allow:1;
+        /** reg_core0_mm_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_flash_allow:1;
+        /** reg_core0_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_l2mem_allow:1;
+        /** reg_core0_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_core0_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_trace0_allow:1;
+        /** reg_core0_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_trace1_allow:1;
+        /** reg_core0_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_cpu_bus_mon_allow:1;
+        /** reg_core0_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_l2mem_mon_allow:1;
+        /** reg_core0_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_tcm_mon_allow:1;
+        /** reg_core0_mm_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_core0_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE CORE0 MM PMS REG1 REG */
+/** Type of core0_mm_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usbotg_allow:1;
+        /** reg_core0_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usbotg11_allow:1;
+        /** reg_core0_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usbotg11_wrap_allow:1;
+        /** reg_core0_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gdma_allow:1;
+        /** reg_core0_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_regdma_allow:1;
+        /** reg_core0_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_sdmmc_allow:1;
+        /** reg_core0_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_ahb_pdma_allow:1;
+        /** reg_core0_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_jpeg_allow:1;
+        /** reg_core0_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_ppa_allow:1;
+        /** reg_core0_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_dma2d_allow:1;
+        /** reg_core0_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_key_manager_allow:1;
+        /** reg_core0_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_axi_pdma_allow:1;
+        /** reg_core0_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_flash_allow:1;
+        /** reg_core0_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_psram_allow:1;
+        /** reg_core0_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_crypto_allow:1;
+        /** reg_core0_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gmac_allow:1;
+        /** reg_core0_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usb_phy_allow:1;
+        /** reg_core0_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_pvt_allow:1;
+        /** reg_core0_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_csi_host_allow:1;
+        /** reg_core0_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_dsi_host_allow:1;
+        /** reg_core0_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_isp_allow:1;
+        /** reg_core0_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_h264_core_allow:1;
+        /** reg_core0_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_rmt_allow:1;
+        /** reg_core0_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_bitsrambler_allow:1;
+        /** reg_core0_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_axi_icm_allow:1;
+        /** reg_core0_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_peri_pms_allow:1;
+        /** reg_core0_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_lp2hp_peri_pms_allow:1;
+        /** reg_core0_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_dma_pms_allow:1;
+        /** reg_core0_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_h264_dma2d_allow:1;
+        /** reg_core0_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_core0_mm_pms_reg1_reg_t;
+
+
+/** Group: TEE CORE0 MM PMS REG2 REG */
+/** Type of core0_mm_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_mcpwm0_allow:1;
+        /** reg_core0_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_mcpwm1_allow:1;
+        /** reg_core0_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_timer_group0_allow:1;
+        /** reg_core0_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_timer_group1_allow:1;
+        /** reg_core0_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2c0_allow:1;
+        /** reg_core0_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2c1_allow:1;
+        /** reg_core0_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2s0_allow:1;
+        /** reg_core0_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2s1_allow:1;
+        /** reg_core0_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i2s2_allow:1;
+        /** reg_core0_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_pcnt_allow:1;
+        /** reg_core0_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart0_allow:1;
+        /** reg_core0_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart1_allow:1;
+        /** reg_core0_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart2_allow:1;
+        /** reg_core0_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart3_allow:1;
+        /** reg_core0_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uart4_allow:1;
+        /** reg_core0_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_parlio_allow:1;
+        /** reg_core0_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gpspi2_allow:1;
+        /** reg_core0_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gpspi3_allow:1;
+        /** reg_core0_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_usbdevice_allow:1;
+        /** reg_core0_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_core0_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_etm_allow:1;
+        /** reg_core0_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_intrmtx_allow:1;
+        /** reg_core0_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_twai0_allow:1;
+        /** reg_core0_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_twai1_allow:1;
+        /** reg_core0_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_twai2_allow:1;
+        /** reg_core0_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i3c_mst_allow:1;
+        /** reg_core0_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_i3c_slv_allow:1;
+        /** reg_core0_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_core0_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_adc_allow:1;
+        /** reg_core0_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_core0_mm_pms_reg2_reg_t;
+
+
+/** Group: TEE CORE0 MM PMS REG3 REG */
+/** Type of core0_mm_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_gpio_allow:1;
+        /** reg_core0_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_iomux_allow:1;
+        /** reg_core0_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_systimer_allow:1;
+        /** reg_core0_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_sys_reg_allow:1;
+        /** reg_core0_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_mm_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_core0_mm_pms_reg3_reg_t;
+
+
+/** Group: TEE CORE0 UM PMS REG0 REG */
+/** Type of core0_um_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_um_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_psram_allow:1;
+        /** reg_core0_um_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_flash_allow:1;
+        /** reg_core0_um_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_l2mem_allow:1;
+        /** reg_core0_um_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_core0_um_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_trace0_allow:1;
+        /** reg_core0_um_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_trace1_allow:1;
+        /** reg_core0_um_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_cpu_bus_mon_allow:1;
+        /** reg_core0_um_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_l2mem_mon_allow:1;
+        /** reg_core0_um_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_tcm_mon_allow:1;
+        /** reg_core0_um_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_core0_um_pms_reg0_reg_t;
+
+
+/** Group: TEE CORE0 UM PMS REG1 REG */
+/** Type of core0_um_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_um_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usbotg_allow:1;
+        /** reg_core0_um_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usbotg11_allow:1;
+        /** reg_core0_um_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usbotg11_wrap_allow:1;
+        /** reg_core0_um_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gdma_allow:1;
+        /** reg_core0_um_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_regdma_allow:1;
+        /** reg_core0_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_sdmmc_allow:1;
+        /** reg_core0_um_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_ahb_pdma_allow:1;
+        /** reg_core0_um_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_jpeg_allow:1;
+        /** reg_core0_um_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_ppa_allow:1;
+        /** reg_core0_um_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_dma2d_allow:1;
+        /** reg_core0_um_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_key_manager_allow:1;
+        /** reg_core0_um_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_axi_pdma_allow:1;
+        /** reg_core0_um_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_flash_allow:1;
+        /** reg_core0_um_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_psram_allow:1;
+        /** reg_core0_um_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_crypto_allow:1;
+        /** reg_core0_um_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gmac_allow:1;
+        /** reg_core0_um_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usb_phy_allow:1;
+        /** reg_core0_um_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_pvt_allow:1;
+        /** reg_core0_um_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_csi_host_allow:1;
+        /** reg_core0_um_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_dsi_host_allow:1;
+        /** reg_core0_um_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_isp_allow:1;
+        /** reg_core0_um_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_h264_core_allow:1;
+        /** reg_core0_um_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_rmt_allow:1;
+        /** reg_core0_um_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_bitsrambler_allow:1;
+        /** reg_core0_um_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_axi_icm_allow:1;
+        /** reg_core0_um_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_peri_pms_allow:1;
+        /** reg_core0_um_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_lp2hp_peri_pms_allow:1;
+        /** reg_core0_um_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_dma_pms_allow:1;
+        /** reg_core0_um_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_h264_dma2d_allow:1;
+        /** reg_core0_um_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_core0_um_pms_reg1_reg_t;
+
+
+/** Group: TEE CORE0 UM PMS REG2 REG */
+/** Type of core0_um_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_um_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_mcpwm0_allow:1;
+        /** reg_core0_um_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_mcpwm1_allow:1;
+        /** reg_core0_um_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_timer_group0_allow:1;
+        /** reg_core0_um_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_timer_group1_allow:1;
+        /** reg_core0_um_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2c0_allow:1;
+        /** reg_core0_um_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2c1_allow:1;
+        /** reg_core0_um_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2s0_allow:1;
+        /** reg_core0_um_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2s1_allow:1;
+        /** reg_core0_um_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i2s2_allow:1;
+        /** reg_core0_um_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_pcnt_allow:1;
+        /** reg_core0_um_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart0_allow:1;
+        /** reg_core0_um_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart1_allow:1;
+        /** reg_core0_um_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart2_allow:1;
+        /** reg_core0_um_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart3_allow:1;
+        /** reg_core0_um_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uart4_allow:1;
+        /** reg_core0_um_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_parlio_allow:1;
+        /** reg_core0_um_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gpspi2_allow:1;
+        /** reg_core0_um_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gpspi3_allow:1;
+        /** reg_core0_um_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_usbdevice_allow:1;
+        /** reg_core0_um_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_core0_um_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_etm_allow:1;
+        /** reg_core0_um_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_intrmtx_allow:1;
+        /** reg_core0_um_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_twai0_allow:1;
+        /** reg_core0_um_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_twai1_allow:1;
+        /** reg_core0_um_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_twai2_allow:1;
+        /** reg_core0_um_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i3c_mst_allow:1;
+        /** reg_core0_um_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_i3c_slv_allow:1;
+        /** reg_core0_um_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_core0_um_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_adc_allow:1;
+        /** reg_core0_um_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_core0_um_pms_reg2_reg_t;
+
+
+/** Group: TEE CORE0 UM PMS REG3 REG */
+/** Type of core0_um_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_um_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_gpio_allow:1;
+        /** reg_core0_um_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_iomux_allow:1;
+        /** reg_core0_um_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_systimer_allow:1;
+        /** reg_core0_um_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_sys_reg_allow:1;
+        /** reg_core0_um_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core0_um_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_core0_um_pms_reg3_reg_t;
+
+
+/** Group: TEE CORE1 MM PMS REG0 REG */
+/** Type of core1_mm_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_mm_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_psram_allow:1;
+        /** reg_core1_mm_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_flash_allow:1;
+        /** reg_core1_mm_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_l2mem_allow:1;
+        /** reg_core1_mm_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_core1_mm_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_trace0_allow:1;
+        /** reg_core1_mm_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_trace1_allow:1;
+        /** reg_core1_mm_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_cpu_bus_mon_allow:1;
+        /** reg_core1_mm_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_l2mem_mon_allow:1;
+        /** reg_core1_mm_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_tcm_mon_allow:1;
+        /** reg_core1_mm_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_core1_mm_pms_reg0_reg_t;
+
+
+/** Group: TEE CORE1 MM PMS REG1 REG */
+/** Type of core1_mm_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_mm_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usbotg_allow:1;
+        /** reg_core1_mm_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usbotg11_allow:1;
+        /** reg_core1_mm_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usbotg11_wrap_allow:1;
+        /** reg_core1_mm_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gdma_allow:1;
+        /** reg_core1_mm_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_regdma_allow:1;
+        /** reg_core1_mm_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_sdmmc_allow:1;
+        /** reg_core1_mm_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_ahb_pdma_allow:1;
+        /** reg_core1_mm_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_jpeg_allow:1;
+        /** reg_core1_mm_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_ppa_allow:1;
+        /** reg_core1_mm_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_dma2d_allow:1;
+        /** reg_core1_mm_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_key_manager_allow:1;
+        /** reg_core1_mm_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_axi_pdma_allow:1;
+        /** reg_core1_mm_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_flash_allow:1;
+        /** reg_core1_mm_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_psram_allow:1;
+        /** reg_core1_mm_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_crypto_allow:1;
+        /** reg_core1_mm_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gmac_allow:1;
+        /** reg_core1_mm_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usb_phy_allow:1;
+        /** reg_core1_mm_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_pvt_allow:1;
+        /** reg_core1_mm_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_csi_host_allow:1;
+        /** reg_core1_mm_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_dsi_host_allow:1;
+        /** reg_core1_mm_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_isp_allow:1;
+        /** reg_core1_mm_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_h264_core_allow:1;
+        /** reg_core1_mm_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_rmt_allow:1;
+        /** reg_core1_mm_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_bitsrambler_allow:1;
+        /** reg_core1_mm_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_axi_icm_allow:1;
+        /** reg_core1_mm_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_peri_pms_allow:1;
+        /** reg_core1_mm_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_lp2hp_peri_pms_allow:1;
+        /** reg_core1_mm_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_dma_pms_allow:1;
+        /** reg_core1_mm_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_h264_dma2d_allow:1;
+        /** reg_core1_mm_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_core1_mm_pms_reg1_reg_t;
+
+
+/** Group: TEE CORE1 MM PMS REG2 REG */
+/** Type of core1_mm_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_mm_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_mcpwm0_allow:1;
+        /** reg_core1_mm_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_mcpwm1_allow:1;
+        /** reg_core1_mm_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_timer_group0_allow:1;
+        /** reg_core1_mm_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_timer_group1_allow:1;
+        /** reg_core1_mm_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2c0_allow:1;
+        /** reg_core1_mm_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2c1_allow:1;
+        /** reg_core1_mm_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2s0_allow:1;
+        /** reg_core1_mm_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2s1_allow:1;
+        /** reg_core1_mm_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i2s2_allow:1;
+        /** reg_core1_mm_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_pcnt_allow:1;
+        /** reg_core1_mm_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart0_allow:1;
+        /** reg_core1_mm_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart1_allow:1;
+        /** reg_core1_mm_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart2_allow:1;
+        /** reg_core1_mm_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart3_allow:1;
+        /** reg_core1_mm_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uart4_allow:1;
+        /** reg_core1_mm_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_parlio_allow:1;
+        /** reg_core1_mm_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gpspi2_allow:1;
+        /** reg_core1_mm_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gpspi3_allow:1;
+        /** reg_core1_mm_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_usbdevice_allow:1;
+        /** reg_core1_mm_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_core1_mm_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_etm_allow:1;
+        /** reg_core1_mm_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_intrmtx_allow:1;
+        /** reg_core1_mm_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_twai0_allow:1;
+        /** reg_core1_mm_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_twai1_allow:1;
+        /** reg_core1_mm_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_twai2_allow:1;
+        /** reg_core1_mm_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i3c_mst_allow:1;
+        /** reg_core1_mm_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_i3c_slv_allow:1;
+        /** reg_core1_mm_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_core1_mm_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_adc_allow:1;
+        /** reg_core1_mm_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_core1_mm_pms_reg2_reg_t;
+
+
+/** Group: TEE CORE1 MM PMS REG3 REG */
+/** Type of core1_mm_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_mm_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_gpio_allow:1;
+        /** reg_core1_mm_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_iomux_allow:1;
+        /** reg_core1_mm_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_systimer_allow:1;
+        /** reg_core1_mm_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_sys_reg_allow:1;
+        /** reg_core1_mm_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_mm_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_core1_mm_pms_reg3_reg_t;
+
+
+/** Group: TEE CORE1 UM PMS REG0 REG */
+/** Type of core1_um_pms_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_um_psram_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_psram_allow:1;
+        /** reg_core1_um_flash_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_flash_allow:1;
+        /** reg_core1_um_l2mem_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_l2mem_allow:1;
+        /** reg_core1_um_l2rom_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_l2rom_allow:1;
+        uint32_t reserved_4:2;
+        /** reg_core1_um_trace0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_trace0_allow:1;
+        /** reg_core1_um_trace1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_trace1_allow:1;
+        /** reg_core1_um_cpu_bus_mon_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_cpu_bus_mon_allow:1;
+        /** reg_core1_um_l2mem_mon_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_l2mem_mon_allow:1;
+        /** reg_core1_um_tcm_mon_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_tcm_mon_allow:1;
+        /** reg_core1_um_cache_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_cache_allow:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} tee_core1_um_pms_reg0_reg_t;
+
+
+/** Group: TEE CORE1 UM PMS REG1 REG */
+/** Type of core1_um_pms_reg1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_um_hp_usbotg_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usbotg_allow:1;
+        /** reg_core1_um_hp_usbotg11_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usbotg11_allow:1;
+        /** reg_core1_um_hp_usbotg11_wrap_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usbotg11_wrap_allow:1;
+        /** reg_core1_um_hp_gdma_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gdma_allow:1;
+        /** reg_core1_um_hp_regdma_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_regdma_allow:1;
+        /** reg_core1_um_hp_sdmmc_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_sdmmc_allow:1;
+        /** reg_core1_um_hp_ahb_pdma_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_ahb_pdma_allow:1;
+        /** reg_core1_um_hp_jpeg_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_jpeg_allow:1;
+        /** reg_core1_um_hp_ppa_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_ppa_allow:1;
+        /** reg_core1_um_hp_dma2d_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_dma2d_allow:1;
+        /** reg_core1_um_hp_key_manager_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_key_manager_allow:1;
+        /** reg_core1_um_hp_axi_pdma_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_axi_pdma_allow:1;
+        /** reg_core1_um_hp_flash_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_flash_allow:1;
+        /** reg_core1_um_hp_psram_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_psram_allow:1;
+        /** reg_core1_um_hp_crypto_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_crypto_allow:1;
+        /** reg_core1_um_hp_gmac_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gmac_allow:1;
+        /** reg_core1_um_hp_usb_phy_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usb_phy_allow:1;
+        /** reg_core1_um_hp_pvt_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_pvt_allow:1;
+        /** reg_core1_um_hp_csi_host_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_csi_host_allow:1;
+        /** reg_core1_um_hp_dsi_host_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_dsi_host_allow:1;
+        /** reg_core1_um_hp_isp_allow : R/W; bitpos: [20]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_isp_allow:1;
+        /** reg_core1_um_hp_h264_core_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_h264_core_allow:1;
+        /** reg_core1_um_hp_rmt_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_rmt_allow:1;
+        /** reg_core1_um_hp_bitsrambler_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_bitsrambler_allow:1;
+        /** reg_core1_um_hp_axi_icm_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_axi_icm_allow:1;
+        /** reg_core1_um_hp_peri_pms_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_peri_pms_allow:1;
+        /** reg_core1_um_lp2hp_peri_pms_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_lp2hp_peri_pms_allow:1;
+        /** reg_core1_um_dma_pms_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_dma_pms_allow:1;
+        /** reg_core1_um_hp_h264_dma2d_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_h264_dma2d_allow:1;
+        /** reg_core1_um_axi_perf_mon_allow : R/W; bitpos: [29]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_axi_perf_mon_allow:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} tee_core1_um_pms_reg1_reg_t;
+
+
+/** Group: TEE CORE1 UM PMS REG2 REG */
+/** Type of core1_um_pms_reg2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_um_hp_mcpwm0_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_mcpwm0_allow:1;
+        /** reg_core1_um_hp_mcpwm1_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_mcpwm1_allow:1;
+        /** reg_core1_um_hp_timer_group0_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_timer_group0_allow:1;
+        /** reg_core1_um_hp_timer_group1_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_timer_group1_allow:1;
+        /** reg_core1_um_hp_i2c0_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2c0_allow:1;
+        /** reg_core1_um_hp_i2c1_allow : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2c1_allow:1;
+        /** reg_core1_um_hp_i2s0_allow : R/W; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2s0_allow:1;
+        /** reg_core1_um_hp_i2s1_allow : R/W; bitpos: [7]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2s1_allow:1;
+        /** reg_core1_um_hp_i2s2_allow : R/W; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i2s2_allow:1;
+        /** reg_core1_um_hp_pcnt_allow : R/W; bitpos: [9]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_pcnt_allow:1;
+        /** reg_core1_um_hp_uart0_allow : R/W; bitpos: [10]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart0_allow:1;
+        /** reg_core1_um_hp_uart1_allow : R/W; bitpos: [11]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart1_allow:1;
+        /** reg_core1_um_hp_uart2_allow : R/W; bitpos: [12]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart2_allow:1;
+        /** reg_core1_um_hp_uart3_allow : R/W; bitpos: [13]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart3_allow:1;
+        /** reg_core1_um_hp_uart4_allow : R/W; bitpos: [14]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uart4_allow:1;
+        /** reg_core1_um_hp_parlio_allow : R/W; bitpos: [15]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_parlio_allow:1;
+        /** reg_core1_um_hp_gpspi2_allow : R/W; bitpos: [16]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gpspi2_allow:1;
+        /** reg_core1_um_hp_gpspi3_allow : R/W; bitpos: [17]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gpspi3_allow:1;
+        /** reg_core1_um_hp_usbdevice_allow : R/W; bitpos: [18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_usbdevice_allow:1;
+        /** reg_core1_um_hp_ledc_allow : R/W; bitpos: [19]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_ledc_allow:1;
+        uint32_t reserved_20:1;
+        /** reg_core1_um_hp_etm_allow : R/W; bitpos: [21]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_etm_allow:1;
+        /** reg_core1_um_hp_intrmtx_allow : R/W; bitpos: [22]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_intrmtx_allow:1;
+        /** reg_core1_um_hp_twai0_allow : R/W; bitpos: [23]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_twai0_allow:1;
+        /** reg_core1_um_hp_twai1_allow : R/W; bitpos: [24]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_twai1_allow:1;
+        /** reg_core1_um_hp_twai2_allow : R/W; bitpos: [25]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_twai2_allow:1;
+        /** reg_core1_um_hp_i3c_mst_allow : R/W; bitpos: [26]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i3c_mst_allow:1;
+        /** reg_core1_um_hp_i3c_slv_allow : R/W; bitpos: [27]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_i3c_slv_allow:1;
+        /** reg_core1_um_hp_lcdcam_allow : R/W; bitpos: [28]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_lcdcam_allow:1;
+        uint32_t reserved_29:1;
+        /** reg_core1_um_hp_adc_allow : R/W; bitpos: [30]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_adc_allow:1;
+        /** reg_core1_um_hp_uhci_allow : R/W; bitpos: [31]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_uhci_allow:1;
+    };
+    uint32_t val;
+} tee_core1_um_pms_reg2_reg_t;
+
+
+/** Group: TEE CORE1 UM PMS REG3 REG */
+/** Type of core1_um_pms_reg3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core1_um_hp_gpio_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_gpio_allow:1;
+        /** reg_core1_um_hp_iomux_allow : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_iomux_allow:1;
+        /** reg_core1_um_hp_systimer_allow : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_systimer_allow:1;
+        /** reg_core1_um_hp_sys_reg_allow : R/W; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_sys_reg_allow:1;
+        /** reg_core1_um_hp_clkrst_allow : R/W; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_core1_um_hp_clkrst_allow:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} tee_core1_um_pms_reg3_reg_t;
+
+
+/** Group: TEE REGDMA PERI PMS REG */
+/** Type of regdma_peri_pms register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_regdma_peri_allow : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_regdma_peri_allow:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} tee_regdma_peri_pms_reg_t;
+
+
+typedef struct {
+    volatile tee_pms_date_reg_t pms_date;
+    volatile tee_pms_clk_en_reg_t pms_clk_en;
+    volatile tee_core0_mm_pms_reg0_reg_t core0_mm_pms_reg0;
+    volatile tee_core0_mm_pms_reg1_reg_t core0_mm_pms_reg1;
+    volatile tee_core0_mm_pms_reg2_reg_t core0_mm_pms_reg2;
+    volatile tee_core0_mm_pms_reg3_reg_t core0_mm_pms_reg3;
+    volatile tee_core0_um_pms_reg0_reg_t core0_um_pms_reg0;
+    volatile tee_core0_um_pms_reg1_reg_t core0_um_pms_reg1;
+    volatile tee_core0_um_pms_reg2_reg_t core0_um_pms_reg2;
+    volatile tee_core0_um_pms_reg3_reg_t core0_um_pms_reg3;
+    volatile tee_core1_mm_pms_reg0_reg_t core1_mm_pms_reg0;
+    volatile tee_core1_mm_pms_reg1_reg_t core1_mm_pms_reg1;
+    volatile tee_core1_mm_pms_reg2_reg_t core1_mm_pms_reg2;
+    volatile tee_core1_mm_pms_reg3_reg_t core1_mm_pms_reg3;
+    volatile tee_core1_um_pms_reg0_reg_t core1_um_pms_reg0;
+    volatile tee_core1_um_pms_reg1_reg_t core1_um_pms_reg1;
+    volatile tee_core1_um_pms_reg2_reg_t core1_um_pms_reg2;
+    volatile tee_core1_um_pms_reg3_reg_t core1_um_pms_reg3;
+    volatile tee_regdma_peri_pms_reg_t regdma_peri_pms;
+} tee_dev_t;
+
+extern tee_dev_t HP_PERI_PMS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(tee_dev_t) == 0x4c, "Invalid size of tee_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp_sys_clkrst_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/hp_sys_clkrst_reg.h
new file mode 100644
index 0000000000..571ef41a2e
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp_sys_clkrst_reg.h
@@ -0,0 +1,4399 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_SYS_CLKRST_CLK_EN0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_CLK_EN0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x0)
+/** HP_SYS_CLKRST_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CLK_EN_M  (HP_SYS_CLKRST_REG_CLK_EN_V << HP_SYS_CLKRST_REG_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x4)
+/** HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM : R/W; bitpos: [3:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM    0x0000000FU
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_M  (HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_V << HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_S)
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_S  0
+/** HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE : WT; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE    (BIT(4))
+#define HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_M  (HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_V << HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_S)
+#define HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SOC_CLK_DIV_UPDATE_S  4
+/** HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM : R/W; bitpos: [12:5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_S  5
+/** HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR : R/W; bitpos: [20:13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_S  13
+/** HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR : R/W; bitpos: [28:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_S  21
+
+/** HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ROOT_CLK_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x8)
+/** HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM : R/W; bitpos: [31:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_S  24
+
+/** HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ROOT_CLK_CTRL2_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc)
+/** HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_S  0
+/** HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_S  8
+/** HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR : R/W; bitpos: [31:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_S  24
+
+/** HP_SYS_CLKRST_ROOT_CLK_CTRL3_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ROOT_CLK_CTRL3_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x10)
+/** HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_S  0
+
+/** HP_SYS_CLKRST_SOC_CLK_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_SOC_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x14)
+/** HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_V << HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_V << HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN : R/W; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN : R/W; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN    (BIT(12))
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_S  12
+/** HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_S  13
+/** HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_EN_S  17
+/** HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_S  23
+/** HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_SYS_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEM_SYS_CLK_EN_S  26
+/** HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN : R/W; bitpos: [29]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_SOC_CLK_CTRL1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_SOC_CLK_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x18)
+/** HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CSI_BRG_SYS_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CSI_HOST_SYS_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN    (BIT(12))
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_S  12
+/** HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_S  13
+/** HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_USB_OTG20_SYS_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_S  17
+/** HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART4_SYS_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_S  23
+/** HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ETM_SYS_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_S  26
+/** HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN : R/W; bitpos: [29]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_H264_SYS_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_H264_SYS_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_H264_SYS_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_SOC_CLK_CTRL2_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_SOC_CLK_CTRL2_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1c)
+/** HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_V << HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_V << HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_ICM_APB_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_V << HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_ADC_APB_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_APB_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_V << HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ADC_APB_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_UART0_APB_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_UART1_APB_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_UART2_APB_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_UART3_APB_CLK_EN : R/W; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_UART4_APB_CLK_EN : R/W; bitpos: [11]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_APB_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART4_APB_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN    (BIT(12))
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_S  12
+/** HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_S  13
+/** HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_APB_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I3C_MST_APB_CLK_EN_S  17
+/** HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I3C_SLV_APB_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_V << HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_S  23
+/** HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI2_APB_CLK_EN_S  26
+/** HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN : R/W; bitpos: [29]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_V << HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_V << HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_SOC_CLK_CTRL3_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_SOC_CLK_CTRL3_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x20)
+/** HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_V << HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_V << HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_ETM_APB_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_V << HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_V << HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_V << HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_EN_S  4
+
+/** HP_SYS_CLKRST_REF_CLK_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REF_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x24)
+/** HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 9;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 19;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM : R/W; bitpos: [31:24]; default: 2;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_S  24
+
+/** HP_SYS_CLKRST_REF_CLK_CTRL1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REF_CLK_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x28)
+/** HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 5;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 23;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_TM_400M_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_400M_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_TM_400M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_400M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_400M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_400M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_400M_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_TM_200M_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_200M_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_TM_200M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_200M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_200M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_200M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_200M_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_TM_100M_CLK_EN : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_100M_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_TM_100M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_100M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_100M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_100M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_100M_CLK_EN_S  26
+/** HP_SYS_CLKRST_REG_REF_50M_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_50M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_50M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_REF_25M_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_25M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_25M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_TM_480M_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_480M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_480M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_REF_240M_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_240M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_240M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_TM_240M_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_240M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_240M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_REF_CLK_CTRL2_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REF_CLK_CTRL2_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x2c)
+/** HP_SYS_CLKRST_REG_REF_160M_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_160M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_160M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TM_160M_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_160M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_160M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_REF_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_120M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_120M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_TM_120M_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_120M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_120M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_REF_80M_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_80M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_80M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_TM_80M_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_80M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_80M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_TM_60M_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_60M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_60M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_TM_48M_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_48M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_48M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_REF_20M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_20M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_20M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_TM_20M_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_20M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_20M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN_S  9
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL00_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL00_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x30)
+/** HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_M  (HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_V << HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_M  (HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_V << HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM : R/W; bitpos: [11:4]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_S  4
+/** HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL : R/W; bitpos: [13:12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_S  12
+/** HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_M  (HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_V << HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PAD_EMAC_REF_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL : R/W; bitpos: [26:25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_SRC_SEL_S  25
+/** HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_RMII_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL    (BIT(28))
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_SRC_SEL_S  28
+/** HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_EN_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL01_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL01_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x34)
+/** HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_EMAC_RX_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL    (BIT(8))
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_SRC_SEL_S  8
+/** HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM : R/W; bitpos: [17:10]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_EMAC_TX_CLK_DIV_NUM_S  10
+/** HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL    (BIT(18))
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_SRC_SEL_S  18
+/** HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_PTP_REF_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED0_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_UNUSED1_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_SDIO_HS_MODE : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE    (BIT(22))
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE_M  (HP_SYS_CLKRST_REG_SDIO_HS_MODE_V << HP_SYS_CLKRST_REG_SDIO_HS_MODE_S)
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE_S  22
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL    (BIT(23))
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_S  23
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_S  24
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL02_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL02_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x38)
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE : WT; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE    (BIT(8))
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_S  8
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L : R/W; bitpos: [12:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L    0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_S  9
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H : R/W; bitpos: [16:13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H    0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_S  13
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N : R/W; bitpos: [20:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N    0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_S  17
+/** HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL : R/W; bitpos: [22:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_S  21
+/** HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL : R/W; bitpos: [24:23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_S  23
+/** HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL : R/W; bitpos: [26:25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_S  25
+/** HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_S  29
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_S  30
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL03_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL03_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x3c)
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_S  1
+/** HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CLK_SRC_SEL_S  2
+/** HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_V << HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_CSI_DPHY_CFG_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_S  5
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_S  7
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL : R/W; bitpos: [18:16]; default:
+ *  0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL    0x00000007U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_V  0x00000007U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_SRC_SEL_S  16
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM : R/W; bitpos: [26:19]; default:
+ *  1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_DIV_NUM_S  19
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL10_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL10_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x40)
+/** HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_I2C0_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C0_CLK_EN_V << HP_SYS_CLKRST_REG_I2C0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM : R/W; bitpos: [9:2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_S  2
+/** HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR : R/W; bitpos: [17:10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_S  10
+/** HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR : R/W; bitpos: [25:18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_S  18
+/** HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL    (BIT(26))
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_S  26
+/** HP_SYS_CLKRST_REG_I2C1_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C1_CLK_EN_V << HP_SYS_CLKRST_REG_I2C1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN_S  27
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL11_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL11_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x44)
+/** HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL : R/W; bitpos: [26:25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_S  25
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL12_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL12_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x48)
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_N : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_S  0
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_X : R/W; bitpos: [16:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_S  8
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y : R/W; bitpos: [25:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_S  17
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL13_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL13_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x4c)
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_S  0
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1 : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1    (BIT(9))
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_S  9
+/** HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL : R/W; bitpos: [12:11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_S  11
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_N : R/W; bitpos: [20:13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_S  13
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_X : R/W; bitpos: [29:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_S  21
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL14_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL14_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x50)
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_S  0
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z : R/W; bitpos: [17:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_S  9
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1 : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1    (BIT(18))
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_S  18
+/** HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL    (BIT(19))
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_M  (HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_V << HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_S  19
+/** HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL : R/W; bitpos: [22:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_S  21
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_N : R/W; bitpos: [30:23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_S  23
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL15_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL15_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x54)
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_X : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_S  0
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y : R/W; bitpos: [17:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_S  9
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z : R/W; bitpos: [26:18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_S  18
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_S  27
+/** HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL16_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL16_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x58)
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_N : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_S  0
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_X : R/W; bitpos: [16:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_S  8
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y : R/W; bitpos: [25:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_S  17
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL17_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL17_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x5c)
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_S  0
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1 : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1    (BIT(9))
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_S  9
+/** HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL    (BIT(10))
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_M  (HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_V << HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_S  10
+/** HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL : R/W; bitpos: [13:12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S2_RX_CLK_SRC_SEL_S  12
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_N : R/W; bitpos: [21:14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_N_S  14
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_X : R/W; bitpos: [30:22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_X_S  22
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL18_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL18_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x60)
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Y_S  0
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z : R/W; bitpos: [17:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_Z_S  9
+/** HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1 : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1    (BIT(18))
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_RX_DIV_YN1_S  18
+/** HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S2_TX_CLK_SRC_SEL_S  20
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_N : R/W; bitpos: [29:22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_N_S  22
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL19_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL19_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x64)
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_X : R/W; bitpos: [8:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_X_S  0
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y : R/W; bitpos: [17:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Y_S  9
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z : R/W; bitpos: [26:18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_Z_S  18
+/** HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_TX_DIV_YN1_S  27
+/** HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL    (BIT(28))
+#define HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_M  (HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_V << HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S2_MST_CLK_SEL_S  28
+/** HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL : R/W; bitpos: [30:29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_S  29
+/** HP_SYS_CLKRST_REG_LCD_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN_M  (HP_SYS_CLKRST_REG_LCD_CLK_EN_V << HP_SYS_CLKRST_REG_LCD_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL110_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL110_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x68)
+/** HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART0_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN_M  (HP_SYS_CLKRST_REG_UART0_CLK_EN_V << HP_SYS_CLKRST_REG_UART0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL111_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL111_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x6c)
+/** HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART1_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN_M  (HP_SYS_CLKRST_REG_UART1_CLK_EN_V << HP_SYS_CLKRST_REG_UART1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL112_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL112_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x70)
+/** HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART2_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN_M  (HP_SYS_CLKRST_REG_UART2_CLK_EN_V << HP_SYS_CLKRST_REG_UART2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL113_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL113_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x74)
+/** HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART3_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN_M  (HP_SYS_CLKRST_REG_UART3_CLK_EN_V << HP_SYS_CLKRST_REG_UART3_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL114_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL114_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x78)
+/** HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART4_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_UART4_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_CLK_EN    (BIT(26))
+#define HP_SYS_CLKRST_REG_UART4_CLK_EN_M  (HP_SYS_CLKRST_REG_UART4_CLK_EN_V << HP_SYS_CLKRST_REG_UART4_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART4_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART4_CLK_EN_S  26
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL115_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL115_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x7c)
+/** HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART4_SCLK_DIV_DENOMINATOR_S  16
+/** HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL    (BIT(24))
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_S  24
+/** HP_SYS_CLKRST_REG_TWAI0_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI0_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL    (BIT(26))
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_S  26
+/** HP_SYS_CLKRST_REG_TWAI1_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI1_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL    (BIT(28))
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_SRC_SEL_S  28
+/** HP_SYS_CLKRST_REG_TWAI2_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI2_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI2_CLK_EN_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL116_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL116_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x80)
+/** HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL    0x00000007U
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_V  0x00000007U
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_S  4
+/** HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_S  12
+/** HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL : R/W; bitpos: [23:21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL    0x00000007U
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_V  0x00000007U
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_S  21
+/** HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_S  24
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL117_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL117_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x84)
+/** HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL : R/W; bitpos: [18:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_S  17
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM : R/W; bitpos: [27:20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_S  20
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL118_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL118_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x88)
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_S  0
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_S  8
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_S  16
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM : R/W; bitpos: [26:19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_S  19
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL119_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL119_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x8c)
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_S  0
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_S  8
+/** HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_SRC_SEL_S  16
+/** HP_SYS_CLKRST_REG_I3C_MST_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_M  (HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_V << HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM : R/W; bitpos: [26:19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I3C_MST_CLK_DIV_NUM_S  19
+/** HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL : R/W; bitpos: [28:27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_S  27
+/** HP_SYS_CLKRST_REG_CAM_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN_M  (HP_SYS_CLKRST_REG_CAM_CLK_EN_V << HP_SYS_CLKRST_REG_CAM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL120_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL120_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x90)
+/** HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_S  16
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL20_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL20_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x94)
+/** HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_MCPWM0_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_S  3
+/** HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL : R/W; bitpos: [12:11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_S  11
+/** HP_SYS_CLKRST_REG_MCPWM1_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_S  13
+/** HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM : R/W; bitpos: [21:14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_S  14
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL : R/W; bitpos: [23:22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_S  22
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_S  24
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL : R/W; bitpos: [26:25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_S  25
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN    (BIT(27))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_S  27
+/** HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL : R/W; bitpos: [29:28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_S  28
+/** HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_S  30
+/** HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN    (BIT(31))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_S  31
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL21_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL21_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x98)
+/** HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL    0x0000000FU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM : R/W; bitpos: [19:4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM    0x0000FFFFU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_V  0x0000FFFFU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_S  4
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_S  20
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL : R/W; bitpos: [24:23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_S  23
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_S  25
+/** HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_S  26
+/** HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN    (BIT(28))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_S  28
+/** HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL    (BIT(29))
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_S  29
+/** HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN    (BIT(30))
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_M  (HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_V << HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_S  30
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL22_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL22_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x9c)
+/** HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_LEDC_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_LEDC_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_LEDC_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_LEDC_CLK_EN_M  (HP_SYS_CLKRST_REG_LEDC_CLK_EN_V << HP_SYS_CLKRST_REG_LEDC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_RMT_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN_M  (HP_SYS_CLKRST_REG_RMT_CLK_EN_V << HP_SYS_CLKRST_REG_RMT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM : R/W; bitpos: [13:6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_S  6
+/** HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR : R/W; bitpos: [21:14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_S  14
+/** HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR : R/W; bitpos: [29:22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_S  22
+/** HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_ADC_CLK_SRC_SEL_S  30
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL23_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL23_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa0)
+/** HP_SYS_CLKRST_REG_ADC_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_ADC_CLK_EN_M  (HP_SYS_CLKRST_REG_ADC_CLK_EN_V << HP_SYS_CLKRST_REG_ADC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ADC_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM : R/W; bitpos: [8:1]; default: 4;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUM_S  1
+/** HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR : R/W; bitpos: [16:9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_NUMERATOR_S  9
+/** HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR : R/W; bitpos: [24:17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_CLK_DIV_DENOMINATOR_S  17
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL24_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL24_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa4)
+/** HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ADC_SAR2_CLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_CLK_DIV_NUM_S  16
+/** HP_SYS_CLKRST_REG_PVT_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_CLK_EN_S  24
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL25_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL25_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa8)
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP1_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP2_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP3_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_V << HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT_PERI_GROUP4_CLK_EN_S  11
+/** HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL : R/W; bitpos: [13:12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_S  12
+/** HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_S  15
+/** HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_S  17
+/** HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_S  18
+/** HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN    (BIT(20))
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_S  20
+/** HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN    (BIT(21))
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_S  21
+/** HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL : R/W; bitpos: [24:23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_ISP_CLK_SRC_SEL_S  23
+/** HP_SYS_CLKRST_REG_ISP_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ISP_CLK_EN    (BIT(25))
+#define HP_SYS_CLKRST_REG_ISP_CLK_EN_M  (HP_SYS_CLKRST_REG_ISP_CLK_EN_V << HP_SYS_CLKRST_REG_ISP_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ISP_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ISP_CLK_EN_S  25
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL26_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL26_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xac)
+/** HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ISP_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL    (BIT(8))
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_S  8
+/** HP_SYS_CLKRST_REG_IOMUX_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN_M  (HP_SYS_CLKRST_REG_IOMUX_CLK_EN_V << HP_SYS_CLKRST_REG_IOMUX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM : R/W; bitpos: [17:10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_S  10
+/** HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL    (BIT(18))
+#define HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_H264_CLK_SRC_SEL_S  18
+/** HP_SYS_CLKRST_REG_H264_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_H264_CLK_EN    (BIT(19))
+#define HP_SYS_CLKRST_REG_H264_CLK_EN_M  (HP_SYS_CLKRST_REG_H264_CLK_EN_V << HP_SYS_CLKRST_REG_H264_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_H264_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_H264_CLK_EN_S  19
+/** HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM : R/W; bitpos: [27:20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_H264_CLK_DIV_NUM_S  20
+/** HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL    (BIT(28))
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_SRC_SEL_S  28
+/** HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN    (BIT(29))
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_V << HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_EN_S  29
+
+/** HP_SYS_CLKRST_PERI_CLK_CTRL27_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_PERI_CLK_CTRL27_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xb0)
+/** HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PADBIST_RX_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL    (BIT(8))
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_SRC_SEL_S  8
+/** HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_V << HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM : R/W; bitpos: [17:10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PADBIST_TX_CLK_DIV_NUM_S  10
+
+/** HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xb4)
+/** HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON    (BIT(0))
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_S  0
+/** HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON    (BIT(1))
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_S  1
+/** HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON : R/W; bitpos: [2]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON    (BIT(2))
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON_S  2
+/** HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON    (BIT(3))
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON_S  3
+/** HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON    (BIT(4))
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON_S  4
+/** HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON : R/W; bitpos: [5]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON    (BIT(5))
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON_S  5
+/** HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON : R/W; bitpos: [6]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON    (BIT(6))
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON_S  6
+/** HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON : R/W; bitpos: [7]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON    (BIT(7))
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_S  7
+/** HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON    (BIT(8))
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_S  8
+/** HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON : R/W; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON    (BIT(9))
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON_S  9
+/** HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON : R/W; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON    (BIT(10))
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON_S  10
+/** HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON : R/W; bitpos: [11]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON    (BIT(11))
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON_S  11
+/** HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON : R/W; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON    (BIT(12))
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON_S  12
+/** HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON : R/W; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON    (BIT(13))
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON_S  13
+/** HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON : R/W; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON    (BIT(14))
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON_S  14
+/** HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON : R/W; bitpos: [15]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON    (BIT(15))
+#define HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SAR1_CLK_FORCE_ON_S  15
+/** HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON    (BIT(16))
+#define HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SAR2_CLK_FORCE_ON_S  16
+/** HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON : R/W; bitpos: [17]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON    (BIT(17))
+#define HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GMAC_TX_CLK_FORCE_ON_S  17
+/** HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON : R/W; bitpos: [18]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON    (BIT(18))
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_L2CACHE_L2MEM_CLK_FORCE_ON_S  18
+
+/** HP_SYS_CLKRST_DPA_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_DPA_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xb8)
+/** HP_SYS_CLKRST_REG_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_M  (HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_V << HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_S)
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_S  0
+/** HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL    (BIT(2))
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_M  (HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_V << HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_S)
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_S  2
+
+/** HP_SYS_CLKRST_ANA_PLL_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_ANA_PLL_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xbc)
+/** HP_SYS_CLKRST_REG_PLLA_CAL_END : RO; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END    (BIT(0))
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END_M  (HP_SYS_CLKRST_REG_PLLA_CAL_END_V << HP_SYS_CLKRST_REG_PLLA_CAL_END_S)
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END_S  0
+/** HP_SYS_CLKRST_REG_PLLA_CAL_STOP : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP    (BIT(1))
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP_M  (HP_SYS_CLKRST_REG_PLLA_CAL_STOP_V << HP_SYS_CLKRST_REG_PLLA_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP_S  1
+/** HP_SYS_CLKRST_REG_CPU_PLL_CAL_END : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END    (BIT(2))
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_V << HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_S  2
+/** HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP    (BIT(3))
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_V << HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_S  3
+/** HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END : RO; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END    (BIT(4))
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_V << HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_S  4
+/** HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP    (BIT(5))
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_V << HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_S  5
+/** HP_SYS_CLKRST_REG_SYS_PLL_CAL_END : RO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_END    (BIT(6))
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_V << HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_END_S  6
+/** HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP    (BIT(7))
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_V << HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYS_PLL_CAL_STOP_S  7
+/** HP_SYS_CLKRST_REG_MSPI_CAL_END : RO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END    (BIT(8))
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END_M  (HP_SYS_CLKRST_REG_MSPI_CAL_END_V << HP_SYS_CLKRST_REG_MSPI_CAL_END_S)
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END_S  8
+/** HP_SYS_CLKRST_REG_MSPI_CAL_STOP : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP    (BIT(9))
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP_M  (HP_SYS_CLKRST_REG_MSPI_CAL_STOP_V << HP_SYS_CLKRST_REG_MSPI_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP_S  9
+
+/** HP_SYS_CLKRST_HP_RST_EN0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_RST_EN0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc0)
+/** HP_SYS_CLKRST_REG_RST_EN_CORECTRL : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORECTRL    (BIT(0))
+#define HP_SYS_CLKRST_REG_RST_EN_CORECTRL_M  (HP_SYS_CLKRST_REG_RST_EN_CORECTRL_V << HP_SYS_CLKRST_REG_RST_EN_CORECTRL_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORECTRL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORECTRL_S  0
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_TOP : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_TOP    (BIT(1))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_V << HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_TOP_S  1
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1 : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1    (BIT(2))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_V << HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP1_S  2
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2 : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2    (BIT(3))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_V << HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP2_S  3
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3 : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3    (BIT(4))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_V << HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP3_S  4
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4 : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4    (BIT(5))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_V << HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_PERI_GROUP4_S  5
+/** HP_SYS_CLKRST_REG_RST_EN_REGDMA : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_REGDMA    (BIT(6))
+#define HP_SYS_CLKRST_REG_RST_EN_REGDMA_M  (HP_SYS_CLKRST_REG_RST_EN_REGDMA_V << HP_SYS_CLKRST_REG_RST_EN_REGDMA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_REGDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_REGDMA_S  6
+/** HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL    (BIT(7))
+#define HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_M  (HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_V << HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORE0_GLOBAL_S  7
+/** HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL    (BIT(8))
+#define HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_M  (HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_V << HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL_S  8
+/** HP_SYS_CLKRST_REG_RST_EN_CORETRACE0 : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE0    (BIT(9))
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_M  (HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_V << HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE0_S  9
+/** HP_SYS_CLKRST_REG_RST_EN_CORETRACE1 : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE1    (BIT(10))
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_M  (HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_V << HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CORETRACE1_S  10
+/** HP_SYS_CLKRST_REG_RST_EN_HP_TCM : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_HP_TCM    (BIT(11))
+#define HP_SYS_CLKRST_REG_RST_EN_HP_TCM_M  (HP_SYS_CLKRST_REG_RST_EN_HP_TCM_V << HP_SYS_CLKRST_REG_RST_EN_HP_TCM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_HP_TCM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_HP_TCM_S  11
+/** HP_SYS_CLKRST_REG_RST_EN_HP_CACHE : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_HP_CACHE    (BIT(12))
+#define HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_HP_CACHE_S  12
+/** HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE    (BIT(13))
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I0_CACHE_S  13
+/** HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE    (BIT(14))
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L1_I1_CACHE_S  14
+/** HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE    (BIT(15))
+#define HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L1_D_CACHE_S  15
+/** HP_SYS_CLKRST_REG_RST_EN_L2_CACHE : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L2_CACHE    (BIT(16))
+#define HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_M  (HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_V << HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L2_CACHE_S  16
+/** HP_SYS_CLKRST_REG_RST_EN_L2_MEM : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L2_MEM    (BIT(17))
+#define HP_SYS_CLKRST_REG_RST_EN_L2_MEM_M  (HP_SYS_CLKRST_REG_RST_EN_L2_MEM_V << HP_SYS_CLKRST_REG_RST_EN_L2_MEM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L2_MEM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L2_MEM_S  17
+/** HP_SYS_CLKRST_REG_RST_EN_L2MEMMON : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_L2MEMMON    (BIT(18))
+#define HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_M  (HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_V << HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_S)
+#define HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_L2MEMMON_S  18
+/** HP_SYS_CLKRST_REG_RST_EN_TCMMON : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_TCMMON    (BIT(19))
+#define HP_SYS_CLKRST_REG_RST_EN_TCMMON_M  (HP_SYS_CLKRST_REG_RST_EN_TCMMON_V << HP_SYS_CLKRST_REG_RST_EN_TCMMON_S)
+#define HP_SYS_CLKRST_REG_RST_EN_TCMMON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_TCMMON_S  19
+/** HP_SYS_CLKRST_REG_RST_EN_PVT_APB : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_APB    (BIT(20))
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_APB_M  (HP_SYS_CLKRST_REG_RST_EN_PVT_APB_V << HP_SYS_CLKRST_REG_RST_EN_PVT_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PVT_APB_S  20
+/** HP_SYS_CLKRST_REG_RST_EN_GDMA : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_GDMA    (BIT(21))
+#define HP_SYS_CLKRST_REG_RST_EN_GDMA_M  (HP_SYS_CLKRST_REG_RST_EN_GDMA_V << HP_SYS_CLKRST_REG_RST_EN_GDMA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_GDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_GDMA_S  21
+/** HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI    (BIT(22))
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_M  (HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_V << HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_S)
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI_S  22
+/** HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI    (BIT(23))
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_M  (HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_V << HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_AXI_S  23
+/** HP_SYS_CLKRST_REG_RST_EN_MSPI_APB : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB    (BIT(24))
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_M  (HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_V << HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB_S  24
+/** HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB    (BIT(25))
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_M  (HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_V << HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DUAL_MSPI_APB_S  25
+/** HP_SYS_CLKRST_REG_RST_EN_DSI_BRG : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DSI_BRG    (BIT(26))
+#define HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_M  (HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_V << HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DSI_BRG_S  26
+/** HP_SYS_CLKRST_REG_RST_EN_CSI_HOST : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_HOST    (BIT(27))
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_M  (HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_V << HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_HOST_S  27
+/** HP_SYS_CLKRST_REG_RST_EN_CSI_BRG : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_BRG    (BIT(28))
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_M  (HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_V << HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CSI_BRG_S  28
+/** HP_SYS_CLKRST_REG_RST_EN_ISP : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ISP    (BIT(29))
+#define HP_SYS_CLKRST_REG_RST_EN_ISP_M  (HP_SYS_CLKRST_REG_RST_EN_ISP_V << HP_SYS_CLKRST_REG_RST_EN_ISP_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ISP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ISP_S  29
+/** HP_SYS_CLKRST_REG_RST_EN_JPEG : R/W; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_JPEG    (BIT(30))
+#define HP_SYS_CLKRST_REG_RST_EN_JPEG_M  (HP_SYS_CLKRST_REG_RST_EN_JPEG_V << HP_SYS_CLKRST_REG_RST_EN_JPEG_S)
+#define HP_SYS_CLKRST_REG_RST_EN_JPEG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_JPEG_S  30
+/** HP_SYS_CLKRST_REG_RST_EN_DMA2D : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DMA2D    (BIT(31))
+#define HP_SYS_CLKRST_REG_RST_EN_DMA2D_M  (HP_SYS_CLKRST_REG_RST_EN_DMA2D_V << HP_SYS_CLKRST_REG_RST_EN_DMA2D_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DMA2D_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DMA2D_S  31
+
+/** HP_SYS_CLKRST_HP_RST_EN1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_RST_EN1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc4)
+/** HP_SYS_CLKRST_REG_RST_EN_PPA : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PPA    (BIT(0))
+#define HP_SYS_CLKRST_REG_RST_EN_PPA_M  (HP_SYS_CLKRST_REG_RST_EN_PPA_V << HP_SYS_CLKRST_REG_RST_EN_PPA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PPA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PPA_S  0
+/** HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA    (BIT(1))
+#define HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_M  (HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_V << HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_AHB_PDMA_S  1
+/** HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA    (BIT(2))
+#define HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_M  (HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_V << HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_AXI_PDMA_S  2
+/** HP_SYS_CLKRST_REG_RST_EN_IOMUX : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_IOMUX    (BIT(3))
+#define HP_SYS_CLKRST_REG_RST_EN_IOMUX_M  (HP_SYS_CLKRST_REG_RST_EN_IOMUX_V << HP_SYS_CLKRST_REG_RST_EN_IOMUX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_IOMUX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_IOMUX_S  3
+/** HP_SYS_CLKRST_REG_RST_EN_PADBIST : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PADBIST    (BIT(4))
+#define HP_SYS_CLKRST_REG_RST_EN_PADBIST_M  (HP_SYS_CLKRST_REG_RST_EN_PADBIST_V << HP_SYS_CLKRST_REG_RST_EN_PADBIST_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PADBIST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PADBIST_S  4
+/** HP_SYS_CLKRST_REG_RST_EN_STIMER : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_STIMER    (BIT(5))
+#define HP_SYS_CLKRST_REG_RST_EN_STIMER_M  (HP_SYS_CLKRST_REG_RST_EN_STIMER_V << HP_SYS_CLKRST_REG_RST_EN_STIMER_S)
+#define HP_SYS_CLKRST_REG_RST_EN_STIMER_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_STIMER_S  5
+/** HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0 : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0    (BIT(6))
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_M  (HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_V << HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP0_S  6
+/** HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1 : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1    (BIT(7))
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_M  (HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_V << HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_TIMERGRP1_S  7
+/** HP_SYS_CLKRST_REG_RST_EN_UART0_CORE : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_CORE    (BIT(8))
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_CORE_S  8
+/** HP_SYS_CLKRST_REG_RST_EN_UART1_CORE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_CORE    (BIT(9))
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_CORE_S  9
+/** HP_SYS_CLKRST_REG_RST_EN_UART2_CORE : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_CORE    (BIT(10))
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_CORE_S  10
+/** HP_SYS_CLKRST_REG_RST_EN_UART3_CORE : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_CORE    (BIT(11))
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_CORE_S  11
+/** HP_SYS_CLKRST_REG_RST_EN_UART4_CORE : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_CORE    (BIT(12))
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_M  (HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_V << HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_CORE_S  12
+/** HP_SYS_CLKRST_REG_RST_EN_UART0_APB : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_APB    (BIT(13))
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART0_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART0_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART0_APB_S  13
+/** HP_SYS_CLKRST_REG_RST_EN_UART1_APB : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_APB    (BIT(14))
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART1_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART1_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART1_APB_S  14
+/** HP_SYS_CLKRST_REG_RST_EN_UART2_APB : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_APB    (BIT(15))
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART2_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART2_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART2_APB_S  15
+/** HP_SYS_CLKRST_REG_RST_EN_UART3_APB : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_APB    (BIT(16))
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART3_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART3_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART3_APB_S  16
+/** HP_SYS_CLKRST_REG_RST_EN_UART4_APB : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_APB    (BIT(17))
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_APB_M  (HP_SYS_CLKRST_REG_RST_EN_UART4_APB_V << HP_SYS_CLKRST_REG_RST_EN_UART4_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UART4_APB_S  17
+/** HP_SYS_CLKRST_REG_RST_EN_UHCI : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_UHCI    (BIT(18))
+#define HP_SYS_CLKRST_REG_RST_EN_UHCI_M  (HP_SYS_CLKRST_REG_RST_EN_UHCI_V << HP_SYS_CLKRST_REG_RST_EN_UHCI_S)
+#define HP_SYS_CLKRST_REG_RST_EN_UHCI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_UHCI_S  18
+/** HP_SYS_CLKRST_REG_RST_EN_I3CMST : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I3CMST    (BIT(19))
+#define HP_SYS_CLKRST_REG_RST_EN_I3CMST_M  (HP_SYS_CLKRST_REG_RST_EN_I3CMST_V << HP_SYS_CLKRST_REG_RST_EN_I3CMST_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I3CMST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I3CMST_S  19
+/** HP_SYS_CLKRST_REG_RST_EN_I3CSLV : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I3CSLV    (BIT(20))
+#define HP_SYS_CLKRST_REG_RST_EN_I3CSLV_M  (HP_SYS_CLKRST_REG_RST_EN_I3CSLV_V << HP_SYS_CLKRST_REG_RST_EN_I3CSLV_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I3CSLV_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I3CSLV_S  20
+/** HP_SYS_CLKRST_REG_RST_EN_I2C1 : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2C1    (BIT(21))
+#define HP_SYS_CLKRST_REG_RST_EN_I2C1_M  (HP_SYS_CLKRST_REG_RST_EN_I2C1_V << HP_SYS_CLKRST_REG_RST_EN_I2C1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2C1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2C1_S  21
+/** HP_SYS_CLKRST_REG_RST_EN_I2C0 : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2C0    (BIT(22))
+#define HP_SYS_CLKRST_REG_RST_EN_I2C0_M  (HP_SYS_CLKRST_REG_RST_EN_I2C0_V << HP_SYS_CLKRST_REG_RST_EN_I2C0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2C0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2C0_S  22
+/** HP_SYS_CLKRST_REG_RST_EN_RMT : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_RMT    (BIT(23))
+#define HP_SYS_CLKRST_REG_RST_EN_RMT_M  (HP_SYS_CLKRST_REG_RST_EN_RMT_V << HP_SYS_CLKRST_REG_RST_EN_RMT_S)
+#define HP_SYS_CLKRST_REG_RST_EN_RMT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_RMT_S  23
+/** HP_SYS_CLKRST_REG_RST_EN_PWM0 : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PWM0    (BIT(24))
+#define HP_SYS_CLKRST_REG_RST_EN_PWM0_M  (HP_SYS_CLKRST_REG_RST_EN_PWM0_V << HP_SYS_CLKRST_REG_RST_EN_PWM0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PWM0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PWM0_S  24
+/** HP_SYS_CLKRST_REG_RST_EN_PWM1 : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PWM1    (BIT(25))
+#define HP_SYS_CLKRST_REG_RST_EN_PWM1_M  (HP_SYS_CLKRST_REG_RST_EN_PWM1_V << HP_SYS_CLKRST_REG_RST_EN_PWM1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PWM1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PWM1_S  25
+/** HP_SYS_CLKRST_REG_RST_EN_CAN0 : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CAN0    (BIT(26))
+#define HP_SYS_CLKRST_REG_RST_EN_CAN0_M  (HP_SYS_CLKRST_REG_RST_EN_CAN0_V << HP_SYS_CLKRST_REG_RST_EN_CAN0_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CAN0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CAN0_S  26
+/** HP_SYS_CLKRST_REG_RST_EN_CAN1 : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CAN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_RST_EN_CAN1_M  (HP_SYS_CLKRST_REG_RST_EN_CAN1_V << HP_SYS_CLKRST_REG_RST_EN_CAN1_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CAN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CAN1_S  27
+/** HP_SYS_CLKRST_REG_RST_EN_CAN2 : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CAN2    (BIT(28))
+#define HP_SYS_CLKRST_REG_RST_EN_CAN2_M  (HP_SYS_CLKRST_REG_RST_EN_CAN2_V << HP_SYS_CLKRST_REG_RST_EN_CAN2_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CAN2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CAN2_S  28
+/** HP_SYS_CLKRST_REG_RST_EN_LEDC : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_LEDC    (BIT(29))
+#define HP_SYS_CLKRST_REG_RST_EN_LEDC_M  (HP_SYS_CLKRST_REG_RST_EN_LEDC_V << HP_SYS_CLKRST_REG_RST_EN_LEDC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_LEDC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_LEDC_S  29
+/** HP_SYS_CLKRST_REG_RST_EN_PCNT : R/W; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PCNT    (BIT(30))
+#define HP_SYS_CLKRST_REG_RST_EN_PCNT_M  (HP_SYS_CLKRST_REG_RST_EN_PCNT_V << HP_SYS_CLKRST_REG_RST_EN_PCNT_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PCNT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PCNT_S  30
+/** HP_SYS_CLKRST_REG_RST_EN_ETM : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ETM    (BIT(31))
+#define HP_SYS_CLKRST_REG_RST_EN_ETM_M  (HP_SYS_CLKRST_REG_RST_EN_ETM_V << HP_SYS_CLKRST_REG_RST_EN_ETM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ETM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ETM_S  31
+
+/** HP_SYS_CLKRST_HP_RST_EN2_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_RST_EN2_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc8)
+/** HP_SYS_CLKRST_REG_RST_EN_INTRMTX : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_INTRMTX    (BIT(0))
+#define HP_SYS_CLKRST_REG_RST_EN_INTRMTX_M  (HP_SYS_CLKRST_REG_RST_EN_INTRMTX_V << HP_SYS_CLKRST_REG_RST_EN_INTRMTX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_INTRMTX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_INTRMTX_S  0
+/** HP_SYS_CLKRST_REG_RST_EN_PARLIO : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO    (BIT(1))
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_M  (HP_SYS_CLKRST_REG_RST_EN_PARLIO_V << HP_SYS_CLKRST_REG_RST_EN_PARLIO_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_S  1
+/** HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX    (BIT(2))
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_M  (HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_V << HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX_S  2
+/** HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX    (BIT(3))
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_M  (HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_V << HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX_S  3
+/** HP_SYS_CLKRST_REG_RST_EN_I2S0_APB : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2S0_APB    (BIT(4))
+#define HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_M  (HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_V << HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2S0_APB_S  4
+/** HP_SYS_CLKRST_REG_RST_EN_I2S1_APB : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2S1_APB    (BIT(5))
+#define HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_M  (HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_V << HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2S1_APB_S  5
+/** HP_SYS_CLKRST_REG_RST_EN_I2S2_APB : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_I2S2_APB    (BIT(6))
+#define HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_M  (HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_V << HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_S)
+#define HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_I2S2_APB_S  6
+/** HP_SYS_CLKRST_REG_RST_EN_SPI2 : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_SPI2    (BIT(7))
+#define HP_SYS_CLKRST_REG_RST_EN_SPI2_M  (HP_SYS_CLKRST_REG_RST_EN_SPI2_V << HP_SYS_CLKRST_REG_RST_EN_SPI2_S)
+#define HP_SYS_CLKRST_REG_RST_EN_SPI2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_SPI2_S  7
+/** HP_SYS_CLKRST_REG_RST_EN_SPI3 : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_SPI3    (BIT(8))
+#define HP_SYS_CLKRST_REG_RST_EN_SPI3_M  (HP_SYS_CLKRST_REG_RST_EN_SPI3_V << HP_SYS_CLKRST_REG_RST_EN_SPI3_S)
+#define HP_SYS_CLKRST_REG_RST_EN_SPI3_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_SPI3_S  8
+/** HP_SYS_CLKRST_REG_RST_EN_LCDCAM : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_LCDCAM    (BIT(9))
+#define HP_SYS_CLKRST_REG_RST_EN_LCDCAM_M  (HP_SYS_CLKRST_REG_RST_EN_LCDCAM_V << HP_SYS_CLKRST_REG_RST_EN_LCDCAM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_LCDCAM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_LCDCAM_S  9
+/** HP_SYS_CLKRST_REG_RST_EN_ADC : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ADC    (BIT(10))
+#define HP_SYS_CLKRST_REG_RST_EN_ADC_M  (HP_SYS_CLKRST_REG_RST_EN_ADC_V << HP_SYS_CLKRST_REG_RST_EN_ADC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ADC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ADC_S  10
+/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER    (BIT(11))
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_M  (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_S)
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_S  11
+/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX    (BIT(12))
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_M  (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_RX_S  12
+/** HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX    (BIT(13))
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_M  (HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_V << HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_S)
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_BITSRAMBLER_TX_S  13
+/** HP_SYS_CLKRST_REG_RST_EN_CRYPTO : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_CRYPTO    (BIT(14))
+#define HP_SYS_CLKRST_REG_RST_EN_CRYPTO_M  (HP_SYS_CLKRST_REG_RST_EN_CRYPTO_V << HP_SYS_CLKRST_REG_RST_EN_CRYPTO_S)
+#define HP_SYS_CLKRST_REG_RST_EN_CRYPTO_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_CRYPTO_S  14
+/** HP_SYS_CLKRST_REG_RST_EN_SEC : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_SEC    (BIT(15))
+#define HP_SYS_CLKRST_REG_RST_EN_SEC_M  (HP_SYS_CLKRST_REG_RST_EN_SEC_V << HP_SYS_CLKRST_REG_RST_EN_SEC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_SEC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_SEC_S  15
+/** HP_SYS_CLKRST_REG_RST_EN_AES : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_AES    (BIT(16))
+#define HP_SYS_CLKRST_REG_RST_EN_AES_M  (HP_SYS_CLKRST_REG_RST_EN_AES_V << HP_SYS_CLKRST_REG_RST_EN_AES_S)
+#define HP_SYS_CLKRST_REG_RST_EN_AES_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_AES_S  16
+/** HP_SYS_CLKRST_REG_RST_EN_DS : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_DS    (BIT(17))
+#define HP_SYS_CLKRST_REG_RST_EN_DS_M  (HP_SYS_CLKRST_REG_RST_EN_DS_V << HP_SYS_CLKRST_REG_RST_EN_DS_S)
+#define HP_SYS_CLKRST_REG_RST_EN_DS_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_DS_S  17
+/** HP_SYS_CLKRST_REG_RST_EN_SHA : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_SHA    (BIT(18))
+#define HP_SYS_CLKRST_REG_RST_EN_SHA_M  (HP_SYS_CLKRST_REG_RST_EN_SHA_V << HP_SYS_CLKRST_REG_RST_EN_SHA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_SHA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_SHA_S  18
+/** HP_SYS_CLKRST_REG_RST_EN_HMAC : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_HMAC    (BIT(19))
+#define HP_SYS_CLKRST_REG_RST_EN_HMAC_M  (HP_SYS_CLKRST_REG_RST_EN_HMAC_V << HP_SYS_CLKRST_REG_RST_EN_HMAC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_HMAC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_HMAC_S  19
+/** HP_SYS_CLKRST_REG_RST_EN_ECDSA : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ECDSA    (BIT(20))
+#define HP_SYS_CLKRST_REG_RST_EN_ECDSA_M  (HP_SYS_CLKRST_REG_RST_EN_ECDSA_V << HP_SYS_CLKRST_REG_RST_EN_ECDSA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ECDSA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ECDSA_S  20
+/** HP_SYS_CLKRST_REG_RST_EN_RSA : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_RSA    (BIT(21))
+#define HP_SYS_CLKRST_REG_RST_EN_RSA_M  (HP_SYS_CLKRST_REG_RST_EN_RSA_V << HP_SYS_CLKRST_REG_RST_EN_RSA_S)
+#define HP_SYS_CLKRST_REG_RST_EN_RSA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_RSA_S  21
+/** HP_SYS_CLKRST_REG_RST_EN_ECC : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_ECC    (BIT(22))
+#define HP_SYS_CLKRST_REG_RST_EN_ECC_M  (HP_SYS_CLKRST_REG_RST_EN_ECC_V << HP_SYS_CLKRST_REG_RST_EN_ECC_S)
+#define HP_SYS_CLKRST_REG_RST_EN_ECC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_ECC_S  22
+/** HP_SYS_CLKRST_REG_RST_EN_KM : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_KM    (BIT(23))
+#define HP_SYS_CLKRST_REG_RST_EN_KM_M  (HP_SYS_CLKRST_REG_RST_EN_KM_V << HP_SYS_CLKRST_REG_RST_EN_KM_S)
+#define HP_SYS_CLKRST_REG_RST_EN_KM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_KM_S  23
+/** HP_SYS_CLKRST_REG_RST_EN_H264 : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_RST_EN_H264    (BIT(24))
+#define HP_SYS_CLKRST_REG_RST_EN_H264_M  (HP_SYS_CLKRST_REG_RST_EN_H264_V << HP_SYS_CLKRST_REG_RST_EN_H264_S)
+#define HP_SYS_CLKRST_REG_RST_EN_H264_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RST_EN_H264_S  24
+
+/** HP_SYS_CLKRST_HP_FORCE_NORST0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_FORCE_NORST0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xcc)
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CORE0 : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE0    (BIT(0))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_V << HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE0_S  0
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CORE1 : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE1    (BIT(1))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_V << HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORE1_S  1
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0 : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0    (BIT(2))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_V << HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE0_S  2
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1 : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1    (BIT(3))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_V << HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CORETRACE1_S  3
+/** HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON    (BIT(4))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_M  (HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_V << HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_L2MEMMON_S  4
+/** HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON    (BIT(5))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_M  (HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_V << HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TCMMON_S  5
+/** HP_SYS_CLKRST_REG_FORCE_NORST_GDMA : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_GDMA    (BIT(6))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_M  (HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_V << HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_GDMA_S  6
+/** HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI    (BIT(7))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_M  (HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_V << HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_AXI_S  7
+/** HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI    (BIT(8))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_M  (HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_V << HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_AXI_S  8
+/** HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB    (BIT(9))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_M  (HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_V << HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_MSPI_APB_S  9
+/** HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB    (BIT(10))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_M  (HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_V << HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DUAL_MSPI_APB_S  10
+/** HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG    (BIT(11))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_M  (HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_V << HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DSI_BRG_S  11
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST    (BIT(12))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_V << HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_HOST_S  12
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG    (BIT(13))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_V << HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CSI_BRG_S  13
+/** HP_SYS_CLKRST_REG_FORCE_NORST_ISP : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ISP    (BIT(14))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ISP_M  (HP_SYS_CLKRST_REG_FORCE_NORST_ISP_V << HP_SYS_CLKRST_REG_FORCE_NORST_ISP_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ISP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ISP_S  14
+/** HP_SYS_CLKRST_REG_FORCE_NORST_JPEG : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_JPEG    (BIT(15))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_M  (HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_V << HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_JPEG_S  15
+/** HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D    (BIT(16))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_M  (HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_V << HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_DMA2D_S  16
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PPA : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PPA    (BIT(17))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PPA_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PPA_V << HP_SYS_CLKRST_REG_FORCE_NORST_PPA_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PPA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PPA_S  17
+/** HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA    (BIT(18))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_M  (HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_V << HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AHB_PDMA_S  18
+/** HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA    (BIT(19))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_M  (HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_V << HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_AXI_PDMA_S  19
+/** HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX    (BIT(20))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_V << HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_IOMUX_S  20
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST    (BIT(21))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_V << HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PADBIST_S  21
+/** HP_SYS_CLKRST_REG_FORCE_NORST_STIMER : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_STIMER    (BIT(22))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_M  (HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_V << HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_STIMER_S  22
+/** HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0 : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0    (BIT(23))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_V << HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP0_S  23
+/** HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1 : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1    (BIT(24))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_V << HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_TIMERGRP1_S  24
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART0 : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART0    (BIT(25))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART0_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART0_S  25
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART1 : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART1    (BIT(26))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART1_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART1_S  26
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART2 : R/W; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART2    (BIT(27))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART2_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART2_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART2_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART2_S  27
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART3 : R/W; bitpos: [28]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART3    (BIT(28))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART3_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART3_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART3_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART3_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART3_S  28
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UART4 : R/W; bitpos: [29]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART4    (BIT(29))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART4_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UART4_V << HP_SYS_CLKRST_REG_FORCE_NORST_UART4_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART4_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UART4_S  29
+/** HP_SYS_CLKRST_REG_FORCE_NORST_UHCI : R/W; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UHCI    (BIT(30))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_M  (HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_V << HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_UHCI_S  30
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST : R/W; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST    (BIT(31))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_V << HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CMST_S  31
+
+/** HP_SYS_CLKRST_HP_FORCE_NORST1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HP_FORCE_NORST1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xd0)
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV    (BIT(0))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_V << HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I3CSLV_S  0
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2C1 : R/W; bitpos: [1]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C1    (BIT(1))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C1_S  1
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2C0 : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C0    (BIT(2))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2C0_S  2
+/** HP_SYS_CLKRST_REG_FORCE_NORST_RMT : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_RMT    (BIT(3))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_RMT_M  (HP_SYS_CLKRST_REG_FORCE_NORST_RMT_V << HP_SYS_CLKRST_REG_FORCE_NORST_RMT_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_RMT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_RMT_S  3
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PWM0 : R/W; bitpos: [4]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM0    (BIT(4))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_V << HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM0_S  4
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PWM1 : R/W; bitpos: [5]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM1    (BIT(5))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_V << HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PWM1_S  5
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CAN0 : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN0    (BIT(6))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_V << HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN0_S  6
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CAN1 : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN1    (BIT(7))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_V << HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN1_S  7
+/** HP_SYS_CLKRST_REG_FORCE_NORST_CAN2 : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN2    (BIT(8))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_M  (HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_V << HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_CAN2_S  8
+/** HP_SYS_CLKRST_REG_FORCE_NORST_LEDC : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LEDC    (BIT(9))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_M  (HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_V << HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LEDC_S  9
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PCNT : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PCNT    (BIT(10))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_V << HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PCNT_S  10
+/** HP_SYS_CLKRST_REG_FORCE_NORST_ETM : R/W; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ETM    (BIT(11))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ETM_M  (HP_SYS_CLKRST_REG_FORCE_NORST_ETM_V << HP_SYS_CLKRST_REG_FORCE_NORST_ETM_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ETM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ETM_S  11
+/** HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX    (BIT(12))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_V << HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_INTRMTX_S  12
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO    (BIT(13))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_V << HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_S  13
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX : R/W; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX    (BIT(14))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_V << HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_RX_S  14
+/** HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX : R/W; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX    (BIT(15))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_V << HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_PARLIO_TX_S  15
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2S0 : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S0    (BIT(16))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S0_S  16
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2S1 : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S1    (BIT(17))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S1_S  17
+/** HP_SYS_CLKRST_REG_FORCE_NORST_I2S2 : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S2    (BIT(18))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_M  (HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_V << HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_I2S2_S  18
+/** HP_SYS_CLKRST_REG_FORCE_NORST_SPI2 : R/W; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI2    (BIT(19))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_M  (HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_V << HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI2_S  19
+/** HP_SYS_CLKRST_REG_FORCE_NORST_SPI3 : R/W; bitpos: [20]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI3    (BIT(20))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_M  (HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_V << HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_SPI3_S  20
+/** HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM : R/W; bitpos: [21]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM    (BIT(21))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_M  (HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_V << HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_LCDCAM_S  21
+/** HP_SYS_CLKRST_REG_FORCE_NORST_ADC : R/W; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC    (BIT(22))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_M  (HP_SYS_CLKRST_REG_FORCE_NORST_ADC_V << HP_SYS_CLKRST_REG_FORCE_NORST_ADC_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_ADC_S  22
+/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER : R/W; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER    (BIT(23))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_M  (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_S  23
+/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX : R/W; bitpos: [24]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX    (BIT(24))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_RX_S  24
+/** HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX : R/W; bitpos: [25]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX    (BIT(25))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_M  (HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_V << HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_BITSRAMBLER_TX_S  25
+/** HP_SYS_CLKRST_REG_FORCE_NORST_H264 : R/W; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_FORCE_NORST_H264    (BIT(26))
+#define HP_SYS_CLKRST_REG_FORCE_NORST_H264_M  (HP_SYS_CLKRST_REG_FORCE_NORST_H264_V << HP_SYS_CLKRST_REG_FORCE_NORST_H264_S)
+#define HP_SYS_CLKRST_REG_FORCE_NORST_H264_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FORCE_NORST_H264_S  26
+
+/** HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xd4)
+/** HP_SYS_CLKRST_REG_HPCORE0_STALL_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_M  (HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_V << HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_S)
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_S  0
+/** HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM : R/W; bitpos: [8:1]; default: 8;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_M  (HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_V << HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_S)
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_S  1
+/** HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN : R/W; bitpos: [16:9]; default: 8;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN    0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_M  (HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_V << HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_S)
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_S  9
+
+/** HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xd8)
+/** HP_SYS_CLKRST_REG_HPCORE1_STALL_EN : R/W; bitpos: [0]; default: 1;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_M  (HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_V << HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_S)
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_S  0
+/** HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM : R/W; bitpos: [8:1]; default: 8;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_M  (HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_V << HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_S)
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_S  1
+/** HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN : R/W; bitpos: [16:9]; default: 8;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN    0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_M  (HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_V << HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_S)
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_S  9
+
+/** HP_SYS_CLKRST_CPU_SRC_FREQ0_REG register
+ *  CPU Source Frequency
+ */
+#define HP_SYS_CLKRST_CPU_SRC_FREQ0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xdc)
+/** HP_SYS_CLKRST_REG_CPU_SRC_FREQ : RO; bitpos: [31:0]; default: 0;
+ *  cpu source clock frequency, step by 0.25MHz
+ */
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ    0xFFFFFFFFU
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ_M  (HP_SYS_CLKRST_REG_CPU_SRC_FREQ_V << HP_SYS_CLKRST_REG_CPU_SRC_FREQ_S)
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ_V  0xFFFFFFFFU
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ_S  0
+
+/** HP_SYS_CLKRST_CPU_CLK_STATUS0_REG register
+ *  CPU Clock Status
+ */
+#define HP_SYS_CLKRST_CPU_CLK_STATUS0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xe0)
+/** HP_SYS_CLKRST_REG_ASIC_OR_FPGA : RO; bitpos: [0]; default: 0;
+ *  0: ASIC mode, 1: FPGA mode
+ */
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA    (BIT(0))
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA_M  (HP_SYS_CLKRST_REG_ASIC_OR_FPGA_V << HP_SYS_CLKRST_REG_ASIC_OR_FPGA_S)
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA_S  0
+/** HP_SYS_CLKRST_REG_CPU_DIV_EFFECT : RO; bitpos: [1]; default: 0;
+ *  0: Divider bypass, 1: Divider takes effect
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT    (BIT(1))
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_M  (HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_V << HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_S  1
+/** HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL : RO; bitpos: [2]; default: 0;
+ *  0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m
+ */
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL    (BIT(2))
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_M  (HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_V << HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_S)
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_S  2
+/** HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR : RO; bitpos: [10:3]; default: 0;
+ *  cpu current div number
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_M  (HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_V << HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_S  3
+/** HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR : RO; bitpos: [18:11]; default: 0;
+ *  cpu current div numerator
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_M  (HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_V << HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_S  11
+/** HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR : RO; bitpos: [26:19]; default: 0;
+ *  cpu current div denominator
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_M  (HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_V << HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_S  19
+
+/** HP_SYS_CLKRST_DBG_CLK_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_DBG_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xe4)
+/** HP_SYS_CLKRST_REG_DBG_CH0_SEL : R/W; bitpos: [7:0]; default: 255;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH0_SEL_V << HP_SYS_CLKRST_REG_DBG_CH0_SEL_S)
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL_S  0
+/** HP_SYS_CLKRST_REG_DBG_CH1_SEL : R/W; bitpos: [15:8]; default: 255;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH1_SEL_V << HP_SYS_CLKRST_REG_DBG_CH1_SEL_S)
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL_S  8
+/** HP_SYS_CLKRST_REG_DBG_CH2_SEL : R/W; bitpos: [23:16]; default: 255;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH2_SEL_V << HP_SYS_CLKRST_REG_DBG_CH2_SEL_S)
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_S  16
+/** HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM : R/W; bitpos: [31:24]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_S  24
+
+/** HP_SYS_CLKRST_DBG_CLK_CTRL1_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_DBG_CLK_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xe8)
+/** HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM : R/W; bitpos: [7:0]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_DBG_CH0_EN : R/W; bitpos: [16]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN_M  (HP_SYS_CLKRST_REG_DBG_CH0_EN_V << HP_SYS_CLKRST_REG_DBG_CH0_EN_S)
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN_S  16
+/** HP_SYS_CLKRST_REG_DBG_CH1_EN : R/W; bitpos: [17]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN_M  (HP_SYS_CLKRST_REG_DBG_CH1_EN_V << HP_SYS_CLKRST_REG_DBG_CH1_EN_S)
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN_S  17
+/** HP_SYS_CLKRST_REG_DBG_CH2_EN : R/W; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN    (BIT(18))
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN_M  (HP_SYS_CLKRST_REG_DBG_CH2_EN_V << HP_SYS_CLKRST_REG_DBG_CH2_EN_S)
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN_S  18
+
+/** HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xec)
+/** HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL : R/W; bitpos: [0]; default: 0;
+ *  1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0
+ */
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL    (BIT(0))
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_M  (HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_V << HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_S)
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_S  0
+/** HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL : R/W; bitpos: [1]; default: 1;
+ *  1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1
+ */
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL    (BIT(1))
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_M  (HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_V << HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_S)
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_S  1
+
+/** HP_SYS_CLKRST_AXI_PERF_MON_CLKRST_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_AXI_PERF_MON_CLKRST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xf0)
+/** HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures axi_perf_mon clk enable
+ */
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures axi_perf_mon rst enable
+ */
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_M  (HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_V << HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_SYS_RST_EN_S  1
+
+/** HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG register
+ *  Reserved
+ */
+#define HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xf4)
+/** HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether cpu core0 waiti signal can control clock gate. If both core0 and
+ *  core1 waiti_icg_en is 1, then only when core0 and core1 all in waiti will close
+ *  related clock
+ */
+#define HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_M  (HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_V << HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_S)
+#define HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_WAITI_ICG_EN_S  0
+/** HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN : R/W; bitpos: [1]; default: 1;
+ *  Configures whether cpu core1 waiti signal can control clock gate. If both core0 and
+ *  core1 waiti_icg_en is 1, then only when core0 and core1 all in waiti will close
+ *  related clock
+ */
+#define HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_M  (HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_V << HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_S)
+#define HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN_S  1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp_sys_clkrst_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/hp_sys_clkrst_struct.h
new file mode 100644
index 0000000000..4fe2960175
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp_sys_clkrst_struct.h
@@ -0,0 +1,3058 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_en */
+/** Type of clk_en0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_clk_en0_reg_t;
+
+
+/** Group: root_clk_ctrl */
+/** Type of root_clk_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_cpuicm_delay_num : R/W; bitpos: [3:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpuicm_delay_num:4;
+        /** reg_soc_clk_div_update : WT; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_soc_clk_div_update:1;
+        /** reg_cpu_clk_div_num : R/W; bitpos: [12:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_clk_div_num:8;
+        /** reg_cpu_clk_div_numerator : R/W; bitpos: [20:13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_clk_div_numerator:8;
+        /** reg_cpu_clk_div_denominator : R/W; bitpos: [28:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_clk_div_denominator:8;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_sys_clkrst_root_clk_ctrl0_reg_t;
+
+/** Type of root_clk_ctrl1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_mem_clk_div_num : R/W; bitpos: [7:0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_mem_clk_div_num:8;
+        /** reg_mem_clk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mem_clk_div_numerator:8;
+        /** reg_mem_clk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mem_clk_div_denominator:8;
+        /** reg_sys_clk_div_num : R/W; bitpos: [31:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_clk_div_num:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_root_clk_ctrl1_reg_t;
+
+/** Type of root_clk_ctrl2 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_sys_clk_div_numerator : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_clk_div_numerator:8;
+        /** reg_sys_clk_div_denominator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_clk_div_denominator:8;
+        /** reg_apb_clk_div_num : R/W; bitpos: [23:16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_apb_clk_div_num:8;
+        /** reg_apb_clk_div_numerator : R/W; bitpos: [31:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_apb_clk_div_numerator:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_root_clk_ctrl2_reg_t;
+
+/** Type of root_clk_ctrl3 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_apb_clk_div_denominator : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_apb_clk_div_denominator:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_sys_clkrst_root_clk_ctrl3_reg_t;
+
+
+/** Group: soc_clk_ctrl */
+/** Type of soc_clk_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_core0_clic_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_core0_clic_clk_en:1;
+        /** reg_core1_clic_clk_en : R/W; bitpos: [1]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_core1_clic_clk_en:1;
+        /** reg_misc_cpu_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_misc_cpu_clk_en:1;
+        /** reg_core0_cpu_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_core0_cpu_clk_en:1;
+        /** reg_core1_cpu_clk_en : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_core1_cpu_clk_en:1;
+        /** reg_tcm_cpu_clk_en : R/W; bitpos: [5]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_tcm_cpu_clk_en:1;
+        /** reg_busmon_cpu_clk_en : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_busmon_cpu_clk_en:1;
+        /** reg_l1cache_cpu_clk_en : R/W; bitpos: [7]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_cpu_clk_en:1;
+        /** reg_l1cache_d_cpu_clk_en : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_d_cpu_clk_en:1;
+        /** reg_l1cache_i0_cpu_clk_en : R/W; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i0_cpu_clk_en:1;
+        /** reg_l1cache_i1_cpu_clk_en : R/W; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i1_cpu_clk_en:1;
+        /** reg_trace_cpu_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_trace_cpu_clk_en:1;
+        /** reg_icm_cpu_clk_en : R/W; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_icm_cpu_clk_en:1;
+        /** reg_gdma_cpu_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gdma_cpu_clk_en:1;
+        /** reg_vpu_cpu_clk_en : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_vpu_cpu_clk_en:1;
+        /** reg_l1cache_mem_clk_en : R/W; bitpos: [15]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_mem_clk_en:1;
+        /** reg_l1cache_d_mem_clk_en : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_d_mem_clk_en:1;
+        /** reg_l1cache_i0_mem_clk_en : R/W; bitpos: [17]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i0_mem_clk_en:1;
+        /** reg_l1cache_i1_mem_clk_en : R/W; bitpos: [18]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i1_mem_clk_en:1;
+        /** reg_l2cache_mem_clk_en : R/W; bitpos: [19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_mem_clk_en:1;
+        /** reg_l2mem_mem_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2mem_mem_clk_en:1;
+        /** reg_l2memmon_mem_clk_en : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_l2memmon_mem_clk_en:1;
+        /** reg_icm_mem_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_icm_mem_clk_en:1;
+        /** reg_misc_sys_clk_en : R/W; bitpos: [23]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_misc_sys_clk_en:1;
+        /** reg_trace_sys_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_trace_sys_clk_en:1;
+        /** reg_l2cache_sys_clk_en : R/W; bitpos: [25]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_sys_clk_en:1;
+        /** reg_l2mem_sys_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2mem_sys_clk_en:1;
+        /** reg_l2memmon_sys_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_l2memmon_sys_clk_en:1;
+        /** reg_tcmmon_sys_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tcmmon_sys_clk_en:1;
+        /** reg_icm_sys_clk_en : R/W; bitpos: [29]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_icm_sys_clk_en:1;
+        /** reg_flash_sys_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_flash_sys_clk_en:1;
+        /** reg_psram_sys_clk_en : R/W; bitpos: [31]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_psram_sys_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_soc_clk_ctrl0_reg_t;
+
+/** Type of soc_clk_ctrl1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpspi2_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_sys_clk_en:1;
+        /** reg_gpspi3_sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_sys_clk_en:1;
+        /** reg_regdma_sys_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_regdma_sys_clk_en:1;
+        /** reg_ahb_pdma_sys_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ahb_pdma_sys_clk_en:1;
+        /** reg_axi_pdma_sys_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_axi_pdma_sys_clk_en:1;
+        /** reg_gdma_sys_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gdma_sys_clk_en:1;
+        /** reg_dma2d_sys_clk_en : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dma2d_sys_clk_en:1;
+        /** reg_vpu_sys_clk_en : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_vpu_sys_clk_en:1;
+        /** reg_jpeg_sys_clk_en : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_jpeg_sys_clk_en:1;
+        /** reg_ppa_sys_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ppa_sys_clk_en:1;
+        /** reg_csi_brg_sys_clk_en : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_csi_brg_sys_clk_en:1;
+        /** reg_csi_host_sys_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_csi_host_sys_clk_en:1;
+        /** reg_dsi_sys_clk_en : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dsi_sys_clk_en:1;
+        /** reg_emac_sys_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_sys_clk_en:1;
+        /** reg_sdmmc_sys_clk_en : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdmmc_sys_clk_en:1;
+        /** reg_usb_otg11_sys_clk_en : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_usb_otg11_sys_clk_en:1;
+        /** reg_usb_otg20_sys_clk_en : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_usb_otg20_sys_clk_en:1;
+        /** reg_uhci_sys_clk_en : R/W; bitpos: [17]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uhci_sys_clk_en:1;
+        /** reg_uart0_sys_clk_en : R/W; bitpos: [18]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart0_sys_clk_en:1;
+        /** reg_uart1_sys_clk_en : R/W; bitpos: [19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart1_sys_clk_en:1;
+        /** reg_uart2_sys_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart2_sys_clk_en:1;
+        /** reg_uart3_sys_clk_en : R/W; bitpos: [21]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart3_sys_clk_en:1;
+        /** reg_uart4_sys_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart4_sys_clk_en:1;
+        /** reg_parlio_sys_clk_en : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_sys_clk_en:1;
+        /** reg_etm_sys_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_etm_sys_clk_en:1;
+        /** reg_pvt_sys_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_sys_clk_en:1;
+        /** reg_crypto_sys_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_sys_clk_en:1;
+        /** reg_key_manager_sys_clk_en : R/W; bitpos: [27]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_key_manager_sys_clk_en:1;
+        /** reg_bitscrambler_sys_clk_en : R/W; bitpos: [28]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_bitscrambler_sys_clk_en:1;
+        /** reg_bitscrambler_rx_sys_clk_en : R/W; bitpos: [29]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_bitscrambler_rx_sys_clk_en:1;
+        /** reg_bitscrambler_tx_sys_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_bitscrambler_tx_sys_clk_en:1;
+        /** reg_h264_sys_clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_h264_sys_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_soc_clk_ctrl1_reg_t;
+
+/** Type of soc_clk_ctrl2 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_rmt_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_sys_clk_en:1;
+        /** reg_hp_clkrst_apb_clk_en : R/W; bitpos: [1]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_hp_clkrst_apb_clk_en:1;
+        /** reg_sysreg_apb_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_sysreg_apb_clk_en:1;
+        /** reg_icm_apb_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_icm_apb_clk_en:1;
+        /** reg_intrmtx_apb_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_intrmtx_apb_clk_en:1;
+        /** reg_adc_apb_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_apb_clk_en:1;
+        /** reg_uhci_apb_clk_en : R/W; bitpos: [6]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uhci_apb_clk_en:1;
+        /** reg_uart0_apb_clk_en : R/W; bitpos: [7]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart0_apb_clk_en:1;
+        /** reg_uart1_apb_clk_en : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart1_apb_clk_en:1;
+        /** reg_uart2_apb_clk_en : R/W; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart2_apb_clk_en:1;
+        /** reg_uart3_apb_clk_en : R/W; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart3_apb_clk_en:1;
+        /** reg_uart4_apb_clk_en : R/W; bitpos: [11]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart4_apb_clk_en:1;
+        /** reg_i2c0_apb_clk_en : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_apb_clk_en:1;
+        /** reg_i2c1_apb_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_apb_clk_en:1;
+        /** reg_i2s0_apb_clk_en : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_apb_clk_en:1;
+        /** reg_i2s1_apb_clk_en : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_apb_clk_en:1;
+        /** reg_i2s2_apb_clk_en : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_apb_clk_en:1;
+        /** reg_i3c_mst_apb_clk_en : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_mst_apb_clk_en:1;
+        /** reg_i3c_slv_apb_clk_en : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_slv_apb_clk_en:1;
+        /** reg_gpspi2_apb_clk_en : R/W; bitpos: [19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_apb_clk_en:1;
+        /** reg_gpspi3_apb_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_apb_clk_en:1;
+        /** reg_timergrp0_apb_clk_en : R/W; bitpos: [21]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_apb_clk_en:1;
+        /** reg_timergrp1_apb_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_apb_clk_en:1;
+        /** reg_systimer_apb_clk_en : R/W; bitpos: [23]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_systimer_apb_clk_en:1;
+        /** reg_twai0_apb_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai0_apb_clk_en:1;
+        /** reg_twai1_apb_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai1_apb_clk_en:1;
+        /** reg_twai2_apb_clk_en : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai2_apb_clk_en:1;
+        /** reg_mcpwm0_apb_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm0_apb_clk_en:1;
+        /** reg_mcpwm1_apb_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm1_apb_clk_en:1;
+        /** reg_usb_device_apb_clk_en : R/W; bitpos: [29]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_usb_device_apb_clk_en:1;
+        /** reg_pcnt_apb_clk_en : R/W; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pcnt_apb_clk_en:1;
+        /** reg_parlio_apb_clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_apb_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_soc_clk_ctrl2_reg_t;
+
+/** Type of soc_clk_ctrl3 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ledc_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ledc_apb_clk_en:1;
+        /** reg_lcdcam_apb_clk_en : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcdcam_apb_clk_en:1;
+        /** reg_etm_apb_clk_en : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_etm_apb_clk_en:1;
+        /** reg_iomux_apb_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_iomux_apb_clk_en:1;
+        /** reg_l2cache_l2mem_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_l2mem_clk_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_sys_clkrst_soc_clk_ctrl3_reg_t;
+
+
+/** Group: ref_clk_ctrl */
+/** Type of ref_clk_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ref_50m_clk_div_num : R/W; bitpos: [7:0]; default: 9;
+         *  Reserved
+         */
+        uint32_t reg_ref_50m_clk_div_num:8;
+        /** reg_ref_25m_clk_div_num : R/W; bitpos: [15:8]; default: 19;
+         *  Reserved
+         */
+        uint32_t reg_ref_25m_clk_div_num:8;
+        /** reg_ref_240m_clk_div_num : R/W; bitpos: [23:16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_240m_clk_div_num:8;
+        /** reg_ref_160m_clk_div_num : R/W; bitpos: [31:24]; default: 2;
+         *  Reserved
+         */
+        uint32_t reg_ref_160m_clk_div_num:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_clk_ctrl0_reg_t;
+
+/** Type of ref_clk_ctrl1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ref_120m_clk_div_num : R/W; bitpos: [7:0]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_ref_120m_clk_div_num:8;
+        /** reg_ref_80m_clk_div_num : R/W; bitpos: [15:8]; default: 5;
+         *  Reserved
+         */
+        uint32_t reg_ref_80m_clk_div_num:8;
+        /** reg_ref_20m_clk_div_num : R/W; bitpos: [23:16]; default: 23;
+         *  Reserved
+         */
+        uint32_t reg_ref_20m_clk_div_num:8;
+        /** reg_tm_400m_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_400m_clk_en:1;
+        /** reg_tm_200m_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_200m_clk_en:1;
+        /** reg_tm_100m_clk_en : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_100m_clk_en:1;
+        /** reg_ref_50m_clk_en : R/W; bitpos: [27]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_50m_clk_en:1;
+        /** reg_ref_25m_clk_en : R/W; bitpos: [28]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_25m_clk_en:1;
+        /** reg_tm_480m_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_480m_clk_en:1;
+        /** reg_ref_240m_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_240m_clk_en:1;
+        /** reg_tm_240m_clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_240m_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_clk_ctrl1_reg_t;
+
+/** Type of ref_clk_ctrl2 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ref_160m_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_160m_clk_en:1;
+        /** reg_tm_160m_clk_en : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_160m_clk_en:1;
+        /** reg_ref_120m_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_120m_clk_en:1;
+        /** reg_tm_120m_clk_en : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_120m_clk_en:1;
+        /** reg_ref_80m_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_80m_clk_en:1;
+        /** reg_tm_80m_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_80m_clk_en:1;
+        /** reg_tm_60m_clk_en : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_60m_clk_en:1;
+        /** reg_tm_48m_clk_en : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_48m_clk_en:1;
+        /** reg_ref_20m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_ref_20m_clk_en:1;
+        /** reg_tm_20m_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_tm_20m_clk_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_clk_ctrl2_reg_t;
+
+
+/** Group: peri_clk_ctrl0 */
+/** Type of peri_clk_ctrl00 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_flash_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_flash_clk_src_sel:2;
+        /** reg_flash_pll_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_flash_pll_clk_en:1;
+        /** reg_flash_core_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_flash_core_clk_en:1;
+        /** reg_flash_core_clk_div_num : R/W; bitpos: [11:4]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_flash_core_clk_div_num:8;
+        /** reg_psram_clk_src_sel : R/W; bitpos: [13:12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_clk_src_sel:2;
+        /** reg_psram_pll_clk_en : R/W; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_psram_pll_clk_en:1;
+        /** reg_psram_core_clk_en : R/W; bitpos: [15]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_psram_core_clk_en:1;
+        /** reg_psram_core_clk_div_num : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_core_clk_div_num:8;
+        /** reg_pad_emac_ref_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pad_emac_ref_clk_en:1;
+        /** reg_emac_rmii_clk_src_sel : R/W; bitpos: [26:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_rmii_clk_src_sel:2;
+        /** reg_emac_rmii_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_rmii_clk_en:1;
+        /** reg_emac_rx_clk_src_sel : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_rx_clk_src_sel:1;
+        /** reg_emac_rx_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_rx_clk_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl00_reg_t;
+
+/** Type of peri_clk_ctrl01 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_emac_rx_clk_div_num : R/W; bitpos: [7:0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_emac_rx_clk_div_num:8;
+        /** reg_emac_tx_clk_src_sel : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_tx_clk_src_sel:1;
+        /** reg_emac_tx_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_tx_clk_en:1;
+        /** reg_emac_tx_clk_div_num : R/W; bitpos: [17:10]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_emac_tx_clk_div_num:8;
+        /** reg_emac_ptp_ref_clk_src_sel : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_ptp_ref_clk_src_sel:1;
+        /** reg_emac_ptp_ref_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_ptp_ref_clk_en:1;
+        /** reg_emac_unused0_clk_en : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_unused0_clk_en:1;
+        /** reg_emac_unused1_clk_en : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_emac_unused1_clk_en:1;
+        /** reg_sdio_hs_mode : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_hs_mode:1;
+        /** reg_sdio_ls_clk_src_sel : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_src_sel:1;
+        /** reg_sdio_ls_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl01_reg_t;
+
+/** Type of peri_clk_ctrl02 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_sdio_ls_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_div_num:8;
+        /** reg_sdio_ls_clk_edge_cfg_update : WT; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_edge_cfg_update:1;
+        /** reg_sdio_ls_clk_edge_l : R/W; bitpos: [12:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_edge_l:4;
+        /** reg_sdio_ls_clk_edge_h : R/W; bitpos: [16:13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_edge_h:4;
+        /** reg_sdio_ls_clk_edge_n : R/W; bitpos: [20:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_clk_edge_n:4;
+        /** reg_sdio_ls_slf_clk_edge_sel : R/W; bitpos: [22:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_slf_clk_edge_sel:2;
+        /** reg_sdio_ls_drv_clk_edge_sel : R/W; bitpos: [24:23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_drv_clk_edge_sel:2;
+        /** reg_sdio_ls_sam_clk_edge_sel : R/W; bitpos: [26:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_sam_clk_edge_sel:2;
+        /** reg_sdio_ls_slf_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_slf_clk_en:1;
+        /** reg_sdio_ls_drv_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_drv_clk_en:1;
+        /** reg_sdio_ls_sam_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_ls_sam_clk_en:1;
+        /** reg_mipi_dsi_dphy_clk_src_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_clk_src_sel:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl02_reg_t;
+
+/** Type of peri_clk_ctrl03 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_mipi_dsi_dphy_cfg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_cfg_clk_en:1;
+        /** reg_mipi_dsi_dphy_pll_refclk_en : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_pll_refclk_en:1;
+        /** reg_mipi_csi_dphy_clk_src_sel : R/W; bitpos: [3:2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_csi_dphy_clk_src_sel:2;
+        /** reg_mipi_csi_dphy_cfg_clk_en : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_csi_dphy_cfg_clk_en:1;
+        /** reg_mipi_dsi_dpiclk_src_sel : R/W; bitpos: [6:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dpiclk_src_sel:2;
+        /** reg_mipi_dsi_dpiclk_en : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dpiclk_en:1;
+        /** reg_mipi_dsi_dpiclk_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dpiclk_div_num:8;
+        /** reg_mipi_dsi_dphy_pll_refclk_src_sel : R/W; bitpos: [18:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_pll_refclk_src_sel:3;
+        /** reg_mipi_dsi_dphy_pll_refclk_div_num : R/W; bitpos: [26:19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_mipi_dsi_dphy_pll_refclk_div_num:8;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl03_reg_t;
+
+
+/** Group: peri_clk_ctrl1 */
+/** Type of peri_clk_ctrl10 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2c0_clk_src_sel : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_src_sel:1;
+        /** reg_i2c0_clk_en : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_en:1;
+        /** reg_i2c0_clk_div_num : R/W; bitpos: [9:2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_div_num:8;
+        /** reg_i2c0_clk_div_numerator : R/W; bitpos: [17:10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_div_numerator:8;
+        /** reg_i2c0_clk_div_denominator : R/W; bitpos: [25:18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c0_clk_div_denominator:8;
+        /** reg_i2c1_clk_src_sel : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_src_sel:1;
+        /** reg_i2c1_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_en:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl10_reg_t;
+
+/** Type of peri_clk_ctrl11 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2c1_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_div_num:8;
+        /** reg_i2c1_clk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_div_numerator:8;
+        /** reg_i2c1_clk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2c1_clk_div_denominator:8;
+        /** reg_i2s0_rx_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_clk_en:1;
+        /** reg_i2s0_rx_clk_src_sel : R/W; bitpos: [26:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_clk_src_sel:2;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl11_reg_t;
+
+/** Type of peri_clk_ctrl12 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_rx_div_n : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_n:8;
+        /** reg_i2s0_rx_div_x : R/W; bitpos: [16:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_x:9;
+        /** reg_i2s0_rx_div_y : R/W; bitpos: [25:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_y:9;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl12_reg_t;
+
+/** Type of peri_clk_ctrl13 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_rx_div_z : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_z:9;
+        /** reg_i2s0_rx_div_yn1 : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_rx_div_yn1:1;
+        /** reg_i2s0_tx_clk_en : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_clk_en:1;
+        /** reg_i2s0_tx_clk_src_sel : R/W; bitpos: [12:11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_clk_src_sel:2;
+        /** reg_i2s0_tx_div_n : R/W; bitpos: [20:13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_n:8;
+        /** reg_i2s0_tx_div_x : R/W; bitpos: [29:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_x:9;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl13_reg_t;
+
+/** Type of peri_clk_ctrl14 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_tx_div_y : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_y:9;
+        /** reg_i2s0_tx_div_z : R/W; bitpos: [17:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_z:9;
+        /** reg_i2s0_tx_div_yn1 : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_tx_div_yn1:1;
+        /** reg_i2s0_mst_clk_sel : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s0_mst_clk_sel:1;
+        /** reg_i2s1_rx_clk_en : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_clk_en:1;
+        /** reg_i2s1_rx_clk_src_sel : R/W; bitpos: [22:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_clk_src_sel:2;
+        /** reg_i2s1_rx_div_n : R/W; bitpos: [30:23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_n:8;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl14_reg_t;
+
+/** Type of peri_clk_ctrl15 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_rx_div_x : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_x:9;
+        /** reg_i2s1_rx_div_y : R/W; bitpos: [17:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_y:9;
+        /** reg_i2s1_rx_div_z : R/W; bitpos: [26:18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_z:9;
+        /** reg_i2s1_rx_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_rx_div_yn1:1;
+        /** reg_i2s1_tx_clk_en : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_clk_en:1;
+        /** reg_i2s1_tx_clk_src_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_clk_src_sel:2;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl15_reg_t;
+
+/** Type of peri_clk_ctrl16 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_tx_div_n : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_n:8;
+        /** reg_i2s1_tx_div_x : R/W; bitpos: [16:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_x:9;
+        /** reg_i2s1_tx_div_y : R/W; bitpos: [25:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_y:9;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl16_reg_t;
+
+/** Type of peri_clk_ctrl17 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_tx_div_z : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_z:9;
+        /** reg_i2s1_tx_div_yn1 : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_tx_div_yn1:1;
+        /** reg_i2s1_mst_clk_sel : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s1_mst_clk_sel:1;
+        /** reg_i2s2_rx_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_clk_en:1;
+        /** reg_i2s2_rx_clk_src_sel : R/W; bitpos: [13:12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_clk_src_sel:2;
+        /** reg_i2s2_rx_div_n : R/W; bitpos: [21:14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_n:8;
+        /** reg_i2s2_rx_div_x : R/W; bitpos: [30:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_x:9;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl17_reg_t;
+
+/** Type of peri_clk_ctrl18 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s2_rx_div_y : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_y:9;
+        /** reg_i2s2_rx_div_z : R/W; bitpos: [17:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_z:9;
+        /** reg_i2s2_rx_div_yn1 : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_rx_div_yn1:1;
+        /** reg_i2s2_tx_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_clk_en:1;
+        /** reg_i2s2_tx_clk_src_sel : R/W; bitpos: [21:20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_clk_src_sel:2;
+        /** reg_i2s2_tx_div_n : R/W; bitpos: [29:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_n:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl18_reg_t;
+
+/** Type of peri_clk_ctrl19 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_i2s2_tx_div_x : R/W; bitpos: [8:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_x:9;
+        /** reg_i2s2_tx_div_y : R/W; bitpos: [17:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_y:9;
+        /** reg_i2s2_tx_div_z : R/W; bitpos: [26:18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_z:9;
+        /** reg_i2s2_tx_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_tx_div_yn1:1;
+        /** reg_i2s2_mst_clk_sel : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i2s2_mst_clk_sel:1;
+        /** reg_lcd_clk_src_sel : R/W; bitpos: [30:29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_src_sel:2;
+        /** reg_lcd_clk_en : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl19_reg_t;
+
+/** Type of peri_clk_ctrl110 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_lcd_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_div_num:8;
+        /** reg_lcd_clk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_div_numerator:8;
+        /** reg_lcd_clk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_lcd_clk_div_denominator:8;
+        /** reg_uart0_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart0_clk_src_sel:2;
+        /** reg_uart0_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart0_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl110_reg_t;
+
+/** Type of peri_clk_ctrl111 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart0_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart0_sclk_div_num:8;
+        /** reg_uart0_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart0_sclk_div_numerator:8;
+        /** reg_uart0_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart0_sclk_div_denominator:8;
+        /** reg_uart1_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart1_clk_src_sel:2;
+        /** reg_uart1_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart1_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl111_reg_t;
+
+/** Type of peri_clk_ctrl112 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart1_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart1_sclk_div_num:8;
+        /** reg_uart1_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart1_sclk_div_numerator:8;
+        /** reg_uart1_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart1_sclk_div_denominator:8;
+        /** reg_uart2_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart2_clk_src_sel:2;
+        /** reg_uart2_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart2_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl112_reg_t;
+
+/** Type of peri_clk_ctrl113 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart2_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart2_sclk_div_num:8;
+        /** reg_uart2_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart2_sclk_div_numerator:8;
+        /** reg_uart2_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart2_sclk_div_denominator:8;
+        /** reg_uart3_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart3_clk_src_sel:2;
+        /** reg_uart3_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart3_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl113_reg_t;
+
+/** Type of peri_clk_ctrl114 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart3_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart3_sclk_div_num:8;
+        /** reg_uart3_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart3_sclk_div_numerator:8;
+        /** reg_uart3_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart3_sclk_div_denominator:8;
+        /** reg_uart4_clk_src_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart4_clk_src_sel:2;
+        /** reg_uart4_clk_en : R/W; bitpos: [26]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_uart4_clk_en:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl114_reg_t;
+
+/** Type of peri_clk_ctrl115 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_uart4_sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart4_sclk_div_num:8;
+        /** reg_uart4_sclk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart4_sclk_div_numerator:8;
+        /** reg_uart4_sclk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_uart4_sclk_div_denominator:8;
+        /** reg_twai0_clk_src_sel : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai0_clk_src_sel:1;
+        /** reg_twai0_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai0_clk_en:1;
+        /** reg_twai1_clk_src_sel : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai1_clk_src_sel:1;
+        /** reg_twai1_clk_en : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai1_clk_en:1;
+        /** reg_twai2_clk_src_sel : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai2_clk_src_sel:1;
+        /** reg_twai2_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_twai2_clk_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl115_reg_t;
+
+/** Type of peri_clk_ctrl116 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpspi2_clk_src_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_clk_src_sel:3;
+        /** reg_gpspi2_hs_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_hs_clk_en:1;
+        /** reg_gpspi2_hs_clk_div_num : R/W; bitpos: [11:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_hs_clk_div_num:8;
+        /** reg_gpspi2_mst_clk_div_num : R/W; bitpos: [19:12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_mst_clk_div_num:8;
+        /** reg_gpspi2_mst_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi2_mst_clk_en:1;
+        /** reg_gpspi3_clk_src_sel : R/W; bitpos: [23:21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_clk_src_sel:3;
+        /** reg_gpspi3_hs_clk_en : R/W; bitpos: [24]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_hs_clk_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl116_reg_t;
+
+/** Type of peri_clk_ctrl117 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_gpspi3_hs_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_hs_clk_div_num:8;
+        /** reg_gpspi3_mst_clk_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_mst_clk_div_num:8;
+        /** reg_gpspi3_mst_clk_en : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gpspi3_mst_clk_en:1;
+        /** reg_parlio_rx_clk_src_sel : R/W; bitpos: [18:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_src_sel:2;
+        /** reg_parlio_rx_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_en:1;
+        /** reg_parlio_rx_clk_div_num : R/W; bitpos: [27:20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_div_num:8;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl117_reg_t;
+
+/** Type of peri_clk_ctrl118 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_parlio_rx_clk_div_numerator : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_div_numerator:8;
+        /** reg_parlio_rx_clk_div_denominator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_rx_clk_div_denominator:8;
+        /** reg_parlio_tx_clk_src_sel : R/W; bitpos: [17:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_src_sel:2;
+        /** reg_parlio_tx_clk_en : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_en:1;
+        /** reg_parlio_tx_clk_div_num : R/W; bitpos: [26:19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_div_num:8;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl118_reg_t;
+
+/** Type of peri_clk_ctrl119 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_parlio_tx_clk_div_numerator : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_div_numerator:8;
+        /** reg_parlio_tx_clk_div_denominator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_parlio_tx_clk_div_denominator:8;
+        /** reg_i3c_mst_clk_src_sel : R/W; bitpos: [17:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_mst_clk_src_sel:2;
+        /** reg_i3c_mst_clk_en : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_mst_clk_en:1;
+        /** reg_i3c_mst_clk_div_num : R/W; bitpos: [26:19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_i3c_mst_clk_div_num:8;
+        /** reg_cam_clk_src_sel : R/W; bitpos: [28:27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_src_sel:2;
+        /** reg_cam_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl119_reg_t;
+
+/** Type of peri_clk_ctrl120 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_cam_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_div_num:8;
+        /** reg_cam_clk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_div_numerator:8;
+        /** reg_cam_clk_div_denominator : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cam_clk_div_denominator:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl120_reg_t;
+
+
+/** Group: peri_clk_ctrl2 */
+/** Type of peri_clk_ctrl20 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_mcpwm0_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm0_clk_src_sel:2;
+        /** reg_mcpwm0_clk_en : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm0_clk_en:1;
+        /** reg_mcpwm0_clk_div_num : R/W; bitpos: [10:3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm0_clk_div_num:8;
+        /** reg_mcpwm1_clk_src_sel : R/W; bitpos: [12:11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm1_clk_src_sel:2;
+        /** reg_mcpwm1_clk_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm1_clk_en:1;
+        /** reg_mcpwm1_clk_div_num : R/W; bitpos: [21:14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mcpwm1_clk_div_num:8;
+        /** reg_timergrp0_t0_src_sel : R/W; bitpos: [23:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_t0_src_sel:2;
+        /** reg_timergrp0_t0_clk_en : R/W; bitpos: [24]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_t0_clk_en:1;
+        /** reg_timergrp0_t1_src_sel : R/W; bitpos: [26:25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_t1_src_sel:2;
+        /** reg_timergrp0_t1_clk_en : R/W; bitpos: [27]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_t1_clk_en:1;
+        /** reg_timergrp0_wdt_src_sel : R/W; bitpos: [29:28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_wdt_src_sel:2;
+        /** reg_timergrp0_wdt_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_wdt_clk_en:1;
+        /** reg_timergrp0_tgrt_clk_en : R/W; bitpos: [31]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_tgrt_clk_en:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl20_reg_t;
+
+/** Type of peri_clk_ctrl21 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_timergrp0_tgrt_clk_src_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_tgrt_clk_src_sel:4;
+        /** reg_timergrp0_tgrt_clk_div_num : R/W; bitpos: [19:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp0_tgrt_clk_div_num:16;
+        /** reg_timergrp1_t0_src_sel : R/W; bitpos: [21:20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_t0_src_sel:2;
+        /** reg_timergrp1_t0_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_t0_clk_en:1;
+        /** reg_timergrp1_t1_src_sel : R/W; bitpos: [24:23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_t1_src_sel:2;
+        /** reg_timergrp1_t1_clk_en : R/W; bitpos: [25]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_t1_clk_en:1;
+        /** reg_timergrp1_wdt_src_sel : R/W; bitpos: [27:26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_wdt_src_sel:2;
+        /** reg_timergrp1_wdt_clk_en : R/W; bitpos: [28]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_timergrp1_wdt_clk_en:1;
+        /** reg_systimer_clk_src_sel : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_systimer_clk_src_sel:1;
+        /** reg_systimer_clk_en : R/W; bitpos: [30]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_systimer_clk_en:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl21_reg_t;
+
+/** Type of peri_clk_ctrl22 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_ledc_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ledc_clk_src_sel:2;
+        /** reg_ledc_clk_en : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_ledc_clk_en:1;
+        /** reg_rmt_clk_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_src_sel:2;
+        /** reg_rmt_clk_en : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_en:1;
+        /** reg_rmt_clk_div_num : R/W; bitpos: [13:6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_div_num:8;
+        /** reg_rmt_clk_div_numerator : R/W; bitpos: [21:14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_div_numerator:8;
+        /** reg_rmt_clk_div_denominator : R/W; bitpos: [29:22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rmt_clk_div_denominator:8;
+        /** reg_adc_clk_src_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_src_sel:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl22_reg_t;
+
+/** Type of peri_clk_ctrl23 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_adc_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_en:1;
+        /** reg_adc_clk_div_num : R/W; bitpos: [8:1]; default: 4;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_div_num:8;
+        /** reg_adc_clk_div_numerator : R/W; bitpos: [16:9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_div_numerator:8;
+        /** reg_adc_clk_div_denominator : R/W; bitpos: [24:17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_adc_clk_div_denominator:8;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl23_reg_t;
+
+/** Type of peri_clk_ctrl24 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_adc_sar1_clk_div_num : R/W; bitpos: [7:0]; default: 4;
+         *  Reserved
+         */
+        uint32_t reg_adc_sar1_clk_div_num:8;
+        /** reg_adc_sar2_clk_div_num : R/W; bitpos: [15:8]; default: 4;
+         *  Reserved
+         */
+        uint32_t reg_adc_sar2_clk_div_num:8;
+        /** reg_pvt_clk_div_num : R/W; bitpos: [23:16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_clk_div_num:8;
+        /** reg_pvt_clk_en : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_clk_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl24_reg_t;
+
+/** Type of peri_clk_ctrl25 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_pvt_peri_group_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group_clk_div_num:8;
+        /** reg_pvt_peri_group1_clk_en : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group1_clk_en:1;
+        /** reg_pvt_peri_group2_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group2_clk_en:1;
+        /** reg_pvt_peri_group3_clk_en : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group3_clk_en:1;
+        /** reg_pvt_peri_group4_clk_en : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_pvt_peri_group4_clk_en:1;
+        /** reg_crypto_clk_src_sel : R/W; bitpos: [13:12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_crypto_clk_src_sel:2;
+        /** reg_crypto_aes_clk_en : R/W; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_aes_clk_en:1;
+        /** reg_crypto_ds_clk_en : R/W; bitpos: [15]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_ds_clk_en:1;
+        /** reg_crypto_ecc_clk_en : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_ecc_clk_en:1;
+        /** reg_crypto_hmac_clk_en : R/W; bitpos: [17]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_hmac_clk_en:1;
+        /** reg_crypto_rsa_clk_en : R/W; bitpos: [18]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_rsa_clk_en:1;
+        /** reg_crypto_sec_clk_en : R/W; bitpos: [19]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_sec_clk_en:1;
+        /** reg_crypto_sha_clk_en : R/W; bitpos: [20]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_sha_clk_en:1;
+        /** reg_crypto_ecdsa_clk_en : R/W; bitpos: [21]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_ecdsa_clk_en:1;
+        /** reg_crypto_km_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_crypto_km_clk_en:1;
+        /** reg_isp_clk_src_sel : R/W; bitpos: [24:23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_isp_clk_src_sel:2;
+        /** reg_isp_clk_en : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_isp_clk_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl25_reg_t;
+
+/** Type of peri_clk_ctrl26 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_isp_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_isp_clk_div_num:8;
+        /** reg_iomux_clk_src_sel : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_iomux_clk_src_sel:1;
+        /** reg_iomux_clk_en : R/W; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_iomux_clk_en:1;
+        /** reg_iomux_clk_div_num : R/W; bitpos: [17:10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_iomux_clk_div_num:8;
+        /** reg_h264_clk_src_sel : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_h264_clk_src_sel:1;
+        /** reg_h264_clk_en : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_h264_clk_en:1;
+        /** reg_h264_clk_div_num : R/W; bitpos: [27:20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_h264_clk_div_num:8;
+        /** reg_padbist_rx_clk_src_sel : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_rx_clk_src_sel:1;
+        /** reg_padbist_rx_clk_en : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_rx_clk_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl26_reg_t;
+
+/** Type of peri_clk_ctrl27 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_padbist_rx_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_rx_clk_div_num:8;
+        /** reg_padbist_tx_clk_src_sel : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_tx_clk_src_sel:1;
+        /** reg_padbist_tx_clk_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_tx_clk_en:1;
+        /** reg_padbist_tx_clk_div_num : R/W; bitpos: [17:10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_padbist_tx_clk_div_num:8;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_sys_clkrst_peri_clk_ctrl27_reg_t;
+
+
+/** Group: clk_force_on_ctrl */
+/** Type of clk_force_on_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_cpuicm_gated_clk_force_on : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_cpuicm_gated_clk_force_on:1;
+        /** reg_tcm_cpu_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_tcm_cpu_clk_force_on:1;
+        /** reg_busmon_cpu_clk_force_on : R/W; bitpos: [2]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_busmon_cpu_clk_force_on:1;
+        /** reg_l1cache_cpu_clk_force_on : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_cpu_clk_force_on:1;
+        /** reg_l1cache_d_cpu_clk_force_on : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_d_cpu_clk_force_on:1;
+        /** reg_l1cache_i0_cpu_clk_force_on : R/W; bitpos: [5]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i0_cpu_clk_force_on:1;
+        /** reg_l1cache_i1_cpu_clk_force_on : R/W; bitpos: [6]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i1_cpu_clk_force_on:1;
+        /** reg_trace_cpu_clk_force_on : R/W; bitpos: [7]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_trace_cpu_clk_force_on:1;
+        /** reg_trace_sys_clk_force_on : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_trace_sys_clk_force_on:1;
+        /** reg_l1cache_mem_clk_force_on : R/W; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_mem_clk_force_on:1;
+        /** reg_l1cache_d_mem_clk_force_on : R/W; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_d_mem_clk_force_on:1;
+        /** reg_l1cache_i0_mem_clk_force_on : R/W; bitpos: [11]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i0_mem_clk_force_on:1;
+        /** reg_l1cache_i1_mem_clk_force_on : R/W; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l1cache_i1_mem_clk_force_on:1;
+        /** reg_l2cache_mem_clk_force_on : R/W; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_mem_clk_force_on:1;
+        /** reg_l2mem_mem_clk_force_on : R/W; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2mem_mem_clk_force_on:1;
+        /** reg_sar1_clk_force_on : R/W; bitpos: [15]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_sar1_clk_force_on:1;
+        /** reg_sar2_clk_force_on : R/W; bitpos: [16]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_sar2_clk_force_on:1;
+        /** reg_gmac_tx_clk_force_on : R/W; bitpos: [17]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_gmac_tx_clk_force_on:1;
+        /** reg_l2cache_l2mem_clk_force_on : R/W; bitpos: [18]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_l2cache_l2mem_clk_force_on:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} hp_sys_clkrst_clk_force_on_ctrl0_reg_t;
+
+
+/** Group: dpa_ctrl */
+/** Type of dpa_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sec_dpa_level:2;
+        /** reg_sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sec_dpa_cfg_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dpa_ctrl0_reg_t;
+
+
+/** Group: ana_pll_ctrl */
+/** Type of ana_pll_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_plla_cal_end : RO; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_plla_cal_end:1;
+        /** reg_plla_cal_stop : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_plla_cal_stop:1;
+        /** reg_cpu_pll_cal_end : RO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_pll_cal_end:1;
+        /** reg_cpu_pll_cal_stop : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_cpu_pll_cal_stop:1;
+        /** reg_sdio_pll_cal_end : RO; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_pll_cal_end:1;
+        /** reg_sdio_pll_cal_stop : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sdio_pll_cal_stop:1;
+        /** reg_sys_pll_cal_end : RO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_pll_cal_end:1;
+        /** reg_sys_pll_cal_stop : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_sys_pll_cal_stop:1;
+        /** reg_mspi_cal_end : RO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mspi_cal_end:1;
+        /** reg_mspi_cal_stop : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_mspi_cal_stop:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ana_pll_ctrl0_reg_t;
+
+
+/** Group: hp_rst_en */
+/** Type of hp_rst_en0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_rst_en_corectrl : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_corectrl:1;
+        /** reg_rst_en_pvt_top : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_top:1;
+        /** reg_rst_en_pvt_peri_group1 : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_peri_group1:1;
+        /** reg_rst_en_pvt_peri_group2 : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_peri_group2:1;
+        /** reg_rst_en_pvt_peri_group3 : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_peri_group3:1;
+        /** reg_rst_en_pvt_peri_group4 : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_peri_group4:1;
+        /** reg_rst_en_regdma : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_regdma:1;
+        /** reg_rst_en_core0_global : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_core0_global:1;
+        /** reg_rst_en_core1_global : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_core1_global:1;
+        /** reg_rst_en_coretrace0 : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_coretrace0:1;
+        /** reg_rst_en_coretrace1 : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_coretrace1:1;
+        /** reg_rst_en_hp_tcm : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_hp_tcm:1;
+        /** reg_rst_en_hp_cache : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_hp_cache:1;
+        /** reg_rst_en_l1_i0_cache : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l1_i0_cache:1;
+        /** reg_rst_en_l1_i1_cache : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l1_i1_cache:1;
+        /** reg_rst_en_l1_d_cache : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l1_d_cache:1;
+        /** reg_rst_en_l2_cache : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l2_cache:1;
+        /** reg_rst_en_l2_mem : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l2_mem:1;
+        /** reg_rst_en_l2memmon : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_l2memmon:1;
+        /** reg_rst_en_tcmmon : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_tcmmon:1;
+        /** reg_rst_en_pvt_apb : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pvt_apb:1;
+        /** reg_rst_en_gdma : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_gdma:1;
+        /** reg_rst_en_mspi_axi : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_mspi_axi:1;
+        /** reg_rst_en_dual_mspi_axi : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_dual_mspi_axi:1;
+        /** reg_rst_en_mspi_apb : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_mspi_apb:1;
+        /** reg_rst_en_dual_mspi_apb : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_dual_mspi_apb:1;
+        /** reg_rst_en_dsi_brg : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_dsi_brg:1;
+        /** reg_rst_en_csi_host : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_csi_host:1;
+        /** reg_rst_en_csi_brg : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_csi_brg:1;
+        /** reg_rst_en_isp : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_isp:1;
+        /** reg_rst_en_jpeg : R/W; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_jpeg:1;
+        /** reg_rst_en_dma2d : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_dma2d:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_rst_en0_reg_t;
+
+/** Type of hp_rst_en1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_rst_en_ppa : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ppa:1;
+        /** reg_rst_en_ahb_pdma : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ahb_pdma:1;
+        /** reg_rst_en_axi_pdma : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_axi_pdma:1;
+        /** reg_rst_en_iomux : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_iomux:1;
+        /** reg_rst_en_padbist : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_padbist:1;
+        /** reg_rst_en_stimer : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_stimer:1;
+        /** reg_rst_en_timergrp0 : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_timergrp0:1;
+        /** reg_rst_en_timergrp1 : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_timergrp1:1;
+        /** reg_rst_en_uart0_core : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart0_core:1;
+        /** reg_rst_en_uart1_core : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart1_core:1;
+        /** reg_rst_en_uart2_core : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart2_core:1;
+        /** reg_rst_en_uart3_core : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart3_core:1;
+        /** reg_rst_en_uart4_core : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart4_core:1;
+        /** reg_rst_en_uart0_apb : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart0_apb:1;
+        /** reg_rst_en_uart1_apb : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart1_apb:1;
+        /** reg_rst_en_uart2_apb : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart2_apb:1;
+        /** reg_rst_en_uart3_apb : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart3_apb:1;
+        /** reg_rst_en_uart4_apb : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uart4_apb:1;
+        /** reg_rst_en_uhci : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_uhci:1;
+        /** reg_rst_en_i3cmst : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i3cmst:1;
+        /** reg_rst_en_i3cslv : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i3cslv:1;
+        /** reg_rst_en_i2c1 : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2c1:1;
+        /** reg_rst_en_i2c0 : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2c0:1;
+        /** reg_rst_en_rmt : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_rmt:1;
+        /** reg_rst_en_pwm0 : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pwm0:1;
+        /** reg_rst_en_pwm1 : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pwm1:1;
+        /** reg_rst_en_twai0 : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_twai0:1;
+        /** reg_rst_en_twai1 : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_twai1:1;
+        /** reg_rst_en_twai2 : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_twai2:1;
+        /** reg_rst_en_ledc : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ledc:1;
+        /** reg_rst_en_pcnt : R/W; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_pcnt:1;
+        /** reg_rst_en_etm : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_etm:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_rst_en1_reg_t;
+
+/** Type of hp_rst_en2 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_rst_en_intrmtx : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_intrmtx:1;
+        /** reg_rst_en_parlio : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_parlio:1;
+        /** reg_rst_en_parlio_rx : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_parlio_rx:1;
+        /** reg_rst_en_parlio_tx : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_parlio_tx:1;
+        /** reg_rst_en_i2s0_apb : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2s0_apb:1;
+        /** reg_rst_en_i2s1_apb : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2s1_apb:1;
+        /** reg_rst_en_i2s2_apb : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_i2s2_apb:1;
+        /** reg_rst_en_spi2 : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_spi2:1;
+        /** reg_rst_en_spi3 : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_spi3:1;
+        /** reg_rst_en_lcdcam : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_lcdcam:1;
+        /** reg_rst_en_adc : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_adc:1;
+        /** reg_rst_en_bitscrambler : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_bitscrambler:1;
+        /** reg_rst_en_bitscrambler_rx : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_bitscrambler_rx:1;
+        /** reg_rst_en_bitscrambler_tx : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_bitscrambler_tx:1;
+        /** reg_rst_en_crypto : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_crypto:1;
+        /** reg_rst_en_sec : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_sec:1;
+        /** reg_rst_en_aes : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_aes:1;
+        /** reg_rst_en_ds : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ds:1;
+        /** reg_rst_en_sha : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_sha:1;
+        /** reg_rst_en_hmac : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_hmac:1;
+        /** reg_rst_en_ecdsa : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ecdsa:1;
+        /** reg_rst_en_rsa : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_rsa:1;
+        /** reg_rst_en_ecc : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_ecc:1;
+        /** reg_rst_en_km : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_km:1;
+        /** reg_rst_en_h264 : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_rst_en_h264:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_rst_en2_reg_t;
+
+
+/** Group: hp_force_norst */
+/** Type of hp_force_norst0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_force_norst_core0 : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_core0:1;
+        /** reg_force_norst_core1 : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_core1:1;
+        /** reg_force_norst_coretrace0 : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_coretrace0:1;
+        /** reg_force_norst_coretrace1 : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_coretrace1:1;
+        /** reg_force_norst_l2memmon : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_l2memmon:1;
+        /** reg_force_norst_tcmmon : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_tcmmon:1;
+        /** reg_force_norst_gdma : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_gdma:1;
+        /** reg_force_norst_mspi_axi : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_mspi_axi:1;
+        /** reg_force_norst_dual_mspi_axi : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_dual_mspi_axi:1;
+        /** reg_force_norst_mspi_apb : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_mspi_apb:1;
+        /** reg_force_norst_dual_mspi_apb : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_dual_mspi_apb:1;
+        /** reg_force_norst_dsi_brg : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_dsi_brg:1;
+        /** reg_force_norst_csi_host : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_csi_host:1;
+        /** reg_force_norst_csi_brg : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_csi_brg:1;
+        /** reg_force_norst_isp : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_isp:1;
+        /** reg_force_norst_jpeg : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_jpeg:1;
+        /** reg_force_norst_dma2d : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_dma2d:1;
+        /** reg_force_norst_ppa : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_ppa:1;
+        /** reg_force_norst_ahb_pdma : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_ahb_pdma:1;
+        /** reg_force_norst_axi_pdma : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_axi_pdma:1;
+        /** reg_force_norst_iomux : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_iomux:1;
+        /** reg_force_norst_padbist : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_padbist:1;
+        /** reg_force_norst_stimer : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_stimer:1;
+        /** reg_force_norst_timergrp0 : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_timergrp0:1;
+        /** reg_force_norst_timergrp1 : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_timergrp1:1;
+        /** reg_force_norst_uart0 : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart0:1;
+        /** reg_force_norst_uart1 : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart1:1;
+        /** reg_force_norst_uart2 : R/W; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart2:1;
+        /** reg_force_norst_uart3 : R/W; bitpos: [28]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart3:1;
+        /** reg_force_norst_uart4 : R/W; bitpos: [29]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uart4:1;
+        /** reg_force_norst_uhci : R/W; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_uhci:1;
+        /** reg_force_norst_i3cmst : R/W; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i3cmst:1;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_force_norst0_reg_t;
+
+/** Type of hp_force_norst1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_force_norst_i3cslv : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i3cslv:1;
+        /** reg_force_norst_i2c1 : R/W; bitpos: [1]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2c1:1;
+        /** reg_force_norst_i2c0 : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2c0:1;
+        /** reg_force_norst_rmt : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_rmt:1;
+        /** reg_force_norst_pwm0 : R/W; bitpos: [4]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_pwm0:1;
+        /** reg_force_norst_pwm1 : R/W; bitpos: [5]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_pwm1:1;
+        /** reg_force_norst_can0 : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_can0:1;
+        /** reg_force_norst_can1 : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_can1:1;
+        /** reg_force_norst_can2 : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_can2:1;
+        /** reg_force_norst_ledc : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_ledc:1;
+        /** reg_force_norst_pcnt : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_pcnt:1;
+        /** reg_force_norst_etm : R/W; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_etm:1;
+        /** reg_force_norst_intrmtx : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_intrmtx:1;
+        /** reg_force_norst_parlio : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_parlio:1;
+        /** reg_force_norst_parlio_rx : R/W; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_parlio_rx:1;
+        /** reg_force_norst_parlio_tx : R/W; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_parlio_tx:1;
+        /** reg_force_norst_i2s0 : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2s0:1;
+        /** reg_force_norst_i2s1 : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2s1:1;
+        /** reg_force_norst_i2s2 : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_i2s2:1;
+        /** reg_force_norst_spi2 : R/W; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_spi2:1;
+        /** reg_force_norst_spi3 : R/W; bitpos: [20]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_spi3:1;
+        /** reg_force_norst_lcdcam : R/W; bitpos: [21]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_lcdcam:1;
+        /** reg_force_norst_adc : R/W; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_adc:1;
+        /** reg_force_norst_bitscrambler : R/W; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_bitscrambler:1;
+        /** reg_force_norst_bitscrambler_rx : R/W; bitpos: [24]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_bitscrambler_rx:1;
+        /** reg_force_norst_bitscrambler_tx : R/W; bitpos: [25]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_bitscrambler_tx:1;
+        /** reg_force_norst_h264 : R/W; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_force_norst_h264:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_force_norst1_reg_t;
+
+
+/** Group: hpwdt_core0_rst_ctrl */
+/** Type of hpwdt_core0_rst_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_hpcore0_stall_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_hpcore0_stall_en:1;
+        /** reg_hpcore0_stall_wait_num : R/W; bitpos: [8:1]; default: 8;
+         *  Reserved
+         */
+        uint32_t reg_hpcore0_stall_wait_num:8;
+        /** reg_wdt_hpcore0_rst_len : R/W; bitpos: [16:9]; default: 8;
+         *  Reserved
+         */
+        uint32_t reg_wdt_hpcore0_rst_len:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpwdt_core0_rst_ctrl0_reg_t;
+
+
+/** Group: hpwdt_core1_rst_ctrl */
+/** Type of hpwdt_core1_rst_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_hpcore1_stall_en : R/W; bitpos: [0]; default: 1;
+         *  Reserved
+         */
+        uint32_t reg_hpcore1_stall_en:1;
+        /** reg_hpcore1_stall_wait_num : R/W; bitpos: [8:1]; default: 8;
+         *  Reserved
+         */
+        uint32_t reg_hpcore1_stall_wait_num:8;
+        /** reg_wdt_hpcore1_rst_len : R/W; bitpos: [16:9]; default: 8;
+         *  Reserved
+         */
+        uint32_t reg_wdt_hpcore1_rst_len:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpwdt_core1_rst_ctrl0_reg_t;
+
+
+/** Group: cpu_src_freq */
+/** Type of cpu_src_freq0 register
+ *  CPU Source Frequency
+ */
+typedef union {
+    struct {
+        /** reg_cpu_src_freq : RO; bitpos: [31:0]; default: 0;
+         *  cpu source clock frequency, step by 0.25MHz
+         */
+        uint32_t reg_cpu_src_freq:32;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_src_freq0_reg_t;
+
+
+/** Group: cpu_clk_status */
+/** Type of cpu_clk_status0 register
+ *  CPU Clock Status
+ */
+typedef union {
+    struct {
+        /** reg_asic_or_fpga : RO; bitpos: [0]; default: 0;
+         *  0: ASIC mode, 1: FPGA mode
+         */
+        uint32_t reg_asic_or_fpga:1;
+        /** reg_cpu_div_effect : RO; bitpos: [1]; default: 0;
+         *  0: Divider bypass, 1: Divider takes effect
+         */
+        uint32_t reg_cpu_div_effect:1;
+        /** reg_cpu_src_is_cpll : RO; bitpos: [2]; default: 0;
+         *  0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m
+         */
+        uint32_t reg_cpu_src_is_cpll:1;
+        /** reg_cpu_div_num_cur : RO; bitpos: [10:3]; default: 0;
+         *  cpu current div number
+         */
+        uint32_t reg_cpu_div_num_cur:8;
+        /** reg_cpu_div_numerator_cur : RO; bitpos: [18:11]; default: 0;
+         *  cpu current div numerator
+         */
+        uint32_t reg_cpu_div_numerator_cur:8;
+        /** reg_cpu_div_denominator_cur : RO; bitpos: [26:19]; default: 0;
+         *  cpu current div denominator
+         */
+        uint32_t reg_cpu_div_denominator_cur:8;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_clk_status0_reg_t;
+
+
+/** Group: dbg_clk_ctrl */
+/** Type of dbg_clk_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_dbg_ch0_sel : R/W; bitpos: [7:0]; default: 255;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch0_sel:8;
+        /** reg_dbg_ch1_sel : R/W; bitpos: [15:8]; default: 255;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch1_sel:8;
+        /** reg_dbg_ch2_sel : R/W; bitpos: [23:16]; default: 255;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch2_sel:8;
+        /** reg_dbg_ch0_div_num : R/W; bitpos: [31:24]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch0_div_num:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dbg_clk_ctrl0_reg_t;
+
+/** Type of dbg_clk_ctrl1 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_dbg_ch1_div_num : R/W; bitpos: [7:0]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch1_div_num:8;
+        /** reg_dbg_ch2_div_num : R/W; bitpos: [15:8]; default: 3;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch2_div_num:8;
+        /** reg_dbg_ch0_en : R/W; bitpos: [16]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch0_en:1;
+        /** reg_dbg_ch1_en : R/W; bitpos: [17]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch1_en:1;
+        /** reg_dbg_ch2_en : R/W; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dbg_ch2_en:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dbg_clk_ctrl1_reg_t;
+
+
+/** Group: hpcore_wdt_reset_source */
+/** Type of hpcore_wdt_reset_source0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_hpcore0_wdt_reset_source_sel : R/W; bitpos: [0]; default: 0;
+         *  1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0
+         */
+        uint32_t reg_hpcore0_wdt_reset_source_sel:1;
+        /** reg_hpcore1_wdt_reset_source_sel : R/W; bitpos: [1]; default: 1;
+         *  1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1
+         */
+        uint32_t reg_hpcore1_wdt_reset_source_sel:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpcore_wdt_reset_source0_reg_t;
+
+
+/** Group: axi_perf_mon_clkrst_ctrl */
+/** Type of axi_perf_mon_clkrst_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_axi_perf_mon_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures axi_perf_mon clk enable
+         */
+        uint32_t reg_axi_perf_mon_sys_clk_en:1;
+        /** reg_axi_perf_mon_sys_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Configures axi_perf_mon rst enable
+         */
+        uint32_t reg_axi_perf_mon_sys_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_axi_perf_mon_clkrst_ctrl0_reg_t;
+
+
+/** Group: cpu_waiti_ctrl */
+/** Type of cpu_waiti_ctrl0 register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** reg_core0_waiti_icg_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether cpu core0 waiti signal can control clock gate. If both core0 and
+         *  core1 waiti_icg_en is 1, then only when core0 and core1 all in waiti will close
+         *  related clock
+         */
+        uint32_t reg_core0_waiti_icg_en:1;
+        /** reg_core1_waiti_icg_en : R/W; bitpos: [1]; default: 1;
+         *  Configures whether cpu core1 waiti signal can control clock gate. If both core0 and
+         *  core1 waiti_icg_en is 1, then only when core0 and core1 all in waiti will close
+         *  related clock
+         */
+        uint32_t reg_core1_waiti_icg_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_waiti_ctrl0_reg_t;
+
+
+typedef struct {
+    volatile hp_sys_clkrst_clk_en0_reg_t clk_en0;
+    volatile hp_sys_clkrst_root_clk_ctrl0_reg_t root_clk_ctrl0;
+    volatile hp_sys_clkrst_root_clk_ctrl1_reg_t root_clk_ctrl1;
+    volatile hp_sys_clkrst_root_clk_ctrl2_reg_t root_clk_ctrl2;
+    volatile hp_sys_clkrst_root_clk_ctrl3_reg_t root_clk_ctrl3;
+    volatile hp_sys_clkrst_soc_clk_ctrl0_reg_t soc_clk_ctrl0;
+    volatile hp_sys_clkrst_soc_clk_ctrl1_reg_t soc_clk_ctrl1;
+    volatile hp_sys_clkrst_soc_clk_ctrl2_reg_t soc_clk_ctrl2;
+    volatile hp_sys_clkrst_soc_clk_ctrl3_reg_t soc_clk_ctrl3;
+    volatile hp_sys_clkrst_ref_clk_ctrl0_reg_t ref_clk_ctrl0;
+    volatile hp_sys_clkrst_ref_clk_ctrl1_reg_t ref_clk_ctrl1;
+    volatile hp_sys_clkrst_ref_clk_ctrl2_reg_t ref_clk_ctrl2;
+    volatile hp_sys_clkrst_peri_clk_ctrl00_reg_t peri_clk_ctrl00;
+    volatile hp_sys_clkrst_peri_clk_ctrl01_reg_t peri_clk_ctrl01;
+    volatile hp_sys_clkrst_peri_clk_ctrl02_reg_t peri_clk_ctrl02;
+    volatile hp_sys_clkrst_peri_clk_ctrl03_reg_t peri_clk_ctrl03;
+    volatile hp_sys_clkrst_peri_clk_ctrl10_reg_t peri_clk_ctrl10;
+    volatile hp_sys_clkrst_peri_clk_ctrl11_reg_t peri_clk_ctrl11;
+    volatile hp_sys_clkrst_peri_clk_ctrl12_reg_t peri_clk_ctrl12;
+    volatile hp_sys_clkrst_peri_clk_ctrl13_reg_t peri_clk_ctrl13;
+    volatile hp_sys_clkrst_peri_clk_ctrl14_reg_t peri_clk_ctrl14;
+    volatile hp_sys_clkrst_peri_clk_ctrl15_reg_t peri_clk_ctrl15;
+    volatile hp_sys_clkrst_peri_clk_ctrl16_reg_t peri_clk_ctrl16;
+    volatile hp_sys_clkrst_peri_clk_ctrl17_reg_t peri_clk_ctrl17;
+    volatile hp_sys_clkrst_peri_clk_ctrl18_reg_t peri_clk_ctrl18;
+    volatile hp_sys_clkrst_peri_clk_ctrl19_reg_t peri_clk_ctrl19;
+    volatile hp_sys_clkrst_peri_clk_ctrl110_reg_t peri_clk_ctrl110;
+    volatile hp_sys_clkrst_peri_clk_ctrl111_reg_t peri_clk_ctrl111;
+    volatile hp_sys_clkrst_peri_clk_ctrl112_reg_t peri_clk_ctrl112;
+    volatile hp_sys_clkrst_peri_clk_ctrl113_reg_t peri_clk_ctrl113;
+    volatile hp_sys_clkrst_peri_clk_ctrl114_reg_t peri_clk_ctrl114;
+    volatile hp_sys_clkrst_peri_clk_ctrl115_reg_t peri_clk_ctrl115;
+    volatile hp_sys_clkrst_peri_clk_ctrl116_reg_t peri_clk_ctrl116;
+    volatile hp_sys_clkrst_peri_clk_ctrl117_reg_t peri_clk_ctrl117;
+    volatile hp_sys_clkrst_peri_clk_ctrl118_reg_t peri_clk_ctrl118;
+    volatile hp_sys_clkrst_peri_clk_ctrl119_reg_t peri_clk_ctrl119;
+    volatile hp_sys_clkrst_peri_clk_ctrl120_reg_t peri_clk_ctrl120;
+    volatile hp_sys_clkrst_peri_clk_ctrl20_reg_t peri_clk_ctrl20;
+    volatile hp_sys_clkrst_peri_clk_ctrl21_reg_t peri_clk_ctrl21;
+    volatile hp_sys_clkrst_peri_clk_ctrl22_reg_t peri_clk_ctrl22;
+    volatile hp_sys_clkrst_peri_clk_ctrl23_reg_t peri_clk_ctrl23;
+    volatile hp_sys_clkrst_peri_clk_ctrl24_reg_t peri_clk_ctrl24;
+    volatile hp_sys_clkrst_peri_clk_ctrl25_reg_t peri_clk_ctrl25;
+    volatile hp_sys_clkrst_peri_clk_ctrl26_reg_t peri_clk_ctrl26;
+    volatile hp_sys_clkrst_peri_clk_ctrl27_reg_t peri_clk_ctrl27;
+    volatile hp_sys_clkrst_clk_force_on_ctrl0_reg_t clk_force_on_ctrl0;
+    volatile hp_sys_clkrst_dpa_ctrl0_reg_t dpa_ctrl0;
+    volatile hp_sys_clkrst_ana_pll_ctrl0_reg_t ana_pll_ctrl0;
+    volatile hp_sys_clkrst_hp_rst_en0_reg_t hp_rst_en0;
+    volatile hp_sys_clkrst_hp_rst_en1_reg_t hp_rst_en1;
+    volatile hp_sys_clkrst_hp_rst_en2_reg_t hp_rst_en2;
+    volatile hp_sys_clkrst_hp_force_norst0_reg_t hp_force_norst0;
+    volatile hp_sys_clkrst_hp_force_norst1_reg_t hp_force_norst1;
+    volatile hp_sys_clkrst_hpwdt_core0_rst_ctrl0_reg_t hpwdt_core0_rst_ctrl0;
+    volatile hp_sys_clkrst_hpwdt_core1_rst_ctrl0_reg_t hpwdt_core1_rst_ctrl0;
+    volatile hp_sys_clkrst_cpu_src_freq0_reg_t cpu_src_freq0;
+    volatile hp_sys_clkrst_cpu_clk_status0_reg_t cpu_clk_status0;
+    volatile hp_sys_clkrst_dbg_clk_ctrl0_reg_t dbg_clk_ctrl0;
+    volatile hp_sys_clkrst_dbg_clk_ctrl1_reg_t dbg_clk_ctrl1;
+    volatile hp_sys_clkrst_hpcore_wdt_reset_source0_reg_t hpcore_wdt_reset_source0;
+    volatile hp_sys_clkrst_axi_perf_mon_clkrst_ctrl0_reg_t axi_perf_mon_clkrst_ctrl0;
+    volatile hp_sys_clkrst_cpu_waiti_ctrl0_reg_t cpu_waiti_ctrl0;
+} hp_sys_clkrst_dev_t;
+
+extern hp_sys_clkrst_dev_t HP_SYS_CLKRST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_sys_clkrst_dev_t) == 0xf8, "Invalid size of hp_sys_clkrst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp_system_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/hp_system_reg.h
new file mode 100644
index 0000000000..81cff32012
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp_system_reg.h
@@ -0,0 +1,2173 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_SYSTEM_VER_DATE_REG register
+ *  NA
+ */
+#define HP_SYSTEM_VER_DATE_REG (DR_REG_HP_SYS_BASE + 0x0)
+/** HP_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539296519;
+ *  NA
+ */
+#define HP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
+#define HP_SYSTEM_REG_VER_DATE_M  (HP_REG_VER_DATE_V << HP_REG_VER_DATE_S)
+#define HP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_VER_DATE_S  0
+
+/** HP_CLK_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CLK_EN_REG (DR_REG_HP_SYS_BASE + 0x4)
+/** HP_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_CLK_EN    (BIT(0))
+#define HP_SYSTEM_REG_CLK_EN_M  (HP_REG_CLK_EN_V << HP_REG_CLK_EN_S)
+#define HP_SYSTEM_REG_CLK_EN_V  0x00000001U
+#define HP_SYSTEM_REG_CLK_EN_S  0
+
+/** HP_CPU_INT_FROM_CPU_0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_REG (DR_REG_HP_SYS_BASE + 0x10)
+/** HP_CPU_INT_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_M  (HP_CPU_INT_FROM_CPU_0_V << HP_CPU_INT_FROM_CPU_0_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_S  0
+
+/** HP_CPU_INT_FROM_CPU_1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_REG (DR_REG_HP_SYS_BASE + 0x14)
+/** HP_CPU_INT_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_M  (HP_CPU_INT_FROM_CPU_1_V << HP_CPU_INT_FROM_CPU_1_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_S  0
+
+/** HP_CPU_INT_FROM_CPU_2_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_REG (DR_REG_HP_SYS_BASE + 0x18)
+/** HP_CPU_INT_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_M  (HP_CPU_INT_FROM_CPU_2_V << HP_CPU_INT_FROM_CPU_2_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_S  0
+
+/** HP_CPU_INT_FROM_CPU_3_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_REG (DR_REG_HP_SYS_BASE + 0x1c)
+/** HP_CPU_INT_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_M  (HP_CPU_INT_FROM_CPU_3_V << HP_CPU_INT_FROM_CPU_3_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_S  0
+
+/** HP_CACHE_CLK_CONFIG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_CLK_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x20)
+/** HP_REG_L2_CACHE_CLK_ON : R/W; bitpos: [0]; default: 1;
+ *  l2 cache clk enable
+ */
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON    (BIT(0))
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_M  (HP_REG_L2_CACHE_CLK_ON_V << HP_REG_L2_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_S  0
+/** HP_REG_L1_D_CACHE_CLK_ON : R/W; bitpos: [1]; default: 1;
+ *  l1 dcahce clk enable
+ */
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON    (BIT(1))
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_M  (HP_REG_L1_D_CACHE_CLK_ON_V << HP_REG_L1_D_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_S  1
+/** HP_REG_L1_I1_CACHE_CLK_ON : R/W; bitpos: [4]; default: 1;
+ *  l1 icahce1 clk enable
+ */
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON    (BIT(4))
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_M  (HP_REG_L1_I1_CACHE_CLK_ON_V << HP_REG_L1_I1_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_S  4
+/** HP_REG_L1_I0_CACHE_CLK_ON : R/W; bitpos: [5]; default: 1;
+ *  l1 icahce0 clk enable
+ */
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON    (BIT(5))
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_M  (HP_REG_L1_I0_CACHE_CLK_ON_V << HP_REG_L1_I0_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_S  5
+
+/** HP_CACHE_RESET_CONFIG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_RESET_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x24)
+/** HP_REG_L1_D_CACHE_RESET : R/W; bitpos: [1]; default: 0;
+ *  set 1 to reset l1 dcahce
+ */
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET    (BIT(1))
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET_M  (HP_REG_L1_D_CACHE_RESET_V << HP_REG_L1_D_CACHE_RESET_S)
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET_S  1
+/** HP_REG_L1_I1_CACHE_RESET : R/W; bitpos: [4]; default: 0;
+ *  set 1 to reset l1 icahce1
+ */
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET    (BIT(4))
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_M  (HP_REG_L1_I1_CACHE_RESET_V << HP_REG_L1_I1_CACHE_RESET_S)
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_S  4
+/** HP_REG_L1_I0_CACHE_RESET : R/W; bitpos: [5]; default: 0;
+ *  set 1 to reset l1 icahce0
+ */
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET    (BIT(5))
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_M  (HP_REG_L1_I0_CACHE_RESET_V << HP_REG_L1_I0_CACHE_RESET_S)
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_S  5
+
+/** HP_SYS_DMA_ADDR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_SYS_DMA_ADDR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2c)
+/** HP_REG_SYS_DMA_ADDR_SEL : R/W; bitpos: [0]; default: 0;
+ *  0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx
+ */
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL    (BIT(0))
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_M  (HP_REG_SYS_DMA_ADDR_SEL_V << HP_REG_SYS_DMA_ADDR_SEL_S)
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_V  0x00000001U
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_S  0
+
+/** HP_TCM_RAM_WRR_CONFIG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RAM_WRR_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x34)
+/** HP_REG_TCM_RAM_IBUS0_WT : R/W; bitpos: [2:0]; default: 7;
+ *  weight value of ibus0
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_M  (HP_REG_TCM_RAM_IBUS0_WT_V << HP_REG_TCM_RAM_IBUS0_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_S  0
+/** HP_REG_TCM_RAM_IBUS1_WT : R/W; bitpos: [5:3]; default: 7;
+ *  weight value of ibus1
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_M  (HP_REG_TCM_RAM_IBUS1_WT_V << HP_REG_TCM_RAM_IBUS1_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_S  3
+/** HP_REG_TCM_RAM_IBUS2_WT : R/W; bitpos: [8:6]; default: 4;
+ *  weight value of ibus2
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_M  (HP_REG_TCM_RAM_IBUS2_WT_V << HP_REG_TCM_RAM_IBUS2_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_S  6
+/** HP_REG_TCM_RAM_IBUS3_WT : R/W; bitpos: [11:9]; default: 4;
+ *  weight value of ibus3
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_M  (HP_REG_TCM_RAM_IBUS3_WT_V << HP_REG_TCM_RAM_IBUS3_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_S  9
+/** HP_REG_TCM_RAM_DBUS0_WT : R/W; bitpos: [14:12]; default: 5;
+ *  weight value of dbus0
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_M  (HP_REG_TCM_RAM_DBUS0_WT_V << HP_REG_TCM_RAM_DBUS0_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_S  12
+/** HP_REG_TCM_RAM_DBUS1_WT : R/W; bitpos: [17:15]; default: 5;
+ *  weight value of dbus1
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_M  (HP_REG_TCM_RAM_DBUS1_WT_V << HP_REG_TCM_RAM_DBUS1_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_S  15
+/** HP_REG_TCM_RAM_DBUS2_WT : R/W; bitpos: [20:18]; default: 3;
+ *  weight value of dbus2
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_M  (HP_REG_TCM_RAM_DBUS2_WT_V << HP_REG_TCM_RAM_DBUS2_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_S  18
+/** HP_REG_TCM_RAM_DBUS3_WT : R/W; bitpos: [23:21]; default: 3;
+ *  weight value of dbus3
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_M  (HP_REG_TCM_RAM_DBUS3_WT_V << HP_REG_TCM_RAM_DBUS3_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_S  21
+/** HP_REG_TCM_RAM_DMA_WT : R/W; bitpos: [26:24]; default: 2;
+ *  weight value of dma
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_M  (HP_REG_TCM_RAM_DMA_WT_V << HP_REG_TCM_RAM_DMA_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_S  24
+/** HP_REG_TCM_RAM_WRR_HIGH : R/W; bitpos: [31]; default: 1;
+ *  enable weighted round robin arbitration
+ */
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH    (BIT(31))
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_M  (HP_REG_TCM_RAM_WRR_HIGH_V << HP_REG_TCM_RAM_WRR_HIGH_S)
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_S  31
+
+/** HP_TCM_SW_PARITY_BWE_MASK_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_SW_PARITY_BWE_MASK_REG (DR_REG_HP_SYS_BASE + 0x38)
+/** HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to mask tcm bwe parity code bit
+ */
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL    (BIT(0))
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_M  (HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_V << HP_REG_TCM_SW_PARITY_BWE_MASK_CTRL_S)
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_S  0
+
+/** HP_TCM_RAM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x3c)
+/** HP_REG_HP_TCM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  hp_tcm clk gatig force on
+ */
+#define HP_SYSTEM_REG_HP_TCM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_HP_TCM_CLK_FORCE_ON_M  (HP_REG_HP_TCM_CLK_FORCE_ON_V << HP_REG_HP_TCM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_HP_TCM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_HP_TCM_CLK_FORCE_ON_S  0
+
+/** HP_L2_ROM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_ROM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x40)
+/** HP_REG_L2_ROM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  l2_rom clk gating force on
+ */
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_M  (HP_REG_L2_ROM_CLK_FORCE_ON_V << HP_REG_L2_ROM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_S  0
+
+/** HP_PROBEA_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBEA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x50)
+/** HP_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  module's probe_out[31:0] in a mode
+ */
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (HP_REG_PROBE_A_MOD_SEL_V << HP_REG_PROBE_A_MOD_SEL_S)
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
+/** HP_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  This field is used to selec module's probe_out[31:0] as probe out in a mode
+ */
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (HP_REG_PROBE_A_TOP_SEL_V << HP_REG_PROBE_A_TOP_SEL_S)
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
+/** HP_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  This field is used to selec probe_out[31:16]
+ */
+#define HP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
+#define HP_SYSTEM_REG_PROBE_L_SEL_M  (HP_REG_PROBE_L_SEL_V << HP_REG_PROBE_L_SEL_S)
+#define HP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
+#define HP_SYSTEM_REG_PROBE_L_SEL_S  24
+/** HP_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This field is used to selec probe_out[31:16]
+ */
+#define HP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
+#define HP_SYSTEM_REG_PROBE_H_SEL_M  (HP_REG_PROBE_H_SEL_V << HP_REG_PROBE_H_SEL_S)
+#define HP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
+#define HP_SYSTEM_REG_PROBE_H_SEL_S  26
+/** HP_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to enable global debug probe in hp system.
+ */
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (HP_REG_PROBE_GLOBAL_EN_V << HP_REG_PROBE_GLOBAL_EN_S)
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28
+
+/** HP_PROBEB_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBEB_CTRL_REG (DR_REG_HP_SYS_BASE + 0x54)
+/** HP_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  module's probe_out[31:0] in b mode.
+ */
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (HP_REG_PROBE_B_MOD_SEL_V << HP_REG_PROBE_B_MOD_SEL_S)
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
+/** HP_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
+ */
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (HP_REG_PROBE_B_TOP_SEL_V << HP_REG_PROBE_B_TOP_SEL_S)
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
+/** HP_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
+ *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
+ */
+#define HP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
+#define HP_SYSTEM_REG_PROBE_B_EN_M  (HP_REG_PROBE_B_EN_V << HP_REG_PROBE_B_EN_S)
+#define HP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
+#define HP_SYSTEM_REG_PROBE_B_EN_S  24
+
+/** HP_PROBE_OUT_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBE_OUT_REG (DR_REG_HP_SYS_BASE + 0x5c)
+/** HP_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_M  (HP_REG_PROBE_TOP_OUT_V << HP_REG_PROBE_TOP_OUT_S)
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_S  0
+
+/** HP_L2_MEM_RAM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x60)
+/** HP_REG_L2_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  l2ram clk_gating force on
+ */
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_M  (HP_REG_L2_MEM_CLK_FORCE_ON_V << HP_REG_L2_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_S  0
+
+/** HP_CPU_CORESTALLED_ST_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_CORESTALLED_ST_REG (DR_REG_HP_SYS_BASE + 0x64)
+/** HP_REG_CORE0_CORESTALLED_ST : RO; bitpos: [0]; default: 0;
+ *  hp core0 corestalled status
+ */
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST    (BIT(0))
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_M  (HP_REG_CORE0_CORESTALLED_ST_V << HP_REG_CORE0_CORESTALLED_ST_S)
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V  0x00000001U
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S  0
+/** HP_REG_CORE1_CORESTALLED_ST : RO; bitpos: [1]; default: 0;
+ *  hp core1 corestalled status
+ */
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST    (BIT(1))
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_M  (HP_REG_CORE1_CORESTALLED_ST_V << HP_REG_CORE1_CORESTALLED_ST_S)
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V  0x00000001U
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S  1
+
+/** HP_CRYPTO_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CRYPTO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70)
+/** HP_REG_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_REG_ENABLE_SPI_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+/** HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/** HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/** HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+
+/** HP_GPIO_O_HOLD_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HOLD_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x74)
+/** HP_REG_GPIO_0_HOLD_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  hold control for gpio47~16
+ */
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_M  (HP_REG_GPIO_0_HOLD_LOW_V << HP_REG_GPIO_0_HOLD_LOW_S)
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_S  0
+
+/** HP_GPIO_O_HOLD_CTRL1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HOLD_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x78)
+/** HP_REG_GPIO_0_HOLD_HIGH : R/W; bitpos: [8:0]; default: 0;
+ *  hold control for gpio56~48
+ */
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH    0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_M  (HP_REG_GPIO_0_HOLD_HIGH_V << HP_REG_GPIO_0_HOLD_HIGH_S)
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_V  0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_S  0
+
+/** HP_SYS_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_SYS_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0x7c)
+/** HP_REG_HP_SYS_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_EN_M  (HP_REG_HP_SYS_RDN_ECO_EN_V << HP_REG_HP_SYS_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_EN_S  0
+/** HP_REG_HP_SYS_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_RESULT_M  (HP_REG_HP_SYS_RDN_ECO_RESULT_V << HP_REG_HP_SYS_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYS_RDN_ECO_RESULT_S  1
+
+/** HP_CACHE_APB_POSTW_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_APB_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x80)
+/** HP_REG_CACHE_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  cache apb register interface post write enable, 1 will speed up write, but will
+ *  take some time to update value to register
+ */
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN    (BIT(0))
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_M  (HP_REG_CACHE_APB_POSTW_EN_V << HP_REG_CACHE_APB_POSTW_EN_S)
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_S  0
+
+/** HP_L2_MEM_SUBSIZE_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_SUBSIZE_REG (DR_REG_HP_SYS_BASE + 0x84)
+/** HP_REG_L2_MEM_SUB_BLKSIZE : R/W; bitpos: [1:0]; default: 0;
+ *  l2mem sub block size 00=>32 01=>64 10=>128 11=>256
+ */
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE    0x00000003U
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_M  (HP_REG_L2_MEM_SUB_BLKSIZE_V << HP_REG_L2_MEM_SUB_BLKSIZE_S)
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_V  0x00000003U
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_S  0
+
+/** HP_L2_MEM_INT_RAW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x9c)
+/** HP_REG_L2_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  intr triggered when two bit error detected and corrected from ecc
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_M  (HP_REG_L2_MEM_ECC_ERR_INT_RAW_V << HP_REG_L2_MEM_ECC_ERR_INT_RAW_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds
+ *  0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_RAW_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_S  1
+/** HP_REG_L2_MEM_ERR_RESP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  intr triggered when err response occurs
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_M  (HP_REG_L2_MEM_ERR_RESP_INT_RAW_V << HP_REG_L2_MEM_ERR_RESP_INT_RAW_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_S  2
+
+/** HP_L2_MEM_INT_ST_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_ST_REG (DR_REG_HP_SYS_BASE + 0xa0)
+/** HP_REG_L2_MEM_ECC_ERR_INT_ST : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_M  (HP_REG_L2_MEM_ECC_ERR_INT_ST_V << HP_REG_L2_MEM_ECC_ERR_INT_ST_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_ST_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_ST_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_S  1
+/** HP_REG_L2_MEM_ERR_RESP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_M  (HP_REG_L2_MEM_ERR_RESP_INT_ST_V << HP_REG_L2_MEM_ERR_RESP_INT_ST_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_S  2
+
+/** HP_L2_MEM_INT_ENA_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0xa4)
+/** HP_REG_L2_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_M  (HP_REG_L2_MEM_ECC_ERR_INT_ENA_V << HP_REG_L2_MEM_ECC_ERR_INT_ENA_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_ENA_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_S  1
+/** HP_REG_L2_MEM_ERR_RESP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_M  (HP_REG_L2_MEM_ERR_RESP_INT_ENA_V << HP_REG_L2_MEM_ERR_RESP_INT_ENA_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_S  2
+
+/** HP_L2_MEM_INT_CLR_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0xa8)
+/** HP_REG_L2_MEM_ECC_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_M  (HP_REG_L2_MEM_ECC_ERR_INT_CLR_V << HP_REG_L2_MEM_ECC_ERR_INT_CLR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_CLR_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_S  1
+/** HP_REG_L2_MEM_ERR_RESP_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_M  (HP_REG_L2_MEM_ERR_RESP_INT_CLR_V << HP_REG_L2_MEM_ERR_RESP_INT_CLR_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_S  2
+
+/** HP_L2_MEM_L2_RAM_ECC_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_L2_RAM_ECC_REG (DR_REG_HP_SYS_BASE + 0xac)
+/** HP_REG_L2_RAM_UNIT0_ECC_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_M  (HP_REG_L2_RAM_UNIT0_ECC_EN_V << HP_REG_L2_RAM_UNIT0_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_S  0
+/** HP_REG_L2_RAM_UNIT1_ECC_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN    (BIT(1))
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_M  (HP_REG_L2_RAM_UNIT1_ECC_EN_V << HP_REG_L2_RAM_UNIT1_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_S  1
+/** HP_REG_L2_RAM_UNIT2_ECC_EN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN    (BIT(2))
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_M  (HP_REG_L2_RAM_UNIT2_ECC_EN_V << HP_REG_L2_RAM_UNIT2_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_S  2
+/** HP_REG_L2_RAM_UNIT3_ECC_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN    (BIT(3))
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_M  (HP_REG_L2_RAM_UNIT3_ECC_EN_V << HP_REG_L2_RAM_UNIT3_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_S  3
+/** HP_REG_L2_RAM_UNIT4_ECC_EN : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN    (BIT(4))
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_M  (HP_REG_L2_RAM_UNIT4_ECC_EN_V << HP_REG_L2_RAM_UNIT4_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_S  4
+/** HP_REG_L2_RAM_UNIT5_ECC_EN : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN    (BIT(5))
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_M  (HP_REG_L2_RAM_UNIT5_ECC_EN_V << HP_REG_L2_RAM_UNIT5_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_S  5
+
+/** HP_L2_MEM_INT_RECORD0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_RECORD0_REG (DR_REG_HP_SYS_BASE + 0xb0)
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR : RO; bitpos: [20:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR    0x001FFFFFU
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_V  0x001FFFFFU
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_S  0
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_WE : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE    (BIT(21))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_WE_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_WE_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_S  21
+/** HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER : RO; bitpos: [24:22]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER    0x00000007U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_M  (HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_V << HP_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_V  0x00000007U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_S  22
+
+/** HP_L2_MEM_INT_RECORD1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_RECORD1_REG (DR_REG_HP_SYS_BASE + 0xb4)
+/** HP_REG_L2_MEM_ECC_ERR_INT_ADDR : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR    0x00007FFFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_M  (HP_REG_L2_MEM_ECC_ERR_INT_ADDR_V << HP_REG_L2_MEM_ECC_ERR_INT_ADDR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_V  0x00007FFFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_S  0
+/** HP_REG_L2_MEM_ECC_ONE_BIT_ERR : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR    (BIT(15))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_M  (HP_REG_L2_MEM_ECC_ONE_BIT_ERR_V << HP_REG_L2_MEM_ECC_ONE_BIT_ERR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_S  15
+/** HP_REG_L2_MEM_ECC_TWO_BIT_ERR : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR    (BIT(16))
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_M  (HP_REG_L2_MEM_ECC_TWO_BIT_ERR_V << HP_REG_L2_MEM_ECC_TWO_BIT_ERR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_S  16
+/** HP_REG_L2_MEM_ECC_ERR_BIT : RO; bitpos: [25:17]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT    0x000001FFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_M  (HP_REG_L2_MEM_ECC_ERR_BIT_V << HP_REG_L2_MEM_ECC_ERR_BIT_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_V  0x000001FFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_S  17
+/** HP_REG_L2_CACHE_ERR_BANK : RO; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK    (BIT(26))
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_M  (HP_REG_L2_CACHE_ERR_BANK_V << HP_REG_L2_CACHE_ERR_BANK_S)
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_V  0x00000001U
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_S  26
+
+/** HP_L2_MEM_L2_CACHE_ECC_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_L2_CACHE_ECC_REG (DR_REG_HP_SYS_BASE + 0xc4)
+/** HP_REG_L2_CACHE_ECC_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_M  (HP_REG_L2_CACHE_ECC_EN_V << HP_REG_L2_CACHE_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_S  0
+
+/** HP_L1CACHE_BUS0_ID_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L1CACHE_BUS0_ID_REG (DR_REG_HP_SYS_BASE + 0xc8)
+/** HP_REG_L1_CACHE_BUS0_ID : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID    0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_M  (HP_REG_L1_CACHE_BUS0_ID_V << HP_REG_L1_CACHE_BUS0_ID_S)
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_V  0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_S  0
+
+/** HP_L1CACHE_BUS1_ID_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L1CACHE_BUS1_ID_REG (DR_REG_HP_SYS_BASE + 0xcc)
+/** HP_REG_L1_CACHE_BUS1_ID : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID    0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_M  (HP_REG_L1_CACHE_BUS1_ID_V << HP_REG_L1_CACHE_BUS1_ID_S)
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_V  0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_S  0
+
+/** HP_L2_MEM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xd8)
+/** HP_REG_L2_MEM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_M  (HP_REG_L2_MEM_RDN_ECO_EN_V << HP_REG_L2_MEM_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_S  0
+/** HP_REG_L2_MEM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_M  (HP_REG_L2_MEM_RDN_ECO_RESULT_V << HP_REG_L2_MEM_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_S  1
+
+/** HP_L2_MEM_RDN_ECO_LOW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xdc)
+/** HP_REG_L2_MEM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_M  (HP_REG_L2_MEM_RDN_ECO_LOW_V << HP_REG_L2_MEM_RDN_ECO_LOW_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_S  0
+
+/** HP_L2_MEM_RDN_ECO_HIGH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xe0)
+/** HP_REG_L2_MEM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_M  (HP_REG_L2_MEM_RDN_ECO_HIGH_V << HP_REG_L2_MEM_RDN_ECO_HIGH_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_S  0
+
+/** HP_TCM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xe4)
+/** HP_REG_HP_TCM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_EN_M  (HP_REG_HP_TCM_RDN_ECO_EN_V << HP_REG_HP_TCM_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_EN_S  0
+/** HP_REG_HP_TCM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_RESULT_M  (HP_REG_HP_TCM_RDN_ECO_RESULT_V << HP_REG_HP_TCM_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_RESULT_S  1
+
+/** HP_TCM_RDN_ECO_LOW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xe8)
+/** HP_REG_HP_TCM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_LOW_M  (HP_REG_HP_TCM_RDN_ECO_LOW_V << HP_REG_HP_TCM_RDN_ECO_LOW_S)
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_LOW_S  0
+
+/** HP_TCM_RDN_ECO_HIGH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xec)
+/** HP_REG_HP_TCM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_HIGH_M  (HP_REG_HP_TCM_RDN_ECO_HIGH_V << HP_REG_HP_TCM_RDN_ECO_HIGH_S)
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_TCM_RDN_ECO_HIGH_S  0
+
+/** HP_GPIO_DED_HOLD_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_DED_HOLD_CTRL_REG (DR_REG_HP_SYS_BASE + 0xf0)
+/** HP_REG_GPIO_DED_HOLD : R/W; bitpos: [25:0]; default: 0;
+ *  hold control for gpio63~56
+ */
+#define HP_SYSTEM_REG_GPIO_DED_HOLD    0x03FFFFFFU
+#define HP_SYSTEM_REG_GPIO_DED_HOLD_M  (HP_REG_GPIO_DED_HOLD_V << HP_REG_GPIO_DED_HOLD_S)
+#define HP_SYSTEM_REG_GPIO_DED_HOLD_V  0x03FFFFFFU
+#define HP_SYSTEM_REG_GPIO_DED_HOLD_S  0
+
+/** HP_L2_MEM_SW_ECC_BWE_MASK_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_SW_ECC_BWE_MASK_REG (DR_REG_HP_SYS_BASE + 0xf4)
+/** HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to mask bwe hamming code bit
+ */
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_M  (HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_V << HP_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_S)
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_S  0
+
+/** HP_USB20OTG_MEM_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_USB20OTG_MEM_CTRL_REG (DR_REG_HP_SYS_BASE + 0xf8)
+/** HP_REG_USB20_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_M  (HP_REG_USB20_MEM_CLK_FORCE_ON_V << HP_REG_USB20_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_S  0
+
+/** HP_TCM_INT_RAW_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0xfc)
+/** HP_TCM_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_M  (HP_TCM_PARITY_ERR_INT_RAW_V << HP_TCM_PARITY_ERR_INT_RAW_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_S  31
+
+/** HP_TCM_INT_ST_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x100)
+/** HP_TCM_PARITY_ERR_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_M  (HP_TCM_PARITY_ERR_INT_ST_V << HP_TCM_PARITY_ERR_INT_ST_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_S  31
+
+/** HP_TCM_INT_ENA_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x104)
+/** HP_TCM_PARITY_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_M  (HP_TCM_PARITY_ERR_INT_ENA_V << HP_TCM_PARITY_ERR_INT_ENA_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_S  31
+
+/** HP_TCM_INT_CLR_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x108)
+/** HP_TCM_PARITY_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_M  (HP_TCM_PARITY_ERR_INT_CLR_V << HP_TCM_PARITY_ERR_INT_CLR_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_S  31
+
+/** HP_TCM_PARITY_INT_RECORD_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_INT_RECORD_REG (DR_REG_HP_SYS_BASE + 0x10c)
+/** HP_TCM_PARITY_ERR_INT_ADDR : RO; bitpos: [12:0]; default: 0;
+ *  hp tcm_parity_err_addr
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR    0x00001FFFU
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_M  (HP_TCM_PARITY_ERR_INT_ADDR_V << HP_TCM_PARITY_ERR_INT_ADDR_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_V  0x00001FFFU
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_S  0
+
+/** HP_L1_CACHE_PWR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L1_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x110)
+/** HP_REG_L1_CACHE_MEM_FO : R/W; bitpos: [5:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO    0x0000003FU
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_M  (HP_REG_L1_CACHE_MEM_FO_V << HP_REG_L1_CACHE_MEM_FO_S)
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_V  0x0000003FU
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_S  0
+
+/** HP_L2_CACHE_PWR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x114)
+/** HP_REG_L2_CACHE_MEM_FO : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO    0x00000003U
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_M  (HP_REG_L2_CACHE_MEM_FO_V << HP_REG_L2_CACHE_MEM_FO_S)
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_V  0x00000003U
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_S  0
+
+/** HP_CPU_WAITI_CONF_REG register
+ *  CPU_WAITI configuration register
+ */
+#define HP_SYSTEM_CPU_WAITI_CONF_REG (DR_REG_HP_SYS_BASE + 0x118)
+/** HP_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to force cpu_waiti_clk enable.
+ */
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (HP_CPU_WAIT_MODE_FORCE_ON_V << HP_CPU_WAIT_MODE_FORCE_ON_S)
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  0
+/** HP_CPU_WAITI_DELAY_NUM : R/W; bitpos: [4:1]; default: 0;
+ *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+ *  will close
+ */
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000FU
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_M  (HP_CPU_WAITI_DELAY_NUM_V << HP_CPU_WAITI_DELAY_NUM_S)
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_V  0x0000000FU
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_S  1
+
+/** HP_SYS_CORE_DEBUG_RUNSTALL_CONF_REG register
+ *  Core Debug runstall configure register
+ */
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x11c)
+/** HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+ */
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_ENABLE    (BIT(0))
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_ENABLE_M  (HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S)
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_ENABLE_V  0x00000001U
+#define HP_SYSTEM_SYS_CORE_DEBUG_RUNSTALL_ENABLE_S  0
+
+/** HP_CORE_AHB_TIMEOUT_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x120)
+/** HP_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 ahb timeout handle
+ */
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_M  (HP_CORE_AHB_TIMEOUT_EN_V << HP_CORE_AHB_TIMEOUT_EN_S)
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_S  0
+/** HP_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 ahb bus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_M  (HP_CORE_AHB_TIMEOUT_THRES_V << HP_CORE_AHB_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_S  1
+
+/** HP_CORE_IBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x124)
+/** HP_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 ibus timeout handle
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_M  (HP_CORE_IBUS_TIMEOUT_EN_V << HP_CORE_IBUS_TIMEOUT_EN_S)
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_S  0
+/** HP_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 ibus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_M  (HP_CORE_IBUS_TIMEOUT_THRES_V << HP_CORE_IBUS_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S  1
+
+/** HP_CORE_DBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x128)
+/** HP_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 dbus timeout handle
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_M  (HP_CORE_DBUS_TIMEOUT_EN_V << HP_CORE_DBUS_TIMEOUT_EN_S)
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_S  0
+/** HP_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 dbus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_M  (HP_CORE_DBUS_TIMEOUT_THRES_V << HP_CORE_DBUS_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S  1
+
+/** HP_ICM_CPU_H2X_CFG_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_ICM_CPU_H2X_CFG_REG (DR_REG_HP_SYS_BASE + 0x138)
+/** HP_CPU_ICM_H2X_POST_WR_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN    (BIT(0))
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_M  (HP_CPU_ICM_H2X_POST_WR_EN_V << HP_CPU_ICM_H2X_POST_WR_EN_S)
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S  0
+/** HP_CPU_ICM_H2X_CUT_THROUGH_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN    (BIT(1))
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_M  (HP_CPU_ICM_H2X_CUT_THROUGH_EN_V << HP_CPU_ICM_H2X_CUT_THROUGH_EN_S)
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S  1
+/** HP_CPU_ICM_H2X_BRIDGE_BUSY : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY    (BIT(2))
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_M  (HP_CPU_ICM_H2X_BRIDGE_BUSY_V << HP_CPU_ICM_H2X_BRIDGE_BUSY_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S  2
+
+/** HP_PERI1_APB_POSTW_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x13c)
+/** HP_PERI1_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  hp_peri1 apb register interface post write enable, 1 will speed up write, but will
+ *  take some time to update value to register
+ */
+#define HP_SYSTEM_PERI1_APB_POSTW_EN    (BIT(0))
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_M  (HP_PERI1_APB_POSTW_EN_V << HP_PERI1_APB_POSTW_EN_S)
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_S  0
+
+/** HP_BITSCRAMBLER_PERI_SEL_REG register
+ *  Bitscrambler Peri Sel
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYS_BASE + 0x140)
+/** HP_BITSCRAMBLER_PERI_RX_SEL : R/W; bitpos: [3:0]; default: 15;
+ *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0
+ *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+ *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+ *  else : none
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL    0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_M  (HP_BITSCRAMBLER_PERI_RX_SEL_V << HP_BITSCRAMBLER_PERI_RX_SEL_S)
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V  0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S  0
+/** HP_BITSCRAMBLER_PERI_TX_SEL : R/W; bitpos: [7:4]; default: 15;
+ *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0
+ *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+ *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+ *  else : none
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL    0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_M  (HP_BITSCRAMBLER_PERI_TX_SEL_V << HP_BITSCRAMBLER_PERI_TX_SEL_S)
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V  0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S  4
+
+/** HP_SYS_APB_SYNC_POSTW_EN_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_APB_SYNC_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x144)
+/** HP_SYS_GMAC_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_APB_POSTW_EN    (BIT(0))
+#define HP_SYSTEM_SYS_GMAC_APB_POSTW_EN_M  (HP_SYS_GMAC_APB_POSTW_EN_V << HP_SYS_GMAC_APB_POSTW_EN_S)
+#define HP_SYSTEM_SYS_GMAC_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_GMAC_APB_POSTW_EN_S  0
+/** HP_SYS_DSI_HOST_APB_POSTW_EN : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_DSI_HOST_APB_POSTW_EN    (BIT(1))
+#define HP_SYSTEM_SYS_DSI_HOST_APB_POSTW_EN_M  (HP_SYS_DSI_HOST_APB_POSTW_EN_V << HP_SYS_DSI_HOST_APB_POSTW_EN_S)
+#define HP_SYSTEM_SYS_DSI_HOST_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_DSI_HOST_APB_POSTW_EN_S  1
+/** HP_SYS_CSI_HOST_APB_SYNC_POSTW_EN : R/W; bitpos: [2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_CSI_HOST_APB_SYNC_POSTW_EN    (BIT(2))
+#define HP_SYSTEM_SYS_CSI_HOST_APB_SYNC_POSTW_EN_M  (HP_SYS_CSI_HOST_APB_SYNC_POSTW_EN_V << HP_SYS_CSI_HOST_APB_SYNC_POSTW_EN_S)
+#define HP_SYSTEM_SYS_CSI_HOST_APB_SYNC_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_CSI_HOST_APB_SYNC_POSTW_EN_S  2
+/** HP_SYS_CSI_HOST_APB_ASYNC_POSTW_EN : R/W; bitpos: [3]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_CSI_HOST_APB_ASYNC_POSTW_EN    (BIT(3))
+#define HP_SYSTEM_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_M  (HP_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_V << HP_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_S)
+#define HP_SYSTEM_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_CSI_HOST_APB_ASYNC_POSTW_EN_S  3
+
+/** HP_SYS_GDMA_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GDMA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x148)
+/** HP_SYS_DEBUG_CH_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_DEBUG_CH_NUM    0x00000003U
+#define HP_SYSTEM_SYS_DEBUG_CH_NUM_M  (HP_SYS_DEBUG_CH_NUM_V << HP_SYS_DEBUG_CH_NUM_S)
+#define HP_SYSTEM_SYS_DEBUG_CH_NUM_V  0x00000003U
+#define HP_SYSTEM_SYS_DEBUG_CH_NUM_S  0
+
+/** HP_SYS_GMAC_CTRL0_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x14c)
+/** HP_SYS_PTP_PPS : RO; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PTP_PPS    (BIT(0))
+#define HP_SYSTEM_SYS_PTP_PPS_M  (HP_SYS_PTP_PPS_V << HP_SYS_PTP_PPS_S)
+#define HP_SYSTEM_SYS_PTP_PPS_V  0x00000001U
+#define HP_SYSTEM_SYS_PTP_PPS_S  0
+/** HP_SYS_SBD_FLOWCTRL : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_SBD_FLOWCTRL    (BIT(1))
+#define HP_SYSTEM_SYS_SBD_FLOWCTRL_M  (HP_SYS_SBD_FLOWCTRL_V << HP_SYS_SBD_FLOWCTRL_S)
+#define HP_SYSTEM_SYS_SBD_FLOWCTRL_V  0x00000001U
+#define HP_SYSTEM_SYS_SBD_FLOWCTRL_S  1
+/** HP_SYS_PHY_INTF_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_INTF_SEL    0x00000007U
+#define HP_SYSTEM_SYS_PHY_INTF_SEL_M  (HP_SYS_PHY_INTF_SEL_V << HP_SYS_PHY_INTF_SEL_S)
+#define HP_SYSTEM_SYS_PHY_INTF_SEL_V  0x00000007U
+#define HP_SYSTEM_SYS_PHY_INTF_SEL_S  2
+/** HP_SYS_GMAC_MEM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_MEM_CLK_FORCE_ON    (BIT(5))
+#define HP_SYSTEM_SYS_GMAC_MEM_CLK_FORCE_ON_M  (HP_SYS_GMAC_MEM_CLK_FORCE_ON_V << HP_SYS_GMAC_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_SYS_GMAC_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_SYS_GMAC_MEM_CLK_FORCE_ON_S  5
+/** HP_SYS_GMAC_RST_CLK_TX_N : RO; bitpos: [6]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_TX_N    (BIT(6))
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_TX_N_M  (HP_SYS_GMAC_RST_CLK_TX_N_V << HP_SYS_GMAC_RST_CLK_TX_N_S)
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_TX_N_V  0x00000001U
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_TX_N_S  6
+/** HP_SYS_GMAC_RST_CLK_RX_N : RO; bitpos: [7]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_RX_N    (BIT(7))
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_RX_N_M  (HP_SYS_GMAC_RST_CLK_RX_N_V << HP_SYS_GMAC_RST_CLK_RX_N_S)
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_RX_N_V  0x00000001U
+#define HP_SYSTEM_SYS_GMAC_RST_CLK_RX_N_S  7
+
+/** HP_SYS_GMAC_CTRL1_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x150)
+/** HP_SYS_PTP_TIMESTAMP_L : RO; bitpos: [31:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_L    0xFFFFFFFFU
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_L_M  (HP_SYS_PTP_TIMESTAMP_L_V << HP_SYS_PTP_TIMESTAMP_L_S)
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_L_V  0xFFFFFFFFU
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_L_S  0
+
+/** HP_SYS_GMAC_CTRL2_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_GMAC_CTRL2_REG (DR_REG_HP_SYS_BASE + 0x154)
+/** HP_SYS_PTP_TIMESTAMP_H : RO; bitpos: [31:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_H    0xFFFFFFFFU
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_H_M  (HP_SYS_PTP_TIMESTAMP_H_V << HP_SYS_PTP_TIMESTAMP_H_S)
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_H_V  0xFFFFFFFFU
+#define HP_SYSTEM_SYS_PTP_TIMESTAMP_H_S  0
+
+/** HP_SYS_VPU_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_VPU_CTRL_REG (DR_REG_HP_SYS_BASE + 0x158)
+/** HP_SYS_PPA_LSLP_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PPA_LSLP_MEM_PD    (BIT(0))
+#define HP_SYSTEM_SYS_PPA_LSLP_MEM_PD_M  (HP_SYS_PPA_LSLP_MEM_PD_V << HP_SYS_PPA_LSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_PPA_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_PPA_LSLP_MEM_PD_S  0
+/** HP_SYS_JPEG_SDSLP_MEM_PD : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_JPEG_SDSLP_MEM_PD    (BIT(1))
+#define HP_SYSTEM_SYS_JPEG_SDSLP_MEM_PD_M  (HP_SYS_JPEG_SDSLP_MEM_PD_V << HP_SYS_JPEG_SDSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_JPEG_SDSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_JPEG_SDSLP_MEM_PD_S  1
+/** HP_SYS_JPEG_LSLP_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_JPEG_LSLP_MEM_PD    (BIT(2))
+#define HP_SYSTEM_SYS_JPEG_LSLP_MEM_PD_M  (HP_SYS_JPEG_LSLP_MEM_PD_V << HP_SYS_JPEG_LSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_JPEG_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_JPEG_LSLP_MEM_PD_S  2
+/** HP_SYS_JPEG_DSLP_MEM_PD : R/W; bitpos: [3]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_JPEG_DSLP_MEM_PD    (BIT(3))
+#define HP_SYSTEM_SYS_JPEG_DSLP_MEM_PD_M  (HP_SYS_JPEG_DSLP_MEM_PD_V << HP_SYS_JPEG_DSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_JPEG_DSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_JPEG_DSLP_MEM_PD_S  3
+/** HP_SYS_DMA2D_LSLP_MEM_PD : R/W; bitpos: [4]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_DMA2D_LSLP_MEM_PD    (BIT(4))
+#define HP_SYSTEM_SYS_DMA2D_LSLP_MEM_PD_M  (HP_SYS_DMA2D_LSLP_MEM_PD_V << HP_SYS_DMA2D_LSLP_MEM_PD_S)
+#define HP_SYSTEM_SYS_DMA2D_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_SYS_DMA2D_LSLP_MEM_PD_S  4
+
+/** HP_SYS_USBOTG20_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_USBOTG20_CTRL_REG (DR_REG_HP_SYS_BASE + 0x15c)
+/** HP_SYS_OTG_PHY_TEST_DONE : RO; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_PHY_TEST_DONE    (BIT(0))
+#define HP_SYSTEM_SYS_OTG_PHY_TEST_DONE_M  (HP_SYS_OTG_PHY_TEST_DONE_V << HP_SYS_OTG_PHY_TEST_DONE_S)
+#define HP_SYSTEM_SYS_OTG_PHY_TEST_DONE_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_PHY_TEST_DONE_S  0
+/** HP_SYS_USB_MEM_AUX_CTRL : R/W; bitpos: [14:1]; default: 4896;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_USB_MEM_AUX_CTRL    0x00003FFFU
+#define HP_SYSTEM_SYS_USB_MEM_AUX_CTRL_M  (HP_SYS_USB_MEM_AUX_CTRL_V << HP_SYS_USB_MEM_AUX_CTRL_S)
+#define HP_SYSTEM_SYS_USB_MEM_AUX_CTRL_V  0x00003FFFU
+#define HP_SYSTEM_SYS_USB_MEM_AUX_CTRL_S  1
+/** HP_SYS_PHY_SUSPENDM : R/W; bitpos: [15]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_SUSPENDM    (BIT(15))
+#define HP_SYSTEM_SYS_PHY_SUSPENDM_M  (HP_SYS_PHY_SUSPENDM_V << HP_SYS_PHY_SUSPENDM_S)
+#define HP_SYSTEM_SYS_PHY_SUSPENDM_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_SUSPENDM_S  15
+/** HP_SYS_PHY_SUSPEND_FORCE_EN : R/W; bitpos: [16]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_SUSPEND_FORCE_EN    (BIT(16))
+#define HP_SYSTEM_SYS_PHY_SUSPEND_FORCE_EN_M  (HP_SYS_PHY_SUSPEND_FORCE_EN_V << HP_SYS_PHY_SUSPEND_FORCE_EN_S)
+#define HP_SYSTEM_SYS_PHY_SUSPEND_FORCE_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_SUSPEND_FORCE_EN_S  16
+/** HP_SYS_PHY_RSTN : R/W; bitpos: [17]; default: 1;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_RSTN    (BIT(17))
+#define HP_SYSTEM_SYS_PHY_RSTN_M  (HP_SYS_PHY_RSTN_V << HP_SYS_PHY_RSTN_S)
+#define HP_SYSTEM_SYS_PHY_RSTN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_RSTN_S  17
+/** HP_SYS_PHY_RESET_FORCE_EN : R/W; bitpos: [18]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_RESET_FORCE_EN    (BIT(18))
+#define HP_SYSTEM_SYS_PHY_RESET_FORCE_EN_M  (HP_SYS_PHY_RESET_FORCE_EN_V << HP_SYS_PHY_RESET_FORCE_EN_S)
+#define HP_SYSTEM_SYS_PHY_RESET_FORCE_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_RESET_FORCE_EN_S  18
+/** HP_SYS_PHY_PLL_FORCE_EN : R/W; bitpos: [19]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_PLL_FORCE_EN    (BIT(19))
+#define HP_SYSTEM_SYS_PHY_PLL_FORCE_EN_M  (HP_SYS_PHY_PLL_FORCE_EN_V << HP_SYS_PHY_PLL_FORCE_EN_S)
+#define HP_SYSTEM_SYS_PHY_PLL_FORCE_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_PLL_FORCE_EN_S  19
+/** HP_SYS_PHY_PLL_EN : R/W; bitpos: [20]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_PHY_PLL_EN    (BIT(20))
+#define HP_SYSTEM_SYS_PHY_PLL_EN_M  (HP_SYS_PHY_PLL_EN_V << HP_SYS_PHY_PLL_EN_S)
+#define HP_SYSTEM_SYS_PHY_PLL_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_PHY_PLL_EN_S  20
+/** HP_SYS_OTG_SUSPENDM : R/W; bitpos: [21]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_SUSPENDM    (BIT(21))
+#define HP_SYSTEM_SYS_OTG_SUSPENDM_M  (HP_SYS_OTG_SUSPENDM_V << HP_SYS_OTG_SUSPENDM_S)
+#define HP_SYSTEM_SYS_OTG_SUSPENDM_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_SUSPENDM_S  21
+/** HP_SYS_OTG_PHY_TXBITSTUFF_EN : R/W; bitpos: [22]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_PHY_TXBITSTUFF_EN    (BIT(22))
+#define HP_SYSTEM_SYS_OTG_PHY_TXBITSTUFF_EN_M  (HP_SYS_OTG_PHY_TXBITSTUFF_EN_V << HP_SYS_OTG_PHY_TXBITSTUFF_EN_S)
+#define HP_SYSTEM_SYS_OTG_PHY_TXBITSTUFF_EN_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_PHY_TXBITSTUFF_EN_S  22
+/** HP_SYS_OTG_PHY_REFCLK_MODE : R/W; bitpos: [23]; default: 1;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_PHY_REFCLK_MODE    (BIT(23))
+#define HP_SYSTEM_SYS_OTG_PHY_REFCLK_MODE_M  (HP_SYS_OTG_PHY_REFCLK_MODE_V << HP_SYS_OTG_PHY_REFCLK_MODE_S)
+#define HP_SYSTEM_SYS_OTG_PHY_REFCLK_MODE_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_PHY_REFCLK_MODE_S  23
+/** HP_SYS_OTG_PHY_BISTEN : R/W; bitpos: [24]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SYS_OTG_PHY_BISTEN    (BIT(24))
+#define HP_SYSTEM_SYS_OTG_PHY_BISTEN_M  (HP_SYS_OTG_PHY_BISTEN_V << HP_SYS_OTG_PHY_BISTEN_S)
+#define HP_SYSTEM_SYS_OTG_PHY_BISTEN_V  0x00000001U
+#define HP_SYSTEM_SYS_OTG_PHY_BISTEN_S  24
+
+/** HP_TCM_ERR_RESP_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_ERR_RESP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x160)
+/** HP_TCM_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on tcm error response
+ */
+#define HP_SYSTEM_TCM_ERR_RESP_EN    (BIT(0))
+#define HP_SYSTEM_TCM_ERR_RESP_EN_M  (HP_TCM_ERR_RESP_EN_V << HP_TCM_ERR_RESP_EN_S)
+#define HP_SYSTEM_TCM_ERR_RESP_EN_V  0x00000001U
+#define HP_SYSTEM_TCM_ERR_RESP_EN_S  0
+
+/** HP_L2_MEM_REFRESH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_REFRESH_REG (DR_REG_HP_SYS_BASE + 0x164)
+/** HP_REG_L2_MEM_UNIT0_REFERSH_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT0_REFERSH_EN_V << HP_REG_L2_MEM_UNIT0_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_S  0
+/** HP_REG_L2_MEM_UNIT1_REFERSH_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT1_REFERSH_EN_V << HP_REG_L2_MEM_UNIT1_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_S  1
+/** HP_REG_L2_MEM_UNIT2_REFERSH_EN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT2_REFERSH_EN_V << HP_REG_L2_MEM_UNIT2_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_S  2
+/** HP_REG_L2_MEM_UNIT3_REFERSH_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN    (BIT(3))
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT3_REFERSH_EN_V << HP_REG_L2_MEM_UNIT3_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_S  3
+/** HP_REG_L2_MEM_UNIT4_REFERSH_EN : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN    (BIT(4))
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT4_REFERSH_EN_V << HP_REG_L2_MEM_UNIT4_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_S  4
+/** HP_REG_L2_MEM_UNIT5_REFERSH_EN : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN    (BIT(5))
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_M  (HP_REG_L2_MEM_UNIT5_REFERSH_EN_V << HP_REG_L2_MEM_UNIT5_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_S  5
+/** HP_REG_L2_MEM_REFERSH_CNT_RESET : R/W; bitpos: [6]; default: 1;
+ *  Set 1 to reset l2mem_refresh_cnt
+ */
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET    (BIT(6))
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_M  (HP_REG_L2_MEM_REFERSH_CNT_RESET_V << HP_REG_L2_MEM_REFERSH_CNT_RESET_S)
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_S  6
+/** HP_REG_L2_MEM_UNIT0_REFRESH_DONE : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE    (BIT(7))
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT0_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT0_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_S  7
+/** HP_REG_L2_MEM_UNIT1_REFRESH_DONE : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE    (BIT(8))
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT1_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT1_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_S  8
+/** HP_REG_L2_MEM_UNIT2_REFRESH_DONE : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE    (BIT(9))
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT2_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT2_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_S  9
+/** HP_REG_L2_MEM_UNIT3_REFRESH_DONE : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE    (BIT(10))
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT3_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT3_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_S  10
+/** HP_REG_L2_MEM_UNIT4_REFRESH_DONE : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE    (BIT(11))
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT4_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT4_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_S  11
+/** HP_REG_L2_MEM_UNIT5_REFRESH_DONE : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE    (BIT(12))
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_M  (HP_REG_L2_MEM_UNIT5_REFRESH_DONE_V << HP_REG_L2_MEM_UNIT5_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_S  12
+
+/** HP_TCM_INIT_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_INIT_REG (DR_REG_HP_SYS_BASE + 0x168)
+/** HP_REG_TCM_INIT_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_TCM_INIT_EN    (BIT(0))
+#define HP_SYSTEM_REG_TCM_INIT_EN_M  (HP_REG_TCM_INIT_EN_V << HP_REG_TCM_INIT_EN_S)
+#define HP_SYSTEM_REG_TCM_INIT_EN_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_INIT_EN_S  0
+/** HP_REG_TCM_INIT_CNT_RESET : R/W; bitpos: [1]; default: 1;
+ *  Set 1 to reset tcm init cnt
+ */
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET    (BIT(1))
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_M  (HP_REG_TCM_INIT_CNT_RESET_V << HP_REG_TCM_INIT_CNT_RESET_S)
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_S  1
+/** HP_REG_TCM_INIT_DONE : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_TCM_INIT_DONE    (BIT(2))
+#define HP_SYSTEM_REG_TCM_INIT_DONE_M  (HP_REG_TCM_INIT_DONE_V << HP_REG_TCM_INIT_DONE_S)
+#define HP_SYSTEM_REG_TCM_INIT_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_INIT_DONE_S  2
+
+/** HP_TCM_PARITY_CHECK_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_CHECK_CTRL_REG (DR_REG_HP_SYS_BASE + 0x16c)
+/** HP_TCM_PARITY_CHECK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on tcm parity check
+ */
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN    (BIT(0))
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN_M  (HP_TCM_PARITY_CHECK_EN_V << HP_TCM_PARITY_CHECK_EN_S)
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN_S  0
+
+/** HP_DESIGN_FOR_VERIFICATION0_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG (DR_REG_HP_SYS_BASE + 0x170)
+/** HP_DFV0 : R/W; bitpos: [31:0]; default: 0;
+ *  register for DV
+ */
+#define HP_SYSTEM_DFV0    0xFFFFFFFFU
+#define HP_SYSTEM_DFV0_M  (HP_DFV0_V << HP_DFV0_S)
+#define HP_SYSTEM_DFV0_V  0xFFFFFFFFU
+#define HP_SYSTEM_DFV0_S  0
+
+/** HP_DESIGN_FOR_VERIFICATION1_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG (DR_REG_HP_SYS_BASE + 0x174)
+/** HP_DFV1 : R/W; bitpos: [31:0]; default: 0;
+ *  register for DV
+ */
+#define HP_SYSTEM_DFV1    0xFFFFFFFFU
+#define HP_SYSTEM_DFV1_M  (HP_DFV1_V << HP_DFV1_S)
+#define HP_SYSTEM_DFV1_V  0xFFFFFFFFU
+#define HP_SYSTEM_DFV1_S  0
+
+/** HP_PSRAM_FLASH_ADDR_INTERCHANGE_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_REG (DR_REG_HP_SYS_BASE + 0x180)
+/** HP_PSRAM_FLASH_ADDR_INTERCHANGE_CPU : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu
+ *  access through cache
+ */
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU    (BIT(0))
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_M  (HP_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_V << HP_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_S)
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_V  0x00000001U
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_S  0
+/** HP_PSRAM_FLASH_ADDR_INTERCHANGE_DMA : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable addr interchange between psram and flash in axi matrix when dma
+ *  device access, lp core access and hp core access through ahb
+ */
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA    (BIT(1))
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_M  (HP_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_V << HP_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_S)
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_V  0x00000001U
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_S  1
+
+/** HP_AHB2AXI_BRESP_ERR_INT_RAW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x188)
+/** HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+ *  post write mode in ahb2axi.
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW    (BIT(0))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_M  (HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V << HP_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S  0
+
+/** HP_AHB2AXI_BRESP_ERR_INT_ST_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x18c)
+/** HP_CPU_ICM_H2X_BRESP_ERR_INT_ST : RO; bitpos: [31]; default: 0;
+ *  the masked interrupt status of  cpu_icm_h2x_bresp_err
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_M  (HP_CPU_ICM_H2X_BRESP_ERR_INT_ST_V << HP_CPU_ICM_H2X_BRESP_ERR_INT_ST_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S  31
+
+/** HP_AHB2AXI_BRESP_ERR_INT_ENA_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x190)
+/** HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to enable cpu_icm_h2x_bresp_err int
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_M  (HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V << HP_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S  31
+
+/** HP_AHB2AXI_BRESP_ERR_INT_CLR_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x194)
+/** HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  Write 1 to clear cpu_icm_h2x_bresp_err  int
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_M  (HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V << HP_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S  31
+
+/** HP_L2_MEM_ERR_RESP_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_L2_MEM_ERR_RESP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x198)
+/** HP_L2_MEM_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on l2mem error response
+ */
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN    (BIT(0))
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_M  (HP_L2_MEM_ERR_RESP_EN_V << HP_L2_MEM_ERR_RESP_EN_S)
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_V  0x00000001U
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_S  0
+
+/** HP_L2_MEM_AHB_BUFFER_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_L2_MEM_AHB_BUFFER_CTRL_REG (DR_REG_HP_SYS_BASE + 0x19c)
+/** HP_L2_MEM_AHB_WRBUFFER_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on l2mem ahb wr buffer
+ */
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN    (BIT(0))
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_M  (HP_L2_MEM_AHB_WRBUFFER_EN_V << HP_L2_MEM_AHB_WRBUFFER_EN_S)
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_V  0x00000001U
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_S  0
+/** HP_L2_MEM_AHB_RDBUFFER_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to turn on l2mem ahb rd buffer
+ */
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN    (BIT(1))
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_M  (HP_L2_MEM_AHB_RDBUFFER_EN_V << HP_L2_MEM_AHB_RDBUFFER_EN_S)
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_V  0x00000001U
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_S  1
+
+/** HP_CORE_DMACTIVE_LPCORE_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG (DR_REG_HP_SYS_BASE + 0x1a0)
+/** HP_CORE_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0;
+ *  hp core dmactive_lpcore value
+ */
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE    (BIT(0))
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_M  (HP_CORE_DMACTIVE_LPCORE_V << HP_CORE_DMACTIVE_LPCORE_S)
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_V  0x00000001U
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_S  0
+
+/** HP_CORE_ERR_RESP_DIS_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_REG (DR_REG_HP_SYS_BASE + 0x1a4)
+/** HP_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
+ *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
+ *  disable ahb err resp.
+ */
+#define HP_SYSTEM_CORE_ERR_RESP_DIS    0x00000007U
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_M  (HP_CORE_ERR_RESP_DIS_V << HP_CORE_ERR_RESP_DIS_S)
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_V  0x00000007U
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_S  0
+
+/** HP_CORE_TIMEOUT_INT_RAW_REG register
+ *  Hp core bus timeout interrupt raw register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x1a8)
+/** HP_CORE0_AHB_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  the raw interrupt status of hp core0  ahb timeout
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_M  (HP_CORE0_AHB_TIMEOUT_INT_RAW_V << HP_CORE0_AHB_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_S  0
+/** HP_CORE1_AHB_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  the raw interrupt status of hp core1  ahb timeout
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_M  (HP_CORE1_AHB_TIMEOUT_INT_RAW_V << HP_CORE1_AHB_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_S  1
+/** HP_CORE0_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  the raw interrupt status of hp core0  ibus timeout
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_M  (HP_CORE0_IBUS_TIMEOUT_INT_RAW_V << HP_CORE0_IBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S  2
+/** HP_CORE1_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  the raw interrupt status of hp core1  ibus timeout
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_M  (HP_CORE1_IBUS_TIMEOUT_INT_RAW_V << HP_CORE1_IBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S  3
+/** HP_CORE0_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  the raw interrupt status of hp core0  dbus timeout
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_M  (HP_CORE0_DBUS_TIMEOUT_INT_RAW_V << HP_CORE0_DBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S  4
+/** HP_CORE1_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  the raw interrupt status of hp core1  dbus timeout
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_M  (HP_CORE1_DBUS_TIMEOUT_INT_RAW_V << HP_CORE1_DBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S  5
+
+/** HP_CORE_TIMEOUT_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x1ac)
+/** HP_CORE0_AHB_TIMEOUT_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of hp core0  ahb timeout
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_M  (HP_CORE0_AHB_TIMEOUT_INT_ST_V << HP_CORE0_AHB_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_S  0
+/** HP_CORE1_AHB_TIMEOUT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of hp core1  ahb timeout
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_M  (HP_CORE1_AHB_TIMEOUT_INT_ST_V << HP_CORE1_AHB_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_S  1
+/** HP_CORE0_IBUS_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  the masked interrupt status of hp core0  ibus timeout
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_M  (HP_CORE0_IBUS_TIMEOUT_INT_ST_V << HP_CORE0_IBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S  2
+/** HP_CORE1_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  the masked interrupt status of hp core1  ibus timeout
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_M  (HP_CORE1_IBUS_TIMEOUT_INT_ST_V << HP_CORE1_IBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S  3
+/** HP_CORE0_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  the masked interrupt status of hp core0  dbus timeout
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_M  (HP_CORE0_DBUS_TIMEOUT_INT_ST_V << HP_CORE0_DBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S  4
+/** HP_CORE1_DBUS_TIMEOUT_INT_ST : RO; bitpos: [5]; default: 0;
+ *  the masked interrupt status of hp core1  dbus timeout
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_M  (HP_CORE1_DBUS_TIMEOUT_INT_ST_V << HP_CORE1_DBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S  5
+
+/** HP_CORE_TIMEOUT_INT_ENA_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x1b0)
+/** HP_CORE0_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable hp_core0_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_M  (HP_CORE0_AHB_TIMEOUT_INT_ENA_V << HP_CORE0_AHB_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_S  0
+/** HP_CORE1_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable hp_core1_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_M  (HP_CORE1_AHB_TIMEOUT_INT_ENA_V << HP_CORE1_AHB_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_S  1
+/** HP_CORE0_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable hp_core0_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_M  (HP_CORE0_IBUS_TIMEOUT_INT_ENA_V << HP_CORE0_IBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S  2
+/** HP_CORE1_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable hp_core1_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_M  (HP_CORE1_IBUS_TIMEOUT_INT_ENA_V << HP_CORE1_IBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S  3
+/** HP_CORE0_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable hp_core0_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_M  (HP_CORE0_DBUS_TIMEOUT_INT_ENA_V << HP_CORE0_DBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S  4
+/** HP_CORE1_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable hp_core1_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_M  (HP_CORE1_DBUS_TIMEOUT_INT_ENA_V << HP_CORE1_DBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S  5
+
+/** HP_CORE_TIMEOUT_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x1b4)
+/** HP_CORE0_AHB_TIMEOUT_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear hp_core0_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_M  (HP_CORE0_AHB_TIMEOUT_INT_CLR_V << HP_CORE0_AHB_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_S  0
+/** HP_CORE1_AHB_TIMEOUT_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear hp_core1_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_M  (HP_CORE1_AHB_TIMEOUT_INT_CLR_V << HP_CORE1_AHB_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_S  1
+/** HP_CORE0_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear hp_core0_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_M  (HP_CORE0_IBUS_TIMEOUT_INT_CLR_V << HP_CORE0_IBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S  2
+/** HP_CORE1_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear hp_core1_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_M  (HP_CORE1_IBUS_TIMEOUT_INT_CLR_V << HP_CORE1_IBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S  3
+/** HP_CORE0_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear hp_core0_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_M  (HP_CORE0_DBUS_TIMEOUT_INT_CLR_V << HP_CORE0_DBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S  4
+/** HP_CORE1_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear hp_core1_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_M  (HP_CORE1_DBUS_TIMEOUT_INT_CLR_V << HP_CORE1_DBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S  5
+
+/** HP_GPIO_O_HYS_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HYS_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x1c0)
+/** HP_REG_GPIO_0_HYS_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  hys control for gpio47~16
+ */
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_M  (HP_REG_GPIO_0_HYS_LOW_V << HP_REG_GPIO_0_HYS_LOW_S)
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_S  0
+
+/** HP_GPIO_O_HYS_CTRL1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HYS_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x1c4)
+/** HP_REG_GPIO_0_HYS_HIGH : R/W; bitpos: [8:0]; default: 0;
+ *  hys control for gpio56~48
+ */
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH    0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_M  (HP_REG_GPIO_0_HYS_HIGH_V << HP_REG_GPIO_0_HYS_HIGH_S)
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_V  0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_S  0
+
+/** HP_RSA_PD_CTRL_REG register
+ *  rsa pd ctrl register
+ */
+#define HP_SYSTEM_RSA_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1d0)
+/** HP_RSA_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down rsa internal memory.
+ */
+#define HP_SYSTEM_RSA_MEM_FORCE_PD    (BIT(0))
+#define HP_SYSTEM_RSA_MEM_FORCE_PD_M  (HP_RSA_MEM_FORCE_PD_V << HP_RSA_MEM_FORCE_PD_S)
+#define HP_SYSTEM_RSA_MEM_FORCE_PD_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_FORCE_PD_S  0
+/** HP_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up rsa internal memory
+ */
+#define HP_SYSTEM_RSA_MEM_FORCE_PU    (BIT(1))
+#define HP_SYSTEM_RSA_MEM_FORCE_PU_M  (HP_RSA_MEM_FORCE_PU_V << HP_RSA_MEM_FORCE_PU_S)
+#define HP_SYSTEM_RSA_MEM_FORCE_PU_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_FORCE_PU_S  1
+/** HP_RSA_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down rsa internal memory.
+ */
+#define HP_SYSTEM_RSA_MEM_PD    (BIT(2))
+#define HP_SYSTEM_RSA_MEM_PD_M  (HP_RSA_MEM_PD_V << HP_RSA_MEM_PD_S)
+#define HP_SYSTEM_RSA_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_PD_S  2
+
+/** HP_ECC_PD_CTRL_REG register
+ *  ecc pd ctrl register
+ */
+#define HP_SYSTEM_ECC_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1d4)
+/** HP_ECC_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down ecc internal memory.
+ */
+#define HP_SYSTEM_ECC_MEM_FORCE_PD    (BIT(0))
+#define HP_SYSTEM_ECC_MEM_FORCE_PD_M  (HP_ECC_MEM_FORCE_PD_V << HP_ECC_MEM_FORCE_PD_S)
+#define HP_SYSTEM_ECC_MEM_FORCE_PD_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_FORCE_PD_S  0
+/** HP_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up ecc internal memory
+ */
+#define HP_SYSTEM_ECC_MEM_FORCE_PU    (BIT(1))
+#define HP_SYSTEM_ECC_MEM_FORCE_PU_M  (HP_ECC_MEM_FORCE_PU_V << HP_ECC_MEM_FORCE_PU_S)
+#define HP_SYSTEM_ECC_MEM_FORCE_PU_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_FORCE_PU_S  1
+/** HP_ECC_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down ecc internal memory.
+ */
+#define HP_SYSTEM_ECC_MEM_PD    (BIT(2))
+#define HP_SYSTEM_ECC_MEM_PD_M  (HP_ECC_MEM_PD_V << HP_ECC_MEM_PD_S)
+#define HP_SYSTEM_ECC_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_PD_S  2
+
+/** HP_RNG_CFG_REG register
+ *  rng cfg register
+ */
+#define HP_SYSTEM_RNG_CFG_REG (DR_REG_HP_SYS_BASE + 0x1d8)
+/** HP_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE    (BIT(0))
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE_M  (HP_RNG_SAMPLE_ENABLE_V << HP_RNG_SAMPLE_ENABLE_S)
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE_V  0x00000001U
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE_S  0
+/** HP_RNG_CHAIN_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
+ *  chain clk div num to pad for debug
+ */
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM    0x000000FFU
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_M  (HP_RNG_CHAIN_CLK_DIV_NUM_V << HP_RNG_CHAIN_CLK_DIV_NUM_S)
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S  16
+
+/** HP_UART_PD_CTRL_REG register
+ *  ecc pd ctrl register
+ */
+#define HP_SYSTEM_UART_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1dc)
+/** HP_UART_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down hp uart internal memory.
+ */
+#define HP_SYSTEM_UART_MEM_FORCE_PD    (BIT(0))
+#define HP_SYSTEM_UART_MEM_FORCE_PD_M  (HP_UART_MEM_FORCE_PD_V << HP_UART_MEM_FORCE_PD_S)
+#define HP_SYSTEM_UART_MEM_FORCE_PD_V  0x00000001U
+#define HP_SYSTEM_UART_MEM_FORCE_PD_S  0
+/** HP_UART_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up hp uart  internal memory
+ */
+#define HP_SYSTEM_UART_MEM_FORCE_PU    (BIT(1))
+#define HP_SYSTEM_UART_MEM_FORCE_PU_M  (HP_UART_MEM_FORCE_PU_V << HP_UART_MEM_FORCE_PU_S)
+#define HP_SYSTEM_UART_MEM_FORCE_PU_V  0x00000001U
+#define HP_SYSTEM_UART_MEM_FORCE_PU_S  1
+
+/** HP_PERI_MEM_CLK_FORCE_ON_REG register
+ *  hp peri mem clk force on regpster
+ */
+#define HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG (DR_REG_HP_SYS_BASE + 0x1e0)
+/** HP_RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force on mem clk in rmt
+ */
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_M  (HP_RMT_MEM_CLK_FORCE_ON_V << HP_RMT_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S  0
+/** HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to force on tx mem clk in bitscrambler
+ */
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON    (BIT(1))
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_M  (HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V << HP_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S  1
+/** HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force on rx mem clk in bitscrambler
+ */
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON    (BIT(2))
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_M  (HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V << HP_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S  2
+/** HP_GDMA_MEM_CLK_FORCE_ON : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force on mem clk in gdma
+ */
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON    (BIT(3))
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_M  (HP_GDMA_MEM_CLK_FORCE_ON_V << HP_GDMA_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S  3
+
+/** HP_USB_OTGHS_PHY_ST_REG register
+ *  Usb otg2.0 PHY status register
+ */
+#define HP_SYSTEM_USB_OTGHS_PHY_ST_REG (DR_REG_HP_SYS_BASE + 0x1e8)
+/** HP_USB_SOFT_RESET_ACTV_PDOMAIN : RO; bitpos: [0]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_USB_SOFT_RESET_ACTV_PDOMAIN    (BIT(0))
+#define HP_SYSTEM_USB_SOFT_RESET_ACTV_PDOMAIN_M  (HP_USB_SOFT_RESET_ACTV_PDOMAIN_V << HP_USB_SOFT_RESET_ACTV_PDOMAIN_S)
+#define HP_SYSTEM_USB_SOFT_RESET_ACTV_PDOMAIN_V  0x00000001U
+#define HP_SYSTEM_USB_SOFT_RESET_ACTV_PDOMAIN_S  0
+/** HP_UTMISRP_SESSEND : RO; bitpos: [1]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_UTMISRP_SESSEND    (BIT(1))
+#define HP_SYSTEM_UTMISRP_SESSEND_M  (HP_UTMISRP_SESSEND_V << HP_UTMISRP_SESSEND_S)
+#define HP_SYSTEM_UTMISRP_SESSEND_V  0x00000001U
+#define HP_SYSTEM_UTMISRP_SESSEND_S  1
+/** HP_UTMIOTG_VBUSVALID : RO; bitpos: [2]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_UTMIOTG_VBUSVALID    (BIT(2))
+#define HP_SYSTEM_UTMIOTG_VBUSVALID_M  (HP_UTMIOTG_VBUSVALID_V << HP_UTMIOTG_VBUSVALID_S)
+#define HP_SYSTEM_UTMIOTG_VBUSVALID_V  0x00000001U
+#define HP_SYSTEM_UTMIOTG_VBUSVALID_S  2
+/** HP_UTMISRP_BVALID : RO; bitpos: [3]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_UTMISRP_BVALID    (BIT(3))
+#define HP_SYSTEM_UTMISRP_BVALID_M  (HP_UTMISRP_BVALID_V << HP_UTMISRP_BVALID_S)
+#define HP_SYSTEM_UTMISRP_BVALID_V  0x00000001U
+#define HP_SYSTEM_UTMISRP_BVALID_S  3
+/** HP_UTMISRP_SESSVALID : RO; bitpos: [4]; default: 0;
+ *  Todo
+ */
+#define HP_SYSTEM_UTMISRP_SESSVALID    (BIT(4))
+#define HP_SYSTEM_UTMISRP_SESSVALID_M  (HP_UTMISRP_SESSVALID_V << HP_UTMISRP_SESSVALID_S)
+#define HP_SYSTEM_UTMISRP_SESSVALID_V  0x00000001U
+#define HP_SYSTEM_UTMISRP_SESSVALID_S  4
+
+/** HP_CPU_WAKEUP_EVENT_REG register
+ *  cpu wakeup event ctrl register
+ */
+#define HP_SYSTEM_CPU_WAKEUP_EVENT_REG (DR_REG_HP_SYS_BASE + 0x1ec)
+/** HP_CORE0_WAKEUP_EVENT : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to wake up hp core0
+ */
+#define HP_SYSTEM_CORE0_WAKEUP_EVENT    (BIT(0))
+#define HP_SYSTEM_CORE0_WAKEUP_EVENT_M  (HP_CORE0_WAKEUP_EVENT_V << HP_CORE0_WAKEUP_EVENT_S)
+#define HP_SYSTEM_CORE0_WAKEUP_EVENT_V  0x00000001U
+#define HP_SYSTEM_CORE0_WAKEUP_EVENT_S  0
+/** HP_CORE1_WAKEUP_EVENT : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to wake up hp core1
+ */
+#define HP_SYSTEM_CORE1_WAKEUP_EVENT    (BIT(1))
+#define HP_SYSTEM_CORE1_WAKEUP_EVENT_M  (HP_CORE1_WAKEUP_EVENT_V << HP_CORE1_WAKEUP_EVENT_S)
+#define HP_SYSTEM_CORE1_WAKEUP_EVENT_V  0x00000001U
+#define HP_SYSTEM_CORE1_WAKEUP_EVENT_S  1
+
+/** HP_HP2LP_INTR_GROUP0_EN_REG register
+ *  HpP2LP Interrupt Enable Register Group0
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP0_EN_REG (DR_REG_HP_SYS_BASE + 0x1f0)
+/** HP_H2LP_INTR_GROUP0_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP0_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP0_EN_M  (HP_H2LP_INTR_GROUP0_EN_V << HP_H2LP_INTR_GROUP0_EN_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP0_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP0_EN_S  0
+
+/** HP_HP2LP_INTR_GROUP1_EN_REG register
+ *  HpP2LP Interrupt Enable Register Group1
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP1_EN_REG (DR_REG_HP_SYS_BASE + 0x1f4)
+/** HP_H2LP_INTR_GROUP1_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP1_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP1_EN_M  (HP_H2LP_INTR_GROUP1_EN_V << HP_H2LP_INTR_GROUP1_EN_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP1_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP1_EN_S  0
+
+/** HP_HP2LP_INTR_GROUP2_EN_REG register
+ *  HpP2LP Interrupt Enable Register Group2
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP2_EN_REG (DR_REG_HP_SYS_BASE + 0x1f8)
+/** HP_H2LP_INTR_GROUP2_EN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP2_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP2_EN_M  (HP_H2LP_INTR_GROUP2_EN_V << HP_H2LP_INTR_GROUP2_EN_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP2_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP2_EN_S  0
+
+/** HP_HP2LP_INTR_GROUP3_EN_REG register
+ *  HpP2LP Interrupt Enable Register Group3
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP3_EN_REG (DR_REG_HP_SYS_BASE + 0x1fc)
+/** HP_H2LP_INTR_GROUP3_EN : R/W; bitpos: [13:0]; default: 16383;
+ *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP3_EN    0x00003FFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP3_EN_M  (HP_H2LP_INTR_GROUP3_EN_V << HP_H2LP_INTR_GROUP3_EN_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP3_EN_V  0x00003FFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP3_EN_S  0
+
+/** HP_HP2LP_INTR_GROUP0_ST_REG register
+ *  HpP2LP Interrupt Status Register Group0
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP0_ST_REG (DR_REG_HP_SYS_BASE + 0x200)
+/** HP_H2LP_INTR_GROUP0_ST : RO; bitpos: [31:0]; default: 0;
+ *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP0_ST    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP0_ST_M  (HP_H2LP_INTR_GROUP0_ST_V << HP_H2LP_INTR_GROUP0_ST_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP0_ST_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP0_ST_S  0
+
+/** HP_HP2LP_INTR_GROUP1_ST_REG register
+ *  HpP2LP Interrupt Enable Register Group1
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP1_ST_REG (DR_REG_HP_SYS_BASE + 0x204)
+/** HP_H2LP_INTR_GROUP1_ST : RO; bitpos: [31:0]; default: 0;
+ *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP1_ST    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP1_ST_M  (HP_H2LP_INTR_GROUP1_ST_V << HP_H2LP_INTR_GROUP1_ST_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP1_ST_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP1_ST_S  0
+
+/** HP_HP2LP_INTR_GROUP2_ST_REG register
+ *  HpP2LP Interrupt Enable Register Group2
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP2_ST_REG (DR_REG_HP_SYS_BASE + 0x208)
+/** HP_H2LP_INTR_GROUP2_ST : RO; bitpos: [31:0]; default: 0;
+ *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP2_ST    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP2_ST_M  (HP_H2LP_INTR_GROUP2_ST_V << HP_H2LP_INTR_GROUP2_ST_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP2_ST_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP2_ST_S  0
+
+/** HP_HP2LP_INTR_GROUP3_ST_REG register
+ *  HpP2LP Interrupt Enable Register Group3
+ */
+#define HP_SYSTEM_HP2LP_INTR_GROUP3_ST_REG (DR_REG_HP_SYS_BASE + 0x20c)
+/** HP_H2LP_INTR_GROUP3_ST : RO; bitpos: [13:0]; default: 0;
+ *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+ */
+#define HP_SYSTEM_H2LP_INTR_GROUP3_ST    0x00003FFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP3_ST_M  (HP_H2LP_INTR_GROUP3_ST_V << HP_H2LP_INTR_GROUP3_ST_S)
+#define HP_SYSTEM_H2LP_INTR_GROUP3_ST_V  0x00003FFFU
+#define HP_SYSTEM_H2LP_INTR_GROUP3_ST_S  0
+
+/** HP_HP2LP_WAKEUP_GROUP0_EN_REG register
+ *  HpP2LP Wakeup Enable Register Group0
+ */
+#define HP_SYSTEM_HP2LP_WAKEUP_GROUP0_EN_REG (DR_REG_HP_SYS_BASE + 0x210)
+/** HP_H2LP_WAKEUP_GROUP0_EN : R/W; bitpos: [31:0]; default: 0;
+ *  Set each bit to enable corresponding peripheral wakeup to PMU.
+ */
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP0_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP0_EN_M  (HP_H2LP_WAKEUP_GROUP0_EN_V << HP_H2LP_WAKEUP_GROUP0_EN_S)
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP0_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP0_EN_S  0
+
+/** HP_HP2LP_WAKEUP_GROUP1_EN_REG register
+ *  HpP2LP Wakeup Enable Register Group1
+ */
+#define HP_SYSTEM_HP2LP_WAKEUP_GROUP1_EN_REG (DR_REG_HP_SYS_BASE + 0x214)
+/** HP_H2LP_WAKEUP_GROUP1_EN : R/W; bitpos: [31:0]; default: 0;
+ *  Set each bit to enable corresponding peripheral wakeup to PMU.
+ */
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP1_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP1_EN_M  (HP_H2LP_WAKEUP_GROUP1_EN_V << HP_H2LP_WAKEUP_GROUP1_EN_S)
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP1_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP1_EN_S  0
+
+/** HP_HP2LP_WAKEUP_GROUP2_EN_REG register
+ *  HpP2LP Wakeup Enable Register Group2
+ */
+#define HP_SYSTEM_HP2LP_WAKEUP_GROUP2_EN_REG (DR_REG_HP_SYS_BASE + 0x218)
+/** HP_H2LP_WAKEUP_GROUP2_EN : R/W; bitpos: [31:0]; default: 0;
+ *  Set each bit to enable corresponding peripheral wakeup to PMU.
+ */
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP2_EN    0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP2_EN_M  (HP_H2LP_WAKEUP_GROUP2_EN_V << HP_H2LP_WAKEUP_GROUP2_EN_S)
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP2_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP2_EN_S  0
+
+/** HP_HP2LP_WAKEUP_GROUP3_EN_REG register
+ *  HpP2LP Wakeup Enable Register Group3
+ */
+#define HP_SYSTEM_HP2LP_WAKEUP_GROUP3_EN_REG (DR_REG_HP_SYS_BASE + 0x21c)
+/** HP_H2LP_WAKEUP_GROUP3_EN : R/W; bitpos: [13:0]; default: 0;
+ *  Set each bit to enable corresponding peripheral wakeup to PMU.
+ */
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP3_EN    0x00003FFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP3_EN_M  (HP_H2LP_WAKEUP_GROUP3_EN_V << HP_H2LP_WAKEUP_GROUP3_EN_S)
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP3_EN_V  0x00003FFFU
+#define HP_SYSTEM_H2LP_WAKEUP_GROUP3_EN_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/hp_system_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/hp_system_struct.h
new file mode 100644
index 0000000000..e48b0e6b43
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/hp_system_struct.h
@@ -0,0 +1,2257 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: HP SYS VER DATE REG */
+/** Type of sys_ver_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [31:0]; default: 539296519;
+         *  NA
+         */
+        uint32_t reg_ver_date:32;
+    };
+    uint32_t val;
+} hp_sys_ver_date_reg_t;
+
+
+/** Group: HP CLK EN REG */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_clk_en_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 0 REG */
+/** Type of cpu_int_from_cpu_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_0 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cpu_int_from_cpu_0_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 1 REG */
+/** Type of cpu_int_from_cpu_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_1 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cpu_int_from_cpu_1_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 2 REG */
+/** Type of cpu_int_from_cpu_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_2 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_2:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cpu_int_from_cpu_2_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 3 REG */
+/** Type of cpu_int_from_cpu_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_3 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_3:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cpu_int_from_cpu_3_reg_t;
+
+
+/** Group: HP CACHE CLK CONFIG REG */
+/** Type of cache_clk_config register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_cache_clk_on : R/W; bitpos: [0]; default: 1;
+         *  l2 cache clk enable
+         */
+        uint32_t reg_l2_cache_clk_on:1;
+        /** reg_l1_d_cache_clk_on : R/W; bitpos: [1]; default: 1;
+         *  l1 dcahce clk enable
+         */
+        uint32_t reg_l1_d_cache_clk_on:1;
+        uint32_t reserved_2:2;
+        /** reg_l1_i1_cache_clk_on : R/W; bitpos: [4]; default: 1;
+         *  l1 icahce1 clk enable
+         */
+        uint32_t reg_l1_i1_cache_clk_on:1;
+        /** reg_l1_i0_cache_clk_on : R/W; bitpos: [5]; default: 1;
+         *  l1 icahce0 clk enable
+         */
+        uint32_t reg_l1_i0_cache_clk_on:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_cache_clk_config_reg_t;
+
+
+/** Group: HP CACHE RESET CONFIG REG */
+/** Type of cache_reset_config register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** reg_l1_d_cache_reset : R/W; bitpos: [1]; default: 0;
+         *  set 1 to reset l1 dcahce
+         */
+        uint32_t reg_l1_d_cache_reset:1;
+        uint32_t reserved_2:2;
+        /** reg_l1_i1_cache_reset : R/W; bitpos: [4]; default: 0;
+         *  set 1 to reset l1 icahce1
+         */
+        uint32_t reg_l1_i1_cache_reset:1;
+        /** reg_l1_i0_cache_reset : R/W; bitpos: [5]; default: 0;
+         *  set 1 to reset l1 icahce0
+         */
+        uint32_t reg_l1_i0_cache_reset:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_cache_reset_config_reg_t;
+
+
+/** Group: HP SYS DMA ADDR CTRL REG */
+/** Type of sys_dma_addr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sys_dma_addr_sel : R/W; bitpos: [0]; default: 0;
+         *  0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx
+         */
+        uint32_t reg_sys_dma_addr_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_dma_addr_ctrl_reg_t;
+
+
+/** Group: HP TCM RAM WRR CONFIG REG */
+/** Type of tcm_ram_wrr_config register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tcm_ram_ibus0_wt : R/W; bitpos: [2:0]; default: 7;
+         *  weight value of ibus0
+         */
+        uint32_t reg_tcm_ram_ibus0_wt:3;
+        /** reg_tcm_ram_ibus1_wt : R/W; bitpos: [5:3]; default: 7;
+         *  weight value of ibus1
+         */
+        uint32_t reg_tcm_ram_ibus1_wt:3;
+        /** reg_tcm_ram_ibus2_wt : R/W; bitpos: [8:6]; default: 4;
+         *  weight value of ibus2
+         */
+        uint32_t reg_tcm_ram_ibus2_wt:3;
+        /** reg_tcm_ram_ibus3_wt : R/W; bitpos: [11:9]; default: 4;
+         *  weight value of ibus3
+         */
+        uint32_t reg_tcm_ram_ibus3_wt:3;
+        /** reg_tcm_ram_dbus0_wt : R/W; bitpos: [14:12]; default: 5;
+         *  weight value of dbus0
+         */
+        uint32_t reg_tcm_ram_dbus0_wt:3;
+        /** reg_tcm_ram_dbus1_wt : R/W; bitpos: [17:15]; default: 5;
+         *  weight value of dbus1
+         */
+        uint32_t reg_tcm_ram_dbus1_wt:3;
+        /** reg_tcm_ram_dbus2_wt : R/W; bitpos: [20:18]; default: 3;
+         *  weight value of dbus2
+         */
+        uint32_t reg_tcm_ram_dbus2_wt:3;
+        /** reg_tcm_ram_dbus3_wt : R/W; bitpos: [23:21]; default: 3;
+         *  weight value of dbus3
+         */
+        uint32_t reg_tcm_ram_dbus3_wt:3;
+        /** reg_tcm_ram_dma_wt : R/W; bitpos: [26:24]; default: 2;
+         *  weight value of dma
+         */
+        uint32_t reg_tcm_ram_dma_wt:3;
+        uint32_t reserved_27:4;
+        /** reg_tcm_ram_wrr_high : R/W; bitpos: [31]; default: 1;
+         *  enable weighted round robin arbitration
+         */
+        uint32_t reg_tcm_ram_wrr_high:1;
+    };
+    uint32_t val;
+} hp_tcm_ram_wrr_config_reg_t;
+
+
+/** Group: HP TCM SW PARITY BWE MASK REG */
+/** Type of tcm_sw_parity_bwe_mask register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tcm_sw_parity_bwe_mask_ctrl : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to mask tcm bwe parity code bit
+         */
+        uint32_t reg_tcm_sw_parity_bwe_mask_ctrl:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_tcm_sw_parity_bwe_mask_reg_t;
+
+
+/** Group: HP TCM RAM PWR CTRL0 REG */
+/** Type of tcm_ram_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_tcm_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  hp_tcm clk gatig force on
+         */
+        uint32_t reg_hp_tcm_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_tcm_ram_pwr_ctrl0_reg_t;
+
+
+/** Group: HP L2 ROM PWR CTRL0 REG */
+/** Type of l2_rom_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_rom_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  l2_rom clk gating force on
+         */
+        uint32_t reg_l2_rom_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_rom_pwr_ctrl0_reg_t;
+
+
+/** Group: HP PROBEA CTRL REG */
+/** Type of probea_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  module's probe_out[31:0] in a mode
+         */
+        uint32_t reg_probe_a_mod_sel:16;
+        /** reg_probe_a_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  This field is used to selec module's probe_out[31:0] as probe out in a mode
+         */
+        uint32_t reg_probe_a_top_sel:8;
+        /** reg_probe_l_sel : R/W; bitpos: [25:24]; default: 0;
+         *  This field is used to selec probe_out[31:16]
+         */
+        uint32_t reg_probe_l_sel:2;
+        /** reg_probe_h_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This field is used to selec probe_out[31:16]
+         */
+        uint32_t reg_probe_h_sel:2;
+        /** reg_probe_global_en : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to enable global debug probe in hp system.
+         */
+        uint32_t reg_probe_global_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_probea_ctrl_reg_t;
+
+
+/** Group: HP PROBEB CTRL REG */
+/** Type of probeb_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  module's probe_out[31:0] in b mode.
+         */
+        uint32_t reg_probe_b_mod_sel:16;
+        /** reg_probe_b_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
+         */
+        uint32_t reg_probe_b_top_sel:8;
+        /** reg_probe_b_en : R/W; bitpos: [24]; default: 0;
+         *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
+         */
+        uint32_t reg_probe_b_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_probeb_ctrl_reg_t;
+
+
+/** Group: HP PROBE OUT REG */
+/** Type of probe_out register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_top_out : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_probe_top_out:32;
+    };
+    uint32_t val;
+} hp_probe_out_reg_t;
+
+
+/** Group: HP L2 MEM RAM PWR CTRL0 REG */
+/** Type of l2_mem_ram_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  l2ram clk_gating force on
+         */
+        uint32_t reg_l2_mem_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_mem_ram_pwr_ctrl0_reg_t;
+
+
+/** Group: HP CPU CORESTALLED ST REG */
+/** Type of cpu_corestalled_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_corestalled_st : RO; bitpos: [0]; default: 0;
+         *  hp core0 corestalled status
+         */
+        uint32_t reg_core0_corestalled_st:1;
+        /** reg_core1_corestalled_st : RO; bitpos: [1]; default: 0;
+         *  hp core1 corestalled status
+         */
+        uint32_t reg_core1_corestalled_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_cpu_corestalled_st_reg_t;
+
+
+/** Group: HP CRYPTO CTRL REG */
+/** Type of crypto_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_spi_manual_encrypt:1;
+        /** reg_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_db_encrypt:1;
+        /** reg_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_g0cb_decrypt:1;
+        /** reg_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_manual_encrypt:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_crypto_ctrl_reg_t;
+
+
+/** Group: HP GPIO O HOLD CTRL0 REG */
+/** Type of gpio_o_hold_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0;
+         *  hold control for gpio47~16
+         */
+        uint32_t reg_gpio_0_hold_low:32;
+    };
+    uint32_t val;
+} hp_gpio_o_hold_ctrl0_reg_t;
+
+
+/** Group: HP GPIO O HOLD CTRL1 REG */
+/** Type of gpio_o_hold_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0;
+         *  hold control for gpio56~48
+         */
+        uint32_t reg_gpio_0_hold_high:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_gpio_o_hold_ctrl1_reg_t;
+
+
+/** Group: HP SYS RDN ECO CS REG */
+/** Type of sys_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_sys_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_sys_rdn_eco_en:1;
+        /** reg_hp_sys_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_sys_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_rdn_eco_cs_reg_t;
+
+
+/** Group: HP CACHE APB POSTW EN REG */
+/** Type of cache_apb_postw_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cache_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  cache apb register interface post write enable, 1 will speed up write, but will
+         *  take some time to update value to register
+         */
+        uint32_t reg_cache_apb_postw_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_cache_apb_postw_en_reg_t;
+
+
+/** Group: HP L2 MEM SUBSIZE REG */
+/** Type of l2_mem_subsize register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_sub_blksize : R/W; bitpos: [1:0]; default: 0;
+         *  l2mem sub block size 00=>32 01=>64 10=>128 11=>256
+         */
+        uint32_t reg_l2_mem_sub_blksize:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_l2_mem_subsize_reg_t;
+
+
+/** Group: HP L2 MEM INT RAW REG */
+/** Type of l2_mem_int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  intr triggered when two bit error detected and corrected from ecc
+         */
+        uint32_t reg_l2_mem_ecc_err_int_raw:1;
+        /** reg_l2_mem_exceed_addr_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds
+         *  0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_raw:1;
+        /** reg_l2_mem_err_resp_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  intr triggered when err response occurs
+         */
+        uint32_t reg_l2_mem_err_resp_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_l2_mem_int_raw_reg_t;
+
+
+/** Group: HP L2 MEM INT ST REG */
+/** Type of l2_mem_int_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_st : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_st:1;
+        /** reg_l2_mem_exceed_addr_int_st : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_st:1;
+        /** reg_l2_mem_err_resp_int_st : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_err_resp_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_l2_mem_int_st_reg_t;
+
+
+/** Group: HP L2 MEM INT ENA REG */
+/** Type of l2_mem_int_ena register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_ena : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_ena:1;
+        /** reg_l2_mem_exceed_addr_int_ena : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_ena:1;
+        /** reg_l2_mem_err_resp_int_ena : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_err_resp_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_l2_mem_int_ena_reg_t;
+
+
+/** Group: HP L2 MEM INT CLR REG */
+/** Type of l2_mem_int_clr register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_clr : WT; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_clr:1;
+        /** reg_l2_mem_exceed_addr_int_clr : WT; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_clr:1;
+        /** reg_l2_mem_err_resp_int_clr : WT; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_err_resp_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_l2_mem_int_clr_reg_t;
+
+
+/** Group: HP L2 MEM L2 RAM ECC REG */
+/** Type of l2_mem_l2_ram_ecc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_ram_unit0_ecc_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit0_ecc_en:1;
+        /** reg_l2_ram_unit1_ecc_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit1_ecc_en:1;
+        /** reg_l2_ram_unit2_ecc_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit2_ecc_en:1;
+        /** reg_l2_ram_unit3_ecc_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit3_ecc_en:1;
+        /** reg_l2_ram_unit4_ecc_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit4_ecc_en:1;
+        /** reg_l2_ram_unit5_ecc_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit5_ecc_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_l2_mem_l2_ram_ecc_reg_t;
+
+
+/** Group: HP L2 MEM INT RECORD0 REG */
+/** Type of l2_mem_int_record0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_exceed_addr_int_addr : RO; bitpos: [20:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_addr:21;
+        /** reg_l2_mem_exceed_addr_int_we : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_we:1;
+        /** reg_l2_mem_exceed_addr_int_master : RO; bitpos: [24:22]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_master:3;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_l2_mem_int_record0_reg_t;
+
+
+/** Group: HP L2 MEM INT RECORD1 REG */
+/** Type of l2_mem_int_record1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_addr : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_addr:15;
+        /** reg_l2_mem_ecc_one_bit_err : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_one_bit_err:1;
+        /** reg_l2_mem_ecc_two_bit_err : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_two_bit_err:1;
+        /** reg_l2_mem_ecc_err_bit : RO; bitpos: [25:17]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_bit:9;
+        /** reg_l2_cache_err_bank : RO; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_cache_err_bank:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_l2_mem_int_record1_reg_t;
+
+
+/** Group: HP L2 MEM L2 CACHE ECC REG */
+/** Type of l2_mem_l2_cache_ecc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_cache_ecc_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_cache_ecc_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_mem_l2_cache_ecc_reg_t;
+
+
+/** Group: HP L1CACHE BUS0 ID REG */
+/** Type of l1cache_bus0_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l1_cache_bus0_id : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l1_cache_bus0_id:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_l1cache_bus0_id_reg_t;
+
+
+/** Group: HP L1CACHE BUS1 ID REG */
+/** Type of l1cache_bus1_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l1_cache_bus1_id : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l1_cache_bus1_id:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_l1cache_bus1_id_reg_t;
+
+
+/** Group: HP L2 MEM RDN ECO CS REG */
+/** Type of l2_mem_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_en:1;
+        /** reg_l2_mem_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_l2_mem_rdn_eco_cs_reg_t;
+
+
+/** Group: HP L2 MEM RDN ECO LOW REG */
+/** Type of l2_mem_rdn_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_low:32;
+    };
+    uint32_t val;
+} hp_l2_mem_rdn_eco_low_reg_t;
+
+
+/** Group: HP L2 MEM RDN ECO HIGH REG */
+/** Type of l2_mem_rdn_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_high:32;
+    };
+    uint32_t val;
+} hp_l2_mem_rdn_eco_high_reg_t;
+
+
+/** Group: HP TCM RDN ECO CS REG */
+/** Type of tcm_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_tcm_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_tcm_rdn_eco_en:1;
+        /** reg_hp_tcm_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_tcm_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_tcm_rdn_eco_cs_reg_t;
+
+
+/** Group: HP TCM RDN ECO LOW REG */
+/** Type of tcm_rdn_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_tcm_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_tcm_rdn_eco_low:32;
+    };
+    uint32_t val;
+} hp_tcm_rdn_eco_low_reg_t;
+
+
+/** Group: HP TCM RDN ECO HIGH REG */
+/** Type of tcm_rdn_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_tcm_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  NA
+         */
+        uint32_t reg_hp_tcm_rdn_eco_high:32;
+    };
+    uint32_t val;
+} hp_tcm_rdn_eco_high_reg_t;
+
+
+/** Group: HP GPIO DEAD HOLD CTRL REG */
+/** Type of gpio_ded_hold_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_ded_hold : R/W; bitpos: [25:0]; default: 0;
+         *  hold control for gpio63~56
+         */
+        uint32_t reg_gpio_ded_hold:26;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} hp_gpio_ded_hold_ctrl_reg_t;
+
+
+/** Group: HP L2 MEM SW ECC BWE MASK REG */
+/** Type of l2_mem_sw_ecc_bwe_mask register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_sw_ecc_bwe_mask_ctrl : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to mask bwe hamming code bit
+         */
+        uint32_t reg_l2_mem_sw_ecc_bwe_mask_ctrl:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_mem_sw_ecc_bwe_mask_reg_t;
+
+
+/** Group: HP USB20OTG MEM CTRL REG */
+/** Type of usb20otg_mem_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_usb20_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_usb20_mem_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_usb20otg_mem_ctrl_reg_t;
+
+
+/** Group: configure_register */
+/** Type of tcm_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_raw:1;
+    };
+    uint32_t val;
+} hp_tcm_int_raw_reg_t;
+
+/** Type of tcm_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_st:1;
+    };
+    uint32_t val;
+} hp_tcm_int_st_reg_t;
+
+/** Type of tcm_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_ena:1;
+    };
+    uint32_t val;
+} hp_tcm_int_ena_reg_t;
+
+/** Type of tcm_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_clr:1;
+    };
+    uint32_t val;
+} hp_tcm_int_clr_reg_t;
+
+/** Type of core_ahb_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_ahb_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 ahb timeout handle
+         */
+        uint32_t core_ahb_timeout_en:1;
+        /** core_ahb_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 ahb bus timeout  threshold
+         */
+        uint32_t core_ahb_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_core_ahb_timeout_reg_t;
+
+/** Type of core_ibus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_ibus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 ibus timeout handle
+         */
+        uint32_t core_ibus_timeout_en:1;
+        /** core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 ibus timeout  threshold
+         */
+        uint32_t core_ibus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_core_ibus_timeout_reg_t;
+
+/** Type of core_dbus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_dbus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 dbus timeout handle
+         */
+        uint32_t core_dbus_timeout_en:1;
+        /** core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 dbus timeout  threshold
+         */
+        uint32_t core_dbus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_core_dbus_timeout_reg_t;
+
+/** Type of icm_cpu_h2x_cfg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** cpu_icm_h2x_post_wr_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_post_wr_en:1;
+        /** cpu_icm_h2x_cut_through_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_cut_through_en:1;
+        /** cpu_icm_h2x_bridge_busy : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_bridge_busy:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_icm_cpu_h2x_cfg_reg_t;
+
+/** Type of bitscrambler_peri_sel register
+ *  Bitscrambler Peri Sel
+ */
+typedef union {
+    struct {
+        /** bitscrambler_peri_rx_sel : R/W; bitpos: [3:0]; default: 15;
+         *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0
+         *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+         *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+         *  else : none
+         */
+        uint32_t bitscrambler_peri_rx_sel:4;
+        /** bitscrambler_peri_tx_sel : R/W; bitpos: [7:4]; default: 15;
+         *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0
+         *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+         *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+         *  else : none
+         */
+        uint32_t bitscrambler_peri_tx_sel:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_bitscrambler_peri_sel_reg_t;
+
+
+/** Group: HP_TCM_PARITY_INT_RECORD_REG */
+/** Type of tcm_parity_int_record register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_parity_err_int_addr : RO; bitpos: [12:0]; default: 0;
+         *  hp tcm_parity_err_addr
+         */
+        uint32_t tcm_parity_err_int_addr:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} hp_tcm_parity_int_record_reg_t;
+
+
+/** Group: HP L1 CACHE PWR CTRL REG */
+/** Type of l1_cache_pwr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l1_cache_mem_fo : R/W; bitpos: [5:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_l1_cache_mem_fo:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_l1_cache_pwr_ctrl_reg_t;
+
+
+/** Group: HP L2 CACHE PWR CTRL REG */
+/** Type of l2_cache_pwr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_cache_mem_fo : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_l2_cache_mem_fo:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_l2_cache_pwr_ctrl_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of cpu_waiti_conf register
+ *  CPU_WAITI configuration register
+ */
+typedef union {
+    struct {
+        /** cpu_wait_mode_force_on : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to force cpu_waiti_clk enable.
+         */
+        uint32_t cpu_wait_mode_force_on:1;
+        /** cpu_waiti_delay_num : R/W; bitpos: [4:1]; default: 0;
+         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+         *  will close
+         */
+        uint32_t cpu_waiti_delay_num:4;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_cpu_waiti_conf_reg_t;
+
+/** Type of sys_core_debug_runstall_conf register
+ *  Core Debug runstall configure register
+ */
+typedef union {
+    struct {
+        /** sys_core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
+         *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+         */
+        uint32_t sys_core_debug_runstall_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_core_debug_runstall_conf_reg_t;
+
+/** Type of rsa_pd_ctrl register
+ *  rsa pd ctrl register
+ */
+typedef union {
+    struct {
+        /** rsa_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down rsa internal memory.
+         */
+        uint32_t rsa_mem_force_pd:1;
+        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up rsa internal memory
+         */
+        uint32_t rsa_mem_force_pu:1;
+        /** rsa_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down rsa internal memory.
+         */
+        uint32_t rsa_mem_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_rsa_pd_ctrl_reg_t;
+
+/** Type of ecc_pd_ctrl register
+ *  ecc pd ctrl register
+ */
+typedef union {
+    struct {
+        /** ecc_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down ecc internal memory.
+         */
+        uint32_t ecc_mem_force_pd:1;
+        /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up ecc internal memory
+         */
+        uint32_t ecc_mem_force_pu:1;
+        /** ecc_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down ecc internal memory.
+         */
+        uint32_t ecc_mem_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_ecc_pd_ctrl_reg_t;
+
+/** Type of rng_cfg register
+ *  rng cfg register
+ */
+typedef union {
+    struct {
+        /** rng_sample_enable : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rng_sample_enable:1;
+        uint32_t reserved_1:15;
+        /** rng_chain_clk_div_num : R/W; bitpos: [23:16]; default: 0;
+         *  chain clk div num to pad for debug
+         */
+        uint32_t rng_chain_clk_div_num:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_rng_cfg_reg_t;
+
+/** Type of uart_pd_ctrl register
+ *  ecc pd ctrl register
+ */
+typedef union {
+    struct {
+        /** uart_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down hp uart internal memory.
+         */
+        uint32_t uart_mem_force_pd:1;
+        /** uart_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up hp uart  internal memory
+         */
+        uint32_t uart_mem_force_pu:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_uart_pd_ctrl_reg_t;
+
+/** Type of peri_mem_clk_force_on register
+ *  hp peri mem clk force on regpster
+ */
+typedef union {
+    struct {
+        /** rmt_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force on mem clk in rmt
+         */
+        uint32_t rmt_mem_clk_force_on:1;
+        /** bitscrambler_tx_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to force on tx mem clk in bitscrambler
+         */
+        uint32_t bitscrambler_tx_mem_clk_force_on:1;
+        /** bitscrambler_rx_mem_clk_force_on : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force on rx mem clk in bitscrambler
+         */
+        uint32_t bitscrambler_rx_mem_clk_force_on:1;
+        /** gdma_mem_clk_force_on : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force on mem clk in gdma
+         */
+        uint32_t gdma_mem_clk_force_on:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_peri_mem_clk_force_on_reg_t;
+
+/** Type of cpu_wakeup_event register
+ *  cpu wakeup event ctrl register
+ */
+typedef union {
+    struct {
+        /** core0_wakeup_event : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to wake up hp core0
+         */
+        uint32_t core0_wakeup_event:1;
+        /** core1_wakeup_event : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to wake up hp core1
+         */
+        uint32_t core1_wakeup_event:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_cpu_wakeup_event_reg_t;
+
+/** Type of hp2lp_intr_group0_en register
+ *  HpP2LP Interrupt Enable Register Group0
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group0_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group0_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group0_en_reg_t;
+
+/** Type of hp2lp_intr_group1_en register
+ *  HpP2LP Interrupt Enable Register Group1
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group1_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group1_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group1_en_reg_t;
+
+/** Type of hp2lp_intr_group2_en register
+ *  HpP2LP Interrupt Enable Register Group2
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group2_en : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group2_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group2_en_reg_t;
+
+/** Type of hp2lp_intr_group3_en register
+ *  HpP2LP Interrupt Enable Register Group3
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group3_en : R/W; bitpos: [13:0]; default: 16383;
+         *  Set each bit to enable corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group3_en:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group3_en_reg_t;
+
+/** Type of hp2lp_wakeup_group0_en register
+ *  HpP2LP Wakeup Enable Register Group0
+ */
+typedef union {
+    struct {
+        /** h2lp_wakeup_group0_en : R/W; bitpos: [31:0]; default: 0;
+         *  Set each bit to enable corresponding peripheral wakeup to PMU.
+         */
+        uint32_t h2lp_wakeup_group0_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_wakeup_group0_en_reg_t;
+
+/** Type of hp2lp_wakeup_group1_en register
+ *  HpP2LP Wakeup Enable Register Group1
+ */
+typedef union {
+    struct {
+        /** h2lp_wakeup_group1_en : R/W; bitpos: [31:0]; default: 0;
+         *  Set each bit to enable corresponding peripheral wakeup to PMU.
+         */
+        uint32_t h2lp_wakeup_group1_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_wakeup_group1_en_reg_t;
+
+/** Type of hp2lp_wakeup_group2_en register
+ *  HpP2LP Wakeup Enable Register Group2
+ */
+typedef union {
+    struct {
+        /** h2lp_wakeup_group2_en : R/W; bitpos: [31:0]; default: 0;
+         *  Set each bit to enable corresponding peripheral wakeup to PMU.
+         */
+        uint32_t h2lp_wakeup_group2_en:32;
+    };
+    uint32_t val;
+} hp_hp2lp_wakeup_group2_en_reg_t;
+
+/** Type of hp2lp_wakeup_group3_en register
+ *  HpP2LP Wakeup Enable Register Group3
+ */
+typedef union {
+    struct {
+        /** h2lp_wakeup_group3_en : R/W; bitpos: [13:0]; default: 0;
+         *  Set each bit to enable corresponding peripheral wakeup to PMU.
+         */
+        uint32_t h2lp_wakeup_group3_en:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_hp2lp_wakeup_group3_en_reg_t;
+
+
+/** Group: HP PERI1 APB POSTW EN REG */
+/** Type of peri1_apb_postw_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** peri1_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  hp_peri1 apb register interface post write enable, 1 will speed up write, but will
+         *  take some time to update value to register
+         */
+        uint32_t peri1_apb_postw_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_peri1_apb_postw_en_reg_t;
+
+
+/** Group: APB Sync Register */
+/** Type of sys_apb_sync_postw_en register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_gmac_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_apb_postw_en:1;
+        /** sys_dsi_host_apb_postw_en : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_dsi_host_apb_postw_en:1;
+        /** sys_csi_host_apb_sync_postw_en : R/W; bitpos: [2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_csi_host_apb_sync_postw_en:1;
+        /** sys_csi_host_apb_async_postw_en : R/W; bitpos: [3]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_csi_host_apb_async_postw_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_apb_sync_postw_en_reg_t;
+
+
+/** Group: GDMA Ctonrol Register */
+/** Type of sys_gdma_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_debug_ch_num : R/W; bitpos: [1:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_debug_ch_num:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_gdma_ctrl_reg_t;
+
+
+/** Group: GMAC Control Register */
+/** Type of sys_gmac_ctrl0 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_pps : RO; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_pps:1;
+        /** sys_sbd_flowctrl : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_sbd_flowctrl:1;
+        /** sys_phy_intf_sel : R/W; bitpos: [4:2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_intf_sel:3;
+        /** sys_gmac_mem_clk_force_on : R/W; bitpos: [5]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_mem_clk_force_on:1;
+        /** sys_gmac_rst_clk_tx_n : RO; bitpos: [6]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_rst_clk_tx_n:1;
+        /** sys_gmac_rst_clk_rx_n : RO; bitpos: [7]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_rst_clk_rx_n:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_sys_gmac_ctrl0_reg_t;
+
+/** Type of sys_gmac_ctrl1 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_timestamp_l : RO; bitpos: [31:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_timestamp_l:32;
+    };
+    uint32_t val;
+} hp_sys_gmac_ctrl1_reg_t;
+
+/** Type of sys_gmac_ctrl2 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_timestamp_h : RO; bitpos: [31:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_timestamp_h:32;
+    };
+    uint32_t val;
+} hp_sys_gmac_ctrl2_reg_t;
+
+
+/** Group: VPU Control Register */
+/** Type of sys_vpu_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ppa_lslp_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ppa_lslp_mem_pd:1;
+        /** sys_jpeg_sdslp_mem_pd : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_sdslp_mem_pd:1;
+        /** sys_jpeg_lslp_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_lslp_mem_pd:1;
+        /** sys_jpeg_dslp_mem_pd : R/W; bitpos: [3]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_dslp_mem_pd:1;
+        /** sys_dma2d_lslp_mem_pd : R/W; bitpos: [4]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_dma2d_lslp_mem_pd:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_sys_vpu_ctrl_reg_t;
+
+
+/** Group: USB OTG20 Control Register */
+/** Type of sys_usbotg20_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_otg_phy_test_done : RO; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_test_done:1;
+        /** sys_usb_mem_aux_ctrl : R/W; bitpos: [14:1]; default: 4896;
+         *  N/A
+         */
+        uint32_t sys_usb_mem_aux_ctrl:14;
+        /** sys_phy_suspendm : R/W; bitpos: [15]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_suspendm:1;
+        /** sys_phy_suspend_force_en : R/W; bitpos: [16]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_suspend_force_en:1;
+        /** sys_phy_rstn : R/W; bitpos: [17]; default: 1;
+         *  N/A
+         */
+        uint32_t sys_phy_rstn:1;
+        /** sys_phy_reset_force_en : R/W; bitpos: [18]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_reset_force_en:1;
+        /** sys_phy_pll_force_en : R/W; bitpos: [19]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_pll_force_en:1;
+        /** sys_phy_pll_en : R/W; bitpos: [20]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_pll_en:1;
+        /** sys_otg_suspendm : R/W; bitpos: [21]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_suspendm:1;
+        /** sys_otg_phy_txbitstuff_en : R/W; bitpos: [22]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_txbitstuff_en:1;
+        /** sys_otg_phy_refclk_mode : R/W; bitpos: [23]; default: 1;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_refclk_mode:1;
+        /** sys_otg_phy_bisten : R/W; bitpos: [24]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_bisten:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_usbotg20_ctrl_reg_t;
+
+
+/** Group: HP_TCM_ERR_RESP_CTRL_REG */
+/** Type of tcm_err_resp_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on tcm error response
+         */
+        uint32_t tcm_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_tcm_err_resp_ctrl_reg_t;
+
+
+/** Group: HP L2 MEM REFRESH REG */
+/** Type of l2_mem_refresh register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_unit0_refersh_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit0_refersh_en:1;
+        /** reg_l2_mem_unit1_refersh_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit1_refersh_en:1;
+        /** reg_l2_mem_unit2_refersh_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit2_refersh_en:1;
+        /** reg_l2_mem_unit3_refersh_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit3_refersh_en:1;
+        /** reg_l2_mem_unit4_refersh_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit4_refersh_en:1;
+        /** reg_l2_mem_unit5_refersh_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit5_refersh_en:1;
+        /** reg_l2_mem_refersh_cnt_reset : R/W; bitpos: [6]; default: 1;
+         *  Set 1 to reset l2mem_refresh_cnt
+         */
+        uint32_t reg_l2_mem_refersh_cnt_reset:1;
+        /** reg_l2_mem_unit0_refresh_done : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit0_refresh_done:1;
+        /** reg_l2_mem_unit1_refresh_done : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit1_refresh_done:1;
+        /** reg_l2_mem_unit2_refresh_done : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit2_refresh_done:1;
+        /** reg_l2_mem_unit3_refresh_done : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit3_refresh_done:1;
+        /** reg_l2_mem_unit4_refresh_done : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit4_refresh_done:1;
+        /** reg_l2_mem_unit5_refresh_done : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit5_refresh_done:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} hp_l2_mem_refresh_reg_t;
+
+
+/** Group: HP TCM INIT REG */
+/** Type of tcm_init register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tcm_init_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_tcm_init_en:1;
+        /** reg_tcm_init_cnt_reset : R/W; bitpos: [1]; default: 1;
+         *  Set 1 to reset tcm init cnt
+         */
+        uint32_t reg_tcm_init_cnt_reset:1;
+        /** reg_tcm_init_done : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_tcm_init_done:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_tcm_init_reg_t;
+
+
+/** Group: HP_TCM_PARITY_CHECK_CTRL_REG */
+/** Type of tcm_parity_check_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_parity_check_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on tcm parity check
+         */
+        uint32_t tcm_parity_check_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_tcm_parity_check_ctrl_reg_t;
+
+
+/** Group: HP_DESIGN_FOR_VERIFICATION0 */
+/** Type of design_for_verification0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dfv0 : R/W; bitpos: [31:0]; default: 0;
+         *  register for DV
+         */
+        uint32_t dfv0:32;
+    };
+    uint32_t val;
+} hp_design_for_verification0_reg_t;
+
+
+/** Group: HP_DESIGN_FOR_VERIFICATION1 */
+/** Type of design_for_verification1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dfv1 : R/W; bitpos: [31:0]; default: 0;
+         *  register for DV
+         */
+        uint32_t dfv1:32;
+    };
+    uint32_t val;
+} hp_design_for_verification1_reg_t;
+
+
+/** Group: HP_PSRAM_FLASH_ADDR_INTERCHANGE */
+/** Type of psram_flash_addr_interchange register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** psram_flash_addr_interchange_cpu : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu
+         *  access through cache
+         */
+        uint32_t psram_flash_addr_interchange_cpu:1;
+        /** psram_flash_addr_interchange_dma : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable addr interchange between psram and flash in axi matrix when dma
+         *  device access, lp core access and hp core access through ahb
+         */
+        uint32_t psram_flash_addr_interchange_dma:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_psram_flash_addr_interchange_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of ahb2axi_bresp_err_int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_icm_h2x_bresp_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+         *  post write mode in ahb2axi.
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_ahb2axi_bresp_err_int_raw_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** cpu_icm_h2x_bresp_err_int_st : RO; bitpos: [31]; default: 0;
+         *  the masked interrupt status of  cpu_icm_h2x_bresp_err
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_st:1;
+    };
+    uint32_t val;
+} hp_ahb2axi_bresp_err_int_st_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** cpu_icm_h2x_bresp_err_int_ena : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to enable cpu_icm_h2x_bresp_err int
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_ena:1;
+    };
+    uint32_t val;
+} hp_ahb2axi_bresp_err_int_ena_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** cpu_icm_h2x_bresp_err_int_clr : WT; bitpos: [31]; default: 0;
+         *  Write 1 to clear cpu_icm_h2x_bresp_err  int
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_clr:1;
+    };
+    uint32_t val;
+} hp_ahb2axi_bresp_err_int_clr_reg_t;
+
+/** Type of core_timeout_int_raw register
+ *  Hp core bus timeout interrupt raw register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of hp core0  ahb timeout
+         */
+        uint32_t core0_ahb_timeout_int_raw:1;
+        /** core1_ahb_timeout_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  the raw interrupt status of hp core1  ahb timeout
+         */
+        uint32_t core1_ahb_timeout_int_raw:1;
+        /** core0_ibus_timeout_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  the raw interrupt status of hp core0  ibus timeout
+         */
+        uint32_t core0_ibus_timeout_int_raw:1;
+        /** core1_ibus_timeout_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  the raw interrupt status of hp core1  ibus timeout
+         */
+        uint32_t core1_ibus_timeout_int_raw:1;
+        /** core0_dbus_timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  the raw interrupt status of hp core0  dbus timeout
+         */
+        uint32_t core0_dbus_timeout_int_raw:1;
+        /** core1_dbus_timeout_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  the raw interrupt status of hp core1  dbus timeout
+         */
+        uint32_t core1_dbus_timeout_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_core_timeout_int_raw_reg_t;
+
+/** Type of core_timeout_int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of hp core0  ahb timeout
+         */
+        uint32_t core0_ahb_timeout_int_st:1;
+        /** core1_ahb_timeout_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of hp core1  ahb timeout
+         */
+        uint32_t core1_ahb_timeout_int_st:1;
+        /** core0_ibus_timeout_int_st : RO; bitpos: [2]; default: 0;
+         *  the masked interrupt status of hp core0  ibus timeout
+         */
+        uint32_t core0_ibus_timeout_int_st:1;
+        /** core1_ibus_timeout_int_st : RO; bitpos: [3]; default: 0;
+         *  the masked interrupt status of hp core1  ibus timeout
+         */
+        uint32_t core1_ibus_timeout_int_st:1;
+        /** core0_dbus_timeout_int_st : RO; bitpos: [4]; default: 0;
+         *  the masked interrupt status of hp core0  dbus timeout
+         */
+        uint32_t core0_dbus_timeout_int_st:1;
+        /** core1_dbus_timeout_int_st : RO; bitpos: [5]; default: 0;
+         *  the masked interrupt status of hp core1  dbus timeout
+         */
+        uint32_t core1_dbus_timeout_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_core_timeout_int_st_reg_t;
+
+/** Type of core_timeout_int_ena register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable hp_core0_ahb_timeout int
+         */
+        uint32_t core0_ahb_timeout_int_ena:1;
+        /** core1_ahb_timeout_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable hp_core1_ahb_timeout int
+         */
+        uint32_t core1_ahb_timeout_int_ena:1;
+        /** core0_ibus_timeout_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable hp_core0_ibus_timeout int
+         */
+        uint32_t core0_ibus_timeout_int_ena:1;
+        /** core1_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable hp_core1_ibus_timeout int
+         */
+        uint32_t core1_ibus_timeout_int_ena:1;
+        /** core0_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable hp_core0_dbus_timeout int
+         */
+        uint32_t core0_dbus_timeout_int_ena:1;
+        /** core1_dbus_timeout_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable hp_core1_dbus_timeout int
+         */
+        uint32_t core1_dbus_timeout_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_core_timeout_int_ena_reg_t;
+
+/** Type of core_timeout_int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear hp_core0_ahb_timeout int
+         */
+        uint32_t core0_ahb_timeout_int_clr:1;
+        /** core1_ahb_timeout_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear hp_core1_ahb_timeout int
+         */
+        uint32_t core1_ahb_timeout_int_clr:1;
+        /** core0_ibus_timeout_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear hp_core0_ibus_timeout int
+         */
+        uint32_t core0_ibus_timeout_int_clr:1;
+        /** core1_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear hp_core1_ibus_timeout int
+         */
+        uint32_t core1_ibus_timeout_int_clr:1;
+        /** core0_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear hp_core0_dbus_timeout int
+         */
+        uint32_t core0_dbus_timeout_int_clr:1;
+        /** core1_dbus_timeout_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear hp_core1_dbus_timeout int
+         */
+        uint32_t core1_dbus_timeout_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_core_timeout_int_clr_reg_t;
+
+
+/** Group: HP_L2_MEM_ERR_RESP_CTRL_REG */
+/** Type of l2_mem_err_resp_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** l2_mem_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on l2mem error response
+         */
+        uint32_t l2_mem_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_l2_mem_err_resp_ctrl_reg_t;
+
+
+/** Group: HP_L2_MEM_AHB_BUFFER_CTRL_REG */
+/** Type of l2_mem_ahb_buffer_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** l2_mem_ahb_wrbuffer_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on l2mem ahb wr buffer
+         */
+        uint32_t l2_mem_ahb_wrbuffer_en:1;
+        /** l2_mem_ahb_rdbuffer_en : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to turn on l2mem ahb rd buffer
+         */
+        uint32_t l2_mem_ahb_rdbuffer_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_l2_mem_ahb_buffer_ctrl_reg_t;
+
+
+/** Group: HP_CORE_DMACTIVE_LPCORE_REG */
+/** Type of core_dmactive_lpcore register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_dmactive_lpcore : RO; bitpos: [0]; default: 0;
+         *  hp core dmactive_lpcore value
+         */
+        uint32_t core_dmactive_lpcore:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_core_dmactive_lpcore_reg_t;
+
+
+/** Group: control registers */
+/** Type of core_err_resp_dis register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_err_resp_dis : R/W; bitpos: [2:0]; default: 0;
+         *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
+         *  disable ahb err resp.
+         */
+        uint32_t core_err_resp_dis:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_core_err_resp_dis_reg_t;
+
+
+/** Group: HP GPIO O HYS CTRL0 REG */
+/** Type of gpio_o_hys_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hys_low : R/W; bitpos: [31:0]; default: 0;
+         *  hys control for gpio47~16
+         */
+        uint32_t reg_gpio_0_hys_low:32;
+    };
+    uint32_t val;
+} hp_gpio_o_hys_ctrl0_reg_t;
+
+
+/** Group: HP GPIO O HYS CTRL1 REG */
+/** Type of gpio_o_hys_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hys_high : R/W; bitpos: [8:0]; default: 0;
+         *  hys control for gpio56~48
+         */
+        uint32_t reg_gpio_0_hys_high:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_gpio_o_hys_ctrl1_reg_t;
+
+
+/** Group: HP USB20OTG PHY ST REG */
+/** Type of usb_otghs_phy_st register
+ *  Usb otg2.0 PHY status register
+ */
+typedef union {
+    struct {
+        /** usb_soft_reset_actv_pdomain : RO; bitpos: [0]; default: 0;
+         *  Todo
+         */
+        uint32_t usb_soft_reset_actv_pdomain:1;
+        /** utmisrp_sessend : RO; bitpos: [1]; default: 0;
+         *  Todo
+         */
+        uint32_t utmisrp_sessend:1;
+        /** utmiotg_vbusvalid : RO; bitpos: [2]; default: 0;
+         *  Todo
+         */
+        uint32_t utmiotg_vbusvalid:1;
+        /** utmisrp_bvalid : RO; bitpos: [3]; default: 0;
+         *  Todo
+         */
+        uint32_t utmisrp_bvalid:1;
+        /** utmisrp_sessvalid : RO; bitpos: [4]; default: 0;
+         *  Todo
+         */
+        uint32_t utmisrp_sessvalid:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_usb_otghs_phy_st_reg_t;
+
+
+/** Group: Status Register */
+/** Type of hp2lp_intr_group0_st register
+ *  HpP2LP Interrupt Status Register Group0
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group0_st : RO; bitpos: [31:0]; default: 0;
+         *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group0_st:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group0_st_reg_t;
+
+/** Type of hp2lp_intr_group1_st register
+ *  HpP2LP Interrupt Enable Register Group1
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group1_st : RO; bitpos: [31:0]; default: 0;
+         *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group1_st:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group1_st_reg_t;
+
+/** Type of hp2lp_intr_group2_st register
+ *  HpP2LP Interrupt Enable Register Group2
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group2_st : RO; bitpos: [31:0]; default: 0;
+         *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group2_st:32;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group2_st_reg_t;
+
+/** Type of hp2lp_intr_group3_st register
+ *  HpP2LP Interrupt Enable Register Group3
+ */
+typedef union {
+    struct {
+        /** h2lp_intr_group3_st : RO; bitpos: [13:0]; default: 0;
+         *  Each bit indicates the status of corresponding peripheral interrupt to LP CPU.
+         */
+        uint32_t h2lp_intr_group3_st:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_hp2lp_intr_group3_st_reg_t;
+
+
+typedef struct {
+    volatile hp_sys_ver_date_reg_t sys_ver_date;
+    volatile hp_clk_en_reg_t clk_en;
+    uint32_t reserved_008[2];
+    volatile hp_cpu_int_from_cpu_0_reg_t cpu_int_from_cpu_0;
+    volatile hp_cpu_int_from_cpu_1_reg_t cpu_int_from_cpu_1;
+    volatile hp_cpu_int_from_cpu_2_reg_t cpu_int_from_cpu_2;
+    volatile hp_cpu_int_from_cpu_3_reg_t cpu_int_from_cpu_3;
+    volatile hp_cache_clk_config_reg_t cache_clk_config;
+    volatile hp_cache_reset_config_reg_t cache_reset_config;
+    uint32_t reserved_028;
+    volatile hp_sys_dma_addr_ctrl_reg_t sys_dma_addr_ctrl;
+    uint32_t reserved_030;
+    volatile hp_tcm_ram_wrr_config_reg_t tcm_ram_wrr_config;
+    volatile hp_tcm_sw_parity_bwe_mask_reg_t tcm_sw_parity_bwe_mask;
+    volatile hp_tcm_ram_pwr_ctrl0_reg_t tcm_ram_pwr_ctrl0;
+    volatile hp_l2_rom_pwr_ctrl0_reg_t l2_rom_pwr_ctrl0;
+    uint32_t reserved_044[3];
+    volatile hp_probea_ctrl_reg_t probea_ctrl;
+    volatile hp_probeb_ctrl_reg_t probeb_ctrl;
+    uint32_t reserved_058;
+    volatile hp_probe_out_reg_t probe_out;
+    volatile hp_l2_mem_ram_pwr_ctrl0_reg_t l2_mem_ram_pwr_ctrl0;
+    volatile hp_cpu_corestalled_st_reg_t cpu_corestalled_st;
+    uint32_t reserved_068[2];
+    volatile hp_crypto_ctrl_reg_t crypto_ctrl;
+    volatile hp_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0;
+    volatile hp_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1;
+    volatile hp_sys_rdn_eco_cs_reg_t sys_rdn_eco_cs;
+    volatile hp_cache_apb_postw_en_reg_t cache_apb_postw_en;
+    volatile hp_l2_mem_subsize_reg_t l2_mem_subsize;
+    uint32_t reserved_088[5];
+    volatile hp_l2_mem_int_raw_reg_t l2_mem_int_raw;
+    volatile hp_l2_mem_int_st_reg_t l2_mem_int_st;
+    volatile hp_l2_mem_int_ena_reg_t l2_mem_int_ena;
+    volatile hp_l2_mem_int_clr_reg_t l2_mem_int_clr;
+    volatile hp_l2_mem_l2_ram_ecc_reg_t l2_mem_l2_ram_ecc;
+    volatile hp_l2_mem_int_record0_reg_t l2_mem_int_record0;
+    volatile hp_l2_mem_int_record1_reg_t l2_mem_int_record1;
+    uint32_t reserved_0b8[3];
+    volatile hp_l2_mem_l2_cache_ecc_reg_t l2_mem_l2_cache_ecc;
+    volatile hp_l1cache_bus0_id_reg_t l1cache_bus0_id;
+    volatile hp_l1cache_bus1_id_reg_t l1cache_bus1_id;
+    uint32_t reserved_0d0[2];
+    volatile hp_l2_mem_rdn_eco_cs_reg_t l2_mem_rdn_eco_cs;
+    volatile hp_l2_mem_rdn_eco_low_reg_t l2_mem_rdn_eco_low;
+    volatile hp_l2_mem_rdn_eco_high_reg_t l2_mem_rdn_eco_high;
+    volatile hp_tcm_rdn_eco_cs_reg_t tcm_rdn_eco_cs;
+    volatile hp_tcm_rdn_eco_low_reg_t tcm_rdn_eco_low;
+    volatile hp_tcm_rdn_eco_high_reg_t tcm_rdn_eco_high;
+    volatile hp_gpio_ded_hold_ctrl_reg_t gpio_ded_hold_ctrl;
+    volatile hp_l2_mem_sw_ecc_bwe_mask_reg_t l2_mem_sw_ecc_bwe_mask;
+    volatile hp_usb20otg_mem_ctrl_reg_t usb20otg_mem_ctrl;
+    volatile hp_tcm_int_raw_reg_t tcm_int_raw;
+    volatile hp_tcm_int_st_reg_t tcm_int_st;
+    volatile hp_tcm_int_ena_reg_t tcm_int_ena;
+    volatile hp_tcm_int_clr_reg_t tcm_int_clr;
+    volatile hp_tcm_parity_int_record_reg_t tcm_parity_int_record;
+    volatile hp_l1_cache_pwr_ctrl_reg_t l1_cache_pwr_ctrl;
+    volatile hp_l2_cache_pwr_ctrl_reg_t l2_cache_pwr_ctrl;
+    volatile hp_cpu_waiti_conf_reg_t cpu_waiti_conf;
+    volatile hp_sys_core_debug_runstall_conf_reg_t sys_core_debug_runstall_conf;
+    volatile hp_core_ahb_timeout_reg_t core_ahb_timeout;
+    volatile hp_core_ibus_timeout_reg_t core_ibus_timeout;
+    volatile hp_core_dbus_timeout_reg_t core_dbus_timeout;
+    uint32_t reserved_12c[3];
+    volatile hp_icm_cpu_h2x_cfg_reg_t icm_cpu_h2x_cfg;
+    volatile hp_peri1_apb_postw_en_reg_t peri1_apb_postw_en;
+    volatile hp_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel;
+    volatile hp_sys_apb_sync_postw_en_reg_t sys_apb_sync_postw_en;
+    volatile hp_sys_gdma_ctrl_reg_t sys_gdma_ctrl;
+    volatile hp_sys_gmac_ctrl0_reg_t sys_gmac_ctrl0;
+    volatile hp_sys_gmac_ctrl1_reg_t sys_gmac_ctrl1;
+    volatile hp_sys_gmac_ctrl2_reg_t sys_gmac_ctrl2;
+    volatile hp_sys_vpu_ctrl_reg_t sys_vpu_ctrl;
+    volatile hp_sys_usbotg20_ctrl_reg_t sys_usbotg20_ctrl;
+    volatile hp_tcm_err_resp_ctrl_reg_t tcm_err_resp_ctrl;
+    volatile hp_l2_mem_refresh_reg_t l2_mem_refresh;
+    volatile hp_tcm_init_reg_t tcm_init;
+    volatile hp_tcm_parity_check_ctrl_reg_t tcm_parity_check_ctrl;
+    volatile hp_design_for_verification0_reg_t design_for_verification0;
+    volatile hp_design_for_verification1_reg_t design_for_verification1;
+    uint32_t reserved_178[2];
+    volatile hp_psram_flash_addr_interchange_reg_t psram_flash_addr_interchange;
+    uint32_t reserved_184;
+    volatile hp_ahb2axi_bresp_err_int_raw_reg_t ahb2axi_bresp_err_int_raw;
+    volatile hp_ahb2axi_bresp_err_int_st_reg_t ahb2axi_bresp_err_int_st;
+    volatile hp_ahb2axi_bresp_err_int_ena_reg_t ahb2axi_bresp_err_int_ena;
+    volatile hp_ahb2axi_bresp_err_int_clr_reg_t ahb2axi_bresp_err_int_clr;
+    volatile hp_l2_mem_err_resp_ctrl_reg_t l2_mem_err_resp_ctrl;
+    volatile hp_l2_mem_ahb_buffer_ctrl_reg_t l2_mem_ahb_buffer_ctrl;
+    volatile hp_core_dmactive_lpcore_reg_t core_dmactive_lpcore;
+    volatile hp_core_err_resp_dis_reg_t core_err_resp_dis;
+    volatile hp_core_timeout_int_raw_reg_t core_timeout_int_raw;
+    volatile hp_core_timeout_int_st_reg_t core_timeout_int_st;
+    volatile hp_core_timeout_int_ena_reg_t core_timeout_int_ena;
+    volatile hp_core_timeout_int_clr_reg_t core_timeout_int_clr;
+    uint32_t reserved_1b8[2];
+    volatile hp_gpio_o_hys_ctrl0_reg_t gpio_o_hys_ctrl0;
+    volatile hp_gpio_o_hys_ctrl1_reg_t gpio_o_hys_ctrl1;
+    uint32_t reserved_1c8[2];
+    volatile hp_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
+    volatile hp_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
+    volatile hp_rng_cfg_reg_t rng_cfg;
+    volatile hp_uart_pd_ctrl_reg_t uart_pd_ctrl;
+    volatile hp_peri_mem_clk_force_on_reg_t peri_mem_clk_force_on;
+    uint32_t reserved_1e4;
+    volatile hp_usb_otghs_phy_st_reg_t usb_otghs_phy_st;
+    volatile hp_cpu_wakeup_event_reg_t cpu_wakeup_event;
+    volatile hp_hp2lp_intr_group0_en_reg_t hp2lp_intr_group0_en;
+    volatile hp_hp2lp_intr_group1_en_reg_t hp2lp_intr_group1_en;
+    volatile hp_hp2lp_intr_group2_en_reg_t hp2lp_intr_group2_en;
+    volatile hp_hp2lp_intr_group3_en_reg_t hp2lp_intr_group3_en;
+    volatile hp_hp2lp_intr_group0_st_reg_t hp2lp_intr_group0_st;
+    volatile hp_hp2lp_intr_group1_st_reg_t hp2lp_intr_group1_st;
+    volatile hp_hp2lp_intr_group2_st_reg_t hp2lp_intr_group2_st;
+    volatile hp_hp2lp_intr_group3_st_reg_t hp2lp_intr_group3_st;
+    volatile hp_hp2lp_wakeup_group0_en_reg_t hp2lp_wakeup_group0_en;
+    volatile hp_hp2lp_wakeup_group1_en_reg_t hp2lp_wakeup_group1_en;
+    volatile hp_hp2lp_wakeup_group2_en_reg_t hp2lp_wakeup_group2_en;
+    volatile hp_hp2lp_wakeup_group3_en_reg_t hp2lp_wakeup_group3_en;
+} hp_dev_t;
+
+extern hp_dev_t HP_SYSTEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_dev_t) == 0x220, "Invalid size of hp_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/huk_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/huk_reg.h
new file mode 100644
index 0000000000..20c44c4d3d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/huk_reg.h
@@ -0,0 +1,230 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HUK_CLK_REG register
+ *  HUK Generator clock gate control register
+ */
+#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
+/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Write 1 to force on register clock gate.
+ */
+#define HUK_CLK_EN    (BIT(0))
+#define HUK_CLK_EN_M  (HUK_CLK_EN_V << HUK_CLK_EN_S)
+#define HUK_CLK_EN_V  0x00000001U
+#define HUK_CLK_EN_S  0
+/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to force on memory clock gate.
+ */
+#define HUK_MEM_CG_FORCE_ON    (BIT(1))
+#define HUK_MEM_CG_FORCE_ON_M  (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
+#define HUK_MEM_CG_FORCE_ON_V  0x00000001U
+#define HUK_MEM_CG_FORCE_ON_S  1
+
+/** HUK_INT_RAW_REG register
+ *  HUK Generator interrupt raw register, valid in level.
+ */
+#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
+/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_RAW    (BIT(0))
+#define HUK_PREP_DONE_INT_RAW_M  (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
+#define HUK_PREP_DONE_INT_RAW_V  0x00000001U
+#define HUK_PREP_DONE_INT_RAW_S  0
+/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_RAW    (BIT(1))
+#define HUK_PROC_DONE_INT_RAW_M  (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
+#define HUK_PROC_DONE_INT_RAW_V  0x00000001U
+#define HUK_PROC_DONE_INT_RAW_S  1
+/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_RAW    (BIT(2))
+#define HUK_POST_DONE_INT_RAW_M  (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
+#define HUK_POST_DONE_INT_RAW_V  0x00000001U
+#define HUK_POST_DONE_INT_RAW_S  2
+
+/** HUK_INT_ST_REG register
+ *  HUK Generator interrupt status register.
+ */
+#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
+/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_ST    (BIT(0))
+#define HUK_PREP_DONE_INT_ST_M  (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
+#define HUK_PREP_DONE_INT_ST_V  0x00000001U
+#define HUK_PREP_DONE_INT_ST_S  0
+/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_ST    (BIT(1))
+#define HUK_PROC_DONE_INT_ST_M  (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
+#define HUK_PROC_DONE_INT_ST_V  0x00000001U
+#define HUK_PROC_DONE_INT_ST_S  1
+/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_ST    (BIT(2))
+#define HUK_POST_DONE_INT_ST_M  (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
+#define HUK_POST_DONE_INT_ST_V  0x00000001U
+#define HUK_POST_DONE_INT_ST_S  2
+
+/** HUK_INT_ENA_REG register
+ *  HUK Generator interrupt enable register.
+ */
+#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
+/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_ENA    (BIT(0))
+#define HUK_PREP_DONE_INT_ENA_M  (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
+#define HUK_PREP_DONE_INT_ENA_V  0x00000001U
+#define HUK_PREP_DONE_INT_ENA_S  0
+/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_ENA    (BIT(1))
+#define HUK_PROC_DONE_INT_ENA_M  (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
+#define HUK_PROC_DONE_INT_ENA_V  0x00000001U
+#define HUK_PROC_DONE_INT_ENA_S  1
+/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_ENA    (BIT(2))
+#define HUK_POST_DONE_INT_ENA_M  (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
+#define HUK_POST_DONE_INT_ENA_V  0x00000001U
+#define HUK_POST_DONE_INT_ENA_S  2
+
+/** HUK_INT_CLR_REG register
+ *  HUK Generator interrupt clear register.
+ */
+#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
+/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_CLR    (BIT(0))
+#define HUK_PREP_DONE_INT_CLR_M  (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
+#define HUK_PREP_DONE_INT_CLR_V  0x00000001U
+#define HUK_PREP_DONE_INT_CLR_S  0
+/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_CLR    (BIT(1))
+#define HUK_PROC_DONE_INT_CLR_M  (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
+#define HUK_PROC_DONE_INT_CLR_V  0x00000001U
+#define HUK_PROC_DONE_INT_CLR_S  1
+/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_CLR    (BIT(2))
+#define HUK_POST_DONE_INT_CLR_M  (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
+#define HUK_POST_DONE_INT_CLR_V  0x00000001U
+#define HUK_POST_DONE_INT_CLR_S  2
+
+/** HUK_CONF_REG register
+ *  HUK Generator configuration register
+ */
+#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
+/** HUK_MODE : R/W; bitpos: [0]; default: 0;
+ *  Set this field to choose the huk process. 1: process huk generate mode. 0: process
+ *  huk recovery mode.
+ */
+#define HUK_MODE    (BIT(0))
+#define HUK_MODE_M  (HUK_MODE_V << HUK_MODE_S)
+#define HUK_MODE_V  0x00000001U
+#define HUK_MODE_S  0
+
+/** HUK_START_REG register
+ *  HUK Generator control register
+ */
+#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
+/** HUK_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to continue HUK Generator operation at LOAD/GAIN state.
+ */
+#define HUK_START    (BIT(0))
+#define HUK_START_M  (HUK_START_V << HUK_START_S)
+#define HUK_START_V  0x00000001U
+#define HUK_START_S  0
+/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to start HUK Generator at IDLE state.
+ */
+#define HUK_CONTINUE    (BIT(1))
+#define HUK_CONTINUE_M  (HUK_CONTINUE_V << HUK_CONTINUE_S)
+#define HUK_CONTINUE_V  0x00000001U
+#define HUK_CONTINUE_S  1
+
+/** HUK_STATE_REG register
+ *  HUK Generator state register
+ */
+#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
+/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
+ *  The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+ */
+#define HUK_STATE    0x00000003U
+#define HUK_STATE_M  (HUK_STATE_V << HUK_STATE_S)
+#define HUK_STATE_V  0x00000003U
+#define HUK_STATE_S  0
+
+/** HUK_STATUS_REG register
+ *  HUK Generator HUK status register
+ */
+#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
+/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
+ *  2: HUK is generated but invalid. 3: reserved.
+ */
+#define HUK_STATUS    0x00000003U
+#define HUK_STATUS_M  (HUK_STATUS_V << HUK_STATUS_S)
+#define HUK_STATUS_V  0x00000003U
+#define HUK_STATUS_S  0
+/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
+ *  The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
+ *  are in the PUF SRAM. 7: Error Level, HUK is invalid.
+ */
+#define HUK_RISK_LEVEL    0x00000007U
+#define HUK_RISK_LEVEL_M  (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
+#define HUK_RISK_LEVEL_V  0x00000007U
+#define HUK_RISK_LEVEL_S  2
+/** HUK_UPDATE_REQ : RO; bitpos: [5]; default: 0;
+ *  The update request of HUK info. 0: User can update HUK info according to the risk
+ *  level. 1: The HUK info is expired, and user need to update it.
+ */
+#define HUK_UPDATE_REQ    (BIT(5))
+#define HUK_UPDATE_REQ_M  (HUK_UPDATE_REQ_V << HUK_UPDATE_REQ_S)
+#define HUK_UPDATE_REQ_V  0x00000001U
+#define HUK_UPDATE_REQ_S  5
+
+/** HUK_DATE_REG register
+ *  Version control register
+ */
+#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
+/** HUK_DATE : R/W; bitpos: [27:0]; default: 37765232;
+ *  HUK Generator version control register.
+ */
+#define HUK_DATE    0x0FFFFFFFU
+#define HUK_DATE_M  (HUK_DATE_V << HUK_DATE_S)
+#define HUK_DATE_V  0x0FFFFFFFU
+#define HUK_DATE_S  0
+
+/** HUK_INFO_MEM register
+ *  The memory that stores HUK info.
+ */
+#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
+#define HUK_INFO_MEM_SIZE_BYTES 384
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/huk_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/huk_struct.h
new file mode 100644
index 0000000000..ed5f416920
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/huk_struct.h
@@ -0,0 +1,247 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Clock gate register */
+/** Type of clk register
+ *  HUK Generator clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_en:1;
+        /** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to force on memory clock gate.
+         */
+        uint32_t mem_cg_force_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} huk_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  HUK Generator interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_raw:1;
+        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_raw:1;
+        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_raw_reg_t;
+
+/** Type of int_st register
+ *  HUK Generator interrupt status register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_st:1;
+        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_st:1;
+        /** post_done_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_st_reg_t;
+
+/** Type of int_ena register
+ *  HUK Generator interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_ena:1;
+        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_ena:1;
+        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  HUK Generator interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_clr:1;
+        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_clr:1;
+        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_clr_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  HUK Generator configuration register
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [0]; default: 0;
+         *  Set this field to choose the huk process. 1: process huk generate mode. 0: process
+         *  huk recovery mode.
+         */
+        uint32_t mode:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} huk_conf_reg_t;
+
+
+/** Group: Control registers */
+/** Type of start register
+ *  HUK Generator control register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to continue HUK Generator operation at LOAD/GAIN state.
+         */
+        uint32_t start:1;
+        /** continue : WT; bitpos: [1]; default: 0;
+         *  Write 1 to start HUK Generator at IDLE state.
+         */
+        uint32_t conti:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} huk_start_reg_t;
+
+
+/** Group: State registers */
+/** Type of state register
+ *  HUK Generator state register
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [1:0]; default: 0;
+         *  The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+         */
+        uint32_t state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} huk_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of status register
+ *  HUK Generator HUK status register
+ */
+typedef union {
+    struct {
+        /** status : RO; bitpos: [1:0]; default: 0;
+         *  The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
+         *  2: HUK is generated but invalid. 3: reserved.
+         */
+        uint32_t status:2;
+        /** risk_level : RO; bitpos: [4:2]; default: 0;
+         *  The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
+         *  are in the PUF SRAM. 7: Error Level, HUK is invalid.
+         */
+        uint32_t risk_level:3;
+        /** update_req : RO; bitpos: [5]; default: 0;
+         *  The update request of HUK info. 0: User can update HUK info according to the risk
+         *  level. 1: The HUK info is expired, and user need to update it.
+         */
+        uint32_t update_req:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} huk_status_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37765232;
+         *  HUK Generator version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} huk_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile huk_clk_reg_t clk;
+    volatile huk_int_raw_reg_t int_raw;
+    volatile huk_int_st_reg_t int_st;
+    volatile huk_int_ena_reg_t int_ena;
+    volatile huk_int_clr_reg_t int_clr;
+    uint32_t reserved_018[2];
+    volatile huk_conf_reg_t conf;
+    volatile huk_start_reg_t start;
+    volatile huk_state_reg_t state;
+    uint32_t reserved_02c[2];
+    volatile huk_status_reg_t status;
+    uint32_t reserved_038[49];
+    volatile huk_date_reg_t date;
+    volatile uint32_t info[96];
+} huk_dev_t;
+
+extern huk_dev_t HUK;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i2c_ana_mst_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/i2c_ana_mst_reg.h
new file mode 100644
index 0000000000..dc16cfa416
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i2c_ana_mst_reg.h
@@ -0,0 +1,301 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2C_ANA_MST_I2C0_CTRL_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
+/** I2C_ANA_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CTRL    0x01FFFFFFU
+#define I2C_ANA_MST_I2C0_CTRL_M  (I2C_ANA_MST_I2C0_CTRL_V << I2C_ANA_MST_I2C0_CTRL_S)
+#define I2C_ANA_MST_I2C0_CTRL_V  0x01FFFFFFU
+#define I2C_ANA_MST_I2C0_CTRL_S  0
+/** I2C_ANA_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_BUSY    (BIT(25))
+#define I2C_ANA_MST_I2C0_BUSY_M  (I2C_ANA_MST_I2C0_BUSY_V << I2C_ANA_MST_I2C0_BUSY_S)
+#define I2C_ANA_MST_I2C0_BUSY_V  0x00000001U
+#define I2C_ANA_MST_I2C0_BUSY_S  25
+
+/** I2C_ANA_MST_I2C1_CTRL_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
+/** I2C_ANA_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CTRL    0x01FFFFFFU
+#define I2C_ANA_MST_I2C1_CTRL_M  (I2C_ANA_MST_I2C1_CTRL_V << I2C_ANA_MST_I2C1_CTRL_S)
+#define I2C_ANA_MST_I2C1_CTRL_V  0x01FFFFFFU
+#define I2C_ANA_MST_I2C1_CTRL_S  0
+/** I2C_ANA_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_BUSY    (BIT(25))
+#define I2C_ANA_MST_I2C1_BUSY_M  (I2C_ANA_MST_I2C1_BUSY_V << I2C_ANA_MST_I2C1_BUSY_S)
+#define I2C_ANA_MST_I2C1_BUSY_V  0x00000001U
+#define I2C_ANA_MST_I2C1_BUSY_S  25
+
+/** I2C_ANA_MST_I2C0_CONF_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
+/** I2C_ANA_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CONF    0x00FFFFFFU
+#define I2C_ANA_MST_I2C0_CONF_M  (I2C_ANA_MST_I2C0_CONF_V << I2C_ANA_MST_I2C0_CONF_S)
+#define I2C_ANA_MST_I2C0_CONF_V  0x00FFFFFFU
+#define I2C_ANA_MST_I2C0_CONF_S  0
+/** I2C_ANA_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_STATUS    0x000000FFU
+#define I2C_ANA_MST_I2C0_STATUS_M  (I2C_ANA_MST_I2C0_STATUS_V << I2C_ANA_MST_I2C0_STATUS_S)
+#define I2C_ANA_MST_I2C0_STATUS_V  0x000000FFU
+#define I2C_ANA_MST_I2C0_STATUS_S  24
+
+/** I2C_ANA_MST_I2C1_CONF_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc)
+/** I2C_ANA_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CONF    0x00FFFFFFU
+#define I2C_ANA_MST_I2C1_CONF_M  (I2C_ANA_MST_I2C1_CONF_V << I2C_ANA_MST_I2C1_CONF_S)
+#define I2C_ANA_MST_I2C1_CONF_V  0x00FFFFFFU
+#define I2C_ANA_MST_I2C1_CONF_S  0
+/** I2C_ANA_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_STATUS    0x000000FFU
+#define I2C_ANA_MST_I2C1_STATUS_M  (I2C_ANA_MST_I2C1_STATUS_V << I2C_ANA_MST_I2C1_STATUS_S)
+#define I2C_ANA_MST_I2C1_STATUS_V  0x000000FFU
+#define I2C_ANA_MST_I2C1_STATUS_S  24
+
+/** I2C_ANA_MST_I2C_BURST_CONF_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
+/** I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL    0xFFFFFFFFU
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M  (I2C_ANA_MST_I2C_MST_BURST_CTRL_V << I2C_ANA_MST_I2C_MST_BURST_CTRL_S)
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V  0xFFFFFFFFU
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S  0
+
+/** I2C_ANA_MST_I2C_BURST_STATUS_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
+/** I2C_ANA_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_BURST_DONE    (BIT(0))
+#define I2C_ANA_MST_I2C_MST_BURST_DONE_M  (I2C_ANA_MST_I2C_MST_BURST_DONE_V << I2C_ANA_MST_I2C_MST_BURST_DONE_S)
+#define I2C_ANA_MST_I2C_MST_BURST_DONE_V  0x00000001U
+#define I2C_ANA_MST_I2C_MST_BURST_DONE_S  0
+/** I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG    (BIT(1))
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M  (I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S)
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V  0x00000001U
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S  1
+/** I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG    (BIT(2))
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M  (I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S)
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V  0x00000001U
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S  2
+/** I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W; bitpos: [31:20]; default: 1024;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT    0x00000FFFU
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M  (I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V << I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S)
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V  0x00000FFFU
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S  20
+
+/** I2C_ANA_MST_ANA_CONF0_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
+/** I2C_ANA_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF0    0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF0_M  (I2C_ANA_MST_ANA_CONF0_V << I2C_ANA_MST_ANA_CONF0_S)
+#define I2C_ANA_MST_ANA_CONF0_V  0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF0_S  0
+/** I2C_ANA_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_STATUS0    0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS0_M  (I2C_ANA_MST_ANA_STATUS0_V << I2C_ANA_MST_ANA_STATUS0_S)
+#define I2C_ANA_MST_ANA_STATUS0_V  0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS0_S  24
+
+/** I2C_ANA_MST_ANA_CONF1_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c)
+/** I2C_ANA_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF1    0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF1_M  (I2C_ANA_MST_ANA_CONF1_V << I2C_ANA_MST_ANA_CONF1_S)
+#define I2C_ANA_MST_ANA_CONF1_V  0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF1_S  0
+/** I2C_ANA_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_STATUS1    0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS1_M  (I2C_ANA_MST_ANA_STATUS1_V << I2C_ANA_MST_ANA_STATUS1_S)
+#define I2C_ANA_MST_ANA_STATUS1_V  0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS1_S  24
+
+/** I2C_ANA_MST_ANA_CONF2_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
+/** I2C_ANA_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_CONF2    0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF2_M  (I2C_ANA_MST_ANA_CONF2_V << I2C_ANA_MST_ANA_CONF2_S)
+#define I2C_ANA_MST_ANA_CONF2_V  0x00FFFFFFU
+#define I2C_ANA_MST_ANA_CONF2_S  0
+/** I2C_ANA_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ANA_STATUS2    0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS2_M  (I2C_ANA_MST_ANA_STATUS2_V << I2C_ANA_MST_ANA_STATUS2_S)
+#define I2C_ANA_MST_ANA_STATUS2_V  0x000000FFU
+#define I2C_ANA_MST_ANA_STATUS2_S  24
+
+/** I2C_ANA_MST_I2C0_CTRL1_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
+/** I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR    0x0000003FU
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M  (I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S)
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V  0x0000003FU
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S  0
+/** I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD    0x0000001FU
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M  (I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S)
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V  0x0000001FU
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S  6
+
+/** I2C_ANA_MST_I2C1_CTRL1_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
+/** I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR    0x0000003FU
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M  (I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V << I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S)
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V  0x0000003FU
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S  0
+/** I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD    0x0000001FU
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M  (I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V << I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S)
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V  0x0000001FU
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S  6
+
+/** I2C_ANA_MST_HW_I2C_CTRL_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c)
+/** I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;
+ *  need des
+ */
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR    0x0000003FU
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M  (I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S)
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V  0x0000003FU
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S  0
+/** I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;
+ *  need des
+ */
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD    0x0000001FU
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M  (I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S)
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V  0x0000001FU
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S  6
+/** I2C_ANA_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_ARBITER_DIS    (BIT(11))
+#define I2C_ANA_MST_ARBITER_DIS_M  (I2C_ANA_MST_ARBITER_DIS_V << I2C_ANA_MST_ARBITER_DIS_S)
+#define I2C_ANA_MST_ARBITER_DIS_V  0x00000001U
+#define I2C_ANA_MST_ARBITER_DIS_S  11
+
+/** I2C_ANA_MST_NOUSE_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
+/** I2C_ANA_MST_I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_NOUSE    0xFFFFFFFFU
+#define I2C_ANA_MST_I2C_MST_NOUSE_M  (I2C_ANA_MST_I2C_MST_NOUSE_V << I2C_ANA_MST_I2C_MST_NOUSE_S)
+#define I2C_ANA_MST_I2C_MST_NOUSE_V  0xFFFFFFFFU
+#define I2C_ANA_MST_I2C_MST_NOUSE_S  0
+
+/** I2C_ANA_MST_CLK160M_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_CLK160M_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
+/** I2C_ANA_MST_CLK_I2C_MST_SEL_160M : R/W; bitpos: [0]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M    (BIT(0))
+#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_M  (I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V << I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S)
+#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_V  0x00000001U
+#define I2C_ANA_MST_CLK_I2C_MST_SEL_160M_S  0
+
+/** I2C_ANA_MST_DATE_REG register
+ *  need des
+ */
+#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x38)
+/** I2C_ANA_MST_DATE : R/W; bitpos: [27:0]; default: 36717104;
+ *  need des
+ */
+#define I2C_ANA_MST_DATE    0x0FFFFFFFU
+#define I2C_ANA_MST_DATE_M  (I2C_ANA_MST_DATE_V << I2C_ANA_MST_DATE_S)
+#define I2C_ANA_MST_DATE_V  0x0FFFFFFFU
+#define I2C_ANA_MST_DATE_S  0
+/** I2C_ANA_MST_I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;
+ *  need des
+ */
+#define I2C_ANA_MST_I2C_MST_CLK_EN    (BIT(28))
+#define I2C_ANA_MST_I2C_MST_CLK_EN_M  (I2C_ANA_MST_I2C_MST_CLK_EN_V << I2C_ANA_MST_I2C_MST_CLK_EN_S)
+#define I2C_ANA_MST_I2C_MST_CLK_EN_V  0x00000001U
+#define I2C_ANA_MST_I2C_MST_CLK_EN_S  28
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i2c_ana_mst_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/i2c_ana_mst_struct.h
new file mode 100644
index 0000000000..2d3457bffa
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i2c_ana_mst_struct.h
@@ -0,0 +1,304 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configure Register */
+/** Type of i2c0_ctrl register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c0_ctrl : R/W; bitpos: [24:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c0_ctrl:25;
+        /** i2c0_busy : RO; bitpos: [25]; default: 0;
+         *  need des
+         */
+        uint32_t i2c0_busy:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c0_ctrl_reg_t;
+
+/** Type of i2c1_ctrl register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c1_ctrl : R/W; bitpos: [24:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c1_ctrl:25;
+        /** i2c1_busy : RO; bitpos: [25]; default: 0;
+         *  need des
+         */
+        uint32_t i2c1_busy:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c1_ctrl_reg_t;
+
+/** Type of i2c0_conf register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c0_conf : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c0_conf:24;
+        /** i2c0_status : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t i2c0_status:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c0_conf_reg_t;
+
+/** Type of i2c1_conf register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c1_conf : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c1_conf:24;
+        /** i2c1_status : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t i2c1_status:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c1_conf_reg_t;
+
+/** Type of i2c_burst_conf register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c_mst_burst_ctrl : R/W; bitpos: [31:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst_burst_ctrl:32;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c_burst_conf_reg_t;
+
+/** Type of i2c_burst_status register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c_mst_burst_done : RO; bitpos: [0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst_burst_done:1;
+        /** i2c_mst0_burst_err_flag : RO; bitpos: [1]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst0_burst_err_flag:1;
+        /** i2c_mst1_burst_err_flag : RO; bitpos: [2]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst1_burst_err_flag:1;
+        uint32_t reserved_3:17;
+        /** i2c_mst_burst_timeout_cnt : R/W; bitpos: [31:20]; default: 1024;
+         *  need des
+         */
+        uint32_t i2c_mst_burst_timeout_cnt:12;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c_burst_status_reg_t;
+
+/** Type of ana_conf0 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** ana_conf0 : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t ana_conf0:24;
+        /** ana_status0 : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t ana_status0:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_ana_conf0_reg_t;
+
+/** Type of ana_conf1 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** ana_conf1 : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t ana_conf1:24;
+        /** ana_status1 : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t ana_status1:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_ana_conf1_reg_t;
+
+/** Type of ana_conf2 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** ana_conf2 : R/W; bitpos: [23:0]; default: 0;
+         *  need des
+         */
+        uint32_t ana_conf2:24;
+        /** ana_status2 : RO; bitpos: [31:24]; default: 0;
+         *  need des
+         */
+        uint32_t ana_status2:8;
+    };
+    uint32_t val;
+} i2c_ana_mst_ana_conf2_reg_t;
+
+/** Type of i2c0_ctrl1 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c0_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
+         *  need des
+         */
+        uint32_t i2c0_scl_pulse_dur:6;
+        /** i2c0_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
+         *  need des
+         */
+        uint32_t i2c0_sda_side_guard:5;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c0_ctrl1_reg_t;
+
+/** Type of i2c1_ctrl1 register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c1_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
+         *  need des
+         */
+        uint32_t i2c1_scl_pulse_dur:6;
+        /** i2c1_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
+         *  need des
+         */
+        uint32_t i2c1_sda_side_guard:5;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} i2c_ana_mst_i2c1_ctrl1_reg_t;
+
+/** Type of hw_i2c_ctrl register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** hw_i2c_scl_pulse_dur : R/W; bitpos: [5:0]; default: 2;
+         *  need des
+         */
+        uint32_t hw_i2c_scl_pulse_dur:6;
+        /** hw_i2c_sda_side_guard : R/W; bitpos: [10:6]; default: 1;
+         *  need des
+         */
+        uint32_t hw_i2c_sda_side_guard:5;
+        /** arbiter_dis : R/W; bitpos: [11]; default: 0;
+         *  need des
+         */
+        uint32_t arbiter_dis:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2c_ana_mst_hw_i2c_ctrl_reg_t;
+
+/** Type of nouse register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** i2c_mst_nouse : R/W; bitpos: [31:0]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst_nouse:32;
+    };
+    uint32_t val;
+} i2c_ana_mst_nouse_reg_t;
+
+/** Type of clk160m register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** clk_i2c_mst_sel_160m : R/W; bitpos: [0]; default: 0;
+         *  need des
+         */
+        uint32_t clk_i2c_mst_sel_160m:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2c_ana_mst_clk160m_reg_t;
+
+/** Type of date register
+ *  need des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36717104;
+         *  need des
+         */
+        uint32_t date:28;
+        /** i2c_mst_clk_en : R/W; bitpos: [28]; default: 0;
+         *  need des
+         */
+        uint32_t i2c_mst_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i2c_ana_mst_date_reg_t;
+
+
+typedef struct {
+    volatile i2c_ana_mst_i2c0_ctrl_reg_t i2c0_ctrl;
+    volatile i2c_ana_mst_i2c1_ctrl_reg_t i2c1_ctrl;
+    volatile i2c_ana_mst_i2c0_conf_reg_t i2c0_conf;
+    volatile i2c_ana_mst_i2c1_conf_reg_t i2c1_conf;
+    volatile i2c_ana_mst_i2c_burst_conf_reg_t i2c_burst_conf;
+    volatile i2c_ana_mst_i2c_burst_status_reg_t i2c_burst_status;
+    volatile i2c_ana_mst_ana_conf0_reg_t ana_conf0;
+    volatile i2c_ana_mst_ana_conf1_reg_t ana_conf1;
+    volatile i2c_ana_mst_ana_conf2_reg_t ana_conf2;
+    volatile i2c_ana_mst_i2c0_ctrl1_reg_t i2c0_ctrl1;
+    volatile i2c_ana_mst_i2c1_ctrl1_reg_t i2c1_ctrl1;
+    volatile i2c_ana_mst_hw_i2c_ctrl_reg_t hw_i2c_ctrl;
+    volatile i2c_ana_mst_nouse_reg_t nouse;
+    volatile i2c_ana_mst_clk160m_reg_t clk160m;
+    volatile i2c_ana_mst_date_reg_t date;
+} i2c_ana_mst_dev_t;
+
+extern i2c_ana_mst_dev_t I2C_ANA_MST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_ana_mst_dev_t) == 0x3c, "Invalid size of i2c_ana_mst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i2c_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/i2c_eco5_struct.h
new file mode 100644
index 0000000000..4f3e3789eb
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i2c_eco5_struct.h
@@ -0,0 +1,1235 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Timing registers */
+/** Type of scl_low_period register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+typedef union {
+    struct {
+        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the low level width of the SCL Clock in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_low_period:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_low_period_reg_t;
+
+/** Type of sda_hold register
+ *  Configures the hold time after a negative SCL edge
+ */
+typedef union {
+    struct {
+        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the time to hold the data after the falling edge of SCL.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_hold_reg_t;
+
+/** Type of sda_sample register
+ *  Configures the sample time after a positive SCL edge
+ */
+typedef union {
+    struct {
+        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the time for sampling SDA.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_sample_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_sample_reg_t;
+
+/** Type of scl_high_period register
+ *  Configures the high level width of SCL
+ */
+typedef union {
+    struct {
+        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures for how long SCL remains high in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_high_period:9;
+        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
+         *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_wait_high_period:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_scl_high_period_reg_t;
+
+/** Type of scl_start_hold register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+typedef union {
+    struct {
+        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+         *  a START condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_start_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_start_hold_reg_t;
+
+/** Type of scl_rstart_setup register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+typedef union {
+    struct {
+        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the positive edge of SCL and the negative edge of SDA
+         *  for a RESTART condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_rstart_setup_reg_t;
+
+/** Type of scl_stop_hold register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the delay after the STOP condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_hold_reg_t;
+
+/** Type of scl_stop_setup register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the positive edgeof SCL and the
+         *  positive edge of SDA, in I2C module clock cycles.
+         */
+        uint32_t scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_setup_reg_t;
+
+/** Type of scl_st_time_out register
+ *  SCL status time out register
+ */
+typedef union {
+    struct {
+        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+         *  more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_st_time_out_reg_t;
+
+/** Type of scl_main_st_time_out register
+ *  SCL main status time out register
+ */
+typedef union {
+    struct {
+        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be
+         *  no more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_main_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_main_st_time_out_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of ctr register
+ *  Transmission setting
+ */
+typedef union {
+    struct {
+        /** sda_force_out : R/W; bitpos: [0]; default: 0;
+         *  Configures the SDA output mode.
+         *  0: Open drain output
+         *  1: Direct output
+         */
+        uint32_t sda_force_out:1;
+        /** scl_force_out : R/W; bitpos: [1]; default: 0;
+         *  Configures the SCL output mode.
+         *  0: Open drain output
+         *  1: Direct output
+         */
+        uint32_t scl_force_out:1;
+        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
+         *  Configures the sample mode for SDA.
+         *  0: Sample SDA data on the SCL high level
+         *  1: Sample SDA data on the SCL low level
+         */
+        uint32_t sample_scl_level:1;
+        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
+         *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
+         *  reached the threshold.
+         */
+        uint32_t rx_full_ack_level:1;
+        /** ms_mode : R/W; bitpos: [4]; default: 0;
+         *  Configures the module as an I2C Master or Slave.
+         *  0: Slave
+         *  1: Master
+         */
+        uint32_t ms_mode:1;
+        /** trans_start : WT; bitpos: [5]; default: 0;
+         *  Configures whether the slave starts sending the data in txfifo.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t trans_start:1;
+        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
+         *  Configures to control the sending order for data needing to be sent.
+         *  0: send data from the most significant bit
+         *  1: send data from the least significant bit
+         */
+        uint32_t tx_lsb_first:1;
+        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
+         *  Configures to control the storage order for received data.
+         *  0: receive data from the most significant bit
+         *  1: receive data from the least significant bit
+         */
+        uint32_t rx_lsb_first:1;
+        /** clk_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to gate clock signal for registers.
+         *  0: Support clock only when registers are read or written to by software
+         *  1: Force clock on for registers
+         */
+        uint32_t clk_en:1;
+        /** arbitration_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable I2C bus arbitration detection.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t arbitration_en:1;
+        /** fsm_rst : WT; bitpos: [10]; default: 0;
+         *  Configures to reset the SCL_FSM.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t fsm_rst:1;
+        /** conf_upgate : WT; bitpos: [11]; default: 0;
+         *  Configures this bit for synchronization.
+         *  0: No effect
+         *  1: Synchronize
+         */
+        uint32_t conf_upgate:1;
+        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable slave to send data automatically
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t slv_tx_auto_start_en:1;
+        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
+         *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
+         *  0: Not check
+         *  1: Check
+         */
+        uint32_t addr_10bit_rw_check_en:1;
+        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
+         *  Configures to support the 7 bit general call function.
+         *  0: Not support
+         *  1: Support
+         */
+        uint32_t addr_broadcasting_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_ctr_reg_t;
+
+/** Type of to register
+ *  Setting time out control for receiving data
+ */
+typedef union {
+    struct {
+        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the timeout threshold period for SCL stucking at high or low level. The
+         *  actual period is 2\^{}(reg_time_out_value).
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t time_out_value:5;
+        /** time_out_en : R/W; bitpos: [5]; default: 0;
+         *  Configures to enable time out control.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t time_out_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i2c_to_reg_t;
+
+/** Type of slave_addr register
+ *  Local slave address setting
+ */
+typedef union {
+    struct {
+        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
+         *  Configure the slave address of I2C Slave.
+         */
+        uint32_t slave_addr:15;
+        uint32_t reserved_15:16;
+        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
+         *  Configures to enable the slave 10-bit addressing mode in master mode.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t addr_10bit_en:1;
+    };
+    uint32_t val;
+} i2c_slave_addr_reg_t;
+
+/** Type of fifo_conf register
+ *  FIFO configuration register
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
+         *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
+         *  I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0],
+         *  I2C_RXFIFO_WM_INT_RAW bit will be valid.
+         *  \tododone{For CJ, please check this description. I habe doubt about
+         *  reg_reg_fifo_prt_en.CJ: modified}
+         */
+        uint32_t rxfifo_wm_thrhd:5;
+        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
+         *  Configures the water mark threshold of TXFIFO in nonfifo access mode.  When
+         *  I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0],
+         *  I2C_TXFIFO_WM_INT_RAW bit will be valid.
+         */
+        uint32_t txfifo_wm_thrhd:5;
+        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable APB nonfifo access.
+         */
+        uint32_t nonfifo_en:1;
+        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
+         *  Configures the slave to enable dual address mode. When this mode is enabled, the
+         *  byte received after the I2C address byte represents the offset address in the I2C
+         *  Slave RAM.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t fifo_addr_cfg_en:1;
+        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
+         *  Configures to reset RXFIFO.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t rx_fifo_rst:1;
+        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
+         *  Configures to reset TXFIFO.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t tx_fifo_rst:1;
+        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
+         *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
+         *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t fifo_prt_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_fifo_conf_reg_t;
+
+/** Type of filter_cfg register
+ *  SCL and SDA filter configuration register
+ */
+typedef union {
+    struct {
+        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_filter_thres:4;
+        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_filter_thres:4;
+        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
+         *  Configures to enable the filter function for SCL.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t scl_filter_en:1;
+        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable the filter function for SDA.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t sda_filter_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} i2c_filter_cfg_reg_t;
+
+/** Type of scl_sp_conf register
+ *  Power configuration register
+ */
+typedef union {
+    struct {
+        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
+         *  equals to I2C_SCL_RST_SLV_NUM[4:0].
+         */
+        uint32_t scl_rst_slv_en:1;
+        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
+         *  Configure the pulses of SCL generated in I2C master mode.
+         *  Valid when I2C_SCL_RST_SLV_EN is 1.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rst_slv_num:5;
+        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
+         *  Configures to power down the I2C output SCL line.
+         *  0: Not power down.
+         *  1: Not work and power down.
+         *  Valid only when I2C_SCL_FORCE_OUT is 1.
+         */
+        uint32_t scl_pd_en:1;
+        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
+         *  Configures to power down the I2C output SDA line.
+         *  0: Not power down.
+         *  1: Not work and power down.
+         *  Valid only when I2C_SDA_FORCE_OUT is 1.
+         */
+        uint32_t sda_pd_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_scl_sp_conf_reg_t;
+
+/** Type of scl_stretch_conf register
+ *  Set SCL stretch of I2C slave
+ */
+typedef union {
+    struct {
+        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
+         *  Configures the time period to release the SCL line from stretching to avoid timing
+         *  violation. Usually it should be larger than the SDA setup time.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t stretch_protect_num:10;
+        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable slave SCL stretch function. The SCL output line will be
+         *  stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The
+         *  stretch cause can be seen in I2C_STRETCH_CAUSE.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t slave_scl_stretch_en:1;
+        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
+         *  Configures to clear the I2C slave SCL stretch function.
+         *  0: No effect
+         *  1: Clear
+         */
+        uint32_t slave_scl_stretch_clr:1;
+        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable the function for slave to control ACK level.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t slave_byte_ack_ctl_en:1;
+        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
+         *  Set the ACK level when slave controlling ACK level function enables.
+         *  0: Low level
+         *  1: High level
+         */
+        uint32_t slave_byte_ack_lvl:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i2c_scl_stretch_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of sr register
+ *  Describe I2C work status
+ */
+typedef union {
+    struct {
+        /** resp_rec : RO; bitpos: [0]; default: 0;
+         *  Represents the received ACK value in master mode or slave mode.
+         *  0: ACK
+         *  1: NACK.
+         */
+        uint32_t resp_rec:1;
+        /** slave_rw : RO; bitpos: [1]; default: 0;
+         *  Represents the transfer direction in slave mode.
+         *  1: Master reads from slave
+         *  0: Master writes to slave.
+         */
+        uint32_t slave_rw:1;
+        uint32_t reserved_2:1;
+        /** arb_lost : RO; bitpos: [3]; default: 0;
+         *  Represents whether the I2C controller loses control of SCL line.
+         *  0: No arbitration lost
+         *  1: Arbitration lost
+         */
+        uint32_t arb_lost:1;
+        /** bus_busy : RO; bitpos: [4]; default: 0;
+         *  Represents the I2C bus state.
+         *  1: The I2C bus is busy transferring data
+         *  0: The I2C bus is in idle state.
+         */
+        uint32_t bus_busy:1;
+        /** slave_addressed : RO; bitpos: [5]; default: 0;
+         *  Represents whether the address sent by the master is equal to the address of the
+         *  slave.
+         *  Valid only when the module is configured as an I2C Slave.
+         *  0: Not equal
+         *  1: Equal
+         */
+        uint32_t slave_addressed:1;
+        uint32_t reserved_6:2;
+        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
+         *  Represents the number of data bytes received in RAM.
+         */
+        uint32_t rxfifo_cnt:6;
+        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
+         *  Represents the cause of SCL clocking stretching in slave mode.
+         *  0: Stretching SCL low when the master starts to read data.
+         *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
+         *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
+         */
+        uint32_t stretch_cause:2;
+        uint32_t reserved_16:2;
+        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
+         *  Represents the number of data bytes to be sent.
+         */
+        uint32_t txfifo_cnt:6;
+        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  Represents the states of the I2C module state machine.
+         *  0: Idle
+         *  1: Address shift
+         *  2: ACK address
+         *  3: Rx data
+         *  4: Tx data
+         *  5: Send ACK
+         *  6: Wait ACK
+         */
+        uint32_t scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  Represents the states of the state machine used to produce SCL.
+         *  0: Idle
+         *  1: Start
+         *  2: Negative edge
+         *  3: Low
+         *  4: Positive edge
+         *  5: High
+         *  6: Stop
+         */
+        uint32_t scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2c_sr_reg_t;
+
+/** Type of fifo_st register
+ *  FIFO status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
+         *  Represents the offset address of the APB reading from RXFIFO.
+         */
+        uint32_t rxfifo_raddr:5;
+        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
+         *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
+         */
+        uint32_t rxfifo_waddr:5;
+        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
+         *  Represents the offset address of i2c module reading from TXFIFO.
+         */
+        uint32_t txfifo_raddr:5;
+        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
+         *  Represents the offset address of APB bus writing to TXFIFO.
+         */
+        uint32_t txfifo_waddr:5;
+        uint32_t reserved_20:2;
+        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
+         *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+         *  I2C slave mode.
+         */
+        uint32_t slave_rw_point:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2c_fifo_st_reg_t;
+
+/** Type of data register
+ *  Rx FIFO read data
+ */
+typedef union {
+    struct {
+        /** fifo_rdata : HRO; bitpos: [7:0]; default: 0;
+         *  Represents the value of RXFIFO read data.
+         */
+        uint32_t fifo_rdata:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_data_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_raw:1;
+        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
+         *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_raw:1;
+        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_raw:1;
+        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_raw:1;
+        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_raw:1;
+        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_raw:1;
+        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_raw:1;
+        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_raw:1;
+        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_raw:1;
+        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_raw:1;
+        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_raw:1;
+        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_raw:1;
+        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_raw:1;
+        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  The raw interrupt status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_raw:1;
+        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_raw:1;
+        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
+         *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_raw:1;
+        /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_raw:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_clr:1;
+        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_clr:1;
+        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_clr:1;
+        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_clr:1;
+        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_clr:1;
+        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_clr:1;
+        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_clr:1;
+        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_clr:1;
+        /** nack_int_clr : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_clr:1;
+        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_clr:1;
+        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_clr:1;
+        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
+         *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_clr:1;
+        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
+         *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_clr:1;
+        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  Write 1 to clear I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_clr:1;
+        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_clr:1;
+        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
+         *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_clr:1;
+        /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_clr:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_ena:1;
+        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_ena:1;
+        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_ena:1;
+        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_ena:1;
+        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_ena:1;
+        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_ena:1;
+        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_ena:1;
+        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_ena:1;
+        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_ena:1;
+        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_ena:1;
+        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_ena:1;
+        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Write 1 to enable I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_ena:1;
+        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_ena:1;
+        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_ena:1;
+        /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_ena:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_ena_reg_t;
+
+/** Type of int_status register
+ *  Status of captured I2C communication events
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_st:1;
+        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_st:1;
+        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_st:1;
+        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_st:1;
+        /** time_out_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_st:1;
+        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_st:1;
+        /** nack_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_st:1;
+        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_st:1;
+        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_st:1;
+        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_st:1;
+        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_st:1;
+        /** det_start_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_st:1;
+        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_st:1;
+        /** general_call_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_st:1;
+        /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_st:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_status_reg_t;
+
+
+/** Group: Command registers */
+/** Type of comd0 register
+ *  I2C command register 0
+ */
+typedef union {
+    struct {
+        /** command0 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 0.
+         *  It consists of three parts:
+         *  op_code is the command
+         *  1: WRITE
+         *  2: STOP
+         *  3: READ
+         *  4: END
+         *  6: RSTART
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure  for more information.
+         *  \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}"
+         */
+        uint32_t command0:14;
+        uint32_t reserved_14:17;
+        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 0 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command0_done:1;
+    };
+    uint32_t val;
+} i2c_comd0_reg_t;
+
+/** Type of comd1 register
+ *  I2C command register 1
+ */
+typedef union {
+    struct {
+        /** command1 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 1.
+         *  See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command1:14;
+        uint32_t reserved_14:17;
+        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 1 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command1_done:1;
+    };
+    uint32_t val;
+} i2c_comd1_reg_t;
+
+/** Type of comd2 register
+ *  I2C command register 2
+ */
+typedef union {
+    struct {
+        /** command2 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 2. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command2:14;
+        uint32_t reserved_14:17;
+        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 2 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command2_done:1;
+    };
+    uint32_t val;
+} i2c_comd2_reg_t;
+
+/** Type of comd3 register
+ *  I2C command register 3
+ */
+typedef union {
+    struct {
+        /** command3 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 3. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command3:14;
+        uint32_t reserved_14:17;
+        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 3 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command3_done:1;
+    };
+    uint32_t val;
+} i2c_comd3_reg_t;
+
+/** Type of comd4 register
+ *  I2C command register 4
+ */
+typedef union {
+    struct {
+        /** command4 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 4. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command4:14;
+        uint32_t reserved_14:17;
+        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 4 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command4_done:1;
+    };
+    uint32_t val;
+} i2c_comd4_reg_t;
+
+/** Type of comd5 register
+ *  I2C command register 5
+ */
+typedef union {
+    struct {
+        /** command5 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 5. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command5:14;
+        uint32_t reserved_14:17;
+        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 5 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command5_done:1;
+    };
+    uint32_t val;
+} i2c_comd5_reg_t;
+
+/** Type of comd6 register
+ *  I2C command register 6
+ */
+typedef union {
+    struct {
+        /** command6 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 6. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command6:14;
+        uint32_t reserved_14:17;
+        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 6 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command6_done:1;
+    };
+    uint32_t val;
+} i2c_comd6_reg_t;
+
+/** Type of comd7 register
+ *  I2C command register 7
+ */
+typedef union {
+    struct {
+        /** command7 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 7. See details in I2C_CMD0_REG[13:0].
+         */
+        uint32_t command7:14;
+        uint32_t reserved_14:17;
+        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 7 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command7_done:1;
+    };
+    uint32_t val;
+} i2c_comd7_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 37765248;
+         *  Version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} i2c_date_reg_t;
+
+
+/** Group: Address register */
+/** Type of txfifo_start_addr register
+ *  I2C TXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Represents the I2C txfifo first address.
+         */
+        uint32_t txfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_txfifo_start_addr_reg_t;
+
+/** Type of rxfifo_start_addr register
+ *  I2C RXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Represents the I2C rxfifo first address.
+         */
+        uint32_t rxfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_rxfifo_start_addr_reg_t;
+
+
+typedef struct {
+    volatile i2c_scl_low_period_reg_t scl_low_period;
+    volatile i2c_ctr_reg_t ctr;
+    volatile i2c_sr_reg_t sr;
+    volatile i2c_to_reg_t to;
+    volatile i2c_slave_addr_reg_t slave_addr;
+    volatile i2c_fifo_st_reg_t fifo_st;
+    volatile i2c_fifo_conf_reg_t fifo_conf;
+    volatile i2c_data_reg_t data;
+    volatile i2c_int_raw_reg_t int_raw;
+    volatile i2c_int_clr_reg_t int_clr;
+    volatile i2c_int_ena_reg_t int_ena;
+    volatile i2c_int_status_reg_t int_status;
+    volatile i2c_sda_hold_reg_t sda_hold;
+    volatile i2c_sda_sample_reg_t sda_sample;
+    volatile i2c_scl_high_period_reg_t scl_high_period;
+    uint32_t reserved_03c;
+    volatile i2c_scl_start_hold_reg_t scl_start_hold;
+    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
+    volatile i2c_filter_cfg_reg_t filter_cfg;
+    uint32_t reserved_054;
+    volatile i2c_comd0_reg_t comd0;
+    volatile i2c_comd1_reg_t comd1;
+    volatile i2c_comd2_reg_t comd2;
+    volatile i2c_comd3_reg_t comd3;
+    volatile i2c_comd4_reg_t comd4;
+    volatile i2c_comd5_reg_t comd5;
+    volatile i2c_comd6_reg_t comd6;
+    volatile i2c_comd7_reg_t comd7;
+    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
+    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
+    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
+    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
+    uint32_t reserved_088[28];
+    volatile i2c_date_reg_t date;
+    uint32_t reserved_0fc;
+    volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
+    uint32_t reserved_104[31];
+    volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
+} i2c_dev_t;
+
+extern i2c_dev_t I2C0;
+extern i2c_dev_t I2C1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i2c_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/i2c_reg.h
new file mode 100644
index 0000000000..0ba382e077
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i2c_reg.h
@@ -0,0 +1,1478 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2C_SCL_LOW_PERIOD_REG register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0)
+/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the low level width of the SCL Clock in master mode.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_LOW_PERIOD    0x000001FFU
+#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
+#define I2C_SCL_LOW_PERIOD_V  0x000001FFU
+#define I2C_SCL_LOW_PERIOD_S  0
+
+/** I2C_CTR_REG register
+ *  Transmission setting
+ */
+#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4)
+/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
+ *  Configures the SDA output mode.
+ *  0: Open drain output
+ *  1: Direct output
+ */
+#define I2C_SDA_FORCE_OUT    (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
+#define I2C_SDA_FORCE_OUT_V  0x00000001U
+#define I2C_SDA_FORCE_OUT_S  0
+/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
+ *  Configures the SCL output mode.
+ *  0: Open drain output
+ *  1: Direct output
+ */
+#define I2C_SCL_FORCE_OUT    (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
+#define I2C_SCL_FORCE_OUT_V  0x00000001U
+#define I2C_SCL_FORCE_OUT_S  1
+/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
+ *  Configures the sample mode for SDA.
+ *  0: Sample SDA data on the SCL high level
+ *  1: Sample SDA data on the SCL low level
+ */
+#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
+#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
+ *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
+ *  reached the threshold.
+ */
+#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
+#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
+ *  Configures the module as an I2C Master or Slave.
+ *  0: Slave
+ *  1: Master
+ */
+#define I2C_MS_MODE    (BIT(4))
+#define I2C_MS_MODE_M  (I2C_MS_MODE_V << I2C_MS_MODE_S)
+#define I2C_MS_MODE_V  0x00000001U
+#define I2C_MS_MODE_S  4
+/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
+ *  Configures whether the slave starts sending the data in txfifo.
+ *  0: No effect
+ *  1: Start
+ */
+#define I2C_TRANS_START    (BIT(5))
+#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
+#define I2C_TRANS_START_V  0x00000001U
+#define I2C_TRANS_START_S  5
+/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
+ *  Configures to control the sending order for data needing to be sent.
+ *  0: send data from the most significant bit
+ *  1: send data from the least significant bit
+ */
+#define I2C_TX_LSB_FIRST    (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
+#define I2C_TX_LSB_FIRST_V  0x00000001U
+#define I2C_TX_LSB_FIRST_S  6
+/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
+ *  Configures to control the storage order for received data.
+ *  0: receive data from the most significant bit
+ *  1: receive data from the least significant bit
+ */
+#define I2C_RX_LSB_FIRST    (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
+#define I2C_RX_LSB_FIRST_V  0x00000001U
+#define I2C_RX_LSB_FIRST_S  7
+/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to gate clock signal for registers.
+ *  0: Support clock only when registers are read or written to by software
+ *  1: Force clock on for registers
+ */
+#define I2C_CLK_EN    (BIT(8))
+#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
+#define I2C_CLK_EN_V  0x00000001U
+#define I2C_CLK_EN_S  8
+/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
+ *  Configures to enable I2C bus arbitration detection.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_ARBITRATION_EN    (BIT(9))
+#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
+#define I2C_ARBITRATION_EN_V  0x00000001U
+#define I2C_ARBITRATION_EN_S  9
+/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
+ *  Configures to reset the SCL_FSM.
+ *  0: No effect
+ *  1: Reset
+ */
+#define I2C_FSM_RST    (BIT(10))
+#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
+#define I2C_FSM_RST_V  0x00000001U
+#define I2C_FSM_RST_S  10
+/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
+ *  Configures this bit for synchronization.
+ *  0: No effect
+ *  1: Synchronize
+ */
+#define I2C_CONF_UPGATE    (BIT(11))
+#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
+#define I2C_CONF_UPGATE_V  0x00000001U
+#define I2C_CONF_UPGATE_S  11
+/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures to enable slave to send data automatically
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_M  (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
+#define I2C_SLV_TX_AUTO_START_EN_V  0x00000001U
+#define I2C_SLV_TX_AUTO_START_EN_S  12
+/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
+ *  0: Not check
+ *  1: Check
+ */
+#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
+#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S)
+#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
+/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures to support the 7 bit general call function.
+ *  0: Not support
+ *  1: Support
+ */
+#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
+#define I2C_ADDR_BROADCASTING_EN_M  (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S)
+#define I2C_ADDR_BROADCASTING_EN_V  0x00000001U
+#define I2C_ADDR_BROADCASTING_EN_S  14
+
+/** I2C_SR_REG register
+ *  Describe I2C work status
+ */
+#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8)
+/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
+ *  Represents the received ACK value in master mode or slave mode.
+ *  0: ACK
+ *  1: NACK.
+ */
+#define I2C_RESP_REC    (BIT(0))
+#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
+#define I2C_RESP_REC_V  0x00000001U
+#define I2C_RESP_REC_S  0
+/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
+ *  Represents the transfer direction in slave mode.
+ *  1: Master reads from slave
+ *  0: Master writes to slave.
+ */
+#define I2C_SLAVE_RW    (BIT(1))
+#define I2C_SLAVE_RW_M  (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S)
+#define I2C_SLAVE_RW_V  0x00000001U
+#define I2C_SLAVE_RW_S  1
+/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
+ *  Represents whether the I2C controller loses control of SCL line.
+ *  0: No arbitration lost
+ *  1: Arbitration lost
+ */
+#define I2C_ARB_LOST    (BIT(3))
+#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
+#define I2C_ARB_LOST_V  0x00000001U
+#define I2C_ARB_LOST_S  3
+/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
+ *  Represents the I2C bus state.
+ *  1: The I2C bus is busy transferring data
+ *  0: The I2C bus is in idle state.
+ */
+#define I2C_BUS_BUSY    (BIT(4))
+#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
+#define I2C_BUS_BUSY_V  0x00000001U
+#define I2C_BUS_BUSY_S  4
+/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0;
+ *  Represents whether the address sent by the master is equal to the address of the
+ *  slave.
+ *  Valid only when the module is configured as an I2C Slave.
+ *  0: Not equal
+ *  1: Equal
+ */
+#define I2C_SLAVE_ADDRESSED    (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M  (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S)
+#define I2C_SLAVE_ADDRESSED_V  0x00000001U
+#define I2C_SLAVE_ADDRESSED_S  5
+/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0;
+ *  Represents the number of data bytes received in RAM.
+ */
+#define I2C_RXFIFO_CNT    0x0000003FU
+#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
+#define I2C_RXFIFO_CNT_V  0x0000003FU
+#define I2C_RXFIFO_CNT_S  8
+/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3;
+ *  Represents the cause of SCL clocking stretching in slave mode.
+ *  0: Stretching SCL low when the master starts to read data.
+ *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
+ *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
+ */
+#define I2C_STRETCH_CAUSE    0x00000003U
+#define I2C_STRETCH_CAUSE_M  (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S)
+#define I2C_STRETCH_CAUSE_V  0x00000003U
+#define I2C_STRETCH_CAUSE_S  14
+/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0;
+ *  Represents the number of data bytes to be sent.
+ */
+#define I2C_TXFIFO_CNT    0x0000003FU
+#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
+#define I2C_TXFIFO_CNT_V  0x0000003FU
+#define I2C_TXFIFO_CNT_S  18
+/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
+ *  Represents the states of the I2C module state machine.
+ *  0: Idle
+ *  1: Address shift
+ *  2: ACK address
+ *  3: Rx data
+ *  4: Tx data
+ *  5: Send ACK
+ *  6: Wait ACK
+ */
+#define I2C_SCL_MAIN_STATE_LAST    0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
+#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
+ *  Represents the states of the state machine used to produce SCL.
+ *  0: Idle
+ *  1: Start
+ *  2: Negative edge
+ *  3: Low
+ *  4: Positive edge
+ *  5: High
+ *  6: Stop
+ */
+#define I2C_SCL_STATE_LAST    0x00000007U
+#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
+#define I2C_SCL_STATE_LAST_V  0x00000007U
+#define I2C_SCL_STATE_LAST_S  28
+
+/** I2C_TO_REG register
+ *  Setting time out control for receiving data
+ */
+#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xc)
+/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the timeout threshold period for SCL stucking at high or low level. The
+ *  actual period is 2\^{}(reg_time_out_value).
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_TIME_OUT_VALUE    0x0000001FU
+#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
+#define I2C_TIME_OUT_VALUE_V  0x0000001FU
+#define I2C_TIME_OUT_VALUE_S  0
+/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures to enable time out control.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_TIME_OUT_EN    (BIT(5))
+#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
+#define I2C_TIME_OUT_EN_V  0x00000001U
+#define I2C_TIME_OUT_EN_S  5
+
+/** I2C_SLAVE_ADDR_REG register
+ *  Local slave address setting
+ */
+#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10)
+/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
+ *  Configure the slave address of I2C Slave.
+ */
+#define I2C_SLAVE_ADDR    0x00007FFFU
+#define I2C_SLAVE_ADDR_M  (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S)
+#define I2C_SLAVE_ADDR_V  0x00007FFFU
+#define I2C_SLAVE_ADDR_S  0
+/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures to enable the slave 10-bit addressing mode in master mode.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_ADDR_10BIT_EN    (BIT(31))
+#define I2C_ADDR_10BIT_EN_M  (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S)
+#define I2C_ADDR_10BIT_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_EN_S  31
+
+/** I2C_FIFO_ST_REG register
+ *  FIFO status register
+ */
+#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14)
+/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
+ *  Represents the offset address of the APB reading from RXFIFO.
+ */
+#define I2C_RXFIFO_RADDR    0x0000001FU
+#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
+#define I2C_RXFIFO_RADDR_V  0x0000001FU
+#define I2C_RXFIFO_RADDR_S  0
+/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0;
+ *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
+ */
+#define I2C_RXFIFO_WADDR    0x0000001FU
+#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
+#define I2C_RXFIFO_WADDR_V  0x0000001FU
+#define I2C_RXFIFO_WADDR_S  5
+/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0;
+ *  Represents the offset address of i2c module reading from TXFIFO.
+ */
+#define I2C_TXFIFO_RADDR    0x0000001FU
+#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
+#define I2C_TXFIFO_RADDR_V  0x0000001FU
+#define I2C_TXFIFO_RADDR_S  10
+/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0;
+ *  Represents the offset address of APB bus writing to TXFIFO.
+ */
+#define I2C_TXFIFO_WADDR    0x0000001FU
+#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
+#define I2C_TXFIFO_WADDR_V  0x0000001FU
+#define I2C_TXFIFO_WADDR_S  15
+/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0;
+ *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+ *  I2C slave mode.
+ */
+#define I2C_SLAVE_RW_POINT    0x000000FFU
+#define I2C_SLAVE_RW_POINT_M  (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S)
+#define I2C_SLAVE_RW_POINT_V  0x000000FFU
+#define I2C_SLAVE_RW_POINT_S  22
+
+/** I2C_FIFO_CONF_REG register
+ *  FIFO configuration register
+ */
+#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18)
+/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
+ *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
+ *  I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0],
+ *  I2C_RXFIFO_WM_INT_RAW bit will be valid.
+ *  \tododone{For CJ, please check this description. I habe doubt about
+ *  reg_reg_fifo_prt_en.CJ: modified}
+ */
+#define I2C_RXFIFO_WM_THRHD    0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
+#define I2C_RXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_S  0
+/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4;
+ *  Configures the water mark threshold of TXFIFO in nonfifo access mode.  When
+ *  I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0],
+ *  I2C_TXFIFO_WM_INT_RAW bit will be valid.
+ */
+#define I2C_TXFIFO_WM_THRHD    0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
+#define I2C_TXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_S  5
+/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures to enable APB nonfifo access.
+ */
+#define I2C_NONFIFO_EN    (BIT(10))
+#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
+#define I2C_NONFIFO_EN_V  0x00000001U
+#define I2C_NONFIFO_EN_S  10
+/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures the slave to enable dual address mode. When this mode is enabled, the
+ *  byte received after the I2C address byte represents the offset address in the I2C
+ *  Slave RAM.
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M  (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S)
+#define I2C_FIFO_ADDR_CFG_EN_V  0x00000001U
+#define I2C_FIFO_ADDR_CFG_EN_S  11
+/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
+ *  Configures to reset RXFIFO.
+ *  0: No effect
+ *  1: Reset
+ */
+#define I2C_RX_FIFO_RST    (BIT(12))
+#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
+#define I2C_RX_FIFO_RST_V  0x00000001U
+#define I2C_RX_FIFO_RST_S  12
+/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
+ *  Configures to reset TXFIFO.
+ *  0: No effect
+ *  1: Reset
+ */
+#define I2C_TX_FIFO_RST    (BIT(13))
+#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
+#define I2C_TX_FIFO_RST_V  0x00000001U
+#define I2C_TX_FIFO_RST_S  13
+/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
+ *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
+ *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_FIFO_PRT_EN    (BIT(14))
+#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
+#define I2C_FIFO_PRT_EN_V  0x00000001U
+#define I2C_FIFO_PRT_EN_S  14
+
+/** I2C_DATA_REG register
+ *  Rx FIFO read data
+ */
+#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1c)
+/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
+ *  Represents the value of RXFIFO read data.
+ */
+#define I2C_FIFO_RDATA    0x000000FFU
+#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
+#define I2C_FIFO_RDATA_V  0x000000FFU
+#define I2C_FIFO_RDATA_S  0
+
+/** I2C_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20)
+/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
+#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
+ *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
+#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_RAW    (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
+#define I2C_END_DETECT_INT_RAW_V  0x00000001U
+#define I2C_END_DETECT_INT_RAW_S  3
+/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
+ *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
+ *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_RAW    (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
+#define I2C_TIME_OUT_INT_RAW_V  0x00000001U
+#define I2C_TIME_OUT_INT_RAW_S  8
+/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
+ *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_RAW    (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
+#define I2C_TRANS_START_INT_RAW_V  0x00000001U
+#define I2C_TRANS_START_INT_RAW_S  9
+/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_RAW    (BIT(10))
+#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
+#define I2C_NACK_INT_RAW_V  0x00000001U
+#define I2C_NACK_INT_RAW_S  10
+/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
+ *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
+ *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
+#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
+ *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
+ *  The raw interrupt status of I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_RAW    (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
+#define I2C_DET_START_INT_RAW_V  0x00000001U
+#define I2C_DET_START_INT_RAW_S  15
+/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_M  (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S)
+#define I2C_SLAVE_STRETCH_INT_RAW_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_RAW_S  16
+/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0;
+ *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
+#define I2C_GENERAL_CALL_INT_RAW_M  (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S)
+#define I2C_GENERAL_CALL_INT_RAW_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_RAW_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M  (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S  18
+
+/** I2C_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24)
+/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
+#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
+#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_CLR    (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
+#define I2C_END_DETECT_INT_CLR_V  0x00000001U
+#define I2C_END_DETECT_INT_CLR_S  3
+/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_CLR    (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
+#define I2C_TIME_OUT_INT_CLR_V  0x00000001U
+#define I2C_TIME_OUT_INT_CLR_S  8
+/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_CLR    (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
+#define I2C_TRANS_START_INT_CLR_V  0x00000001U
+#define I2C_TRANS_START_INT_CLR_S  9
+/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_CLR    (BIT(10))
+#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
+#define I2C_NACK_INT_CLR_V  0x00000001U
+#define I2C_NACK_INT_CLR_S  10
+/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
+#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Write 1 to clear I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_CLR    (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
+#define I2C_DET_START_INT_CLR_V  0x00000001U
+#define I2C_DET_START_INT_CLR_S  15
+/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_M  (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S)
+#define I2C_SLAVE_STRETCH_INT_CLR_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_CLR_S  16
+/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
+#define I2C_GENERAL_CALL_INT_CLR_M  (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S)
+#define I2C_GENERAL_CALL_INT_CLR_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_CLR_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M  (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S  18
+
+/** I2C_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28)
+/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
+#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
+#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ENA    (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
+#define I2C_END_DETECT_INT_ENA_V  0x00000001U
+#define I2C_END_DETECT_INT_ENA_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ENA    (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
+#define I2C_TIME_OUT_INT_ENA_V  0x00000001U
+#define I2C_TIME_OUT_INT_ENA_S  8
+/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ENA    (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
+#define I2C_TRANS_START_INT_ENA_V  0x00000001U
+#define I2C_TRANS_START_INT_ENA_S  9
+/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ENA    (BIT(10))
+#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
+#define I2C_NACK_INT_ENA_V  0x00000001U
+#define I2C_NACK_INT_ENA_S  10
+/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
+#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  Write 1 to enable I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ENA    (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
+#define I2C_DET_START_INT_ENA_V  0x00000001U
+#define I2C_DET_START_INT_ENA_S  15
+/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_M  (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S)
+#define I2C_SLAVE_STRETCH_INT_ENA_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ENA_S  16
+/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ENA_M  (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S)
+#define I2C_GENERAL_CALL_INT_ENA_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ENA_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S  18
+
+/** I2C_INT_STATUS_REG register
+ *  Status of captured I2C communication events
+ */
+#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2c)
+/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
+#define I2C_RXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ST_S  0
+/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
+#define I2C_TXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ST_S  1
+/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
+#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ST    (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
+#define I2C_END_DETECT_INT_ST_V  0x00000001U
+#define I2C_END_DETECT_INT_ST_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ST    (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
+#define I2C_TIME_OUT_INT_ST_V  0x00000001U
+#define I2C_TIME_OUT_INT_ST_S  8
+/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ST    (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
+#define I2C_TRANS_START_INT_ST_V  0x00000001U
+#define I2C_TRANS_START_INT_ST_S  9
+/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ST    (BIT(10))
+#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
+#define I2C_NACK_INT_ST_V  0x00000001U
+#define I2C_NACK_INT_ST_S  10
+/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
+#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
+#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
+#define I2C_SCL_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked interrupt status status of I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ST    (BIT(15))
+#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
+#define I2C_DET_START_INT_ST_V  0x00000001U
+#define I2C_DET_START_INT_ST_S  15
+/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_M  (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S)
+#define I2C_SLAVE_STRETCH_INT_ST_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ST_S  16
+/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ST_M  (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S)
+#define I2C_GENERAL_CALL_INT_ST_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ST_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S  18
+
+/** I2C_SDA_HOLD_REG register
+ *  Configures the hold time after a negative SCL edge
+ */
+#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30)
+/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the time to hold the data after the falling edge of SCL.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SDA_HOLD_TIME    0x000001FFU
+#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
+#define I2C_SDA_HOLD_TIME_V  0x000001FFU
+#define I2C_SDA_HOLD_TIME_S  0
+
+/** I2C_SDA_SAMPLE_REG register
+ *  Configures the sample time after a positive SCL edge
+ */
+#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34)
+/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the time for sampling SDA.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SDA_SAMPLE_TIME    0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
+#define I2C_SDA_SAMPLE_TIME_V  0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+/** I2C_SCL_HIGH_PERIOD_REG register
+ *  Configures the high level width of SCL
+ */
+#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38)
+/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  Configures for how long SCL remains high in master mode.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_HIGH_PERIOD    0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
+#define I2C_SCL_HIGH_PERIOD_V  0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_S  0
+/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
+ *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+
+/** I2C_SCL_START_HOLD_REG register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40)
+/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+ *  a START condition.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_START_HOLD_TIME    0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
+#define I2C_SCL_START_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+/** I2C_SCL_RSTART_SETUP_REG register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44)
+/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the positive edge of SCL and the negative edge of SDA
+ *  for a RESTART condition.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+/** I2C_SCL_STOP_HOLD_REG register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48)
+/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the delay after the STOP condition.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_STOP_HOLD_TIME    0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
+#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+/** I2C_SCL_STOP_SETUP_REG register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4c)
+/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the positive edgeof SCL and the
+ *  positive edge of SDA, in I2C module clock cycles.
+ */
+#define I2C_SCL_STOP_SETUP_TIME    0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
+#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+/** I2C_FILTER_CFG_REG register
+ *  SCL and SDA filter configuration register
+ */
+#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50)
+/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+ *  input has smaller width than this register value, the I2C controller will ignore
+ *  that pulse.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_FILTER_THRES    0x0000000FU
+#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
+#define I2C_SCL_FILTER_THRES_V  0x0000000FU
+#define I2C_SCL_FILTER_THRES_S  0
+/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+ *  input has smaller width than this register value, the I2C controller will ignore
+ *  that pulse.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SDA_FILTER_THRES    0x0000000FU
+#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
+#define I2C_SDA_FILTER_THRES_V  0x0000000FU
+#define I2C_SDA_FILTER_THRES_S  4
+/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
+ *  Configures to enable the filter function for SCL.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_SCL_FILTER_EN    (BIT(8))
+#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
+#define I2C_SCL_FILTER_EN_V  0x00000001U
+#define I2C_SCL_FILTER_EN_S  8
+/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
+ *  Configures to enable the filter function for SDA.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_SDA_FILTER_EN    (BIT(9))
+#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
+#define I2C_SDA_FILTER_EN_V  0x00000001U
+#define I2C_SDA_FILTER_EN_S  9
+
+/** I2C_COMD0_REG register
+ *  I2C command register 0
+ */
+#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58)
+/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 0.
+ *  It consists of three parts:
+ *  op_code is the command
+ *  1: WRITE
+ *  2: STOP
+ *  3: READ
+ *  4: END
+ *  6: RSTART
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure  for more information.
+ *  \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}"
+ */
+#define I2C_COMMAND0    0x00003FFFU
+#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
+#define I2C_COMMAND0_V  0x00003FFFU
+#define I2C_COMMAND0_S  0
+/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 0 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND0_DONE    (BIT(31))
+#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
+#define I2C_COMMAND0_DONE_V  0x00000001U
+#define I2C_COMMAND0_DONE_S  31
+
+/** I2C_COMD1_REG register
+ *  I2C command register 1
+ */
+#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5c)
+/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 1.
+ *  See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND1    0x00003FFFU
+#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
+#define I2C_COMMAND1_V  0x00003FFFU
+#define I2C_COMMAND1_S  0
+/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 1 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND1_DONE    (BIT(31))
+#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
+#define I2C_COMMAND1_DONE_V  0x00000001U
+#define I2C_COMMAND1_DONE_S  31
+
+/** I2C_COMD2_REG register
+ *  I2C command register 2
+ */
+#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60)
+/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 2. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND2    0x00003FFFU
+#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
+#define I2C_COMMAND2_V  0x00003FFFU
+#define I2C_COMMAND2_S  0
+/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 2 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND2_DONE    (BIT(31))
+#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
+#define I2C_COMMAND2_DONE_V  0x00000001U
+#define I2C_COMMAND2_DONE_S  31
+
+/** I2C_COMD3_REG register
+ *  I2C command register 3
+ */
+#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64)
+/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 3. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND3    0x00003FFFU
+#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
+#define I2C_COMMAND3_V  0x00003FFFU
+#define I2C_COMMAND3_S  0
+/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 3 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND3_DONE    (BIT(31))
+#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
+#define I2C_COMMAND3_DONE_V  0x00000001U
+#define I2C_COMMAND3_DONE_S  31
+
+/** I2C_COMD4_REG register
+ *  I2C command register 4
+ */
+#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68)
+/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 4. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND4    0x00003FFFU
+#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
+#define I2C_COMMAND4_V  0x00003FFFU
+#define I2C_COMMAND4_S  0
+/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 4 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND4_DONE    (BIT(31))
+#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
+#define I2C_COMMAND4_DONE_V  0x00000001U
+#define I2C_COMMAND4_DONE_S  31
+
+/** I2C_COMD5_REG register
+ *  I2C command register 5
+ */
+#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6c)
+/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 5. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND5    0x00003FFFU
+#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
+#define I2C_COMMAND5_V  0x00003FFFU
+#define I2C_COMMAND5_S  0
+/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 5 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND5_DONE    (BIT(31))
+#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
+#define I2C_COMMAND5_DONE_V  0x00000001U
+#define I2C_COMMAND5_DONE_S  31
+
+/** I2C_COMD6_REG register
+ *  I2C command register 6
+ */
+#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70)
+/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 6. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND6    0x00003FFFU
+#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
+#define I2C_COMMAND6_V  0x00003FFFU
+#define I2C_COMMAND6_S  0
+/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 6 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND6_DONE    (BIT(31))
+#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
+#define I2C_COMMAND6_DONE_V  0x00000001U
+#define I2C_COMMAND6_DONE_S  31
+
+/** I2C_COMD7_REG register
+ *  I2C command register 7
+ */
+#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74)
+/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 7. See details in I2C_CMD0_REG[13:0].
+ */
+#define I2C_COMMAND7    0x00003FFFU
+#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
+#define I2C_COMMAND7_V  0x00003FFFU
+#define I2C_COMMAND7_S  0
+/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 7 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND7_DONE    (BIT(31))
+#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
+#define I2C_COMMAND7_DONE_V  0x00000001U
+#define I2C_COMMAND7_DONE_S  31
+
+/** I2C_SCL_ST_TIME_OUT_REG register
+ *  SCL status time out register
+ */
+#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78)
+/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+ *  more than 23.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
+#define I2C_SCL_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_ST_TO_I2C_S  0
+
+/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
+ *  SCL main status time out register
+ */
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7c)
+/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be
+ *  no more than 23.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
+#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_S  0
+
+/** I2C_SCL_SP_CONF_REG register
+ *  Power configuration register
+ */
+#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80)
+/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
+ *  equals to I2C_SCL_RST_SLV_NUM[4:0].
+ */
+#define I2C_SCL_RST_SLV_EN    (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
+#define I2C_SCL_RST_SLV_EN_V  0x00000001U
+#define I2C_SCL_RST_SLV_EN_S  0
+/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
+ *  Configure the pulses of SCL generated in I2C master mode.
+ *  Valid when I2C_SCL_RST_SLV_EN is 1.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_SCL_RST_SLV_NUM    0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
+#define I2C_SCL_RST_SLV_NUM_V  0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_S  1
+/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures to power down the I2C output SCL line.
+ *  0: Not power down.
+ *  1: Not work and power down.
+ *  Valid only when I2C_SCL_FORCE_OUT is 1.
+ */
+#define I2C_SCL_PD_EN    (BIT(6))
+#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
+#define I2C_SCL_PD_EN_V  0x00000001U
+#define I2C_SCL_PD_EN_S  6
+/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures to power down the I2C output SDA line.
+ *  0: Not power down.
+ *  1: Not work and power down.
+ *  Valid only when I2C_SDA_FORCE_OUT is 1.
+ */
+#define I2C_SDA_PD_EN    (BIT(7))
+#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
+#define I2C_SDA_PD_EN_V  0x00000001U
+#define I2C_SDA_PD_EN_S  7
+
+/** I2C_SCL_STRETCH_CONF_REG register
+ *  Set SCL stretch of I2C slave
+ */
+#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84)
+/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
+ *  Configures the time period to release the SCL line from stretching to avoid timing
+ *  violation. Usually it should be larger than the SDA setup time.
+ *  Measurement unit: i2c_sclk
+ */
+#define I2C_STRETCH_PROTECT_NUM    0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_M  (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S)
+#define I2C_STRETCH_PROTECT_NUM_V  0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_S  0
+/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures to enable slave SCL stretch function. The SCL output line will be
+ *  stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The
+ *  stretch cause can be seen in I2C_STRETCH_CAUSE.
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_M  (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S)
+#define I2C_SLAVE_SCL_STRETCH_EN_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_EN_S  10
+/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures to clear the I2C slave SCL stretch function.
+ *  0: No effect
+ *  1: Clear
+ */
+#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_M  (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S)
+#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
+/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures to enable the function for slave to control ACK level.
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S)
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
+/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0;
+ *  Set the ACK level when slave controlling ACK level function enables.
+ *  0: Low level
+ *  1: High level
+ */
+#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
+#define I2C_SLAVE_BYTE_ACK_LVL_M  (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S)
+#define I2C_SLAVE_BYTE_ACK_LVL_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_LVL_S  13
+
+/** I2C_DATE_REG register
+ *  Version register
+ */
+#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xf8)
+/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765248;
+ *  Version control register.
+ */
+#define I2C_DATE    0xFFFFFFFFU
+#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
+#define I2C_DATE_V  0xFFFFFFFFU
+#define I2C_DATE_S  0
+
+/** I2C_TXFIFO_START_ADDR_REG register
+ *  I2C TXFIFO base address register
+ */
+#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100)
+/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Represents the I2C txfifo first address.
+ */
+#define I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
+#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_S  0
+
+/** I2C_RXFIFO_START_ADDR_REG register
+ *  I2C RXFIFO base address register
+ */
+#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180)
+/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Represents the I2C rxfifo first address.
+ */
+#define I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
+#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i2c_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/i2c_struct.h
new file mode 100644
index 0000000000..b8c06265a1
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i2c_struct.h
@@ -0,0 +1,1095 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Timing registers */
+/** Type of scl_low_period register
+ *  Configures the low level width of the SCL Clock.
+ */
+typedef union {
+    struct {
+        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the low level width of the SCL Clock.
+         *  Measurement unit: i2c_sclk.
+         */
+        uint32_t scl_low_period:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_low_period_reg_t;
+
+/** Type of sda_hold register
+ *  Configures the hold time after a negative SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the time to hold the data after the falling edge of SCL.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_hold_reg_t;
+
+/** Type of sda_sample register
+ *  Configures the sample time after a positive SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the sample time after a positive SCL edge.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_sample_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_sample_reg_t;
+
+/** Type of scl_high_period register
+ *  Configures the high level width of SCL
+ */
+typedef union {
+    struct {
+        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures for how long SCL remains high in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_high_period:9;
+        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
+         *  Configures the SCL_FSM's waiting period for SCL high level in master mode.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_wait_high_period:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_scl_high_period_reg_t;
+
+/** Type of scl_start_hold register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+typedef union {
+    struct {
+        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+         *  a START condition.
+         *  Measurement unit: i2c_sclk.
+         */
+        uint32_t scl_start_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_start_hold_reg_t;
+
+/** Type of scl_rstart_setup register
+ *  Configures the delay between the positive edge of SCL and the negative edge of SDA
+ */
+typedef union {
+    struct {
+        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the positive edge of SCL and the negative edge of SDA
+         *  for a RESTART condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_rstart_setup_reg_t;
+
+/** Type of scl_stop_hold register
+ *  Configures the delay after the SCL clock edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the delay after the STOP condition.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_hold_reg_t;
+
+/** Type of scl_stop_setup register
+ *  Configures the delay between the SDA and SCL rising edge for a stop condition.
+ *  Measurement unit: i2c_sclk
+ */
+typedef union {
+    struct {
+        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the rising edge of SCL and the rising edge of SDA.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_setup_reg_t;
+
+/** Type of scl_st_time_out register
+ *  SCL status time out register
+ */
+typedef union {
+    struct {
+        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+         *  more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_st_time_out_reg_t;
+
+/** Type of scl_main_st_time_out register
+ *  SCL main status time out register
+ */
+typedef union {
+    struct {
+        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be
+         *  no more than 23.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_main_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_main_st_time_out_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of ctr register
+ *  Transmission setting
+ */
+typedef union {
+    struct {
+        /** sda_force_out : R/W; bitpos: [0]; default: 0;
+         *  Configures the SDA output mode
+         *  1: Direct output,
+         *
+         *  0: Open drain output.
+         */
+        uint32_t sda_force_out:1;
+        /** scl_force_out : R/W; bitpos: [1]; default: 0;
+         *  Configures the SCL output mode
+         *  1: Direct output,
+         *
+         *  0: Open drain output.
+         */
+        uint32_t scl_force_out:1;
+        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
+         *  Configures the sample mode for SDA.
+         *  1: Sample SDA data on the SCL low level.
+         *
+         *  0: Sample SDA data on the SCL high level.
+         */
+        uint32_t sample_scl_level:1;
+        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
+         *  Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has
+         *  reached the threshold.
+         */
+        uint32_t rx_full_ack_level:1;
+        /** ms_mode : R/W; bitpos: [4]; default: 0;
+         *  Configures the module as an I2C Master or Slave.
+         *  0: Slave
+         *
+         *  1: Master
+         */
+        uint32_t ms_mode:1;
+        /** trans_start : WT; bitpos: [5]; default: 0;
+         *  Configures to start sending the data in txfifo for slave.
+         *  0: No effect
+         *
+         *  1: Start
+         */
+        uint32_t trans_start:1;
+        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
+         *  Configures to control the sending order for data needing to be sent.
+         *  1: send data from the least significant bit,
+         *
+         *  0: send data from the most significant bit.
+         */
+        uint32_t tx_lsb_first:1;
+        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
+         *  Configures to control the storage order for received data.
+         *  1: receive data from the least significant bit
+         *
+         *  0: receive data from the most significant bit.
+         */
+        uint32_t rx_lsb_first:1;
+        /** clk_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to gate clock signal for registers.
+         *
+         *  0: Force clock on for registers
+         *
+         *  1: Support clock only when registers are read or written to by software.
+         */
+        uint32_t clk_en:1;
+        /** arbitration_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable I2C bus arbitration detection.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t arbitration_en:1;
+        /** fsm_rst : WT; bitpos: [10]; default: 0;
+         *  Configures to reset the SCL_FSM.
+         *  0: No effect
+         *
+         *  1: Reset
+         */
+        uint32_t fsm_rst:1;
+        /** conf_upgate : WT; bitpos: [11]; default: 0;
+         *  Configures this bit for synchronization
+         *  0: No effect
+         *
+         *  1: Synchronize
+         */
+        uint32_t conf_upgate:1;
+        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable slave to send data automatically
+         *  0: Disable
+         *
+         *  1: Enable
+         */
+        uint32_t slv_tx_auto_start_en:1;
+        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
+         *  Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.
+         *  0: Not check
+         *
+         *  1: Check
+         */
+        uint32_t addr_10bit_rw_check_en:1;
+        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
+         *  Configures to support the 7bit general call function.
+         *  0: Not support
+         *
+         *  1: Support
+         */
+        uint32_t addr_broadcasting_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_ctr_reg_t;
+
+/** Type of to register
+ *  Setting time out control for receiving data.
+ */
+typedef union {
+    struct {
+        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the timeout threshold period for SCL stucking at high or low level. The
+         *  actual period is 2^(reg_time_out_value).
+         *  Measurement unit: i2c_sclk.
+         */
+        uint32_t time_out_value:5;
+        /** time_out_en : R/W; bitpos: [5]; default: 0;
+         *  Configures to enable time out control.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t time_out_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i2c_to_reg_t;
+
+/** Type of slave_addr register
+ *  Local slave address setting
+ */
+typedef union {
+    struct {
+        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
+         *  Configure the slave address of I2C Slave.
+         */
+        uint32_t slave_addr:15;
+        uint32_t reserved_15:16;
+        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
+         *  Configures to enable the slave 10-bit addressing mode in master mode.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t addr_10bit_en:1;
+    };
+    uint32_t val;
+} i2c_slave_addr_reg_t;
+
+/** Type of fifo_conf register
+ *  FIFO configuration register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
+         *  Configures the water mark threshold of RXFIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+         *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t rxfifo_wm_thrhd:5;
+        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
+         *  Configures the water mark threshold of TXFIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+         *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t txfifo_wm_thrhd:5;
+        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable APB nonfifo access.
+         */
+        uint32_t nonfifo_en:1;
+        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
+         *  Configures to enable double addressing mode. When this mode is enabled, the byte
+         *  received after the I2C address byte represents the offset address in the I2C Slave
+         *  RAM.
+         *  0: Disable
+         *
+         *  1: Enable
+         */
+        uint32_t fifo_addr_cfg_en:1;
+        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
+         *  Configures to reset RXFIFO.
+         *  0: No effect
+         *
+         *  1: Reset
+         */
+        uint32_t rx_fifo_rst:1;
+        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
+         *  Configures to reset TXFIFO.
+         *  0: No effect
+         *
+         *  1: Reset
+         */
+        uint32_t tx_fifo_rst:1;
+        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
+         *  Configures to enable FIFO pointer in non-fifo access mode. This bit controls the
+         *  valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.
+         *  0: No effect
+         *
+         *  1: Enable
+         */
+        uint32_t fifo_prt_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_fifo_conf_reg_t;
+
+/** Type of filter_cfg register
+ *  SCL and SDA filter configuration register
+ */
+typedef union {
+    struct {
+        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_filter_thres:4;
+        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t sda_filter_thres:4;
+        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
+         *  Configures to enable the filter function for SCL.
+         */
+        uint32_t scl_filter_en:1;
+        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
+         *  Configures to enable the filter function for SDA.
+         */
+        uint32_t sda_filter_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} i2c_filter_cfg_reg_t;
+
+/** Type of scl_sp_conf register
+ *  Power configuration register
+ */
+typedef union {
+    struct {
+        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures to send out SCL pulses when I2C master is IDLE. The number of pulses
+         *  equals to reg_scl_rst_slv_num[4:0].
+         */
+        uint32_t scl_rst_slv_en:1;
+        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
+         *  Configure the pulses of SCL generated in I2C master mode.
+         *  Valid when reg_scl_rst_slv_en is 1.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t scl_rst_slv_num:5;
+        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
+         *  Configures to power down the I2C output SCL line.
+         *  0: Not power down.
+         *
+         *  1: Power down.
+         *  Valid only when reg_scl_force_out is 1.
+         */
+        uint32_t scl_pd_en:1;
+        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
+         *  Configures to power down the I2C output SDA line.
+         *  0: Not power down.
+         *
+         *  1: Power down.
+         *  Valid only when reg_sda_force_out is 1.
+         */
+        uint32_t sda_pd_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_scl_sp_conf_reg_t;
+
+/** Type of scl_stretch_conf register
+ *  Set SCL stretch of I2C slave
+ */
+typedef union {
+    struct {
+        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
+         *  Configures the time period to release the SCL line from stretching to avoid timing
+         *  violation. Usually it should be larger than the SDA setup time.
+         *  Measurement unit: i2c_sclk
+         */
+        uint32_t stretch_protect_num:10;
+        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
+         *  Configures to enable slave SCL stretch function.
+         *  0: Disable
+         *
+         *  1: Enable
+         *  The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and
+         *  stretch event happens. The stretch cause can be seen in reg_stretch_cause.
+         */
+        uint32_t slave_scl_stretch_en:1;
+        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
+         *  Configures to clear the I2C slave SCL stretch function.
+         *  0: No effect
+         *
+         *  1: Clear
+         */
+        uint32_t slave_scl_stretch_clr:1;
+        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
+         *  Configures to enable the function for slave to control ACK level.
+         *  0: Disable
+         *
+         *  1: Enable
+         */
+        uint32_t slave_byte_ack_ctl_en:1;
+        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
+         *  Set the ACK level when slave controlling ACK level function enables.
+         *  0: Low level
+         *
+         *  1: High level
+         */
+        uint32_t slave_byte_ack_lvl:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i2c_scl_stretch_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of sr register
+ *  Describe I2C work status.
+ */
+typedef union {
+    struct {
+        /** resp_rec : RO; bitpos: [0]; default: 0;
+         *  Represents the received ACK value in master mode or slave mode.
+         *  0: ACK,
+         *
+         *  1: NACK.
+         */
+        uint32_t resp_rec:1;
+        /** slave_rw : RO; bitpos: [1]; default: 0;
+         *  Represents the transfer direction in slave mode,.
+         *  1: Master reads from slave,
+         *
+         *  0: Master writes to slave.
+         */
+        uint32_t slave_rw:1;
+        uint32_t reserved_2:1;
+        /** arb_lost : RO; bitpos: [3]; default: 0;
+         *  Represents whether the I2C controller loses control of SCL line.
+         *  0: No arbitration lost
+         *
+         *  1: Arbitration lost
+         */
+        uint32_t arb_lost:1;
+        /** bus_busy : RO; bitpos: [4]; default: 0;
+         *  Represents the I2C bus state.
+         *  1: The I2C bus is busy transferring data,
+         *
+         *  0: The I2C bus is in idle state.
+         */
+        uint32_t bus_busy:1;
+        /** slave_addressed : RO; bitpos: [5]; default: 0;
+         *  Represents whether the address sent by the master is equal to the address of the
+         *  slave.
+         *  Valid only when the module is configured as an I2C Slave.
+         *  0: Not equal
+         *
+         *  1: Equal
+         */
+        uint32_t slave_addressed:1;
+        uint32_t reserved_6:2;
+        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
+         *  Represents the number of data bytes to be sent.
+         */
+        uint32_t rxfifo_cnt:6;
+        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
+         *  Represents the cause of SCL clocking stretching in slave mode.
+         *  0: Stretching SCL low when the master starts to read data.
+         *
+         *  1: Stretching SCL low when I2C TX FIFO is empty in slave mode.
+         *
+         *  2: Stretching SCL low when I2C RX FIFO is full in slave mode.
+         */
+        uint32_t stretch_cause:2;
+        uint32_t reserved_16:2;
+        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
+         *  Represents the number of data bytes received in RAM.
+         */
+        uint32_t txfifo_cnt:6;
+        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  Represents the states of the I2C module state machine.
+         *  0: Idle,
+         *
+         *  1: Address shift,
+         *
+         *  2: ACK address,
+         *
+         *  3: Rx data,
+         *
+         *  4: Tx data,
+         *
+         *  5: Send ACK,
+         *
+         *  6: Wait ACK
+         */
+        uint32_t scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  Represents the states of the state machine used to produce SCL.
+         *  0: Idle,
+         *
+         *  1: Start,
+         *
+         *  2: Negative edge,
+         *
+         *  3: Low,
+         *
+         *  4: Positive edge,
+         *
+         *  5: High,
+         *
+         *  6: Stop
+         */
+        uint32_t scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2c_sr_reg_t;
+
+/** Type of fifo_st register
+ *  FIFO status register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
+         *  Represents the offset address of the APB reading from RXFIFO
+         */
+        uint32_t rxfifo_raddr:5;
+        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
+         *  Represents the offset address of i2c module receiving data and writing to RXFIFO.
+         */
+        uint32_t rxfifo_waddr:5;
+        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
+         *  Represents the offset address of i2c module reading from TXFIFO.
+         */
+        uint32_t txfifo_raddr:5;
+        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
+         *  Represents the offset address of APB bus writing to TXFIFO.
+         */
+        uint32_t txfifo_waddr:5;
+        uint32_t reserved_20:2;
+        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
+         *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+         *  I2C slave mode.
+         */
+        uint32_t slave_rw_point:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2c_fifo_st_reg_t;
+
+/** Type of data register
+ *  Rx FIFO read data.
+ */
+typedef union {
+    struct {
+        /** fifo_rdata : HRO; bitpos: [7:0]; default: 0;
+         *  Represents the value of RXFIFO read data.
+         */
+        uint32_t fifo_rdata:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_data_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_raw:1;
+        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
+         *  The raw interrupt status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_raw:1;
+        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_raw:1;
+        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_raw:1;
+        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_raw:1;
+        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_raw:1;
+        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  The raw interrupt status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_raw:1;
+        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_raw:1;
+        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_raw:1;
+        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_raw:1;
+        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_raw:1;
+        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  The raw interrupt status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_raw:1;
+        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_raw:1;
+        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  The raw interrupt status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_raw:1;
+        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_raw:1;
+        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
+         *  The raw interrupt status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_raw:1;
+        /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_raw:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_clr:1;
+        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_clr:1;
+        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_clr:1;
+        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_clr:1;
+        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_clr:1;
+        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_clr:1;
+        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_clr:1;
+        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_clr:1;
+        /** nack_int_clr : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_clr:1;
+        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_clr:1;
+        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_clr:1;
+        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
+         *  Write 1 to clear I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_clr:1;
+        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
+         *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_clr:1;
+        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  Write 1 to clear I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_clr:1;
+        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_clr:1;
+        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
+         *  Write 1 to clear I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_clr:1;
+        /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_clr:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_ena:1;
+        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_ena:1;
+        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_ena:1;
+        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_ena:1;
+        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_ena:1;
+        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_ena:1;
+        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_ena:1;
+        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_ena:1;
+        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_ena:1;
+        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Write 1 to enable I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_ena:1;
+        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_ena:1;
+        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Write 1 to enable I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_ena:1;
+        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_ena:1;
+        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Write 1 to enable I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_ena:1;
+        /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_ena:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_ena_reg_t;
+
+/** Type of int_status register
+ *  Status of captured I2C communication events
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_st:1;
+        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_st:1;
+        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status status of the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_st:1;
+        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_st:1;
+        /** time_out_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status status of the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_st:1;
+        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status status of the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_st:1;
+        /** nack_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_st:1;
+        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_st:1;
+        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status status of I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_st:1;
+        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_st:1;
+        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_st:1;
+        /** det_start_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status status of I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_st:1;
+        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_st:1;
+        /** general_call_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_st:1;
+        /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt.
+         */
+        uint32_t slave_addr_unmatch_int_st:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_status_reg_t;
+
+
+/** Group: Command registers */
+/** Type of comd0 register
+ *  I2C command register 0~7
+ */
+typedef union {
+    struct {
+        /** command : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command. It consists of three parts:
+         *  op_code is the command,
+         *  0: RSTART,
+         *  1: WRITE,
+         *  2: READ,
+         *  3: STOP,
+         *  4: END.
+         *
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more information.
+         */
+        uint32_t command:14;
+        uint32_t reserved_14:17;
+        /** command_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command is done in I2C Master mode.
+         *  0: Not done
+         *
+         *  1: Done
+         */
+        uint32_t command_done:1;
+    };
+    uint32_t val;
+} i2c_comd_reg_t;
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35656050;
+         *  Version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} i2c_date_reg_t;
+
+
+typedef struct {
+    volatile i2c_scl_low_period_reg_t scl_low_period;
+    volatile i2c_ctr_reg_t ctr;
+    volatile i2c_sr_reg_t sr;
+    volatile i2c_to_reg_t to;
+    volatile i2c_slave_addr_reg_t slave_addr;
+    volatile i2c_fifo_st_reg_t fifo_st;
+    volatile i2c_fifo_conf_reg_t fifo_conf;
+    volatile i2c_data_reg_t data;
+    volatile i2c_int_raw_reg_t int_raw;
+    volatile i2c_int_clr_reg_t int_clr;
+    volatile i2c_int_ena_reg_t int_ena;
+    volatile i2c_int_status_reg_t int_status;
+    volatile i2c_sda_hold_reg_t sda_hold;
+    volatile i2c_sda_sample_reg_t sda_sample;
+    volatile i2c_scl_high_period_reg_t scl_high_period;
+    uint32_t reserved_03c;
+    volatile i2c_scl_start_hold_reg_t scl_start_hold;
+    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
+    volatile i2c_filter_cfg_reg_t filter_cfg;
+    uint32_t reserved_054;
+    volatile i2c_comd_reg_t command[8];
+    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
+    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
+    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
+    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
+    uint32_t reserved_088[28];
+    volatile i2c_date_reg_t date;
+    uint32_t reserved_0fc;
+    volatile uint32_t txfifo_mem[32];
+    volatile uint32_t rxfifo_mem[32];
+} i2c_dev_t;
+
+extern i2c_dev_t I2C0;
+extern i2c_dev_t I2C1;
+extern i2c_dev_t LP_I2C;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i2s_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/i2s_eco5_struct.h
new file mode 100644
index 0000000000..fac3b8b8fd
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i2s_eco5_struct.h
@@ -0,0 +1,1009 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_14:1;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t rx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:8;
+        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_rx_conf1_reg_t;
+
+/** Type of rx_pdm2pcm_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable PDM2PCM RX mode. 0: DIsable.
+         */
+        uint32_t rx_pdm2pcm_en:1;
+        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
+         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+         *  sampling rate is 128. 0: down sampling rate is 64.
+         */
+        uint32_t rx_pdm_sinc_dsr_16_en:1;
+        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
+         *  Configure PDM RX amplify number.
+         */
+        uint32_t rx_pdm2pcm_amplify_num:4;
+        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
+         *  I2S PDM RX bypass hp filter or not.
+         */
+        uint32_t rx_pdm_hp_bypass:1;
+        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_5:3;
+        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_0:3;
+    };
+    uint32_t val;
+} i2s_rx_pdm2pcm_conf_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan2_en:1;
+        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan3_en:1;
+        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan4_en:1;
+        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan5_en:1;
+        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan6_en:1;
+        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan7_en:1;
+        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan8_en:1;
+        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan9_en:1;
+        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan10_en:1;
+        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan11_en:1;
+        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan12_en:1;
+        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan13_en:1;
+        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan14_en:1;
+        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan15_en:1;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rxeof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_rxeof_num_reg_t;
+
+
+/** Group: TX Control and configuration registers */
+/** Type of tx_conf register
+ *  I2S TX configure register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset transmitter
+         */
+        uint32_t tx_reset:1;
+        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Tx AFIFO
+         */
+        uint32_t tx_fifo_reset:1;
+        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start transmitting data
+         */
+        uint32_t tx_start:1;
+        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave transmitter mode
+         */
+        uint32_t tx_slave_mod:1;
+        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+         */
+        uint32_t tx_stop_en:1;
+        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
+         *  1: The value of Left channel data is equal to the value of right channel data in
+         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+         */
+        uint32_t tx_chan_equal:1;
+        /** tx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter in mono mode
+         */
+        uint32_t tx_mono:1;
+        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+         *  value.
+         */
+        uint32_t tx_big_endian:1;
+        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t tx_update:1;
+        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+         *  channel data value is valid in I2S TX mono mode.
+         */
+        uint32_t tx_mono_fst_vld:1;
+        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
+         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t tx_pcm_conf:2;
+        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+         */
+        uint32_t tx_pcm_bypass:1;
+        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable transmitter in Phillips standard mode
+         */
+        uint32_t tx_msb_shift:1;
+        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
+         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+         *  generate pos/neg edge in master mode.
+         */
+        uint32_t tx_bck_no_dly:1;
+        /** tx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+         */
+        uint32_t tx_left_align:1;
+        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+         */
+        uint32_t tx_24_fill_en:1;
+        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+         */
+        uint32_t tx_ws_idle_pol:1;
+        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+         *  sent first.
+         */
+        uint32_t tx_bit_order:1;
+        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_tdm_en:1;
+        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_pdm_en:1;
+        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in transmitter mode.
+         */
+        uint32_t tx_bck_div_num:6;
+        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
+         *  I2S transmitter channel mode configuration bits.
+         */
+        uint32_t tx_chan_mod:3;
+        /** sig_loopback : R/W; bitpos: [30]; default: 0;
+         *  Enable signal loop back mode with transmitter module and receiver module sharing
+         *  the same WS and BCK signals.
+         */
+        uint32_t sig_loopback:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_tx_conf_reg_t;
+
+/** Type of tx_conf1 register
+ *  I2S TX configure register 1
+ */
+typedef union {
+    struct {
+        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t tx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t tx_bits_mod:5;
+        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Tx half sample bits -1.
+         */
+        uint32_t tx_half_sample_bits:8;
+        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Tx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t tx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_tx_conf1_reg_t;
+
+/** Type of tx_pcm2pdm_conf register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
+         *  I2S TX PDM OSR2 value
+         */
+        uint32_t tx_pdm_sinc_osr2:4;
+        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
+         *  I2S TX PDM prescale for sigmadelta
+         */
+        uint32_t tx_pdm_prescale:8;
+        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_hp_in_shift:2;
+        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_lp_in_shift:2;
+        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sinc_in_shift:2;
+        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sigmadelta_in_shift:2;
+        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
+         *  I2S TX PDM sigmadelta dither2 value
+         */
+        uint32_t tx_pdm_sigmadelta_dither2:1;
+        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
+         *  I2S TX PDM sigmadelta dither value
+         */
+        uint32_t tx_pdm_sigmadelta_dither:1;
+        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
+         *  I2S TX PDM dac mode enable
+         */
+        uint32_t tx_pdm_dac_2out_en:1;
+        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
+         *  I2S TX PDM dac 2channel enable
+         */
+        uint32_t tx_pdm_dac_mode_en:1;
+        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
+         *  I2S TX PDM Converter enable
+         */
+        uint32_t pcm2pdm_conv_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf1 register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
+         *  I2S TX PDM Fp
+         */
+        uint32_t tx_pdm_fp:10;
+        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
+         *  I2S TX PDM Fs
+         */
+        uint32_t tx_pdm_fs:10;
+        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_5:3;
+        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_0:3;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf1_reg_t;
+
+/** Type of tx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan0_en:1;
+        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan1_en:1;
+        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan2_en:1;
+        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan3_en:1;
+        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan4_en:1;
+        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan5_en:1;
+        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan6_en:1;
+        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan7_en:1;
+        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan8_en:1;
+        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan9_en:1;
+        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan10_en:1;
+        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan11_en:1;
+        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan12_en:1;
+        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan13_en:1;
+        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan14_en:1;
+        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan15_en:1;
+        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t tx_tdm_tot_chan_num:4;
+        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
+         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+         *  only the data of the enabled channels is sent, then this bit should be set. Clear
+         *  it when all the data stored in DMA TX buffer is for enabled channels.
+         */
+        uint32_t tx_tdm_skip_msk_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_tx_tdm_ctrl_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:2;
+        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd1_in_dm:2;
+        uint32_t reserved_6:2;
+        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
+         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd2_in_dm:2;
+        uint32_t reserved_10:2;
+        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
+         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd3_in_dm:2;
+        uint32_t reserved_14:2;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_timing_reg_t;
+
+
+/** Group: TX clock and timing registers */
+/** Type of tx_timing register
+ *  I2S TX timing control register
+ */
+typedef union {
+    struct {
+        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd_out_dm:2;
+        uint32_t reserved_2:2;
+        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd1_out_dm:2;
+        uint32_t reserved_6:10;
+        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_tx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_sigle_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} i2s_conf_sigle_data_reg_t;
+
+
+/** Group: TX status registers */
+/** Type of state register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** tx_idle : RO; bitpos: [0]; default: 1;
+         *  1: i2s_tx is idle state. 0: i2s_tx is working.
+         */
+        uint32_t tx_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_state_reg_t;
+
+
+/** Group: ETM registers */
+/** Type of etm_conf register
+ *  I2S ETM configure register
+ */
+typedef union {
+    struct {
+        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
+         *  I2S ETM send x words event. When sending word number of
+         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_tx_send_word_num:10;
+        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
+         *  I2S ETM receive x words event. When receiving word number of
+         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_rx_receive_word_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_etm_conf_reg_t;
+
+
+/** Group: Sync counter registers */
+/** Type of fifo_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx fifo counter value.
+         */
+        uint32_t tx_fifo_cnt:31;
+        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx fifo counter.
+         */
+        uint32_t tx_fifo_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_fifo_cnt_reg_t;
+
+/** Type of bck_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx bck counter value.
+         */
+        uint32_t tx_bck_cnt:31;
+        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx bck counter.
+         */
+        uint32_t tx_bck_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_bck_cnt_reg_t;
+
+
+/** Group: Clock registers */
+/** Type of clk_gate register
+ *  Clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit to enable clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_clk_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36713024;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile i2s_int_raw_reg_t int_raw;
+    volatile i2s_int_st_reg_t int_st;
+    volatile i2s_int_ena_reg_t int_ena;
+    volatile i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile i2s_rx_conf_reg_t rx_conf;
+    volatile i2s_tx_conf_reg_t tx_conf;
+    volatile i2s_rx_conf1_reg_t rx_conf1;
+    volatile i2s_tx_conf1_reg_t tx_conf1;
+    uint32_t reserved_030[4];
+    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
+    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
+    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
+    uint32_t reserved_04c;
+    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
+    volatile i2s_rx_timing_reg_t rx_timing;
+    volatile i2s_tx_timing_reg_t tx_timing;
+    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile i2s_rxeof_num_reg_t rxeof_num;
+    volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
+    volatile i2s_state_reg_t state;
+    volatile i2s_etm_conf_reg_t etm_conf;
+    volatile i2s_fifo_cnt_reg_t fifo_cnt;
+    volatile i2s_bck_cnt_reg_t bck_cnt;
+    volatile i2s_clk_gate_reg_t clk_gate;
+    volatile i2s_date_reg_t date;
+} i2s_dev_t;
+
+extern i2s_dev_t I2S0;
+extern i2s_dev_t I2S1;
+extern i2s_dev_t I2S2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i2s_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/i2s_reg.h
new file mode 100644
index 0000000000..6f6340f257
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i2s_reg.h
@@ -0,0 +1,1268 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2S_INT_RAW_REG register
+ *  I2S interrupt raw register, valid in level.
+ */
+#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
+/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_RAW    (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
+#define I2S_RX_DONE_INT_RAW_V  0x00000001U
+#define I2S_RX_DONE_INT_RAW_S  0
+/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_RAW    (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
+#define I2S_TX_DONE_INT_RAW_V  0x00000001U
+#define I2S_TX_DONE_INT_RAW_S  1
+/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_RAW    (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
+#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_RX_HUNG_INT_RAW_S  2
+/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_RAW    (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
+#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_TX_HUNG_INT_RAW_S  3
+
+/** I2S_INT_ST_REG register
+ *  I2S interrupt status register.
+ */
+#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
+/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ST    (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
+#define I2S_RX_DONE_INT_ST_V  0x00000001U
+#define I2S_RX_DONE_INT_ST_S  0
+/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ST    (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
+#define I2S_TX_DONE_INT_ST_V  0x00000001U
+#define I2S_TX_DONE_INT_ST_S  1
+/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ST    (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
+#define I2S_RX_HUNG_INT_ST_V  0x00000001U
+#define I2S_RX_HUNG_INT_ST_S  2
+/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ST    (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
+#define I2S_TX_HUNG_INT_ST_V  0x00000001U
+#define I2S_TX_HUNG_INT_ST_S  3
+
+/** I2S_INT_ENA_REG register
+ *  I2S interrupt enable register.
+ */
+#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
+/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ENA    (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
+#define I2S_RX_DONE_INT_ENA_V  0x00000001U
+#define I2S_RX_DONE_INT_ENA_S  0
+/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ENA    (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
+#define I2S_TX_DONE_INT_ENA_V  0x00000001U
+#define I2S_TX_DONE_INT_ENA_S  1
+/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ENA    (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
+#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_RX_HUNG_INT_ENA_S  2
+/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ENA    (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
+#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_TX_HUNG_INT_ENA_S  3
+
+/** I2S_INT_CLR_REG register
+ *  I2S interrupt clear register.
+ */
+#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
+/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_CLR    (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
+#define I2S_RX_DONE_INT_CLR_V  0x00000001U
+#define I2S_RX_DONE_INT_CLR_S  0
+/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_CLR    (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
+#define I2S_TX_DONE_INT_CLR_V  0x00000001U
+#define I2S_TX_DONE_INT_CLR_S  1
+/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_CLR    (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
+#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_RX_HUNG_INT_CLR_S  2
+/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_CLR    (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
+#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_TX_HUNG_INT_CLR_S  3
+
+/** I2S_RX_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
+/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset receiver
+ */
+#define I2S_RX_RESET    (BIT(0))
+#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
+#define I2S_RX_RESET_V  0x00000001U
+#define I2S_RX_RESET_S  0
+/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Rx AFIFO
+ */
+#define I2S_RX_FIFO_RESET    (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
+#define I2S_RX_FIFO_RESET_V  0x00000001U
+#define I2S_RX_FIFO_RESET_S  1
+/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start receiving data
+ */
+#define I2S_RX_START    (BIT(2))
+#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
+#define I2S_RX_START_V  0x00000001U
+#define I2S_RX_START_S  2
+/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave receiver mode
+ */
+#define I2S_RX_SLAVE_MOD    (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
+#define I2S_RX_SLAVE_MOD_V  0x00000001U
+#define I2S_RX_SLAVE_MOD_S  3
+/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+ *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+ */
+#define I2S_RX_STOP_MODE    0x00000003U
+#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
+#define I2S_RX_STOP_MODE_V  0x00000003U
+#define I2S_RX_STOP_MODE_S  4
+/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable receiver  in mono mode
+ */
+#define I2S_RX_MONO    (BIT(6))
+#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
+#define I2S_RX_MONO_V  0x00000001U
+#define I2S_RX_MONO_S  6
+/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+ */
+#define I2S_RX_BIG_ENDIAN    (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
+#define I2S_RX_BIG_ENDIAN_V  0x00000001U
+#define I2S_RX_BIG_ENDIAN_S  7
+/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_RX_UPDATE    (BIT(8))
+#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
+#define I2S_RX_UPDATE_V  0x00000001U
+#define I2S_RX_UPDATE_S  8
+/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+ *  channel data value is valid in I2S RX mono mode.
+ */
+#define I2S_RX_MONO_FST_VLD    (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
+#define I2S_RX_MONO_FST_VLD_V  0x00000001U
+#define I2S_RX_MONO_FST_VLD_S  9
+/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
+ *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_RX_PCM_CONF    0x00000003U
+#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
+#define I2S_RX_PCM_CONF_V  0x00000003U
+#define I2S_RX_PCM_CONF_S  10
+/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass Compress/Decompress module for received data.
+ */
+#define I2S_RX_PCM_BYPASS    (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
+#define I2S_RX_PCM_BYPASS_V  0x00000001U
+#define I2S_RX_PCM_BYPASS_S  12
+/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable receiver in Phillips standard mode
+ */
+#define I2S_RX_MSB_SHIFT    (BIT(13))
+#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
+#define I2S_RX_MSB_SHIFT_V  0x00000001U
+#define I2S_RX_MSB_SHIFT_S  13
+/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+ */
+#define I2S_RX_LEFT_ALIGN    (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
+#define I2S_RX_LEFT_ALIGN_V  0x00000001U
+#define I2S_RX_LEFT_ALIGN_S  15
+/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+ */
+#define I2S_RX_24_FILL_EN    (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
+#define I2S_RX_24_FILL_EN_V  0x00000001U
+#define I2S_RX_24_FILL_EN_S  16
+/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+ *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+ */
+#define I2S_RX_WS_IDLE_POL    (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
+#define I2S_RX_WS_IDLE_POL_V  0x00000001U
+#define I2S_RX_WS_IDLE_POL_S  17
+/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+ *  is received first.
+ */
+#define I2S_RX_BIT_ORDER    (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
+#define I2S_RX_BIT_ORDER_V  0x00000001U
+#define I2S_RX_BIT_ORDER_S  18
+/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_TDM_EN    (BIT(19))
+#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
+#define I2S_RX_TDM_EN_V  0x00000001U
+#define I2S_RX_TDM_EN_S  19
+/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_PDM_EN    (BIT(20))
+#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
+#define I2S_RX_PDM_EN_V  0x00000001U
+#define I2S_RX_PDM_EN_S  20
+/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in receiver mode.
+ */
+#define I2S_RX_BCK_DIV_NUM    0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
+#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_S  21
+
+/** I2S_TX_CONF_REG register
+ *  I2S TX configure register
+ */
+#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
+/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset transmitter
+ */
+#define I2S_TX_RESET    (BIT(0))
+#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
+#define I2S_TX_RESET_V  0x00000001U
+#define I2S_TX_RESET_S  0
+/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Tx AFIFO
+ */
+#define I2S_TX_FIFO_RESET    (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
+#define I2S_TX_FIFO_RESET_V  0x00000001U
+#define I2S_TX_FIFO_RESET_S  1
+/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start transmitting data
+ */
+#define I2S_TX_START    (BIT(2))
+#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
+#define I2S_TX_START_V  0x00000001U
+#define I2S_TX_START_S  2
+/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave transmitter mode
+ */
+#define I2S_TX_SLAVE_MOD    (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
+#define I2S_TX_SLAVE_MOD_V  0x00000001U
+#define I2S_TX_SLAVE_MOD_S  3
+/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+ */
+#define I2S_TX_STOP_EN    (BIT(4))
+#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
+#define I2S_TX_STOP_EN_V  0x00000001U
+#define I2S_TX_STOP_EN_S  4
+/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
+ *  1: The value of Left channel data is equal to the value of right channel data in
+ *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+ *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+ */
+#define I2S_TX_CHAN_EQUAL    (BIT(5))
+#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
+#define I2S_TX_CHAN_EQUAL_V  0x00000001U
+#define I2S_TX_CHAN_EQUAL_S  5
+/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter in mono mode
+ */
+#define I2S_TX_MONO    (BIT(6))
+#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
+#define I2S_TX_MONO_V  0x00000001U
+#define I2S_TX_MONO_S  6
+/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+ *  value.
+ */
+#define I2S_TX_BIG_ENDIAN    (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
+#define I2S_TX_BIG_ENDIAN_V  0x00000001U
+#define I2S_TX_BIG_ENDIAN_S  7
+/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_TX_UPDATE    (BIT(8))
+#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
+#define I2S_TX_UPDATE_V  0x00000001U
+#define I2S_TX_UPDATE_S  8
+/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+ *  channel data value is valid in I2S TX mono mode.
+ */
+#define I2S_TX_MONO_FST_VLD    (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
+#define I2S_TX_MONO_FST_VLD_V  0x00000001U
+#define I2S_TX_MONO_FST_VLD_S  9
+/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
+ *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_TX_PCM_CONF    0x00000003U
+#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
+#define I2S_TX_PCM_CONF_V  0x00000003U
+#define I2S_TX_PCM_CONF_S  10
+/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+ */
+#define I2S_TX_PCM_BYPASS    (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
+#define I2S_TX_PCM_BYPASS_V  0x00000001U
+#define I2S_TX_PCM_BYPASS_S  12
+/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable transmitter in Phillips standard mode
+ */
+#define I2S_TX_MSB_SHIFT    (BIT(13))
+#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
+#define I2S_TX_MSB_SHIFT_V  0x00000001U
+#define I2S_TX_MSB_SHIFT_S  13
+/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
+ *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+ *  generate pos/neg edge in master mode.
+ */
+#define I2S_TX_BCK_NO_DLY    (BIT(14))
+#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
+#define I2S_TX_BCK_NO_DLY_V  0x00000001U
+#define I2S_TX_BCK_NO_DLY_S  14
+/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+ */
+#define I2S_TX_LEFT_ALIGN    (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
+#define I2S_TX_LEFT_ALIGN_V  0x00000001U
+#define I2S_TX_LEFT_ALIGN_S  15
+/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+ */
+#define I2S_TX_24_FILL_EN    (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
+#define I2S_TX_24_FILL_EN_V  0x00000001U
+#define I2S_TX_24_FILL_EN_S  16
+/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+ *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+ */
+#define I2S_TX_WS_IDLE_POL    (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
+#define I2S_TX_WS_IDLE_POL_V  0x00000001U
+#define I2S_TX_WS_IDLE_POL_S  17
+/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+ *  sent first.
+ */
+#define I2S_TX_BIT_ORDER    (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
+#define I2S_TX_BIT_ORDER_V  0x00000001U
+#define I2S_TX_BIT_ORDER_S  18
+/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_TDM_EN    (BIT(19))
+#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
+#define I2S_TX_TDM_EN_V  0x00000001U
+#define I2S_TX_TDM_EN_S  19
+/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_PDM_EN    (BIT(20))
+#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
+#define I2S_TX_PDM_EN_V  0x00000001U
+#define I2S_TX_PDM_EN_S  20
+/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in transmitter mode.
+ */
+#define I2S_TX_BCK_DIV_NUM    0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
+#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_S  21
+/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
+ *  I2S transmitter channel mode configuration bits.
+ */
+#define I2S_TX_CHAN_MOD    0x00000007U
+#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
+#define I2S_TX_CHAN_MOD_V  0x00000007U
+#define I2S_TX_CHAN_MOD_S  27
+/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
+ *  Enable signal loop back mode with transmitter module and receiver module sharing
+ *  the same WS and BCK signals.
+ */
+#define I2S_SIG_LOOPBACK    (BIT(30))
+#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
+#define I2S_SIG_LOOPBACK_V  0x00000001U
+#define I2S_SIG_LOOPBACK_S  30
+
+/** I2S_RX_CONF1_REG register
+ *  I2S RX configure register 1
+ */
+#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
+/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
+#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_S  0
+/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+ *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_RX_BITS_MOD    0x0000001FU
+#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
+#define I2S_RX_BITS_MOD_V  0x0000001FU
+#define I2S_RX_BITS_MOD_S  14
+/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Rx half sample bits -1.
+ */
+#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_S  19
+/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Rx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
+#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_CONF1_REG register
+ *  I2S TX configure register 1
+ */
+#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
+/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
+#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_S  0
+/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+ *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_TX_BITS_MOD    0x0000001FU
+#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
+#define I2S_TX_BITS_MOD_V  0x0000001FU
+#define I2S_TX_BITS_MOD_S  14
+/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Tx half sample bits -1.
+ */
+#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_S  19
+/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Tx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
+#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_PCM2PDM_CONF_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x40)
+/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
+ *  I2S TX PDM OSR2 value
+ */
+#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
+#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
+ *  I2S TX PDM prescale for sigmadelta
+ */
+#define I2S_TX_PDM_PRESCALE    0x000000FFU
+#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
+#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
+#define I2S_TX_PDM_PRESCALE_S  5
+/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
+ *  I2S TX PDM sigmadelta dither2 value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
+ *  I2S TX PDM sigmadelta dither value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
+ *  I2S TX PDM dac mode enable
+ */
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
+ *  I2S TX PDM dac 2channel enable
+ */
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
+ *  I2S TX PDM Converter enable
+ */
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
+#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
+#define I2S_PCM2PDM_CONV_EN_S  25
+
+/** I2S_TX_PCM2PDM_CONF1_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44)
+/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
+ *  I2S TX PDM Fp
+ */
+#define I2S_TX_PDM_FP    0x000003FFU
+#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
+#define I2S_TX_PDM_FP_V  0x000003FFU
+#define I2S_TX_PDM_FP_S  0
+/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
+ *  I2S TX PDM Fs
+ */
+#define I2S_TX_PDM_FS    0x000003FFU
+#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
+#define I2S_TX_PDM_FS_V  0x000003FFU
+#define I2S_TX_PDM_FS_S  10
+/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
+#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
+#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+
+/** I2S_RX_PDM2PCM_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_PDM2PCM_CONF_REG(i) (REG_I2S_BASE(i) + 0x48)
+/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable PDM2PCM RX mode. 0: DIsable.
+ */
+#define I2S_RX_PDM2PCM_EN    (BIT(19))
+#define I2S_RX_PDM2PCM_EN_M  (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
+#define I2S_RX_PDM2PCM_EN_V  0x00000001U
+#define I2S_RX_PDM2PCM_EN_S  19
+/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
+ *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+ *  sampling rate is 128. 0: down sampling rate is 64.
+ */
+#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(20))
+#define I2S_RX_PDM_SINC_DSR_16_EN_M  (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
+#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x00000001U
+#define I2S_RX_PDM_SINC_DSR_16_EN_S  20
+/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
+ *  Configure PDM RX amplify number.
+ */
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM    0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M  (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V  0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S  21
+/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
+ *  I2S PDM RX bypass hp filter or not.
+ */
+#define I2S_RX_PDM_HP_BYPASS    (BIT(25))
+#define I2S_RX_PDM_HP_BYPASS_M  (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
+#define I2S_RX_PDM_HP_BYPASS_V  0x00000001U
+#define I2S_RX_PDM_HP_BYPASS_S  25
+/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_RX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_RX_IIR_HP_MULT12_5_M  (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
+#define I2S_RX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_RX_IIR_HP_MULT12_5_S  26
+/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_RX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_RX_IIR_HP_MULT12_0_M  (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
+#define I2S_RX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_RX_IIR_HP_MULT12_0_S  29
+
+/** I2S_RX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
+/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
+#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
+#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
+#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
+#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
+#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
+#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
+#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
+#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+
+/** I2S_TX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
+/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
+#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN0_EN_S  0
+/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
+#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
+#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
+#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
+#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
+#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
+#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
+#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
+#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
+#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
+#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
+#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
+#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
+#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
+#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
+#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
+ *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+ *  only the data of the enabled channels is sent, then this bit should be set. Clear
+ *  it when all the data stored in DMA TX buffer is for enabled channels.
+ */
+#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+
+/** I2S_RX_TIMING_REG register
+ *  I2S RX timing control register
+ */
+#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
+/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD_IN_DM    0x00000003U
+#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
+#define I2S_RX_SD_IN_DM_V  0x00000003U
+#define I2S_RX_SD_IN_DM_S  0
+/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD1_IN_DM    0x00000003U
+#define I2S_RX_SD1_IN_DM_M  (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S)
+#define I2S_RX_SD1_IN_DM_V  0x00000003U
+#define I2S_RX_SD1_IN_DM_S  4
+/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0;
+ *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD2_IN_DM    0x00000003U
+#define I2S_RX_SD2_IN_DM_M  (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S)
+#define I2S_RX_SD2_IN_DM_V  0x00000003U
+#define I2S_RX_SD2_IN_DM_S  8
+/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0;
+ *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD3_IN_DM    0x00000003U
+#define I2S_RX_SD3_IN_DM_M  (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S)
+#define I2S_RX_SD3_IN_DM_V  0x00000003U
+#define I2S_RX_SD3_IN_DM_S  12
+/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_OUT_DM    0x00000003U
+#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
+#define I2S_RX_WS_OUT_DM_V  0x00000003U
+#define I2S_RX_WS_OUT_DM_S  16
+/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_OUT_DM    0x00000003U
+#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
+#define I2S_RX_BCK_OUT_DM_V  0x00000003U
+#define I2S_RX_BCK_OUT_DM_S  20
+/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_IN_DM    0x00000003U
+#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
+#define I2S_RX_WS_IN_DM_V  0x00000003U
+#define I2S_RX_WS_IN_DM_S  24
+/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_IN_DM    0x00000003U
+#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
+#define I2S_RX_BCK_IN_DM_V  0x00000003U
+#define I2S_RX_BCK_IN_DM_S  28
+
+/** I2S_TX_TIMING_REG register
+ *  I2S TX timing control register
+ */
+#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
+/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD_OUT_DM    0x00000003U
+#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
+#define I2S_TX_SD_OUT_DM_V  0x00000003U
+#define I2S_TX_SD_OUT_DM_S  0
+/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD1_OUT_DM    0x00000003U
+#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
+#define I2S_TX_SD1_OUT_DM_V  0x00000003U
+#define I2S_TX_SD1_OUT_DM_S  4
+/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_OUT_DM    0x00000003U
+#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
+#define I2S_TX_WS_OUT_DM_V  0x00000003U
+#define I2S_TX_WS_OUT_DM_S  16
+/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_OUT_DM    0x00000003U
+#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
+#define I2S_TX_BCK_OUT_DM_V  0x00000003U
+#define I2S_TX_BCK_OUT_DM_S  20
+/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_IN_DM    0x00000003U
+#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
+#define I2S_TX_WS_IN_DM_V  0x00000003U
+#define I2S_TX_WS_IN_DM_S  24
+/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_IN_DM    0x00000003U
+#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
+#define I2S_TX_BCK_IN_DM_V  0x00000003U
+#define I2S_TX_BCK_IN_DM_S  28
+
+/** I2S_LC_HUNG_CONF_REG register
+ *  I2S HUNG configure register.
+ */
+#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
+/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+ *  when fifo hung counter is equal to this value
+ */
+#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
+#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_S  0
+/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  The bits are used to scale tick counter threshold. The tick counter is reset when
+ *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+ */
+#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  The enable bit for FIFO timeout
+ */
+#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+
+/** I2S_RXEOF_NUM_REG register
+ *  I2S RX data number control register.
+ */
+#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
+/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
+ *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+ *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+ */
+#define I2S_RX_EOF_NUM    0x00000FFFU
+#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
+#define I2S_RX_EOF_NUM_V  0x00000FFFU
+#define I2S_RX_EOF_NUM_S  0
+
+/** I2S_CONF_SIGLE_DATA_REG register
+ *  I2S signal data register
+ */
+#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
+/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The configured constant channel data to be sent out.
+ */
+#define I2S_SINGLE_DATA    0xFFFFFFFFU
+#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
+#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
+#define I2S_SINGLE_DATA_S  0
+
+/** I2S_STATE_REG register
+ *  I2S TX status register
+ */
+#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
+/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
+ *  1: i2s_tx is idle state. 0: i2s_tx is working.
+ */
+#define I2S_TX_IDLE    (BIT(0))
+#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
+#define I2S_TX_IDLE_V  0x00000001U
+#define I2S_TX_IDLE_S  0
+
+/** I2S_ETM_CONF_REG register
+ *  I2S ETM configure register
+ */
+#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
+/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
+ *  I2S ETM send x words event. When sending word number of
+ *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
+#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_S  0
+/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
+ *  I2S ETM receive x words event. When receiving word number of
+ *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
+
+/** I2S_FIFO_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x74)
+/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx fifo counter value.
+ */
+#define I2S_TX_FIFO_CNT    0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_M  (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S)
+#define I2S_TX_FIFO_CNT_V  0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_S  0
+/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx fifo counter.
+ */
+#define I2S_TX_FIFO_CNT_RST    (BIT(31))
+#define I2S_TX_FIFO_CNT_RST_M  (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S)
+#define I2S_TX_FIFO_CNT_RST_V  0x00000001U
+#define I2S_TX_FIFO_CNT_RST_S  31
+
+/** I2S_BCK_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x78)
+/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx bck counter value.
+ */
+#define I2S_TX_BCK_CNT    0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_M  (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S)
+#define I2S_TX_BCK_CNT_V  0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_S  0
+/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx bck counter.
+ */
+#define I2S_TX_BCK_CNT_RST    (BIT(31))
+#define I2S_TX_BCK_CNT_RST_M  (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S)
+#define I2S_TX_BCK_CNT_RST_V  0x00000001U
+#define I2S_TX_BCK_CNT_RST_S  31
+
+/** I2S_CLK_GATE_REG register
+ *  Clock gate register
+ */
+#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0x7c)
+/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit to enable clock gate
+ */
+#define I2S_CLK_EN    (BIT(0))
+#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
+#define I2S_CLK_EN_V  0x00000001U
+#define I2S_CLK_EN_S  0
+
+/** I2S_DATE_REG register
+ *  Version control register
+ */
+#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x80)
+/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024;
+ *  I2S version control register
+ */
+#define I2S_DATE    0x0FFFFFFFU
+#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
+#define I2S_DATE_V  0x0FFFFFFFU
+#define I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i2s_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/i2s_struct.h
new file mode 100644
index 0000000000..727e9aae71
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i2s_struct.h
@@ -0,0 +1,1012 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_14:1;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t rx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:8;
+        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_rx_conf1_reg_t;
+
+/** Type of rx_pdm2pcm_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable PDM2PCM RX mode. 0: DIsable.
+         */
+        uint32_t rx_pdm2pcm_en:1;
+        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
+         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+         *  sampling rate is 128. 0: down sampling rate is 64.
+         */
+        uint32_t rx_pdm_sinc_dsr_16_en:1;
+        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
+         *  Configure PDM RX amplify number.
+         */
+        uint32_t rx_pdm2pcm_amplify_num:4;
+        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
+         *  I2S PDM RX bypass hp filter or not.
+         */
+        uint32_t rx_pdm_hp_bypass:1;
+        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_5:3;
+        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_0:3;
+    };
+    uint32_t val;
+} i2s_rx_pdm2pcm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
+         *  I2S TX PDM bypass hp filter or not. The option has been removed.
+         */
+        uint32_t tx_pdm_hp_bypass:1;
+        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
+         *  I2S TX PDM OSR2 value
+         */
+        uint32_t tx_pdm_sinc_osr2:4;
+        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
+         *  I2S TX PDM prescale for sigmadelta
+         */
+        uint32_t tx_pdm_prescale:8;
+        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_hp_in_shift:2;
+        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_lp_in_shift:2;
+        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sinc_in_shift:2;
+        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sigmadelta_in_shift:2;
+        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
+         *  I2S TX PDM sigmadelta dither2 value
+         */
+        uint32_t tx_pdm_sigmadelta_dither2:1;
+        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
+         *  I2S TX PDM sigmadelta dither value
+         */
+        uint32_t tx_pdm_sigmadelta_dither:1;
+        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
+         *  I2S TX PDM dac mode enable
+         */
+        uint32_t tx_pdm_dac_2out_en:1;
+        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
+         *  I2S TX PDM dac 2channel enable
+         */
+        uint32_t tx_pdm_dac_mode_en:1;
+        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
+         *  I2S TX PDM Converter enable
+         */
+        uint32_t pcm2pdm_conv_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf1 register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
+         *  I2S TX PDM Fp
+         */
+        uint32_t tx_pdm_fp:10;
+        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
+         *  I2S TX PDM Fs
+         */
+        uint32_t tx_pdm_fs:10;
+        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_5:3;
+        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_0:3;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf1_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan2_en:1;
+        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan3_en:1;
+        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan4_en:1;
+        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan5_en:1;
+        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan6_en:1;
+        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan7_en:1;
+        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan8_en:1;
+        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan9_en:1;
+        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan10_en:1;
+        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan11_en:1;
+        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan12_en:1;
+        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan13_en:1;
+        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan14_en:1;
+        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan15_en:1;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rx_eof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_rx_eof_num_reg_t;
+
+
+/** Group: TX Control and configuration registers */
+/** Type of tx_conf register
+ *  I2S TX configure register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset transmitter
+         */
+        uint32_t tx_reset:1;
+        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Tx AFIFO
+         */
+        uint32_t tx_fifo_reset:1;
+        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start transmitting data
+         */
+        uint32_t tx_start:1;
+        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave transmitter mode
+         */
+        uint32_t tx_slave_mod:1;
+        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+         */
+        uint32_t tx_stop_en:1;
+        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
+         *  1: The value of Left channel data is equal to the value of right channel data in
+         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+         */
+        uint32_t tx_chan_equal:1;
+        /** tx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter in mono mode
+         */
+        uint32_t tx_mono:1;
+        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+         *  value.
+         */
+        uint32_t tx_big_endian:1;
+        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t tx_update:1;
+        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+         *  channel data value is valid in I2S TX mono mode.
+         */
+        uint32_t tx_mono_fst_vld:1;
+        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
+         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t tx_pcm_conf:2;
+        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+         */
+        uint32_t tx_pcm_bypass:1;
+        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable transmitter in Phillips standard mode
+         */
+        uint32_t tx_msb_shift:1;
+        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
+         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+         *  generate pos/neg edge in master mode.
+         */
+        uint32_t tx_bck_no_dly:1;
+        /** tx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+         */
+        uint32_t tx_left_align:1;
+        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+         */
+        uint32_t tx_24_fill_en:1;
+        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+         */
+        uint32_t tx_ws_idle_pol:1;
+        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+         *  sent first.
+         */
+        uint32_t tx_bit_order:1;
+        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_tdm_en:1;
+        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_pdm_en:1;
+        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in transmitter mode.
+         */
+        uint32_t tx_bck_div_num:6;
+        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
+         *  I2S transmitter channel mode configuration bits.
+         */
+        uint32_t tx_chan_mod:3;
+        /** sig_loopback : R/W; bitpos: [30]; default: 0;
+         *  Enable signal loop back mode with transmitter module and receiver module sharing
+         *  the same WS and BCK signals.
+         */
+        uint32_t sig_loopback:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_tx_conf_reg_t;
+
+/** Type of tx_conf1 register
+ *  I2S TX configure register 1
+ */
+typedef union {
+    struct {
+        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t tx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t tx_bits_mod:5;
+        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Tx half sample bits -1.
+         */
+        uint32_t tx_half_sample_bits:8;
+        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Tx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t tx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_tx_conf1_reg_t;
+
+/** Type of tx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan0_en:1;
+        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan1_en:1;
+        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan2_en:1;
+        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan3_en:1;
+        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan4_en:1;
+        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan5_en:1;
+        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan6_en:1;
+        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan7_en:1;
+        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan8_en:1;
+        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan9_en:1;
+        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan10_en:1;
+        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan11_en:1;
+        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan12_en:1;
+        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan13_en:1;
+        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan14_en:1;
+        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan15_en:1;
+        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t tx_tdm_tot_chan_num:4;
+        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
+         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+         *  only the data of the enabled channels is sent, then this bit should be set. Clear
+         *  it when all the data stored in DMA TX buffer is for enabled channels.
+         */
+        uint32_t tx_tdm_skip_msk_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_tx_tdm_ctrl_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:2;
+        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd1_in_dm:2;
+        uint32_t reserved_6:2;
+        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
+         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd2_in_dm:2;
+        uint32_t reserved_10:2;
+        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
+         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd3_in_dm:2;
+        uint32_t reserved_14:2;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_timing_reg_t;
+
+
+/** Group: TX clock and timing registers */
+/** Type of tx_timing register
+ *  I2S TX timing control register
+ */
+typedef union {
+    struct {
+        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd_out_dm:2;
+        uint32_t reserved_2:2;
+        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd1_out_dm:2;
+        uint32_t reserved_6:10;
+        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_tx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_single_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} i2s_conf_single_data_reg_t;
+
+
+/** Group: TX status registers */
+/** Type of state register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** tx_idle : RO; bitpos: [0]; default: 1;
+         *  1: i2s_tx is idle state. 0: i2s_tx is working.
+         */
+        uint32_t tx_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_state_reg_t;
+
+
+/** Group: ETM registers */
+/** Type of etm_conf register
+ *  I2S ETM configure register
+ */
+typedef union {
+    struct {
+        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
+         *  I2S ETM send x words event. When sending word number of
+         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_tx_send_word_num:10;
+        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
+         *  I2S ETM receive x words event. When receiving word number of
+         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_rx_receive_word_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_etm_conf_reg_t;
+
+
+/** Group: Sync counter registers */
+/** Type of fifo_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx fifo counter value.
+         */
+        uint32_t tx_fifo_cnt:31;
+        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx fifo counter.
+         */
+        uint32_t tx_fifo_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_fifo_cnt_reg_t;
+
+/** Type of bck_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx bck counter value.
+         */
+        uint32_t tx_bck_cnt:31;
+        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx bck counter.
+         */
+        uint32_t tx_bck_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_bck_cnt_reg_t;
+
+
+/** Group: Clock registers */
+/** Type of clk_gate register
+ *  Clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit to enable clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_clk_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36713024;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile i2s_int_raw_reg_t int_raw;
+    volatile i2s_int_st_reg_t int_st;
+    volatile i2s_int_ena_reg_t int_ena;
+    volatile i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile i2s_rx_conf_reg_t rx_conf;
+    volatile i2s_tx_conf_reg_t tx_conf;
+    volatile i2s_rx_conf1_reg_t rx_conf1;
+    volatile i2s_tx_conf1_reg_t tx_conf1;
+    uint32_t reserved_030[4];
+    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
+    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
+    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
+    uint32_t reserved_04c;
+    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
+    volatile i2s_rx_timing_reg_t rx_timing;
+    volatile i2s_tx_timing_reg_t tx_timing;
+    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile i2s_rx_eof_num_reg_t rx_eof_num;
+    volatile i2s_conf_single_data_reg_t conf_single_data;
+    volatile i2s_state_reg_t state;
+    volatile i2s_etm_conf_reg_t etm_conf;
+    volatile i2s_fifo_cnt_reg_t fifo_cnt;
+    volatile i2s_bck_cnt_reg_t bck_cnt;
+    volatile i2s_clk_gate_reg_t clk_gate;
+    volatile i2s_date_reg_t date;
+} i2s_dev_t;
+
+extern i2s_dev_t I2S0;
+extern i2s_dev_t I2S1;
+extern i2s_dev_t I2S2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_eco5_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_eco5_struct.h
new file mode 100644
index 0000000000..b6d4d6431d
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_eco5_struct.h
@@ -0,0 +1,1354 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: I3C COMMAND BUF PORT REG */
+/** Type of command_buf_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_command : R/W; bitpos: [31:0]; default: 0;
+         *  Contains a Command Descriptor structure that depends on the requested transfer
+         *  type. Command Descriptor structure is used to schedule the transfers to devices on
+         *  I3C bus.
+         */
+        uint32_t reg_command:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_command_buf_port_reg_t;
+
+
+/** Group: I3C RESPONSE BUF PORT REG */
+/** Type of response_buf_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** response : RO; bitpos: [31:0]; default: 0;
+         *  The Response Buffer can be read through this register. The response status for each
+         *  Command is written into the Response Buffer by the controller if ROC (Response On
+         *  Completion) bit is set or if transfer error has occurred. The response buffer can
+         *  be read through this register.
+         */
+        uint32_t response:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_response_buf_port_reg_t;
+
+
+/** Group: I3C RX DATA PORT REG */
+/** Type of rx_data_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rx_data_port : RO; bitpos: [31:0]; default: 0;
+         *  Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is
+         *  always packed in 4-byte aligned data words.  If the length of data transfer is not
+         *  aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional
+         *  data bytes have to be ignored) at the end of the transferred data. The valid data
+         *  must be identified using the DATA_LENGTH filed in the Response Descriptor.
+         */
+        uint32_t rx_data_port:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_rx_data_port_reg_t;
+
+
+/** Group: I3C TX DATA PORT REG */
+/** Type of tx_data_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tx_data_port : R/W; bitpos: [31:0]; default: 0;
+         *  Transmit Data Port. Transmit data is mapped to the Tx-data  buffer and transmit
+         *  data is always packed in 4-byte aligned data words.  If the length of data transfer
+         *  is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the
+         *  additional data bytes have to be ignored) at the end of the transferred data. The
+         *  valid data must be identified using the DATA_LENGTH filed in the Response
+         *  Descriptor.
+         */
+        uint32_t reg_tx_data_port:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_tx_data_port_reg_t;
+
+
+/** Group: I3C IBI STATUS BUF REG */
+/** Type of ibi_status_buf register
+ *  In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is
+ *  used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)
+ */
+typedef union {
+    struct {
+        /** data_length : RO; bitpos: [7:0]; default: 0;
+         *  This field represents the length of data received along with IBI, in bytes.
+         */
+        uint32_t data_length:8;
+        /** ibi_id : RO; bitpos: [15:8]; default: 0;
+         *  IBI Identifier. The byte received after START which includes the address the R/W
+         *  bit: Device  address and R/W bit in case of Slave Interrupt or Master Request.
+         */
+        uint32_t ibi_id:8;
+        uint32_t reserved_16:12;
+        /** ibi_sts : RO; bitpos: [28]; default: 0;
+         *  IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI
+         *  Data is always packed in4-byte aligned and put to the IBI Buffer. This register
+         *  When read from, reads the data from the IBI buffer. IBI Status register when read
+         *  from, returns the data from the IBI Buffer and indicates how the controller
+         *  responded to incoming IBI(SIR, MR and HJ).
+         */
+        uint32_t ibi_sts:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i3c_mst_mem_ibi_status_buf_reg_t;
+
+
+/** Group: I3C IBI DATA BUF REG */
+/** Type of ibi_data_buf register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ibi_data : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_ibi_data_buf_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE1 LOC REG */
+/** Type of dev_addr_table1_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev1_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev1_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev1_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev1_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev1_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev1_nack_retry_cnt:2;
+        /** reg_dat_dev1_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev1_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table1_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE2 LOC REG */
+/** Type of dev_addr_table2_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev2_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev2_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev2_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev2_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev2_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev2_nack_retry_cnt:2;
+        /** reg_dat_dev2_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev2_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table2_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE3 LOC REG */
+/** Type of dev_addr_table3_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev3_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev3_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev3_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev3_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev3_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev3_nack_retry_cnt:2;
+        /** reg_dat_dev3_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev3_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table3_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE4 LOC REG */
+/** Type of dev_addr_table4_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev4_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev4_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev4_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev4_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev4_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev4_nack_retry_cnt:2;
+        /** reg_dat_dev4_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev4_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table4_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE5 LOC REG */
+/** Type of dev_addr_table5_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev5_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev5_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev5_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev5_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev5_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev5_nack_retry_cnt:2;
+        /** reg_dat_dev5_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev5_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table5_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE6 LOC REG */
+/** Type of dev_addr_table6_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev6_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev6_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev6_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev6_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev6_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev6_nack_retry_cnt:2;
+        /** reg_dat_dev6_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev6_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table6_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE7 LOC REG */
+/** Type of dev_addr_table7_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev7_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev7_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev7_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev7_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev7_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev7_nack_retry_cnt:2;
+        /** reg_dat_dev7_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev7_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table7_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE8 LOC REG */
+/** Type of dev_addr_table8_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev8_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev8_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev8_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev8_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev8_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev8_nack_retry_cnt:2;
+        /** reg_dat_dev8_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev8_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table8_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE9 LOC REG */
+/** Type of dev_addr_table9_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev9_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev9_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev9_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev9_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev9_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev9_nack_retry_cnt:2;
+        /** reg_dat_dev9_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev9_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table9_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE10 LOC REG */
+/** Type of dev_addr_table10_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev10_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev10_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev10_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev10_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev10_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev10_nack_retry_cnt:2;
+        /** reg_dat_dev10_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev10_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table10_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE11 LOC REG */
+/** Type of dev_addr_table11_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev11_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev11_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev11_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev11_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev11_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev11_nack_retry_cnt:2;
+        /** reg_dat_dev11_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev11_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table11_loc_reg_t;
+
+
+/** Group: I3C DEV ADDR TABLE12 LOC REG */
+/** Type of dev_addr_table12_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_dev12_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_dev12_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev12_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_dev12_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev12_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_dev12_nack_retry_cnt:2;
+        /** reg_dat_dev12_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_dev12_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_table12_loc_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE1 LOC1 REG */
+/** Type of dev_char_table1_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev1_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev1_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table1_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE1 LOC2 REG */
+/** Type of dev_char_table1_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev1_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev1_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table1_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE1 LOC3 REG */
+/** Type of dev_char_table1_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev1_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev1_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table1_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE1 LOC4 REG */
+/** Type of dev_char_table1_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev1_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev1_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table1_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE2 LOC1 REG */
+/** Type of dev_char_table2_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev2_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev2_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table2_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE2 LOC2 REG */
+/** Type of dev_char_table2_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev2_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev2_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table2_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE2 LOC3 REG */
+/** Type of dev_char_table2_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev2_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev2_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table2_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE2 LOC4 REG */
+/** Type of dev_char_table2_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev2_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev2_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table2_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE3 LOC1 REG */
+/** Type of dev_char_table3_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev3_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev3_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table3_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE3 LOC2 REG */
+/** Type of dev_char_table3_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev3_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev3_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table3_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE3 LOC3 REG */
+/** Type of dev_char_table3_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev3_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev3_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table3_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE3 LOC4 REG */
+/** Type of dev_char_table3_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev3_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev3_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table3_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE4 LOC1 REG */
+/** Type of dev_char_table4_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev4_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev4_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table4_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE4 LOC2 REG */
+/** Type of dev_char_table4_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev4_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev4_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table4_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE4 LOC3 REG */
+/** Type of dev_char_table4_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev4_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev4_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table4_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE4 LOC4 REG */
+/** Type of dev_char_table4_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev4_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev4_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table4_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE5 LOC1 REG */
+/** Type of dev_char_table5_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev5_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev5_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table5_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE5 LOC2 REG */
+/** Type of dev_char_table5_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev5_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev5_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table5_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE5 LOC3 REG */
+/** Type of dev_char_table5_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev5_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev5_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table5_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE5 LOC4 REG */
+/** Type of dev_char_table5_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev5_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev5_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table5_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE6 LOC1 REG */
+/** Type of dev_char_table6_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev6_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev6_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table6_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE6 LOC2 REG */
+/** Type of dev_char_table6_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev6_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev6_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table6_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE6 LOC3 REG */
+/** Type of dev_char_table6_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev6_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev6_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table6_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE6 LOC4 REG */
+/** Type of dev_char_table6_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev6_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev6_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table6_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE7 LOC1 REG */
+/** Type of dev_char_table7_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev7_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev7_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table7_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE7 LOC2 REG */
+/** Type of dev_char_table7_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev7_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev7_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table7_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE7 LOC3 REG */
+/** Type of dev_char_table7_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev7_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev7_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table7_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE7 LOC4 REG */
+/** Type of dev_char_table7_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev7_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev7_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table7_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE8 LOC1 REG */
+/** Type of dev_char_table8_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev8_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev8_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table8_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE8 LOC2 REG */
+/** Type of dev_char_table8_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev8_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev8_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table8_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE8 LOC3 REG */
+/** Type of dev_char_table8_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev8_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev8_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table8_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE8 LOC4 REG */
+/** Type of dev_char_table8_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev8_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev8_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table8_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE9 LOC1 REG */
+/** Type of dev_char_table9_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev9_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev9_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table9_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE9 LOC2 REG */
+/** Type of dev_char_table9_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev9_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev9_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table9_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE9 LOC3 REG */
+/** Type of dev_char_table9_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev9_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev9_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table9_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE9 LOC4 REG */
+/** Type of dev_char_table9_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev9_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev9_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table9_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE10 LOC1 REG */
+/** Type of dev_char_table10_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev10_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev10_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table10_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE10 LOC2 REG */
+/** Type of dev_char_table10_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev10_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev10_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table10_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE10 LOC3 REG */
+/** Type of dev_char_table10_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev10_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev10_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table10_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE10 LOC4 REG */
+/** Type of dev_char_table10_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev10_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev10_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table10_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE11 LOC1 REG */
+/** Type of dev_char_table11_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev11_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev11_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table11_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE11 LOC2 REG */
+/** Type of dev_char_table11_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev11_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev11_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table11_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE11 LOC3 REG */
+/** Type of dev_char_table11_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev11_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev11_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table11_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE11 LOC4 REG */
+/** Type of dev_char_table11_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev11_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev11_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table11_loc4_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE12 LOC1 REG */
+/** Type of dev_char_table12_loc1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev12_loc1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev12_loc1:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table12_loc1_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE12 LOC2 REG */
+/** Type of dev_char_table12_loc2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev12_loc2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev12_loc2:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table12_loc2_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE12 LOC3 REG */
+/** Type of dev_char_table12_loc3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev12_loc3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev12_loc3:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table12_loc3_reg_t;
+
+
+/** Group: I3C DEV CHAR TABLE12 LOC4 REG */
+/** Type of dev_char_table12_loc4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** dct_dev12_loc4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t dct_dev12_loc4:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_char_table12_loc4_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[2];
+    volatile i3c_mst_mem_command_buf_port_reg_t command_buf_port;
+    volatile i3c_mst_mem_response_buf_port_reg_t response_buf_port;
+    volatile i3c_mst_mem_rx_data_port_reg_t rx_data_port;
+    volatile i3c_mst_mem_tx_data_port_reg_t tx_data_port;
+    volatile i3c_mst_mem_ibi_status_buf_reg_t ibi_status_buf;
+    uint32_t reserved_01c[9];
+    volatile i3c_mst_mem_ibi_data_buf_reg_t ibi_data_buf;
+    uint32_t reserved_044[31];
+    volatile i3c_mst_mem_dev_addr_table1_loc_reg_t dev_addr_table1_loc;
+    volatile i3c_mst_mem_dev_addr_table2_loc_reg_t dev_addr_table2_loc;
+    volatile i3c_mst_mem_dev_addr_table3_loc_reg_t dev_addr_table3_loc;
+    volatile i3c_mst_mem_dev_addr_table4_loc_reg_t dev_addr_table4_loc;
+    volatile i3c_mst_mem_dev_addr_table5_loc_reg_t dev_addr_table5_loc;
+    volatile i3c_mst_mem_dev_addr_table6_loc_reg_t dev_addr_table6_loc;
+    volatile i3c_mst_mem_dev_addr_table7_loc_reg_t dev_addr_table7_loc;
+    volatile i3c_mst_mem_dev_addr_table8_loc_reg_t dev_addr_table8_loc;
+    volatile i3c_mst_mem_dev_addr_table9_loc_reg_t dev_addr_table9_loc;
+    volatile i3c_mst_mem_dev_addr_table10_loc_reg_t dev_addr_table10_loc;
+    volatile i3c_mst_mem_dev_addr_table11_loc_reg_t dev_addr_table11_loc;
+    volatile i3c_mst_mem_dev_addr_table12_loc_reg_t dev_addr_table12_loc;
+    uint32_t reserved_0f0[4];
+    volatile i3c_mst_mem_dev_char_table1_loc1_reg_t dev_char_table1_loc1;
+    volatile i3c_mst_mem_dev_char_table1_loc2_reg_t dev_char_table1_loc2;
+    volatile i3c_mst_mem_dev_char_table1_loc3_reg_t dev_char_table1_loc3;
+    volatile i3c_mst_mem_dev_char_table1_loc4_reg_t dev_char_table1_loc4;
+    volatile i3c_mst_mem_dev_char_table2_loc1_reg_t dev_char_table2_loc1;
+    volatile i3c_mst_mem_dev_char_table2_loc2_reg_t dev_char_table2_loc2;
+    volatile i3c_mst_mem_dev_char_table2_loc3_reg_t dev_char_table2_loc3;
+    volatile i3c_mst_mem_dev_char_table2_loc4_reg_t dev_char_table2_loc4;
+    volatile i3c_mst_mem_dev_char_table3_loc1_reg_t dev_char_table3_loc1;
+    volatile i3c_mst_mem_dev_char_table3_loc2_reg_t dev_char_table3_loc2;
+    volatile i3c_mst_mem_dev_char_table3_loc3_reg_t dev_char_table3_loc3;
+    volatile i3c_mst_mem_dev_char_table3_loc4_reg_t dev_char_table3_loc4;
+    volatile i3c_mst_mem_dev_char_table4_loc1_reg_t dev_char_table4_loc1;
+    volatile i3c_mst_mem_dev_char_table4_loc2_reg_t dev_char_table4_loc2;
+    volatile i3c_mst_mem_dev_char_table4_loc3_reg_t dev_char_table4_loc3;
+    volatile i3c_mst_mem_dev_char_table4_loc4_reg_t dev_char_table4_loc4;
+    volatile i3c_mst_mem_dev_char_table5_loc1_reg_t dev_char_table5_loc1;
+    volatile i3c_mst_mem_dev_char_table5_loc2_reg_t dev_char_table5_loc2;
+    volatile i3c_mst_mem_dev_char_table5_loc3_reg_t dev_char_table5_loc3;
+    volatile i3c_mst_mem_dev_char_table5_loc4_reg_t dev_char_table5_loc4;
+    volatile i3c_mst_mem_dev_char_table6_loc1_reg_t dev_char_table6_loc1;
+    volatile i3c_mst_mem_dev_char_table6_loc2_reg_t dev_char_table6_loc2;
+    volatile i3c_mst_mem_dev_char_table6_loc3_reg_t dev_char_table6_loc3;
+    volatile i3c_mst_mem_dev_char_table6_loc4_reg_t dev_char_table6_loc4;
+    volatile i3c_mst_mem_dev_char_table7_loc1_reg_t dev_char_table7_loc1;
+    volatile i3c_mst_mem_dev_char_table7_loc2_reg_t dev_char_table7_loc2;
+    volatile i3c_mst_mem_dev_char_table7_loc3_reg_t dev_char_table7_loc3;
+    volatile i3c_mst_mem_dev_char_table7_loc4_reg_t dev_char_table7_loc4;
+    volatile i3c_mst_mem_dev_char_table8_loc1_reg_t dev_char_table8_loc1;
+    volatile i3c_mst_mem_dev_char_table8_loc2_reg_t dev_char_table8_loc2;
+    volatile i3c_mst_mem_dev_char_table8_loc3_reg_t dev_char_table8_loc3;
+    volatile i3c_mst_mem_dev_char_table8_loc4_reg_t dev_char_table8_loc4;
+    volatile i3c_mst_mem_dev_char_table9_loc1_reg_t dev_char_table9_loc1;
+    volatile i3c_mst_mem_dev_char_table9_loc2_reg_t dev_char_table9_loc2;
+    volatile i3c_mst_mem_dev_char_table9_loc3_reg_t dev_char_table9_loc3;
+    volatile i3c_mst_mem_dev_char_table9_loc4_reg_t dev_char_table9_loc4;
+    volatile i3c_mst_mem_dev_char_table10_loc1_reg_t dev_char_table10_loc1;
+    volatile i3c_mst_mem_dev_char_table10_loc2_reg_t dev_char_table10_loc2;
+    volatile i3c_mst_mem_dev_char_table10_loc3_reg_t dev_char_table10_loc3;
+    volatile i3c_mst_mem_dev_char_table10_loc4_reg_t dev_char_table10_loc4;
+    volatile i3c_mst_mem_dev_char_table11_loc1_reg_t dev_char_table11_loc1;
+    volatile i3c_mst_mem_dev_char_table11_loc2_reg_t dev_char_table11_loc2;
+    volatile i3c_mst_mem_dev_char_table11_loc3_reg_t dev_char_table11_loc3;
+    volatile i3c_mst_mem_dev_char_table11_loc4_reg_t dev_char_table11_loc4;
+    volatile i3c_mst_mem_dev_char_table12_loc1_reg_t dev_char_table12_loc1;
+    volatile i3c_mst_mem_dev_char_table12_loc2_reg_t dev_char_table12_loc2;
+    volatile i3c_mst_mem_dev_char_table12_loc3_reg_t dev_char_table12_loc3;
+    volatile i3c_mst_mem_dev_char_table12_loc4_reg_t dev_char_table12_loc4;
+} i3c_mst_mem_dev_t;
+
+extern i3c_mst_mem_dev_t I3C_MST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i3c_mst_mem_dev_t) == 0x1c0, "Invalid size of i3c_mst_mem_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_reg.h
new file mode 100644
index 0000000000..4b729dde74
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_reg.h
@@ -0,0 +1,1166 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I3C_MST_MEM_COMMAND_BUF_PORT_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_COMMAND_BUF_PORT_REG (DR_REG_I3C_MST_MEM_BASE + 0x8)
+/** I3C_MST_MEM_REG_COMMAND : R/W; bitpos: [31:0]; default: 0;
+ *  Contains a Command Descriptor structure that depends on the requested transfer
+ *  type. Command Descriptor structure is used to schedule the transfers to devices on
+ *  I3C bus.
+ */
+#define I3C_MST_MEM_REG_COMMAND    0xFFFFFFFFU
+#define I3C_MST_MEM_REG_COMMAND_M  (I3C_MST_MEM_REG_COMMAND_V << I3C_MST_MEM_REG_COMMAND_S)
+#define I3C_MST_MEM_REG_COMMAND_V  0xFFFFFFFFU
+#define I3C_MST_MEM_REG_COMMAND_S  0
+
+/** I3C_MST_MEM_RESPONSE_BUF_PORT_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_RESPONSE_BUF_PORT_REG (DR_REG_I3C_MST_MEM_BASE + 0xc)
+/** I3C_MST_MEM_RESPONSE : RO; bitpos: [31:0]; default: 0;
+ *  The Response Buffer can be read through this register. The response status for each
+ *  Command is written into the Response Buffer by the controller if ROC (Response On
+ *  Completion) bit is set or if transfer error has occurred. The response buffer can
+ *  be read through this register.
+ */
+#define I3C_MST_MEM_RESPONSE    0xFFFFFFFFU
+#define I3C_MST_MEM_RESPONSE_M  (I3C_MST_MEM_RESPONSE_V << I3C_MST_MEM_RESPONSE_S)
+#define I3C_MST_MEM_RESPONSE_V  0xFFFFFFFFU
+#define I3C_MST_MEM_RESPONSE_S  0
+
+/** I3C_MST_MEM_RX_DATA_PORT_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_RX_DATA_PORT_REG (DR_REG_I3C_MST_MEM_BASE + 0x10)
+/** I3C_MST_MEM_RX_DATA_PORT : RO; bitpos: [31:0]; default: 0;
+ *  Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is
+ *  always packed in 4-byte aligned data words.  If the length of data transfer is not
+ *  aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional
+ *  data bytes have to be ignored) at the end of the transferred data. The valid data
+ *  must be identified using the DATA_LENGTH filed in the Response Descriptor.
+ */
+#define I3C_MST_MEM_RX_DATA_PORT    0xFFFFFFFFU
+#define I3C_MST_MEM_RX_DATA_PORT_M  (I3C_MST_MEM_RX_DATA_PORT_V << I3C_MST_MEM_RX_DATA_PORT_S)
+#define I3C_MST_MEM_RX_DATA_PORT_V  0xFFFFFFFFU
+#define I3C_MST_MEM_RX_DATA_PORT_S  0
+
+/** I3C_MST_MEM_TX_DATA_PORT_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_TX_DATA_PORT_REG (DR_REG_I3C_MST_MEM_BASE + 0x14)
+/** I3C_MST_MEM_REG_TX_DATA_PORT : R/W; bitpos: [31:0]; default: 0;
+ *  Transmit Data Port. Transmit data is mapped to the Tx-data  buffer and transmit
+ *  data is always packed in 4-byte aligned data words.  If the length of data transfer
+ *  is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the
+ *  additional data bytes have to be ignored) at the end of the transferred data. The
+ *  valid data must be identified using the DATA_LENGTH filed in the Response
+ *  Descriptor.
+ */
+#define I3C_MST_MEM_REG_TX_DATA_PORT    0xFFFFFFFFU
+#define I3C_MST_MEM_REG_TX_DATA_PORT_M  (I3C_MST_MEM_REG_TX_DATA_PORT_V << I3C_MST_MEM_REG_TX_DATA_PORT_S)
+#define I3C_MST_MEM_REG_TX_DATA_PORT_V  0xFFFFFFFFU
+#define I3C_MST_MEM_REG_TX_DATA_PORT_S  0
+
+/** I3C_MST_MEM_IBI_STATUS_BUF_REG register
+ *  In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is
+ *  used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)
+ */
+#define I3C_MST_MEM_IBI_STATUS_BUF_REG (DR_REG_I3C_MST_MEM_BASE + 0x18)
+/** I3C_MST_MEM_DATA_LENGTH : RO; bitpos: [7:0]; default: 0;
+ *  This field represents the length of data received along with IBI, in bytes.
+ */
+#define I3C_MST_MEM_DATA_LENGTH    0x000000FFU
+#define I3C_MST_MEM_DATA_LENGTH_M  (I3C_MST_MEM_DATA_LENGTH_V << I3C_MST_MEM_DATA_LENGTH_S)
+#define I3C_MST_MEM_DATA_LENGTH_V  0x000000FFU
+#define I3C_MST_MEM_DATA_LENGTH_S  0
+/** I3C_MST_MEM_IBI_ID : RO; bitpos: [15:8]; default: 0;
+ *  IBI Identifier. The byte received after START which includes the address the R/W
+ *  bit: Device  address and R/W bit in case of Slave Interrupt or Master Request.
+ */
+#define I3C_MST_MEM_IBI_ID    0x000000FFU
+#define I3C_MST_MEM_IBI_ID_M  (I3C_MST_MEM_IBI_ID_V << I3C_MST_MEM_IBI_ID_S)
+#define I3C_MST_MEM_IBI_ID_V  0x000000FFU
+#define I3C_MST_MEM_IBI_ID_S  8
+/** I3C_MST_MEM_IBI_STS : RO; bitpos: [28]; default: 0;
+ *  IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI
+ *  Data is always packed in4-byte aligned and put to the IBI Buffer. This register
+ *  When read from, reads the data from the IBI buffer. IBI Status register when read
+ *  from, returns the data from the IBI Buffer and indicates how the controller
+ *  responded to incoming IBI(SIR, MR and HJ).
+ */
+#define I3C_MST_MEM_IBI_STS    (BIT(28))
+#define I3C_MST_MEM_IBI_STS_M  (I3C_MST_MEM_IBI_STS_V << I3C_MST_MEM_IBI_STS_S)
+#define I3C_MST_MEM_IBI_STS_V  0x00000001U
+#define I3C_MST_MEM_IBI_STS_S  28
+
+/** I3C_MST_MEM_IBI_DATA_BUF_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_IBI_DATA_BUF_REG (DR_REG_I3C_MST_MEM_BASE + 0x40)
+/** I3C_MST_MEM_IBI_DATA : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_IBI_DATA    0xFFFFFFFFU
+#define I3C_MST_MEM_IBI_DATA_M  (I3C_MST_MEM_IBI_DATA_V << I3C_MST_MEM_IBI_DATA_S)
+#define I3C_MST_MEM_IBI_DATA_V  0xFFFFFFFFU
+#define I3C_MST_MEM_IBI_DATA_S  0
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE1_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xc0)
+/** I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV1_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV1_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV1_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV1_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV1_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV1_I2C_M  (I3C_MST_MEM_REG_DAT_DEV1_I2C_V << I3C_MST_MEM_REG_DAT_DEV1_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV1_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV1_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE2_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xc4)
+/** I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV2_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV2_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV2_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV2_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV2_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV2_I2C_M  (I3C_MST_MEM_REG_DAT_DEV2_I2C_V << I3C_MST_MEM_REG_DAT_DEV2_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV2_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV2_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE3_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xc8)
+/** I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV3_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV3_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV3_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV3_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV3_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV3_I2C_M  (I3C_MST_MEM_REG_DAT_DEV3_I2C_V << I3C_MST_MEM_REG_DAT_DEV3_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV3_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV3_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE4_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xcc)
+/** I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV4_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV4_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV4_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV4_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV4_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV4_I2C_M  (I3C_MST_MEM_REG_DAT_DEV4_I2C_V << I3C_MST_MEM_REG_DAT_DEV4_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV4_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV4_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE5_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xd0)
+/** I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV5_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV5_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV5_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV5_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV5_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV5_I2C_M  (I3C_MST_MEM_REG_DAT_DEV5_I2C_V << I3C_MST_MEM_REG_DAT_DEV5_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV5_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV5_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE6_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xd4)
+/** I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV6_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV6_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV6_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV6_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV6_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV6_I2C_M  (I3C_MST_MEM_REG_DAT_DEV6_I2C_V << I3C_MST_MEM_REG_DAT_DEV6_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV6_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV6_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE7_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xd8)
+/** I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV7_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV7_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV7_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV7_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV7_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV7_I2C_M  (I3C_MST_MEM_REG_DAT_DEV7_I2C_V << I3C_MST_MEM_REG_DAT_DEV7_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV7_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV7_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE8_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xdc)
+/** I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV8_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV8_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV8_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV8_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV8_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV8_I2C_M  (I3C_MST_MEM_REG_DAT_DEV8_I2C_V << I3C_MST_MEM_REG_DAT_DEV8_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV8_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV8_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE9_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xe0)
+/** I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV9_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV9_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV9_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV9_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV9_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV9_I2C_M  (I3C_MST_MEM_REG_DAT_DEV9_I2C_V << I3C_MST_MEM_REG_DAT_DEV9_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV9_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV9_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE10_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xe4)
+/** I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV10_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV10_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV10_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV10_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV10_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV10_I2C_M  (I3C_MST_MEM_REG_DAT_DEV10_I2C_V << I3C_MST_MEM_REG_DAT_DEV10_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV10_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV10_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE11_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xe8)
+/** I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV11_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV11_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV11_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV11_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV11_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV11_I2C_M  (I3C_MST_MEM_REG_DAT_DEV11_I2C_V << I3C_MST_MEM_REG_DAT_DEV11_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV11_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV11_I2C_S  31
+
+/** I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_ADDR_TABLE12_LOC_REG (DR_REG_I3C_MST_MEM_BASE + 0xec)
+/** I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR : R/W; bitpos: [6:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR    0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_V  0x0000007FU
+#define I3C_MST_MEM_REG_DAT_DEV12_STATIC_ADDR_S  0
+/** I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR : R/W; bitpos: [23:16]; default: 0;
+ *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+ *  parity of dynamic address.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR    0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_M  (I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_V << I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_S)
+#define I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_V  0x000000FFU
+#define I3C_MST_MEM_REG_DAT_DEV12_DYNAMIC_ADDR_S  16
+/** I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT : R/W; bitpos: [30:29]; default: 0;
+ *  This field is used to set the Device NACK Retry count for the particular device. If
+ *  the Device NACK's for the device address, the controller automatically retries the
+ *  same device until this count expires. If the Slave does not ACK for the mentioned
+ *  number of retries, then controller generates an error response and move to the Halt
+ *  state.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT    0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_M  (I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_V << I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_S)
+#define I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_V  0x00000003U
+#define I3C_MST_MEM_REG_DAT_DEV12_NACK_RETRY_CNT_S  29
+/** I3C_MST_MEM_REG_DAT_DEV12_I2C : R/W; bitpos: [31]; default: 0;
+ *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+ *  device.
+ */
+#define I3C_MST_MEM_REG_DAT_DEV12_I2C    (BIT(31))
+#define I3C_MST_MEM_REG_DAT_DEV12_I2C_M  (I3C_MST_MEM_REG_DAT_DEV12_I2C_V << I3C_MST_MEM_REG_DAT_DEV12_I2C_S)
+#define I3C_MST_MEM_REG_DAT_DEV12_I2C_V  0x00000001U
+#define I3C_MST_MEM_REG_DAT_DEV12_I2C_S  31
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE1_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE1_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x100)
+/** I3C_MST_MEM_DCT_DEV1_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV1_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC1_M  (I3C_MST_MEM_DCT_DEV1_LOC1_V << I3C_MST_MEM_DCT_DEV1_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV1_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE1_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE1_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x104)
+/** I3C_MST_MEM_DCT_DEV1_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV1_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC2_M  (I3C_MST_MEM_DCT_DEV1_LOC2_V << I3C_MST_MEM_DCT_DEV1_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV1_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE1_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE1_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x108)
+/** I3C_MST_MEM_DCT_DEV1_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV1_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC3_M  (I3C_MST_MEM_DCT_DEV1_LOC3_V << I3C_MST_MEM_DCT_DEV1_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV1_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE1_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE1_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x10c)
+/** I3C_MST_MEM_DCT_DEV1_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV1_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC4_M  (I3C_MST_MEM_DCT_DEV1_LOC4_V << I3C_MST_MEM_DCT_DEV1_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV1_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV1_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE2_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE2_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x110)
+/** I3C_MST_MEM_DCT_DEV2_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV2_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC1_M  (I3C_MST_MEM_DCT_DEV2_LOC1_V << I3C_MST_MEM_DCT_DEV2_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV2_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE2_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE2_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x114)
+/** I3C_MST_MEM_DCT_DEV2_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV2_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC2_M  (I3C_MST_MEM_DCT_DEV2_LOC2_V << I3C_MST_MEM_DCT_DEV2_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV2_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE2_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE2_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x118)
+/** I3C_MST_MEM_DCT_DEV2_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV2_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC3_M  (I3C_MST_MEM_DCT_DEV2_LOC3_V << I3C_MST_MEM_DCT_DEV2_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV2_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE2_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE2_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x11c)
+/** I3C_MST_MEM_DCT_DEV2_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV2_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC4_M  (I3C_MST_MEM_DCT_DEV2_LOC4_V << I3C_MST_MEM_DCT_DEV2_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV2_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV2_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE3_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE3_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x120)
+/** I3C_MST_MEM_DCT_DEV3_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV3_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC1_M  (I3C_MST_MEM_DCT_DEV3_LOC1_V << I3C_MST_MEM_DCT_DEV3_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV3_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE3_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE3_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x124)
+/** I3C_MST_MEM_DCT_DEV3_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV3_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC2_M  (I3C_MST_MEM_DCT_DEV3_LOC2_V << I3C_MST_MEM_DCT_DEV3_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV3_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE3_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE3_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x128)
+/** I3C_MST_MEM_DCT_DEV3_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV3_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC3_M  (I3C_MST_MEM_DCT_DEV3_LOC3_V << I3C_MST_MEM_DCT_DEV3_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV3_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE3_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE3_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x12c)
+/** I3C_MST_MEM_DCT_DEV3_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV3_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC4_M  (I3C_MST_MEM_DCT_DEV3_LOC4_V << I3C_MST_MEM_DCT_DEV3_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV3_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV3_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE4_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE4_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x130)
+/** I3C_MST_MEM_DCT_DEV4_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV4_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC1_M  (I3C_MST_MEM_DCT_DEV4_LOC1_V << I3C_MST_MEM_DCT_DEV4_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV4_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE4_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE4_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x134)
+/** I3C_MST_MEM_DCT_DEV4_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV4_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC2_M  (I3C_MST_MEM_DCT_DEV4_LOC2_V << I3C_MST_MEM_DCT_DEV4_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV4_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE4_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE4_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x138)
+/** I3C_MST_MEM_DCT_DEV4_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV4_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC3_M  (I3C_MST_MEM_DCT_DEV4_LOC3_V << I3C_MST_MEM_DCT_DEV4_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV4_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE4_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE4_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x13c)
+/** I3C_MST_MEM_DCT_DEV4_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV4_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC4_M  (I3C_MST_MEM_DCT_DEV4_LOC4_V << I3C_MST_MEM_DCT_DEV4_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV4_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV4_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE5_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE5_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x140)
+/** I3C_MST_MEM_DCT_DEV5_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV5_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC1_M  (I3C_MST_MEM_DCT_DEV5_LOC1_V << I3C_MST_MEM_DCT_DEV5_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV5_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE5_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE5_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x144)
+/** I3C_MST_MEM_DCT_DEV5_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV5_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC2_M  (I3C_MST_MEM_DCT_DEV5_LOC2_V << I3C_MST_MEM_DCT_DEV5_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV5_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE5_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE5_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x148)
+/** I3C_MST_MEM_DCT_DEV5_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV5_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC3_M  (I3C_MST_MEM_DCT_DEV5_LOC3_V << I3C_MST_MEM_DCT_DEV5_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV5_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE5_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE5_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x14c)
+/** I3C_MST_MEM_DCT_DEV5_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV5_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC4_M  (I3C_MST_MEM_DCT_DEV5_LOC4_V << I3C_MST_MEM_DCT_DEV5_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV5_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV5_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE6_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE6_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x150)
+/** I3C_MST_MEM_DCT_DEV6_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV6_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC1_M  (I3C_MST_MEM_DCT_DEV6_LOC1_V << I3C_MST_MEM_DCT_DEV6_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV6_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE6_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE6_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x154)
+/** I3C_MST_MEM_DCT_DEV6_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV6_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC2_M  (I3C_MST_MEM_DCT_DEV6_LOC2_V << I3C_MST_MEM_DCT_DEV6_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV6_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE6_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE6_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x158)
+/** I3C_MST_MEM_DCT_DEV6_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV6_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC3_M  (I3C_MST_MEM_DCT_DEV6_LOC3_V << I3C_MST_MEM_DCT_DEV6_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV6_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE6_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE6_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x15c)
+/** I3C_MST_MEM_DCT_DEV6_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV6_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC4_M  (I3C_MST_MEM_DCT_DEV6_LOC4_V << I3C_MST_MEM_DCT_DEV6_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV6_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV6_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE7_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE7_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x160)
+/** I3C_MST_MEM_DCT_DEV7_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV7_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC1_M  (I3C_MST_MEM_DCT_DEV7_LOC1_V << I3C_MST_MEM_DCT_DEV7_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV7_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE7_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE7_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x164)
+/** I3C_MST_MEM_DCT_DEV7_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV7_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC2_M  (I3C_MST_MEM_DCT_DEV7_LOC2_V << I3C_MST_MEM_DCT_DEV7_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV7_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE7_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE7_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x168)
+/** I3C_MST_MEM_DCT_DEV7_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV7_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC3_M  (I3C_MST_MEM_DCT_DEV7_LOC3_V << I3C_MST_MEM_DCT_DEV7_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV7_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE7_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE7_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x16c)
+/** I3C_MST_MEM_DCT_DEV7_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV7_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC4_M  (I3C_MST_MEM_DCT_DEV7_LOC4_V << I3C_MST_MEM_DCT_DEV7_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV7_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV7_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE8_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE8_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x170)
+/** I3C_MST_MEM_DCT_DEV8_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV8_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC1_M  (I3C_MST_MEM_DCT_DEV8_LOC1_V << I3C_MST_MEM_DCT_DEV8_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV8_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE8_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE8_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x174)
+/** I3C_MST_MEM_DCT_DEV8_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV8_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC2_M  (I3C_MST_MEM_DCT_DEV8_LOC2_V << I3C_MST_MEM_DCT_DEV8_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV8_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE8_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE8_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x178)
+/** I3C_MST_MEM_DCT_DEV8_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV8_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC3_M  (I3C_MST_MEM_DCT_DEV8_LOC3_V << I3C_MST_MEM_DCT_DEV8_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV8_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE8_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE8_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x17c)
+/** I3C_MST_MEM_DCT_DEV8_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV8_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC4_M  (I3C_MST_MEM_DCT_DEV8_LOC4_V << I3C_MST_MEM_DCT_DEV8_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV8_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV8_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE9_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE9_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x180)
+/** I3C_MST_MEM_DCT_DEV9_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV9_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC1_M  (I3C_MST_MEM_DCT_DEV9_LOC1_V << I3C_MST_MEM_DCT_DEV9_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV9_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE9_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE9_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x184)
+/** I3C_MST_MEM_DCT_DEV9_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV9_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC2_M  (I3C_MST_MEM_DCT_DEV9_LOC2_V << I3C_MST_MEM_DCT_DEV9_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV9_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE9_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE9_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x188)
+/** I3C_MST_MEM_DCT_DEV9_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV9_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC3_M  (I3C_MST_MEM_DCT_DEV9_LOC3_V << I3C_MST_MEM_DCT_DEV9_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV9_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE9_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE9_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x18c)
+/** I3C_MST_MEM_DCT_DEV9_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV9_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC4_M  (I3C_MST_MEM_DCT_DEV9_LOC4_V << I3C_MST_MEM_DCT_DEV9_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV9_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV9_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE10_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE10_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x190)
+/** I3C_MST_MEM_DCT_DEV10_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV10_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC1_M  (I3C_MST_MEM_DCT_DEV10_LOC1_V << I3C_MST_MEM_DCT_DEV10_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV10_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE10_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE10_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x194)
+/** I3C_MST_MEM_DCT_DEV10_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV10_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC2_M  (I3C_MST_MEM_DCT_DEV10_LOC2_V << I3C_MST_MEM_DCT_DEV10_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV10_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE10_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE10_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x198)
+/** I3C_MST_MEM_DCT_DEV10_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV10_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC3_M  (I3C_MST_MEM_DCT_DEV10_LOC3_V << I3C_MST_MEM_DCT_DEV10_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV10_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE10_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE10_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x19c)
+/** I3C_MST_MEM_DCT_DEV10_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV10_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC4_M  (I3C_MST_MEM_DCT_DEV10_LOC4_V << I3C_MST_MEM_DCT_DEV10_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV10_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV10_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE11_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE11_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x1a0)
+/** I3C_MST_MEM_DCT_DEV11_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV11_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC1_M  (I3C_MST_MEM_DCT_DEV11_LOC1_V << I3C_MST_MEM_DCT_DEV11_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV11_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE11_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE11_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x1a4)
+/** I3C_MST_MEM_DCT_DEV11_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV11_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC2_M  (I3C_MST_MEM_DCT_DEV11_LOC2_V << I3C_MST_MEM_DCT_DEV11_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV11_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE11_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE11_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x1a8)
+/** I3C_MST_MEM_DCT_DEV11_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV11_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC3_M  (I3C_MST_MEM_DCT_DEV11_LOC3_V << I3C_MST_MEM_DCT_DEV11_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV11_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE11_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE11_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x1ac)
+/** I3C_MST_MEM_DCT_DEV11_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV11_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC4_M  (I3C_MST_MEM_DCT_DEV11_LOC4_V << I3C_MST_MEM_DCT_DEV11_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV11_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV11_LOC4_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE12_LOC1_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE12_LOC1_REG (DR_REG_I3C_MST_MEM_BASE + 0x1b0)
+/** I3C_MST_MEM_DCT_DEV12_LOC1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV12_LOC1    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC1_M  (I3C_MST_MEM_DCT_DEV12_LOC1_V << I3C_MST_MEM_DCT_DEV12_LOC1_S)
+#define I3C_MST_MEM_DCT_DEV12_LOC1_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC1_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE12_LOC2_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE12_LOC2_REG (DR_REG_I3C_MST_MEM_BASE + 0x1b4)
+/** I3C_MST_MEM_DCT_DEV12_LOC2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV12_LOC2    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC2_M  (I3C_MST_MEM_DCT_DEV12_LOC2_V << I3C_MST_MEM_DCT_DEV12_LOC2_S)
+#define I3C_MST_MEM_DCT_DEV12_LOC2_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC2_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE12_LOC3_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE12_LOC3_REG (DR_REG_I3C_MST_MEM_BASE + 0x1b8)
+/** I3C_MST_MEM_DCT_DEV12_LOC3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV12_LOC3    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC3_M  (I3C_MST_MEM_DCT_DEV12_LOC3_V << I3C_MST_MEM_DCT_DEV12_LOC3_S)
+#define I3C_MST_MEM_DCT_DEV12_LOC3_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC3_S  0
+
+/** I3C_MST_MEM_DEV_CHAR_TABLE12_LOC4_REG register
+ *  NA
+ */
+#define I3C_MST_MEM_DEV_CHAR_TABLE12_LOC4_REG (DR_REG_I3C_MST_MEM_BASE + 0x1bc)
+/** I3C_MST_MEM_DCT_DEV12_LOC4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MEM_DCT_DEV12_LOC4    0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC4_M  (I3C_MST_MEM_DCT_DEV12_LOC4_V << I3C_MST_MEM_DCT_DEV12_LOC4_S)
+#define I3C_MST_MEM_DCT_DEV12_LOC4_V  0xFFFFFFFFU
+#define I3C_MST_MEM_DCT_DEV12_LOC4_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_struct.h
new file mode 100644
index 0000000000..1d2b2bf779
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_mem_struct.h
@@ -0,0 +1,196 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: I3C COMMAND BUF PORT REG */
+/** Type of command_buf_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_command : R/W; bitpos: [31:0]; default: 0;
+         *  Contains a Command Descriptor structure that depends on the requested transfer
+         *  type. Command Descriptor structure is used to schedule the transfers to devices on
+         *  I3C bus.
+         */
+        uint32_t reg_command:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_command_buf_port_reg_t;
+
+
+/** Group: I3C RESPONSE BUF PORT REG */
+/** Type of response_buf_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** response : RO; bitpos: [31:0]; default: 0;
+         *  The Response Buffer can be read through this register. The response status for each
+         *  Command is written into the Response Buffer by the controller if ROC (Response On
+         *  Completion) bit is set or if transfer error has occurred. The response buffer can
+         *  be read through this register.
+         */
+        uint32_t response:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_response_buf_port_reg_t;
+
+
+/** Group: I3C RX DATA PORT REG */
+/** Type of rx_data_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rx_data_port : RO; bitpos: [31:0]; default: 0;
+         *  Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is
+         *  always packed in 4-byte aligned data words.  If the length of data transfer is not
+         *  aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional
+         *  data bytes have to be ignored) at the end of the transferred data. The valid data
+         *  must be identified using the DATA_LENGTH filed in the Response Descriptor.
+         */
+        uint32_t rx_data_port:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_rx_data_port_reg_t;
+
+
+/** Group: I3C TX DATA PORT REG */
+/** Type of tx_data_port register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tx_data_port : R/W; bitpos: [31:0]; default: 0;
+         *  Transmit Data Port. Transmit data is mapped to the Tx-data  buffer and transmit
+         *  data is always packed in 4-byte aligned data words.  If the length of data transfer
+         *  is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the
+         *  additional data bytes have to be ignored) at the end of the transferred data. The
+         *  valid data must be identified using the DATA_LENGTH filed in the Response
+         *  Descriptor.
+         */
+        uint32_t reg_tx_data_port:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_tx_data_port_reg_t;
+
+
+/** Group: I3C IBI STATUS BUF REG */
+/** Type of ibi_status_buf register
+ *  In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is
+ *  used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)
+ */
+typedef union {
+    struct {
+        /** data_length : RO; bitpos: [7:0]; default: 0;
+         *  This field represents the length of data received along with IBI, in bytes.
+         */
+        uint32_t data_length:8;
+        /** ibi_id : RO; bitpos: [15:8]; default: 0;
+         *  IBI Identifier. The byte received after START which includes the address the R/W
+         *  bit: Device  address and R/W bit in case of Slave Interrupt or Master Request.
+         */
+        uint32_t ibi_id:8;
+        uint32_t reserved_16:12;
+        /** ibi_sts : RO; bitpos: [28]; default: 0;
+         *  IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI
+         *  Data is always packed in4-byte aligned and put to the IBI Buffer. This register
+         *  When read from, reads the data from the IBI buffer. IBI Status register when read
+         *  from, returns the data from the IBI Buffer and indicates how the controller
+         *  responded to incoming IBI(SIR, MR and HJ).
+         */
+        uint32_t ibi_sts:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i3c_mst_mem_ibi_status_buf_reg_t;
+
+
+/** Group: I3C IBI DATA BUF REG */
+/** Type of ibi_data_buf register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** ibi_data : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data:32;
+    };
+    uint32_t val;
+} i3c_mst_mem_ibi_data_buf_reg_t;
+
+/** Group: I3C DEV ADDR TABLEn LOC REG */
+/** Type of dev_addr_tablen_loc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dat_devn_static_addr : R/W; bitpos: [6:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_devn_static_addr:7;
+        uint32_t reserved_7:9;
+        /** reg_dat_dev12_dynamic_addr : R/W; bitpos: [23:16]; default: 0;
+         *  Device Dynamic Address with parity, The MSB,bit[23], should be programmed with
+         *  parity of dynamic address.
+         */
+        uint32_t reg_dat_devn_dynamic_addr:8;
+        uint32_t reserved_24:5;
+        /** reg_dat_dev12_nack_retry_cnt : R/W; bitpos: [30:29]; default: 0;
+         *  This field is used to set the Device NACK Retry count for the particular device. If
+         *  the Device NACK's for the device address, the controller automatically retries the
+         *  same device until this count expires. If the Slave does not ACK for the mentioned
+         *  number of retries, then controller generates an error response and move to the Halt
+         *  state.
+         */
+        uint32_t reg_dat_devn_nack_retry_cnt:2;
+        /** reg_dat_dev12_i2c : R/W; bitpos: [31]; default: 0;
+         *  Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C
+         *  device.
+         */
+        uint32_t reg_dat_devn_i2c:1;
+    };
+    uint32_t val;
+} i3c_mst_mem_dev_addr_tablen_loc_reg_t;
+
+typedef struct {
+    volatile uint32_t loc1;
+    volatile uint32_t loc2;
+    volatile uint32_t loc3;
+    volatile uint32_t loc4;
+} i3c_mst_mem_dev_char_tablen_reg_t;
+
+typedef struct {
+    uint32_t reserved_000[2];
+    volatile i3c_mst_mem_command_buf_port_reg_t command_buf_port;
+    volatile i3c_mst_mem_response_buf_port_reg_t response_buf_port;
+    volatile i3c_mst_mem_rx_data_port_reg_t rx_data_port;
+    volatile i3c_mst_mem_tx_data_port_reg_t tx_data_port;
+    volatile i3c_mst_mem_ibi_status_buf_reg_t ibi_status_buf;
+    uint32_t reserved_01c[9];
+    volatile i3c_mst_mem_ibi_data_buf_reg_t ibi_data_buf;
+    uint32_t reserved_044[31];
+    volatile i3c_mst_mem_dev_addr_tablen_loc_reg_t dev_addr_table[12];
+    uint32_t reserved_0f0[4];
+    volatile i3c_mst_mem_dev_char_tablen_reg_t dev_char_table[12];
+} i3c_mst_mem_dev_t;
+
+extern i3c_mst_mem_dev_t I3C_MST_MEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i3c_mst_mem_dev_t) == 0x1c0, "Invalid size of i3c_mst_mem_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_reg.h
new file mode 100644
index 0000000000..34cef41cee
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_reg.h
@@ -0,0 +1,1353 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I3C_MST_DEVICE_CTRL_REG register
+ *  DEVICE_CTRL register controls the transfer properties and disposition of
+ *  controllers capabilities.
+ */
+#define I3C_MST_DEVICE_CTRL_REG (DR_REG_I3C_MST_BASE + 0x0)
+/** I3C_MST_REG_BA_INCLUDE : R/W; bitpos: [1]; default: 0;
+ *  This bit is used to include I3C broadcast address(0x7E) for private transfer.(If
+ *  I3C broadcast address is not include for the private transfer, In-Band Interrupts
+ *  driven from Slaves may not win address arbitration. Hence IBIs will get delayed)
+ */
+#define I3C_MST_REG_BA_INCLUDE    (BIT(1))
+#define I3C_MST_REG_BA_INCLUDE_M  (I3C_MST_REG_BA_INCLUDE_V << I3C_MST_REG_BA_INCLUDE_S)
+#define I3C_MST_REG_BA_INCLUDE_V  0x00000001U
+#define I3C_MST_REG_BA_INCLUDE_S  1
+/** I3C_MST_REG_TRANS_START : R/W; bitpos: [2]; default: 0;
+ *  Transfer Start
+ */
+#define I3C_MST_REG_TRANS_START    (BIT(2))
+#define I3C_MST_REG_TRANS_START_M  (I3C_MST_REG_TRANS_START_V << I3C_MST_REG_TRANS_START_S)
+#define I3C_MST_REG_TRANS_START_V  0x00000001U
+#define I3C_MST_REG_TRANS_START_S  2
+/** I3C_MST_REG_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_CLK_EN    (BIT(3))
+#define I3C_MST_REG_CLK_EN_M  (I3C_MST_REG_CLK_EN_V << I3C_MST_REG_CLK_EN_S)
+#define I3C_MST_REG_CLK_EN_V  0x00000001U
+#define I3C_MST_REG_CLK_EN_S  3
+/** I3C_MST_REG_IBI_RSTART_TRANS_EN : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_RSTART_TRANS_EN    (BIT(4))
+#define I3C_MST_REG_IBI_RSTART_TRANS_EN_M  (I3C_MST_REG_IBI_RSTART_TRANS_EN_V << I3C_MST_REG_IBI_RSTART_TRANS_EN_S)
+#define I3C_MST_REG_IBI_RSTART_TRANS_EN_V  0x00000001U
+#define I3C_MST_REG_IBI_RSTART_TRANS_EN_S  4
+/** I3C_MST_REG_AUTO_DIS_IBI_EN : R/W; bitpos: [5]; default: 1;
+ *  NA
+ */
+#define I3C_MST_REG_AUTO_DIS_IBI_EN    (BIT(5))
+#define I3C_MST_REG_AUTO_DIS_IBI_EN_M  (I3C_MST_REG_AUTO_DIS_IBI_EN_V << I3C_MST_REG_AUTO_DIS_IBI_EN_S)
+#define I3C_MST_REG_AUTO_DIS_IBI_EN_V  0x00000001U
+#define I3C_MST_REG_AUTO_DIS_IBI_EN_S  5
+/** I3C_MST_REG_DMA_RX_EN : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_DMA_RX_EN    (BIT(6))
+#define I3C_MST_REG_DMA_RX_EN_M  (I3C_MST_REG_DMA_RX_EN_V << I3C_MST_REG_DMA_RX_EN_S)
+#define I3C_MST_REG_DMA_RX_EN_V  0x00000001U
+#define I3C_MST_REG_DMA_RX_EN_S  6
+/** I3C_MST_REG_DMA_TX_EN : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_DMA_TX_EN    (BIT(7))
+#define I3C_MST_REG_DMA_TX_EN_M  (I3C_MST_REG_DMA_TX_EN_V << I3C_MST_REG_DMA_TX_EN_S)
+#define I3C_MST_REG_DMA_TX_EN_V  0x00000001U
+#define I3C_MST_REG_DMA_TX_EN_S  7
+/** I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN : R/W; bitpos: [8]; default: 0;
+ *  0: rx high bit first, 1: rx low bit first
+ */
+#define I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN    (BIT(8))
+#define I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_M  (I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_V << I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_S)
+#define I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_V  0x00000001U
+#define I3C_MST_REG_MULTI_SLV_SINGLE_CCC_EN_S  8
+/** I3C_MST_REG_RX_BIT_ORDER : R/W; bitpos: [9]; default: 0;
+ *  0: rx low byte fist, 1: rx high byte first
+ */
+#define I3C_MST_REG_RX_BIT_ORDER    (BIT(9))
+#define I3C_MST_REG_RX_BIT_ORDER_M  (I3C_MST_REG_RX_BIT_ORDER_V << I3C_MST_REG_RX_BIT_ORDER_S)
+#define I3C_MST_REG_RX_BIT_ORDER_V  0x00000001U
+#define I3C_MST_REG_RX_BIT_ORDER_S  9
+/** I3C_MST_REG_RX_BYTE_ORDER : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RX_BYTE_ORDER    (BIT(10))
+#define I3C_MST_REG_RX_BYTE_ORDER_M  (I3C_MST_REG_RX_BYTE_ORDER_V << I3C_MST_REG_RX_BYTE_ORDER_S)
+#define I3C_MST_REG_RX_BYTE_ORDER_V  0x00000001U
+#define I3C_MST_REG_RX_BYTE_ORDER_S  10
+/** I3C_MST_REG_SCL_PULLUP_FORCE_EN : R/W; bitpos: [11]; default: 0;
+ *  This bit is used to force scl_pullup_en
+ */
+#define I3C_MST_REG_SCL_PULLUP_FORCE_EN    (BIT(11))
+#define I3C_MST_REG_SCL_PULLUP_FORCE_EN_M  (I3C_MST_REG_SCL_PULLUP_FORCE_EN_V << I3C_MST_REG_SCL_PULLUP_FORCE_EN_S)
+#define I3C_MST_REG_SCL_PULLUP_FORCE_EN_V  0x00000001U
+#define I3C_MST_REG_SCL_PULLUP_FORCE_EN_S  11
+/** I3C_MST_REG_SCL_OE_FORCE_EN : R/W; bitpos: [12]; default: 1;
+ *  This bit is used to force scl_oe
+ */
+#define I3C_MST_REG_SCL_OE_FORCE_EN    (BIT(12))
+#define I3C_MST_REG_SCL_OE_FORCE_EN_M  (I3C_MST_REG_SCL_OE_FORCE_EN_V << I3C_MST_REG_SCL_OE_FORCE_EN_S)
+#define I3C_MST_REG_SCL_OE_FORCE_EN_V  0x00000001U
+#define I3C_MST_REG_SCL_OE_FORCE_EN_S  12
+/** I3C_MST_REG_SDA_PP_RD_PULLUP_EN : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_SDA_PP_RD_PULLUP_EN    (BIT(13))
+#define I3C_MST_REG_SDA_PP_RD_PULLUP_EN_M  (I3C_MST_REG_SDA_PP_RD_PULLUP_EN_V << I3C_MST_REG_SDA_PP_RD_PULLUP_EN_S)
+#define I3C_MST_REG_SDA_PP_RD_PULLUP_EN_V  0x00000001U
+#define I3C_MST_REG_SDA_PP_RD_PULLUP_EN_S  13
+/** I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN    (BIT(14))
+#define I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_M  (I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_V << I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_S)
+#define I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_V  0x00000001U
+#define I3C_MST_REG_SDA_RD_TBIT_HLVL_PULLUP_EN_S  14
+/** I3C_MST_REG_SDA_PP_WR_PULLUP_EN : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_SDA_PP_WR_PULLUP_EN    (BIT(15))
+#define I3C_MST_REG_SDA_PP_WR_PULLUP_EN_M  (I3C_MST_REG_SDA_PP_WR_PULLUP_EN_V << I3C_MST_REG_SDA_PP_WR_PULLUP_EN_S)
+#define I3C_MST_REG_SDA_PP_WR_PULLUP_EN_V  0x00000001U
+#define I3C_MST_REG_SDA_PP_WR_PULLUP_EN_S  15
+/** I3C_MST_REG_DATA_BYTE_CNT_UNLATCH : R/W; bitpos: [16]; default: 0;
+ *  1: read current real-time updated value  0: read latch data byte cnt value
+ */
+#define I3C_MST_REG_DATA_BYTE_CNT_UNLATCH    (BIT(16))
+#define I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_M  (I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_V << I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_S)
+#define I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_V  0x00000001U
+#define I3C_MST_REG_DATA_BYTE_CNT_UNLATCH_S  16
+/** I3C_MST_REG_MEM_CLK_FORCE_ON : R/W; bitpos: [17]; default: 0;
+ *  1: dev characteristic and address table memory clk  date force on . 0 :  clock
+ *  gating by rd/wr.
+ */
+#define I3C_MST_REG_MEM_CLK_FORCE_ON    (BIT(17))
+#define I3C_MST_REG_MEM_CLK_FORCE_ON_M  (I3C_MST_REG_MEM_CLK_FORCE_ON_V << I3C_MST_REG_MEM_CLK_FORCE_ON_S)
+#define I3C_MST_REG_MEM_CLK_FORCE_ON_V  0x00000001U
+#define I3C_MST_REG_MEM_CLK_FORCE_ON_S  17
+
+/** I3C_MST_BUFFER_THLD_CTRL_REG register
+ *  In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C
+ *  controller generates an IBI status. This field controls the number of IBI status
+ *  entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.
+ */
+#define I3C_MST_BUFFER_THLD_CTRL_REG (DR_REG_I3C_MST_BASE + 0x1c)
+/** I3C_MST_REG_CMD_BUF_EMPTY_THLD : R/W; bitpos: [3:0]; default: 1;
+ *  Command Buffer Empty Threshold Value is used to control the number of empty
+ *  locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT
+ *  interrupt.
+ */
+#define I3C_MST_REG_CMD_BUF_EMPTY_THLD    0x0000000FU
+#define I3C_MST_REG_CMD_BUF_EMPTY_THLD_M  (I3C_MST_REG_CMD_BUF_EMPTY_THLD_V << I3C_MST_REG_CMD_BUF_EMPTY_THLD_S)
+#define I3C_MST_REG_CMD_BUF_EMPTY_THLD_V  0x0000000FU
+#define I3C_MST_REG_CMD_BUF_EMPTY_THLD_S  0
+/** I3C_MST_REG_RESP_BUF_THLD : R/W; bitpos: [8:6]; default: 1;
+ *  Response Buffer Threshold Value is used to control the number of entries in the
+ *  Response Buffer that trigger the RESP_READY_STAT_INTR.
+ */
+#define I3C_MST_REG_RESP_BUF_THLD    0x00000007U
+#define I3C_MST_REG_RESP_BUF_THLD_M  (I3C_MST_REG_RESP_BUF_THLD_V << I3C_MST_REG_RESP_BUF_THLD_S)
+#define I3C_MST_REG_RESP_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_RESP_BUF_THLD_S  6
+/** I3C_MST_REG_IBI_DATA_BUF_THLD : R/W; bitpos: [14:12]; default: 1;
+ *  In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C
+ *  controller generates an IBI status. This field controls the number of IBI data
+ *  entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt.
+ */
+#define I3C_MST_REG_IBI_DATA_BUF_THLD    0x00000007U
+#define I3C_MST_REG_IBI_DATA_BUF_THLD_M  (I3C_MST_REG_IBI_DATA_BUF_THLD_V << I3C_MST_REG_IBI_DATA_BUF_THLD_S)
+#define I3C_MST_REG_IBI_DATA_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_IBI_DATA_BUF_THLD_S  12
+/** I3C_MST_REG_IBI_STATUS_BUF_THLD : R/W; bitpos: [20:18]; default: 1;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_STATUS_BUF_THLD    0x00000007U
+#define I3C_MST_REG_IBI_STATUS_BUF_THLD_M  (I3C_MST_REG_IBI_STATUS_BUF_THLD_V << I3C_MST_REG_IBI_STATUS_BUF_THLD_S)
+#define I3C_MST_REG_IBI_STATUS_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_IBI_STATUS_BUF_THLD_S  18
+
+/** I3C_MST_DATA_BUFFER_THLD_CTRL_REG register
+ *  NA
+ */
+#define I3C_MST_DATA_BUFFER_THLD_CTRL_REG (DR_REG_I3C_MST_BASE + 0x20)
+/** I3C_MST_REG_TX_DATA_BUF_THLD : R/W; bitpos: [2:0]; default: 1;
+ *  Transmit Buffer Threshold Value. This field controls the number of empty locations
+ *  in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values:
+ *  000:2  001:4  010:8  011:16  100:31, else:31
+ */
+#define I3C_MST_REG_TX_DATA_BUF_THLD    0x00000007U
+#define I3C_MST_REG_TX_DATA_BUF_THLD_M  (I3C_MST_REG_TX_DATA_BUF_THLD_V << I3C_MST_REG_TX_DATA_BUF_THLD_S)
+#define I3C_MST_REG_TX_DATA_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_TX_DATA_BUF_THLD_S  0
+/** I3C_MST_REG_RX_DATA_BUF_THLD : R/W; bitpos: [5:3]; default: 1;
+ *  Receive Buffer Threshold Value. This field controls the number of empty locations
+ *  in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2  001:4
+ *  010:8  011:16  100:31, else:31
+ */
+#define I3C_MST_REG_RX_DATA_BUF_THLD    0x00000007U
+#define I3C_MST_REG_RX_DATA_BUF_THLD_M  (I3C_MST_REG_RX_DATA_BUF_THLD_V << I3C_MST_REG_RX_DATA_BUF_THLD_S)
+#define I3C_MST_REG_RX_DATA_BUF_THLD_V  0x00000007U
+#define I3C_MST_REG_RX_DATA_BUF_THLD_S  3
+
+/** I3C_MST_IBI_NOTIFY_CTRL_REG register
+ *  NA
+ */
+#define I3C_MST_IBI_NOTIFY_CTRL_REG (DR_REG_I3C_MST_BASE + 0x24)
+/** I3C_MST_REG_NOTIFY_SIR_REJECTED : R/W; bitpos: [2]; default: 0;
+ *  Notify Rejected Slave Interrupt Request Control. This bit is used to suppress
+ *  reporting to the application about Slave Interrupt Request. 0:Suppress passing the
+ *  IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request
+ *  is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI
+ *  Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed
+ *  and auto-disabled based on the IBI_SIR_REQ_REJECT registerl.
+ */
+#define I3C_MST_REG_NOTIFY_SIR_REJECTED    (BIT(2))
+#define I3C_MST_REG_NOTIFY_SIR_REJECTED_M  (I3C_MST_REG_NOTIFY_SIR_REJECTED_V << I3C_MST_REG_NOTIFY_SIR_REJECTED_S)
+#define I3C_MST_REG_NOTIFY_SIR_REJECTED_V  0x00000001U
+#define I3C_MST_REG_NOTIFY_SIR_REJECTED_S  2
+
+/** I3C_MST_IBI_SIR_REQ_PAYLOAD_REG register
+ *  NA
+ */
+#define I3C_MST_IBI_SIR_REQ_PAYLOAD_REG (DR_REG_I3C_MST_BASE + 0x28)
+/** I3C_MST_REG_SIR_REQ_PAYLOAD : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_SIR_REQ_PAYLOAD    0xFFFFFFFFU
+#define I3C_MST_REG_SIR_REQ_PAYLOAD_M  (I3C_MST_REG_SIR_REQ_PAYLOAD_V << I3C_MST_REG_SIR_REQ_PAYLOAD_S)
+#define I3C_MST_REG_SIR_REQ_PAYLOAD_V  0xFFFFFFFFU
+#define I3C_MST_REG_SIR_REQ_PAYLOAD_S  0
+
+/** I3C_MST_IBI_SIR_REQ_REJECT_REG register
+ *  NA
+ */
+#define I3C_MST_IBI_SIR_REQ_REJECT_REG (DR_REG_I3C_MST_BASE + 0x2c)
+/** I3C_MST_REG_SIR_REQ_REJECT : R/W; bitpos: [31:0]; default: 0;
+ *  The application of controller can decide whether to send ACK or NACK for Slave
+ *  request received from any I3C device. A device specific response control bit is
+ *  provided to select the response option, Master will ACK/NACK the Master Request
+ *  based on programming of control bit, corresponding to the interrupting device.
+ *  0:ACK the SIR Request  1:NACK and send direct auto disable CCC
+ */
+#define I3C_MST_REG_SIR_REQ_REJECT    0xFFFFFFFFU
+#define I3C_MST_REG_SIR_REQ_REJECT_M  (I3C_MST_REG_SIR_REQ_REJECT_V << I3C_MST_REG_SIR_REQ_REJECT_S)
+#define I3C_MST_REG_SIR_REQ_REJECT_V  0xFFFFFFFFU
+#define I3C_MST_REG_SIR_REQ_REJECT_S  0
+
+/** I3C_MST_INT_CLR_REG register
+ *  NA
+ */
+#define I3C_MST_INT_CLR_REG (DR_REG_I3C_MST_BASE + 0x30)
+/** I3C_MST_TX_DATA_BUF_THLD_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TX_DATA_BUF_THLD_INT_CLR    (BIT(0))
+#define I3C_MST_TX_DATA_BUF_THLD_INT_CLR_M  (I3C_MST_TX_DATA_BUF_THLD_INT_CLR_V << I3C_MST_TX_DATA_BUF_THLD_INT_CLR_S)
+#define I3C_MST_TX_DATA_BUF_THLD_INT_CLR_V  0x00000001U
+#define I3C_MST_TX_DATA_BUF_THLD_INT_CLR_S  0
+/** I3C_MST_RX_DATA_BUF_THLD_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RX_DATA_BUF_THLD_INT_CLR    (BIT(1))
+#define I3C_MST_RX_DATA_BUF_THLD_INT_CLR_M  (I3C_MST_RX_DATA_BUF_THLD_INT_CLR_V << I3C_MST_RX_DATA_BUF_THLD_INT_CLR_S)
+#define I3C_MST_RX_DATA_BUF_THLD_INT_CLR_V  0x00000001U
+#define I3C_MST_RX_DATA_BUF_THLD_INT_CLR_S  1
+/** I3C_MST_IBI_STATUS_THLD_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_THLD_INT_CLR    (BIT(2))
+#define I3C_MST_IBI_STATUS_THLD_INT_CLR_M  (I3C_MST_IBI_STATUS_THLD_INT_CLR_V << I3C_MST_IBI_STATUS_THLD_INT_CLR_S)
+#define I3C_MST_IBI_STATUS_THLD_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_STATUS_THLD_INT_CLR_S  2
+/** I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR    (BIT(3))
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_M  (I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_V << I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_S)
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_V  0x00000001U
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_CLR_S  3
+/** I3C_MST_RESP_READY_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_READY_INT_CLR    (BIT(4))
+#define I3C_MST_RESP_READY_INT_CLR_M  (I3C_MST_RESP_READY_INT_CLR_V << I3C_MST_RESP_READY_INT_CLR_S)
+#define I3C_MST_RESP_READY_INT_CLR_V  0x00000001U
+#define I3C_MST_RESP_READY_INT_CLR_S  4
+/** I3C_MST_NXT_CMD_REQ_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_CLR    (BIT(5))
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_M  (I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_V << I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_S)
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_V  0x00000001U
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_CLR_S  5
+/** I3C_MST_TRANSFER_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_ERR_INT_CLR    (BIT(6))
+#define I3C_MST_TRANSFER_ERR_INT_CLR_M  (I3C_MST_TRANSFER_ERR_INT_CLR_V << I3C_MST_TRANSFER_ERR_INT_CLR_S)
+#define I3C_MST_TRANSFER_ERR_INT_CLR_V  0x00000001U
+#define I3C_MST_TRANSFER_ERR_INT_CLR_S  6
+/** I3C_MST_TRANSFER_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_COMPLETE_INT_CLR    (BIT(7))
+#define I3C_MST_TRANSFER_COMPLETE_INT_CLR_M  (I3C_MST_TRANSFER_COMPLETE_INT_CLR_V << I3C_MST_TRANSFER_COMPLETE_INT_CLR_S)
+#define I3C_MST_TRANSFER_COMPLETE_INT_CLR_V  0x00000001U
+#define I3C_MST_TRANSFER_COMPLETE_INT_CLR_S  7
+/** I3C_MST_COMMAND_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_COMMAND_DONE_INT_CLR    (BIT(8))
+#define I3C_MST_COMMAND_DONE_INT_CLR_M  (I3C_MST_COMMAND_DONE_INT_CLR_V << I3C_MST_COMMAND_DONE_INT_CLR_S)
+#define I3C_MST_COMMAND_DONE_INT_CLR_V  0x00000001U
+#define I3C_MST_COMMAND_DONE_INT_CLR_S  8
+/** I3C_MST_DETECT_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_DETECT_START_INT_CLR    (BIT(9))
+#define I3C_MST_DETECT_START_INT_CLR_M  (I3C_MST_DETECT_START_INT_CLR_V << I3C_MST_DETECT_START_INT_CLR_S)
+#define I3C_MST_DETECT_START_INT_CLR_V  0x00000001U
+#define I3C_MST_DETECT_START_INT_CLR_S  9
+/** I3C_MST_RESP_BUF_OVF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_BUF_OVF_INT_CLR    (BIT(10))
+#define I3C_MST_RESP_BUF_OVF_INT_CLR_M  (I3C_MST_RESP_BUF_OVF_INT_CLR_V << I3C_MST_RESP_BUF_OVF_INT_CLR_S)
+#define I3C_MST_RESP_BUF_OVF_INT_CLR_V  0x00000001U
+#define I3C_MST_RESP_BUF_OVF_INT_CLR_S  10
+/** I3C_MST_IBI_DATA_BUF_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_CLR    (BIT(11))
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_M  (I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_V << I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_S)
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_CLR_S  11
+/** I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR    (BIT(12))
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_M  (I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_V << I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_S)
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_CLR_S  12
+/** I3C_MST_IBI_HANDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_HANDLE_DONE_INT_CLR    (BIT(13))
+#define I3C_MST_IBI_HANDLE_DONE_INT_CLR_M  (I3C_MST_IBI_HANDLE_DONE_INT_CLR_V << I3C_MST_IBI_HANDLE_DONE_INT_CLR_S)
+#define I3C_MST_IBI_HANDLE_DONE_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_HANDLE_DONE_INT_CLR_S  13
+/** I3C_MST_IBI_DETECT_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DETECT_INT_CLR    (BIT(14))
+#define I3C_MST_IBI_DETECT_INT_CLR_M  (I3C_MST_IBI_DETECT_INT_CLR_V << I3C_MST_IBI_DETECT_INT_CLR_S)
+#define I3C_MST_IBI_DETECT_INT_CLR_V  0x00000001U
+#define I3C_MST_IBI_DETECT_INT_CLR_S  14
+/** I3C_MST_CMD_CCC_MISMATCH_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_CCC_MISMATCH_INT_CLR    (BIT(15))
+#define I3C_MST_CMD_CCC_MISMATCH_INT_CLR_M  (I3C_MST_CMD_CCC_MISMATCH_INT_CLR_V << I3C_MST_CMD_CCC_MISMATCH_INT_CLR_S)
+#define I3C_MST_CMD_CCC_MISMATCH_INT_CLR_V  0x00000001U
+#define I3C_MST_CMD_CCC_MISMATCH_INT_CLR_S  15
+
+/** I3C_MST_INT_RAW_REG register
+ *  NA
+ */
+#define I3C_MST_INT_RAW_REG (DR_REG_I3C_MST_BASE + 0x34)
+/** I3C_MST_TX_DATA_BUF_THLD_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TX_DATA_BUF_THLD_INT_RAW    (BIT(0))
+#define I3C_MST_TX_DATA_BUF_THLD_INT_RAW_M  (I3C_MST_TX_DATA_BUF_THLD_INT_RAW_V << I3C_MST_TX_DATA_BUF_THLD_INT_RAW_S)
+#define I3C_MST_TX_DATA_BUF_THLD_INT_RAW_V  0x00000001U
+#define I3C_MST_TX_DATA_BUF_THLD_INT_RAW_S  0
+/** I3C_MST_RX_DATA_BUF_THLD_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RX_DATA_BUF_THLD_INT_RAW    (BIT(1))
+#define I3C_MST_RX_DATA_BUF_THLD_INT_RAW_M  (I3C_MST_RX_DATA_BUF_THLD_INT_RAW_V << I3C_MST_RX_DATA_BUF_THLD_INT_RAW_S)
+#define I3C_MST_RX_DATA_BUF_THLD_INT_RAW_V  0x00000001U
+#define I3C_MST_RX_DATA_BUF_THLD_INT_RAW_S  1
+/** I3C_MST_IBI_STATUS_THLD_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_THLD_INT_RAW    (BIT(2))
+#define I3C_MST_IBI_STATUS_THLD_INT_RAW_M  (I3C_MST_IBI_STATUS_THLD_INT_RAW_V << I3C_MST_IBI_STATUS_THLD_INT_RAW_S)
+#define I3C_MST_IBI_STATUS_THLD_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_STATUS_THLD_INT_RAW_S  2
+/** I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  NA
+ */
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW    (BIT(3))
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_M  (I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_V << I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_S)
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_V  0x00000001U
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_RAW_S  3
+/** I3C_MST_RESP_READY_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_READY_INT_RAW    (BIT(4))
+#define I3C_MST_RESP_READY_INT_RAW_M  (I3C_MST_RESP_READY_INT_RAW_V << I3C_MST_RESP_READY_INT_RAW_S)
+#define I3C_MST_RESP_READY_INT_RAW_V  0x00000001U
+#define I3C_MST_RESP_READY_INT_RAW_S  4
+/** I3C_MST_NXT_CMD_REQ_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_RAW    (BIT(5))
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_M  (I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_V << I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_S)
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_V  0x00000001U
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_RAW_S  5
+/** I3C_MST_TRANSFER_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_ERR_INT_RAW    (BIT(6))
+#define I3C_MST_TRANSFER_ERR_INT_RAW_M  (I3C_MST_TRANSFER_ERR_INT_RAW_V << I3C_MST_TRANSFER_ERR_INT_RAW_S)
+#define I3C_MST_TRANSFER_ERR_INT_RAW_V  0x00000001U
+#define I3C_MST_TRANSFER_ERR_INT_RAW_S  6
+/** I3C_MST_TRANSFER_COMPLETE_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_COMPLETE_INT_RAW    (BIT(7))
+#define I3C_MST_TRANSFER_COMPLETE_INT_RAW_M  (I3C_MST_TRANSFER_COMPLETE_INT_RAW_V << I3C_MST_TRANSFER_COMPLETE_INT_RAW_S)
+#define I3C_MST_TRANSFER_COMPLETE_INT_RAW_V  0x00000001U
+#define I3C_MST_TRANSFER_COMPLETE_INT_RAW_S  7
+/** I3C_MST_COMMAND_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_COMMAND_DONE_INT_RAW    (BIT(8))
+#define I3C_MST_COMMAND_DONE_INT_RAW_M  (I3C_MST_COMMAND_DONE_INT_RAW_V << I3C_MST_COMMAND_DONE_INT_RAW_S)
+#define I3C_MST_COMMAND_DONE_INT_RAW_V  0x00000001U
+#define I3C_MST_COMMAND_DONE_INT_RAW_S  8
+/** I3C_MST_DETECT_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_DETECT_START_INT_RAW    (BIT(9))
+#define I3C_MST_DETECT_START_INT_RAW_M  (I3C_MST_DETECT_START_INT_RAW_V << I3C_MST_DETECT_START_INT_RAW_S)
+#define I3C_MST_DETECT_START_INT_RAW_V  0x00000001U
+#define I3C_MST_DETECT_START_INT_RAW_S  9
+/** I3C_MST_RESP_BUF_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_BUF_OVF_INT_RAW    (BIT(10))
+#define I3C_MST_RESP_BUF_OVF_INT_RAW_M  (I3C_MST_RESP_BUF_OVF_INT_RAW_V << I3C_MST_RESP_BUF_OVF_INT_RAW_S)
+#define I3C_MST_RESP_BUF_OVF_INT_RAW_V  0x00000001U
+#define I3C_MST_RESP_BUF_OVF_INT_RAW_S  10
+/** I3C_MST_IBI_DATA_BUF_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_RAW    (BIT(11))
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_M  (I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_V << I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_S)
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_RAW_S  11
+/** I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW    (BIT(12))
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_M  (I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_V << I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_S)
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_RAW_S  12
+/** I3C_MST_IBI_HANDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_HANDLE_DONE_INT_RAW    (BIT(13))
+#define I3C_MST_IBI_HANDLE_DONE_INT_RAW_M  (I3C_MST_IBI_HANDLE_DONE_INT_RAW_V << I3C_MST_IBI_HANDLE_DONE_INT_RAW_S)
+#define I3C_MST_IBI_HANDLE_DONE_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_HANDLE_DONE_INT_RAW_S  13
+/** I3C_MST_IBI_DETECT_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DETECT_INT_RAW    (BIT(14))
+#define I3C_MST_IBI_DETECT_INT_RAW_M  (I3C_MST_IBI_DETECT_INT_RAW_V << I3C_MST_IBI_DETECT_INT_RAW_S)
+#define I3C_MST_IBI_DETECT_INT_RAW_V  0x00000001U
+#define I3C_MST_IBI_DETECT_INT_RAW_S  14
+/** I3C_MST_CMD_CCC_MISMATCH_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_CCC_MISMATCH_INT_RAW    (BIT(15))
+#define I3C_MST_CMD_CCC_MISMATCH_INT_RAW_M  (I3C_MST_CMD_CCC_MISMATCH_INT_RAW_V << I3C_MST_CMD_CCC_MISMATCH_INT_RAW_S)
+#define I3C_MST_CMD_CCC_MISMATCH_INT_RAW_V  0x00000001U
+#define I3C_MST_CMD_CCC_MISMATCH_INT_RAW_S  15
+
+/** I3C_MST_INT_ST_REG register
+ *  NA
+ */
+#define I3C_MST_INT_ST_REG (DR_REG_I3C_MST_BASE + 0x38)
+/** I3C_MST_TX_DATA_BUF_THLD_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This interrupt is generated when number of empty locations in transmit buffer is
+ *  greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in
+ *  DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+ *  number of empty locations in transmit buffer is less than threshold value.
+ */
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ST    (BIT(0))
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ST_M  (I3C_MST_TX_DATA_BUF_THLD_INT_ST_V << I3C_MST_TX_DATA_BUF_THLD_INT_ST_S)
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ST_V  0x00000001U
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ST_S  0
+/** I3C_MST_RX_DATA_BUF_THLD_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This interrupt is generated when number of entries in receive buffer is greater
+ *  than or equal to threshold value specified by RX_BUF_THLD field in
+ *  DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+ *  number of entries in receive buffer is less than threshold value.
+ */
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ST    (BIT(1))
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ST_M  (I3C_MST_RX_DATA_BUF_THLD_INT_ST_V << I3C_MST_RX_DATA_BUF_THLD_INT_ST_S)
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ST_V  0x00000001U
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ST_S  1
+/** I3C_MST_IBI_STATUS_THLD_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Only used in master mode. This interrupt is generated when number of entries in IBI
+ *  buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field
+ *  in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+ *  number of entries in IBI buffer is less than threshold value.
+ */
+#define I3C_MST_IBI_STATUS_THLD_INT_ST    (BIT(2))
+#define I3C_MST_IBI_STATUS_THLD_INT_ST_M  (I3C_MST_IBI_STATUS_THLD_INT_ST_V << I3C_MST_IBI_STATUS_THLD_INT_ST_S)
+#define I3C_MST_IBI_STATUS_THLD_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_STATUS_THLD_INT_ST_S  2
+/** I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This interrupt is generated when number of empty locations in command buffer is
+ *  greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in
+ *  BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number
+ *  of empty locations in command buffer is less than threshold value.
+ */
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST    (BIT(3))
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_M  (I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_V << I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_S)
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_V  0x00000001U
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ST_S  3
+/** I3C_MST_RESP_READY_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This interrupt is generated when number of entries in response buffer is greater
+ *  than or equal to threshold value specified by RESP_BUF_THLD field in
+ *  BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number
+ *  of entries in response buffer is less than threshold value.
+ */
+#define I3C_MST_RESP_READY_INT_ST    (BIT(4))
+#define I3C_MST_RESP_READY_INT_ST_M  (I3C_MST_RESP_READY_INT_ST_V << I3C_MST_RESP_READY_INT_ST_S)
+#define I3C_MST_RESP_READY_INT_ST_V  0x00000001U
+#define I3C_MST_RESP_READY_INT_ST_S  4
+/** I3C_MST_NXT_CMD_REQ_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This interrupt is generated if toc is 0(master will restart next command), but
+ *  command buf is empty.
+ */
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ST    (BIT(5))
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ST_M  (I3C_MST_NXT_CMD_REQ_ERR_INT_ST_V << I3C_MST_NXT_CMD_REQ_ERR_INT_ST_S)
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ST_V  0x00000001U
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ST_S  5
+/** I3C_MST_TRANSFER_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This interrupt is generated if any error occurs during transfer. The error type
+ *  will be specified in the response packet associated with the command (in ERR_STATUS
+ *  field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1.
+ */
+#define I3C_MST_TRANSFER_ERR_INT_ST    (BIT(6))
+#define I3C_MST_TRANSFER_ERR_INT_ST_M  (I3C_MST_TRANSFER_ERR_INT_ST_V << I3C_MST_TRANSFER_ERR_INT_ST_S)
+#define I3C_MST_TRANSFER_ERR_INT_ST_V  0x00000001U
+#define I3C_MST_TRANSFER_ERR_INT_ST_S  6
+/** I3C_MST_TRANSFER_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_COMPLETE_INT_ST    (BIT(7))
+#define I3C_MST_TRANSFER_COMPLETE_INT_ST_M  (I3C_MST_TRANSFER_COMPLETE_INT_ST_V << I3C_MST_TRANSFER_COMPLETE_INT_ST_S)
+#define I3C_MST_TRANSFER_COMPLETE_INT_ST_V  0x00000001U
+#define I3C_MST_TRANSFER_COMPLETE_INT_ST_S  7
+/** I3C_MST_COMMAND_DONE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_COMMAND_DONE_INT_ST    (BIT(8))
+#define I3C_MST_COMMAND_DONE_INT_ST_M  (I3C_MST_COMMAND_DONE_INT_ST_V << I3C_MST_COMMAND_DONE_INT_ST_S)
+#define I3C_MST_COMMAND_DONE_INT_ST_V  0x00000001U
+#define I3C_MST_COMMAND_DONE_INT_ST_S  8
+/** I3C_MST_DETECT_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_DETECT_START_INT_ST    (BIT(9))
+#define I3C_MST_DETECT_START_INT_ST_M  (I3C_MST_DETECT_START_INT_ST_V << I3C_MST_DETECT_START_INT_ST_S)
+#define I3C_MST_DETECT_START_INT_ST_V  0x00000001U
+#define I3C_MST_DETECT_START_INT_ST_S  9
+/** I3C_MST_RESP_BUF_OVF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_BUF_OVF_INT_ST    (BIT(10))
+#define I3C_MST_RESP_BUF_OVF_INT_ST_M  (I3C_MST_RESP_BUF_OVF_INT_ST_V << I3C_MST_RESP_BUF_OVF_INT_ST_S)
+#define I3C_MST_RESP_BUF_OVF_INT_ST_V  0x00000001U
+#define I3C_MST_RESP_BUF_OVF_INT_ST_S  10
+/** I3C_MST_IBI_DATA_BUF_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ST    (BIT(11))
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ST_M  (I3C_MST_IBI_DATA_BUF_OVF_INT_ST_V << I3C_MST_IBI_DATA_BUF_OVF_INT_ST_S)
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ST_S  11
+/** I3C_MST_IBI_STATUS_BUF_OVF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ST    (BIT(12))
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_M  (I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_V << I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_S)
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ST_S  12
+/** I3C_MST_IBI_HANDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_HANDLE_DONE_INT_ST    (BIT(13))
+#define I3C_MST_IBI_HANDLE_DONE_INT_ST_M  (I3C_MST_IBI_HANDLE_DONE_INT_ST_V << I3C_MST_IBI_HANDLE_DONE_INT_ST_S)
+#define I3C_MST_IBI_HANDLE_DONE_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_HANDLE_DONE_INT_ST_S  13
+/** I3C_MST_IBI_DETECT_INT_ST : RO; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DETECT_INT_ST    (BIT(14))
+#define I3C_MST_IBI_DETECT_INT_ST_M  (I3C_MST_IBI_DETECT_INT_ST_V << I3C_MST_IBI_DETECT_INT_ST_S)
+#define I3C_MST_IBI_DETECT_INT_ST_V  0x00000001U
+#define I3C_MST_IBI_DETECT_INT_ST_S  14
+/** I3C_MST_CMD_CCC_MISMATCH_INT_ST : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ST    (BIT(15))
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ST_M  (I3C_MST_CMD_CCC_MISMATCH_INT_ST_V << I3C_MST_CMD_CCC_MISMATCH_INT_ST_S)
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ST_V  0x00000001U
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ST_S  15
+
+/** I3C_MST_INT_ST_ENA_REG register
+ *  The Interrupt status will be updated in INTR_STATUS register if corresponding
+ *  Status Enable bit set.
+ */
+#define I3C_MST_INT_ST_ENA_REG (DR_REG_I3C_MST_BASE + 0x3c)
+/** I3C_MST_TX_DATA_BUF_THLD_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Transmit Buffer threshold status enable.
+ */
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ENA    (BIT(0))
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ENA_M  (I3C_MST_TX_DATA_BUF_THLD_INT_ENA_V << I3C_MST_TX_DATA_BUF_THLD_INT_ENA_S)
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ENA_V  0x00000001U
+#define I3C_MST_TX_DATA_BUF_THLD_INT_ENA_S  0
+/** I3C_MST_RX_DATA_BUF_THLD_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Receive Buffer threshold status enable.
+ */
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ENA    (BIT(1))
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ENA_M  (I3C_MST_RX_DATA_BUF_THLD_INT_ENA_V << I3C_MST_RX_DATA_BUF_THLD_INT_ENA_S)
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ENA_V  0x00000001U
+#define I3C_MST_RX_DATA_BUF_THLD_INT_ENA_S  1
+/** I3C_MST_IBI_STATUS_THLD_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Only used in master mode. IBI Buffer threshold status enable.
+ */
+#define I3C_MST_IBI_STATUS_THLD_INT_ENA    (BIT(2))
+#define I3C_MST_IBI_STATUS_THLD_INT_ENA_M  (I3C_MST_IBI_STATUS_THLD_INT_ENA_V << I3C_MST_IBI_STATUS_THLD_INT_ENA_S)
+#define I3C_MST_IBI_STATUS_THLD_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_STATUS_THLD_INT_ENA_S  2
+/** I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Command buffer ready status enable.
+ */
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA    (BIT(3))
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_M  (I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_V << I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_S)
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_V  0x00000001U
+#define I3C_MST_CMD_BUF_EMPTY_THLD_INT_ENA_S  3
+/** I3C_MST_RESP_READY_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Response buffer ready status enable.
+ */
+#define I3C_MST_RESP_READY_INT_ENA    (BIT(4))
+#define I3C_MST_RESP_READY_INT_ENA_M  (I3C_MST_RESP_READY_INT_ENA_V << I3C_MST_RESP_READY_INT_ENA_S)
+#define I3C_MST_RESP_READY_INT_ENA_V  0x00000001U
+#define I3C_MST_RESP_READY_INT_ENA_S  4
+/** I3C_MST_NXT_CMD_REQ_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  next command request error status enable
+ */
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ENA    (BIT(5))
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_M  (I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_V << I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_S)
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_V  0x00000001U
+#define I3C_MST_NXT_CMD_REQ_ERR_INT_ENA_S  5
+/** I3C_MST_TRANSFER_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Transfer error status enable
+ */
+#define I3C_MST_TRANSFER_ERR_INT_ENA    (BIT(6))
+#define I3C_MST_TRANSFER_ERR_INT_ENA_M  (I3C_MST_TRANSFER_ERR_INT_ENA_V << I3C_MST_TRANSFER_ERR_INT_ENA_S)
+#define I3C_MST_TRANSFER_ERR_INT_ENA_V  0x00000001U
+#define I3C_MST_TRANSFER_ERR_INT_ENA_S  6
+/** I3C_MST_TRANSFER_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define I3C_MST_TRANSFER_COMPLETE_INT_ENA    (BIT(7))
+#define I3C_MST_TRANSFER_COMPLETE_INT_ENA_M  (I3C_MST_TRANSFER_COMPLETE_INT_ENA_V << I3C_MST_TRANSFER_COMPLETE_INT_ENA_S)
+#define I3C_MST_TRANSFER_COMPLETE_INT_ENA_V  0x00000001U
+#define I3C_MST_TRANSFER_COMPLETE_INT_ENA_S  7
+/** I3C_MST_COMMAND_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_COMMAND_DONE_INT_ENA    (BIT(8))
+#define I3C_MST_COMMAND_DONE_INT_ENA_M  (I3C_MST_COMMAND_DONE_INT_ENA_V << I3C_MST_COMMAND_DONE_INT_ENA_S)
+#define I3C_MST_COMMAND_DONE_INT_ENA_V  0x00000001U
+#define I3C_MST_COMMAND_DONE_INT_ENA_S  8
+/** I3C_MST_DETECT_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_DETECT_START_INT_ENA    (BIT(9))
+#define I3C_MST_DETECT_START_INT_ENA_M  (I3C_MST_DETECT_START_INT_ENA_V << I3C_MST_DETECT_START_INT_ENA_S)
+#define I3C_MST_DETECT_START_INT_ENA_V  0x00000001U
+#define I3C_MST_DETECT_START_INT_ENA_S  9
+/** I3C_MST_RESP_BUF_OVF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RESP_BUF_OVF_INT_ENA    (BIT(10))
+#define I3C_MST_RESP_BUF_OVF_INT_ENA_M  (I3C_MST_RESP_BUF_OVF_INT_ENA_V << I3C_MST_RESP_BUF_OVF_INT_ENA_S)
+#define I3C_MST_RESP_BUF_OVF_INT_ENA_V  0x00000001U
+#define I3C_MST_RESP_BUF_OVF_INT_ENA_S  10
+/** I3C_MST_IBI_DATA_BUF_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ENA    (BIT(11))
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_M  (I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_V << I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_S)
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_DATA_BUF_OVF_INT_ENA_S  11
+/** I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA    (BIT(12))
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_M  (I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_V << I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_S)
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_STATUS_BUF_OVF_INT_ENA_S  12
+/** I3C_MST_IBI_HANDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_HANDLE_DONE_INT_ENA    (BIT(13))
+#define I3C_MST_IBI_HANDLE_DONE_INT_ENA_M  (I3C_MST_IBI_HANDLE_DONE_INT_ENA_V << I3C_MST_IBI_HANDLE_DONE_INT_ENA_S)
+#define I3C_MST_IBI_HANDLE_DONE_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_HANDLE_DONE_INT_ENA_S  13
+/** I3C_MST_IBI_DETECT_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_DETECT_INT_ENA    (BIT(14))
+#define I3C_MST_IBI_DETECT_INT_ENA_M  (I3C_MST_IBI_DETECT_INT_ENA_V << I3C_MST_IBI_DETECT_INT_ENA_S)
+#define I3C_MST_IBI_DETECT_INT_ENA_V  0x00000001U
+#define I3C_MST_IBI_DETECT_INT_ENA_S  14
+/** I3C_MST_CMD_CCC_MISMATCH_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ENA    (BIT(15))
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ENA_M  (I3C_MST_CMD_CCC_MISMATCH_INT_ENA_V << I3C_MST_CMD_CCC_MISMATCH_INT_ENA_S)
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ENA_V  0x00000001U
+#define I3C_MST_CMD_CCC_MISMATCH_INT_ENA_S  15
+
+/** I3C_MST_RESET_CTRL_REG register
+ *  NA
+ */
+#define I3C_MST_RESET_CTRL_REG (DR_REG_I3C_MST_BASE + 0x44)
+/** I3C_MST_REG_CORE_SOFT_RST : WT; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_CORE_SOFT_RST    (BIT(0))
+#define I3C_MST_REG_CORE_SOFT_RST_M  (I3C_MST_REG_CORE_SOFT_RST_V << I3C_MST_REG_CORE_SOFT_RST_S)
+#define I3C_MST_REG_CORE_SOFT_RST_V  0x00000001U
+#define I3C_MST_REG_CORE_SOFT_RST_S  0
+/** I3C_MST_REG_CMD_BUF_RST : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_CMD_BUF_RST    (BIT(1))
+#define I3C_MST_REG_CMD_BUF_RST_M  (I3C_MST_REG_CMD_BUF_RST_V << I3C_MST_REG_CMD_BUF_RST_S)
+#define I3C_MST_REG_CMD_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_CMD_BUF_RST_S  1
+/** I3C_MST_REG_RESP_BUF_RST : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RESP_BUF_RST    (BIT(2))
+#define I3C_MST_REG_RESP_BUF_RST_M  (I3C_MST_REG_RESP_BUF_RST_V << I3C_MST_REG_RESP_BUF_RST_S)
+#define I3C_MST_REG_RESP_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_RESP_BUF_RST_S  2
+/** I3C_MST_REG_TX_DATA_BUF_BUF_RST : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_TX_DATA_BUF_BUF_RST    (BIT(3))
+#define I3C_MST_REG_TX_DATA_BUF_BUF_RST_M  (I3C_MST_REG_TX_DATA_BUF_BUF_RST_V << I3C_MST_REG_TX_DATA_BUF_BUF_RST_S)
+#define I3C_MST_REG_TX_DATA_BUF_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_TX_DATA_BUF_BUF_RST_S  3
+/** I3C_MST_REG_RX_DATA_BUF_RST : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RX_DATA_BUF_RST    (BIT(4))
+#define I3C_MST_REG_RX_DATA_BUF_RST_M  (I3C_MST_REG_RX_DATA_BUF_RST_V << I3C_MST_REG_RX_DATA_BUF_RST_S)
+#define I3C_MST_REG_RX_DATA_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_RX_DATA_BUF_RST_S  4
+/** I3C_MST_REG_IBI_DATA_BUF_RST : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_DATA_BUF_RST    (BIT(5))
+#define I3C_MST_REG_IBI_DATA_BUF_RST_M  (I3C_MST_REG_IBI_DATA_BUF_RST_V << I3C_MST_REG_IBI_DATA_BUF_RST_S)
+#define I3C_MST_REG_IBI_DATA_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_IBI_DATA_BUF_RST_S  5
+/** I3C_MST_REG_IBI_STATUS_BUF_RST : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_STATUS_BUF_RST    (BIT(6))
+#define I3C_MST_REG_IBI_STATUS_BUF_RST_M  (I3C_MST_REG_IBI_STATUS_BUF_RST_V << I3C_MST_REG_IBI_STATUS_BUF_RST_S)
+#define I3C_MST_REG_IBI_STATUS_BUF_RST_V  0x00000001U
+#define I3C_MST_REG_IBI_STATUS_BUF_RST_S  6
+
+/** I3C_MST_BUFFER_STATUS_LEVEL_REG register
+ *  BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.
+ */
+#define I3C_MST_BUFFER_STATUS_LEVEL_REG (DR_REG_I3C_MST_BASE + 0x48)
+/** I3C_MST_CMD_BUF_EMPTY_CNT : RO; bitpos: [4:0]; default: 16;
+ *  Command Buffer Empty Locations contains the number of empty locations in the
+ *  command buffer.
+ */
+#define I3C_MST_CMD_BUF_EMPTY_CNT    0x0000001FU
+#define I3C_MST_CMD_BUF_EMPTY_CNT_M  (I3C_MST_CMD_BUF_EMPTY_CNT_V << I3C_MST_CMD_BUF_EMPTY_CNT_S)
+#define I3C_MST_CMD_BUF_EMPTY_CNT_V  0x0000001FU
+#define I3C_MST_CMD_BUF_EMPTY_CNT_S  0
+/** I3C_MST_RESP_BUF_CNT : RO; bitpos: [11:8]; default: 0;
+ *  Response Buffer Level Value contains the number of valid data entries in the
+ *  response buffer.
+ */
+#define I3C_MST_RESP_BUF_CNT    0x0000000FU
+#define I3C_MST_RESP_BUF_CNT_M  (I3C_MST_RESP_BUF_CNT_V << I3C_MST_RESP_BUF_CNT_S)
+#define I3C_MST_RESP_BUF_CNT_V  0x0000000FU
+#define I3C_MST_RESP_BUF_CNT_S  8
+/** I3C_MST_IBI_DATA_BUF_CNT : RO; bitpos: [19:16]; default: 0;
+ *  IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This
+ *  is field is used in master mode.
+ */
+#define I3C_MST_IBI_DATA_BUF_CNT    0x0000000FU
+#define I3C_MST_IBI_DATA_BUF_CNT_M  (I3C_MST_IBI_DATA_BUF_CNT_V << I3C_MST_IBI_DATA_BUF_CNT_S)
+#define I3C_MST_IBI_DATA_BUF_CNT_V  0x0000000FU
+#define I3C_MST_IBI_DATA_BUF_CNT_S  16
+/** I3C_MST_IBI_STATUS_BUF_CNT : RO; bitpos: [27:24]; default: 0;
+ *  IBI Buffer Status Count contains the number of IBI status entries in the IBI
+ *  Buffer. This field is used in master mode.
+ */
+#define I3C_MST_IBI_STATUS_BUF_CNT    0x0000000FU
+#define I3C_MST_IBI_STATUS_BUF_CNT_M  (I3C_MST_IBI_STATUS_BUF_CNT_V << I3C_MST_IBI_STATUS_BUF_CNT_S)
+#define I3C_MST_IBI_STATUS_BUF_CNT_V  0x0000000FU
+#define I3C_MST_IBI_STATUS_BUF_CNT_S  24
+
+/** I3C_MST_DATA_BUFFER_STATUS_LEVEL_REG register
+ *  DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.
+ */
+#define I3C_MST_DATA_BUFFER_STATUS_LEVEL_REG (DR_REG_I3C_MST_BASE + 0x4c)
+/** I3C_MST_TX_DATA_BUF_EMPTY_CNT : RO; bitpos: [5:0]; default: 32;
+ *  Transmit Buffer Empty Level Value contains the number of empty locations in the
+ *  transmit Buffer.
+ */
+#define I3C_MST_TX_DATA_BUF_EMPTY_CNT    0x0000003FU
+#define I3C_MST_TX_DATA_BUF_EMPTY_CNT_M  (I3C_MST_TX_DATA_BUF_EMPTY_CNT_V << I3C_MST_TX_DATA_BUF_EMPTY_CNT_S)
+#define I3C_MST_TX_DATA_BUF_EMPTY_CNT_V  0x0000003FU
+#define I3C_MST_TX_DATA_BUF_EMPTY_CNT_S  0
+/** I3C_MST_RX_DATA_BUF_CNT : RO; bitpos: [21:16]; default: 0;
+ *  Receive Buffer Level value contains the number of valid data entries in the receive
+ *  buffer.
+ */
+#define I3C_MST_RX_DATA_BUF_CNT    0x0000003FU
+#define I3C_MST_RX_DATA_BUF_CNT_M  (I3C_MST_RX_DATA_BUF_CNT_V << I3C_MST_RX_DATA_BUF_CNT_S)
+#define I3C_MST_RX_DATA_BUF_CNT_V  0x0000003FU
+#define I3C_MST_RX_DATA_BUF_CNT_S  16
+
+/** I3C_MST_PRESENT_STATE0_REG register
+ *  NA
+ */
+#define I3C_MST_PRESENT_STATE0_REG (DR_REG_I3C_MST_BASE + 0x50)
+/** I3C_MST_SDA_LVL : RO; bitpos: [0]; default: 1;
+ *  This bit is used to check the SCL line level to recover from error and  for
+ *  debugging. This bit reflects the value of synchronized scl_in_a.
+ */
+#define I3C_MST_SDA_LVL    (BIT(0))
+#define I3C_MST_SDA_LVL_M  (I3C_MST_SDA_LVL_V << I3C_MST_SDA_LVL_S)
+#define I3C_MST_SDA_LVL_V  0x00000001U
+#define I3C_MST_SDA_LVL_S  0
+/** I3C_MST_SCL_LVL : RO; bitpos: [1]; default: 1;
+ *  This bit is used to check the SDA line level to recover from error and  for
+ *  debugging. This bit reflects the value of synchronized sda_in_a.
+ */
+#define I3C_MST_SCL_LVL    (BIT(1))
+#define I3C_MST_SCL_LVL_M  (I3C_MST_SCL_LVL_V << I3C_MST_SCL_LVL_S)
+#define I3C_MST_SCL_LVL_V  0x00000001U
+#define I3C_MST_SCL_LVL_S  1
+/** I3C_MST_BUS_BUSY : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define I3C_MST_BUS_BUSY    (BIT(2))
+#define I3C_MST_BUS_BUSY_M  (I3C_MST_BUS_BUSY_V << I3C_MST_BUS_BUSY_S)
+#define I3C_MST_BUS_BUSY_V  0x00000001U
+#define I3C_MST_BUS_BUSY_S  2
+/** I3C_MST_BUS_FREE : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define I3C_MST_BUS_FREE    (BIT(3))
+#define I3C_MST_BUS_FREE_M  (I3C_MST_BUS_FREE_V << I3C_MST_BUS_FREE_S)
+#define I3C_MST_BUS_FREE_V  0x00000001U
+#define I3C_MST_BUS_FREE_S  3
+/** I3C_MST_CMD_TID : RO; bitpos: [12:9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_CMD_TID    0x0000000FU
+#define I3C_MST_CMD_TID_M  (I3C_MST_CMD_TID_V << I3C_MST_CMD_TID_S)
+#define I3C_MST_CMD_TID_V  0x0000000FU
+#define I3C_MST_CMD_TID_S  9
+/** I3C_MST_SCL_GEN_FSM_STATE : RO; bitpos: [15:13]; default: 0;
+ *  NA
+ */
+#define I3C_MST_SCL_GEN_FSM_STATE    0x00000007U
+#define I3C_MST_SCL_GEN_FSM_STATE_M  (I3C_MST_SCL_GEN_FSM_STATE_V << I3C_MST_SCL_GEN_FSM_STATE_S)
+#define I3C_MST_SCL_GEN_FSM_STATE_V  0x00000007U
+#define I3C_MST_SCL_GEN_FSM_STATE_S  13
+/** I3C_MST_IBI_EV_HANDLE_FSM_STATE : RO; bitpos: [18:16]; default: 0;
+ *  NA
+ */
+#define I3C_MST_IBI_EV_HANDLE_FSM_STATE    0x00000007U
+#define I3C_MST_IBI_EV_HANDLE_FSM_STATE_M  (I3C_MST_IBI_EV_HANDLE_FSM_STATE_V << I3C_MST_IBI_EV_HANDLE_FSM_STATE_S)
+#define I3C_MST_IBI_EV_HANDLE_FSM_STATE_V  0x00000007U
+#define I3C_MST_IBI_EV_HANDLE_FSM_STATE_S  16
+/** I3C_MST_I2C_MODE_FSM_STATE : RO; bitpos: [21:19]; default: 0;
+ *  NA
+ */
+#define I3C_MST_I2C_MODE_FSM_STATE    0x00000007U
+#define I3C_MST_I2C_MODE_FSM_STATE_M  (I3C_MST_I2C_MODE_FSM_STATE_V << I3C_MST_I2C_MODE_FSM_STATE_S)
+#define I3C_MST_I2C_MODE_FSM_STATE_V  0x00000007U
+#define I3C_MST_I2C_MODE_FSM_STATE_S  19
+/** I3C_MST_SDR_MODE_FSM_STATE : RO; bitpos: [25:22]; default: 0;
+ *  NA
+ */
+#define I3C_MST_SDR_MODE_FSM_STATE    0x0000000FU
+#define I3C_MST_SDR_MODE_FSM_STATE_M  (I3C_MST_SDR_MODE_FSM_STATE_V << I3C_MST_SDR_MODE_FSM_STATE_S)
+#define I3C_MST_SDR_MODE_FSM_STATE_V  0x0000000FU
+#define I3C_MST_SDR_MODE_FSM_STATE_S  22
+/** I3C_MST_DAA_MODE_FSM_STATE : RO; bitpos: [28:26]; default: 0;
+ *  Reflects whether the Master Controller is in IDLE or not. This bit will be set when
+ *  all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the
+ *  Master State machine is in idle state. 0X0: not in idle  0x1: in idle
+ */
+#define I3C_MST_DAA_MODE_FSM_STATE    0x00000007U
+#define I3C_MST_DAA_MODE_FSM_STATE_M  (I3C_MST_DAA_MODE_FSM_STATE_V << I3C_MST_DAA_MODE_FSM_STATE_S)
+#define I3C_MST_DAA_MODE_FSM_STATE_V  0x00000007U
+#define I3C_MST_DAA_MODE_FSM_STATE_S  26
+/** I3C_MST_MAIN_FSM_STATE : RO; bitpos: [31:29]; default: 0;
+ *  NA
+ */
+#define I3C_MST_MAIN_FSM_STATE    0x00000007U
+#define I3C_MST_MAIN_FSM_STATE_M  (I3C_MST_MAIN_FSM_STATE_V << I3C_MST_MAIN_FSM_STATE_S)
+#define I3C_MST_MAIN_FSM_STATE_V  0x00000007U
+#define I3C_MST_MAIN_FSM_STATE_S  29
+
+/** I3C_MST_PRESENT_STATE1_REG register
+ *  NA
+ */
+#define I3C_MST_PRESENT_STATE1_REG (DR_REG_I3C_MST_BASE + 0x54)
+/** I3C_MST_DATA_BYTE_CNT : RO; bitpos: [15:0]; default: 0;
+ *  Present transfer data byte cnt: tx data byte cnt if write  rx data byte cnt if read
+ *  ibi data byte cnt if IBI handle.
+ */
+#define I3C_MST_DATA_BYTE_CNT    0x0000FFFFU
+#define I3C_MST_DATA_BYTE_CNT_M  (I3C_MST_DATA_BYTE_CNT_V << I3C_MST_DATA_BYTE_CNT_S)
+#define I3C_MST_DATA_BYTE_CNT_V  0x0000FFFFU
+#define I3C_MST_DATA_BYTE_CNT_S  0
+
+/** I3C_MST_DEVICE_TABLE_REG register
+ *  Pointer for Device Address Table
+ */
+#define I3C_MST_DEVICE_TABLE_REG (DR_REG_I3C_MST_BASE + 0x58)
+/** I3C_MST_REG_DCT_DAA_INIT_INDEX : R/W; bitpos: [3:0]; default: 0;
+ *  Reserved
+ */
+#define I3C_MST_REG_DCT_DAA_INIT_INDEX    0x0000000FU
+#define I3C_MST_REG_DCT_DAA_INIT_INDEX_M  (I3C_MST_REG_DCT_DAA_INIT_INDEX_V << I3C_MST_REG_DCT_DAA_INIT_INDEX_S)
+#define I3C_MST_REG_DCT_DAA_INIT_INDEX_V  0x0000000FU
+#define I3C_MST_REG_DCT_DAA_INIT_INDEX_S  0
+/** I3C_MST_REG_DAT_DAA_INIT_INDEX : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_DAT_DAA_INIT_INDEX    0x0000000FU
+#define I3C_MST_REG_DAT_DAA_INIT_INDEX_M  (I3C_MST_REG_DAT_DAA_INIT_INDEX_V << I3C_MST_REG_DAT_DAA_INIT_INDEX_S)
+#define I3C_MST_REG_DAT_DAA_INIT_INDEX_V  0x0000000FU
+#define I3C_MST_REG_DAT_DAA_INIT_INDEX_S  4
+/** I3C_MST_PRESENT_DCT_INDEX : RO; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_PRESENT_DCT_INDEX    0x0000000FU
+#define I3C_MST_PRESENT_DCT_INDEX_M  (I3C_MST_PRESENT_DCT_INDEX_V << I3C_MST_PRESENT_DCT_INDEX_S)
+#define I3C_MST_PRESENT_DCT_INDEX_V  0x0000000FU
+#define I3C_MST_PRESENT_DCT_INDEX_S  8
+/** I3C_MST_PRESENT_DAT_INDEX : RO; bitpos: [15:12]; default: 0;
+ *  NA
+ */
+#define I3C_MST_PRESENT_DAT_INDEX    0x0000000FU
+#define I3C_MST_PRESENT_DAT_INDEX_M  (I3C_MST_PRESENT_DAT_INDEX_V << I3C_MST_PRESENT_DAT_INDEX_S)
+#define I3C_MST_PRESENT_DAT_INDEX_V  0x0000000FU
+#define I3C_MST_PRESENT_DAT_INDEX_S  12
+
+/** I3C_MST_TIME_OUT_VALUE_REG register
+ *  NA
+ */
+#define I3C_MST_TIME_OUT_VALUE_REG (DR_REG_I3C_MST_BASE + 0x5c)
+/** I3C_MST_REG_RESP_BUF_TO_VALUE : R/W; bitpos: [4:0]; default: 16;
+ *  NA
+ */
+#define I3C_MST_REG_RESP_BUF_TO_VALUE    0x0000001FU
+#define I3C_MST_REG_RESP_BUF_TO_VALUE_M  (I3C_MST_REG_RESP_BUF_TO_VALUE_V << I3C_MST_REG_RESP_BUF_TO_VALUE_S)
+#define I3C_MST_REG_RESP_BUF_TO_VALUE_V  0x0000001FU
+#define I3C_MST_REG_RESP_BUF_TO_VALUE_S  0
+/** I3C_MST_REG_RESP_BUF_TO_EN : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RESP_BUF_TO_EN    (BIT(5))
+#define I3C_MST_REG_RESP_BUF_TO_EN_M  (I3C_MST_REG_RESP_BUF_TO_EN_V << I3C_MST_REG_RESP_BUF_TO_EN_S)
+#define I3C_MST_REG_RESP_BUF_TO_EN_V  0x00000001U
+#define I3C_MST_REG_RESP_BUF_TO_EN_S  5
+/** I3C_MST_REG_IBI_DATA_BUF_TO_VALUE : R/W; bitpos: [10:6]; default: 16;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_DATA_BUF_TO_VALUE    0x0000001FU
+#define I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_M  (I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_V << I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_S)
+#define I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_V  0x0000001FU
+#define I3C_MST_REG_IBI_DATA_BUF_TO_VALUE_S  6
+/** I3C_MST_REG_IBI_DATA_BUF_TO_EN : R/W; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_DATA_BUF_TO_EN    (BIT(11))
+#define I3C_MST_REG_IBI_DATA_BUF_TO_EN_M  (I3C_MST_REG_IBI_DATA_BUF_TO_EN_V << I3C_MST_REG_IBI_DATA_BUF_TO_EN_S)
+#define I3C_MST_REG_IBI_DATA_BUF_TO_EN_V  0x00000001U
+#define I3C_MST_REG_IBI_DATA_BUF_TO_EN_S  11
+/** I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE : R/W; bitpos: [16:12]; default: 16;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE    0x0000001FU
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_M  (I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_V << I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_S)
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_V  0x0000001FU
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_VALUE_S  12
+/** I3C_MST_REG_IBI_STATUS_BUF_TO_EN : R/W; bitpos: [17]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_EN    (BIT(17))
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_EN_M  (I3C_MST_REG_IBI_STATUS_BUF_TO_EN_V << I3C_MST_REG_IBI_STATUS_BUF_TO_EN_S)
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_EN_V  0x00000001U
+#define I3C_MST_REG_IBI_STATUS_BUF_TO_EN_S  17
+/** I3C_MST_REG_RX_DATA_BUF_TO_VALUE : R/W; bitpos: [22:18]; default: 16;
+ *  NA
+ */
+#define I3C_MST_REG_RX_DATA_BUF_TO_VALUE    0x0000001FU
+#define I3C_MST_REG_RX_DATA_BUF_TO_VALUE_M  (I3C_MST_REG_RX_DATA_BUF_TO_VALUE_V << I3C_MST_REG_RX_DATA_BUF_TO_VALUE_S)
+#define I3C_MST_REG_RX_DATA_BUF_TO_VALUE_V  0x0000001FU
+#define I3C_MST_REG_RX_DATA_BUF_TO_VALUE_S  18
+/** I3C_MST_REG_RX_DATA_BUF_TO_EN : R/W; bitpos: [23]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RX_DATA_BUF_TO_EN    (BIT(23))
+#define I3C_MST_REG_RX_DATA_BUF_TO_EN_M  (I3C_MST_REG_RX_DATA_BUF_TO_EN_V << I3C_MST_REG_RX_DATA_BUF_TO_EN_S)
+#define I3C_MST_REG_RX_DATA_BUF_TO_EN_V  0x00000001U
+#define I3C_MST_REG_RX_DATA_BUF_TO_EN_S  23
+
+/** I3C_MST_SCL_I3C_MST_OD_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_I3C_MST_OD_TIME_REG (DR_REG_I3C_MST_BASE + 0x60)
+/** I3C_MST_REG_I3C_MST_OD_LOW_PERIOD : R/W; bitpos: [15:0]; default: 25;
+ *  SCL Open-Drain low count for I3C transfers targeted to I3C devices.
+ */
+#define I3C_MST_REG_I3C_MST_OD_LOW_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_M  (I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_V << I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_S)
+#define I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I3C_MST_OD_LOW_PERIOD_S  0
+/** I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD : R/W; bitpos: [31:16]; default: 5;
+ *  SCL Open-Drain High count for I3C transfers targeted to I3C devices.
+ */
+#define I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_M  (I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_V << I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_S)
+#define I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I3C_MST_OD_HIGH_PERIOD_S  16
+
+/** I3C_MST_SCL_I3C_MST_PP_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_I3C_MST_PP_TIME_REG (DR_REG_I3C_MST_BASE + 0x64)
+/** I3C_MST_REG_I3C_MST_PP_LOW_PERIOD : R/W; bitpos: [7:0]; default: 5;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_PP_LOW_PERIOD    0x000000FFU
+#define I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_M  (I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_V << I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_S)
+#define I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_PP_LOW_PERIOD_S  0
+/** I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD : R/W; bitpos: [23:16]; default: 5;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD    0x000000FFU
+#define I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_M  (I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_V << I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_S)
+#define I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_PP_HIGH_PERIOD_S  16
+
+/** I3C_MST_SCL_I2C_FM_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_I2C_FM_TIME_REG (DR_REG_I3C_MST_BASE + 0x68)
+/** I3C_MST_REG_I2C_FM_LOW_PERIOD : R/W; bitpos: [15:0]; default: 163;
+ *  NA
+ */
+#define I3C_MST_REG_I2C_FM_LOW_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I2C_FM_LOW_PERIOD_M  (I3C_MST_REG_I2C_FM_LOW_PERIOD_V << I3C_MST_REG_I2C_FM_LOW_PERIOD_S)
+#define I3C_MST_REG_I2C_FM_LOW_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I2C_FM_LOW_PERIOD_S  0
+/** I3C_MST_REG_I2C_FM_HIGH_PERIOD : R/W; bitpos: [31:16]; default: 75;
+ *  The SCL open-drain low count timing for I2C Fast Mode transfers.
+ */
+#define I3C_MST_REG_I2C_FM_HIGH_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I2C_FM_HIGH_PERIOD_M  (I3C_MST_REG_I2C_FM_HIGH_PERIOD_V << I3C_MST_REG_I2C_FM_HIGH_PERIOD_S)
+#define I3C_MST_REG_I2C_FM_HIGH_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I2C_FM_HIGH_PERIOD_S  16
+
+/** I3C_MST_SCL_I2C_FMP_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_I2C_FMP_TIME_REG (DR_REG_I3C_MST_BASE + 0x6c)
+/** I3C_MST_REG_I2C_FMP_LOW_PERIOD : R/W; bitpos: [15:0]; default: 63;
+ *  NA
+ */
+#define I3C_MST_REG_I2C_FMP_LOW_PERIOD    0x0000FFFFU
+#define I3C_MST_REG_I2C_FMP_LOW_PERIOD_M  (I3C_MST_REG_I2C_FMP_LOW_PERIOD_V << I3C_MST_REG_I2C_FMP_LOW_PERIOD_S)
+#define I3C_MST_REG_I2C_FMP_LOW_PERIOD_V  0x0000FFFFU
+#define I3C_MST_REG_I2C_FMP_LOW_PERIOD_S  0
+/** I3C_MST_REG_I2C_FMP_HIGH_PERIOD : R/W; bitpos: [23:16]; default: 33;
+ *  NA
+ */
+#define I3C_MST_REG_I2C_FMP_HIGH_PERIOD    0x000000FFU
+#define I3C_MST_REG_I2C_FMP_HIGH_PERIOD_M  (I3C_MST_REG_I2C_FMP_HIGH_PERIOD_V << I3C_MST_REG_I2C_FMP_HIGH_PERIOD_S)
+#define I3C_MST_REG_I2C_FMP_HIGH_PERIOD_V  0x000000FFU
+#define I3C_MST_REG_I2C_FMP_HIGH_PERIOD_S  16
+
+/** I3C_MST_SCL_EXT_LOW_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_EXT_LOW_TIME_REG (DR_REG_I3C_MST_BASE + 0x70)
+/** I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1 : R/W; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1    0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_M  (I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_V << I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_S)
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD1_S  0
+/** I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2 : R/W; bitpos: [15:8]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2    0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_M  (I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_V << I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_S)
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD2_S  8
+/** I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3 : R/W; bitpos: [23:16]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3    0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_M  (I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_V << I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_S)
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD3_S  16
+/** I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4 : R/W; bitpos: [31:24]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4    0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_M  (I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_V << I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_S)
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_EXT_LOW_PERIOD4_S  24
+
+/** I3C_MST_SDA_SAMPLE_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SDA_SAMPLE_TIME_REG (DR_REG_I3C_MST_BASE + 0x74)
+/** I3C_MST_REG_SDA_OD_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  It is used to adjust sda sample point when scl high under open drain speed
+ */
+#define I3C_MST_REG_SDA_OD_SAMPLE_TIME    0x000001FFU
+#define I3C_MST_REG_SDA_OD_SAMPLE_TIME_M  (I3C_MST_REG_SDA_OD_SAMPLE_TIME_V << I3C_MST_REG_SDA_OD_SAMPLE_TIME_S)
+#define I3C_MST_REG_SDA_OD_SAMPLE_TIME_V  0x000001FFU
+#define I3C_MST_REG_SDA_OD_SAMPLE_TIME_S  0
+/** I3C_MST_REG_SDA_PP_SAMPLE_TIME : R/W; bitpos: [13:9]; default: 0;
+ *  It is used to adjust sda sample point when scl high under push pull speed
+ */
+#define I3C_MST_REG_SDA_PP_SAMPLE_TIME    0x0000001FU
+#define I3C_MST_REG_SDA_PP_SAMPLE_TIME_M  (I3C_MST_REG_SDA_PP_SAMPLE_TIME_V << I3C_MST_REG_SDA_PP_SAMPLE_TIME_S)
+#define I3C_MST_REG_SDA_PP_SAMPLE_TIME_V  0x0000001FU
+#define I3C_MST_REG_SDA_PP_SAMPLE_TIME_S  9
+
+/** I3C_MST_SDA_HOLD_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SDA_HOLD_TIME_REG (DR_REG_I3C_MST_BASE + 0x78)
+/** I3C_MST_REG_SDA_OD_TX_HOLD_TIME : R/W; bitpos: [8:0]; default: 1;
+ *  It is used to adjust sda drive point after scl neg under open drain speed
+ */
+#define I3C_MST_REG_SDA_OD_TX_HOLD_TIME    0x000001FFU
+#define I3C_MST_REG_SDA_OD_TX_HOLD_TIME_M  (I3C_MST_REG_SDA_OD_TX_HOLD_TIME_V << I3C_MST_REG_SDA_OD_TX_HOLD_TIME_S)
+#define I3C_MST_REG_SDA_OD_TX_HOLD_TIME_V  0x000001FFU
+#define I3C_MST_REG_SDA_OD_TX_HOLD_TIME_S  0
+/** I3C_MST_REG_SDA_PP_TX_HOLD_TIME : R/W; bitpos: [13:9]; default: 0;
+ *  It is used to adjust sda dirve point after scl neg under push pull speed
+ */
+#define I3C_MST_REG_SDA_PP_TX_HOLD_TIME    0x0000001FU
+#define I3C_MST_REG_SDA_PP_TX_HOLD_TIME_M  (I3C_MST_REG_SDA_PP_TX_HOLD_TIME_V << I3C_MST_REG_SDA_PP_TX_HOLD_TIME_S)
+#define I3C_MST_REG_SDA_PP_TX_HOLD_TIME_V  0x0000001FU
+#define I3C_MST_REG_SDA_PP_TX_HOLD_TIME_S  9
+
+/** I3C_MST_SCL_START_HOLD_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_START_HOLD_REG (DR_REG_I3C_MST_BASE + 0x7c)
+/** I3C_MST_REG_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  I2C_SCL_START_HOLD_TIME
+ */
+#define I3C_MST_REG_SCL_START_HOLD_TIME    0x000001FFU
+#define I3C_MST_REG_SCL_START_HOLD_TIME_M  (I3C_MST_REG_SCL_START_HOLD_TIME_V << I3C_MST_REG_SCL_START_HOLD_TIME_S)
+#define I3C_MST_REG_SCL_START_HOLD_TIME_V  0x000001FFU
+#define I3C_MST_REG_SCL_START_HOLD_TIME_S  0
+/** I3C_MST_REG_START_DET_HOLD_TIME : R/W; bitpos: [10:9]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_START_DET_HOLD_TIME    0x00000003U
+#define I3C_MST_REG_START_DET_HOLD_TIME_M  (I3C_MST_REG_START_DET_HOLD_TIME_V << I3C_MST_REG_START_DET_HOLD_TIME_S)
+#define I3C_MST_REG_START_DET_HOLD_TIME_V  0x00000003U
+#define I3C_MST_REG_START_DET_HOLD_TIME_S  9
+
+/** I3C_MST_SCL_RSTART_SETUP_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_RSTART_SETUP_REG (DR_REG_I3C_MST_BASE + 0x80)
+/** I3C_MST_REG_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  I2C_SCL_RSTART_SETUP_TIME
+ */
+#define I3C_MST_REG_SCL_RSTART_SETUP_TIME    0x000001FFU
+#define I3C_MST_REG_SCL_RSTART_SETUP_TIME_M  (I3C_MST_REG_SCL_RSTART_SETUP_TIME_V << I3C_MST_REG_SCL_RSTART_SETUP_TIME_S)
+#define I3C_MST_REG_SCL_RSTART_SETUP_TIME_V  0x000001FFU
+#define I3C_MST_REG_SCL_RSTART_SETUP_TIME_S  0
+
+/** I3C_MST_SCL_STOP_HOLD_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_STOP_HOLD_REG (DR_REG_I3C_MST_BASE + 0x84)
+/** I3C_MST_REG_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  I2C_SCL_STOP_HOLD_TIME
+ */
+#define I3C_MST_REG_SCL_STOP_HOLD_TIME    0x000001FFU
+#define I3C_MST_REG_SCL_STOP_HOLD_TIME_M  (I3C_MST_REG_SCL_STOP_HOLD_TIME_V << I3C_MST_REG_SCL_STOP_HOLD_TIME_S)
+#define I3C_MST_REG_SCL_STOP_HOLD_TIME_V  0x000001FFU
+#define I3C_MST_REG_SCL_STOP_HOLD_TIME_S  0
+
+/** I3C_MST_SCL_STOP_SETUP_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_STOP_SETUP_REG (DR_REG_I3C_MST_BASE + 0x88)
+/** I3C_MST_REG_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  I2C_SCL_STOP_SETUP_TIME
+ */
+#define I3C_MST_REG_SCL_STOP_SETUP_TIME    0x000001FFU
+#define I3C_MST_REG_SCL_STOP_SETUP_TIME_M  (I3C_MST_REG_SCL_STOP_SETUP_TIME_V << I3C_MST_REG_SCL_STOP_SETUP_TIME_S)
+#define I3C_MST_REG_SCL_STOP_SETUP_TIME_V  0x000001FFU
+#define I3C_MST_REG_SCL_STOP_SETUP_TIME_S  0
+
+/** I3C_MST_BUS_FREE_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_BUS_FREE_TIME_REG (DR_REG_I3C_MST_BASE + 0x90)
+/** I3C_MST_REG_BUS_FREE_TIME : R/W; bitpos: [15:0]; default: 5;
+ *  I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus
+ *  System, this field represents tCAS.  In Mixed Bus System, this field is expected to
+ *  be programmed to tLOW of I2C Timing.
+ */
+#define I3C_MST_REG_BUS_FREE_TIME    0x0000FFFFU
+#define I3C_MST_REG_BUS_FREE_TIME_M  (I3C_MST_REG_BUS_FREE_TIME_V << I3C_MST_REG_BUS_FREE_TIME_S)
+#define I3C_MST_REG_BUS_FREE_TIME_V  0x0000FFFFU
+#define I3C_MST_REG_BUS_FREE_TIME_S  0
+
+/** I3C_MST_SCL_TERMN_T_EXT_LOW_TIME_REG register
+ *  NA
+ */
+#define I3C_MST_SCL_TERMN_T_EXT_LOW_TIME_REG (DR_REG_I3C_MST_BASE + 0x94)
+/** I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME : R/W; bitpos: [7:0]; default: 2;
+ *  NA
+ */
+#define I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME    0x000000FFU
+#define I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_M  (I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_V << I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_S)
+#define I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_V  0x000000FFU
+#define I3C_MST_REG_I3C_MST_TERMN_T_EXT_LOW_TIME_S  0
+
+/** I3C_MST_VER_ID_REG register
+ *  NA
+ */
+#define I3C_MST_VER_ID_REG (DR_REG_I3C_MST_BASE + 0xa0)
+/** I3C_MST_REG_I3C_MST_VER_ID : R/W; bitpos: [31:0]; default: 539165956;
+ *  This field indicates the controller current release number that is read by an
+ *  application.
+ */
+#define I3C_MST_REG_I3C_MST_VER_ID    0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_VER_ID_M  (I3C_MST_REG_I3C_MST_VER_ID_V << I3C_MST_REG_I3C_MST_VER_ID_S)
+#define I3C_MST_REG_I3C_MST_VER_ID_V  0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_VER_ID_S  0
+
+/** I3C_MST_VER_TYPE_REG register
+ *  NA
+ */
+#define I3C_MST_VER_TYPE_REG (DR_REG_I3C_MST_BASE + 0xa4)
+/** I3C_MST_REG_I3C_MST_VER_TYPE : R/W; bitpos: [31:0]; default: 0;
+ *  This field indicates the controller current release type that is read by an
+ *  application.
+ */
+#define I3C_MST_REG_I3C_MST_VER_TYPE    0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_VER_TYPE_M  (I3C_MST_REG_I3C_MST_VER_TYPE_V << I3C_MST_REG_I3C_MST_VER_TYPE_S)
+#define I3C_MST_REG_I3C_MST_VER_TYPE_V  0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_VER_TYPE_S  0
+
+/** I3C_MST_FPGA_DEBUG_PROBE_REG register
+ *  NA
+ */
+#define I3C_MST_FPGA_DEBUG_PROBE_REG (DR_REG_I3C_MST_BASE + 0xac)
+/** I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE : R/W; bitpos: [31:0]; default: 1;
+ *  For Debug Probe Test on FPGA
+ */
+#define I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE    0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_M  (I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_V << I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_S)
+#define I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_V  0xFFFFFFFFU
+#define I3C_MST_REG_I3C_MST_FPGA_DEBUG_PROBE_S  0
+
+/** I3C_MST_RND_ECO_CS_REG register
+ *  NA
+ */
+#define I3C_MST_RND_ECO_CS_REG (DR_REG_I3C_MST_BASE + 0xb0)
+/** I3C_MST_REG_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RND_ECO_EN    (BIT(0))
+#define I3C_MST_REG_RND_ECO_EN_M  (I3C_MST_REG_RND_ECO_EN_V << I3C_MST_REG_RND_ECO_EN_S)
+#define I3C_MST_REG_RND_ECO_EN_V  0x00000001U
+#define I3C_MST_REG_RND_ECO_EN_S  0
+/** I3C_MST_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define I3C_MST_RND_ECO_RESULT    (BIT(1))
+#define I3C_MST_RND_ECO_RESULT_M  (I3C_MST_RND_ECO_RESULT_V << I3C_MST_RND_ECO_RESULT_S)
+#define I3C_MST_RND_ECO_RESULT_V  0x00000001U
+#define I3C_MST_RND_ECO_RESULT_S  1
+
+/** I3C_MST_RND_ECO_LOW_REG register
+ *  NA
+ */
+#define I3C_MST_RND_ECO_LOW_REG (DR_REG_I3C_MST_BASE + 0xb4)
+/** I3C_MST_REG_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_MST_REG_RND_ECO_LOW    0xFFFFFFFFU
+#define I3C_MST_REG_RND_ECO_LOW_M  (I3C_MST_REG_RND_ECO_LOW_V << I3C_MST_REG_RND_ECO_LOW_S)
+#define I3C_MST_REG_RND_ECO_LOW_V  0xFFFFFFFFU
+#define I3C_MST_REG_RND_ECO_LOW_S  0
+
+/** I3C_MST_RND_ECO_HIGH_REG register
+ *  NA
+ */
+#define I3C_MST_RND_ECO_HIGH_REG (DR_REG_I3C_MST_BASE + 0xb8)
+/** I3C_MST_REG_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 65535;
+ *  NA
+ */
+#define I3C_MST_REG_RND_ECO_HIGH    0xFFFFFFFFU
+#define I3C_MST_REG_RND_ECO_HIGH_M  (I3C_MST_REG_RND_ECO_HIGH_V << I3C_MST_REG_RND_ECO_HIGH_S)
+#define I3C_MST_REG_RND_ECO_HIGH_V  0xFFFFFFFFU
+#define I3C_MST_REG_RND_ECO_HIGH_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_struct.h
new file mode 100644
index 0000000000..de7c314a21
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i3c_mst_struct.h
@@ -0,0 +1,1183 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: I3C DEVICE CTRL REG */
+/** Type of device_ctrl register
+ *  DEVICE_CTRL register controls the transfer properties and disposition of
+ *  controllers capabilities.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** reg_ba_include : R/W; bitpos: [1]; default: 0;
+         *  This bit is used to include I3C broadcast address(0x7E) for private transfer.(If
+         *  I3C broadcast address is not include for the private transfer, In-Band Interrupts
+         *  driven from Slaves may not win address arbitration. Hence IBIs will get delayed)
+         */
+        uint32_t reg_ba_include:1;
+        /** reg_trans_start : R/W; bitpos: [2]; default: 0;
+         *  Transfer Start
+         */
+        uint32_t reg_trans_start:1;
+        /** reg_clk_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        /** reg_ibi_rstart_trans_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_rstart_trans_en:1;
+        /** reg_auto_dis_ibi_en : R/W; bitpos: [5]; default: 1;
+         *  NA
+         */
+        uint32_t reg_auto_dis_ibi_en:1;
+        /** reg_dma_rx_en : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma_rx_en:1;
+        /** reg_dma_tx_en : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma_tx_en:1;
+        /** reg_multi_slv_single_ccc_en : R/W; bitpos: [8]; default: 0;
+         *  0: rx high bit first, 1: rx low bit first
+         */
+        uint32_t reg_multi_slv_single_ccc_en:1;
+        /** reg_rx_bit_order : R/W; bitpos: [9]; default: 0;
+         *  0: rx low byte fist, 1: rx high byte first
+         */
+        uint32_t reg_rx_bit_order:1;
+        /** reg_rx_byte_order : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rx_byte_order:1;
+        /** reg_scl_pullup_force_en : R/W; bitpos: [11]; default: 0;
+         *  This bit is used to force scl_pullup_en
+         */
+        uint32_t reg_scl_pullup_force_en:1;
+        /** reg_scl_oe_force_en : R/W; bitpos: [12]; default: 1;
+         *  This bit is used to force scl_oe
+         */
+        uint32_t reg_scl_oe_force_en:1;
+        /** reg_sda_pp_rd_pullup_en : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sda_pp_rd_pullup_en:1;
+        /** reg_sda_rd_tbit_hlvl_pullup_en : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sda_rd_tbit_hlvl_pullup_en:1;
+        /** reg_sda_pp_wr_pullup_en : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sda_pp_wr_pullup_en:1;
+        /** reg_data_byte_cnt_unlatch : R/W; bitpos: [16]; default: 0;
+         *  1: read current real-time updated value  0: read latch data byte cnt value
+         */
+        uint32_t reg_data_byte_cnt_unlatch:1;
+        /** reg_mem_clk_force_on : R/W; bitpos: [17]; default: 0;
+         *  1: dev characteristic and address table memory clk  date force on . 0 :  clock
+         *  gating by rd/wr.
+         */
+        uint32_t reg_mem_clk_force_on:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} i3c_mst_device_ctrl_reg_t;
+
+
+/** Group: I3C BUFFER THLD CTRL REG */
+/** Type of buffer_thld_ctrl register
+ *  In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C
+ *  controller generates an IBI status. This field controls the number of IBI status
+ *  entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt.
+ */
+typedef union {
+    struct {
+        /** reg_cmd_buf_empty_thld : R/W; bitpos: [3:0]; default: 1;
+         *  Command Buffer Empty Threshold Value is used to control the number of empty
+         *  locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT
+         *  interrupt.
+         */
+        uint32_t reg_cmd_buf_empty_thld:4;
+        uint32_t reserved_4:2;
+        /** reg_resp_buf_thld : R/W; bitpos: [8:6]; default: 1;
+         *  Response Buffer Threshold Value is used to control the number of entries in the
+         *  Response Buffer that trigger the RESP_READY_STAT_INTR.
+         */
+        uint32_t reg_resp_buf_thld:3;
+        uint32_t reserved_9:3;
+        /** reg_ibi_data_buf_thld : R/W; bitpos: [14:12]; default: 1;
+         *  In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C
+         *  controller generates an IBI status. This field controls the number of IBI data
+         *  entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt.
+         */
+        uint32_t reg_ibi_data_buf_thld:3;
+        uint32_t reserved_15:3;
+        /** reg_ibi_status_buf_thld : R/W; bitpos: [20:18]; default: 1;
+         *  NA
+         */
+        uint32_t reg_ibi_status_buf_thld:3;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i3c_mst_buffer_thld_ctrl_reg_t;
+
+
+/** Group: I3C DATA BUFFER THLD CTRL REG */
+/** Type of data_buffer_thld_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tx_data_buf_thld : R/W; bitpos: [2:0]; default: 1;
+         *  Transmit Buffer Threshold Value. This field controls the number of empty locations
+         *  in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values:
+         *  000:2  001:4  010:8  011:16  100:31, else:31
+         */
+        uint32_t reg_tx_data_buf_thld:3;
+        /** reg_rx_data_buf_thld : R/W; bitpos: [5:3]; default: 1;
+         *  Receive Buffer Threshold Value. This field controls the number of empty locations
+         *  in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2  001:4
+         *  010:8  011:16  100:31, else:31
+         */
+        uint32_t reg_rx_data_buf_thld:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i3c_mst_data_buffer_thld_ctrl_reg_t;
+
+
+/** Group: I3C IBI NOTIFY CTRL REG */
+/** Type of ibi_notify_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** reg_notify_sir_rejected : R/W; bitpos: [2]; default: 0;
+         *  Notify Rejected Slave Interrupt Request Control. This bit is used to suppress
+         *  reporting to the application about Slave Interrupt Request. 0:Suppress passing the
+         *  IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request
+         *  is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI
+         *  Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed
+         *  and auto-disabled based on the IBI_SIR_REQ_REJECT registerl.
+         */
+        uint32_t reg_notify_sir_rejected:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} i3c_mst_ibi_notify_ctrl_reg_t;
+
+
+/** Group: I3C IBI SIR REQ PAYLOAD REG */
+/** Type of ibi_sir_req_payload register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sir_req_payload : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_sir_req_payload:32;
+    };
+    uint32_t val;
+} i3c_mst_ibi_sir_req_payload_reg_t;
+
+
+/** Group: I3C IBI SIR REQ REJECT REG */
+/** Type of ibi_sir_req_reject register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sir_req_reject : R/W; bitpos: [31:0]; default: 0;
+         *  The application of controller can decide whether to send ACK or NACK for Slave
+         *  request received from any I3C device. A device specific response control bit is
+         *  provided to select the response option, Master will ACK/NACK the Master Request
+         *  based on programming of control bit, corresponding to the interrupting device.
+         *  0:ACK the SIR Request  1:NACK and send direct auto disable CCC
+         */
+        uint32_t reg_sir_req_reject:32;
+    };
+    uint32_t val;
+} i3c_mst_ibi_sir_req_reject_reg_t;
+
+
+/** Group: I3C INT CLR REG */
+/** Type of int_clr register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_thld_int_clr : WT; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t tx_data_buf_thld_int_clr:1;
+        /** rx_data_buf_thld_int_clr : WT; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t rx_data_buf_thld_int_clr:1;
+        /** ibi_status_thld_int_clr : WT; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_thld_int_clr:1;
+        /** cmd_buf_empty_thld_int_clr : WT; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_buf_empty_thld_int_clr:1;
+        /** resp_ready_int_clr : WT; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t resp_ready_int_clr:1;
+        /** nxt_cmd_req_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t nxt_cmd_req_err_int_clr:1;
+        /** transfer_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_err_int_clr:1;
+        /** transfer_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_complete_int_clr:1;
+        /** command_done_int_clr : WT; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t command_done_int_clr:1;
+        /** detect_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t detect_start_int_clr:1;
+        /** resp_buf_ovf_int_clr : WT; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t resp_buf_ovf_int_clr:1;
+        /** ibi_data_buf_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data_buf_ovf_int_clr:1;
+        /** ibi_status_buf_ovf_int_clr : WT; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_buf_ovf_int_clr:1;
+        /** ibi_handle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_handle_done_int_clr:1;
+        /** ibi_detect_int_clr : WT; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_detect_int_clr:1;
+        /** cmd_ccc_mismatch_int_clr : WT; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_ccc_mismatch_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_int_clr_reg_t;
+
+
+/** Group: I3C INT RAW REG */
+/** Type of int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_thld_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t tx_data_buf_thld_int_raw:1;
+        /** rx_data_buf_thld_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t rx_data_buf_thld_int_raw:1;
+        /** ibi_status_thld_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_thld_int_raw:1;
+        /** cmd_buf_empty_thld_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
+         *  NA
+         */
+        uint32_t cmd_buf_empty_thld_int_raw:1;
+        /** resp_ready_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t resp_ready_int_raw:1;
+        /** nxt_cmd_req_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t nxt_cmd_req_err_int_raw:1;
+        /** transfer_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_err_int_raw:1;
+        /** transfer_complete_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_complete_int_raw:1;
+        /** command_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t command_done_int_raw:1;
+        /** detect_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t detect_start_int_raw:1;
+        /** resp_buf_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t resp_buf_ovf_int_raw:1;
+        /** ibi_data_buf_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data_buf_ovf_int_raw:1;
+        /** ibi_status_buf_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_buf_ovf_int_raw:1;
+        /** ibi_handle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_handle_done_int_raw:1;
+        /** ibi_detect_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_detect_int_raw:1;
+        /** cmd_ccc_mismatch_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_ccc_mismatch_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_int_raw_reg_t;
+
+
+/** Group: I3C INT ST REG */
+/** Type of int_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_thld_int_st : RO; bitpos: [0]; default: 0;
+         *  This interrupt is generated when number of empty locations in transmit buffer is
+         *  greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in
+         *  DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+         *  number of empty locations in transmit buffer is less than threshold value.
+         */
+        uint32_t tx_data_buf_thld_int_st:1;
+        /** rx_data_buf_thld_int_st : RO; bitpos: [1]; default: 0;
+         *  This interrupt is generated when number of entries in receive buffer is greater
+         *  than or equal to threshold value specified by RX_BUF_THLD field in
+         *  DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+         *  number of entries in receive buffer is less than threshold value.
+         */
+        uint32_t rx_data_buf_thld_int_st:1;
+        /** ibi_status_thld_int_st : RO; bitpos: [2]; default: 0;
+         *  Only used in master mode. This interrupt is generated when number of entries in IBI
+         *  buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field
+         *  in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when
+         *  number of entries in IBI buffer is less than threshold value.
+         */
+        uint32_t ibi_status_thld_int_st:1;
+        /** cmd_buf_empty_thld_int_st : RO; bitpos: [3]; default: 0;
+         *  This interrupt is generated when number of empty locations in command buffer is
+         *  greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in
+         *  BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number
+         *  of empty locations in command buffer is less than threshold value.
+         */
+        uint32_t cmd_buf_empty_thld_int_st:1;
+        /** resp_ready_int_st : RO; bitpos: [4]; default: 0;
+         *  This interrupt is generated when number of entries in response buffer is greater
+         *  than or equal to threshold value specified by RESP_BUF_THLD field in
+         *  BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number
+         *  of entries in response buffer is less than threshold value.
+         */
+        uint32_t resp_ready_int_st:1;
+        /** nxt_cmd_req_err_int_st : RO; bitpos: [5]; default: 0;
+         *  This interrupt is generated if toc is 0(master will restart next command), but
+         *  command buf is empty.
+         */
+        uint32_t nxt_cmd_req_err_int_st:1;
+        /** transfer_err_int_st : RO; bitpos: [6]; default: 0;
+         *  This interrupt is generated if any error occurs during transfer. The error type
+         *  will be specified in the response packet associated with the command (in ERR_STATUS
+         *  field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1.
+         */
+        uint32_t transfer_err_int_st:1;
+        /** transfer_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_complete_int_st:1;
+        /** command_done_int_st : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t command_done_int_st:1;
+        /** detect_start_int_st : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t detect_start_int_st:1;
+        /** resp_buf_ovf_int_st : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t resp_buf_ovf_int_st:1;
+        /** ibi_data_buf_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data_buf_ovf_int_st:1;
+        /** ibi_status_buf_ovf_int_st : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_buf_ovf_int_st:1;
+        /** ibi_handle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_handle_done_int_st:1;
+        /** ibi_detect_int_st : RO; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_detect_int_st:1;
+        /** cmd_ccc_mismatch_int_st : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_ccc_mismatch_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_int_st_reg_t;
+
+
+/** Group: I3C INT ST ENA REG */
+/** Type of int_st_ena register
+ *  The Interrupt status will be updated in INTR_STATUS register if corresponding
+ *  Status Enable bit set.
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_thld_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Transmit Buffer threshold status enable.
+         */
+        uint32_t tx_data_buf_thld_int_ena:1;
+        /** rx_data_buf_thld_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Receive Buffer threshold status enable.
+         */
+        uint32_t rx_data_buf_thld_int_ena:1;
+        /** ibi_status_thld_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Only used in master mode. IBI Buffer threshold status enable.
+         */
+        uint32_t ibi_status_thld_int_ena:1;
+        /** cmd_buf_empty_thld_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Command buffer ready status enable.
+         */
+        uint32_t cmd_buf_empty_thld_int_ena:1;
+        /** resp_ready_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Response buffer ready status enable.
+         */
+        uint32_t resp_ready_int_ena:1;
+        /** nxt_cmd_req_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  next command request error status enable
+         */
+        uint32_t nxt_cmd_req_err_int_ena:1;
+        /** transfer_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Transfer error status enable
+         */
+        uint32_t transfer_err_int_ena:1;
+        /** transfer_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t transfer_complete_int_ena:1;
+        /** command_done_int_ena : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t command_done_int_ena:1;
+        /** detect_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t detect_start_int_ena:1;
+        /** resp_buf_ovf_int_ena : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t resp_buf_ovf_int_ena:1;
+        /** ibi_data_buf_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_data_buf_ovf_int_ena:1;
+        /** ibi_status_buf_ovf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_status_buf_ovf_int_ena:1;
+        /** ibi_handle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_handle_done_int_ena:1;
+        /** ibi_detect_int_ena : R/W; bitpos: [14]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_detect_int_ena:1;
+        /** cmd_ccc_mismatch_int_ena : R/W; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_ccc_mismatch_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_int_st_ena_reg_t;
+
+
+/** Group: I3C RESET CTRL REG */
+/** Type of reset_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core_soft_rst : WT; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_core_soft_rst:1;
+        /** reg_cmd_buf_rst : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cmd_buf_rst:1;
+        /** reg_resp_buf_rst : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_resp_buf_rst:1;
+        /** reg_tx_data_buf_buf_rst : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_tx_data_buf_buf_rst:1;
+        /** reg_rx_data_buf_rst : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rx_data_buf_rst:1;
+        /** reg_ibi_data_buf_rst : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_data_buf_rst:1;
+        /** reg_ibi_status_buf_rst : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_status_buf_rst:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} i3c_mst_reset_ctrl_reg_t;
+
+
+/** Group: I3C BUFFER STATUS LEVEL REG */
+/** Type of buffer_status_level register
+ *  BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller.
+ */
+typedef union {
+    struct {
+        /** cmd_buf_empty_cnt : RO; bitpos: [4:0]; default: 16;
+         *  Command Buffer Empty Locations contains the number of empty locations in the
+         *  command buffer.
+         */
+        uint32_t cmd_buf_empty_cnt:5;
+        uint32_t reserved_5:3;
+        /** resp_buf_cnt : RO; bitpos: [11:8]; default: 0;
+         *  Response Buffer Level Value contains the number of valid data entries in the
+         *  response buffer.
+         */
+        uint32_t resp_buf_cnt:4;
+        uint32_t reserved_12:4;
+        /** ibi_data_buf_cnt : RO; bitpos: [19:16]; default: 0;
+         *  IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This
+         *  is field is used in master mode.
+         */
+        uint32_t ibi_data_buf_cnt:4;
+        uint32_t reserved_20:4;
+        /** ibi_status_buf_cnt : RO; bitpos: [27:24]; default: 0;
+         *  IBI Buffer Status Count contains the number of IBI status entries in the IBI
+         *  Buffer. This field is used in master mode.
+         */
+        uint32_t ibi_status_buf_cnt:4;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i3c_mst_buffer_status_level_reg_t;
+
+
+/** Group: I3C DATA BUFFER STATUS LEVEL REG */
+/** Type of data_buffer_status_level register
+ *  DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller.
+ */
+typedef union {
+    struct {
+        /** tx_data_buf_empty_cnt : RO; bitpos: [5:0]; default: 32;
+         *  Transmit Buffer Empty Level Value contains the number of empty locations in the
+         *  transmit Buffer.
+         */
+        uint32_t tx_data_buf_empty_cnt:6;
+        uint32_t reserved_6:10;
+        /** rx_data_buf_cnt : RO; bitpos: [21:16]; default: 0;
+         *  Receive Buffer Level value contains the number of valid data entries in the receive
+         *  buffer.
+         */
+        uint32_t rx_data_buf_cnt:6;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} i3c_mst_data_buffer_status_level_reg_t;
+
+
+/** Group: I3C PRESENT STATE0 REG */
+/** Type of present_state0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sda_lvl : RO; bitpos: [0]; default: 1;
+         *  This bit is used to check the SCL line level to recover from error and  for
+         *  debugging. This bit reflects the value of synchronized scl_in_a.
+         */
+        uint32_t sda_lvl:1;
+        /** scl_lvl : RO; bitpos: [1]; default: 1;
+         *  This bit is used to check the SDA line level to recover from error and  for
+         *  debugging. This bit reflects the value of synchronized sda_in_a.
+         */
+        uint32_t scl_lvl:1;
+        /** bus_busy : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t bus_busy:1;
+        /** bus_free : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t bus_free:1;
+        uint32_t reserved_4:5;
+        /** cmd_tid : RO; bitpos: [12:9]; default: 0;
+         *  NA
+         */
+        uint32_t cmd_tid:4;
+        /** scl_gen_fsm_state : RO; bitpos: [15:13]; default: 0;
+         *  NA
+         */
+        uint32_t scl_gen_fsm_state:3;
+        /** ibi_ev_handle_fsm_state : RO; bitpos: [18:16]; default: 0;
+         *  NA
+         */
+        uint32_t ibi_ev_handle_fsm_state:3;
+        /** i2c_mode_fsm_state : RO; bitpos: [21:19]; default: 0;
+         *  NA
+         */
+        uint32_t i2c_mode_fsm_state:3;
+        /** sdr_mode_fsm_state : RO; bitpos: [25:22]; default: 0;
+         *  NA
+         */
+        uint32_t sdr_mode_fsm_state:4;
+        /** daa_mode_fsm_state : RO; bitpos: [28:26]; default: 0;
+         *  Reflects whether the Master Controller is in IDLE or not. This bit will be set when
+         *  all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the
+         *  Master State machine is in idle state. 0X0: not in idle  0x1: in idle
+         */
+        uint32_t daa_mode_fsm_state:3;
+        /** main_fsm_state : RO; bitpos: [31:29]; default: 0;
+         *  NA
+         */
+        uint32_t main_fsm_state:3;
+    };
+    uint32_t val;
+} i3c_mst_present_state0_reg_t;
+
+
+/** Group: I3C PRESENT STATE1 REG */
+/** Type of present_state1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** data_byte_cnt : RO; bitpos: [15:0]; default: 0;
+         *  Present transfer data byte cnt: tx data byte cnt if write  rx data byte cnt if read
+         *  ibi data byte cnt if IBI handle.
+         */
+        uint32_t data_byte_cnt:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_present_state1_reg_t;
+
+
+/** Group: I3C DEVICE TABLE REG */
+/** Type of device_table register
+ *  Pointer for Device Address Table
+ */
+typedef union {
+    struct {
+        /** reg_dct_daa_init_index : R/W; bitpos: [3:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_dct_daa_init_index:4;
+        /** reg_dat_daa_init_index : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dat_daa_init_index:4;
+        /** present_dct_index : RO; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t present_dct_index:4;
+        /** present_dat_index : RO; bitpos: [15:12]; default: 0;
+         *  NA
+         */
+        uint32_t present_dat_index:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_device_table_reg_t;
+
+
+/** Group: I3C TIME OUT VALUE REG */
+/** Type of time_out_value register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_resp_buf_to_value : R/W; bitpos: [4:0]; default: 16;
+         *  NA
+         */
+        uint32_t reg_resp_buf_to_value:5;
+        /** reg_resp_buf_to_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_resp_buf_to_en:1;
+        /** reg_ibi_data_buf_to_value : R/W; bitpos: [10:6]; default: 16;
+         *  NA
+         */
+        uint32_t reg_ibi_data_buf_to_value:5;
+        /** reg_ibi_data_buf_to_en : R/W; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_data_buf_to_en:1;
+        /** reg_ibi_status_buf_to_value : R/W; bitpos: [16:12]; default: 16;
+         *  NA
+         */
+        uint32_t reg_ibi_status_buf_to_value:5;
+        /** reg_ibi_status_buf_to_en : R/W; bitpos: [17]; default: 0;
+         *  NA
+         */
+        uint32_t reg_ibi_status_buf_to_en:1;
+        /** reg_rx_data_buf_to_value : R/W; bitpos: [22:18]; default: 16;
+         *  NA
+         */
+        uint32_t reg_rx_data_buf_to_value:5;
+        /** reg_rx_data_buf_to_en : R/W; bitpos: [23]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rx_data_buf_to_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} i3c_mst_time_out_value_reg_t;
+
+
+/** Group: I3C SCL I3C OD TIME REG */
+/** Type of scl_i3c_mst_od_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_od_low_period : R/W; bitpos: [15:0]; default: 25;
+         *  SCL Open-Drain low count for I3C transfers targeted to I3C devices.
+         */
+        uint32_t reg_i3c_mst_od_low_period:16;
+        /** reg_i3c_mst_od_high_period : R/W; bitpos: [31:16]; default: 5;
+         *  SCL Open-Drain High count for I3C transfers targeted to I3C devices.
+         */
+        uint32_t reg_i3c_mst_od_high_period:16;
+    };
+    uint32_t val;
+} i3c_mst_scl_i3c_mst_od_time_reg_t;
+
+
+/** Group: I3C SCL I3C PP TIME REG */
+/** Type of scl_i3c_mst_pp_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_pp_low_period : R/W; bitpos: [7:0]; default: 5;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_pp_low_period:8;
+        uint32_t reserved_8:8;
+        /** reg_i3c_mst_pp_high_period : R/W; bitpos: [23:16]; default: 5;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_pp_high_period:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} i3c_mst_scl_i3c_mst_pp_time_reg_t;
+
+
+/** Group: I3C SCL I2C FM TIME REG */
+/** Type of scl_i2c_fm_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i2c_fm_low_period : R/W; bitpos: [15:0]; default: 163;
+         *  NA
+         */
+        uint32_t reg_i2c_fm_low_period:16;
+        /** reg_i2c_fm_high_period : R/W; bitpos: [31:16]; default: 75;
+         *  The SCL open-drain low count timing for I2C Fast Mode transfers.
+         */
+        uint32_t reg_i2c_fm_high_period:16;
+    };
+    uint32_t val;
+} i3c_mst_scl_i2c_fm_time_reg_t;
+
+
+/** Group: I3C SCL I2C FMP TIME REG */
+/** Type of scl_i2c_fmp_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i2c_fmp_low_period : R/W; bitpos: [15:0]; default: 63;
+         *  NA
+         */
+        uint32_t reg_i2c_fmp_low_period:16;
+        /** reg_i2c_fmp_high_period : R/W; bitpos: [23:16]; default: 33;
+         *  NA
+         */
+        uint32_t reg_i2c_fmp_high_period:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} i3c_mst_scl_i2c_fmp_time_reg_t;
+
+
+/** Group: I3C SCL EXT LOW TIME REG */
+/** Type of scl_ext_low_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_ext_low_period1 : R/W; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_ext_low_period1:8;
+        /** reg_i3c_mst_ext_low_period2 : R/W; bitpos: [15:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_ext_low_period2:8;
+        /** reg_i3c_mst_ext_low_period3 : R/W; bitpos: [23:16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_ext_low_period3:8;
+        /** reg_i3c_mst_ext_low_period4 : R/W; bitpos: [31:24]; default: 0;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_ext_low_period4:8;
+    };
+    uint32_t val;
+} i3c_mst_scl_ext_low_time_reg_t;
+
+
+/** Group: I3C SDA SAMPLE TIME REG */
+/** Type of sda_sample_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sda_od_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  It is used to adjust sda sample point when scl high under open drain speed
+         */
+        uint32_t reg_sda_od_sample_time:9;
+        /** reg_sda_pp_sample_time : R/W; bitpos: [13:9]; default: 0;
+         *  It is used to adjust sda sample point when scl high under push pull speed
+         */
+        uint32_t reg_sda_pp_sample_time:5;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i3c_mst_sda_sample_time_reg_t;
+
+
+/** Group: I3C SDA HOLD TIME REG */
+/** Type of sda_hold_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sda_od_tx_hold_time : R/W; bitpos: [8:0]; default: 1;
+         *  It is used to adjust sda drive point after scl neg under open drain speed
+         */
+        uint32_t reg_sda_od_tx_hold_time:9;
+        /** reg_sda_pp_tx_hold_time : R/W; bitpos: [13:9]; default: 0;
+         *  It is used to adjust sda dirve point after scl neg under push pull speed
+         */
+        uint32_t reg_sda_pp_tx_hold_time:5;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i3c_mst_sda_hold_time_reg_t;
+
+
+/** Group: I3C SCL START HOLD REG */
+/** Type of scl_start_hold register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  I2C_SCL_START_HOLD_TIME
+         */
+        uint32_t reg_scl_start_hold_time:9;
+        /** reg_start_det_hold_time : R/W; bitpos: [10:9]; default: 0;
+         *  NA
+         */
+        uint32_t reg_start_det_hold_time:2;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} i3c_mst_scl_start_hold_reg_t;
+
+
+/** Group: I3C SCL RSTART SETUP REG */
+/** Type of scl_rstart_setup register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  I2C_SCL_RSTART_SETUP_TIME
+         */
+        uint32_t reg_scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i3c_mst_scl_rstart_setup_reg_t;
+
+
+/** Group: I3C SCL STOP HOLD REG */
+/** Type of scl_stop_hold register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  I2C_SCL_STOP_HOLD_TIME
+         */
+        uint32_t reg_scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i3c_mst_scl_stop_hold_reg_t;
+
+
+/** Group: I3C SCL STOP SETUP REG */
+/** Type of scl_stop_setup register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  I2C_SCL_STOP_SETUP_TIME
+         */
+        uint32_t reg_scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i3c_mst_scl_stop_setup_reg_t;
+
+
+/** Group: I3C BUS FREE TIME REG */
+/** Type of bus_free_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_bus_free_time : R/W; bitpos: [15:0]; default: 5;
+         *  I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus
+         *  System, this field represents tCAS.  In Mixed Bus System, this field is expected to
+         *  be programmed to tLOW of I2C Timing.
+         */
+        uint32_t reg_bus_free_time:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_mst_bus_free_time_reg_t;
+
+
+/** Group: I3C SCL TERMN T EXT LOW TIME REG */
+/** Type of scl_termn_t_ext_low_time register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_termn_t_ext_low_time : R/W; bitpos: [7:0]; default: 2;
+         *  NA
+         */
+        uint32_t reg_i3c_mst_termn_t_ext_low_time:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i3c_mst_scl_termn_t_ext_low_time_reg_t;
+
+
+/** Group: I3C VER ID REG */
+/** Type of ver_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_ver_id : R/W; bitpos: [31:0]; default: 539165956;
+         *  This field indicates the controller current release number that is read by an
+         *  application.
+         */
+        uint32_t reg_i3c_mst_ver_id:32;
+    };
+    uint32_t val;
+} i3c_mst_ver_id_reg_t;
+
+
+/** Group: I3C VER TYPE REG */
+/** Type of ver_type register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_ver_type : R/W; bitpos: [31:0]; default: 0;
+         *  This field indicates the controller current release type that is read by an
+         *  application.
+         */
+        uint32_t reg_i3c_mst_ver_type:32;
+    };
+    uint32_t val;
+} i3c_mst_ver_type_reg_t;
+
+
+/** Group: I3C FPGA DEBUG PROBE REG */
+/** Type of fpga_debug_probe register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_i3c_mst_fpga_debug_probe : R/W; bitpos: [31:0]; default: 1;
+         *  For Debug Probe Test on FPGA
+         */
+        uint32_t reg_i3c_mst_fpga_debug_probe:32;
+    };
+    uint32_t val;
+} i3c_mst_fpga_debug_probe_reg_t;
+
+
+/** Group: I3C RND ECO CS REG */
+/** Type of rnd_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rnd_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rnd_eco_en:1;
+        /** rnd_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t rnd_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} i3c_mst_rnd_eco_cs_reg_t;
+
+
+/** Group: I3C RND ECO LOW REG */
+/** Type of rnd_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rnd_eco_low:32;
+    };
+    uint32_t val;
+} i3c_mst_rnd_eco_low_reg_t;
+
+
+/** Group: I3C RND ECO HIGH REG */
+/** Type of rnd_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rnd_eco_high : R/W; bitpos: [31:0]; default: 65535;
+         *  NA
+         */
+        uint32_t reg_rnd_eco_high:32;
+    };
+    uint32_t val;
+} i3c_mst_rnd_eco_high_reg_t;
+
+
+typedef struct i3c_mst_dev_t {
+    volatile i3c_mst_device_ctrl_reg_t device_ctrl;
+    uint32_t reserved_004[6];
+    volatile i3c_mst_buffer_thld_ctrl_reg_t buffer_thld_ctrl;
+    volatile i3c_mst_data_buffer_thld_ctrl_reg_t data_buffer_thld_ctrl;
+    volatile i3c_mst_ibi_notify_ctrl_reg_t ibi_notify_ctrl;
+    volatile i3c_mst_ibi_sir_req_payload_reg_t ibi_sir_req_payload;
+    volatile i3c_mst_ibi_sir_req_reject_reg_t ibi_sir_req_reject;
+    volatile i3c_mst_int_clr_reg_t int_clr;
+    volatile i3c_mst_int_raw_reg_t int_raw;
+    volatile i3c_mst_int_st_reg_t int_st;
+    volatile i3c_mst_int_st_ena_reg_t int_st_ena;
+    uint32_t reserved_040;
+    volatile i3c_mst_reset_ctrl_reg_t reset_ctrl;
+    volatile i3c_mst_buffer_status_level_reg_t buffer_status_level;
+    volatile i3c_mst_data_buffer_status_level_reg_t data_buffer_status_level;
+    volatile i3c_mst_present_state0_reg_t present_state0;
+    volatile i3c_mst_present_state1_reg_t present_state1;
+    volatile i3c_mst_device_table_reg_t device_table;
+    volatile i3c_mst_time_out_value_reg_t time_out_value;
+    volatile i3c_mst_scl_i3c_mst_od_time_reg_t scl_i3c_mst_od_time;
+    volatile i3c_mst_scl_i3c_mst_pp_time_reg_t scl_i3c_mst_pp_time;
+    volatile i3c_mst_scl_i2c_fm_time_reg_t scl_i2c_fm_time;
+    volatile i3c_mst_scl_i2c_fmp_time_reg_t scl_i2c_fmp_time;
+    volatile i3c_mst_scl_ext_low_time_reg_t scl_ext_low_time;
+    volatile i3c_mst_sda_sample_time_reg_t sda_sample_time;
+    volatile i3c_mst_sda_hold_time_reg_t sda_hold_time;
+    volatile i3c_mst_scl_start_hold_reg_t scl_start_hold;
+    volatile i3c_mst_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i3c_mst_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i3c_mst_scl_stop_setup_reg_t scl_stop_setup;
+    uint32_t reserved_08c;
+    volatile i3c_mst_bus_free_time_reg_t bus_free_time;
+    volatile i3c_mst_scl_termn_t_ext_low_time_reg_t scl_termn_t_ext_low_time;
+    uint32_t reserved_098[2];
+    volatile i3c_mst_ver_id_reg_t ver_id;
+    volatile i3c_mst_ver_type_reg_t ver_type;
+    uint32_t reserved_0a8;
+    volatile i3c_mst_fpga_debug_probe_reg_t fpga_debug_probe;
+    volatile i3c_mst_rnd_eco_cs_reg_t rnd_eco_cs;
+    volatile i3c_mst_rnd_eco_low_reg_t rnd_eco_low;
+    volatile i3c_mst_rnd_eco_high_reg_t rnd_eco_high;
+} i3c_mst_dev_t;
+
+extern i3c_mst_dev_t I3C_MST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i3c_mst_dev_t) == 0xbc, "Invalid size of i3c_mst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i3c_slv_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/i3c_slv_reg.h
new file mode 100644
index 0000000000..00343ef2f9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i3c_slv_reg.h
@@ -0,0 +1,585 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I3C_SLV_CONFIG_REG register
+ *  NA
+ */
+#define I3C_SLV_CONFIG_REG (DR_REG_I3C_SLV_BASE + 0x4)
+/** I3C_SLV_SLVENA : R/W; bitpos: [0]; default: 1;
+ *  1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus.
+ *  This should be not set until registers such as PARTNO, IDEXT and the like are set
+ *  1st  -if used- since they impact data to the master
+ */
+#define I3C_SLV_SLVENA    (BIT(0))
+#define I3C_SLV_SLVENA_M  (I3C_SLV_SLVENA_V << I3C_SLV_SLVENA_S)
+#define I3C_SLV_SLVENA_V  0x00000001U
+#define I3C_SLV_SLVENA_S  0
+/** I3C_SLV_NACK : R/W; bitpos: [1]; default: 0;
+ *  1:the slave will NACK all requests to it except CCC broadcast. This should be used
+ *  with caution as the Master may determine the slave is missing if overused.
+ */
+#define I3C_SLV_NACK    (BIT(1))
+#define I3C_SLV_NACK_M  (I3C_SLV_NACK_V << I3C_SLV_NACK_S)
+#define I3C_SLV_NACK_V  0x00000001U
+#define I3C_SLV_NACK_S  1
+/** I3C_SLV_MATCHSS : R/W; bitpos: [2]; default: 0;
+ *  1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This
+ *  allows START and STOP to be used to detect end of a message to /from this slave.
+ */
+#define I3C_SLV_MATCHSS    (BIT(2))
+#define I3C_SLV_MATCHSS_M  (I3C_SLV_MATCHSS_V << I3C_SLV_MATCHSS_S)
+#define I3C_SLV_MATCHSS_V  0x00000001U
+#define I3C_SLV_MATCHSS_S  2
+/** I3C_SLV_S0IGNORE : R/W; bitpos: [3]; default: 0;
+ *  If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an
+ *  Exit Pattern. This should only be used when the bus will not use HDR.
+ */
+#define I3C_SLV_S0IGNORE    (BIT(3))
+#define I3C_SLV_S0IGNORE_M  (I3C_SLV_S0IGNORE_V << I3C_SLV_S0IGNORE_S)
+#define I3C_SLV_S0IGNORE_V  0x00000001U
+#define I3C_SLV_S0IGNORE_S  3
+/** I3C_SLV_DDROK : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_DDROK    (BIT(4))
+#define I3C_SLV_DDROK_M  (I3C_SLV_DDROK_V << I3C_SLV_DDROK_S)
+#define I3C_SLV_DDROK_V  0x00000001U
+#define I3C_SLV_DDROK_S  4
+/** I3C_SLV_IDRAND : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_IDRAND    (BIT(8))
+#define I3C_SLV_IDRAND_M  (I3C_SLV_IDRAND_V << I3C_SLV_IDRAND_S)
+#define I3C_SLV_IDRAND_V  0x00000001U
+#define I3C_SLV_IDRAND_S  8
+/** I3C_SLV_OFFLINE : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_OFFLINE    (BIT(9))
+#define I3C_SLV_OFFLINE_M  (I3C_SLV_OFFLINE_V << I3C_SLV_OFFLINE_S)
+#define I3C_SLV_OFFLINE_V  0x00000001U
+#define I3C_SLV_OFFLINE_S  9
+/** I3C_SLV_BAMATCH : R/W; bitpos: [23:16]; default: 47;
+ *  Bus Available condition match value for current ???Slow clock???. This provides the
+ *  count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low
+ *  when the Master is not doing so. The max width , and so max value, is controlled by
+ *  the block. Only if enabled for events such IBI or MR or HJ, and if enabled to
+ *  provide this as a register. With is limited to CLK_SLOW_BITS
+ */
+#define I3C_SLV_BAMATCH    0x000000FFU
+#define I3C_SLV_BAMATCH_M  (I3C_SLV_BAMATCH_V << I3C_SLV_BAMATCH_S)
+#define I3C_SLV_BAMATCH_V  0x000000FFU
+#define I3C_SLV_BAMATCH_S  16
+/** I3C_SLV_SADDR : R/W; bitpos: [31:25]; default: 0;
+ *  If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled
+ *  to use one and to be provided by SW. Block may provide in HW as well.
+ */
+#define I3C_SLV_SADDR    0x0000007FU
+#define I3C_SLV_SADDR_M  (I3C_SLV_SADDR_V << I3C_SLV_SADDR_S)
+#define I3C_SLV_SADDR_V  0x0000007FU
+#define I3C_SLV_SADDR_S  25
+
+/** I3C_SLV_STATUS_REG register
+ *  NA
+ */
+#define I3C_SLV_STATUS_REG (DR_REG_I3C_SLV_BASE + 0x8)
+/** I3C_SLV_STNOTSTOP : RO; bitpos: [0]; default: 0;
+ *  Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also
+ *  set when busy. Note that this can also be true from an S0 or S1 error, which waits
+ *  for an Exit Pattern.
+ */
+#define I3C_SLV_STNOTSTOP    (BIT(0))
+#define I3C_SLV_STNOTSTOP_M  (I3C_SLV_STNOTSTOP_V << I3C_SLV_STNOTSTOP_S)
+#define I3C_SLV_STNOTSTOP_V  0x00000001U
+#define I3C_SLV_STNOTSTOP_S  0
+/** I3C_SLV_STMSG : RO; bitpos: [1]; default: 0;
+ *  Is 1 if this bus Slave is listening to the bus traffic or responding, If
+ *  STNOSTOP=1, then this will be 0 when a non-matching address seen until next
+ *  respeated START it STOP.
+ */
+#define I3C_SLV_STMSG    (BIT(1))
+#define I3C_SLV_STMSG_M  (I3C_SLV_STMSG_V << I3C_SLV_STMSG_S)
+#define I3C_SLV_STMSG_V  0x00000001U
+#define I3C_SLV_STMSG_S  1
+/** I3C_SLV_STCCCH : RO; bitpos: [2]; default: 0;
+ *  Is 1 if a CCC message is being handled automatically.
+ */
+#define I3C_SLV_STCCCH    (BIT(2))
+#define I3C_SLV_STCCCH_M  (I3C_SLV_STCCCH_V << I3C_SLV_STCCCH_S)
+#define I3C_SLV_STCCCH_V  0x00000001U
+#define I3C_SLV_STCCCH_S  2
+/** I3C_SLV_STREQRD : RO; bitpos: [3]; default: 0;
+ *  1 if the req in process is an sdr read from this slave or an IBI is being pushed
+ *  out,
+ */
+#define I3C_SLV_STREQRD    (BIT(3))
+#define I3C_SLV_STREQRD_M  (I3C_SLV_STREQRD_V << I3C_SLV_STREQRD_S)
+#define I3C_SLV_STREQRD_V  0x00000001U
+#define I3C_SLV_STREQRD_S  3
+/** I3C_SLV_STREQWR : RO; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_STREQWR    (BIT(4))
+#define I3C_SLV_STREQWR_M  (I3C_SLV_STREQWR_V << I3C_SLV_STREQWR_S)
+#define I3C_SLV_STREQWR_V  0x00000001U
+#define I3C_SLV_STREQWR_S  4
+/** I3C_SLV_STDAA : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_STDAA    (BIT(5))
+#define I3C_SLV_STDAA_M  (I3C_SLV_STDAA_V << I3C_SLV_STDAA_S)
+#define I3C_SLV_STDAA_V  0x00000001U
+#define I3C_SLV_STDAA_S  5
+/** I3C_SLV_STHDR : RO; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_STHDR    (BIT(6))
+#define I3C_SLV_STHDR_M  (I3C_SLV_STHDR_V << I3C_SLV_STHDR_S)
+#define I3C_SLV_STHDR_V  0x00000001U
+#define I3C_SLV_STHDR_S  6
+/** I3C_SLV_START : R/W; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_START    (BIT(8))
+#define I3C_SLV_START_M  (I3C_SLV_START_V << I3C_SLV_START_S)
+#define I3C_SLV_START_V  0x00000001U
+#define I3C_SLV_START_S  8
+/** I3C_SLV_MATCHED : R/W; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_MATCHED    (BIT(9))
+#define I3C_SLV_MATCHED_M  (I3C_SLV_MATCHED_V << I3C_SLV_MATCHED_S)
+#define I3C_SLV_MATCHED_V  0x00000001U
+#define I3C_SLV_MATCHED_S  9
+/** I3C_SLV_STOP : R/W; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_STOP    (BIT(10))
+#define I3C_SLV_STOP_M  (I3C_SLV_STOP_V << I3C_SLV_STOP_S)
+#define I3C_SLV_STOP_V  0x00000001U
+#define I3C_SLV_STOP_S  10
+/** I3C_SLV_RXPEND : RO; bitpos: [11]; default: 0;
+ *  Receiving a message from master,which is not being handled by block(not a CCC
+ *  internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which
+ *  defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will
+ *  self-clear if data is read(FIFO and non-FIFO)
+ */
+#define I3C_SLV_RXPEND    (BIT(11))
+#define I3C_SLV_RXPEND_M  (I3C_SLV_RXPEND_V << I3C_SLV_RXPEND_S)
+#define I3C_SLV_RXPEND_V  0x00000001U
+#define I3C_SLV_RXPEND_S  11
+/** I3C_SLV_TXNOTFULL : RO; bitpos: [12]; default: 0;
+ *  Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all
+ *  but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is
+ *  enabled for TX, it will also be signaled to provide more.
+ */
+#define I3C_SLV_TXNOTFULL    (BIT(12))
+#define I3C_SLV_TXNOTFULL_M  (I3C_SLV_TXNOTFULL_V << I3C_SLV_TXNOTFULL_S)
+#define I3C_SLV_TXNOTFULL_V  0x00000001U
+#define I3C_SLV_TXNOTFULL_S  12
+/** I3C_SLV_DACHG : R/W; bitpos: [13]; default: 0;
+ *  The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in
+ *  that state of being valid or none. Actual DA can be seen in the DYNADDR register.
+ *  Note that this will also be used when MAP Auto feature is configured. This will be
+ *  changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main
+ *  DA(0) will indicate if last change was due to Auto MAP.
+ */
+#define I3C_SLV_DACHG    (BIT(13))
+#define I3C_SLV_DACHG_M  (I3C_SLV_DACHG_V << I3C_SLV_DACHG_S)
+#define I3C_SLV_DACHG_V  0x00000001U
+#define I3C_SLV_DACHG_S  13
+/** I3C_SLV_CCC : R/W; bitpos: [14]; default: 0;
+ *  A common -command-code(CCC), not handled by block, has been received. This acts
+ *  differently between: *Broadcasted ones, which will then also correspond with RXPEND
+ *  and the 1st byte will be the CCC(command) . *Direct ones, which may never be
+ *  directed to this device.  If it is, then the TXSEND or RXPEND will be triggered
+ *  with this end the RXPEND will contain the command.
+ */
+#define I3C_SLV_CCC    (BIT(14))
+#define I3C_SLV_CCC_M  (I3C_SLV_CCC_V << I3C_SLV_CCC_S)
+#define I3C_SLV_CCC_V  0x00000001U
+#define I3C_SLV_CCC_S  14
+/** I3C_SLV_ERRWARN : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_ERRWARN    (BIT(15))
+#define I3C_SLV_ERRWARN_M  (I3C_SLV_ERRWARN_V << I3C_SLV_ERRWARN_S)
+#define I3C_SLV_ERRWARN_V  0x00000001U
+#define I3C_SLV_ERRWARN_S  15
+/** I3C_SLV_HDRMATCH : R/W; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_HDRMATCH    (BIT(16))
+#define I3C_SLV_HDRMATCH_M  (I3C_SLV_HDRMATCH_V << I3C_SLV_HDRMATCH_S)
+#define I3C_SLV_HDRMATCH_V  0x00000001U
+#define I3C_SLV_HDRMATCH_S  16
+
+/** I3C_SLV_CTRL_REG register
+ *  NA
+ */
+#define I3C_SLV_CTRL_REG (DR_REG_I3C_SLV_BASE + 0xc)
+/** I3C_SLV_SLV_EVENT : R/W; bitpos: [1:0]; default: 0;
+ *  If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will
+ *  show the status as it progresses. Once completed, the field will automatically
+ *  return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal
+ *  mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1:
+ *  start an IBI. This will try to push through an IBI on the bus. If data associate
+ *  with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is
+ *  enabled, this will include anytime control related bytes  further, the IBIDATA byte
+ *  will have bit7 set to 1.
+ */
+#define I3C_SLV_SLV_EVENT    0x00000003U
+#define I3C_SLV_SLV_EVENT_M  (I3C_SLV_SLV_EVENT_V << I3C_SLV_SLV_EVENT_S)
+#define I3C_SLV_SLV_EVENT_V  0x00000003U
+#define I3C_SLV_SLV_EVENT_S  0
+/** I3C_SLV_EXTDATA : R/W; bitpos: [3]; default: 0;
+ *  reserved
+ */
+#define I3C_SLV_EXTDATA    (BIT(3))
+#define I3C_SLV_EXTDATA_M  (I3C_SLV_EXTDATA_V << I3C_SLV_EXTDATA_S)
+#define I3C_SLV_EXTDATA_V  0x00000001U
+#define I3C_SLV_EXTDATA_S  3
+/** I3C_SLV_MAPIDX : R/W; bitpos: [7:4]; default: 0;
+ *  Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic
+ *  Address, or can be any valid index.
+ */
+#define I3C_SLV_MAPIDX    0x0000000FU
+#define I3C_SLV_MAPIDX_M  (I3C_SLV_MAPIDX_V << I3C_SLV_MAPIDX_S)
+#define I3C_SLV_MAPIDX_V  0x0000000FU
+#define I3C_SLV_MAPIDX_S  4
+/** I3C_SLV_IBIDATA : R/W; bitpos: [15:8]; default: 0;
+ *  Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is
+ *  required.
+ */
+#define I3C_SLV_IBIDATA    0x000000FFU
+#define I3C_SLV_IBIDATA_M  (I3C_SLV_IBIDATA_V << I3C_SLV_IBIDATA_S)
+#define I3C_SLV_IBIDATA_V  0x000000FFU
+#define I3C_SLV_IBIDATA_S  8
+/** I3C_SLV_PENDINT : R/W; bitpos: [19:16]; default: 0;
+ *  Should be set to the pending interrupt that GETSTATUS CCC will return. This should
+ *  be maintained by the application if used and configured, as the Master will read
+ *  this. If not configured, the GETSTATUS field will return 1 if an IBI is pending,
+ *  and 0 otherwise.
+ */
+#define I3C_SLV_PENDINT    0x0000000FU
+#define I3C_SLV_PENDINT_M  (I3C_SLV_PENDINT_V << I3C_SLV_PENDINT_S)
+#define I3C_SLV_PENDINT_V  0x0000000FU
+#define I3C_SLV_PENDINT_S  16
+/** I3C_SLV_ACTSTATE : R/W; bitpos: [21:20]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_ACTSTATE    0x00000003U
+#define I3C_SLV_ACTSTATE_M  (I3C_SLV_ACTSTATE_V << I3C_SLV_ACTSTATE_S)
+#define I3C_SLV_ACTSTATE_V  0x00000003U
+#define I3C_SLV_ACTSTATE_S  20
+/** I3C_SLV_VENDINFO : R/W; bitpos: [31:24]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_VENDINFO    0x000000FFU
+#define I3C_SLV_VENDINFO_M  (I3C_SLV_VENDINFO_V << I3C_SLV_VENDINFO_S)
+#define I3C_SLV_VENDINFO_V  0x000000FFU
+#define I3C_SLV_VENDINFO_S  24
+
+/** I3C_SLV_INTSET_REG register
+ *  INSET allows setting enables for interrupts(connecting the corresponding STATUS
+ *  source to causing an IRQ to the processor)
+ */
+#define I3C_SLV_INTSET_REG (DR_REG_I3C_SLV_BASE + 0x10)
+/** I3C_SLV_STOP_ENA : R/W; bitpos: [10]; default: 0;
+ *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+ *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+ *  relates to the state of being stopped.
+ */
+#define I3C_SLV_STOP_ENA    (BIT(10))
+#define I3C_SLV_STOP_ENA_M  (I3C_SLV_STOP_ENA_V << I3C_SLV_STOP_ENA_S)
+#define I3C_SLV_STOP_ENA_V  0x00000001U
+#define I3C_SLV_STOP_ENA_S  10
+/** I3C_SLV_RXPEND_ENA : R/W; bitpos: [11]; default: 0;
+ *  Interrupt when receiving a message from Master, which is not being handled by the
+ *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+ *  trigger. If DMA, then message end.
+ */
+#define I3C_SLV_RXPEND_ENA    (BIT(11))
+#define I3C_SLV_RXPEND_ENA_M  (I3C_SLV_RXPEND_ENA_V << I3C_SLV_RXPEND_ENA_S)
+#define I3C_SLV_RXPEND_ENA_V  0x00000001U
+#define I3C_SLV_RXPEND_ENA_S  11
+/** I3C_SLV_TXSEND_ENA : R/W; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXSEND_ENA    (BIT(12))
+#define I3C_SLV_TXSEND_ENA_M  (I3C_SLV_TXSEND_ENA_V << I3C_SLV_TXSEND_ENA_S)
+#define I3C_SLV_TXSEND_ENA_V  0x00000001U
+#define I3C_SLV_TXSEND_ENA_S  12
+
+/** I3C_SLV_INTCLR_REG register
+ *  NA
+ */
+#define I3C_SLV_INTCLR_REG (DR_REG_I3C_SLV_BASE + 0x14)
+/** I3C_SLV_STOP_CLR : WO; bitpos: [10]; default: 0;
+ *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+ *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+ *  relates to the state of being stopped.
+ */
+#define I3C_SLV_STOP_CLR    (BIT(10))
+#define I3C_SLV_STOP_CLR_M  (I3C_SLV_STOP_CLR_V << I3C_SLV_STOP_CLR_S)
+#define I3C_SLV_STOP_CLR_V  0x00000001U
+#define I3C_SLV_STOP_CLR_S  10
+/** I3C_SLV_RXPEND_CLR : WO; bitpos: [11]; default: 0;
+ *  Interrupt when receiving a message from Master, which is not being handled by the
+ *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+ *  trigger. If DMA, then message end.
+ */
+#define I3C_SLV_RXPEND_CLR    (BIT(11))
+#define I3C_SLV_RXPEND_CLR_M  (I3C_SLV_RXPEND_CLR_V << I3C_SLV_RXPEND_CLR_S)
+#define I3C_SLV_RXPEND_CLR_V  0x00000001U
+#define I3C_SLV_RXPEND_CLR_S  11
+/** I3C_SLV_TXSEND_CLR : WO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXSEND_CLR    (BIT(12))
+#define I3C_SLV_TXSEND_CLR_M  (I3C_SLV_TXSEND_CLR_V << I3C_SLV_TXSEND_CLR_S)
+#define I3C_SLV_TXSEND_CLR_V  0x00000001U
+#define I3C_SLV_TXSEND_CLR_S  12
+
+/** I3C_SLV_INTMASKED_REG register
+ *  NA
+ */
+#define I3C_SLV_INTMASKED_REG (DR_REG_I3C_SLV_BASE + 0x18)
+/** I3C_SLV_STOP_MASK : RO; bitpos: [10]; default: 0;
+ *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+ *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+ *  relates to the state of being stopped.
+ */
+#define I3C_SLV_STOP_MASK    (BIT(10))
+#define I3C_SLV_STOP_MASK_M  (I3C_SLV_STOP_MASK_V << I3C_SLV_STOP_MASK_S)
+#define I3C_SLV_STOP_MASK_V  0x00000001U
+#define I3C_SLV_STOP_MASK_S  10
+/** I3C_SLV_RXPEND_MASK : RO; bitpos: [11]; default: 0;
+ *  Interrupt when receiving a message from Master, which is not being handled by the
+ *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+ *  trigger. If DMA, then message end.
+ */
+#define I3C_SLV_RXPEND_MASK    (BIT(11))
+#define I3C_SLV_RXPEND_MASK_M  (I3C_SLV_RXPEND_MASK_V << I3C_SLV_RXPEND_MASK_S)
+#define I3C_SLV_RXPEND_MASK_V  0x00000001U
+#define I3C_SLV_RXPEND_MASK_S  11
+/** I3C_SLV_TXSEND_MASK : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXSEND_MASK    (BIT(12))
+#define I3C_SLV_TXSEND_MASK_M  (I3C_SLV_TXSEND_MASK_V << I3C_SLV_TXSEND_MASK_S)
+#define I3C_SLV_TXSEND_MASK_V  0x00000001U
+#define I3C_SLV_TXSEND_MASK_S  12
+
+/** I3C_SLV_DATACTRL_REG register
+ *  NA
+ */
+#define I3C_SLV_DATACTRL_REG (DR_REG_I3C_SLV_BASE + 0x2c)
+/** I3C_SLV_FLUSHTB : WO; bitpos: [0]; default: 0;
+ *  Flushes the from-bus buffer/FIFO. Not normally used
+ */
+#define I3C_SLV_FLUSHTB    (BIT(0))
+#define I3C_SLV_FLUSHTB_M  (I3C_SLV_FLUSHTB_V << I3C_SLV_FLUSHTB_S)
+#define I3C_SLV_FLUSHTB_V  0x00000001U
+#define I3C_SLV_FLUSHTB_S  0
+/** I3C_SLV_FLUSHFB : WO; bitpos: [1]; default: 0;
+ *  Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message
+ *  prematurely
+ */
+#define I3C_SLV_FLUSHFB    (BIT(1))
+#define I3C_SLV_FLUSHFB_M  (I3C_SLV_FLUSHFB_V << I3C_SLV_FLUSHFB_S)
+#define I3C_SLV_FLUSHFB_V  0x00000001U
+#define I3C_SLV_FLUSHFB_S  1
+/** I3C_SLV_UNLOCK : WO; bitpos: [3]; default: 0;
+ *  If this bit is not written 1, the register bits from 7 to 4 are not changed on
+ *  write.
+ */
+#define I3C_SLV_UNLOCK    (BIT(3))
+#define I3C_SLV_UNLOCK_M  (I3C_SLV_UNLOCK_V << I3C_SLV_UNLOCK_S)
+#define I3C_SLV_UNLOCK_V  0x00000001U
+#define I3C_SLV_UNLOCK_S  3
+/** I3C_SLV_TXTRIG : R/W; bitpos: [5:4]; default: 3;
+ *  Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled).
+ *  The defaults is 3
+ */
+#define I3C_SLV_TXTRIG    0x00000003U
+#define I3C_SLV_TXTRIG_M  (I3C_SLV_TXTRIG_V << I3C_SLV_TXTRIG_S)
+#define I3C_SLV_TXTRIG_V  0x00000003U
+#define I3C_SLV_TXTRIG_S  4
+/** I3C_SLV_RXTRIG : R/W; bitpos: [7:6]; default: 2;
+ *  Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled).
+ *  The defaults is 3
+ */
+#define I3C_SLV_RXTRIG    0x00000003U
+#define I3C_SLV_RXTRIG_M  (I3C_SLV_RXTRIG_V << I3C_SLV_RXTRIG_S)
+#define I3C_SLV_RXTRIG_V  0x00000003U
+#define I3C_SLV_RXTRIG_S  6
+/** I3C_SLV_TXCOUNT : RO; bitpos: [20:16]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXCOUNT    0x0000001FU
+#define I3C_SLV_TXCOUNT_M  (I3C_SLV_TXCOUNT_V << I3C_SLV_TXCOUNT_S)
+#define I3C_SLV_TXCOUNT_V  0x0000001FU
+#define I3C_SLV_TXCOUNT_S  16
+/** I3C_SLV_RXCOUNT : RO; bitpos: [28:24]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_RXCOUNT    0x0000001FU
+#define I3C_SLV_RXCOUNT_M  (I3C_SLV_RXCOUNT_V << I3C_SLV_RXCOUNT_S)
+#define I3C_SLV_RXCOUNT_V  0x0000001FU
+#define I3C_SLV_RXCOUNT_S  24
+/** I3C_SLV_TXFULL : RO; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_TXFULL    (BIT(30))
+#define I3C_SLV_TXFULL_M  (I3C_SLV_TXFULL_V << I3C_SLV_TXFULL_S)
+#define I3C_SLV_TXFULL_V  0x00000001U
+#define I3C_SLV_TXFULL_S  30
+/** I3C_SLV_RXEMPTY : RO; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_RXEMPTY    (BIT(31))
+#define I3C_SLV_RXEMPTY_M  (I3C_SLV_RXEMPTY_V << I3C_SLV_RXEMPTY_S)
+#define I3C_SLV_RXEMPTY_V  0x00000001U
+#define I3C_SLV_RXEMPTY_S  31
+
+/** I3C_SLV_WDATAB_REG register
+ *  NA
+ */
+#define I3C_SLV_WDATAB_REG (DR_REG_I3C_SLV_BASE + 0x30)
+/** I3C_SLV_WDATAB : WO; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_WDATAB    0x000000FFU
+#define I3C_SLV_WDATAB_M  (I3C_SLV_WDATAB_V << I3C_SLV_WDATAB_S)
+#define I3C_SLV_WDATAB_V  0x000000FFU
+#define I3C_SLV_WDATAB_S  0
+/** I3C_SLV_WDATA_END : WO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_WDATA_END    (BIT(8))
+#define I3C_SLV_WDATA_END_M  (I3C_SLV_WDATA_END_V << I3C_SLV_WDATA_END_S)
+#define I3C_SLV_WDATA_END_V  0x00000001U
+#define I3C_SLV_WDATA_END_S  8
+
+/** I3C_SLV_WDATABE_REG register
+ *  NA
+ */
+#define I3C_SLV_WDATABE_REG (DR_REG_I3C_SLV_BASE + 0x34)
+/** I3C_SLV_WDATABE : WO; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_WDATABE    0x000000FFU
+#define I3C_SLV_WDATABE_M  (I3C_SLV_WDATABE_V << I3C_SLV_WDATABE_S)
+#define I3C_SLV_WDATABE_V  0x000000FFU
+#define I3C_SLV_WDATABE_S  0
+
+/** I3C_SLV_RDARAB_REG register
+ *  Read Byte Data (from-bus) register
+ */
+#define I3C_SLV_RDARAB_REG (DR_REG_I3C_SLV_BASE + 0x40)
+/** I3C_SLV_DATA0 : RO; bitpos: [7:0]; default: 0;
+ *  This register allows reading a byte from the bus unless external FIFO is used. A
+ *  byte should not be read unless there is data waiting, as indicated by the RXPEND
+ *  bit being set in the STATUS register
+ */
+#define I3C_SLV_DATA0    0x000000FFU
+#define I3C_SLV_DATA0_M  (I3C_SLV_DATA0_V << I3C_SLV_DATA0_S)
+#define I3C_SLV_DATA0_V  0x000000FFU
+#define I3C_SLV_DATA0_S  0
+
+/** I3C_SLV_RDATAH_REG register
+ *  Read Half-word Data (from-bus) register
+ */
+#define I3C_SLV_RDATAH_REG (DR_REG_I3C_SLV_BASE + 0x48)
+/** I3C_SLV_DATA_LSB : RO; bitpos: [7:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_DATA_LSB    0x000000FFU
+#define I3C_SLV_DATA_LSB_M  (I3C_SLV_DATA_LSB_V << I3C_SLV_DATA_LSB_S)
+#define I3C_SLV_DATA_LSB_V  0x000000FFU
+#define I3C_SLV_DATA_LSB_S  0
+/** I3C_SLV_DATA_MSB : RO; bitpos: [15:8]; default: 0;
+ *  This register allows reading a Half-word (byte pair)  from the bus unless external
+ *  FIFO is used. A Half-word should not be read unless there is at least 2 bytes of
+ *  data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space
+ *  in the DATACTRL register
+ */
+#define I3C_SLV_DATA_MSB    0x000000FFU
+#define I3C_SLV_DATA_MSB_M  (I3C_SLV_DATA_MSB_V << I3C_SLV_DATA_MSB_S)
+#define I3C_SLV_DATA_MSB_V  0x000000FFU
+#define I3C_SLV_DATA_MSB_S  8
+
+/** I3C_SLV_CAPABILITIES2_REG register
+ *  NA
+ */
+#define I3C_SLV_CAPABILITIES2_REG (DR_REG_I3C_SLV_BASE + 0x5c)
+/** I3C_SLV_CAPABLITIES2 : RO; bitpos: [31:0]; default: 256;
+ *  NA
+ */
+#define I3C_SLV_CAPABLITIES2    0xFFFFFFFFU
+#define I3C_SLV_CAPABLITIES2_M  (I3C_SLV_CAPABLITIES2_V << I3C_SLV_CAPABLITIES2_S)
+#define I3C_SLV_CAPABLITIES2_V  0xFFFFFFFFU
+#define I3C_SLV_CAPABLITIES2_S  0
+
+/** I3C_SLV_CAPABILITIES_REG register
+ *  NA
+ */
+#define I3C_SLV_CAPABILITIES_REG (DR_REG_I3C_SLV_BASE + 0x60)
+/** I3C_SLV_CAPABLITIES : RO; bitpos: [31:0]; default: 2081684508;
+ *  NA
+ */
+#define I3C_SLV_CAPABLITIES    0xFFFFFFFFU
+#define I3C_SLV_CAPABLITIES_M  (I3C_SLV_CAPABLITIES_V << I3C_SLV_CAPABLITIES_S)
+#define I3C_SLV_CAPABLITIES_V  0xFFFFFFFFU
+#define I3C_SLV_CAPABLITIES_S  0
+
+/** I3C_SLV_IDPARTNO_REG register
+ *  NA
+ */
+#define I3C_SLV_IDPARTNO_REG (DR_REG_I3C_SLV_BASE + 0x6c)
+/** I3C_SLV_PARTNO : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_PARTNO    0xFFFFFFFFU
+#define I3C_SLV_PARTNO_M  (I3C_SLV_PARTNO_V << I3C_SLV_PARTNO_S)
+#define I3C_SLV_PARTNO_V  0xFFFFFFFFU
+#define I3C_SLV_PARTNO_S  0
+
+/** I3C_SLV_IDEXT_REG register
+ *  NA
+ */
+#define I3C_SLV_IDEXT_REG (DR_REG_I3C_SLV_BASE + 0x70)
+/** I3C_SLV_IDEXT : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define I3C_SLV_IDEXT    0xFFFFFFFFU
+#define I3C_SLV_IDEXT_M  (I3C_SLV_IDEXT_V << I3C_SLV_IDEXT_S)
+#define I3C_SLV_IDEXT_V  0xFFFFFFFFU
+#define I3C_SLV_IDEXT_S  0
+
+/** I3C_SLV_VENDORID_REG register
+ *  NA
+ */
+#define I3C_SLV_VENDORID_REG (DR_REG_I3C_SLV_BASE + 0x74)
+/** I3C_SLV_VID : R/W; bitpos: [14:0]; default: 21840;
+ *  NA
+ */
+#define I3C_SLV_VID    0x00007FFFU
+#define I3C_SLV_VID_M  (I3C_SLV_VID_V << I3C_SLV_VID_S)
+#define I3C_SLV_VID_V  0x00007FFFU
+#define I3C_SLV_VID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/i3c_slv_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/i3c_slv_struct.h
new file mode 100644
index 0000000000..dd95aff933
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/i3c_slv_struct.h
@@ -0,0 +1,550 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: I3C_SLV CONFIG REG */
+/** Type of config register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** slvena : R/W; bitpos: [0]; default: 1;
+         *  1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus.
+         *  This should be not set until registers such as PARTNO, IDEXT and the like are set
+         *  1st  -if used- since they impact data to the master
+         */
+        uint32_t slvena:1;
+        /** nack : R/W; bitpos: [1]; default: 0;
+         *  1:the slave will NACK all requests to it except CCC broadcast. This should be used
+         *  with caution as the Master may determine the slave is missing if overused.
+         */
+        uint32_t nack:1;
+        /** matchss : R/W; bitpos: [2]; default: 0;
+         *  1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This
+         *  allows START and STOP to be used to detect end of a message to /from this slave.
+         */
+        uint32_t matchss:1;
+        /** s0ignore : R/W; bitpos: [3]; default: 0;
+         *  If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an
+         *  Exit Pattern. This should only be used when the bus will not use HDR.
+         */
+        uint32_t s0ignore:1;
+        /** ddrok : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t ddrok:1;
+        uint32_t reserved_5:3;
+        /** idrand : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t idrand:1;
+        /** offline : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t offline:1;
+        uint32_t reserved_10:6;
+        /** bamatch : R/W; bitpos: [23:16]; default: 47;
+         *  Bus Available condition match value for current ???Slow clock???. This provides the
+         *  count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low
+         *  when the Master is not doing so. The max width , and so max value, is controlled by
+         *  the block. Only if enabled for events such IBI or MR or HJ, and if enabled to
+         *  provide this as a register. With is limited to CLK_SLOW_BITS
+         */
+        uint32_t bamatch:8;
+        uint32_t reserved_24:1;
+        /** saddr : R/W; bitpos: [31:25]; default: 0;
+         *  If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled
+         *  to use one and to be provided by SW. Block may provide in HW as well.
+         */
+        uint32_t saddr:7;
+    };
+    uint32_t val;
+} i3c_slv_config_reg_t;
+
+
+/** Group: I3C_SLV STATUS REG */
+/** Type of status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** stnotstop : RO; bitpos: [0]; default: 0;
+         *  Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also
+         *  set when busy. Note that this can also be true from an S0 or S1 error, which waits
+         *  for an Exit Pattern.
+         */
+        uint32_t stnotstop:1;
+        /** stmsg : RO; bitpos: [1]; default: 0;
+         *  Is 1 if this bus Slave is listening to the bus traffic or responding, If
+         *  STNOSTOP=1, then this will be 0 when a non-matching address seen until next
+         *  respeated START it STOP.
+         */
+        uint32_t stmsg:1;
+        /** stccch : RO; bitpos: [2]; default: 0;
+         *  Is 1 if a CCC message is being handled automatically.
+         */
+        uint32_t stccch:1;
+        /** streqrd : RO; bitpos: [3]; default: 0;
+         *  1 if the req in process is an sdr read from this slave or an IBI is being pushed
+         *  out,
+         */
+        uint32_t streqrd:1;
+        /** streqwr : RO; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t streqwr:1;
+        /** stdaa : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t stdaa:1;
+        /** sthdr : RO; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t sthdr:1;
+        uint32_t reserved_7:1;
+        /** start : R/W; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t start:1;
+        /** matched : R/W; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t matched:1;
+        /** stop : R/W; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t stop:1;
+        /** rxpend : RO; bitpos: [11]; default: 0;
+         *  Receiving a message from master,which is not being handled by block(not a CCC
+         *  internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which
+         *  defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will
+         *  self-clear if data is read(FIFO and non-FIFO)
+         */
+        uint32_t rxpend:1;
+        /** txnotfull : RO; bitpos: [12]; default: 0;
+         *  Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all
+         *  but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is
+         *  enabled for TX, it will also be signaled to provide more.
+         */
+        uint32_t txnotfull:1;
+        /** dachg : R/W; bitpos: [13]; default: 0;
+         *  The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in
+         *  that state of being valid or none. Actual DA can be seen in the DYNADDR register.
+         *  Note that this will also be used when MAP Auto feature is configured. This will be
+         *  changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main
+         *  DA(0) will indicate if last change was due to Auto MAP.
+         */
+        uint32_t dachg:1;
+        /** ccc : R/W; bitpos: [14]; default: 0;
+         *  A common -command-code(CCC), not handled by block, has been received. This acts
+         *  differently between: *Broadcasted ones, which will then also correspond with RXPEND
+         *  and the 1st byte will be the CCC(command) . *Direct ones, which may never be
+         *  directed to this device.  If it is, then the TXSEND or RXPEND will be triggered
+         *  with this end the RXPEND will contain the command.
+         */
+        uint32_t ccc:1;
+        /** errwarn : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t errwarn:1;
+        /** hdrmatch : R/W; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t hdrmatch:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} i3c_slv_status_reg_t;
+
+
+/** Group: I3C_SLV CTRL REG */
+/** Type of ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** slv_event : R/W; bitpos: [1:0]; default: 0;
+         *  If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will
+         *  show the status as it progresses. Once completed, the field will automatically
+         *  return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal
+         *  mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1:
+         *  start an IBI. This will try to push through an IBI on the bus. If data associate
+         *  with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is
+         *  enabled, this will include anytime control related bytes  further, the IBIDATA byte
+         *  will have bit7 set to 1.
+         */
+        uint32_t slv_event:2;
+        uint32_t reserved_2:1;
+        /** extdata : R/W; bitpos: [3]; default: 0;
+         *  reserved
+         */
+        uint32_t extdata:1;
+        /** mapidx : R/W; bitpos: [7:4]; default: 0;
+         *  Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic
+         *  Address, or can be any valid index.
+         */
+        uint32_t mapidx:4;
+        /** ibidata : R/W; bitpos: [15:8]; default: 0;
+         *  Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is
+         *  required.
+         */
+        uint32_t ibidata:8;
+        /** pendint : R/W; bitpos: [19:16]; default: 0;
+         *  Should be set to the pending interrupt that GETSTATUS CCC will return. This should
+         *  be maintained by the application if used and configured, as the Master will read
+         *  this. If not configured, the GETSTATUS field will return 1 if an IBI is pending,
+         *  and 0 otherwise.
+         */
+        uint32_t pendint:4;
+        /** actstate : R/W; bitpos: [21:20]; default: 0;
+         *  NA
+         */
+        uint32_t actstate:2;
+        uint32_t reserved_22:2;
+        /** vendinfo : R/W; bitpos: [31:24]; default: 0;
+         *  NA
+         */
+        uint32_t vendinfo:8;
+    };
+    uint32_t val;
+} i3c_slv_ctrl_reg_t;
+
+
+/** Group: I3C_SLV INTSET REG */
+/** Type of intset register
+ *  INSET allows setting enables for interrupts(connecting the corresponding STATUS
+ *  source to causing an IRQ to the processor)
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** stop_ena : R/W; bitpos: [10]; default: 0;
+         *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+         *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+         *  relates to the state of being stopped.
+         */
+        uint32_t stop_ena:1;
+        /** rxpend_ena : R/W; bitpos: [11]; default: 0;
+         *  Interrupt when receiving a message from Master, which is not being handled by the
+         *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+         *  trigger. If DMA, then message end.
+         */
+        uint32_t rxpend_ena:1;
+        /** txsend_ena : R/W; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t txsend_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} i3c_slv_intset_reg_t;
+
+
+/** Group: I3C_SLV INTCLR REG */
+/** Type of intclr register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** stop_clr : WO; bitpos: [10]; default: 0;
+         *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+         *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+         *  relates to the state of being stopped.
+         */
+        uint32_t stop_clr:1;
+        /** rxpend_clr : WO; bitpos: [11]; default: 0;
+         *  Interrupt when receiving a message from Master, which is not being handled by the
+         *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+         *  trigger. If DMA, then message end.
+         */
+        uint32_t rxpend_clr:1;
+        /** txsend_clr : WO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t txsend_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} i3c_slv_intclr_reg_t;
+
+
+/** Group: I3C_SLV INTMASKED REG */
+/** Type of intmasked register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** stop_mask : RO; bitpos: [10]; default: 0;
+         *  Interrupt on STOP state on the bus. See Start as the preferred interrupt when
+         *  needed. This interrupt may not trigger for quick STOP/START combination, as it
+         *  relates to the state of being stopped.
+         */
+        uint32_t stop_mask:1;
+        /** rxpend_mask : RO; bitpos: [11]; default: 0;
+         *  Interrupt when receiving a message from Master, which is not being handled by the
+         *  block (excludes CCCs being handled automatically). If FIFO, then RX fullness
+         *  trigger. If DMA, then message end.
+         */
+        uint32_t rxpend_mask:1;
+        /** txsend_mask : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t txsend_mask:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} i3c_slv_intmasked_reg_t;
+
+
+/** Group: I3C_SLV DATACTRL REG */
+/** Type of datactrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** flushtb : WO; bitpos: [0]; default: 0;
+         *  Flushes the from-bus buffer/FIFO. Not normally used
+         */
+        uint32_t flushtb:1;
+        /** flushfb : WO; bitpos: [1]; default: 0;
+         *  Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message
+         *  prematurely
+         */
+        uint32_t flushfb:1;
+        uint32_t reserved_2:1;
+        /** unlock : WO; bitpos: [3]; default: 0;
+         *  If this bit is not written 1, the register bits from 7 to 4 are not changed on
+         *  write.
+         */
+        uint32_t unlock:1;
+        /** txtrig : R/W; bitpos: [5:4]; default: 3;
+         *  Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled).
+         *  The defaults is 3
+         */
+        uint32_t txtrig:2;
+        /** rxtrig : R/W; bitpos: [7:6]; default: 2;
+         *  Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled).
+         *  The defaults is 3
+         */
+        uint32_t rxtrig:2;
+        uint32_t reserved_8:8;
+        /** txcount : RO; bitpos: [20:16]; default: 0;
+         *  NA
+         */
+        uint32_t txcount:5;
+        uint32_t reserved_21:3;
+        /** rxcount : RO; bitpos: [28:24]; default: 0;
+         *  NA
+         */
+        uint32_t rxcount:5;
+        uint32_t reserved_29:1;
+        /** txfull : RO; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t txfull:1;
+        /** rxempty : RO; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t rxempty:1;
+    };
+    uint32_t val;
+} i3c_slv_datactrl_reg_t;
+
+
+/** Group: I3C_SLV WDATAB REG */
+/** Type of wdatab register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** wdatab : WO; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t wdatab:8;
+        /** wdata_end : WO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t wdata_end:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i3c_slv_wdatab_reg_t;
+
+
+/** Group: I3C_SLV WDATABE REG */
+/** Type of wdatabe register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** wdatabe : WO; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t wdatabe:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i3c_slv_wdatabe_reg_t;
+
+
+/** Group: I3C_SLV RDARAB REG */
+/** Type of rdarab register
+ *  Read Byte Data (from-bus) register
+ */
+typedef union {
+    struct {
+        /** data0 : RO; bitpos: [7:0]; default: 0;
+         *  This register allows reading a byte from the bus unless external FIFO is used. A
+         *  byte should not be read unless there is data waiting, as indicated by the RXPEND
+         *  bit being set in the STATUS register
+         */
+        uint32_t data0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i3c_slv_rdarab_reg_t;
+
+
+/** Group: I3C_SLV RDATAH REG */
+/** Type of rdatah register
+ *  Read Half-word Data (from-bus) register
+ */
+typedef union {
+    struct {
+        /** data_lsb : RO; bitpos: [7:0]; default: 0;
+         *  NA
+         */
+        uint32_t data_lsb:8;
+        /** data_msb : RO; bitpos: [15:8]; default: 0;
+         *  This register allows reading a Half-word (byte pair)  from the bus unless external
+         *  FIFO is used. A Half-word should not be read unless there is at least 2 bytes of
+         *  data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space
+         *  in the DATACTRL register
+         */
+        uint32_t data_msb:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i3c_slv_rdatah_reg_t;
+
+
+/** Group: I3C_SLV CAPABILITIES2 REG */
+/** Type of capabilities2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** capablities2 : RO; bitpos: [31:0]; default: 256;
+         *  NA
+         */
+        uint32_t capablities2:32;
+    };
+    uint32_t val;
+} i3c_slv_capabilities2_reg_t;
+
+
+/** Group: I3C_SLV CAPABILITIES REG */
+/** Type of capabilities register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** capabilities : RO; bitpos: [31:0]; default: 2081684508;
+         *  NA
+         */
+        uint32_t capabilities:32;
+    };
+    uint32_t val;
+} i3c_slv_capabilities_reg_t;
+
+
+/** Group: I3C_SLV IDPARTNO REG */
+/** Type of idpartno register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** partno : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t partno:32;
+    };
+    uint32_t val;
+} i3c_slv_idpartno_reg_t;
+
+
+/** Group: I3C_SLV IDEXT REG */
+/** Type of idext register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** idext : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t idext:32;
+    };
+    uint32_t val;
+} i3c_slv_idext_reg_t;
+
+
+/** Group: I3C_SLV VENDORID REG */
+/** Type of vendorid register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** vid : R/W; bitpos: [14:0]; default: 21840;
+         *  NA
+         */
+        uint32_t vid:15;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i3c_slv_vendorid_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile i3c_slv_config_reg_t config;
+    volatile i3c_slv_status_reg_t status;
+    volatile i3c_slv_ctrl_reg_t ctrl;
+    volatile i3c_slv_intset_reg_t intset;
+    volatile i3c_slv_intclr_reg_t intclr;
+    volatile i3c_slv_intmasked_reg_t intmasked;
+    uint32_t reserved_01c[4];
+    volatile i3c_slv_datactrl_reg_t datactrl;
+    volatile i3c_slv_wdatab_reg_t wdatab;
+    volatile i3c_slv_wdatabe_reg_t wdatabe;
+    uint32_t reserved_038[2];
+    volatile i3c_slv_rdarab_reg_t rdarab;
+    uint32_t reserved_044;
+    volatile i3c_slv_rdatah_reg_t rdatah;
+    uint32_t reserved_04c[4];
+    volatile i3c_slv_capabilities2_reg_t capabilities2;
+    volatile i3c_slv_capabilities_reg_t capabilities;
+    uint32_t reserved_064[2];
+    volatile i3c_slv_idpartno_reg_t idpartno;
+    volatile i3c_slv_idext_reg_t idext;
+    volatile i3c_slv_vendorid_reg_t vendorid;
+} i3c_slv_dev_t;
+
+extern i3c_slv_dev_t I3C_SLV;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i3c_slv_dev_t) == 0x78, "Invalid size of i3c_slv_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_reg.h
new file mode 100644
index 0000000000..8f1143edce
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_reg.h
@@ -0,0 +1,176 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ICM_AXI_VERID_FILEDS_REG register
+ *  NA
+ */
+#define ICM_AXI_VERID_FILEDS_REG (DR_REG_ICM_AXI_BASE + 0x0)
+/** ICM_AXI_REG_VERID : RO; bitpos: [31:0]; default: 875574314;
+ *  NA
+ */
+#define ICM_AXI_REG_VERID    0xFFFFFFFFU
+#define ICM_AXI_REG_VERID_M  (ICM_AXI_REG_VERID_V << ICM_AXI_REG_VERID_S)
+#define ICM_AXI_REG_VERID_V  0xFFFFFFFFU
+#define ICM_AXI_REG_VERID_S  0
+
+/** ICM_AXI_HW_CFG_REG_REG register
+ *  NA
+ */
+#define ICM_AXI_HW_CFG_REG_REG (DR_REG_ICM_AXI_BASE + 0x4)
+/** ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT : RO; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT    (BIT(0))
+#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_M  (ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_V << ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_S)
+#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_QOS_SUPPORT_S  0
+/** ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT    (BIT(1))
+#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_M  (ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_V << ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_S)
+#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_APB3_SUPPORT_S  1
+/** ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT    (BIT(2))
+#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_M  (ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_V << ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_S)
+#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_AXI4_SUPPORT_S  2
+/** ICM_AXI_REG_AXI_HWCFG_LOCK_EN : RO; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN    (BIT(3))
+#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN_M  (ICM_AXI_REG_AXI_HWCFG_LOCK_EN_V << ICM_AXI_REG_AXI_HWCFG_LOCK_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_LOCK_EN_S  3
+/** ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN : RO; bitpos: [4]; default: 1;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN    (BIT(4))
+#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_M  (ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_V << ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_TRUST_ZONE_EN_S  4
+/** ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE : RO; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE    (BIT(5))
+#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_M  (ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_V << ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_S)
+#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_DECODER_TYPE_S  5
+/** ICM_AXI_REG_AXI_HWCFG_REMAP_EN : RO; bitpos: [6]; default: 1;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN    (BIT(6))
+#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN_M  (ICM_AXI_REG_AXI_HWCFG_REMAP_EN_V << ICM_AXI_REG_AXI_HWCFG_REMAP_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_REMAP_EN_S  6
+/** ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN    (BIT(7))
+#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_M  (ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_V << ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_BI_DIR_CMD_EN_S  7
+/** ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN : RO; bitpos: [8]; default: 1;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN    (BIT(8))
+#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_M  (ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_V << ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_S)
+#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_HWCFG_LOW_POWER_INF_EN_S  8
+/** ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS : RO; bitpos: [16:12]; default: 13;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS    0x0000001FU
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_M  (ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_V << ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_S)
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_V  0x0000001FU
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_MASTERS_S  12
+/** ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES : RO; bitpos: [24:20]; default: 7;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES    0x0000001FU
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_M  (ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_V << ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_S)
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_V  0x0000001FU
+#define ICM_AXI_REG_AXI_HWCFG_AXI_NUM_SLAVES_S  20
+
+/** ICM_AXI_CMD_REG register
+ *  NA
+ */
+#define ICM_AXI_CMD_REG (DR_REG_ICM_AXI_BASE + 0x8)
+/** ICM_AXI_REG_AXI_CMD : R/W; bitpos: [2:0]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_CMD    0x00000007U
+#define ICM_AXI_REG_AXI_CMD_M  (ICM_AXI_REG_AXI_CMD_V << ICM_AXI_REG_AXI_CMD_S)
+#define ICM_AXI_REG_AXI_CMD_V  0x00000007U
+#define ICM_AXI_REG_AXI_CMD_S  0
+/** ICM_AXI_REG_RD_WR_CHAN : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_RD_WR_CHAN    (BIT(7))
+#define ICM_AXI_REG_RD_WR_CHAN_M  (ICM_AXI_REG_RD_WR_CHAN_V << ICM_AXI_REG_RD_WR_CHAN_S)
+#define ICM_AXI_REG_RD_WR_CHAN_V  0x00000001U
+#define ICM_AXI_REG_RD_WR_CHAN_S  7
+/** ICM_AXI_REG_AXI_MASTER_PORT : R/W; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_MASTER_PORT    0x0000000FU
+#define ICM_AXI_REG_AXI_MASTER_PORT_M  (ICM_AXI_REG_AXI_MASTER_PORT_V << ICM_AXI_REG_AXI_MASTER_PORT_S)
+#define ICM_AXI_REG_AXI_MASTER_PORT_V  0x0000000FU
+#define ICM_AXI_REG_AXI_MASTER_PORT_S  8
+/** ICM_AXI_REG_AXI_ERR_BIT : RO; bitpos: [28]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_ERR_BIT    (BIT(28))
+#define ICM_AXI_REG_AXI_ERR_BIT_M  (ICM_AXI_REG_AXI_ERR_BIT_V << ICM_AXI_REG_AXI_ERR_BIT_S)
+#define ICM_AXI_REG_AXI_ERR_BIT_V  0x00000001U
+#define ICM_AXI_REG_AXI_ERR_BIT_S  28
+/** ICM_AXI_REG_AXI_SOFT_RESET_BIT : R/W; bitpos: [29]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_SOFT_RESET_BIT    (BIT(29))
+#define ICM_AXI_REG_AXI_SOFT_RESET_BIT_M  (ICM_AXI_REG_AXI_SOFT_RESET_BIT_V << ICM_AXI_REG_AXI_SOFT_RESET_BIT_S)
+#define ICM_AXI_REG_AXI_SOFT_RESET_BIT_V  0x00000001U
+#define ICM_AXI_REG_AXI_SOFT_RESET_BIT_S  29
+/** ICM_AXI_REG_AXI_RD_WR_CMD : R/W; bitpos: [30]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_RD_WR_CMD    (BIT(30))
+#define ICM_AXI_REG_AXI_RD_WR_CMD_M  (ICM_AXI_REG_AXI_RD_WR_CMD_V << ICM_AXI_REG_AXI_RD_WR_CMD_S)
+#define ICM_AXI_REG_AXI_RD_WR_CMD_V  0x00000001U
+#define ICM_AXI_REG_AXI_RD_WR_CMD_S  30
+/** ICM_AXI_REG_AXI_CMD_EN : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_AXI_CMD_EN    (BIT(31))
+#define ICM_AXI_REG_AXI_CMD_EN_M  (ICM_AXI_REG_AXI_CMD_EN_V << ICM_AXI_REG_AXI_CMD_EN_S)
+#define ICM_AXI_REG_AXI_CMD_EN_V  0x00000001U
+#define ICM_AXI_REG_AXI_CMD_EN_S  31
+
+/** ICM_AXI_DATA_REG register
+ *  NA
+ */
+#define ICM_AXI_DATA_REG (DR_REG_ICM_AXI_BASE + 0xc)
+/** ICM_AXI_REG_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define ICM_AXI_REG_DATA    0xFFFFFFFFU
+#define ICM_AXI_REG_DATA_M  (ICM_AXI_REG_DATA_V << ICM_AXI_REG_DATA_S)
+#define ICM_AXI_REG_DATA_V  0xFFFFFFFFU
+#define ICM_AXI_REG_DATA_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_struct.h
new file mode 100644
index 0000000000..8e66405ca9
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_qos_struct.h
@@ -0,0 +1,157 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: ICM AXI VERID FIELDS REG */
+/** Type of verid_fileds register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_verid : RO; bitpos: [31:0]; default: 875574314;
+         *  NA
+         */
+        uint32_t reg_verid:32;
+    };
+    uint32_t val;
+} icm_axi_verid_fileds_reg_t;
+
+
+/** Group: ICM AXI HW CFG REG REG */
+/** Type of hw_cfg_reg register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_axi_hwcfg_qos_support : RO; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_qos_support:1;
+        /** reg_axi_hwcfg_apb3_support : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_apb3_support:1;
+        /** reg_axi_hwcfg_axi4_support : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_axi4_support:1;
+        /** reg_axi_hwcfg_lock_en : RO; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_lock_en:1;
+        /** reg_axi_hwcfg_trust_zone_en : RO; bitpos: [4]; default: 1;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_trust_zone_en:1;
+        /** reg_axi_hwcfg_decoder_type : RO; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_decoder_type:1;
+        /** reg_axi_hwcfg_remap_en : RO; bitpos: [6]; default: 1;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_remap_en:1;
+        /** reg_axi_hwcfg_bi_dir_cmd_en : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_bi_dir_cmd_en:1;
+        /** reg_axi_hwcfg_low_power_inf_en : RO; bitpos: [8]; default: 1;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_low_power_inf_en:1;
+        uint32_t reserved_9:3;
+        /** reg_axi_hwcfg_axi_num_masters : RO; bitpos: [16:12]; default: 13;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_axi_num_masters:5;
+        uint32_t reserved_17:3;
+        /** reg_axi_hwcfg_axi_num_slaves : RO; bitpos: [24:20]; default: 7;
+         *  NA
+         */
+        uint32_t reg_axi_hwcfg_axi_num_slaves:5;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} icm_axi_hw_cfg_reg_reg_t;
+
+
+/** Group: ICM AXI CMD REG */
+/** Type of cmd register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_axi_cmd : R/W; bitpos: [2:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_cmd:3;
+        uint32_t reserved_3:4;
+        /** reg_rd_wr_chan : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rd_wr_chan:1;
+        /** reg_axi_master_port : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_master_port:4;
+        uint32_t reserved_12:16;
+        /** reg_axi_err_bit : RO; bitpos: [28]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_err_bit:1;
+        /** reg_axi_soft_reset_bit : R/W; bitpos: [29]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_soft_reset_bit:1;
+        /** reg_axi_rd_wr_cmd : R/W; bitpos: [30]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_rd_wr_cmd:1;
+        /** reg_axi_cmd_en : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_cmd_en:1;
+    };
+    uint32_t val;
+} icm_axi_cmd_reg_t;
+
+
+/** Group: ICM AXI DATA REG */
+/** Type of data register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_data : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_data:32;
+    };
+    uint32_t val;
+} icm_axi_data_reg_t;
+
+
+typedef struct {
+    volatile icm_axi_verid_fileds_reg_t verid_fileds;
+    volatile icm_axi_hw_cfg_reg_reg_t hw_cfg_reg;
+    volatile icm_axi_cmd_reg_t cmd;
+    volatile icm_axi_data_reg_t data;
+} icm_axi_dev_t;
+
+extern icm_axi_dev_t ICM_SYS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(icm_axi_dev_t) == 0x10, "Invalid size of icm_axi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_reg.h
new file mode 100644
index 0000000000..160f1de846
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_reg.h
@@ -0,0 +1,546 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ICM_VER_DATE_REG register
+ *  NA
+ */
+#define ICM_VER_DATE_REG (DR_REG_ICM_BASE + 0x0)
+/** ICM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165204;
+ *  NA
+ */
+#define ICM_REG_VER_DATE    0xFFFFFFFFU
+#define ICM_REG_VER_DATE_M  (ICM_REG_VER_DATE_V << ICM_REG_VER_DATE_S)
+#define ICM_REG_VER_DATE_V  0xFFFFFFFFU
+#define ICM_REG_VER_DATE_S  0
+
+/** ICM_CLK_EN_REG register
+ *  NA
+ */
+#define ICM_CLK_EN_REG (DR_REG_ICM_BASE + 0x4)
+/** ICM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CLK_EN    (BIT(0))
+#define ICM_REG_CLK_EN_M  (ICM_REG_CLK_EN_V << ICM_REG_CLK_EN_S)
+#define ICM_REG_CLK_EN_V  0x00000001U
+#define ICM_REG_CLK_EN_S  0
+
+/** ICM_DLOCK_STATUS_REG register
+ *  NA
+ */
+#define ICM_DLOCK_STATUS_REG (DR_REG_ICM_BASE + 0x8)
+/** ICM_REG_DLOCK_MST : RO; bitpos: [3:0]; default: 0;
+ *  Lowest numbered deadlocked master
+ */
+#define ICM_REG_DLOCK_MST    0x0000000FU
+#define ICM_REG_DLOCK_MST_M  (ICM_REG_DLOCK_MST_V << ICM_REG_DLOCK_MST_S)
+#define ICM_REG_DLOCK_MST_V  0x0000000FU
+#define ICM_REG_DLOCK_MST_S  0
+/** ICM_REG_DLOCK_SLV : RO; bitpos: [6:4]; default: 0;
+ *  Slave with which dlock_mst is deadlocked
+ */
+#define ICM_REG_DLOCK_SLV    0x00000007U
+#define ICM_REG_DLOCK_SLV_M  (ICM_REG_DLOCK_SLV_V << ICM_REG_DLOCK_SLV_S)
+#define ICM_REG_DLOCK_SLV_V  0x00000007U
+#define ICM_REG_DLOCK_SLV_S  4
+/** ICM_REG_DLOCK_ID : RO; bitpos: [10:7]; default: 0;
+ *  AXI ID of deadlocked transaction
+ */
+#define ICM_REG_DLOCK_ID    0x0000000FU
+#define ICM_REG_DLOCK_ID_M  (ICM_REG_DLOCK_ID_V << ICM_REG_DLOCK_ID_S)
+#define ICM_REG_DLOCK_ID_V  0x0000000FU
+#define ICM_REG_DLOCK_ID_S  7
+/** ICM_REG_DLOCK_WR : RO; bitpos: [11]; default: 0;
+ *  Asserted if deadlocked transaction is a write
+ */
+#define ICM_REG_DLOCK_WR    (BIT(11))
+#define ICM_REG_DLOCK_WR_M  (ICM_REG_DLOCK_WR_V << ICM_REG_DLOCK_WR_S)
+#define ICM_REG_DLOCK_WR_V  0x00000001U
+#define ICM_REG_DLOCK_WR_S  11
+
+/** ICM_INT_RAW_REG register
+ *  NA
+ */
+#define ICM_INT_RAW_REG (DR_REG_ICM_BASE + 0xc)
+/** ICM_REG_DLOCK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DLOCK_INT_RAW    (BIT(0))
+#define ICM_REG_DLOCK_INT_RAW_M  (ICM_REG_DLOCK_INT_RAW_V << ICM_REG_DLOCK_INT_RAW_S)
+#define ICM_REG_DLOCK_INT_RAW_V  0x00000001U
+#define ICM_REG_DLOCK_INT_RAW_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW    (BIT(1))
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_M  (ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_RAW_S  1
+/** ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW    (BIT(2))
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_M  (ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_RAW_S  2
+
+/** ICM_INT_ST_REG register
+ *  NA
+ */
+#define ICM_INT_ST_REG (DR_REG_ICM_BASE + 0x10)
+/** ICM_REG_DLOCK_INT_ST : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DLOCK_INT_ST    (BIT(0))
+#define ICM_REG_DLOCK_INT_ST_M  (ICM_REG_DLOCK_INT_ST_V << ICM_REG_DLOCK_INT_ST_S)
+#define ICM_REG_DLOCK_INT_ST_V  0x00000001U
+#define ICM_REG_DLOCK_INT_ST_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST    (BIT(1))
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_M  (ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ST_S  1
+/** ICM_REG_ICM_CPU_ADDRHOLE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST    (BIT(2))
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_M  (ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ST_S  2
+
+/** ICM_INT_ENA_REG register
+ *  NA
+ */
+#define ICM_INT_ENA_REG (DR_REG_ICM_BASE + 0x14)
+/** ICM_REG_DLOCK_INT_ENA : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define ICM_REG_DLOCK_INT_ENA    (BIT(0))
+#define ICM_REG_DLOCK_INT_ENA_M  (ICM_REG_DLOCK_INT_ENA_V << ICM_REG_DLOCK_INT_ENA_S)
+#define ICM_REG_DLOCK_INT_ENA_V  0x00000001U
+#define ICM_REG_DLOCK_INT_ENA_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA : R/W; bitpos: [1]; default: 1;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA    (BIT(1))
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_M  (ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_ENA_S  1
+/** ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA : R/W; bitpos: [2]; default: 1;
+ *  NA
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA    (BIT(2))
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_M  (ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_ENA_S  2
+
+/** ICM_INT_CLR_REG register
+ *  NA
+ */
+#define ICM_INT_CLR_REG (DR_REG_ICM_BASE + 0x18)
+/** ICM_REG_DLOCK_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DLOCK_INT_CLR    (BIT(0))
+#define ICM_REG_DLOCK_INT_CLR_M  (ICM_REG_DLOCK_INT_CLR_V << ICM_REG_DLOCK_INT_CLR_S)
+#define ICM_REG_DLOCK_INT_CLR_V  0x00000001U
+#define ICM_REG_DLOCK_INT_CLR_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR    (BIT(1))
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_M  (ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_V << ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_INT_CLR_S  1
+/** ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR    (BIT(2))
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_M  (ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_V << ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_INT_CLR_S  2
+
+/** ICM_MST_ARB_PRIORITY_REG0_REG register
+ *  NA
+ */
+#define ICM_MST_ARB_PRIORITY_REG0_REG (DR_REG_ICM_BASE + 0x1c)
+/** ICM_REG_CPU_PRIORITY : R/W; bitpos: [3:0]; default: 0;
+ *  CPU arbitration priority for command channels between masters connected to sys_icm
+ */
+#define ICM_REG_CPU_PRIORITY    0x0000000FU
+#define ICM_REG_CPU_PRIORITY_M  (ICM_REG_CPU_PRIORITY_V << ICM_REG_CPU_PRIORITY_S)
+#define ICM_REG_CPU_PRIORITY_V  0x0000000FU
+#define ICM_REG_CPU_PRIORITY_S  0
+/** ICM_REG_CACHE_PRIORITY : R/W; bitpos: [7:4]; default: 0;
+ *  CACHE arbitration priority for command channels between masters connected to sys_icm
+ */
+#define ICM_REG_CACHE_PRIORITY    0x0000000FU
+#define ICM_REG_CACHE_PRIORITY_M  (ICM_REG_CACHE_PRIORITY_V << ICM_REG_CACHE_PRIORITY_S)
+#define ICM_REG_CACHE_PRIORITY_V  0x0000000FU
+#define ICM_REG_CACHE_PRIORITY_S  4
+/** ICM_REG_DMA2D_PRIORITY : R/W; bitpos: [11:8]; default: 0;
+ *  GFX arbitration priority for command channels between masters connected to sys_icm
+ */
+#define ICM_REG_DMA2D_PRIORITY    0x0000000FU
+#define ICM_REG_DMA2D_PRIORITY_M  (ICM_REG_DMA2D_PRIORITY_V << ICM_REG_DMA2D_PRIORITY_S)
+#define ICM_REG_DMA2D_PRIORITY_V  0x0000000FU
+#define ICM_REG_DMA2D_PRIORITY_S  8
+/** ICM_REG_GDMA_MST1_PRIORITY : R/W; bitpos: [15:12]; default: 0;
+ *  GDMA mst1 arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_GDMA_MST1_PRIORITY    0x0000000FU
+#define ICM_REG_GDMA_MST1_PRIORITY_M  (ICM_REG_GDMA_MST1_PRIORITY_V << ICM_REG_GDMA_MST1_PRIORITY_S)
+#define ICM_REG_GDMA_MST1_PRIORITY_V  0x0000000FU
+#define ICM_REG_GDMA_MST1_PRIORITY_S  12
+/** ICM_REG_GDMA_MST2_PRIORITY : R/W; bitpos: [19:16]; default: 0;
+ *  GDMA mst2 arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_GDMA_MST2_PRIORITY    0x0000000FU
+#define ICM_REG_GDMA_MST2_PRIORITY_M  (ICM_REG_GDMA_MST2_PRIORITY_V << ICM_REG_GDMA_MST2_PRIORITY_S)
+#define ICM_REG_GDMA_MST2_PRIORITY_V  0x0000000FU
+#define ICM_REG_GDMA_MST2_PRIORITY_S  16
+/** ICM_REG_H264_M1_PRIORITY : R/W; bitpos: [23:20]; default: 0;
+ *  H264 mst1 arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_H264_M1_PRIORITY    0x0000000FU
+#define ICM_REG_H264_M1_PRIORITY_M  (ICM_REG_H264_M1_PRIORITY_V << ICM_REG_H264_M1_PRIORITY_S)
+#define ICM_REG_H264_M1_PRIORITY_V  0x0000000FU
+#define ICM_REG_H264_M1_PRIORITY_S  20
+/** ICM_REG_H264_M2_PRIORITY : R/W; bitpos: [27:24]; default: 0;
+ *  H264 mst2 arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_H264_M2_PRIORITY    0x0000000FU
+#define ICM_REG_H264_M2_PRIORITY_M  (ICM_REG_H264_M2_PRIORITY_V << ICM_REG_H264_M2_PRIORITY_S)
+#define ICM_REG_H264_M2_PRIORITY_V  0x0000000FU
+#define ICM_REG_H264_M2_PRIORITY_S  24
+/** ICM_REG_AXI_PDMA_PRIORITY : R/W; bitpos: [31:28]; default: 0;
+ *  AXI PDMA  arbitration priority for command channels between masters connected to
+ *  sys_icm
+ */
+#define ICM_REG_AXI_PDMA_PRIORITY    0x0000000FU
+#define ICM_REG_AXI_PDMA_PRIORITY_M  (ICM_REG_AXI_PDMA_PRIORITY_V << ICM_REG_AXI_PDMA_PRIORITY_S)
+#define ICM_REG_AXI_PDMA_PRIORITY_V  0x0000000FU
+#define ICM_REG_AXI_PDMA_PRIORITY_S  28
+
+/** ICM_SLV_ARB_PRIORITY_REG register
+ *  NA
+ */
+#define ICM_SLV_ARB_PRIORITY_REG (DR_REG_ICM_BASE + 0x24)
+/** ICM_REG_L2MEM_PRIORITY : R/W; bitpos: [5:3]; default: 0;
+ *  L2MEM arbitration priority for response channels between slaves connected to sys_icm
+ */
+#define ICM_REG_L2MEM_PRIORITY    0x00000007U
+#define ICM_REG_L2MEM_PRIORITY_M  (ICM_REG_L2MEM_PRIORITY_V << ICM_REG_L2MEM_PRIORITY_S)
+#define ICM_REG_L2MEM_PRIORITY_V  0x00000007U
+#define ICM_REG_L2MEM_PRIORITY_S  3
+/** ICM_REG_FLASH_MSPI_PRIORITY : R/W; bitpos: [14:12]; default: 0;
+ *  FLASH MSPI arbitration priority for response channels between slaves connected to
+ *  sys_icm
+ */
+#define ICM_REG_FLASH_MSPI_PRIORITY    0x00000007U
+#define ICM_REG_FLASH_MSPI_PRIORITY_M  (ICM_REG_FLASH_MSPI_PRIORITY_V << ICM_REG_FLASH_MSPI_PRIORITY_S)
+#define ICM_REG_FLASH_MSPI_PRIORITY_V  0x00000007U
+#define ICM_REG_FLASH_MSPI_PRIORITY_S  12
+/** ICM_REG_PSRAM_MSPI_PRIORITY : R/W; bitpos: [17:15]; default: 0;
+ *  PSRAM MSPI arbitration priority for response channels between slaves connected to
+ *  sys_icm
+ */
+#define ICM_REG_PSRAM_MSPI_PRIORITY    0x00000007U
+#define ICM_REG_PSRAM_MSPI_PRIORITY_M  (ICM_REG_PSRAM_MSPI_PRIORITY_V << ICM_REG_PSRAM_MSPI_PRIORITY_S)
+#define ICM_REG_PSRAM_MSPI_PRIORITY_V  0x00000007U
+#define ICM_REG_PSRAM_MSPI_PRIORITY_S  15
+/** ICM_REG_LCD_PRIORITY : R/W; bitpos: [20:18]; default: 0;
+ *  MIPI_LCD registers arbitration priority for response channels between slaves
+ *  connected to sys_icm
+ */
+#define ICM_REG_LCD_PRIORITY    0x00000007U
+#define ICM_REG_LCD_PRIORITY_M  (ICM_REG_LCD_PRIORITY_V << ICM_REG_LCD_PRIORITY_S)
+#define ICM_REG_LCD_PRIORITY_V  0x00000007U
+#define ICM_REG_LCD_PRIORITY_S  18
+/** ICM_REG_CAM_PRIORITY : R/W; bitpos: [23:21]; default: 0;
+ *  MIPI_CAM registers arbitration priority for response channels between slaves
+ *  connected to sys_icm
+ */
+#define ICM_REG_CAM_PRIORITY    0x00000007U
+#define ICM_REG_CAM_PRIORITY_M  (ICM_REG_CAM_PRIORITY_V << ICM_REG_CAM_PRIORITY_S)
+#define ICM_REG_CAM_PRIORITY_V  0x00000007U
+#define ICM_REG_CAM_PRIORITY_S  21
+
+/** ICM_MST_ARQOS_REG0_REG register
+ *  NA
+ */
+#define ICM_MST_ARQOS_REG0_REG (DR_REG_ICM_BASE + 0x28)
+/** ICM_REG_CPU_ARQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CPU_ARQOS    0x0000000FU
+#define ICM_REG_CPU_ARQOS_M  (ICM_REG_CPU_ARQOS_V << ICM_REG_CPU_ARQOS_S)
+#define ICM_REG_CPU_ARQOS_V  0x0000000FU
+#define ICM_REG_CPU_ARQOS_S  0
+/** ICM_REG_CACHE_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CACHE_ARQOS    0x0000000FU
+#define ICM_REG_CACHE_ARQOS_M  (ICM_REG_CACHE_ARQOS_V << ICM_REG_CACHE_ARQOS_S)
+#define ICM_REG_CACHE_ARQOS_V  0x0000000FU
+#define ICM_REG_CACHE_ARQOS_S  4
+/** ICM_REG_DMA2D_ARQOS : R/W; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DMA2D_ARQOS    0x0000000FU
+#define ICM_REG_DMA2D_ARQOS_M  (ICM_REG_DMA2D_ARQOS_V << ICM_REG_DMA2D_ARQOS_S)
+#define ICM_REG_DMA2D_ARQOS_V  0x0000000FU
+#define ICM_REG_DMA2D_ARQOS_S  8
+/** ICM_REG_GDMA_MST1_ARQOS : R/W; bitpos: [15:12]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GDMA_MST1_ARQOS    0x0000000FU
+#define ICM_REG_GDMA_MST1_ARQOS_M  (ICM_REG_GDMA_MST1_ARQOS_V << ICM_REG_GDMA_MST1_ARQOS_S)
+#define ICM_REG_GDMA_MST1_ARQOS_V  0x0000000FU
+#define ICM_REG_GDMA_MST1_ARQOS_S  12
+/** ICM_REG_GDMA_MST2_ARQOS : R/W; bitpos: [19:16]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GDMA_MST2_ARQOS    0x0000000FU
+#define ICM_REG_GDMA_MST2_ARQOS_M  (ICM_REG_GDMA_MST2_ARQOS_V << ICM_REG_GDMA_MST2_ARQOS_S)
+#define ICM_REG_GDMA_MST2_ARQOS_V  0x0000000FU
+#define ICM_REG_GDMA_MST2_ARQOS_S  16
+/** ICM_REG_H264_DMA2D_M1_ARQOS : R/W; bitpos: [23:20]; default: 0;
+ *  NA
+ */
+#define ICM_REG_H264_DMA2D_M1_ARQOS    0x0000000FU
+#define ICM_REG_H264_DMA2D_M1_ARQOS_M  (ICM_REG_H264_DMA2D_M1_ARQOS_V << ICM_REG_H264_DMA2D_M1_ARQOS_S)
+#define ICM_REG_H264_DMA2D_M1_ARQOS_V  0x0000000FU
+#define ICM_REG_H264_DMA2D_M1_ARQOS_S  20
+/** ICM_REG_H264_DMA2D_M2_ARQOS : R/W; bitpos: [27:24]; default: 0;
+ *  NA
+ */
+#define ICM_REG_H264_DMA2D_M2_ARQOS    0x0000000FU
+#define ICM_REG_H264_DMA2D_M2_ARQOS_M  (ICM_REG_H264_DMA2D_M2_ARQOS_V << ICM_REG_H264_DMA2D_M2_ARQOS_S)
+#define ICM_REG_H264_DMA2D_M2_ARQOS_V  0x0000000FU
+#define ICM_REG_H264_DMA2D_M2_ARQOS_S  24
+/** ICM_REG_AXI_PDMA_INT_ARQOS : R/W; bitpos: [31:28]; default: 0;
+ *  NA
+ */
+#define ICM_REG_AXI_PDMA_INT_ARQOS    0x0000000FU
+#define ICM_REG_AXI_PDMA_INT_ARQOS_M  (ICM_REG_AXI_PDMA_INT_ARQOS_V << ICM_REG_AXI_PDMA_INT_ARQOS_S)
+#define ICM_REG_AXI_PDMA_INT_ARQOS_V  0x0000000FU
+#define ICM_REG_AXI_PDMA_INT_ARQOS_S  28
+
+/** ICM_MST_AWQOS_REG0_REG register
+ *  NA
+ */
+#define ICM_MST_AWQOS_REG0_REG (DR_REG_ICM_BASE + 0x30)
+/** ICM_REG_CPU_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CPU_AWQOS    0x0000000FU
+#define ICM_REG_CPU_AWQOS_M  (ICM_REG_CPU_AWQOS_V << ICM_REG_CPU_AWQOS_S)
+#define ICM_REG_CPU_AWQOS_V  0x0000000FU
+#define ICM_REG_CPU_AWQOS_S  0
+/** ICM_REG_CACHE_AWQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CACHE_AWQOS    0x0000000FU
+#define ICM_REG_CACHE_AWQOS_M  (ICM_REG_CACHE_AWQOS_V << ICM_REG_CACHE_AWQOS_S)
+#define ICM_REG_CACHE_AWQOS_V  0x0000000FU
+#define ICM_REG_CACHE_AWQOS_S  4
+/** ICM_REG_DMA2D_AWQOS : R/W; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DMA2D_AWQOS    0x0000000FU
+#define ICM_REG_DMA2D_AWQOS_M  (ICM_REG_DMA2D_AWQOS_V << ICM_REG_DMA2D_AWQOS_S)
+#define ICM_REG_DMA2D_AWQOS_V  0x0000000FU
+#define ICM_REG_DMA2D_AWQOS_S  8
+/** ICM_REG_GDMA_MST1_AWQOS : R/W; bitpos: [15:12]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GDMA_MST1_AWQOS    0x0000000FU
+#define ICM_REG_GDMA_MST1_AWQOS_M  (ICM_REG_GDMA_MST1_AWQOS_V << ICM_REG_GDMA_MST1_AWQOS_S)
+#define ICM_REG_GDMA_MST1_AWQOS_V  0x0000000FU
+#define ICM_REG_GDMA_MST1_AWQOS_S  12
+/** ICM_REG_GDMA_MST2_AWQOS : R/W; bitpos: [19:16]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GDMA_MST2_AWQOS    0x0000000FU
+#define ICM_REG_GDMA_MST2_AWQOS_M  (ICM_REG_GDMA_MST2_AWQOS_V << ICM_REG_GDMA_MST2_AWQOS_S)
+#define ICM_REG_GDMA_MST2_AWQOS_V  0x0000000FU
+#define ICM_REG_GDMA_MST2_AWQOS_S  16
+/** ICM_REG_H264_DMA2D_M1_AWQOS : R/W; bitpos: [23:20]; default: 0;
+ *  NA
+ */
+#define ICM_REG_H264_DMA2D_M1_AWQOS    0x0000000FU
+#define ICM_REG_H264_DMA2D_M1_AWQOS_M  (ICM_REG_H264_DMA2D_M1_AWQOS_V << ICM_REG_H264_DMA2D_M1_AWQOS_S)
+#define ICM_REG_H264_DMA2D_M1_AWQOS_V  0x0000000FU
+#define ICM_REG_H264_DMA2D_M1_AWQOS_S  20
+/** ICM_REG_H264_DMA2D_M2_AWQOS : R/W; bitpos: [27:24]; default: 0;
+ *  NA
+ */
+#define ICM_REG_H264_DMA2D_M2_AWQOS    0x0000000FU
+#define ICM_REG_H264_DMA2D_M2_AWQOS_M  (ICM_REG_H264_DMA2D_M2_AWQOS_V << ICM_REG_H264_DMA2D_M2_AWQOS_S)
+#define ICM_REG_H264_DMA2D_M2_AWQOS_V  0x0000000FU
+#define ICM_REG_H264_DMA2D_M2_AWQOS_S  24
+/** ICM_REG_PDMA_INT_AWQOS : R/W; bitpos: [31:28]; default: 0;
+ *  NA
+ */
+#define ICM_REG_PDMA_INT_AWQOS    0x0000000FU
+#define ICM_REG_PDMA_INT_AWQOS_M  (ICM_REG_PDMA_INT_AWQOS_V << ICM_REG_PDMA_INT_AWQOS_S)
+#define ICM_REG_PDMA_INT_AWQOS_V  0x0000000FU
+#define ICM_REG_PDMA_INT_AWQOS_S  28
+
+/** ICM_SYS_ADDRHOLE_ADDR_REG register
+ *  icm sys addr hole address registers
+ */
+#define ICM_SYS_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x38)
+/** ICM_REG_ICM_SYS_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_M  (ICM_REG_ICM_SYS_ADDRHOLE_ADDR_V << ICM_REG_ICM_SYS_ADDRHOLE_ADDR_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define ICM_REG_ICM_SYS_ADDRHOLE_ADDR_S  0
+
+/** ICM_SYS_ADDRHOLE_INFO_REG register
+ *  NA
+ */
+#define ICM_SYS_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x3c)
+/** ICM_REG_ICM_SYS_ADDRHOLE_ID : RO; bitpos: [7:0]; default: 0;
+ *  master id = 4-bit CID + 4-bit  UID(refer to related IP) . CID is used to verify
+ *  master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma,
+ *  4'ha: dma2d, 4'hb: h264 mst1, 4'hc: h264 mst2.
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_ID    0x000000FFU
+#define ICM_REG_ICM_SYS_ADDRHOLE_ID_M  (ICM_REG_ICM_SYS_ADDRHOLE_ID_V << ICM_REG_ICM_SYS_ADDRHOLE_ID_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_ID_V  0x000000FFU
+#define ICM_REG_ICM_SYS_ADDRHOLE_ID_S  0
+/** ICM_REG_ICM_SYS_ADDRHOLE_WR : RO; bitpos: [8]; default: 0;
+ *  1: illegal address access, 0: access without permission
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_WR    (BIT(8))
+#define ICM_REG_ICM_SYS_ADDRHOLE_WR_M  (ICM_REG_ICM_SYS_ADDRHOLE_WR_V << ICM_REG_ICM_SYS_ADDRHOLE_WR_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_WR_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_WR_S  8
+/** ICM_REG_ICM_SYS_ADDRHOLE_SECURE : RO; bitpos: [9]; default: 0;
+ *  It is illegall access address if reg_icm_cpu_addrhole_secure is 1, Otherwise, it
+ *  the address without permission to access.
+ */
+#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE    (BIT(9))
+#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_M  (ICM_REG_ICM_SYS_ADDRHOLE_SECURE_V << ICM_REG_ICM_SYS_ADDRHOLE_SECURE_S)
+#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_V  0x00000001U
+#define ICM_REG_ICM_SYS_ADDRHOLE_SECURE_S  9
+
+/** ICM_CPU_ADDRHOLE_ADDR_REG register
+ *  icm cpu addr hole address registers
+ */
+#define ICM_CPU_ADDRHOLE_ADDR_REG (DR_REG_ICM_BASE + 0x40)
+/** ICM_REG_ICM_CPU_ADDRHOLE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it
+ *  the address without permission to access.
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR    0xFFFFFFFFU
+#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_M  (ICM_REG_ICM_CPU_ADDRHOLE_ADDR_V << ICM_REG_ICM_CPU_ADDRHOLE_ADDR_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_V  0xFFFFFFFFU
+#define ICM_REG_ICM_CPU_ADDRHOLE_ADDR_S  0
+
+/** ICM_CPU_ADDRHOLE_INFO_REG register
+ *  NA
+ */
+#define ICM_CPU_ADDRHOLE_INFO_REG (DR_REG_ICM_BASE + 0x44)
+/** ICM_REG_ICM_CPU_ADDRHOLE_ID : RO; bitpos: [4:0]; default: 0;
+ *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
+ *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
+ *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_ID    0x0000001FU
+#define ICM_REG_ICM_CPU_ADDRHOLE_ID_M  (ICM_REG_ICM_CPU_ADDRHOLE_ID_V << ICM_REG_ICM_CPU_ADDRHOLE_ID_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_ID_V  0x0000001FU
+#define ICM_REG_ICM_CPU_ADDRHOLE_ID_S  0
+/** ICM_REG_ICM_CPU_ADDRHOLE_WR : RO; bitpos: [8]; default: 0;
+ *  1:write trans, 0: read trans.
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_WR    (BIT(8))
+#define ICM_REG_ICM_CPU_ADDRHOLE_WR_M  (ICM_REG_ICM_CPU_ADDRHOLE_WR_V << ICM_REG_ICM_CPU_ADDRHOLE_WR_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_WR_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_WR_S  8
+/** ICM_REG_ICM_CPU_ADDRHOLE_SECURE : RO; bitpos: [9]; default: 0;
+ *  1: illegal address access, 0: access without permission
+ */
+#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE    (BIT(9))
+#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_M  (ICM_REG_ICM_CPU_ADDRHOLE_SECURE_V << ICM_REG_ICM_CPU_ADDRHOLE_SECURE_S)
+#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_V  0x00000001U
+#define ICM_REG_ICM_CPU_ADDRHOLE_SECURE_S  9
+
+/** ICM_DLOCK_TIMEOUT_REG register
+ *  NA
+ */
+#define ICM_DLOCK_TIMEOUT_REG (DR_REG_ICM_BASE + 0x48)
+/** ICM_REG_DLOCK_TIMEOUT : R/W; bitpos: [12:0]; default: 2048;
+ *  if no response until reg_dlock_timeout bus clock cycle, deadlock will happen
+ */
+#define ICM_REG_DLOCK_TIMEOUT    0x00001FFFU
+#define ICM_REG_DLOCK_TIMEOUT_M  (ICM_REG_DLOCK_TIMEOUT_V << ICM_REG_DLOCK_TIMEOUT_S)
+#define ICM_REG_DLOCK_TIMEOUT_V  0x00001FFFU
+#define ICM_REG_DLOCK_TIMEOUT_S  0
+
+/** ICM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define ICM_RDN_ECO_CS_REG (DR_REG_ICM_BASE + 0x50)
+/** ICM_REG_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_RDN_ECO_EN    (BIT(0))
+#define ICM_REG_RDN_ECO_EN_M  (ICM_REG_RDN_ECO_EN_V << ICM_REG_RDN_ECO_EN_S)
+#define ICM_REG_RDN_ECO_EN_V  0x00000001U
+#define ICM_REG_RDN_ECO_EN_S  0
+/** ICM_REG_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define ICM_REG_RDN_ECO_RESULT    (BIT(1))
+#define ICM_REG_RDN_ECO_RESULT_M  (ICM_REG_RDN_ECO_RESULT_V << ICM_REG_RDN_ECO_RESULT_S)
+#define ICM_REG_RDN_ECO_RESULT_V  0x00000001U
+#define ICM_REG_RDN_ECO_RESULT_S  1
+
+/** ICM_RDN_ECO_LOW_REG register
+ *  NA
+ */
+#define ICM_RDN_ECO_LOW_REG (DR_REG_ICM_BASE + 0x54)
+/** ICM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define ICM_RDN_ECO_LOW    0xFFFFFFFFU
+#define ICM_RDN_ECO_LOW_M  (ICM_RDN_ECO_LOW_V << ICM_RDN_ECO_LOW_S)
+#define ICM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define ICM_RDN_ECO_LOW_S  0
+
+/** ICM_RDN_ECO_HIGH_REG register
+ *  NA
+ */
+#define ICM_RDN_ECO_HIGH_REG (DR_REG_ICM_BASE + 0x58)
+/** ICM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  NA
+ */
+#define ICM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define ICM_RDN_ECO_HIGH_M  (ICM_RDN_ECO_HIGH_V << ICM_RDN_ECO_HIGH_S)
+#define ICM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define ICM_RDN_ECO_HIGH_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_struct.h
new file mode 100644
index 0000000000..92fe8de9fd
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/icm_sys_struct.h
@@ -0,0 +1,521 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: ICM VER DATE REG */
+/** Type of ver_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [31:0]; default: 539165204;
+         *  NA
+         */
+        uint32_t reg_ver_date:32;
+    };
+    uint32_t val;
+} icm_ver_date_reg_t;
+
+
+/** Group: ICM CLK EN REG */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} icm_clk_en_reg_t;
+
+
+/** Group: ICM DLOCK STATUS REG */
+/** Type of dlock_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_mst : RO; bitpos: [3:0]; default: 0;
+         *  Lowest numbered deadlocked master
+         */
+        uint32_t reg_dlock_mst:4;
+        /** reg_dlock_slv : RO; bitpos: [6:4]; default: 0;
+         *  Slave with which dlock_mst is deadlocked
+         */
+        uint32_t reg_dlock_slv:3;
+        /** reg_dlock_id : RO; bitpos: [10:7]; default: 0;
+         *  AXI ID of deadlocked transaction
+         */
+        uint32_t reg_dlock_id:4;
+        /** reg_dlock_wr : RO; bitpos: [11]; default: 0;
+         *  Asserted if deadlocked transaction is a write
+         */
+        uint32_t reg_dlock_wr:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} icm_dlock_status_reg_t;
+
+
+/** Group: ICM INT RAW REG */
+/** Type of int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dlock_int_raw:1;
+        /** reg_icm_sys_addrhole_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_int_raw:1;
+        /** reg_icm_cpu_addrhole_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_cpu_addrhole_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} icm_int_raw_reg_t;
+
+
+/** Group: ICM INT ST REG */
+/** Type of int_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_int_st : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dlock_int_st:1;
+        /** reg_icm_sys_addrhole_int_st : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_int_st:1;
+        /** reg_icm_cpu_addrhole_int_st : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_cpu_addrhole_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} icm_int_st_reg_t;
+
+
+/** Group: ICM INT ENA REG */
+/** Type of int_ena register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_int_ena : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t reg_dlock_int_ena:1;
+        /** reg_icm_sys_addrhole_int_ena : R/W; bitpos: [1]; default: 1;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_int_ena:1;
+        /** reg_icm_cpu_addrhole_int_ena : R/W; bitpos: [2]; default: 1;
+         *  NA
+         */
+        uint32_t reg_icm_cpu_addrhole_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} icm_int_ena_reg_t;
+
+
+/** Group: ICM INT CLR REG */
+/** Type of int_clr register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_int_clr : WT; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dlock_int_clr:1;
+        /** reg_icm_sys_addrhole_int_clr : WT; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_int_clr:1;
+        /** reg_icm_cpu_addrhole_int_clr : WT; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_cpu_addrhole_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} icm_int_clr_reg_t;
+
+
+/** Group: ICM MST ARB PRIORITY REG0 REG */
+/** Type of mst_arb_priority_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cpu_priority : R/W; bitpos: [3:0]; default: 0;
+         *  CPU arbitration priority for command channels between masters connected to sys_icm
+         */
+        uint32_t reg_cpu_priority:4;
+        /** reg_cache_priority : R/W; bitpos: [7:4]; default: 0;
+         *  CACHE arbitration priority for command channels between masters connected to sys_icm
+         */
+        uint32_t reg_cache_priority:4;
+        /** reg_dma2d_priority : R/W; bitpos: [11:8]; default: 0;
+         *  GFX arbitration priority for command channels between masters connected to sys_icm
+         */
+        uint32_t reg_dma2d_priority:4;
+        /** reg_gdma_mst1_priority : R/W; bitpos: [15:12]; default: 0;
+         *  GDMA mst1 arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_gdma_mst1_priority:4;
+        /** reg_gdma_mst2_priority : R/W; bitpos: [19:16]; default: 0;
+         *  GDMA mst2 arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_gdma_mst2_priority:4;
+        /** reg_h264_m1_priority : R/W; bitpos: [23:20]; default: 0;
+         *  H264 mst1 arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_h264_m1_priority:4;
+        /** reg_h264_m2_priority : R/W; bitpos: [27:24]; default: 0;
+         *  H264 mst2 arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_h264_m2_priority:4;
+        /** reg_axi_pdma_priority : R/W; bitpos: [31:28]; default: 0;
+         *  AXI PDMA  arbitration priority for command channels between masters connected to
+         *  sys_icm
+         */
+        uint32_t reg_axi_pdma_priority:4;
+    };
+    uint32_t val;
+} icm_mst_arb_priority_reg0_reg_t;
+
+
+/** Group: ICM SLV ARB PRIORITY REG */
+/** Type of slv_arb_priority register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** reg_l2mem_priority : R/W; bitpos: [5:3]; default: 0;
+         *  L2MEM arbitration priority for response channels between slaves connected to sys_icm
+         */
+        uint32_t reg_l2mem_priority:3;
+        uint32_t reserved_6:6;
+        /** reg_flash_mspi_priority : R/W; bitpos: [14:12]; default: 0;
+         *  FLASH MSPI arbitration priority for response channels between slaves connected to
+         *  sys_icm
+         */
+        uint32_t reg_flash_mspi_priority:3;
+        /** reg_psram_mspi_priority : R/W; bitpos: [17:15]; default: 0;
+         *  PSRAM MSPI arbitration priority for response channels between slaves connected to
+         *  sys_icm
+         */
+        uint32_t reg_psram_mspi_priority:3;
+        /** reg_lcd_priority : R/W; bitpos: [20:18]; default: 0;
+         *  MIPI_LCD registers arbitration priority for response channels between slaves
+         *  connected to sys_icm
+         */
+        uint32_t reg_lcd_priority:3;
+        /** reg_cam_priority : R/W; bitpos: [23:21]; default: 0;
+         *  MIPI_CAM registers arbitration priority for response channels between slaves
+         *  connected to sys_icm
+         */
+        uint32_t reg_cam_priority:3;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} icm_slv_arb_priority_reg_t;
+
+
+/** Group: ICM MST ARQOS REG0 REG */
+/** Type of mst_arqos_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cpu_arqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cpu_arqos:4;
+        /** reg_cache_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cache_arqos:4;
+        /** reg_dma2d_arqos : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma2d_arqos:4;
+        /** reg_gdma_mst1_arqos : R/W; bitpos: [15:12]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gdma_mst1_arqos:4;
+        /** reg_gdma_mst2_arqos : R/W; bitpos: [19:16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gdma_mst2_arqos:4;
+        /** reg_h264_dma2d_m1_arqos : R/W; bitpos: [23:20]; default: 0;
+         *  NA
+         */
+        uint32_t reg_h264_dma2d_m1_arqos:4;
+        /** reg_h264_dma2d_m2_arqos : R/W; bitpos: [27:24]; default: 0;
+         *  NA
+         */
+        uint32_t reg_h264_dma2d_m2_arqos:4;
+        /** reg_axi_pdma_int_arqos : R/W; bitpos: [31:28]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_pdma_int_arqos:4;
+    };
+    uint32_t val;
+} icm_mst_arqos_reg0_reg_t;
+
+
+/** Group: ICM MST AWQOS REG0 REG */
+/** Type of mst_awqos_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cpu_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cpu_awqos:4;
+        /** reg_cache_awqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cache_awqos:4;
+        /** reg_dma2d_awqos : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma2d_awqos:4;
+        /** reg_gdma_mst1_awqos : R/W; bitpos: [15:12]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gdma_mst1_awqos:4;
+        /** reg_gdma_mst2_awqos : R/W; bitpos: [19:16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gdma_mst2_awqos:4;
+        /** reg_h264_dma2d_m1_awqos : R/W; bitpos: [23:20]; default: 0;
+         *  NA
+         */
+        uint32_t reg_h264_dma2d_m1_awqos:4;
+        /** reg_h264_dma2d_m2_awqos : R/W; bitpos: [27:24]; default: 0;
+         *  NA
+         */
+        uint32_t reg_h264_dma2d_m2_awqos:4;
+        /** reg_pdma_int_awqos : R/W; bitpos: [31:28]; default: 0;
+         *  NA
+         */
+        uint32_t reg_pdma_int_awqos:4;
+    };
+    uint32_t val;
+} icm_mst_awqos_reg0_reg_t;
+
+
+/** Group: ICM ADDRHOLE ADDR REG */
+/** Type of sys_addrhole_addr register
+ *  icm sys addr hole address registers
+ */
+typedef union {
+    struct {
+        /** reg_icm_sys_addrhole_addr : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_icm_sys_addrhole_addr:32;
+    };
+    uint32_t val;
+} icm_sys_addrhole_addr_reg_t;
+
+/** Type of cpu_addrhole_addr register
+ *  icm cpu addr hole address registers
+ */
+typedef union {
+    struct {
+        /** reg_icm_cpu_addrhole_addr : RO; bitpos: [31:0]; default: 0;
+         *  It is illegall access address if reg_icm_cpu_addrhole_secure is 1. Otherwise, it
+         *  the address without permission to access.
+         */
+        uint32_t reg_icm_cpu_addrhole_addr:32;
+    };
+    uint32_t val;
+} icm_cpu_addrhole_addr_reg_t;
+
+
+/** Group: ICM ADDRHOLE INFO REG */
+/** Type of sys_addrhole_info register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_icm_sys_addrhole_id : RO; bitpos: [7:0]; default: 0;
+         *  master id = 4-bit CID + 4-bit  UID(refer to related IP) . CID is used to verify
+         *  master in icm. CID: 4'h1: cache, 4'h5 gdma mst1, 4'h6: gdma mst2, 4'h8: axi pdma,
+         *  4'ha: dma2d, 4'hb: h264 mst1, 4'hc: h264 mst2.
+         */
+        uint32_t reg_icm_sys_addrhole_id:8;
+        /** reg_icm_sys_addrhole_wr : RO; bitpos: [8]; default: 0;
+         *  1: illegal address access, 0: access without permission
+         */
+        uint32_t reg_icm_sys_addrhole_wr:1;
+        /** reg_icm_sys_addrhole_secure : RO; bitpos: [9]; default: 0;
+         *  It is illegall access address if reg_icm_cpu_addrhole_secure is 1, Otherwise, it
+         *  the address without permission to access.
+         */
+        uint32_t reg_icm_sys_addrhole_secure:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} icm_sys_addrhole_info_reg_t;
+
+/** Type of cpu_addrhole_info register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_icm_cpu_addrhole_id : RO; bitpos: [4:0]; default: 0;
+         *  master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4:
+         *  regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha
+         *  tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma.
+         */
+        uint32_t reg_icm_cpu_addrhole_id:5;
+        uint32_t reserved_5:3;
+        /** reg_icm_cpu_addrhole_wr : RO; bitpos: [8]; default: 0;
+         *  1:write trans, 0: read trans.
+         */
+        uint32_t reg_icm_cpu_addrhole_wr:1;
+        /** reg_icm_cpu_addrhole_secure : RO; bitpos: [9]; default: 0;
+         *  1: illegal address access, 0: access without permission
+         */
+        uint32_t reg_icm_cpu_addrhole_secure:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} icm_cpu_addrhole_info_reg_t;
+
+
+/** Group: ICM DLOCK TIMEOUT REG */
+/** Type of dlock_timeout register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_dlock_timeout : R/W; bitpos: [12:0]; default: 2048;
+         *  if no response until reg_dlock_timeout bus clock cycle, deadlock will happen
+         */
+        uint32_t reg_dlock_timeout:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} icm_dlock_timeout_reg_t;
+
+
+/** Group: ICM RDN ECO CS REG */
+/** Type of rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rdn_eco_en:1;
+        /** reg_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} icm_rdn_eco_cs_reg_t;
+
+
+/** Group: ICM RDN ECO LOW REG */
+/** Type of rdn_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} icm_rdn_eco_low_reg_t;
+
+
+/** Group: ICM RDN ECO HIGH REG */
+/** Type of rdn_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  NA
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} icm_rdn_eco_high_reg_t;
+
+
+typedef struct {
+    volatile icm_ver_date_reg_t ver_date;
+    volatile icm_clk_en_reg_t clk_en;
+    volatile icm_dlock_status_reg_t dlock_status;
+    volatile icm_int_raw_reg_t int_raw;
+    volatile icm_int_st_reg_t int_st;
+    volatile icm_int_ena_reg_t int_ena;
+    volatile icm_int_clr_reg_t int_clr;
+    volatile icm_mst_arb_priority_reg0_reg_t mst_arb_priority_reg0;
+    uint32_t reserved_020;
+    volatile icm_slv_arb_priority_reg_t slv_arb_priority;
+    volatile icm_mst_arqos_reg0_reg_t mst_arqos_reg0;
+    uint32_t reserved_02c;
+    volatile icm_mst_awqos_reg0_reg_t mst_awqos_reg0;
+    uint32_t reserved_034;
+    volatile icm_sys_addrhole_addr_reg_t sys_addrhole_addr;
+    volatile icm_sys_addrhole_info_reg_t sys_addrhole_info;
+    volatile icm_cpu_addrhole_addr_reg_t cpu_addrhole_addr;
+    volatile icm_cpu_addrhole_info_reg_t cpu_addrhole_info;
+    volatile icm_dlock_timeout_reg_t dlock_timeout;
+    uint32_t reserved_04c;
+    volatile icm_rdn_eco_cs_reg_t rdn_eco_cs;
+    volatile icm_rdn_eco_low_reg_t rdn_eco_low;
+    volatile icm_rdn_eco_high_reg_t rdn_eco_high;
+} icm_dev_t;
+
+extern icm_dev_t ICM_SYS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(icm_dev_t) == 0x5c, "Invalid size of icm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core0_reg.h b/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core0_reg.h
new file mode 100644
index 0000000000..0bfca792f2
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core0_reg.h
@@ -0,0 +1,3592 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CORE0_LP_RTC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_RTC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
+/** CORE0_CORE0_LP_RTC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_MAP_M  (CORE0_CORE0_LP_RTC_INT_MAP_V << CORE0_CORE0_LP_RTC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_MAP_S  0
+/** CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_RTC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
+/** CORE0_CORE0_LP_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_MAP_M  (CORE0_CORE0_LP_WDT_INT_MAP_V << CORE0_CORE0_LP_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_MAP_S  0
+/** CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_WDT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_TIMER_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
+/** CORE0_CORE0_LP_TIMER_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_M  (CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_MAP_S  0
+/** CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_TIMER_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc)
+/** CORE0_CORE0_LP_TIMER_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_M  (CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V << CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_MAP_S  0
+/** CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TIMER_REG_1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_MB_HP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_MB_HP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
+/** CORE0_CORE0_MB_HP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_MAP_M  (CORE0_CORE0_MB_HP_INT_MAP_V << CORE0_CORE0_MB_HP_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_MAP_S  0
+/** CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_MB_HP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_MB_LP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_MB_LP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
+/** CORE0_CORE0_MB_LP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_MAP_M  (CORE0_CORE0_MB_LP_INT_MAP_V << CORE0_CORE0_MB_LP_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_MAP_S  0
+/** CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_MB_LP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PMU_REG_0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMU_REG_0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
+/** CORE0_CORE0_PMU_REG_0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_MAP_M  (CORE0_CORE0_PMU_REG_0_INT_MAP_V << CORE0_CORE0_PMU_REG_0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_MAP_S  0
+/** CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMU_REG_0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PMU_REG_1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMU_REG_1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c)
+/** CORE0_CORE0_PMU_REG_1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_MAP_M  (CORE0_CORE0_PMU_REG_1_INT_MAP_V << CORE0_CORE0_PMU_REG_1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_MAP_S  0
+/** CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMU_REG_1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_ANAPERI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_ANAPERI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
+/** CORE0_CORE0_LP_ANAPERI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_MAP_M  (CORE0_CORE0_LP_ANAPERI_INT_MAP_V << CORE0_CORE0_LP_ANAPERI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_MAP_S  0
+/** CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_ANAPERI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
+/** CORE0_CORE0_LP_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_MAP_M  (CORE0_CORE0_LP_ADC_INT_MAP_V << CORE0_CORE0_LP_ADC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_MAP_S  0
+/** CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_ADC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_GPIO_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_GPIO_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
+/** CORE0_CORE0_LP_GPIO_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_MAP_M  (CORE0_CORE0_LP_GPIO_INT_MAP_V << CORE0_CORE0_LP_GPIO_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_MAP_S  0
+/** CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_GPIO_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_I2C_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_I2C_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c)
+/** CORE0_CORE0_LP_I2C_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_MAP_M  (CORE0_CORE0_LP_I2C_INT_MAP_V << CORE0_CORE0_LP_I2C_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_MAP_S  0
+/** CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_I2C_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_I2S_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_I2S_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
+/** CORE0_CORE0_LP_I2S_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_MAP_M  (CORE0_CORE0_LP_I2S_INT_MAP_V << CORE0_CORE0_LP_I2S_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_MAP_S  0
+/** CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_I2S_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_SPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
+/** CORE0_CORE0_LP_SPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_MAP_M  (CORE0_CORE0_LP_SPI_INT_MAP_V << CORE0_CORE0_LP_SPI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_MAP_S  0
+/** CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_TOUCH_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TOUCH_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
+/** CORE0_CORE0_LP_TOUCH_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_MAP_M  (CORE0_CORE0_LP_TOUCH_INT_MAP_V << CORE0_CORE0_LP_TOUCH_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_MAP_S  0
+/** CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TOUCH_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_TSENS_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_TSENS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c)
+/** CORE0_CORE0_LP_TSENS_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_MAP_M  (CORE0_CORE0_LP_TSENS_INT_MAP_V << CORE0_CORE0_LP_TSENS_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_MAP_S  0
+/** CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_TSENS_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_UART_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_UART_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
+/** CORE0_CORE0_LP_UART_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_MAP_M  (CORE0_CORE0_LP_UART_INT_MAP_V << CORE0_CORE0_LP_UART_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_MAP_S  0
+/** CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_UART_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_EFUSE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
+/** CORE0_CORE0_LP_EFUSE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_MAP_M  (CORE0_CORE0_LP_EFUSE_INT_MAP_V << CORE0_CORE0_LP_EFUSE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_MAP_S  0
+/** CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_EFUSE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_SW_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SW_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
+/** CORE0_CORE0_LP_SW_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_MAP_M  (CORE0_CORE0_LP_SW_INT_MAP_V << CORE0_CORE0_LP_SW_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_MAP_S  0
+/** CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SW_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c)
+/** CORE0_CORE0_LP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_MAP_M  (CORE0_CORE0_LP_SYSREG_INT_MAP_V << CORE0_CORE0_LP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_MAP_S  0
+/** CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_SYSREG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LP_HUK_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LP_HUK_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
+/** CORE0_CORE0_LP_HUK_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_MAP_M  (CORE0_CORE0_LP_HUK_INT_MAP_V << CORE0_CORE0_LP_HUK_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_MAP_S  0
+/** CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LP_HUK_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SYS_ICM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYS_ICM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
+/** CORE0_CORE0_SYS_ICM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_MAP_M  (CORE0_CORE0_SYS_ICM_INT_MAP_V << CORE0_CORE0_SYS_ICM_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_MAP_S  0
+/** CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYS_ICM_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_USB_DEVICE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
+/** CORE0_CORE0_USB_DEVICE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_MAP_M  (CORE0_CORE0_USB_DEVICE_INT_MAP_V << CORE0_CORE0_USB_DEVICE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_MAP_S  0
+/** CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_DEVICE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SDIO_HOST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SDIO_HOST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c)
+/** CORE0_CORE0_SDIO_HOST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_MAP_M  (CORE0_CORE0_SDIO_HOST_INT_MAP_V << CORE0_CORE0_SDIO_HOST_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_MAP_S  0
+/** CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SDIO_HOST_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GDMA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GDMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
+/** CORE0_CORE0_GDMA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_MAP_M  (CORE0_CORE0_GDMA_INT_MAP_V << CORE0_CORE0_GDMA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_MAP_S  0
+/** CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GDMA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SPI2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SPI2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
+/** CORE0_CORE0_SPI2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_MAP_M  (CORE0_CORE0_SPI2_INT_MAP_V << CORE0_CORE0_SPI2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_MAP_S  0
+/** CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SPI2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SPI3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SPI3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
+/** CORE0_CORE0_SPI3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_MAP_M  (CORE0_CORE0_SPI3_INT_MAP_V << CORE0_CORE0_SPI3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_MAP_S  0
+/** CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SPI3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2S0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
+/** CORE0_CORE0_I2S0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_MAP_M  (CORE0_CORE0_I2S0_INT_MAP_V << CORE0_CORE0_I2S0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_MAP_S  0
+/** CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2S1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
+/** CORE0_CORE0_I2S1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_MAP_M  (CORE0_CORE0_I2S1_INT_MAP_V << CORE0_CORE0_I2S1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_MAP_S  0
+/** CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2S2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2S2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
+/** CORE0_CORE0_I2S2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_MAP_M  (CORE0_CORE0_I2S2_INT_MAP_V << CORE0_CORE0_I2S2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_MAP_S  0
+/** CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2S2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UHCI0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UHCI0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
+/** CORE0_CORE0_UHCI0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_MAP_M  (CORE0_CORE0_UHCI0_INT_MAP_V << CORE0_CORE0_UHCI0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_MAP_S  0
+/** CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UHCI0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c)
+/** CORE0_CORE0_UART0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART0_INT_MAP_M  (CORE0_CORE0_UART0_INT_MAP_V << CORE0_CORE0_UART0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART0_INT_MAP_S  0
+/** CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
+/** CORE0_CORE0_UART1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART1_INT_MAP_M  (CORE0_CORE0_UART1_INT_MAP_V << CORE0_CORE0_UART1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART1_INT_MAP_S  0
+/** CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
+/** CORE0_CORE0_UART2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART2_INT_MAP_M  (CORE0_CORE0_UART2_INT_MAP_V << CORE0_CORE0_UART2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART2_INT_MAP_S  0
+/** CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
+/** CORE0_CORE0_UART3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART3_INT_MAP_M  (CORE0_CORE0_UART3_INT_MAP_V << CORE0_CORE0_UART3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART3_INT_MAP_S  0
+/** CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_UART4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_UART4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
+/** CORE0_CORE0_UART4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_UART4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART4_INT_MAP_M  (CORE0_CORE0_UART4_INT_MAP_V << CORE0_CORE0_UART4_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_UART4_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_UART4_INT_MAP_S  0
+/** CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_UART4_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LCD_CAM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
+/** CORE0_CORE0_LCD_CAM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_MAP_M  (CORE0_CORE0_LCD_CAM_INT_MAP_V << CORE0_CORE0_LCD_CAM_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_MAP_S  0
+/** CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LCD_CAM_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ADC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
+/** CORE0_CORE0_ADC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ADC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ADC_INT_MAP_M  (CORE0_CORE0_ADC_INT_MAP_V << CORE0_CORE0_ADC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ADC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ADC_INT_MAP_S  0
+/** CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ADC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PWM0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PWM0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
+/** CORE0_CORE0_PWM0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_MAP_M  (CORE0_CORE0_PWM0_INT_MAP_V << CORE0_CORE0_PWM0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_MAP_S  0
+/** CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PWM0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PWM1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PWM1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
+/** CORE0_CORE0_PWM1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_MAP_M  (CORE0_CORE0_PWM1_INT_MAP_V << CORE0_CORE0_PWM1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_MAP_S  0
+/** CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PWM1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CAN0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
+/** CORE0_CORE0_CAN0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_MAP_M  (CORE0_CORE0_CAN0_INT_MAP_V << CORE0_CORE0_CAN0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_MAP_S  0
+/** CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CAN1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4)
+/** CORE0_CORE0_CAN1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_MAP_M  (CORE0_CORE0_CAN1_INT_MAP_V << CORE0_CORE0_CAN1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_MAP_S  0
+/** CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CAN2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CAN2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8)
+/** CORE0_CORE0_CAN2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_MAP_M  (CORE0_CORE0_CAN2_INT_MAP_V << CORE0_CORE0_CAN2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_MAP_S  0
+/** CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CAN2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_RMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_RMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
+/** CORE0_CORE0_RMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_RMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_RMT_INT_MAP_M  (CORE0_CORE0_RMT_INT_MAP_V << CORE0_CORE0_RMT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_RMT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_RMT_INT_MAP_S  0
+/** CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_RMT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2C0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2C0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0)
+/** CORE0_CORE0_I2C0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_MAP_M  (CORE0_CORE0_I2C0_INT_MAP_V << CORE0_CORE0_I2C0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_MAP_S  0
+/** CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2C0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I2C1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I2C1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4)
+/** CORE0_CORE0_I2C1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_MAP_M  (CORE0_CORE0_I2C1_INT_MAP_V << CORE0_CORE0_I2C1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_MAP_S  0
+/** CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I2C1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP0_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8)
+/** CORE0_CORE0_TIMERGRP0_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_MAP_M  (CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP0_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc)
+/** CORE0_CORE0_TIMERGRP0_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_MAP_M  (CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_T1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP0_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
+/** CORE0_CORE0_TIMERGRP0_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_M  (CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP0_WDT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP1_T0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
+/** CORE0_CORE0_TIMERGRP1_T0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_MAP_M  (CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP1_T1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
+/** CORE0_CORE0_TIMERGRP1_T1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_MAP_M  (CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V << CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_T1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_TIMERGRP1_WDT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
+/** CORE0_CORE0_TIMERGRP1_WDT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_M  (CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V << CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_MAP_S  0
+/** CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_TIMERGRP1_WDT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LEDC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
+/** CORE0_CORE0_LEDC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_MAP_M  (CORE0_CORE0_LEDC_INT_MAP_V << CORE0_CORE0_LEDC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_MAP_S  0
+/** CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LEDC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SYSTIMER_TARGET0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
+/** CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_M  (CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
+/** CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SYSTIMER_TARGET1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
+/** CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_M  (CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
+/** CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SYSTIMER_TARGET2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
+/** CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_M  (CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V << CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
+/** CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SYSTIMER_TARGET2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
+/** CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
+/** CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8)
+/** CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec)
+/** CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0)
+/** CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4)
+/** CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_M  (CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_MAP_S  0
+/** CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AHB_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8)
+/** CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc)
+/** CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
+/** CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
+/** CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
+/** CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
+/** CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_M  (CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V << CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PDMA_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_RSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
+/** CORE0_CORE0_RSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_RSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_RSA_INT_MAP_M  (CORE0_CORE0_RSA_INT_MAP_V << CORE0_CORE0_RSA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_RSA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_RSA_INT_MAP_S  0
+/** CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_RSA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AES_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
+/** CORE0_CORE0_AES_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AES_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AES_INT_MAP_M  (CORE0_CORE0_AES_INT_MAP_V << CORE0_CORE0_AES_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AES_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AES_INT_MAP_S  0
+/** CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AES_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SHA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
+/** CORE0_CORE0_SHA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SHA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SHA_INT_MAP_M  (CORE0_CORE0_SHA_INT_MAP_V << CORE0_CORE0_SHA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SHA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SHA_INT_MAP_S  0
+/** CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SHA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ECC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
+/** CORE0_CORE0_ECC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ECC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ECC_INT_MAP_M  (CORE0_CORE0_ECC_INT_MAP_V << CORE0_CORE0_ECC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ECC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ECC_INT_MAP_S  0
+/** CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ECC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ECDSA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ECDSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
+/** CORE0_CORE0_ECDSA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_MAP_M  (CORE0_CORE0_ECDSA_INT_MAP_V << CORE0_CORE0_ECDSA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_MAP_S  0
+/** CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ECDSA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_KM_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_KM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
+/** CORE0_CORE0_KM_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_KM_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_KM_INT_MAP_M  (CORE0_CORE0_KM_INT_MAP_V << CORE0_CORE0_KM_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_KM_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_KM_INT_MAP_S  0
+/** CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_KM_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_INT0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
+/** CORE0_CORE0_GPIO_INT0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_MAP_M  (CORE0_CORE0_GPIO_INT0_MAP_V << CORE0_CORE0_GPIO_INT0_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_MAP_S  0
+/** CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT0_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_INT1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
+/** CORE0_CORE0_GPIO_INT1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_MAP_M  (CORE0_CORE0_GPIO_INT1_MAP_V << CORE0_CORE0_GPIO_INT1_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_MAP_S  0
+/** CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT1_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_INT2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
+/** CORE0_CORE0_GPIO_INT2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_MAP_M  (CORE0_CORE0_GPIO_INT2_MAP_V << CORE0_CORE0_GPIO_INT2_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_MAP_S  0
+/** CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT2_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_INT3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_INT3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
+/** CORE0_CORE0_GPIO_INT3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_MAP_M  (CORE0_CORE0_GPIO_INT3_MAP_V << CORE0_CORE0_GPIO_INT3_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_MAP_S  0
+/** CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_INT3_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GPIO_PAD_COMP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GPIO_PAD_COMP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
+/** CORE0_CORE0_GPIO_PAD_COMP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_M  (CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V << CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_MAP_S  0
+/** CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GPIO_PAD_COMP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CPU_INT_FROM_CPU_0_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
+/** CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_MAP_S  0
+/** CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_V << CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_0_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CPU_INT_FROM_CPU_1_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
+/** CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_MAP_S  0
+/** CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_V << CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_1_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CPU_INT_FROM_CPU_2_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
+/** CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_MAP_S  0
+/** CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_V << CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_2_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CPU_INT_FROM_CPU_3_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CPU_INT_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
+/** CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_M  (CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V << CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_MAP_S  0
+/** CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_V << CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CPU_INT_FROM_CPU_3_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CACHE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CACHE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
+/** CORE0_CORE0_CACHE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_MAP_M  (CORE0_CORE0_CACHE_INT_MAP_V << CORE0_CORE0_CACHE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_MAP_S  0
+/** CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CACHE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_FLASH_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_FLASH_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
+/** CORE0_CORE0_FLASH_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_MAP_M  (CORE0_CORE0_FLASH_MSPI_INT_MAP_V << CORE0_CORE0_FLASH_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_MAP_S  0
+/** CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_FLASH_MSPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
+/** CORE0_CORE0_CSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_MAP_M  (CORE0_CORE0_CSI_BRIDGE_INT_MAP_V << CORE0_CORE0_CSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_MAP_S  0
+/** CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DSI_BRIDGE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DSI_BRIDGE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
+/** CORE0_CORE0_DSI_BRIDGE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_MAP_M  (CORE0_CORE0_DSI_BRIDGE_INT_MAP_V << CORE0_CORE0_DSI_BRIDGE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_MAP_S  0
+/** CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DSI_BRIDGE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c)
+/** CORE0_CORE0_CSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CSI_INT_MAP_M  (CORE0_CORE0_CSI_INT_MAP_V << CORE0_CORE0_CSI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CSI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CSI_INT_MAP_S  0
+/** CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CSI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DSI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DSI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
+/** CORE0_CORE0_DSI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DSI_INT_MAP_M  (CORE0_CORE0_DSI_INT_MAP_V << CORE0_CORE0_DSI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DSI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DSI_INT_MAP_S  0
+/** CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DSI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_GMII_PHY_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_GMII_PHY_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
+/** CORE0_CORE0_GMII_PHY_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_MAP_M  (CORE0_CORE0_GMII_PHY_INT_MAP_V << CORE0_CORE0_GMII_PHY_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_MAP_S  0
+/** CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_GMII_PHY_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_LPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_LPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
+/** CORE0_CORE0_LPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_LPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LPI_INT_MAP_M  (CORE0_CORE0_LPI_INT_MAP_V << CORE0_CORE0_LPI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_LPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_LPI_INT_MAP_S  0
+/** CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_LPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PMT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PMT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c)
+/** CORE0_CORE0_PMT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PMT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMT_INT_MAP_M  (CORE0_CORE0_PMT_INT_MAP_V << CORE0_CORE0_PMT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PMT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PMT_INT_MAP_S  0
+/** CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PMT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_SBD_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_SBD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
+/** CORE0_CORE0_SBD_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_SBD_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SBD_INT_MAP_M  (CORE0_CORE0_SBD_INT_MAP_V << CORE0_CORE0_SBD_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_SBD_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_SBD_INT_MAP_S  0
+/** CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_SBD_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_USB_OTG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
+/** CORE0_CORE0_USB_OTG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_MAP_M  (CORE0_CORE0_USB_OTG_INT_MAP_V << CORE0_CORE0_USB_OTG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_MAP_S  0
+/** CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
+/** CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_M  (CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V << CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_MAP_S  0
+/** CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6];
+ *  default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7];
+ *  default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG_ENDP_MULTI_PROC_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_JPEG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_JPEG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c)
+/** CORE0_CORE0_JPEG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_MAP_M  (CORE0_CORE0_JPEG_INT_MAP_V << CORE0_CORE0_JPEG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_MAP_S  0
+/** CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_JPEG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PPA_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PPA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
+/** CORE0_CORE0_PPA_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PPA_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PPA_INT_MAP_M  (CORE0_CORE0_PPA_INT_MAP_V << CORE0_CORE0_PPA_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PPA_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PPA_INT_MAP_S  0
+/** CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PPA_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CORE0_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
+/** CORE0_CORE0_CORE0_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_MAP_M  (CORE0_CORE0_CORE0_TRACE_INT_MAP_V << CORE0_CORE0_CORE0_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_MAP_S  0
+/** CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CORE0_TRACE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_CORE1_TRACE_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE1_TRACE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
+/** CORE0_CORE0_CORE1_TRACE_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_MAP_M  (CORE0_CORE0_CORE1_TRACE_INT_MAP_V << CORE0_CORE0_CORE1_TRACE_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_MAP_S  0
+/** CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_CORE1_TRACE_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_CORE_CTRL_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_CORE_CTRL_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c)
+/** CORE0_CORE0_HP_CORE_CTRL_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_MAP_M  (CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V << CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_MAP_S  0
+/** CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_CORE_CTRL_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ISP_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ISP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
+/** CORE0_CORE0_ISP_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ISP_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ISP_INT_MAP_M  (CORE0_CORE0_ISP_INT_MAP_V << CORE0_CORE0_ISP_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ISP_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ISP_INT_MAP_S  0
+/** CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ISP_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I3C_MST_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I3C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
+/** CORE0_CORE0_I3C_MST_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_MAP_M  (CORE0_CORE0_I3C_MST_INT_MAP_V << CORE0_CORE0_I3C_MST_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_MAP_S  0
+/** CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I3C_MST_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_I3C_SLV_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_I3C_SLV_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
+/** CORE0_CORE0_I3C_SLV_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_MAP_M  (CORE0_CORE0_I3C_SLV_INT_MAP_V << CORE0_CORE0_I3C_SLV_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_MAP_S  0
+/** CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_I3C_SLV_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_USB_OTG11_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_USB_OTG11_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c)
+/** CORE0_CORE0_USB_OTG11_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_MAP_M  (CORE0_CORE0_USB_OTG11_INT_MAP_V << CORE0_CORE0_USB_OTG11_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_MAP_S  0
+/** CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_USB_OTG11_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0)
+/** CORE0_CORE0_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_M  (CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4)
+/** CORE0_CORE0_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_M  (CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8)
+/** CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac)
+/** CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0)
+/** CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PSRAM_MSPI_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PSRAM_MSPI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b4)
+/** CORE0_CORE0_PSRAM_MSPI_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_MAP_M  (CORE0_CORE0_PSRAM_MSPI_INT_MAP_V << CORE0_CORE0_PSRAM_MSPI_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_MAP_S  0
+/** CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PSRAM_MSPI_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_SYSREG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_SYSREG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b8)
+/** CORE0_CORE0_HP_SYSREG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_MAP_M  (CORE0_CORE0_HP_SYSREG_INT_MAP_V << CORE0_CORE0_HP_SYSREG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_MAP_S  0
+/** CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_SYSREG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_PCNT_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_PCNT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1bc)
+/** CORE0_CORE0_PCNT_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_MAP_M  (CORE0_CORE0_PCNT_INT_MAP_V << CORE0_CORE0_PCNT_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_MAP_S  0
+/** CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_PCNT_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_PAU_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PAU_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c0)
+/** CORE0_CORE0_HP_PAU_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_MAP_M  (CORE0_CORE0_HP_PAU_INT_MAP_V << CORE0_CORE0_HP_PAU_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_MAP_S  0
+/** CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PAU_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_PARLIO_RX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c4)
+/** CORE0_CORE0_HP_PARLIO_RX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_MAP_M  (CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_MAP_S  0
+/** CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_RX_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_HP_PARLIO_TX_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c8)
+/** CORE0_CORE0_HP_PARLIO_TX_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_MAP_M  (CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V << CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_MAP_S  0
+/** CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_HP_PARLIO_TX_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1cc)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d0)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d4)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d8)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1dc)
+/** CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_OUT_CH4_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e0)
+/** CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH0_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e4)
+/** CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH1_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e8)
+/** CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ec)
+/** CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f0)
+/** CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH4_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_DMA2D_IN_CH5_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f4)
+/** CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_M  (CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V << CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_MAP_S  0
+/** CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_DMA2D_IN_CH5_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_H264_REG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_H264_REG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f8)
+/** CORE0_CORE0_H264_REG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_MAP_M  (CORE0_CORE0_H264_REG_INT_MAP_V << CORE0_CORE0_H264_REG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_MAP_S  0
+/** CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_H264_REG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_ASSIST_DEBUG_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1fc)
+/** CORE0_CORE0_ASSIST_DEBUG_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_MAP_M  (CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V << CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_MAP_S  0
+/** CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_ASSIST_DEBUG_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_INTR_STATUS_REG_0_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x200)
+/** CORE0_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_0_M  (CORE0_CORE0_INTR_STATUS_0_V << CORE0_CORE0_INTR_STATUS_0_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_0_S  0
+
+/** CORE0_INTR_STATUS_REG_1_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x204)
+/** CORE0_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_1_M  (CORE0_CORE0_INTR_STATUS_1_V << CORE0_CORE0_INTR_STATUS_1_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_1_S  0
+
+/** CORE0_INTR_STATUS_REG_2_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x208)
+/** CORE0_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_2_M  (CORE0_CORE0_INTR_STATUS_2_V << CORE0_CORE0_INTR_STATUS_2_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_2_S  0
+
+/** CORE0_INTR_STATUS_REG_3_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20c)
+/** CORE0_CORE0_INTR_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_3_M  (CORE0_CORE0_INTR_STATUS_3_V << CORE0_CORE0_INTR_STATUS_3_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_3_S  0
+
+/** CORE0_CLOCK_GATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x210)
+/** CORE0_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_REG_CLK_EN    (BIT(0))
+#define INTERRUPT_CORE0_CORE0_REG_CLK_EN_M  (CORE0_CORE0_REG_CLK_EN_V << CORE0_CORE0_REG_CLK_EN_S)
+#define INTERRUPT_CORE0_CORE0_REG_CLK_EN_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_REG_CLK_EN_S  0
+
+/** CORE0_DMA2D_IN_CH2_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x214)
+/** CORE0_CORE0_DMA2D_IN_CH2_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_M  (CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_V << CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_IN_CH2_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_DMA2D_OUT_CH3_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x218)
+/** CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_M  (CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_V << CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_MAP_S  0
+/** CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_DMA2D_OUT_CH3_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_AXI_PERF_MON_INT_MAP_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_AXI_PERF_MON_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x21c)
+/** CORE0_CORE0_AXI_PERF_MON_INT_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_MAP_M  (CORE0_CORE0_AXI_PERF_MON_INT_MAP_V << CORE0_CORE0_AXI_PERF_MON_INT_MAP_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_MAP_S  0
+/** CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC : R/W; bitpos: [6]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC    (BIT(6))
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_M  (CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_V << CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_PASS_IN_SEC_S  6
+/** CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG : R/W; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG    (BIT(7))
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_M  (CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_V << CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_S)
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_V  0x00000001U
+#define INTERRUPT_CORE0_CORE0_AXI_PERF_MON_INT_SRC_IN_SEC_FLAG_S  7
+
+/** CORE0_INTR_STATUS_REG_4_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x220)
+/** CORE0_CORE0_INTR_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_4_M  (CORE0_CORE0_INTR_STATUS_4_V << CORE0_CORE0_INTR_STATUS_4_S)
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_STATUS_4_S  0
+
+/** CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x228)
+/** CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_M  (CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_V << CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_S  0
+
+/** CORE0_INTR_SEC_STATUS_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SEC_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x22c)
+/** CORE0_CORE0_INTR_SEC_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SEC_STATUS    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SEC_STATUS_M  (CORE0_CORE0_INTR_SEC_STATUS_V << CORE0_CORE0_INTR_SEC_STATUS_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SEC_STATUS_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SEC_STATUS_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x230)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_0_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x234)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_1_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x238)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_2_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x23c)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_3_S  0
+
+/** CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x240)
+/** CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_M  (CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_V << CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_S)
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTR_SRC_PASS_IN_SEC_STATUS_4_S  0
+
+/** CORE0_INTERRUPT_REG_DATE_REG register
+ *  NA
+ */
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3fc)
+/** CORE0_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 38806144;
+ *  NA
+ */
+#define INTERRUPT_CORE0_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTERRUPT_REG_DATE_M  (CORE0_CORE0_INTERRUPT_REG_DATE_V << CORE0_CORE0_INTERRUPT_REG_DATE_S)
+#define INTERRUPT_CORE0_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
+#define INTERRUPT_CORE0_CORE0_INTERRUPT_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core0_struct.h b/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core0_struct.h
new file mode 100644
index 0000000000..3b33d6c820
--- /dev/null
+++ b/components/soc/esp32p4/register/hw_ver2/soc/interrupt_core0_struct.h
@@ -0,0 +1,3528 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: CORE0 LP RTC INT MAP REG */
+/** Type of lp_rtc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_rtc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_rtc_int_map:6;
+        /** core0_lp_rtc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_rtc_int_src_pass_in_sec:1;
+        /** core0_lp_rtc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_rtc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_rtc_int_map_reg_t;
+
+
+/** Group: CORE0 LP WDT INT MAP REG */
+/** Type of lp_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_wdt_int_map:6;
+        /** core0_lp_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_wdt_int_src_pass_in_sec:1;
+        /** core0_lp_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_wdt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_wdt_int_map_reg_t;
+
+
+/** Group: CORE0 LP TIMER REG 0 INT MAP REG */
+/** Type of lp_timer_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_timer_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_timer_reg_0_int_map:6;
+        /** core0_lp_timer_reg_0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_timer_reg_0_int_src_pass_in_sec:1;
+        /** core0_lp_timer_reg_0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_timer_reg_0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_timer_reg_0_int_map_reg_t;
+
+
+/** Group: CORE0 LP TIMER REG 1 INT MAP REG */
+/** Type of lp_timer_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_timer_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_timer_reg_1_int_map:6;
+        /** core0_lp_timer_reg_1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_timer_reg_1_int_src_pass_in_sec:1;
+        /** core0_lp_timer_reg_1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_timer_reg_1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_timer_reg_1_int_map_reg_t;
+
+
+/** Group: CORE0 MB HP INT MAP REG */
+/** Type of mb_hp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_mb_hp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_mb_hp_int_map:6;
+        /** core0_mb_hp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_mb_hp_int_src_pass_in_sec:1;
+        /** core0_mb_hp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_mb_hp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_mb_hp_int_map_reg_t;
+
+
+/** Group: CORE0 MB LP INT MAP REG */
+/** Type of mb_lp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_mb_lp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_mb_lp_int_map:6;
+        /** core0_mb_lp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_mb_lp_int_src_pass_in_sec:1;
+        /** core0_mb_lp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_mb_lp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_mb_lp_int_map_reg_t;
+
+
+/** Group: CORE0 PMU REG 0 INT MAP REG */
+/** Type of pmu_reg_0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pmu_reg_0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pmu_reg_0_int_map:6;
+        /** core0_pmu_reg_0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmu_reg_0_int_src_pass_in_sec:1;
+        /** core0_pmu_reg_0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmu_reg_0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pmu_reg_0_int_map_reg_t;
+
+
+/** Group: CORE0 PMU REG 1 INT MAP REG */
+/** Type of pmu_reg_1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pmu_reg_1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pmu_reg_1_int_map:6;
+        /** core0_pmu_reg_1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmu_reg_1_int_src_pass_in_sec:1;
+        /** core0_pmu_reg_1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmu_reg_1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pmu_reg_1_int_map_reg_t;
+
+
+/** Group: CORE0 LP ANAPERI INT MAP REG */
+/** Type of lp_anaperi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_anaperi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_anaperi_int_map:6;
+        /** core0_lp_anaperi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_anaperi_int_src_pass_in_sec:1;
+        /** core0_lp_anaperi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_anaperi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_anaperi_int_map_reg_t;
+
+
+/** Group: CORE0 LP ADC INT MAP REG */
+/** Type of lp_adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_adc_int_map:6;
+        /** core0_lp_adc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_adc_int_src_pass_in_sec:1;
+        /** core0_lp_adc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_adc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_adc_int_map_reg_t;
+
+
+/** Group: CORE0 LP GPIO INT MAP REG */
+/** Type of lp_gpio_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_gpio_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_gpio_int_map:6;
+        /** core0_lp_gpio_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_gpio_int_src_pass_in_sec:1;
+        /** core0_lp_gpio_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_gpio_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_gpio_int_map_reg_t;
+
+
+/** Group: CORE0 LP I2C INT MAP REG */
+/** Type of lp_i2c_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_i2c_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_i2c_int_map:6;
+        /** core0_lp_i2c_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_i2c_int_src_pass_in_sec:1;
+        /** core0_lp_i2c_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_i2c_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_i2c_int_map_reg_t;
+
+
+/** Group: CORE0 LP I2S INT MAP REG */
+/** Type of lp_i2s_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_i2s_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_i2s_int_map:6;
+        /** core0_lp_i2s_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_i2s_int_src_pass_in_sec:1;
+        /** core0_lp_i2s_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_i2s_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_i2s_int_map_reg_t;
+
+
+/** Group: CORE0 LP SPI INT MAP REG */
+/** Type of lp_spi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_spi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_spi_int_map:6;
+        /** core0_lp_spi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_spi_int_src_pass_in_sec:1;
+        /** core0_lp_spi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_spi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_spi_int_map_reg_t;
+
+
+/** Group: CORE0 LP TOUCH INT MAP REG */
+/** Type of lp_touch_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_touch_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_touch_int_map:6;
+        /** core0_lp_touch_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_touch_int_src_pass_in_sec:1;
+        /** core0_lp_touch_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_touch_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_touch_int_map_reg_t;
+
+
+/** Group: CORE0 LP TSENS INT MAP REG */
+/** Type of lp_tsens_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_tsens_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_tsens_int_map:6;
+        /** core0_lp_tsens_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_tsens_int_src_pass_in_sec:1;
+        /** core0_lp_tsens_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_tsens_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_tsens_int_map_reg_t;
+
+
+/** Group: CORE0 LP UART INT MAP REG */
+/** Type of lp_uart_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_uart_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_uart_int_map:6;
+        /** core0_lp_uart_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_uart_int_src_pass_in_sec:1;
+        /** core0_lp_uart_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_uart_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_uart_int_map_reg_t;
+
+
+/** Group: CORE0 LP EFUSE INT MAP REG */
+/** Type of lp_efuse_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_efuse_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_efuse_int_map:6;
+        /** core0_lp_efuse_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_efuse_int_src_pass_in_sec:1;
+        /** core0_lp_efuse_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_efuse_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_efuse_int_map_reg_t;
+
+
+/** Group: CORE0 LP SW INT MAP REG */
+/** Type of lp_sw_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_sw_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_sw_int_map:6;
+        /** core0_lp_sw_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_sw_int_src_pass_in_sec:1;
+        /** core0_lp_sw_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_sw_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_sw_int_map_reg_t;
+
+
+/** Group: CORE0 LP SYSREG INT MAP REG */
+/** Type of lp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_sysreg_int_map:6;
+        /** core0_lp_sysreg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_sysreg_int_src_pass_in_sec:1;
+        /** core0_lp_sysreg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_sysreg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_sysreg_int_map_reg_t;
+
+
+/** Group: CORE0 LP HUK INT MAP REG */
+/** Type of lp_huk_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lp_huk_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lp_huk_int_map:6;
+        /** core0_lp_huk_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_huk_int_src_pass_in_sec:1;
+        /** core0_lp_huk_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lp_huk_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lp_huk_int_map_reg_t;
+
+
+/** Group: CORE0 SYS ICM INT MAP REG */
+/** Type of sys_icm_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_sys_icm_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_sys_icm_int_map:6;
+        /** core0_sys_icm_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sys_icm_int_src_pass_in_sec:1;
+        /** core0_sys_icm_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sys_icm_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_sys_icm_int_map_reg_t;
+
+
+/** Group: CORE0 USB DEVICE INT MAP REG */
+/** Type of usb_device_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_usb_device_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_usb_device_int_map:6;
+        /** core0_usb_device_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_device_int_src_pass_in_sec:1;
+        /** core0_usb_device_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_device_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_usb_device_int_map_reg_t;
+
+
+/** Group: CORE0 SDIO HOST INT MAP REG */
+/** Type of sdio_host_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_sdio_host_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_sdio_host_int_map:6;
+        /** core0_sdio_host_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sdio_host_int_src_pass_in_sec:1;
+        /** core0_sdio_host_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sdio_host_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_sdio_host_int_map_reg_t;
+
+
+/** Group: CORE0 GDMA INT MAP REG */
+/** Type of gdma_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gdma_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gdma_int_map:6;
+        /** core0_gdma_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gdma_int_src_pass_in_sec:1;
+        /** core0_gdma_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gdma_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gdma_int_map_reg_t;
+
+
+/** Group: CORE0 SPI2 INT MAP REG */
+/** Type of spi2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_spi2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_spi2_int_map:6;
+        /** core0_spi2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_spi2_int_src_pass_in_sec:1;
+        /** core0_spi2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_spi2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_spi2_int_map_reg_t;
+
+
+/** Group: CORE0 SPI3 INT MAP REG */
+/** Type of spi3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_spi3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_spi3_int_map:6;
+        /** core0_spi3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_spi3_int_src_pass_in_sec:1;
+        /** core0_spi3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_spi3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_spi3_int_map_reg_t;
+
+
+/** Group: CORE0 I2S0 INT MAP REG */
+/** Type of i2s0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2s0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2s0_int_map:6;
+        /** core0_i2s0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s0_int_src_pass_in_sec:1;
+        /** core0_i2s0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2s0_int_map_reg_t;
+
+
+/** Group: CORE0 I2S1 INT MAP REG */
+/** Type of i2s1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2s1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2s1_int_map:6;
+        /** core0_i2s1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s1_int_src_pass_in_sec:1;
+        /** core0_i2s1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2s1_int_map_reg_t;
+
+
+/** Group: CORE0 I2S2 INT MAP REG */
+/** Type of i2s2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2s2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2s2_int_map:6;
+        /** core0_i2s2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s2_int_src_pass_in_sec:1;
+        /** core0_i2s2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2s2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2s2_int_map_reg_t;
+
+
+/** Group: CORE0 UHCI0 INT MAP REG */
+/** Type of uhci0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uhci0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uhci0_int_map:6;
+        /** core0_uhci0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uhci0_int_src_pass_in_sec:1;
+        /** core0_uhci0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uhci0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uhci0_int_map_reg_t;
+
+
+/** Group: CORE0 UART0 INT MAP REG */
+/** Type of uart0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart0_int_map:6;
+        /** core0_uart0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart0_int_src_pass_in_sec:1;
+        /** core0_uart0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart0_int_map_reg_t;
+
+
+/** Group: CORE0 UART1 INT MAP REG */
+/** Type of uart1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart1_int_map:6;
+        /** core0_uart1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart1_int_src_pass_in_sec:1;
+        /** core0_uart1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart1_int_map_reg_t;
+
+
+/** Group: CORE0 UART2 INT MAP REG */
+/** Type of uart2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart2_int_map:6;
+        /** core0_uart2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart2_int_src_pass_in_sec:1;
+        /** core0_uart2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart2_int_map_reg_t;
+
+
+/** Group: CORE0 UART3 INT MAP REG */
+/** Type of uart3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart3_int_map:6;
+        /** core0_uart3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart3_int_src_pass_in_sec:1;
+        /** core0_uart3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart3_int_map_reg_t;
+
+
+/** Group: CORE0 UART4 INT MAP REG */
+/** Type of uart4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_uart4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_uart4_int_map:6;
+        /** core0_uart4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart4_int_src_pass_in_sec:1;
+        /** core0_uart4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_uart4_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_uart4_int_map_reg_t;
+
+
+/** Group: CORE0 LCD CAM INT MAP REG */
+/** Type of lcd_cam_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lcd_cam_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lcd_cam_int_map:6;
+        /** core0_lcd_cam_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lcd_cam_int_src_pass_in_sec:1;
+        /** core0_lcd_cam_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lcd_cam_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lcd_cam_int_map_reg_t;
+
+
+/** Group: CORE0 ADC INT MAP REG */
+/** Type of adc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_adc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_adc_int_map:6;
+        /** core0_adc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_adc_int_src_pass_in_sec:1;
+        /** core0_adc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_adc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_adc_int_map_reg_t;
+
+
+/** Group: CORE0 PWM0 INT MAP REG */
+/** Type of pwm0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pwm0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pwm0_int_map:6;
+        /** core0_pwm0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pwm0_int_src_pass_in_sec:1;
+        /** core0_pwm0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pwm0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pwm0_int_map_reg_t;
+
+
+/** Group: CORE0 PWM1 INT MAP REG */
+/** Type of pwm1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pwm1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pwm1_int_map:6;
+        /** core0_pwm1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pwm1_int_src_pass_in_sec:1;
+        /** core0_pwm1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pwm1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pwm1_int_map_reg_t;
+
+
+/** Group: CORE0 CAN0 INT MAP REG */
+/** Type of can0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_can0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_can0_int_map:6;
+        /** core0_can0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can0_int_src_pass_in_sec:1;
+        /** core0_can0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_can0_int_map_reg_t;
+
+
+/** Group: CORE0 CAN1 INT MAP REG */
+/** Type of can1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_can1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_can1_int_map:6;
+        /** core0_can1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can1_int_src_pass_in_sec:1;
+        /** core0_can1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_can1_int_map_reg_t;
+
+
+/** Group: CORE0 CAN2 INT MAP REG */
+/** Type of can2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_can2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_can2_int_map:6;
+        /** core0_can2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can2_int_src_pass_in_sec:1;
+        /** core0_can2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_can2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_can2_int_map_reg_t;
+
+
+/** Group: CORE0 RMT INT MAP REG */
+/** Type of rmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_rmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_rmt_int_map:6;
+        /** core0_rmt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_rmt_int_src_pass_in_sec:1;
+        /** core0_rmt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_rmt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_rmt_int_map_reg_t;
+
+
+/** Group: CORE0 I2C0 INT MAP REG */
+/** Type of i2c0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2c0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2c0_int_map:6;
+        /** core0_i2c0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2c0_int_src_pass_in_sec:1;
+        /** core0_i2c0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2c0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2c0_int_map_reg_t;
+
+
+/** Group: CORE0 I2C1 INT MAP REG */
+/** Type of i2c1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i2c1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i2c1_int_map:6;
+        /** core0_i2c1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2c1_int_src_pass_in_sec:1;
+        /** core0_i2c1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i2c1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i2c1_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP0 T0 INT MAP REG */
+/** Type of timergrp0_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp0_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp0_t0_int_map:6;
+        /** core0_timergrp0_t0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_t0_int_src_pass_in_sec:1;
+        /** core0_timergrp0_t0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_t0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp0_t0_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP0 T1 INT MAP REG */
+/** Type of timergrp0_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp0_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp0_t1_int_map:6;
+        /** core0_timergrp0_t1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_t1_int_src_pass_in_sec:1;
+        /** core0_timergrp0_t1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_t1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp0_t1_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP0 WDT INT MAP REG */
+/** Type of timergrp0_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp0_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp0_wdt_int_map:6;
+        /** core0_timergrp0_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_wdt_int_src_pass_in_sec:1;
+        /** core0_timergrp0_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp0_wdt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp0_wdt_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP1 T0 INT MAP REG */
+/** Type of timergrp1_t0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp1_t0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp1_t0_int_map:6;
+        /** core0_timergrp1_t0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_t0_int_src_pass_in_sec:1;
+        /** core0_timergrp1_t0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_t0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp1_t0_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP1 T1 INT MAP REG */
+/** Type of timergrp1_t1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp1_t1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp1_t1_int_map:6;
+        /** core0_timergrp1_t1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_t1_int_src_pass_in_sec:1;
+        /** core0_timergrp1_t1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_t1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp1_t1_int_map_reg_t;
+
+
+/** Group: CORE0 TIMERGRP1 WDT INT MAP REG */
+/** Type of timergrp1_wdt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_timergrp1_wdt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_timergrp1_wdt_int_map:6;
+        /** core0_timergrp1_wdt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_wdt_int_src_pass_in_sec:1;
+        /** core0_timergrp1_wdt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_timergrp1_wdt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_timergrp1_wdt_int_map_reg_t;
+
+
+/** Group: CORE0 LEDC INT MAP REG */
+/** Type of ledc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ledc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ledc_int_map:6;
+        /** core0_ledc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ledc_int_src_pass_in_sec:1;
+        /** core0_ledc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ledc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ledc_int_map_reg_t;
+
+
+/** Group: CORE0 SYSTIMER TARGET0 INT MAP REG */
+/** Type of systimer_target0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_systimer_target0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_systimer_target0_int_map:6;
+        /** core0_systimer_target0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target0_int_src_pass_in_sec:1;
+        /** core0_systimer_target0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_systimer_target0_int_map_reg_t;
+
+
+/** Group: CORE0 SYSTIMER TARGET1 INT MAP REG */
+/** Type of systimer_target1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_systimer_target1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_systimer_target1_int_map:6;
+        /** core0_systimer_target1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target1_int_src_pass_in_sec:1;
+        /** core0_systimer_target1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_systimer_target1_int_map_reg_t;
+
+
+/** Group: CORE0 SYSTIMER TARGET2 INT MAP REG */
+/** Type of systimer_target2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_systimer_target2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_systimer_target2_int_map:6;
+        /** core0_systimer_target2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target2_int_src_pass_in_sec:1;
+        /** core0_systimer_target2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_systimer_target2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_systimer_target2_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA IN CH0 INT MAP REG */
+/** Type of ahb_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_in_ch0_int_map:6;
+        /** core0_ahb_pdma_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch0_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA IN CH1 INT MAP REG */
+/** Type of ahb_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_in_ch1_int_map:6;
+        /** core0_ahb_pdma_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch1_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA IN CH2 INT MAP REG */
+/** Type of ahb_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_in_ch2_int_map:6;
+        /** core0_ahb_pdma_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch2_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA OUT CH0 INT MAP REG */
+/** Type of ahb_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_out_ch0_int_map:6;
+        /** core0_ahb_pdma_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch0_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA OUT CH1 INT MAP REG */
+/** Type of ahb_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_out_ch1_int_map:6;
+        /** core0_ahb_pdma_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch1_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 AHB PDMA OUT CH2 INT MAP REG */
+/** Type of ahb_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ahb_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ahb_pdma_out_ch2_int_map:6;
+        /** core0_ahb_pdma_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch2_int_src_pass_in_sec:1;
+        /** core0_ahb_pdma_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ahb_pdma_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ahb_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA IN CH0 INT MAP REG */
+/** Type of axi_pdma_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_in_ch0_int_map:6;
+        /** core0_axi_pdma_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch0_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA IN CH1 INT MAP REG */
+/** Type of axi_pdma_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_in_ch1_int_map:6;
+        /** core0_axi_pdma_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch1_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA IN CH2 INT MAP REG */
+/** Type of axi_pdma_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_in_ch2_int_map:6;
+        /** core0_axi_pdma_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch2_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA OUT CH0 INT MAP REG */
+/** Type of axi_pdma_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_out_ch0_int_map:6;
+        /** core0_axi_pdma_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch0_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA OUT CH1 INT MAP REG */
+/** Type of axi_pdma_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_out_ch1_int_map:6;
+        /** core0_axi_pdma_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch1_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PDMA OUT CH2 INT MAP REG */
+/** Type of axi_pdma_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_pdma_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_pdma_out_ch2_int_map:6;
+        /** core0_axi_pdma_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch2_int_src_pass_in_sec:1;
+        /** core0_axi_pdma_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_pdma_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_pdma_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 RSA INT MAP REG */
+/** Type of rsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_rsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_rsa_int_map:6;
+        /** core0_rsa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_rsa_int_src_pass_in_sec:1;
+        /** core0_rsa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_rsa_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_rsa_int_map_reg_t;
+
+
+/** Group: CORE0 AES INT MAP REG */
+/** Type of aes_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_aes_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_aes_int_map:6;
+        /** core0_aes_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_aes_int_src_pass_in_sec:1;
+        /** core0_aes_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_aes_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_aes_int_map_reg_t;
+
+
+/** Group: CORE0 SHA INT MAP REG */
+/** Type of sha_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_sha_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_sha_int_map:6;
+        /** core0_sha_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sha_int_src_pass_in_sec:1;
+        /** core0_sha_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sha_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_sha_int_map_reg_t;
+
+
+/** Group: CORE0 ECC INT MAP REG */
+/** Type of ecc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ecc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ecc_int_map:6;
+        /** core0_ecc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ecc_int_src_pass_in_sec:1;
+        /** core0_ecc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ecc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ecc_int_map_reg_t;
+
+
+/** Group: CORE0 ECDSA INT MAP REG */
+/** Type of ecdsa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ecdsa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ecdsa_int_map:6;
+        /** core0_ecdsa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ecdsa_int_src_pass_in_sec:1;
+        /** core0_ecdsa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ecdsa_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ecdsa_int_map_reg_t;
+
+
+/** Group: CORE0 KM INT MAP REG */
+/** Type of km_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_km_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_km_int_map:6;
+        /** core0_km_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_km_int_src_pass_in_sec:1;
+        /** core0_km_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_km_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_km_int_map_reg_t;
+
+
+/** Group: CORE0 GPIO INT0 MAP REG */
+/** Type of gpio_int0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_int0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_int0_map:6;
+        /** core0_gpio_int0_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int0_src_pass_in_sec:1;
+        /** core0_gpio_int0_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int0_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_int0_map_reg_t;
+
+
+/** Group: CORE0 GPIO INT1 MAP REG */
+/** Type of gpio_int1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_int1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_int1_map:6;
+        /** core0_gpio_int1_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int1_src_pass_in_sec:1;
+        /** core0_gpio_int1_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int1_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_int1_map_reg_t;
+
+
+/** Group: CORE0 GPIO INT2 MAP REG */
+/** Type of gpio_int2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_int2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_int2_map:6;
+        /** core0_gpio_int2_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int2_src_pass_in_sec:1;
+        /** core0_gpio_int2_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int2_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_int2_map_reg_t;
+
+
+/** Group: CORE0 GPIO INT3 MAP REG */
+/** Type of gpio_int3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_int3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_int3_map:6;
+        /** core0_gpio_int3_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int3_src_pass_in_sec:1;
+        /** core0_gpio_int3_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_int3_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_int3_map_reg_t;
+
+
+/** Group: CORE0 GPIO PAD COMP INT MAP REG */
+/** Type of gpio_pad_comp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gpio_pad_comp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gpio_pad_comp_int_map:6;
+        /** core0_gpio_pad_comp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_pad_comp_int_src_pass_in_sec:1;
+        /** core0_gpio_pad_comp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gpio_pad_comp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gpio_pad_comp_int_map_reg_t;
+
+
+/** Group: CORE0 CPU INT FROM CPU 0 MAP REG */
+/** Type of cpu_int_from_cpu_0_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cpu_int_from_cpu_0_map:6;
+        /** core0_cpu_int_from_cpu_0_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_0_src_pass_in_sec:1;
+        /** core0_cpu_int_from_cpu_0_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_0_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cpu_int_from_cpu_0_map_reg_t;
+
+
+/** Group: CORE0 CPU INT FROM CPU 1 MAP REG */
+/** Type of cpu_int_from_cpu_1_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cpu_int_from_cpu_1_map:6;
+        /** core0_cpu_int_from_cpu_1_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_1_src_pass_in_sec:1;
+        /** core0_cpu_int_from_cpu_1_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_1_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cpu_int_from_cpu_1_map_reg_t;
+
+
+/** Group: CORE0 CPU INT FROM CPU 2 MAP REG */
+/** Type of cpu_int_from_cpu_2_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cpu_int_from_cpu_2_map:6;
+        /** core0_cpu_int_from_cpu_2_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_2_src_pass_in_sec:1;
+        /** core0_cpu_int_from_cpu_2_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_2_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cpu_int_from_cpu_2_map_reg_t;
+
+
+/** Group: CORE0 CPU INT FROM CPU 3 MAP REG */
+/** Type of cpu_int_from_cpu_3_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cpu_int_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cpu_int_from_cpu_3_map:6;
+        /** core0_cpu_int_from_cpu_3_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_3_src_pass_in_sec:1;
+        /** core0_cpu_int_from_cpu_3_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cpu_int_from_cpu_3_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cpu_int_from_cpu_3_map_reg_t;
+
+
+/** Group: CORE0 CACHE INT MAP REG */
+/** Type of cache_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_cache_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_cache_int_map:6;
+        /** core0_cache_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cache_int_src_pass_in_sec:1;
+        /** core0_cache_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_cache_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_cache_int_map_reg_t;
+
+
+/** Group: CORE0 FLASH MSPI INT MAP REG */
+/** Type of flash_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_flash_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_flash_mspi_int_map:6;
+        /** core0_flash_mspi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_flash_mspi_int_src_pass_in_sec:1;
+        /** core0_flash_mspi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_flash_mspi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_flash_mspi_int_map_reg_t;
+
+
+/** Group: CORE0 CSI BRIDGE INT MAP REG */
+/** Type of csi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_csi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_csi_bridge_int_map:6;
+        /** core0_csi_bridge_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_csi_bridge_int_src_pass_in_sec:1;
+        /** core0_csi_bridge_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_csi_bridge_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_csi_bridge_int_map_reg_t;
+
+
+/** Group: CORE0 DSI BRIDGE INT MAP REG */
+/** Type of dsi_bridge_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dsi_bridge_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dsi_bridge_int_map:6;
+        /** core0_dsi_bridge_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dsi_bridge_int_src_pass_in_sec:1;
+        /** core0_dsi_bridge_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dsi_bridge_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dsi_bridge_int_map_reg_t;
+
+
+/** Group: CORE0 CSI INT MAP REG */
+/** Type of csi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_csi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_csi_int_map:6;
+        /** core0_csi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_csi_int_src_pass_in_sec:1;
+        /** core0_csi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_csi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_csi_int_map_reg_t;
+
+
+/** Group: CORE0 DSI INT MAP REG */
+/** Type of dsi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dsi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dsi_int_map:6;
+        /** core0_dsi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dsi_int_src_pass_in_sec:1;
+        /** core0_dsi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dsi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dsi_int_map_reg_t;
+
+
+/** Group: CORE0 GMII PHY INT MAP REG */
+/** Type of gmii_phy_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_gmii_phy_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_gmii_phy_int_map:6;
+        /** core0_gmii_phy_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gmii_phy_int_src_pass_in_sec:1;
+        /** core0_gmii_phy_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_gmii_phy_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_gmii_phy_int_map_reg_t;
+
+
+/** Group: CORE0 LPI INT MAP REG */
+/** Type of lpi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_lpi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_lpi_int_map:6;
+        /** core0_lpi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lpi_int_src_pass_in_sec:1;
+        /** core0_lpi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_lpi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_lpi_int_map_reg_t;
+
+
+/** Group: CORE0 PMT INT MAP REG */
+/** Type of pmt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pmt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pmt_int_map:6;
+        /** core0_pmt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmt_int_src_pass_in_sec:1;
+        /** core0_pmt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pmt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pmt_int_map_reg_t;
+
+
+/** Group: CORE0 SBD INT MAP REG */
+/** Type of sbd_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_sbd_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_sbd_int_map:6;
+        /** core0_sbd_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sbd_int_src_pass_in_sec:1;
+        /** core0_sbd_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_sbd_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_sbd_int_map_reg_t;
+
+
+/** Group: CORE0 USB OTG INT MAP REG */
+/** Type of usb_otg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_usb_otg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_usb_otg_int_map:6;
+        /** core0_usb_otg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg_int_src_pass_in_sec:1;
+        /** core0_usb_otg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_usb_otg_int_map_reg_t;
+
+
+/** Group: CORE0 USB OTG ENDP MULTI PROC INT MAP REG */
+/** Type of usb_otg_endp_multi_proc_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_usb_otg_endp_multi_proc_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_usb_otg_endp_multi_proc_int_map:6;
+        /** core0_usb_otg_endp_multi_proc_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg_endp_multi_proc_int_src_pass_in_sec:1;
+        /** core0_usb_otg_endp_multi_proc_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg_endp_multi_proc_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_usb_otg_endp_multi_proc_int_map_reg_t;
+
+
+/** Group: CORE0 JPEG INT MAP REG */
+/** Type of jpeg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_jpeg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_jpeg_int_map:6;
+        /** core0_jpeg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_jpeg_int_src_pass_in_sec:1;
+        /** core0_jpeg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_jpeg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_jpeg_int_map_reg_t;
+
+
+/** Group: CORE0 PPA INT MAP REG */
+/** Type of ppa_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_ppa_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_ppa_int_map:6;
+        /** core0_ppa_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ppa_int_src_pass_in_sec:1;
+        /** core0_ppa_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_ppa_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_ppa_int_map_reg_t;
+
+
+/** Group: CORE0 CORE0 TRACE INT MAP REG */
+/** Type of core0_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_core0_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_core0_trace_int_map:6;
+        /** core0_core0_trace_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_core0_trace_int_src_pass_in_sec:1;
+        /** core0_core0_trace_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_core0_trace_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_core0_trace_int_map_reg_t;
+
+
+/** Group: CORE0 CORE1 TRACE INT MAP REG */
+/** Type of core1_trace_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_core1_trace_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_core1_trace_int_map:6;
+        /** core0_core1_trace_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_core1_trace_int_src_pass_in_sec:1;
+        /** core0_core1_trace_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_core1_trace_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_core1_trace_int_map_reg_t;
+
+
+/** Group: CORE0 HP CORE CTRL INT MAP REG */
+/** Type of hp_core_ctrl_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_core_ctrl_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_core_ctrl_int_map:6;
+        /** core0_hp_core_ctrl_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_core_ctrl_int_src_pass_in_sec:1;
+        /** core0_hp_core_ctrl_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_core_ctrl_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_core_ctrl_int_map_reg_t;
+
+
+/** Group: CORE0 ISP INT MAP REG */
+/** Type of isp_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_isp_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_isp_int_map:6;
+        /** core0_isp_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_isp_int_src_pass_in_sec:1;
+        /** core0_isp_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_isp_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_isp_int_map_reg_t;
+
+
+/** Group: CORE0 I3C MST INT MAP REG */
+/** Type of i3c_mst_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i3c_mst_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i3c_mst_int_map:6;
+        /** core0_i3c_mst_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i3c_mst_int_src_pass_in_sec:1;
+        /** core0_i3c_mst_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i3c_mst_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i3c_mst_int_map_reg_t;
+
+
+/** Group: CORE0 I3C SLV INT MAP REG */
+/** Type of i3c_slv_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_i3c_slv_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_i3c_slv_int_map:6;
+        /** core0_i3c_slv_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i3c_slv_int_src_pass_in_sec:1;
+        /** core0_i3c_slv_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_i3c_slv_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_i3c_slv_int_map_reg_t;
+
+
+/** Group: CORE0 USB OTG11 INT MAP REG */
+/** Type of usb_otg11_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_usb_otg11_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_usb_otg11_int_map:6;
+        /** core0_usb_otg11_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg11_int_src_pass_in_sec:1;
+        /** core0_usb_otg11_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_usb_otg11_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_usb_otg11_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D IN CH0 INT MAP REG */
+/** Type of dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_in_ch0_int_map:6;
+        /** core0_dma2d_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch0_int_src_pass_in_sec:1;
+        /** core0_dma2d_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D IN CH1 INT MAP REG */
+/** Type of dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_in_ch1_int_map:6;
+        /** core0_dma2d_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch1_int_src_pass_in_sec:1;
+        /** core0_dma2d_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D OUT CH0 INT MAP REG */
+/** Type of dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_out_ch0_int_map:6;
+        /** core0_dma2d_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch0_int_src_pass_in_sec:1;
+        /** core0_dma2d_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D OUT CH1 INT MAP REG */
+/** Type of dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_out_ch1_int_map:6;
+        /** core0_dma2d_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch1_int_src_pass_in_sec:1;
+        /** core0_dma2d_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D OUT CH2 INT MAP REG */
+/** Type of dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_out_ch2_int_map:6;
+        /** core0_dma2d_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch2_int_src_pass_in_sec:1;
+        /** core0_dma2d_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 PSRAM MSPI INT MAP REG */
+/** Type of psram_mspi_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_psram_mspi_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_psram_mspi_int_map:6;
+        /** core0_psram_mspi_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_psram_mspi_int_src_pass_in_sec:1;
+        /** core0_psram_mspi_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_psram_mspi_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_psram_mspi_int_map_reg_t;
+
+
+/** Group: CORE0 HP SYSREG INT MAP REG */
+/** Type of hp_sysreg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_sysreg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_sysreg_int_map:6;
+        /** core0_hp_sysreg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_sysreg_int_src_pass_in_sec:1;
+        /** core0_hp_sysreg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_sysreg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_sysreg_int_map_reg_t;
+
+
+/** Group: CORE0 PCNT INT MAP REG */
+/** Type of pcnt_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_pcnt_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_pcnt_int_map:6;
+        /** core0_pcnt_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pcnt_int_src_pass_in_sec:1;
+        /** core0_pcnt_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_pcnt_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_pcnt_int_map_reg_t;
+
+
+/** Group: CORE0 HP PAU INT MAP REG */
+/** Type of hp_pau_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_pau_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_pau_int_map:6;
+        /** core0_hp_pau_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_pau_int_src_pass_in_sec:1;
+        /** core0_hp_pau_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_pau_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_pau_int_map_reg_t;
+
+
+/** Group: CORE0 HP PARLIO RX INT MAP REG */
+/** Type of hp_parlio_rx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_parlio_rx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_parlio_rx_int_map:6;
+        /** core0_hp_parlio_rx_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_parlio_rx_int_src_pass_in_sec:1;
+        /** core0_hp_parlio_rx_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_parlio_rx_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_parlio_rx_int_map_reg_t;
+
+
+/** Group: CORE0 HP PARLIO TX INT MAP REG */
+/** Type of hp_parlio_tx_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_hp_parlio_tx_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_hp_parlio_tx_int_map:6;
+        /** core0_hp_parlio_tx_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_parlio_tx_int_src_pass_in_sec:1;
+        /** core0_hp_parlio_tx_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_hp_parlio_tx_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_hp_parlio_tx_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH0 INT MAP REG */
+/** Type of h264_dma2d_out_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch0_int_map:6;
+        /** core0_h264_dma2d_out_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch0_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH1 INT MAP REG */
+/** Type of h264_dma2d_out_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch1_int_map:6;
+        /** core0_h264_dma2d_out_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch1_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH2 INT MAP REG */
+/** Type of h264_dma2d_out_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch2_int_map:6;
+        /** core0_h264_dma2d_out_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch2_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH3 INT MAP REG */
+/** Type of h264_dma2d_out_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch3_int_map:6;
+        /** core0_h264_dma2d_out_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch3_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch3_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D OUT CH4 INT MAP REG */
+/** Type of h264_dma2d_out_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_out_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_out_ch4_int_map:6;
+        /** core0_h264_dma2d_out_ch4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch4_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_out_ch4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_out_ch4_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_out_ch4_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH0 INT MAP REG */
+/** Type of h264_dma2d_in_ch0_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch0_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch0_int_map:6;
+        /** core0_h264_dma2d_in_ch0_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch0_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch0_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch0_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch0_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH1 INT MAP REG */
+/** Type of h264_dma2d_in_ch1_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch1_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch1_int_map:6;
+        /** core0_h264_dma2d_in_ch1_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch1_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch1_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch1_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch1_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH2 INT MAP REG */
+/** Type of h264_dma2d_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch2_int_map:6;
+        /** core0_h264_dma2d_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch2_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH3 INT MAP REG */
+/** Type of h264_dma2d_in_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch3_int_map:6;
+        /** core0_h264_dma2d_in_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch3_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch3_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH4 INT MAP REG */
+/** Type of h264_dma2d_in_ch4_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch4_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch4_int_map:6;
+        /** core0_h264_dma2d_in_ch4_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch4_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch4_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch4_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch4_int_map_reg_t;
+
+
+/** Group: CORE0 H264 DMA2D IN CH5 INT MAP REG */
+/** Type of h264_dma2d_in_ch5_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_dma2d_in_ch5_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_dma2d_in_ch5_int_map:6;
+        /** core0_h264_dma2d_in_ch5_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch5_int_src_pass_in_sec:1;
+        /** core0_h264_dma2d_in_ch5_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_dma2d_in_ch5_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_dma2d_in_ch5_int_map_reg_t;
+
+
+/** Group: CORE0 H264 REG INT MAP REG */
+/** Type of h264_reg_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_h264_reg_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_h264_reg_int_map:6;
+        /** core0_h264_reg_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_reg_int_src_pass_in_sec:1;
+        /** core0_h264_reg_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_h264_reg_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_h264_reg_int_map_reg_t;
+
+
+/** Group: CORE0 ASSIST DEBUG INT MAP REG */
+/** Type of assist_debug_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_assist_debug_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_assist_debug_int_map:6;
+        /** core0_assist_debug_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_assist_debug_int_src_pass_in_sec:1;
+        /** core0_assist_debug_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_assist_debug_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_assist_debug_int_map_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 0 REG */
+/** Type of intr_status_reg_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_0:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_0_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 1 REG */
+/** Type of intr_status_reg_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_1:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_1_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 2 REG */
+/** Type of intr_status_reg_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_2:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_2_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 3 REG */
+/** Type of intr_status_reg_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_3:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_3_reg_t;
+
+
+/** Group: CORE0 CLOCK GATE REG */
+/** Type of clock_gate register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  NA
+         */
+        uint32_t core0_reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} core0_clock_gate_reg_t;
+
+
+/** Group: CORE0 DMA2D IN CH2 INT MAP REG */
+/** Type of dma2d_in_ch2_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_in_ch2_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_in_ch2_int_map:6;
+        /** core0_dma2d_in_ch2_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch2_int_src_pass_in_sec:1;
+        /** core0_dma2d_in_ch2_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_in_ch2_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_in_ch2_int_map_reg_t;
+
+
+/** Group: CORE0 DMA2D OUT CH3 INT MAP REG */
+/** Type of dma2d_out_ch3_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_dma2d_out_ch3_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_dma2d_out_ch3_int_map:6;
+        /** core0_dma2d_out_ch3_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch3_int_src_pass_in_sec:1;
+        /** core0_dma2d_out_ch3_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_dma2d_out_ch3_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_dma2d_out_ch3_int_map_reg_t;
+
+
+/** Group: CORE0 AXI PERF MON INT MAP REG */
+/** Type of axi_perf_mon_int_map register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_axi_perf_mon_int_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_axi_perf_mon_int_map:6;
+        /** core0_axi_perf_mon_int_src_pass_in_sec : R/W; bitpos: [6]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_perf_mon_int_src_pass_in_sec:1;
+        /** core0_axi_perf_mon_int_src_in_sec_flag : R/W; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t core0_axi_perf_mon_int_src_in_sec_flag:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} core0_axi_perf_mon_int_map_reg_t;
+
+
+/** Group: CORE0 INTR STATUS REG 4 REG */
+/** Type of intr_status_reg_4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_status_4:32;
+    };
+    uint32_t val;
+} core0_intr_status_reg_4_reg_t;
+
+
+/** Group: CORE0 INTR SIG IDX ASSERT IN SEC REG */
+/** Type of intr_sig_idx_assert_in_sec register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_sig_idx_assert_in_sec : R/W; bitpos: [5:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_sig_idx_assert_in_sec:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} core0_intr_sig_idx_assert_in_sec_reg_t;
+
+
+/** Group: CORE0 INTR SEC STATUS REG */
+/** Type of intr_sec_status register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_sec_status : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_sec_status:32;
+    };
+    uint32_t val;
+} core0_intr_sec_status_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 0 REG */
+/** Type of intr_src_pass_in_sec_status_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_0:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_0_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 1 REG */
+/** Type of intr_src_pass_in_sec_status_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_1:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_1_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 2 REG */
+/** Type of intr_src_pass_in_sec_status_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_2:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_2_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 3 REG */
+/** Type of intr_src_pass_in_sec_status_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_3:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_3_reg_t;
+
+
+/** Group: CORE0 INTR SRC PASS IN SEC STATUS 4 REG */
+/** Type of intr_src_pass_in_sec_status_4 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_intr_src_pass_in_sec_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t core0_intr_src_pass_in_sec_status_4:32;
+    };
+    uint32_t val;
+} core0_intr_src_pass_in_sec_status_4_reg_t;
+
+
+/** Group: CORE0 INTERRUPT REG DATE REG */
+/** Type of interrupt_reg_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** core0_interrupt_reg_date : R/W; bitpos: [27:0]; default: 38806144;
+         *  NA
+         */
+        uint32_t core0_interrupt_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} core0_interrupt_reg_date_reg_t;
+
+
+typedef struct {
+    volatile core0_lp_rtc_int_map_reg_t lp_rtc_int_map;
+    volatile core0_lp_wdt_int_map_reg_t lp_wdt_int_map;
+    volatile core0_lp_timer_reg_0_int_map_reg_t lp_timer_reg_0_int_map;
+    volatile core0_lp_timer_reg_1_int_map_reg_t lp_timer_reg_1_int_map;
+    volatile core0_mb_hp_int_map_reg_t mb_hp_int_map;
+    volatile core0_mb_lp_int_map_reg_t mb_lp_int_map;
+    volatile core0_pmu_reg_0_int_map_reg_t pmu_reg_0_int_map;
+    volatile core0_pmu_reg_1_int_map_reg_t pmu_reg_1_int_map;
+    volatile core0_lp_anaperi_int_map_reg_t lp_anaperi_int_map;
+    volatile core0_lp_adc_int_map_reg_t lp_adc_int_map;
+    volatile core0_lp_gpio_int_map_reg_t lp_gpio_int_map;
+    volatile core0_lp_i2c_int_map_reg_t lp_i2c_int_map;
+    volatile core0_lp_i2s_int_map_reg_t lp_i2s_int_map;
+    volatile core0_lp_spi_int_map_reg_t lp_spi_int_map;
+    volatile core0_lp_touch_int_map_reg_t lp_touch_int_map;
+    volatile core0_lp_tsens_int_map_reg_t lp_tsens_int_map;
+    volatile core0_lp_uart_int_map_reg_t lp_uart_int_map;
+    volatile core0_lp_efuse_int_map_reg_t lp_efuse_int_map;
+    volatile core0_lp_sw_int_map_reg_t lp_sw_int_map;
+    volatile core0_lp_sysreg_int_map_reg_t lp_sysreg_int_map;
+    volatile core0_lp_huk_int_map_reg_t lp_huk_int_map;
+    volatile core0_sys_icm_int_map_reg_t sys_icm_int_map;
+    volatile core0_usb_device_int_map_reg_t usb_device_int_map;
+    volatile core0_sdio_host_int_map_reg_t sdio_host_int_map;
+    volatile core0_gdma_int_map_reg_t gdma_int_map;
+    volatile core0_spi2_int_map_reg_t spi2_int_map;
+    volatile core0_spi3_int_map_reg_t spi3_int_map;
+    volatile core0_i2s0_int_map_reg_t i2s0_int_map;
+    volatile core0_i2s1_int_map_reg_t i2s1_int_map;
+    volatile core0_i2s2_int_map_reg_t i2s2_int_map;
+    volatile core0_uhci0_int_map_reg_t uhci0_int_map;
+    volatile core0_uart0_int_map_reg_t uart0_int_map;
+    volatile core0_uart1_int_map_reg_t uart1_int_map;
+    volatile core0_uart2_int_map_reg_t uart2_int_map;
+    volatile core0_uart3_int_map_reg_t uart3_int_map;
+    volatile core0_uart4_int_map_reg_t uart4_int_map;
+    volatile core0_lcd_cam_int_map_reg_t lcd_cam_int_map;
+    volatile core0_adc_int_map_reg_t adc_int_map;
+    volatile core0_pwm0_int_map_reg_t pwm0_int_map;
+    volatile core0_pwm1_int_map_reg_t pwm1_int_map;
+    volatile core0_can0_int_map_reg_t can0_int_map;
+    volatile core0_can1_int_map_reg_t can1_int_map;
+    volatile core0_can2_int_map_reg_t can2_int_map;
+    volatile core0_rmt_int_map_reg_t rmt_int_map;
+    volatile core0_i2c0_int_map_reg_t i2c0_int_map;
+    volatile core0_i2c1_int_map_reg_t i2c1_int_map;
+    volatile core0_timergrp0_t0_int_map_reg_t timergrp0_t0_int_map;
+    volatile core0_timergrp0_t1_int_map_reg_t timergrp0_t1_int_map;
+    volatile core0_timergrp0_wdt_int_map_reg_t timergrp0_wdt_int_map;
+    volatile core0_timergrp1_t0_int_map_reg_t timergrp1_t0_int_map;
+    volatile core0_timergrp1_t1_int_map_reg_t timergrp1_t1_int_map;
+    volatile core0_timergrp1_wdt_int_map_reg_t timergrp1_wdt_int_map;
+    volatile core0_ledc_int_map_reg_t ledc_int_map;
+    volatile core0_systimer_target0_int_map_reg_t systimer_target0_int_map;
+    volatile core0_systimer_target1_int_map_reg_t systimer_target1_int_map;
+    volatile core0_systimer_target2_int_map_reg_t systimer_target2_int_map;
+    volatile core0_ahb_pdma_in_ch0_int_map_reg_t ahb_pdma_in_ch0_int_map;
+    volatile core0_ahb_pdma_in_ch1_int_map_reg_t ahb_pdma_in_ch1_int_map;
+    volatile core0_ahb_pdma_in_ch2_int_map_reg_t ahb_pdma_in_ch2_int_map;
+    volatile core0_ahb_pdma_out_ch0_int_map_reg_t ahb_pdma_out_ch0_int_map;
+    volatile core0_ahb_pdma_out_ch1_int_map_reg_t ahb_pdma_out_ch1_int_map;
+    volatile core0_ahb_pdma_out_ch2_int_map_reg_t ahb_pdma_out_ch2_int_map;
+    volatile core0_axi_pdma_in_ch0_int_map_reg_t axi_pdma_in_ch0_int_map;
+    volatile core0_axi_pdma_in_ch1_int_map_reg_t axi_pdma_in_ch1_int_map;
+    volatile core0_axi_pdma_in_ch2_int_map_reg_t axi_pdma_in_ch2_int_map;
+    volatile core0_axi_pdma_out_ch0_int_map_reg_t axi_pdma_out_ch0_int_map;
+    volatile core0_axi_pdma_out_ch1_int_map_reg_t axi_pdma_out_ch1_int_map;
+    volatile core0_axi_pdma_out_ch2_int_map_reg_t axi_pdma_out_ch2_int_map;
+    volatile core0_rsa_int_map_reg_t rsa_int_map;
+    volatile core0_aes_int_map_reg_t aes_int_map;
+    volatile core0_sha_int_map_reg_t sha_int_map;
+    volatile core0_ecc_int_map_reg_t ecc_int_map;
+    volatile core0_ecdsa_int_map_reg_t ecdsa_int_map;
+    volatile core0_km_int_map_reg_t km_int_map;
+    volatile core0_gpio_int0_map_reg_t gpio_int0_map;
+    volatile core0_gpio_int1_map_reg_t gpio_int1_map;
+    volatile core0_gpio_int2_map_reg_t gpio_int2_map;
+    volatile core0_gpio_int3_map_reg_t gpio_int3_map;
+    volatile core0_gpio_pad_comp_int_map_reg_t gpio_pad_comp_int_map;
+    volatile core0_cpu_int_from_cpu_0_map_reg_t cpu_int_from_cpu_0_map;
+    volatile core0_cpu_int_from_cpu_1_map_reg_t cpu_int_from_cpu_1_map;
+    volatile core0_cpu_int_from_cpu_2_map_reg_t cpu_int_from_cpu_2_map;
+    volatile core0_cpu_int_from_cpu_3_map_reg_t cpu_int_from_cpu_3_map;
+    volatile core0_cache_int_map_reg_t cache_int_map;
+    volatile core0_flash_mspi_int_map_reg_t flash_mspi_int_map;
+    volatile core0_csi_bridge_int_map_reg_t csi_bridge_int_map;
+    volatile core0_dsi_bridge_int_map_reg_t dsi_bridge_int_map;
+    volatile core0_csi_int_map_reg_t csi_int_map;
+    volatile core0_dsi_int_map_reg_t dsi_int_map;
+    volatile core0_gmii_phy_int_map_reg_t gmii_phy_int_map;
+    volatile core0_lpi_int_map_reg_t lpi_int_map;
+    volatile core0_pmt_int_map_reg_t pmt_int_map;
+    volatile core0_sbd_int_map_reg_t sbd_int_map;
+    volatile core0_usb_otg_int_map_reg_t usb_otg_int_map;
+    volatile core0_usb_otg_endp_multi_proc_int_map_reg_t usb_otg_endp_multi_proc_int_map;
+    volatile core0_jpeg_int_map_reg_t jpeg_int_map;
+    volatile core0_ppa_int_map_reg_t ppa_int_map;
+    volatile core0_core0_trace_int_map_reg_t core0_trace_int_map;
+    volatile core0_core1_trace_int_map_reg_t core1_trace_int_map;
+    volatile core0_hp_core_ctrl_int_map_reg_t hp_core_ctrl_int_map;
+    volatile core0_isp_int_map_reg_t isp_int_map;
+    volatile core0_i3c_mst_int_map_reg_t i3c_mst_int_map;
+    volatile core0_i3c_slv_int_map_reg_t i3c_slv_int_map;
+    volatile core0_usb_otg11_int_map_reg_t usb_otg11_int_map;
+    volatile core0_dma2d_in_ch0_int_map_reg_t dma2d_in_ch0_int_map;
+    volatile core0_dma2d_in_ch1_int_map_reg_t dma2d_in_ch1_int_map;
+    volatile core0_dma2d_out_ch0_int_map_reg_t dma2d_out_ch0_int_map;
+    volatile core0_dma2d_out_ch1_int_map_reg_t dma2d_out_ch1_int_map;
+    volatile core0_dma2d_out_ch2_int_map_reg_t dma2d_out_ch2_int_map;
+    volatile core0_psram_mspi_int_map_reg_t psram_mspi_int_map;
+    volatile core0_hp_sysreg_int_map_reg_t hp_sysreg_int_map;
+    volatile core0_pcnt_int_map_reg_t pcnt_int_map;
+    volatile core0_hp_pau_int_map_reg_t hp_pau_int_map;
+    volatile core0_hp_parlio_rx_int_map_reg_t hp_parlio_rx_int_map;
+    volatile core0_hp_parlio_tx_int_map_reg_t hp_parlio_tx_int_map;
+    volatile core0_h264_dma2d_out_ch0_int_map_reg_t h264_dma2d_out_ch0_int_map;
+    volatile core0_h264_dma2d_out_ch1_int_map_reg_t h264_dma2d_out_ch1_int_map;
+    volatile core0_h264_dma2d_out_ch2_int_map_reg_t h264_dma2d_out_ch2_int_map;
+    volatile core0_h264_dma2d_out_ch3_int_map_reg_t h264_dma2d_out_ch3_int_map;
+    volatile core0_h264_dma2d_out_ch4_int_map_reg_t h264_dma2d_out_ch4_int_map;
+    volatile core0_h264_dma2d_in_ch0_int_map_reg_t h264_dma2d_in_ch0_int_map;
+    volatile core0_h264_dma2d_in_ch1_int_map_reg_t h264_dma2d_in_ch1_int_map;
+    volatile core0_h264_dma2d_in_ch2_int_map_reg_t h264_dma2d_in_ch2_int_map;
+    volatile core0_h264_dma2d_in_ch3_int_map_reg_t h264_dma2d_in_ch3_int_map;
+    volatile core0_h264_dma2d_in_ch4_int_map_reg_t h264_dma2d_in_ch4_int_map;
+    volatile core0_h264_dma2d_in_ch5_int_map_reg_t h264_dma2d_in_ch5_int_map;
+    volatile core0_h264_reg_int_map_reg_t h264_reg_int_map;
+    volatile core0_assist_debug_int_map_reg_t assist_debug_int_map;
+    volatile core0_intr_status_reg_0_reg_t intr_status_reg_0;
+    volatile core0_intr_status_reg_1_reg_t intr_status_reg_1;
+    volatile core0_intr_status_reg_2_reg_t intr_status_reg_2;
+    volatile core0_intr_status_reg_3_reg_t intr_status_reg_3;
+    volatile core0_clock_gate_reg_t clock_gate;
+    volatile core0_dma2d_in_ch2_int_map_reg_t dma2d_in_ch2_int_map;
+    volatile core0_dma2d_out_ch3_int_map_reg_t dma2d_out_ch3_int_map;
+    volatile core0_axi_perf_mon_int_map_reg_t axi_perf_mon_int_map;
+    volatile core0_intr_status_reg_4_reg_t intr_status_reg_4;
+    uint32_t reserved_224;
+    volatile core0_intr_sig_idx_assert_in_sec_reg_t intr_sig_idx_assert_in_sec;
+    volatile core0_intr_sec_status_reg_t intr_sec_status;
+    volatile core0_intr_src_pass_in_sec_status_0_reg_t intr_src_pass_in_sec_status_0;
+    volatile core0_intr_src_pass_in_sec_status_1_reg_t intr_src_pass_in_sec_status_1;
+    volatile core0_intr_src_pass_in_sec_status_2_reg_t intr_src_pass_in_sec_status_2;
+    volatile core0_intr_src_pass_in_sec_status_3_reg_t intr_src_pass_in_sec_status_3;
+    volatile core0_intr_src_pass_in_sec_status_4_reg_t intr_src_pass_in_sec_status_4;
+    uint32_t reserved_244[110];
+    volatile core0_interrupt_reg_date_reg_t interrupt_reg_date;
+} core0_dev_t;
+
+extern core0_dev_t INTR_CORE0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(core0_dev_t) == 0x400, "Invalid size of core0_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif