diff --git a/components/hal/esp32c2/include/hal/cache_ll.h b/components/hal/esp32c2/include/hal/cache_ll.h
index 50a3952302..1f5dd2f4a1 100644
--- a/components/hal/esp32c2/include/hal/cache_ll.h
+++ b/components/hal/esp32c2/include/hal/cache_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -162,6 +162,32 @@ static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t ty
     Cache_Invalidate_ICache_All();
 }
 
+/**
+ * @brief Freeze Cache
+ *
+ * @param cache_level  level of the cache
+ * @param type         see `cache_type_t`
+ * @param cache_id     id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
+}
+
+/**
+ * @brief Unfreeze Cache
+ *
+ * @param cache_level  level of the cache
+ * @param type         see `cache_type_t`
+ * @param cache_id     id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Freeze_ICache_Disable();
+}
+
 /**
  * @brief Get Cache line size, in bytes
  *
diff --git a/components/hal/esp32c3/include/hal/cache_ll.h b/components/hal/esp32c3/include/hal/cache_ll.h
index 748548079a..e1397016a6 100644
--- a/components/hal/esp32c3/include/hal/cache_ll.h
+++ b/components/hal/esp32c3/include/hal/cache_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -165,6 +165,32 @@ static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t ty
     Cache_Invalidate_ICache_All();
 }
 
+/**
+ * @brief Freeze Cache
+ *
+ * @param cache_level  level of the cache
+ * @param type         see `cache_type_t`
+ * @param cache_id     id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_freeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
+}
+
+/**
+ * @brief Unfreeze Cache
+ *
+ * @param cache_level  level of the cache
+ * @param type         see `cache_type_t`
+ * @param cache_id     id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Freeze_ICache_Disable();
+}
+
 /**
  * @brief Get Cache line size, in bytes
  *
diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
index c7b300bb14..ab19f7ca6a 100644
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@@ -227,6 +227,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
     bool
     default y
 
+config SOC_CACHE_FREEZE_SUPPORTED
+    bool
+    default y
+
 config SOC_CPU_CORES_NUM
     int
     default 1
diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h
index d67b6ad19a..89189ee996 100644
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -93,6 +93,7 @@
 
 /*-------------------------- CACHE CAPS --------------------------------------*/
 #define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+#define SOC_CACHE_FREEZE_SUPPORTED              1
 
 /*-------------------------- CPU CAPS ----------------------------------------*/
 #define SOC_CPU_CORES_NUM               (1U)
diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
index 37eda226ec..afaa031a1c 100644
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -315,6 +315,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
     bool
     default y
 
+config SOC_CACHE_FREEZE_SUPPORTED
+    bool
+    default y
+
 config SOC_CACHE_MEMORY_IBANK_SIZE
     hex
     default 0x4000
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index 92faf08970..9c0b52212c 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -125,6 +125,7 @@
 
 /*-------------------------- CACHE CAPS --------------------------------------*/
 #define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+#define SOC_CACHE_FREEZE_SUPPORTED              1
 #define SOC_CACHE_MEMORY_IBANK_SIZE        0x4000   // has to be same as the definition in ROM component
 
 /*-------------------------- CPU CAPS ----------------------------------------*/