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Merge branch 'bugfix/fix_728_series_reboot_failure' into 'master'

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[system]: Fix two  (re)boot failure issues on ESP32S3Beta

Closes WIFI-3548, WIFI-3559, and IDF-3170

See merge request espressif/esp-idf!13268
This commit is contained in:
Jiang Jiang Jian
2021-04-30 03:20:47 +00:00
parent 4faba8aecf fa8389da00
commit efb9f87951
2 changed files with 13 additions and 12 deletions
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21
components/esp_system/port/soc/esp32s3/system_internal.c
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@@ -54,16 +54,6 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true); wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx);
// Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter
// to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = cpu_hal_get_core_id();
#if !CONFIG_FREERTOS_UNICORE
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_cpu_reset(other_core_id);
esp_cpu_stall(other_core_id);
#endif
// Disable TG0/TG1 watchdogs // Disable TG0/TG1 watchdogs
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
@@ -83,6 +73,17 @@ void IRAM_ATTR esp_restart_noos(void)
Cache_Disable_ICache(); Cache_Disable_ICache();
Cache_Disable_DCache(); Cache_Disable_DCache();
// Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter
// to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = cpu_hal_get_core_id();
#if !CONFIG_FREERTOS_UNICORE
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_cpu_reset(other_core_id);
esp_cpu_stall(other_core_id);
#endif
// 2nd stage bootloader reconfigures SPI flash signals. // 2nd stage bootloader reconfigures SPI flash signals.
// Reset them to the defaults expected by ROM. // Reset them to the defaults expected by ROM.
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);

4
components/spi_flash/cache_utils.c
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@@ -141,9 +141,9 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
// Scheduler hasn't been started yet, it means that spi_flash API is being // Scheduler hasn't been started yet, it means that spi_flash API is being
// called from the 2nd stage bootloader or from user_start_cpu0, i.e. from // called from the 2nd stage bootloader or from user_start_cpu0, i.e. from
// PRO CPU. APP CPU is either in reset or spinning inside user_start_cpu1, // PRO CPU. APP CPU is either in reset or spinning inside user_start_cpu1,
// which is in IRAM. So it is safe to disable cache for the other_cpuid here. // which is in IRAM. So it is safe to disable cache for the other_cpuid after
// esp_intr_noniram_disable.
assert(other_cpuid == 1); assert(other_cpuid == 1);
spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
} else { } else {
// Temporarily raise current task priority to prevent a deadlock while // Temporarily raise current task priority to prevent a deadlock while
// waiting for IPC task to start on the other CPU // waiting for IPC task to start on the other CPU