diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 913bfb6144..71287988ba 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -338,6 +338,10 @@ void IRAM_ATTR call_start_cpu0(void)
     extern void rom_config_data_cache_mode(uint32_t cfg_cache_size, uint8_t cfg_cache_ways, uint8_t cfg_cache_line_size);
     rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE, CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS, CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
     Cache_Resume_DCache(0);
+
+    /*add lock to protect cache operation*/
+    extern void esp_cache_op_lock_init(void);
+    esp_cache_op_lock_init();
 #endif // CONFIG_IDF_TARGET_ESP32S3
 
     if (esp_efuse_check_errors() != ESP_OK) {
diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c
index 0f5c045f0a..974da40bc0 100644
--- a/components/spi_flash/cache_utils.c
+++ b/components/spi_flash/cache_utils.c
@@ -941,3 +941,24 @@ void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
     spi_flash_restore_cache(0, 0); // TODO cache_value should be non-zero
 #endif
 }
+
+#if CONFIG_IDF_TARGET_ESP32S3
+/*protect cache opreation*/
+static spinlock_t cache_op_lock = SPINLOCK_INITIALIZER;
+
+IRAM_ATTR void esp_cache_op_lock(void)
+{
+    portENTER_CRITICAL_SAFE(&cache_op_lock);
+}
+
+IRAM_ATTR void esp_cache_op_unlock(void)
+{
+    portEXIT_CRITICAL_SAFE(&cache_op_lock);
+}
+
+IRAM_ATTR void esp_cache_op_lock_init(void)
+{
+    rom_cache_op_cb.start = esp_cache_op_lock;
+    rom_cache_op_cb.end = esp_cache_op_unlock;
+}
+#endif// CONFIG_IDF_TARGET_ESP32S3