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Merge branch 'cleanup/unicore_reset' into 'master'

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system: Clean up code, some single core chips have useless dual-core code

See merge request espressif/esp-idf!22698
This commit is contained in:
C.S.M
2023-03-13 15:29:07 +08:00
parent 251e0c5fc7 8b5f4f54fc
commit f17bf1dd6a
7 changed files with 19 additions and 140 deletions
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10
components/esp_system/port/soc/esp32/system_internal.c
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@@ -55,7 +55,7 @@ void IRAM_ATTR esp_restart_noos(void)
// to the stalled CPU, preventing current CPU from accessing this pool. // to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = esp_cpu_get_core_id(); const uint32_t core_id = esp_cpu_get_core_id();
const uint32_t other_core_id = (core_id == 0) ? 1 : 0; const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_cpu_reset(other_core_id); esp_rom_software_reset_cpu(other_core_id);
esp_cpu_stall(other_core_id); esp_cpu_stall(other_core_id);
// Other core is now stalled, can access DPORT registers directly // Other core is now stalled, can access DPORT registers directly
@@ -130,14 +130,14 @@ void IRAM_ATTR esp_restart_noos(void)
// Reset CPUs // Reset CPUs
if (core_id == 0) { if (core_id == 0) {
// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
esp_cpu_reset(1); esp_rom_software_reset_cpu(1);
esp_cpu_reset(0); esp_rom_software_reset_cpu(0);
} else { } else {
// Running on APP CPU: need to reset PRO CPU and unstall it, // Running on APP CPU: need to reset PRO CPU and unstall it,
// then reset APP CPU // then reset APP CPU
esp_cpu_reset(0); esp_rom_software_reset_cpu(0);
esp_cpu_unstall(0); esp_cpu_unstall(0);
esp_cpu_reset(1); esp_rom_software_reset_cpu(1);
} }
while(true) { while(true) {
; ;

25
components/esp_system/port/soc/esp32c2/system_internal.c
View File

@@ -46,17 +46,6 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true); wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx);
// Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter
// to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = esp_cpu_get_core_id();
#if !CONFIG_FREERTOS_UNICORE
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_cpu_reset(other_core_id);
esp_cpu_stall(other_core_id);
#endif
// Disable TG0/TG1 watchdogs // Disable TG0/TG1 watchdogs
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
wdt_hal_write_protect_disable(&wdt0_context); wdt_hal_write_protect_disable(&wdt0_context);
@@ -95,19 +84,9 @@ void IRAM_ATTR esp_restart_noos(void)
rtc_clk_cpu_set_to_default_config(); rtc_clk_cpu_set_to_default_config();
#endif #endif
#if !CONFIG_FREERTOS_UNICORE // Reset CPU
// Clear entry point for APP CPU esp_rom_software_reset_cpu(0);
REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
#endif
// Reset CPUs
if (core_id == 0) {
// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
#if !CONFIG_FREERTOS_UNICORE
esp_cpu_reset(1);
#endif
esp_cpu_reset(0);
}
while (true) { while (true) {
; ;
} }

35
components/esp_system/port/soc/esp32c3/system_internal.c
View File

@@ -47,17 +47,6 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true); wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx);
// Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter
// to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = esp_cpu_get_core_id();
#if !CONFIG_FREERTOS_UNICORE
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_cpu_reset(other_core_id);
esp_cpu_stall(other_core_id);
#endif
// Disable TG0/TG1 watchdogs // Disable TG0/TG1 watchdogs
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
wdt_hal_write_protect_disable(&wdt0_context); wdt_hal_write_protect_disable(&wdt0_context);
@@ -109,28 +98,8 @@ void IRAM_ATTR esp_restart_noos(void)
rtc_clk_cpu_set_to_default_config(); rtc_clk_cpu_set_to_default_config();
#endif #endif
#if !CONFIG_FREERTOS_UNICORE // Reset CPU
// Clear entry point for APP CPU esp_rom_software_reset_cpu(0);
REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
#endif
// Reset CPUs
if (core_id == 0) {
// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
#if !CONFIG_FREERTOS_UNICORE
esp_cpu_reset(1);
#endif
esp_cpu_reset(0);
}
#if !CONFIG_FREERTOS_UNICORE
else {
// Running on APP CPU: need to reset PRO CPU and unstall it,
// then reset APP CPU
esp_cpu_reset(0);
esp_cpu_unstall(0);
esp_cpu_reset(1);
}
#endif
while (true) { while (true) {
; ;
} }

34
components/esp_system/port/soc/esp32h2/system_internal.c
View File

@@ -48,17 +48,6 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true); wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx);
// Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter
// to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = esp_cpu_get_core_id();
#if !CONFIG_FREERTOS_UNICORE
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_rom_software_reset_cpu(other_core_id);
esp_cpu_stall(other_core_id);
#endif
// Disable TG0/TG1 watchdogs // Disable TG0/TG1 watchdogs
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
wdt_hal_write_protect_disable(&wdt0_context); wdt_hal_write_protect_disable(&wdt0_context);
@@ -108,28 +97,9 @@ void IRAM_ATTR esp_restart_noos(void)
rtc_clk_cpu_set_to_default_config(); rtc_clk_cpu_set_to_default_config();
#endif #endif
#if !CONFIG_FREERTOS_UNICORE // Reset CPU
// Clear entry point for APP CPU esp_rom_software_reset_cpu(0);
REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
#endif
// Reset CPUs
if (core_id == 0) {
// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
#if !CONFIG_FREERTOS_UNICORE
esp_rom_software_reset_cpu(1);
#endif
esp_rom_software_reset_cpu(0);
}
#if !CONFIG_FREERTOS_UNICORE
else {
// Running on APP CPU: need to reset PRO CPU and unstall it,
// then reset APP CPU
esp_rom_software_reset_cpu(0);
esp_cpu_unstall(0);
esp_rom_software_reset_cpu(1);
}
#endif
while (true) { while (true) {
; ;
} }

35
components/esp_system/port/soc/esp32h4/system_internal.c
View File

@@ -46,17 +46,6 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true); wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx);
// Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter
// to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = esp_cpu_get_core_id();
#if !CONFIG_FREERTOS_UNICORE
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_cpu_reset(other_core_id);
esp_cpu_stall(other_core_id);
#endif
// Disable TG0/TG1 watchdogs // Disable TG0/TG1 watchdogs
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
wdt_hal_write_protect_disable(&wdt0_context); wdt_hal_write_protect_disable(&wdt0_context);
@@ -104,28 +93,8 @@ void IRAM_ATTR esp_restart_noos(void)
rtc_clk_cpu_set_to_default_config(); rtc_clk_cpu_set_to_default_config();
#endif #endif
#if !CONFIG_FREERTOS_UNICORE // Reset CPU
// Clear entry point for APP CPU esp_rom_software_reset_cpu(0);
REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
#endif
// Reset CPUs
if (core_id == 0) {
// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
#if !CONFIG_FREERTOS_UNICORE
esp_cpu_reset(1);
#endif
esp_cpu_reset(0);
}
#if !CONFIG_FREERTOS_UNICORE
else {
// Running on APP CPU: need to reset PRO CPU and unstall it,
// then reset APP CPU
esp_cpu_reset(0);
esp_cpu_unstall(0);
esp_cpu_reset(1);
}
#endif
while (true) { while (true) {
; ;
} }

10
components/esp_system/port/soc/esp32s2/system_internal.c
View File

@@ -51,12 +51,6 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true); wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
wdt_hal_write_protect_enable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx);
// Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter
// to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = esp_cpu_get_core_id();
//Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context //Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
// Disable TG0/TG1 watchdogs // Disable TG0/TG1 watchdogs
wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
@@ -118,9 +112,7 @@ void IRAM_ATTR esp_restart_noos(void)
rtc_clk_cpu_set_to_default_config(); rtc_clk_cpu_set_to_default_config();
// Reset CPUs // Reset CPUs
if (core_id == 0) { esp_rom_software_reset_cpu(0);
esp_cpu_reset(0);
}
while (true) { while (true) {
; ;
} }

10
components/esp_system/port/soc/esp32s3/system_internal.c
View File

@@ -88,7 +88,7 @@ void IRAM_ATTR esp_restart_noos(void)
const uint32_t core_id = esp_cpu_get_core_id(); const uint32_t core_id = esp_cpu_get_core_id();
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
const uint32_t other_core_id = (core_id == 0) ? 1 : 0; const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_cpu_reset(other_core_id); esp_rom_software_reset_cpu(other_core_id);
esp_cpu_stall(other_core_id); esp_cpu_stall(other_core_id);
#endif #endif
@@ -135,17 +135,17 @@ void IRAM_ATTR esp_restart_noos(void)
if (core_id == 0) { if (core_id == 0) {
// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
esp_cpu_reset(1); esp_rom_software_reset_cpu(1);
#endif #endif
esp_cpu_reset(0); esp_rom_software_reset_cpu(0);
} }
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
else { else {
// Running on APP CPU: need to reset PRO CPU and unstall it, // Running on APP CPU: need to reset PRO CPU and unstall it,
// then reset APP CPU // then reset APP CPU
esp_cpu_reset(0); esp_rom_software_reset_cpu(0);
esp_cpu_unstall(0); esp_cpu_unstall(0);
esp_cpu_reset(1); esp_rom_software_reset_cpu(1);
} }
#endif #endif
while (true) { while (true) {