diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
index 544fcd1ad4..c26c83381e 100644
--- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
+++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
@@ -91,13 +91,16 @@ static inline void bootloader_hardware_init(void)
 {
     // regi2c is enabled by default on ESP32P4, do nothing
 
-    // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
-    // And we are fixing SPLL to be 480MHz at all runtime
-    // Suppose to fix the issue on ECO1, will check when chip comes back
-    // TODO: IDF-8939
-    REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
-    REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
-    esp_rom_delay_us(100);
+    unsigned chip_version = efuse_hal_chip_revision();
+    if (chip_version == 0) {
+        // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
+        // And we are fixing SPLL to be 480MHz at all runtime
+        // Suppose to fix the issue on ECO1, will check when chip comes back
+        // TODO: IDF-8939
+        REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
+        REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
+        esp_rom_delay_us(100);
+    }
     REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10);
     REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);
 }
diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
index 919197fb48..391d80597d 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
@@ -27,6 +27,7 @@
 #include "pmu_param.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_uart.h"
+#include "hal/efuse_hal.h"
 
 #define HP(state)   (PMU_MODE_HP_ ## state)
 #define LP(state)   (PMU_MODE_LP_ ## state)
@@ -317,8 +318,11 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(void)
     }
     pmu_sleep_shutdown_ldo();
 
-    REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
-    REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
+    unsigned chip_version = efuse_hal_chip_revision();
+    if (chip_version == 0) {
+        REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
+        REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
+    }
     return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
 }
 
diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h
index f504917fe7..0e65f9e6b6 100644
--- a/components/hal/esp32p4/include/hal/clk_tree_ll.h
+++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h
@@ -22,6 +22,7 @@
 #include "hal/log.h"
 #include "esp32p4/rom/rtc.h"
 #include "hal/misc.h"
+#include "hal/efuse_hal.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -309,7 +310,13 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(u
 {
     uint8_t div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0);
     uint8_t ref_div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_REF_DIV);
-    return xtal_freq_mhz * (div + 4) / (ref_div + 1);
+#if !ESP_CHIP_REV_ABOVE(ESP_HAL_CHIP_REV_MIN, 1)
+    unsigned chip_version = efuse_hal_chip_revision();
+    if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
+        return xtal_freq_mhz * (div + 4) / (ref_div + 1);
+    } else
+#endif
+    return xtal_freq_mhz * div / (ref_div + 1);
 }
 
 /**
@@ -336,22 +343,41 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_
     uint8_t dchgp = 5;
     uint8_t dcur = 3;
     uint8_t oc_enb_fcal = 0;
+    unsigned chip_version = efuse_hal_chip_revision();
 
     // Currently, only supporting 40MHz XTAL
     HAL_ASSERT(xtal_freq_mhz == SOC_XTAL_FREQ_40M);
-    switch (cpll_freq_mhz) {
-    case CLK_LL_PLL_400M_FREQ_MHZ:
-        /* Configure 400M CPLL */
-        div7_0 = 6;
-        div_ref = 0;
-        break;
-    case CLK_LL_PLL_360M_FREQ_MHZ:
-    default:
-        /* Configure 360M CPLL */
-        div7_0 = 5;
-        div_ref = 0;
-        break;
+    if (chip_version == 0) {
+        switch (cpll_freq_mhz) {
+        case CLK_LL_PLL_400M_FREQ_MHZ:
+            /* Configure 400M CPLL */
+            div7_0 = 6;
+            div_ref = 0;
+            break;
+        case CLK_LL_PLL_360M_FREQ_MHZ:
+        default:
+            /* Configure 360M CPLL */
+            div7_0 = 5;
+            div_ref = 0;
+            break;
+        }
+    } else {
+        /*div7_0 bit2 & bit3 will swap from ECO1*/
+        switch (cpll_freq_mhz) {
+        case CLK_LL_PLL_400M_FREQ_MHZ:
+            /* Configure 400M CPLL */
+            div7_0 = 10;
+            div_ref = 0;
+            break;
+        case CLK_LL_PLL_360M_FREQ_MHZ:
+        default:
+            /* Configure 360M CPLL */
+            div7_0 = 9;
+            div_ref = 0;
+            break;
+        }
     }
+
     uint8_t i2c_cpll_lref  = (oc_enb_fcal << I2C_CPLL_OC_ENB_FCAL_LSB) | (dchgp << I2C_CPLL_OC_DCHGP_LSB) | (div_ref);
     uint8_t i2c_cpll_div_7_0 = div7_0;
     uint8_t i2c_cpll_dcur = (1 << I2C_CPLL_OC_DLREF_SEL_LSB ) | (3 << I2C_CPLL_OC_DHREF_SEL_LSB) | dcur;