Merge branch 'feat/support_flash_h21' into 'master'

feat(spi_flash): Add basic flash support for esp32h21, esp32h4

Closes IDF-12388 and IDF-11609

See merge request espressif/esp-idf!40643

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c

@@ -125,16 +125,10 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)
     const char *str;
     switch (bootloader_hdr->spi_speed) {
     case ESP_IMAGE_SPI_SPEED_DIV_2:
-        str = "32MHz";
+        str = "24MHz";
-        break;
-    case ESP_IMAGE_SPI_SPEED_DIV_3:
-        str = "21.3MHz";
-        break;
-    case ESP_IMAGE_SPI_SPEED_DIV_4:
-        str = "16MHz";
         break;
     case ESP_IMAGE_SPI_SPEED_DIV_1:
-        str = "64MHz";
+        str = "48MHz";
         break;
     default:
         str = "16MHz";

components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c

@@ -25,6 +25,7 @@
 #include "hal/mmu_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
+#include "hal/mspi_ll.h"
 
 static const char *TAG = "boot.esp32h4";
 
@@ -84,6 +85,16 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
     esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
 }
 
+static void IRAM_ATTR bootloader_mspi_clock_init(void)
+{
+    // // To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK
+    // // (FPGA image fixed MSPI0/1 clock to 64MHz)
+    // clk_ll_xtal_x2_enable();
+    // _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
+    // IDF-13632
+    _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F48M);
+}
+
 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
 {
     uint32_t size;
@@ -121,16 +132,16 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)
     const char *str;
     switch (bootloader_hdr->spi_speed) {
     case ESP_IMAGE_SPI_SPEED_DIV_2:
-        str = "32MHz";
+        str = "24MHz";
         break;
     case ESP_IMAGE_SPI_SPEED_DIV_4:
-        str = "16MHz";
+        str = "12MHz";
         break;
     case ESP_IMAGE_SPI_SPEED_DIV_1:
-        str = "64MHz";
+        str = "48MHz";
         break;
     default:
-        str = "16MHz";
+        str = "12MHz";
         break;
     }
     ESP_EARLY_LOGI(TAG, "SPI Speed      : %s", str);
@@ -185,6 +196,7 @@ static void print_flash_info(const esp_image_header_t *bootloader_hdr)
 
 static void IRAM_ATTR bootloader_init_flash_configure(void)
 {
+    bootloader_mspi_clock_init();
     bootloader_configure_spi_pins(1);
     bootloader_flash_cs_timing_config();
 }
@@ -267,6 +279,7 @@ void bootloader_flash_hardware_init(void)
     bootloader_configure_spi_pins(1);
     bootloader_flash_set_spi_mode(&hdr);
     bootloader_flash_clock_config(&hdr);
+    bootloader_mspi_clock_init();
     bootloader_flash_cs_timing_config();
 
     bootloader_spi_flash_resume();

components/hal/esp32h21/include/hal/cache_ll.h

@@ -128,6 +128,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Invalidate all
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ */
+__attribute__((always_inline))
+static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
+{
+    Cache_Invalidate_ICache_All();
+}
+
 /**
  * @brief Freeze Cache
  *

components/hal/esp32h21/include/hal/spimem_flash_ll.h

@@ -603,14 +603,12 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_
  */
 static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
 {
-    // dev->ctrl2.cs_hold_time = hold_n - 1;
+    // not supported on esp32h21
-    // dev->user.cs_hold = (hold_n > 0? 1: 0);
 }
 
 static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
 {
-    // dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
+    // not supported on esp32h21
-    // dev->ctrl2.cs_setup_time = cs_setup_time - 1;
 }
 
 /**
@@ -626,7 +624,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
     uint8_t clock_val = 0;
     switch (PCR.mspi_conf.mspi_clk_sel) {
     case 0:
-        clock_val = 32;
+        clock_val = 48;
         break;
     case 1:
         clock_val = 8;
@@ -635,7 +633,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
         clock_val = 64;
         break;
     case 3:
-        clock_val = 32;
+        clock_val = 48;
         break;
     default:
         HAL_ASSERT(false);
@@ -727,6 +725,79 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_
     dev->user2.val = user2_reg;
 }
 
+
+#define SPIMEM_FLASH_LL_SUSPEND_END_INTR  SPI_MEM_PES_END_INT_ENA_M
+#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE  ETS_MSPI_INTR_SOURCE
+
+/**
+ * @brief Get the address of the interrupt status register.
+ *
+ * This function returns a pointer to the interrupt status register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @return volatile void* Pointer to the interrupt status register.
+ */
+static inline volatile void *spimem_flash_ll_get_interrupt_status_reg(spi_mem_dev_t *dev)
+{
+    return &dev->int_st;
+}
+
+/**
+ * @brief Clear specific interrupt status bits.
+ *
+ * This function clears the specified interrupt bits in the interrupt clear register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @param[in] mask Bitmask specifying which interrupt bits to clear.
+ */
+__attribute__((always_inline))
+static inline void spimem_flash_ll_clear_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
+{
+    dev->int_clr.val = mask;
+}
+
+/**
+ * @brief Enable specific interrupt bits.
+ *
+ * This function enables the specified interrupts in the interrupt enable register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @param[in] mask Bitmask specifying which interrupt bits to enable.
+ */
+__attribute__((always_inline))
+static inline void spimem_flash_ll_enable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
+{
+    dev->int_ena.val |= mask;
+}
+
+/**
+ * @brief Disable specific interrupt bits.
+ *
+ * This function disables the specified interrupts in the interrupt enable register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @param[in] mask Bitmask specifying which interrupt bits to disable.
+ */
+__attribute__((always_inline))
+static inline void spimem_flash_ll_disable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
+{
+    dev->int_ena.val &= (~mask);
+}
+
+/**
+ * @brief Get the current interrupt status.
+ *
+ * This function retrieves the current interrupt status from the interrupt status register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @param[out] intr_status Pointer to a variable where the interrupt status will be stored.
+ */
+__attribute__((always_inline))
+static inline void spimem_flash_ll_get_intr_mask(spi_mem_dev_t *dev, uint32_t *intr_status)
+{
+    *intr_status = dev->int_st.val;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h4/include/hal/mspi_ll.h

@@ -46,7 +46,23 @@ __attribute__((always_inline))
 static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_periph_flash_clk_src_t clk_src)
 {
     HAL_ASSERT(mspi_id == 0);
-    // TODO [ESP32H4]
+    switch (clk_src) {
+    case FLASH_CLK_SRC_XTAL:
+        PCR.mspi_clk_conf.mspi_func_clk_sel = 0;
+        break;
+    case FLASH_CLK_SRC_RC_FAST:
+        PCR.mspi_clk_conf.mspi_func_clk_sel = 1;
+        break;
+    // case FLASH_CLK_SRC_PLL_F64M:
+    //     PCR.mspi_clk_conf.mspi_func_clk_sel = 2;
+    //     break;
+    // TODO: [ESP32H4] IDF-13632, support 64M
+    case FLASH_CLK_SRC_PLL_F48M:
+        PCR.mspi_clk_conf.mspi_func_clk_sel = 3;
+        break;
+    default:
+        HAL_ASSERT(false);
+    }
 }
 
 #ifdef __cplusplus

components/hal/esp32h4/include/hal/spimem_flash_ll.h

@@ -28,8 +28,6 @@
 #include "soc/pcr_struct.h"
 #include "esp_rom_sys.h"
 
-//TODO: [ESP32H4] IDF-12388 inherited from verification branch, need check
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -522,11 +520,8 @@ static inline void spimem_flash_ll_set_mosi_bitlen(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_command(spi_mem_dev_t *dev, uint32_t command, uint32_t bitlen)
 {
     dev->user.usr_command = 1;
-    typeof(dev->user2) user2 = {
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user2, usr_command_value, command);
-        .usr_command_value = command,
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user2, usr_command_bitlen, (bitlen - 1));
-        .usr_command_bitlen = (bitlen - 1),
-    };
-    dev->user2.val = user2.val;
 }
 
 /**
@@ -561,7 +556,7 @@ static inline void spimem_flash_ll_set_addr_bitlen(spi_mem_dev_t *dev, uint32_t
 static inline void spimem_flash_ll_set_extra_address(spi_mem_dev_t *dev, uint32_t extra_addr)
 {
     dev->cache_fctrl.usr_addr_4byte = 0;
-    dev->rd_status.wb_mode = extra_addr;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rd_status, wb_mode, extra_addr);
 }
 
 /**
@@ -607,12 +602,12 @@ static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_
  */
 static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
 {
-    //TODO: [ESP32H4] IDF-12388
+    //not supported on esp32h4
 }
 
 static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
 {
-    //TODO: [ESP32H4] IDF-12388
+    //not supported on esp32h4
 }
 
 /**
@@ -625,7 +620,24 @@ static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_
  */
 static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
 {
-    return 64;
+    uint8_t clock_val = 0;
+    switch (PCR.mspi_clk_conf.mspi_func_clk_sel) {
+    case 0:
+        clock_val = 48;
+        break;
+    case 1:
+        clock_val = 8;
+        break;
+    case 2:
+        clock_val = 64;
+        break;
+    case 3:
+        clock_val = 48;
+        break;
+    default:
+        HAL_ASSERT(false);
+    }
+    return clock_val;
 }
 
 /**
@@ -712,6 +724,79 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_
     dev->user2.val = user2_reg;
 }
 
+
+#define SPIMEM_FLASH_LL_SUSPEND_END_INTR  SPI_MEM_PES_END_INT_ENA_M
+#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE  ETS_MSPI_INTR_SOURCE
+
+/**
+ * @brief Get the address of the interrupt status register.
+ *
+ * This function returns a pointer to the interrupt status register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @return volatile void* Pointer to the interrupt status register.
+ */
+static inline volatile void *spimem_flash_ll_get_interrupt_status_reg(spi_mem_dev_t *dev)
+{
+    return &dev->int_st;
+}
+
+/**
+ * @brief Clear specific interrupt status bits.
+ *
+ * This function clears the specified interrupt bits in the interrupt clear register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @param[in] mask Bitmask specifying which interrupt bits to clear.
+ */
+__attribute__((always_inline))
+static inline void spimem_flash_ll_clear_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
+{
+    dev->int_clr.val = mask;
+}
+
+/**
+ * @brief Enable specific interrupt bits.
+ *
+ * This function enables the specified interrupts in the interrupt enable register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @param[in] mask Bitmask specifying which interrupt bits to enable.
+ */
+__attribute__((always_inline))
+static inline void spimem_flash_ll_enable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
+{
+    dev->int_ena.val |= mask;
+}
+
+/**
+ * @brief Disable specific interrupt bits.
+ *
+ * This function disables the specified interrupts in the interrupt enable register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @param[in] mask Bitmask specifying which interrupt bits to disable.
+ */
+__attribute__((always_inline))
+static inline void spimem_flash_ll_disable_intr_mask(spi_mem_dev_t *dev, uint32_t mask)
+{
+    dev->int_ena.val &= (~mask);
+}
+
+/**
+ * @brief Get the current interrupt status.
+ *
+ * This function retrieves the current interrupt status from the interrupt status register of the SPI memory device.
+ *
+ * @param[in] dev Pointer to the SPI memory device structure.
+ * @param[out] intr_status Pointer to a variable where the interrupt status will be stored.
+ */
+__attribute__((always_inline))
+static inline void spimem_flash_ll_get_intr_mask(spi_mem_dev_t *dev, uint32_t *intr_status)
+{
+    *intr_status = dev->int_st.val;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h21/include/soc/Kconfig.soc_caps.in

@@ -567,6 +567,10 @@ config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
     bool
     default y
 
+config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
+    bool
+    default y
+
 config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
     bool
     default y
@@ -587,18 +591,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP
     bool
     default y
 
-config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED
-    bool
-    default y
-
-config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED
-    bool
-    default y
-
-config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED
-    bool
-    default y
-
 config SOC_SYSTIMER_COUNTER_NUM
     int
     default 2

components/soc/esp32h21/include/soc/soc_caps.h

@@ -415,17 +415,13 @@
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
-// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1) //TODO: [ESP32H21] IDF-11526
+#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)
 #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME                   (1)
 #define SOC_SPI_MEM_SUPPORT_IDLE_INTR                     (1)
 #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND                    (1)
 #define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
 #define SOC_SPI_MEM_SUPPORT_WRAP                          (1)
 
-#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED         1
-#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED         1
-#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED         1
-
 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
 #define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
 #define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -335,6 +335,10 @@ config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
     bool
     default y
 
+config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
+    bool
+    default y
+
 config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
     bool
     default y
@@ -355,18 +359,6 @@ config SOC_SPI_MEM_SUPPORT_WRAP
     bool
     default y
 
-config SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED
-    bool
-    default y
-
-config SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED
-    bool
-    default y
-
-config SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED
-    bool
-    default y
-
 config SOC_SYSTIMER_COUNTER_NUM
     int
     default 2

components/soc/esp32h4/include/soc/clk_tree_defs.h

@@ -257,7 +257,7 @@ typedef enum {
     FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
     FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
     // FLASH_CLK_SRC_REF_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
-    FLASH_CLK_SRC_REF_F48M = SOC_MOD_CLK_PLL_F48M,   /*!< Select PLL_F48M as the source clock */
+    FLASH_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M,   /*!< Select PLL_F48M as the source clock */
     FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,        /*!< Select XTAL as the default clock choice */
     FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as ROM default clock source */
 } soc_periph_flash_clk_src_t;

components/soc/esp32h4/include/soc/soc_caps.h

@@ -407,17 +407,13 @@
 
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
-// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1) // TODO: [ESP32H4] IDF-12290
+#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)
 #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME                   (1)
 #define SOC_SPI_MEM_SUPPORT_IDLE_INTR                     (1)
 #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND                    (1)
 #define SOC_SPI_MEM_SUPPORT_CHECK_SUS                     (1)
 #define SOC_SPI_MEM_SUPPORT_WRAP                          (1)
 
-#define SOC_MEMSPI_SRC_FREQ_64M_SUPPORTED         1
-#define SOC_MEMSPI_SRC_FREQ_32M_SUPPORTED         1
-#define SOC_MEMSPI_SRC_FREQ_16M_SUPPORTED         1
-
 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
 #define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
 #define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units

components/spi_flash/esp32h21/Kconfig.flash_freq

@@ -1,10 +1,8 @@
 choice ESPTOOLPY_FLASHFREQ
     prompt "Flash SPI speed"
-    default ESPTOOLPY_FLASHFREQ_32M
+    default ESPTOOLPY_FLASHFREQ_48M
-    config ESPTOOLPY_FLASHFREQ_64M
+    config ESPTOOLPY_FLASHFREQ_48M
-        bool "64 MHz"
+        bool "48 MHz"
-    config ESPTOOLPY_FLASHFREQ_32M
+    config ESPTOOLPY_FLASHFREQ_24M
-        bool "32 MHz"
+        bool "24 MHz"
-    config ESPTOOLPY_FLASHFREQ_16M
-        bool "16 MHz"
 endchoice

components/spi_flash/esp32h4/Kconfig.flash_freq

@@ -1,10 +1,8 @@
 choice ESPTOOLPY_FLASHFREQ
     prompt "Flash SPI speed"
-    default ESPTOOLPY_FLASHFREQ_32M
+    default ESPTOOLPY_FLASHFREQ_48M
-    config ESPTOOLPY_FLASHFREQ_64M
+    config ESPTOOLPY_FLASHFREQ_48M
-        bool "64 MHz"
+        bool "48 MHz"
-    config ESPTOOLPY_FLASHFREQ_32M
+    config ESPTOOLPY_FLASHFREQ_24M
-        bool "32 MHz"
+        bool "24 MHz"
-    config ESPTOOLPY_FLASHFREQ_16M
-        bool "16 MHz"
 endchoice

components/spi_flash/spi_flash_chip_gd.c

@@ -73,6 +73,7 @@ esp_err_t spi_flash_chip_gd_detect_size(esp_flash_t *chip, uint32_t *size)
 #define FLASH_SIZE_MASK     0xFF
 #define GD25Q_PRODUCT_ID    0x4000
 #define GD25LQ_PRODUCT_ID   0x6000
+#define GD25UF_PRODUCT_ID   0x8300
 
 #define WRSR_16B_REQUIRED(chip_id) (((chip_id) & FLASH_ID_MASK) == GD25LQ_PRODUCT_ID || \
                                     ((chip_id) & FLASH_SIZE_MASK) <= 0x15)
@@ -88,7 +89,7 @@ esp_err_t spi_flash_chip_gd_probe(esp_flash_t *chip, uint32_t flash_id)
     }
 
     uint32_t product_id = flash_id & FLASH_ID_MASK;
-    if (product_id != GD25Q_PRODUCT_ID && product_id != GD25LQ_PRODUCT_ID) {
+    if (product_id != GD25Q_PRODUCT_ID && product_id != GD25LQ_PRODUCT_ID && product_id != GD25UF_PRODUCT_ID) {
         return ESP_ERR_NOT_FOUND;
     }
 

components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h

@@ -88,7 +88,7 @@
 #define HSPI_PIN_NUM_WP     FSPI_PIN_NUM_WP
 #define HSPI_PIN_NUM_CS     FSPI_PIN_NUM_CS
 
-#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21
+#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
 
 #define FSPI_PIN_NUM_MOSI   5
 #define FSPI_PIN_NUM_MISO   0

components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c

@@ -597,7 +597,9 @@ TEST_CASE_MULTI_FLASH_IGNORE("Test esp_flash_write can toggle QE bit", test_togg
 
 // This table could be chip specific in the future.
 #if CONFIG_IDF_TARGET_ESP32C2
-uint8_t flash_frequency_table[5] = {5, 10, 20, 40};
+uint8_t flash_frequency_table[4] = {5, 10, 20, 40};
+#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
+uint8_t flash_frequency_table[4] = {6, 12, 24, 48};
 #else
 uint8_t flash_frequency_table[6] = {5, 10, 20, 26, 40, 80};
 #endif

components/spi_flash/test_apps/flash_suspend/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

components/spi_flash/test_apps/flash_suspend/main/test_flash_suspend.c

@@ -23,6 +23,7 @@
 #include "esp_flash.h"
 #include "hal/gpio_hal.h"
 #include "rom/cache.h"
+#include "hal/cache_ll.h"
 
 #include "test_utils.h"
 
@@ -77,6 +78,8 @@ static bool IRAM_ATTR gptimer_alarm_suspend_cb(gptimer_handle_t timer, const gpt
 #endif
 #if CONFIG_IDF_TARGET_ESP32P4
     Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
+#elif CONFIG_IDF_TARGET_ESP32H4
+    cache_ll_invalidate_all(CACHE_LL_LEVEL_ALL, CACHE_TYPE_ALL, CACHE_LL_ID_ALL);
 #elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
     Cache_Invalidate_All();
 #else