From f2b0f256ab278e3fdf4220a6b5309b10672ae13d Mon Sep 17 00:00:00 2001 From: Laukik Hase Date: Tue, 15 Jul 2025 13:53:05 +0530 Subject: [PATCH] fix(esp_rom): Patch the `esp_rom_delay_us` API to use U-mode cycle CSR --- components/esp_rom/CMakeLists.txt | 6 +++ .../esp_rom/esp32c5/Kconfig.soc_caps.in | 4 ++ components/esp_rom/esp32c5/esp_rom_caps.h | 1 + .../esp32c5/include/esp32c5/rom/ets_sys.h | 6 +-- components/esp_rom/esp32c5/ld/esp32c5.rom.ld | 2 +- .../esp_rom/esp32c61/Kconfig.soc_caps.in | 4 ++ components/esp_rom/esp32c61/esp_rom_caps.h | 1 + .../esp32c61/include/esp32c61/rom/ets_sys.h | 6 +-- .../esp_rom/esp32c61/ld/esp32c61.rom.ld | 2 +- components/esp_rom/patches/esp_rom_sys.c | 45 +++++++++++++++++++ components/riscv/include/riscv/rv_utils.h | 2 +- 11 files changed, 70 insertions(+), 9 deletions(-) diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 2e02d5c5b5..c1fb9041d9 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -388,6 +388,12 @@ else() # Regular app build endif() endif() + if(CONFIG_ESP_ROM_DELAY_US_PATCH AND + (CONFIG_ESP32C5_REV_MIN_FULL LESS_EQUAL 100 OR CONFIG_ESP32C61_REV_MIN_FULL LESS_EQUAL 100)) + # Force the linker to include esp_rom_sys.c for ets_ops_set_rom_patches constructor + target_link_libraries(${COMPONENT_LIB} PRIVATE "-u ets_ops_set_rom_patches") + endif() + if(CONFIG_IDF_TARGET_ARCH_XTENSA) target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=longjmp") endif() diff --git a/components/esp_rom/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/Kconfig.soc_caps.in index 87e02d1eef..0092c8f37e 100644 --- a/components/esp_rom/esp32c5/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c5/Kconfig.soc_caps.in @@ -118,3 +118,7 @@ config ESP_ROM_CLIC_INT_THRESH_PATCH config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY bool default y + +config ESP_ROM_DELAY_US_PATCH + bool + default y diff --git a/components/esp_rom/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/esp_rom_caps.h index fb876b5512..2d0fd6829e 100644 --- a/components/esp_rom/esp32c5/esp_rom_caps.h +++ b/components/esp_rom/esp32c5/esp_rom_caps.h @@ -35,3 +35,4 @@ #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) #define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. +#define ESP_ROM_DELAY_US_PATCH (1) // ROM ets_delay_us needs patch for U-mode operation diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/ets_sys.h b/components/esp_rom/esp32c5/include/esp32c5/rom/ets_sys.h index f596e45f97..35b2bcc075 100644 --- a/components/esp_rom/esp32c5/include/esp32c5/rom/ets_sys.h +++ b/components/esp_rom/esp32c5/include/esp32c5/rom/ets_sys.h @@ -64,9 +64,9 @@ struct ETSEventTag { typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processor*/ typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ - - - +typedef struct ets_ops { + void (*ets_delay_us)(uint32_t us); +} ets_ops; /** * @} diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.ld index b3df4e6e38..7abce52964 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.ld +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.ld @@ -27,7 +27,7 @@ ets_install_putc2 = 0x4000002c; ets_install_uart_printf = 0x40000030; ets_install_usb_printf = 0x40000034; ets_get_printf_channel = 0x40000038; -ets_delay_us = 0x4000003c; +PROVIDE ( ets_delay_us = 0x4000003c ); ets_get_cpu_frequency = 0x40000040; ets_update_cpu_frequency = 0x40000044; ets_install_lock = 0x40000048; diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index 62368fb55c..de114450fa 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -114,3 +114,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY bool default y + +config ESP_ROM_DELAY_US_PATCH + bool + default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index 4dd9d35a86..88c28b664d 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -34,3 +34,4 @@ #define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. +#define ESP_ROM_DELAY_US_PATCH (1) // ROM ets_delay_us needs patch for U-mode operation diff --git a/components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h b/components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h index bab7236c16..e65942925c 100644 --- a/components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h +++ b/components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h @@ -64,9 +64,9 @@ struct ETSEventTag { typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processor*/ typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/ - - - +typedef struct ets_ops { + void (*ets_delay_us)(uint32_t us); +} ets_ops; /** * @} diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld index 390992ee54..d68ff6d40b 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld @@ -23,7 +23,7 @@ ets_install_putc2 = 0x4000002c; ets_install_uart_printf = 0x40000030; ets_install_usb_printf = 0x40000034; ets_get_printf_channel = 0x40000038; -ets_delay_us = 0x4000003c; +PROVIDE ( ets_delay_us = 0x4000003c ); ets_get_cpu_frequency = 0x40000040; ets_update_cpu_frequency = 0x40000044; ets_install_lock = 0x40000048; diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c index 6ff8c8079b..8c5c897d05 100644 --- a/components/esp_rom/patches/esp_rom_sys.c +++ b/components/esp_rom/patches/esp_rom_sys.c @@ -7,10 +7,12 @@ #include #include #include +#include #include "soc/soc_caps.h" #include "esp_rom_caps.h" #include "esp_rom_serial_output.h" #include "rom/ets_sys.h" +#include "esp_rom_sys.h" #include "sdkconfig.h" #if !ESP_ROM_HAS_OUTPUT_PUTC_FUNC @@ -114,3 +116,46 @@ uint32_t esp_rom_get_bootloader_offset(void) return offset_of_active_bootloader; } #endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED + +#if ESP_ROM_DELAY_US_PATCH && !NON_OS_BUILD +#if CONFIG_ESP32C5_REV_MIN_FULL <= 100 || CONFIG_ESP32C61_REV_MIN_FULL <= 100 + +#include "riscv/rv_utils.h" + +extern const ets_ops *ets_ops_table_ptr; + +struct ets_ops ets_ops_patch_table_ptr; + +/* + * NOTE: Workaround for ROM delay API in ESP32-C5 (<=ECO2) and ESP32-C61 (<=ECO3): + * + * The ROM implementation of `ets_delay_us` uses the `mcycle` CSR to get CPU cycle count. + * This CSR is accessible only in M-mode and when the ROM API is called from U-mode, + * accessing `mcycle` causes an illegal instruction fault. + * + * This issue has been fixed in later ECO revisions of both SoCs. + */ +void ets_delay_us(uint32_t us) +{ + uint32_t start = rv_utils_get_cycle_count(); + uint32_t end = us * esp_rom_get_cpu_ticks_per_us(); + + while ((rv_utils_get_cycle_count() - start) < end) { + /* busy-wait loop for delay */ + } +} + +void __attribute__((constructor)) ets_ops_set_rom_patches(void) +{ + /* Copy ROM default function table into our patch table */ + memcpy(&ets_ops_patch_table_ptr, ets_ops_table_ptr, sizeof(struct ets_ops)); + + /* Replace the ROM's delay function with the patched version */ + ets_ops_patch_table_ptr.ets_delay_us = ets_delay_us; + + /* Redirect ROM calls to use the patched function table */ + ets_ops_table_ptr = &ets_ops_patch_table_ptr; +} + +#endif // CONFIG_ESP32C5_REV_MIN_100 || CONFIG_ESP32C61_REV_MIN_100 +#endif // ESP_ROM_DELAY_US_PATCH && CONFIG_SECURE_ENABLE_TEE && !NON_OS_BUILD diff --git a/components/riscv/include/riscv/rv_utils.h b/components/riscv/include/riscv/rv_utils.h index 1970017e8a..dca85fa17b 100644 --- a/components/riscv/include/riscv/rv_utils.h +++ b/components/riscv/include/riscv/rv_utils.h @@ -104,7 +104,7 @@ FORCE_INLINE_ATTR void *rv_utils_get_sp(void) FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_get_cycle_count(void) { #if !SOC_CPU_HAS_CSR_PC - return RV_READ_CSR(mcycle); + return RV_READ_CSR(cycle); #else if (IS_PRV_M_MODE()) { return RV_READ_CSR(CSR_PCCR_MACHINE);