From f2e92f564e2ba1d792d8dc6e8824154fa1118d40 Mon Sep 17 00:00:00 2001 From: jingli Date: Tue, 29 Nov 2022 14:28:20 +0800 Subject: [PATCH] bt: fix bt sleep flow hangs in btdm_sleep_clock_sync Bluetooth low power related logic and regs have separate power domain from MAC and BB, and do not power down during light sleep. If reset when power up MAC and BB in sleep flow, it may destroy the state of bt low power part. --- components/soc/esp32/include/soc/dport_reg.h | 3 +-- components/soc/esp32c3/include/soc/syscon_reg.h | 2 -- components/soc/esp32s2/include/soc/syscon_reg.h | 3 +-- components/soc/esp32s3/include/soc/syscon_reg.h | 2 -- 4 files changed, 2 insertions(+), 8 deletions(-) diff --git a/components/soc/esp32/include/soc/dport_reg.h b/components/soc/esp32/include/soc/dport_reg.h index d8528730a1..bca81ab914 100644 --- a/components/soc/esp32/include/soc/dport_reg.h +++ b/components/soc/esp32/include/soc/dport_reg.h @@ -1093,8 +1093,7 @@ DPORT_WIFIMAC_RST | \ DPORT_BTBB_RST | \ DPORT_BTMAC_RST | \ - DPORT_RW_BTMAC_RST | \ - DPORT_RW_BTLP_RST) + DPORT_RW_BTMAC_RST) #define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4) /* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */ diff --git a/components/soc/esp32c3/include/soc/syscon_reg.h b/components/soc/esp32c3/include/soc/syscon_reg.h index 9514a644cb..e61f84eda3 100644 --- a/components/soc/esp32c3/include/soc/syscon_reg.h +++ b/components/soc/esp32c3/include/soc/syscon_reg.h @@ -216,9 +216,7 @@ extern "C" { SYSTEM_BTBB_RST | \ SYSTEM_BTMAC_RST | \ SYSTEM_RW_BTMAC_RST | \ - SYSTEM_RW_BTLP_RST | \ SYSTEM_RW_BTMAC_REG_RST | \ - SYSTEM_RW_BTLP_REG_RST | \ SYSTEM_BTBB_REG_RST) #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) diff --git a/components/soc/esp32s2/include/soc/syscon_reg.h b/components/soc/esp32s2/include/soc/syscon_reg.h index bf7332412d..91d9e15375 100644 --- a/components/soc/esp32s2/include/soc/syscon_reg.h +++ b/components/soc/esp32s2/include/soc/syscon_reg.h @@ -485,8 +485,7 @@ extern "C" { DPORT_WIFIMAC_RST | \ DPORT_BTBB_RST | \ DPORT_BTMAC_RST | \ - DPORT_RW_BTMAC_RST | \ - DPORT_RW_BTLP_RST) + DPORT_RW_BTMAC_RST) #define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098) /* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ diff --git a/components/soc/esp32s3/include/soc/syscon_reg.h b/components/soc/esp32s3/include/soc/syscon_reg.h index 00dd82df92..cd90d70a4c 100644 --- a/components/soc/esp32s3/include/soc/syscon_reg.h +++ b/components/soc/esp32s3/include/soc/syscon_reg.h @@ -235,9 +235,7 @@ extern "C" { SYSTEM_BTBB_RST | \ SYSTEM_BTMAC_RST | \ SYSTEM_RW_BTMAC_RST | \ - SYSTEM_RW_BTLP_RST | \ SYSTEM_RW_BTMAC_REG_RST | \ - SYSTEM_RW_BTLP_REG_RST | \ SYSTEM_BTBB_REG_RST) #define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)