diff --git a/Kconfig b/Kconfig index 2553a7ce55..8ad408bea2 100644 --- a/Kconfig +++ b/Kconfig @@ -151,6 +151,7 @@ mainmenu "Espressif IoT Development Framework Configuration" default "y" if IDF_TARGET="esp32h4" select IDF_TARGET_ARCH_RISCV select IDF_ENV_BRINGUP + select IDF_ENV_FPGA if ESP32H4_SELECTS_REV_MP config IDF_TARGET_LINUX bool diff --git a/components/esp_hw_support/port/esp32h4/Kconfig.hw_support b/components/esp_hw_support/port/esp32h4/Kconfig.hw_support index c07fec9dfe..2945c1b94c 100644 --- a/components/esp_hw_support/port/esp32h4/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32h4/Kconfig.hw_support @@ -1,3 +1,14 @@ +comment "NOTE! Support of ESP32-H4 MP is mutually exclusive" +comment "Read the help text of the option below for explanation" + +config ESP32H4_SELECTS_REV_MP + bool "Select ESP32-H4 MP version" + default n + help + Enable this option to select ESP32-H4 MP revision. + MP revisions have some hardware differences with Beta revision. + MP revisions is not compatible with Beta revision. + choice ESP32H4_REV_MIN prompt "Minimum Supported ESP32-H4 Revision" default ESP32H4_REV_MIN_0 diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt index cb1d5014e8..7782f24e8d 100644 --- a/components/soc/CMakeLists.txt +++ b/components/soc/CMakeLists.txt @@ -4,11 +4,19 @@ set(target_folder "${target}") # On Linux the soc component is a simple wrapper, without much functionality if(NOT ${target} STREQUAL "linux") - set(srcs "lldesc.c" - "dport_access_common.c" - "${target_folder}/interrupts.c" - "${target_folder}/gpio_periph.c" - "${target_folder}/uart_periph.c") + if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835 + set(srcs "lldesc.c" + "dport_access_common.c" + "${target_folder}/interrupts_beta5.c" + "${target_folder}/gpio_periph.c" + "${target_folder}/uart_periph.c") + else() + set(srcs "lldesc.c" + "dport_access_common.c" + "${target_folder}/interrupts.c" + "${target_folder}/gpio_periph.c" + "${target_folder}/uart_periph.c") + endif() endif() set(includes "include" "${target_folder}") @@ -16,6 +24,13 @@ set(includes "include" "${target_folder}") if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/include") # miscellaneous headers, like definitions, man-made register headers, wrappers, etc. list(APPEND includes "${target_folder}/include") + if(CONFIG_IDF_TARGET_ESP32H4) # TODO: ESP32H4 IDF-13835 + if(CONFIG_ESP32H4_SELECTS_REV_MP) + list(APPEND includes "${target_folder}/include/hw_ver_mp") + else() + list(APPEND includes "${target_folder}/include/hw_ver_beta5") + endif() + endif() endif() # register headers that generated by script from CSV @@ -25,13 +40,20 @@ if(CONFIG_IDF_TARGET_ESP32P4) else() list(APPEND includes "${target_folder}/register/hw_ver2") endif() -elseif(CONFIG_IDF_TARGET_ESP32H21) # TODO: ESP32H4 IDF-13835 +elseif(CONFIG_IDF_TARGET_ESP32H21) # TODO: ESP32H21 IDF-13923 list(APPEND includes "${target_folder}/register") if(CONFIG_ESP32H21_SELECTS_REV_MP) list(APPEND includes "${target_folder}/register/hw_ver_mp") else() list(APPEND includes "${target_folder}/register/hw_ver_beta1") endif() +elseif(CONFIG_IDF_TARGET_ESP32H4) # TODO: ESP32H4 IDF-13835 + list(APPEND includes "${target_folder}/register") + if(CONFIG_ESP32H4_SELECTS_REV_MP) + list(APPEND includes "${target_folder}/register/hw_ver_mp") + else() + list(APPEND includes "${target_folder}/register/hw_ver_beta5") + endif() else() if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register") list(APPEND includes "${target_folder}/register") @@ -210,5 +232,9 @@ if(target STREQUAL "esp32") endif() if(NOT CONFIG_IDF_TARGET_LINUX) - target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld") + if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835 + target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.beta5.ld") + else() + target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld") + endif() endif() diff --git a/components/soc/esp32h4/include/soc/interrupts.h b/components/soc/esp32h4/include/hw_ver_beta5/soc/interrupts.h similarity index 100% rename from components/soc/esp32h4/include/soc/interrupts.h rename to components/soc/esp32h4/include/hw_ver_beta5/soc/interrupts.h diff --git a/components/soc/esp32h4/include/hw_ver_mp/soc/interrupts.h b/components/soc/esp32h4/include/hw_ver_mp/soc/interrupts.h new file mode 100644 index 0000000000..328fe011ff --- /dev/null +++ b/components/soc/esp32h4/include/hw_ver_mp/soc/interrupts.h @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +//Interrupt hardware source table +//This table is decided by hardware, don't touch this. +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE, + ETS_WIFI_MAC_NMI_SOURCE, + ETS_WIFI_PWR_INTR_SOURCE, + ETS_WIFI_BB_INTR_SOURCE, + ETS_BT_MAC_INTR_SOURCE, + ETS_BT_BB_INTR_SOURCE, + ETS_BT_BB_NMI_SOURCE, + ETS_LP_TIMER_INTR_SOURCE, + ETS_COEX_INTR_SOURCE, + ETS_BLE_TIMER_INTR_SOURCE, + ETS_BLE_SEC_INTR_SOURCE, + ETS_I2C_MST_INTR_SOURCE, + ETS_ZB_MAC_INTR_SOURCE, + ETS_MODEM_APB_TIMEOUT_INTR_SOURCE, + ETS_BT_MAC_INT1_SOURCE, + ETS_PMU_INTR_SOURCE, + ETS_EFUSE_INTR_SOURCE, + ETS_LP_RTC_TIMER_INTR_SOURCE, + ETS_LP_RTC_BLE_TIMER_INTR_SOURCE, + ETS_LP_WDT_INTR_SOURCE, + ETS_TOUCH_INTR_SOURCE, + ETS_HUK_INTR_SOURCE, + ETS_LP_PERI_PMS_INTR_SOURCE, + ETS_CPU_INTR_FROM_CPU_0_SOURCE, + ETS_CPU_INTR_FROM_CPU_1_SOURCE, + ETS_CPU_INTR_FROM_CPU_2_SOURCE, + ETS_CPU_INTR_FROM_CPU_3_SOURCE, + ETS_BUS_MONITOR_INTR_SOURCE, + ETS_CORE0_TRACE_INTR_SOURCE, + ETS_CORE1_TRACE_INTR_SOURCE, + ETS_CACHE_INTR_SOURCE, + ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, + ETS_GPIO_INTERRUPT_PRO_SOURCE, + ETS_GPIO_INTERRUPT_2_SOURCE, + ETS_PAU_INTR_SOURCE, + ETS_HP_PERI_TIMEOUT_INTR_SOURCE, + ETS_HP_APM_M0_INTR_SOURCE, + ETS_HP_APM_M1_INTR_SOURCE, + ETS_HP_APM_M2_INTR_SOURCE, + ETS_HP_APM_M3_INTR_SOURCE, + ETS_HP_APM_M4_INTR_SOURCE, + ETS_HP_MEM_APM_M0_INTR_SOURCE, + ETS_HP_MEM_APM_M1_INTR_SOURCE, + ETS_HP_MEM_APM_M2_INTR_SOURCE, + ETS_HP_MEM_APM_M3_INTR_SOURCE, + ETS_CPU_APM_M0_INTR_SOURCE, + ETS_CPU_APM_M1_INTR_SOURCE, + ETS_CPU_APM_M2_INTR_SOURCE, + ETS_CPU_APM_M3_INTR_SOURCE, + ETS_HP_PERI_PMS_INTR_SOURCE, + ETS_MODEM_PERI_PMS_INTR_SOURCE, + ETS_CPU_PERI_PMS_INTR_SOURCE, + ETS_MSPI_INTR_SOURCE, + ETS_I2S_INTR_SOURCE, + ETS_UHCI0_INTR_SOURCE, + ETS_UART0_INTR_SOURCE, + ETS_UART1_INTR_SOURCE, + ETS_LEDC_INTR_SOURCE, + ETS_TWAI0_INTR_SOURCE, + ETS_TWAI0_TIMER_INTR_SOURCE, + ETS_USB_SERIAL_JTAG_INTR_SOURCE, + ETS_RMT_INTR_SOURCE, + ETS_I2C_EXT0_INTR_SOURCE, + ETS_I2C_EXT1_INTR_SOURCE, + ETS_TG0_T0_INTR_SOURCE, + ETS_TG0_WDT_INTR_SOURCE, + ETS_TG1_T0_INTR_SOURCE, + ETS_TG1_WDT_INTR_SOURCE, + ETS_SYSTIMER_TARGET0_INTR_SOURCE, + ETS_SYSTIMER_TARGET1_INTR_SOURCE, + ETS_SYSTIMER_TARGET2_INTR_SOURCE, + ETS_APB_ADC_INTR_SOURCE, + ETS_PWM0_INTR_SOURCE, + ETS_PWM1_INTR_SOURCE, + ETS_PCNT_INTR_SOURCE, + ETS_PARL_IO_TX_INTR_SOURCE, + ETS_PARL_IO_RX_INTR_SOURCE, + ETS_USB_OTG11_INTR_SOURCE, + ETS_ASRC_CHNL0_INTR_SOURCE, + ETS_ASRC_CHNL1_INTR_SOURCE, + ETS_ZERO_DET_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, + ETS_DMA_IN_CH1_INTR_SOURCE, + ETS_DMA_IN_CH2_INTR_SOURCE, + ETS_DMA_IN_CH3_INTR_SOURCE, + ETS_DMA_IN_CH4_INTR_SOURCE, + ETS_DMA_OUT_CH0_INTR_SOURCE, + ETS_DMA_OUT_CH1_INTR_SOURCE, + ETS_DMA_OUT_CH2_INTR_SOURCE, + ETS_DMA_OUT_CH3_INTR_SOURCE, + ETS_DMA_OUT_CH4_INTR_SOURCE, + ETS_GPSPI2_INTR_SOURCE, + ETS_GPSPI3_INTR_SOURCE, + ETS_AES_INTR_SOURCE, + ETS_SHA_INTR_SOURCE, + ETS_ECC_INTR_SOURCE, + ETS_ECDSA_INTR_SOURCE, + ETS_KM_INTR_SOURCE, + ETS_MAX_INTR_SOURCE, +} periph_interrupt_t; + +extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE]; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/interrupts.c b/components/soc/esp32h4/interrupts.c index 5acc172a83..a134be85b3 100644 --- a/components/soc/esp32h4/interrupts.c +++ b/components/soc/esp32h4/interrupts.c @@ -29,72 +29,80 @@ const char *const esp_isr_names[] = { [19] = "LP_WDT", [20] = "TOUCH", [21] = "HUK", - [22] = "CPU_FROM_CPU_0", - [23] = "CPU_FROM_CPU_1", - [24] = "CPU_FROM_CPU_2", - [25] = "CPU_FROM_CPU_3", - [26] = "BUS_MONITOR", - [27] = "CORE0_TRACE", - [28] = "CORE1_TRACE", - [29] = "CACHE", - [30] = "CPU_PERI_TIMEOUT", - [31] = "GPIO_INTERRUPT_PRO", - [32] = "GPIO_INTERRUPT_2", - [33] = "PAU", - [34] = "HP_PERI_TIMEOUT", - [35] = "HP_APM_M0", - [36] = "HP_APM_M1", - [37] = "HP_APM_M2", - [38] = "HP_APM_M3", - [39] = "HP_APM_M4", - [40] = "CPU_APM_M0", - [41] = "CPU_APM_M1", - [42] = "CPU_APM_M2", - [43] = "CPU_APM_M3", - [44] = "MSPI", - [45] = "I2S", - [46] = "UHCI0", - [47] = "UART0", - [48] = "UART1", - [49] = "LEDC", - [50] = "TWAI0", - [51] = "TWAI0_TIMER", - [52] = "USB_SERIAL_JTAG", - [53] = "RMT", - [54] = "I2C_EXT0", - [55] = "I2C_EXT1", - [56] = "TG0_T0", - [57] = "TG0_WDT", - [58] = "TG1_T0", - [59] = "TG1_WDT", - [60] = "SYSTIMER_TARGET0", - [61] = "SYSTIMER_TARGET1", - [62] = "SYSTIMER_TARGET2", - [63] = "APB_ADC", - [64] = "PWM0", - [65] = "PWM1", - [66] = "PCNT", - [67] = "PARL_IO_TX", - [68] = "PARL_IO_RX", - [69] = "USB_OTG11", - [70] = "ASRC_CHNL0", - [71] = "ASRC_CHNL1", - [72] = "ZERO_DET", - [73] = "DMA_IN_CH0", - [74] = "DMA_IN_CH1", - [75] = "DMA_IN_CH2", - [76] = "DMA_IN_CH3", - [77] = "DMA_IN_CH4", - [78] = "DMA_OUT_CH0", - [79] = "DMA_OUT_CH1", - [80] = "DMA_OUT_CH2", - [81] = "DMA_OUT_CH3", - [82] = "DMA_OUT_CH4", - [83] = "GPSPI2", - [84] = "GPSPI3", - [85] = "AES", - [86] = "SHA", - [87] = "ECC", - [88] = "ECDSA", - [89] = "KM", + [22] = "LP_PERI_PMS", + [23] = "CPU_FROM_CPU_0", + [24] = "CPU_FROM_CPU_1", + [25] = "CPU_FROM_CPU_2", + [26] = "CPU_FROM_CPU_3", + [27] = "BUS_MONITOR", + [28] = "CORE0_TRACE", + [29] = "CORE1_TRACE", + [30] = "CACHE", + [31] = "CPU_PERI_TIMEOUT", + [32] = "GPIO_INTERRUPT_PRO", + [33] = "GPIO_INTERRUPT_2", + [34] = "PAU", + [35] = "HP_PERI_TIMEOUT", + [36] = "HP_APM_M0", + [37] = "HP_APM_M1", + [38] = "HP_APM_M2", + [39] = "HP_APM_M3", + [40] = "HP_APM_M4", + [41] = "HP_MEM_APM_M0", + [42] = "HP_MEM_APM_M1", + [43] = "HP_MEM_APM_M2", + [44] = "HP_MEM_APM_M3", + [45] = "CPU_APM_M0", + [46] = "CPU_APM_M1", + [47] = "CPU_APM_M2", + [48] = "CPU_APM_M3", + [49] = "HP_PERI_PMS", + [50] = "MODEM_PERI_PMS", + [51] = "CPU_PERI_PMS", + [52] = "MSPI", + [53] = "I2S", + [54] = "UHCI0", + [55] = "UART0", + [56] = "UART1", + [57] = "LEDC", + [58] = "TWAI0", + [59] = "TWAI0_TIMER", + [60] = "USB_SERIAL_JTAG", + [61] = "RMT", + [62] = "I2C_EXT0", + [63] = "I2C_EXT1", + [64] = "TG0_T0", + [65] = "TG0_WDT", + [66] = "TG1_T0", + [67] = "TG1_WDT", + [68] = "SYSTIMER_TARGET0", + [69] = "SYSTIMER_TARGET1", + [70] = "SYSTIMER_TARGET2", + [71] = "APB_ADC", + [72] = "PWM0", + [73] = "PWM1", + [74] = "PCNT", + [75] = "PARL_IO_TX", + [76] = "PARL_IO_RX", + [77] = "USB_OTG11", + [78] = "ASRC_CHNL0", + [79] = "ASRC_CHNL1", + [80] = "ZERO_DET", + [81] = "DMA_IN_CH0", + [82] = "DMA_IN_CH1", + [83] = "DMA_IN_CH2", + [84] = "DMA_IN_CH3", + [85] = "DMA_IN_CH4", + [86] = "DMA_OUT_CH0", + [87] = "DMA_OUT_CH1", + [88] = "DMA_OUT_CH2", + [89] = "DMA_OUT_CH3", + [90] = "DMA_OUT_CH4", + [91] = "GPSPI2", + [92] = "GPSPI3", + [93] = "AES", + [94] = "SHA", + [95] = "ECC", + [96] = "ECDSA", + [97] = "KM", }; diff --git a/components/soc/esp32h4/interrupts_beta5.c b/components/soc/esp32h4/interrupts_beta5.c new file mode 100644 index 0000000000..5acc172a83 --- /dev/null +++ b/components/soc/esp32h4/interrupts_beta5.c @@ -0,0 +1,100 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "soc/interrupts.h" + +const char *const esp_isr_names[] = { + [0] = "WIFI_MAC", + [1] = "WIFI_MAC_NMI", + [2] = "WIFI_PWR", + [3] = "WIFI_BB", + [4] = "BT_MAC", + [5] = "BT_BB", + [6] = "BT_BB_NMI", + [7] = "LP_TIMER", + [8] = "COEX", + [9] = "BLE_TIMER", + [10] = "BLE_SEC", + [11] = "I2C_MST", + [12] = "ZB_MAC", + [13] = "MODEM_APB_TIMEOUT", + [14] = "BT_MAC_INT1", + [15] = "PMU", + [16] = "EFUSE", + [17] = "LP_RTC_TIMER", + [18] = "LP_RTC_BLE_TIMER", + [19] = "LP_WDT", + [20] = "TOUCH", + [21] = "HUK", + [22] = "CPU_FROM_CPU_0", + [23] = "CPU_FROM_CPU_1", + [24] = "CPU_FROM_CPU_2", + [25] = "CPU_FROM_CPU_3", + [26] = "BUS_MONITOR", + [27] = "CORE0_TRACE", + [28] = "CORE1_TRACE", + [29] = "CACHE", + [30] = "CPU_PERI_TIMEOUT", + [31] = "GPIO_INTERRUPT_PRO", + [32] = "GPIO_INTERRUPT_2", + [33] = "PAU", + [34] = "HP_PERI_TIMEOUT", + [35] = "HP_APM_M0", + [36] = "HP_APM_M1", + [37] = "HP_APM_M2", + [38] = "HP_APM_M3", + [39] = "HP_APM_M4", + [40] = "CPU_APM_M0", + [41] = "CPU_APM_M1", + [42] = "CPU_APM_M2", + [43] = "CPU_APM_M3", + [44] = "MSPI", + [45] = "I2S", + [46] = "UHCI0", + [47] = "UART0", + [48] = "UART1", + [49] = "LEDC", + [50] = "TWAI0", + [51] = "TWAI0_TIMER", + [52] = "USB_SERIAL_JTAG", + [53] = "RMT", + [54] = "I2C_EXT0", + [55] = "I2C_EXT1", + [56] = "TG0_T0", + [57] = "TG0_WDT", + [58] = "TG1_T0", + [59] = "TG1_WDT", + [60] = "SYSTIMER_TARGET0", + [61] = "SYSTIMER_TARGET1", + [62] = "SYSTIMER_TARGET2", + [63] = "APB_ADC", + [64] = "PWM0", + [65] = "PWM1", + [66] = "PCNT", + [67] = "PARL_IO_TX", + [68] = "PARL_IO_RX", + [69] = "USB_OTG11", + [70] = "ASRC_CHNL0", + [71] = "ASRC_CHNL1", + [72] = "ZERO_DET", + [73] = "DMA_IN_CH0", + [74] = "DMA_IN_CH1", + [75] = "DMA_IN_CH2", + [76] = "DMA_IN_CH3", + [77] = "DMA_IN_CH4", + [78] = "DMA_OUT_CH0", + [79] = "DMA_OUT_CH1", + [80] = "DMA_OUT_CH2", + [81] = "DMA_OUT_CH3", + [82] = "DMA_OUT_CH4", + [83] = "GPSPI2", + [84] = "GPSPI3", + [85] = "AES", + [86] = "SHA", + [87] = "ECC", + [88] = "ECDSA", + [89] = "KM", +}; diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld new file mode 100644 index 0000000000..4ecd54aa6c --- /dev/null +++ b/components/soc/esp32h4/ld/esp32h4.peripherals.beta5.ld @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +PROVIDE ( TRACE0 = 0x60000000 ); +PROVIDE ( TRACE1 = 0x60001000 ); +PROVIDE ( ASSIST_DEBUG = 0x60002000 ); +PROVIDE ( INTPRI = 0x60005000 ); +PROVIDE ( CACHE = 0x60008000 ); +PROVIDE ( GPSPI2 = 0x60010000 ); +PROVIDE ( GPSPI3 = 0x60011000 ); +PROVIDE ( UART0 = 0x60012000 ); +PROVIDE ( UART1 = 0x60013000 ); +PROVIDE ( UHCI0 = 0x60014000 ); +PROVIDE ( I2C0 = 0x60015000 ); +PROVIDE ( I2C1 = 0x60016000 ); +PROVIDE ( I2S0 = 0x60017000 ); +PROVIDE ( PARL_IO = 0x60018000 ); +PROVIDE ( MCPWM0 = 0x60019000 ); +PROVIDE ( MCPWM1 = 0x6001A000 ); +PROVIDE ( LEDC = 0x6001B000 ); +PROVIDE ( TWAI0 = 0x6001C000 ); +PROVIDE ( USB_SERIAL_JTAG = 0x6001D000 ); +PROVIDE ( RMT = 0x6001E000 ); +PROVIDE ( RMTMEM = 0x6001E400 ); +PROVIDE ( AHB_DMA = 0x6001F000 ); +PROVIDE ( PAU = 0x60020000 ); +PROVIDE ( SOC_ETM = 0x60021000 ); +PROVIDE ( ADC = 0x60022000 ); +PROVIDE ( SYSTIMER = 0x60023000 ); +PROVIDE ( PSRAM_ACS_MONITOR = 0x60024000 ); /* TODO: IDF-12491 [ESP32H4] inherit from verify code, need check */ +PROVIDE ( MEM_MONITOR = 0x60025000 ); +PROVIDE ( PVT = 0x60026000 ); +PROVIDE ( PCNT = 0x60027000 ); +PROVIDE ( SAMPLE_RATE_CONVERTER = 0x60028000 ); +PROVIDE ( ZERO_DET = 0x60029000 ); +PROVIDE ( USB_OTG_FS_CORE0 = 0x60040000 ); +PROVIDE ( USB_OTG_FS_CORE1 = 0x6007F000 ); +PROVIDE ( USB_OTG_FS_PHY = 0x60080000 ); +PROVIDE ( TIMERG0 = 0x60090000 ); +PROVIDE ( TIMERG1 = 0x60091000 ); +PROVIDE ( IO_MUX = 0x60092000 ); +PROVIDE ( GPIO = 0x60093000 ); +PROVIDE ( GPIO_EXT = 0x60093E00 ); +PROVIDE ( SDM = 0x60093E00 ); +PROVIDE ( GLITCH_FILTER = 0x60093ED8 ); +PROVIDE ( GPIO_ETM = 0x60093F18 ); +PROVIDE ( PCR = 0x60094000 ); +PROVIDE ( SPIMEM0 = 0x60098000 ); +PROVIDE ( SPIMEM1 = 0x60099000 ); +PROVIDE ( INTMTX0 = 0x6009A000 ); +PROVIDE ( INTMTX1 = 0x6009B000 ); +PROVIDE ( HP_SYSTEM = 0x6009C000 ); +PROVIDE ( HP_APM = 0x6009D000 ); +PROVIDE ( CPU_APM = 0x6009E000 ); +PROVIDE ( TEE = 0x6009F000 ); +PROVIDE ( KEYMNG = 0x600A5000 ); +PROVIDE ( AES = 0x600A6000 ); +PROVIDE ( SHA = 0x600A7000 ); +PROVIDE ( ECC = 0x600A8000 ); +PROVIDE ( HMAC = 0x600A9000 ); +PROVIDE ( ECDSA = 0x600AA000 ); +PROVIDE ( HUK = 0x600B1000 ); +PROVIDE ( LP_TEE = 0x600B1400 ); +PROVIDE ( EFUSE = 0x600B1800 ); +PROVIDE ( OTP_DEBUG = 0x600B1C00 ); +PROVIDE ( TRNG = 0x600B2000 ); +PROVIDE ( PMU = 0x600B2400 ); +PROVIDE ( LP_AON = 0x600B2800 ); +PROVIDE ( LP_ANA_PERI = 0x600B2C00 ); +PROVIDE ( LP_CLKRST = 0x600B3000 ); +PROVIDE ( LPPERI = 0x600B3400 ); +PROVIDE ( LP_IO_MUX = 0x600B3800 ); +PROVIDE ( LP_GPIO = 0x600B3C00 ); +PROVIDE ( LP_TIMER = 0x600B5000 ); +PROVIDE ( LP_WDT = 0x600B5400 ); +PROVIDE ( TOUCH_SENS = 0x600B5800 ); +PROVIDE ( TOUCH_AON = 0x600B5C00 ); +PROVIDE ( MODEM_SYSCON = 0x600C9C00 ); +PROVIDE ( MODEM_LPCON = 0x600CF000 ); diff --git a/components/soc/esp32h4/ld/esp32h4.peripherals.ld b/components/soc/esp32h4/ld/esp32h4.peripherals.ld index 4ecd54aa6c..1590a3c3f8 100644 --- a/components/soc/esp32h4/ld/esp32h4.peripherals.ld +++ b/components/soc/esp32h4/ld/esp32h4.peripherals.ld @@ -54,7 +54,8 @@ PROVIDE ( INTMTX0 = 0x6009A000 ); PROVIDE ( INTMTX1 = 0x6009B000 ); PROVIDE ( HP_SYSTEM = 0x6009C000 ); PROVIDE ( HP_APM = 0x6009D000 ); -PROVIDE ( CPU_APM = 0x6009E000 ); +PROVIDE ( HP_MEM_APM_REG = 0x6009E000 ); +PROVIDE ( CPU_APM = 0x6009E800 ); PROVIDE ( TEE = 0x6009F000 ); PROVIDE ( KEYMNG = 0x600A5000 ); PROVIDE ( AES = 0x600A6000 ); diff --git a/components/soc/esp32h4/register/soc/cpu_apm_reg.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_reg.h similarity index 100% rename from components/soc/esp32h4/register/soc/cpu_apm_reg.h rename to components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_reg.h diff --git a/components/soc/esp32h4/register/soc/cpu_apm_struct.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_struct.h similarity index 100% rename from components/soc/esp32h4/register/soc/cpu_apm_struct.h rename to components/soc/esp32h4/register/hw_ver_beta5/soc/cpu_apm_struct.h diff --git a/components/soc/esp32h4/register/soc/interrupt_matrix_reg.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_reg.h similarity index 100% rename from components/soc/esp32h4/register/soc/interrupt_matrix_reg.h rename to components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_reg.h diff --git a/components/soc/esp32h4/register/soc/interrupt_matrix_struct.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_struct.h similarity index 100% rename from components/soc/esp32h4/register/soc/interrupt_matrix_struct.h rename to components/soc/esp32h4/register/hw_ver_beta5/soc/interrupt_matrix_struct.h diff --git a/components/soc/esp32h4/register/soc/tee_reg.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/tee_reg.h similarity index 100% rename from components/soc/esp32h4/register/soc/tee_reg.h rename to components/soc/esp32h4/register/hw_ver_beta5/soc/tee_reg.h diff --git a/components/soc/esp32h4/register/soc/tee_struct.h b/components/soc/esp32h4/register/hw_ver_beta5/soc/tee_struct.h similarity index 100% rename from components/soc/esp32h4/register/soc/tee_struct.h rename to components/soc/esp32h4/register/hw_ver_beta5/soc/tee_struct.h diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_reg.h b/components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_reg.h new file mode 100644 index 0000000000..cc3f4e14c9 --- /dev/null +++ b/components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_reg.h @@ -0,0 +1,1402 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CPU_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_BASE + 0x0) +/** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ +#define CPU_APM_REGION_FILTER_EN 0x000000FFU +#define CPU_APM_REGION_FILTER_EN_M (CPU_APM_REGION_FILTER_EN_V << CPU_APM_REGION_FILTER_EN_S) +#define CPU_APM_REGION_FILTER_EN_V 0x000000FFU +#define CPU_APM_REGION_FILTER_EN_S 0 + +/** CPU_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4) +/** CPU_APM_REGION0_ADDR_START_L : HRO; bitpos: [12:0]; default: 0; + * Low 12 bit, start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START_L 0x00001FFFU +#define CPU_APM_REGION0_ADDR_START_L_M (CPU_APM_REGION0_ADDR_START_L_V << CPU_APM_REGION0_ADDR_START_L_S) +#define CPU_APM_REGION0_ADDR_START_L_V 0x00001FFFU +#define CPU_APM_REGION0_ADDR_START_L_S 0 +/** CPU_APM_REGION0_ADDR_START : R/W; bitpos: [24:13]; default: 0; + * Configures start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START 0x00000FFFU +#define CPU_APM_REGION0_ADDR_START_M (CPU_APM_REGION0_ADDR_START_V << CPU_APM_REGION0_ADDR_START_S) +#define CPU_APM_REGION0_ADDR_START_V 0x00000FFFU +#define CPU_APM_REGION0_ADDR_START_S 13 +/** CPU_APM_REGION0_ADDR_START_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START_H 0x0000007FU +#define CPU_APM_REGION0_ADDR_START_H_M (CPU_APM_REGION0_ADDR_START_H_V << CPU_APM_REGION0_ADDR_START_H_S) +#define CPU_APM_REGION0_ADDR_START_H_V 0x0000007FU +#define CPU_APM_REGION0_ADDR_START_H_S 25 + +/** CPU_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x8) +/** CPU_APM_REGION0_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191; + * Low 12 bit, end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END_L 0x00001FFFU +#define CPU_APM_REGION0_ADDR_END_L_M (CPU_APM_REGION0_ADDR_END_L_V << CPU_APM_REGION0_ADDR_END_L_S) +#define CPU_APM_REGION0_ADDR_END_L_V 0x00001FFFU +#define CPU_APM_REGION0_ADDR_END_L_S 0 +/** CPU_APM_REGION0_ADDR_END : R/W; bitpos: [24:13]; default: 4095; + * Configures end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END 0x00000FFFU +#define CPU_APM_REGION0_ADDR_END_M (CPU_APM_REGION0_ADDR_END_V << CPU_APM_REGION0_ADDR_END_S) +#define CPU_APM_REGION0_ADDR_END_V 0x00000FFFU +#define CPU_APM_REGION0_ADDR_END_S 13 +/** CPU_APM_REGION0_ADDR_END_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END_H 0x0000007FU +#define CPU_APM_REGION0_ADDR_END_H_M (CPU_APM_REGION0_ADDR_END_H_V << CPU_APM_REGION0_ADDR_END_H_S) +#define CPU_APM_REGION0_ADDR_END_H_V 0x0000007FU +#define CPU_APM_REGION0_ADDR_END_H_S 25 + +/** CPU_APM_REGION0_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_BASE + 0xc) +/** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_X (BIT(0)) +#define CPU_APM_REGION0_R0_X_M (CPU_APM_REGION0_R0_X_V << CPU_APM_REGION0_R0_X_S) +#define CPU_APM_REGION0_R0_X_V 0x00000001U +#define CPU_APM_REGION0_R0_X_S 0 +/** CPU_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_W (BIT(1)) +#define CPU_APM_REGION0_R0_W_M (CPU_APM_REGION0_R0_W_V << CPU_APM_REGION0_R0_W_S) +#define CPU_APM_REGION0_R0_W_V 0x00000001U +#define CPU_APM_REGION0_R0_W_S 1 +/** CPU_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_R (BIT(2)) +#define CPU_APM_REGION0_R0_R_M (CPU_APM_REGION0_R0_R_V << CPU_APM_REGION0_R0_R_S) +#define CPU_APM_REGION0_R0_R_V 0x00000001U +#define CPU_APM_REGION0_R0_R_S 2 +/** CPU_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_X (BIT(4)) +#define CPU_APM_REGION0_R1_X_M (CPU_APM_REGION0_R1_X_V << CPU_APM_REGION0_R1_X_S) +#define CPU_APM_REGION0_R1_X_V 0x00000001U +#define CPU_APM_REGION0_R1_X_S 4 +/** CPU_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_W (BIT(5)) +#define CPU_APM_REGION0_R1_W_M (CPU_APM_REGION0_R1_W_V << CPU_APM_REGION0_R1_W_S) +#define CPU_APM_REGION0_R1_W_V 0x00000001U +#define CPU_APM_REGION0_R1_W_S 5 +/** CPU_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_R (BIT(6)) +#define CPU_APM_REGION0_R1_R_M (CPU_APM_REGION0_R1_R_V << CPU_APM_REGION0_R1_R_S) +#define CPU_APM_REGION0_R1_R_V 0x00000001U +#define CPU_APM_REGION0_R1_R_S 6 +/** CPU_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_X (BIT(8)) +#define CPU_APM_REGION0_R2_X_M (CPU_APM_REGION0_R2_X_V << CPU_APM_REGION0_R2_X_S) +#define CPU_APM_REGION0_R2_X_V 0x00000001U +#define CPU_APM_REGION0_R2_X_S 8 +/** CPU_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_W (BIT(9)) +#define CPU_APM_REGION0_R2_W_M (CPU_APM_REGION0_R2_W_V << CPU_APM_REGION0_R2_W_S) +#define CPU_APM_REGION0_R2_W_V 0x00000001U +#define CPU_APM_REGION0_R2_W_S 9 +/** CPU_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_R (BIT(10)) +#define CPU_APM_REGION0_R2_R_M (CPU_APM_REGION0_R2_R_V << CPU_APM_REGION0_R2_R_S) +#define CPU_APM_REGION0_R2_R_V 0x00000001U +#define CPU_APM_REGION0_R2_R_S 10 +/** CPU_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION0_LOCK (BIT(11)) +#define CPU_APM_REGION0_LOCK_M (CPU_APM_REGION0_LOCK_V << CPU_APM_REGION0_LOCK_S) +#define CPU_APM_REGION0_LOCK_V 0x00000001U +#define CPU_APM_REGION0_LOCK_S 11 + +/** CPU_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x10) +/** CPU_APM_REGION1_ADDR_START_L : HRO; bitpos: [12:0]; default: 0; + * Low 12 bit, start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START_L 0x00001FFFU +#define CPU_APM_REGION1_ADDR_START_L_M (CPU_APM_REGION1_ADDR_START_L_V << CPU_APM_REGION1_ADDR_START_L_S) +#define CPU_APM_REGION1_ADDR_START_L_V 0x00001FFFU +#define CPU_APM_REGION1_ADDR_START_L_S 0 +/** CPU_APM_REGION1_ADDR_START : R/W; bitpos: [24:13]; default: 0; + * Configures start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START 0x00000FFFU +#define CPU_APM_REGION1_ADDR_START_M (CPU_APM_REGION1_ADDR_START_V << CPU_APM_REGION1_ADDR_START_S) +#define CPU_APM_REGION1_ADDR_START_V 0x00000FFFU +#define CPU_APM_REGION1_ADDR_START_S 13 +/** CPU_APM_REGION1_ADDR_START_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START_H 0x0000007FU +#define CPU_APM_REGION1_ADDR_START_H_M (CPU_APM_REGION1_ADDR_START_H_V << CPU_APM_REGION1_ADDR_START_H_S) +#define CPU_APM_REGION1_ADDR_START_H_V 0x0000007FU +#define CPU_APM_REGION1_ADDR_START_H_S 25 + +/** CPU_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x14) +/** CPU_APM_REGION1_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191; + * Low 12 bit, end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END_L 0x00001FFFU +#define CPU_APM_REGION1_ADDR_END_L_M (CPU_APM_REGION1_ADDR_END_L_V << CPU_APM_REGION1_ADDR_END_L_S) +#define CPU_APM_REGION1_ADDR_END_L_V 0x00001FFFU +#define CPU_APM_REGION1_ADDR_END_L_S 0 +/** CPU_APM_REGION1_ADDR_END : R/W; bitpos: [24:13]; default: 4095; + * Configures end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END 0x00000FFFU +#define CPU_APM_REGION1_ADDR_END_M (CPU_APM_REGION1_ADDR_END_V << CPU_APM_REGION1_ADDR_END_S) +#define CPU_APM_REGION1_ADDR_END_V 0x00000FFFU +#define CPU_APM_REGION1_ADDR_END_S 13 +/** CPU_APM_REGION1_ADDR_END_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END_H 0x0000007FU +#define CPU_APM_REGION1_ADDR_END_H_M (CPU_APM_REGION1_ADDR_END_H_V << CPU_APM_REGION1_ADDR_END_H_S) +#define CPU_APM_REGION1_ADDR_END_H_V 0x0000007FU +#define CPU_APM_REGION1_ADDR_END_H_S 25 + +/** CPU_APM_REGION1_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_BASE + 0x18) +/** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_X (BIT(0)) +#define CPU_APM_REGION1_R0_X_M (CPU_APM_REGION1_R0_X_V << CPU_APM_REGION1_R0_X_S) +#define CPU_APM_REGION1_R0_X_V 0x00000001U +#define CPU_APM_REGION1_R0_X_S 0 +/** CPU_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_W (BIT(1)) +#define CPU_APM_REGION1_R0_W_M (CPU_APM_REGION1_R0_W_V << CPU_APM_REGION1_R0_W_S) +#define CPU_APM_REGION1_R0_W_V 0x00000001U +#define CPU_APM_REGION1_R0_W_S 1 +/** CPU_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_R (BIT(2)) +#define CPU_APM_REGION1_R0_R_M (CPU_APM_REGION1_R0_R_V << CPU_APM_REGION1_R0_R_S) +#define CPU_APM_REGION1_R0_R_V 0x00000001U +#define CPU_APM_REGION1_R0_R_S 2 +/** CPU_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_X (BIT(4)) +#define CPU_APM_REGION1_R1_X_M (CPU_APM_REGION1_R1_X_V << CPU_APM_REGION1_R1_X_S) +#define CPU_APM_REGION1_R1_X_V 0x00000001U +#define CPU_APM_REGION1_R1_X_S 4 +/** CPU_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_W (BIT(5)) +#define CPU_APM_REGION1_R1_W_M (CPU_APM_REGION1_R1_W_V << CPU_APM_REGION1_R1_W_S) +#define CPU_APM_REGION1_R1_W_V 0x00000001U +#define CPU_APM_REGION1_R1_W_S 5 +/** CPU_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_R (BIT(6)) +#define CPU_APM_REGION1_R1_R_M (CPU_APM_REGION1_R1_R_V << CPU_APM_REGION1_R1_R_S) +#define CPU_APM_REGION1_R1_R_V 0x00000001U +#define CPU_APM_REGION1_R1_R_S 6 +/** CPU_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_X (BIT(8)) +#define CPU_APM_REGION1_R2_X_M (CPU_APM_REGION1_R2_X_V << CPU_APM_REGION1_R2_X_S) +#define CPU_APM_REGION1_R2_X_V 0x00000001U +#define CPU_APM_REGION1_R2_X_S 8 +/** CPU_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_W (BIT(9)) +#define CPU_APM_REGION1_R2_W_M (CPU_APM_REGION1_R2_W_V << CPU_APM_REGION1_R2_W_S) +#define CPU_APM_REGION1_R2_W_V 0x00000001U +#define CPU_APM_REGION1_R2_W_S 9 +/** CPU_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_R (BIT(10)) +#define CPU_APM_REGION1_R2_R_M (CPU_APM_REGION1_R2_R_V << CPU_APM_REGION1_R2_R_S) +#define CPU_APM_REGION1_R2_R_V 0x00000001U +#define CPU_APM_REGION1_R2_R_S 10 +/** CPU_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION1_LOCK (BIT(11)) +#define CPU_APM_REGION1_LOCK_M (CPU_APM_REGION1_LOCK_V << CPU_APM_REGION1_LOCK_S) +#define CPU_APM_REGION1_LOCK_V 0x00000001U +#define CPU_APM_REGION1_LOCK_S 11 + +/** CPU_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x1c) +/** CPU_APM_REGION2_ADDR_START_L : HRO; bitpos: [12:0]; default: 0; + * Low 12 bit, start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START_L 0x00001FFFU +#define CPU_APM_REGION2_ADDR_START_L_M (CPU_APM_REGION2_ADDR_START_L_V << CPU_APM_REGION2_ADDR_START_L_S) +#define CPU_APM_REGION2_ADDR_START_L_V 0x00001FFFU +#define CPU_APM_REGION2_ADDR_START_L_S 0 +/** CPU_APM_REGION2_ADDR_START : R/W; bitpos: [24:13]; default: 0; + * Configures start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START 0x00000FFFU +#define CPU_APM_REGION2_ADDR_START_M (CPU_APM_REGION2_ADDR_START_V << CPU_APM_REGION2_ADDR_START_S) +#define CPU_APM_REGION2_ADDR_START_V 0x00000FFFU +#define CPU_APM_REGION2_ADDR_START_S 13 +/** CPU_APM_REGION2_ADDR_START_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START_H 0x0000007FU +#define CPU_APM_REGION2_ADDR_START_H_M (CPU_APM_REGION2_ADDR_START_H_V << CPU_APM_REGION2_ADDR_START_H_S) +#define CPU_APM_REGION2_ADDR_START_H_V 0x0000007FU +#define CPU_APM_REGION2_ADDR_START_H_S 25 + +/** CPU_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x20) +/** CPU_APM_REGION2_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191; + * Low 12 bit, end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END_L 0x00001FFFU +#define CPU_APM_REGION2_ADDR_END_L_M (CPU_APM_REGION2_ADDR_END_L_V << CPU_APM_REGION2_ADDR_END_L_S) +#define CPU_APM_REGION2_ADDR_END_L_V 0x00001FFFU +#define CPU_APM_REGION2_ADDR_END_L_S 0 +/** CPU_APM_REGION2_ADDR_END : R/W; bitpos: [24:13]; default: 4095; + * Configures end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END 0x00000FFFU +#define CPU_APM_REGION2_ADDR_END_M (CPU_APM_REGION2_ADDR_END_V << CPU_APM_REGION2_ADDR_END_S) +#define CPU_APM_REGION2_ADDR_END_V 0x00000FFFU +#define CPU_APM_REGION2_ADDR_END_S 13 +/** CPU_APM_REGION2_ADDR_END_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END_H 0x0000007FU +#define CPU_APM_REGION2_ADDR_END_H_M (CPU_APM_REGION2_ADDR_END_H_V << CPU_APM_REGION2_ADDR_END_H_S) +#define CPU_APM_REGION2_ADDR_END_H_V 0x0000007FU +#define CPU_APM_REGION2_ADDR_END_H_S 25 + +/** CPU_APM_REGION2_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_BASE + 0x24) +/** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_X (BIT(0)) +#define CPU_APM_REGION2_R0_X_M (CPU_APM_REGION2_R0_X_V << CPU_APM_REGION2_R0_X_S) +#define CPU_APM_REGION2_R0_X_V 0x00000001U +#define CPU_APM_REGION2_R0_X_S 0 +/** CPU_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_W (BIT(1)) +#define CPU_APM_REGION2_R0_W_M (CPU_APM_REGION2_R0_W_V << CPU_APM_REGION2_R0_W_S) +#define CPU_APM_REGION2_R0_W_V 0x00000001U +#define CPU_APM_REGION2_R0_W_S 1 +/** CPU_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_R (BIT(2)) +#define CPU_APM_REGION2_R0_R_M (CPU_APM_REGION2_R0_R_V << CPU_APM_REGION2_R0_R_S) +#define CPU_APM_REGION2_R0_R_V 0x00000001U +#define CPU_APM_REGION2_R0_R_S 2 +/** CPU_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_X (BIT(4)) +#define CPU_APM_REGION2_R1_X_M (CPU_APM_REGION2_R1_X_V << CPU_APM_REGION2_R1_X_S) +#define CPU_APM_REGION2_R1_X_V 0x00000001U +#define CPU_APM_REGION2_R1_X_S 4 +/** CPU_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_W (BIT(5)) +#define CPU_APM_REGION2_R1_W_M (CPU_APM_REGION2_R1_W_V << CPU_APM_REGION2_R1_W_S) +#define CPU_APM_REGION2_R1_W_V 0x00000001U +#define CPU_APM_REGION2_R1_W_S 5 +/** CPU_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_R (BIT(6)) +#define CPU_APM_REGION2_R1_R_M (CPU_APM_REGION2_R1_R_V << CPU_APM_REGION2_R1_R_S) +#define CPU_APM_REGION2_R1_R_V 0x00000001U +#define CPU_APM_REGION2_R1_R_S 6 +/** CPU_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_X (BIT(8)) +#define CPU_APM_REGION2_R2_X_M (CPU_APM_REGION2_R2_X_V << CPU_APM_REGION2_R2_X_S) +#define CPU_APM_REGION2_R2_X_V 0x00000001U +#define CPU_APM_REGION2_R2_X_S 8 +/** CPU_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_W (BIT(9)) +#define CPU_APM_REGION2_R2_W_M (CPU_APM_REGION2_R2_W_V << CPU_APM_REGION2_R2_W_S) +#define CPU_APM_REGION2_R2_W_V 0x00000001U +#define CPU_APM_REGION2_R2_W_S 9 +/** CPU_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_R (BIT(10)) +#define CPU_APM_REGION2_R2_R_M (CPU_APM_REGION2_R2_R_V << CPU_APM_REGION2_R2_R_S) +#define CPU_APM_REGION2_R2_R_V 0x00000001U +#define CPU_APM_REGION2_R2_R_S 10 +/** CPU_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION2_LOCK (BIT(11)) +#define CPU_APM_REGION2_LOCK_M (CPU_APM_REGION2_LOCK_V << CPU_APM_REGION2_LOCK_S) +#define CPU_APM_REGION2_LOCK_V 0x00000001U +#define CPU_APM_REGION2_LOCK_S 11 + +/** CPU_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x28) +/** CPU_APM_REGION3_ADDR_START_L : HRO; bitpos: [12:0]; default: 0; + * Low 12 bit, start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START_L 0x00001FFFU +#define CPU_APM_REGION3_ADDR_START_L_M (CPU_APM_REGION3_ADDR_START_L_V << CPU_APM_REGION3_ADDR_START_L_S) +#define CPU_APM_REGION3_ADDR_START_L_V 0x00001FFFU +#define CPU_APM_REGION3_ADDR_START_L_S 0 +/** CPU_APM_REGION3_ADDR_START : R/W; bitpos: [24:13]; default: 0; + * Configures start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START 0x00000FFFU +#define CPU_APM_REGION3_ADDR_START_M (CPU_APM_REGION3_ADDR_START_V << CPU_APM_REGION3_ADDR_START_S) +#define CPU_APM_REGION3_ADDR_START_V 0x00000FFFU +#define CPU_APM_REGION3_ADDR_START_S 13 +/** CPU_APM_REGION3_ADDR_START_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START_H 0x0000007FU +#define CPU_APM_REGION3_ADDR_START_H_M (CPU_APM_REGION3_ADDR_START_H_V << CPU_APM_REGION3_ADDR_START_H_S) +#define CPU_APM_REGION3_ADDR_START_H_V 0x0000007FU +#define CPU_APM_REGION3_ADDR_START_H_S 25 + +/** CPU_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x2c) +/** CPU_APM_REGION3_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191; + * Low 12 bit, end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END_L 0x00001FFFU +#define CPU_APM_REGION3_ADDR_END_L_M (CPU_APM_REGION3_ADDR_END_L_V << CPU_APM_REGION3_ADDR_END_L_S) +#define CPU_APM_REGION3_ADDR_END_L_V 0x00001FFFU +#define CPU_APM_REGION3_ADDR_END_L_S 0 +/** CPU_APM_REGION3_ADDR_END : R/W; bitpos: [24:13]; default: 4095; + * Configures end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END 0x00000FFFU +#define CPU_APM_REGION3_ADDR_END_M (CPU_APM_REGION3_ADDR_END_V << CPU_APM_REGION3_ADDR_END_S) +#define CPU_APM_REGION3_ADDR_END_V 0x00000FFFU +#define CPU_APM_REGION3_ADDR_END_S 13 +/** CPU_APM_REGION3_ADDR_END_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END_H 0x0000007FU +#define CPU_APM_REGION3_ADDR_END_H_M (CPU_APM_REGION3_ADDR_END_H_V << CPU_APM_REGION3_ADDR_END_H_S) +#define CPU_APM_REGION3_ADDR_END_H_V 0x0000007FU +#define CPU_APM_REGION3_ADDR_END_H_S 25 + +/** CPU_APM_REGION3_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_BASE + 0x30) +/** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_X (BIT(0)) +#define CPU_APM_REGION3_R0_X_M (CPU_APM_REGION3_R0_X_V << CPU_APM_REGION3_R0_X_S) +#define CPU_APM_REGION3_R0_X_V 0x00000001U +#define CPU_APM_REGION3_R0_X_S 0 +/** CPU_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_W (BIT(1)) +#define CPU_APM_REGION3_R0_W_M (CPU_APM_REGION3_R0_W_V << CPU_APM_REGION3_R0_W_S) +#define CPU_APM_REGION3_R0_W_V 0x00000001U +#define CPU_APM_REGION3_R0_W_S 1 +/** CPU_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_R (BIT(2)) +#define CPU_APM_REGION3_R0_R_M (CPU_APM_REGION3_R0_R_V << CPU_APM_REGION3_R0_R_S) +#define CPU_APM_REGION3_R0_R_V 0x00000001U +#define CPU_APM_REGION3_R0_R_S 2 +/** CPU_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_X (BIT(4)) +#define CPU_APM_REGION3_R1_X_M (CPU_APM_REGION3_R1_X_V << CPU_APM_REGION3_R1_X_S) +#define CPU_APM_REGION3_R1_X_V 0x00000001U +#define CPU_APM_REGION3_R1_X_S 4 +/** CPU_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_W (BIT(5)) +#define CPU_APM_REGION3_R1_W_M (CPU_APM_REGION3_R1_W_V << CPU_APM_REGION3_R1_W_S) +#define CPU_APM_REGION3_R1_W_V 0x00000001U +#define CPU_APM_REGION3_R1_W_S 5 +/** CPU_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_R (BIT(6)) +#define CPU_APM_REGION3_R1_R_M (CPU_APM_REGION3_R1_R_V << CPU_APM_REGION3_R1_R_S) +#define CPU_APM_REGION3_R1_R_V 0x00000001U +#define CPU_APM_REGION3_R1_R_S 6 +/** CPU_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_X (BIT(8)) +#define CPU_APM_REGION3_R2_X_M (CPU_APM_REGION3_R2_X_V << CPU_APM_REGION3_R2_X_S) +#define CPU_APM_REGION3_R2_X_V 0x00000001U +#define CPU_APM_REGION3_R2_X_S 8 +/** CPU_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_W (BIT(9)) +#define CPU_APM_REGION3_R2_W_M (CPU_APM_REGION3_R2_W_V << CPU_APM_REGION3_R2_W_S) +#define CPU_APM_REGION3_R2_W_V 0x00000001U +#define CPU_APM_REGION3_R2_W_S 9 +/** CPU_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_R (BIT(10)) +#define CPU_APM_REGION3_R2_R_M (CPU_APM_REGION3_R2_R_V << CPU_APM_REGION3_R2_R_S) +#define CPU_APM_REGION3_R2_R_V 0x00000001U +#define CPU_APM_REGION3_R2_R_S 10 +/** CPU_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION3_LOCK (BIT(11)) +#define CPU_APM_REGION3_LOCK_M (CPU_APM_REGION3_LOCK_V << CPU_APM_REGION3_LOCK_S) +#define CPU_APM_REGION3_LOCK_V 0x00000001U +#define CPU_APM_REGION3_LOCK_S 11 + +/** CPU_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x34) +/** CPU_APM_REGION4_ADDR_START_L : HRO; bitpos: [12:0]; default: 0; + * Low 12 bit, start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START_L 0x00001FFFU +#define CPU_APM_REGION4_ADDR_START_L_M (CPU_APM_REGION4_ADDR_START_L_V << CPU_APM_REGION4_ADDR_START_L_S) +#define CPU_APM_REGION4_ADDR_START_L_V 0x00001FFFU +#define CPU_APM_REGION4_ADDR_START_L_S 0 +/** CPU_APM_REGION4_ADDR_START : R/W; bitpos: [24:13]; default: 0; + * Configures start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START 0x00000FFFU +#define CPU_APM_REGION4_ADDR_START_M (CPU_APM_REGION4_ADDR_START_V << CPU_APM_REGION4_ADDR_START_S) +#define CPU_APM_REGION4_ADDR_START_V 0x00000FFFU +#define CPU_APM_REGION4_ADDR_START_S 13 +/** CPU_APM_REGION4_ADDR_START_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START_H 0x0000007FU +#define CPU_APM_REGION4_ADDR_START_H_M (CPU_APM_REGION4_ADDR_START_H_V << CPU_APM_REGION4_ADDR_START_H_S) +#define CPU_APM_REGION4_ADDR_START_H_V 0x0000007FU +#define CPU_APM_REGION4_ADDR_START_H_S 25 + +/** CPU_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x38) +/** CPU_APM_REGION4_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191; + * Low 12 bit, end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END_L 0x00001FFFU +#define CPU_APM_REGION4_ADDR_END_L_M (CPU_APM_REGION4_ADDR_END_L_V << CPU_APM_REGION4_ADDR_END_L_S) +#define CPU_APM_REGION4_ADDR_END_L_V 0x00001FFFU +#define CPU_APM_REGION4_ADDR_END_L_S 0 +/** CPU_APM_REGION4_ADDR_END : R/W; bitpos: [24:13]; default: 4095; + * Configures end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END 0x00000FFFU +#define CPU_APM_REGION4_ADDR_END_M (CPU_APM_REGION4_ADDR_END_V << CPU_APM_REGION4_ADDR_END_S) +#define CPU_APM_REGION4_ADDR_END_V 0x00000FFFU +#define CPU_APM_REGION4_ADDR_END_S 13 +/** CPU_APM_REGION4_ADDR_END_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END_H 0x0000007FU +#define CPU_APM_REGION4_ADDR_END_H_M (CPU_APM_REGION4_ADDR_END_H_V << CPU_APM_REGION4_ADDR_END_H_S) +#define CPU_APM_REGION4_ADDR_END_H_V 0x0000007FU +#define CPU_APM_REGION4_ADDR_END_H_S 25 + +/** CPU_APM_REGION4_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_BASE + 0x3c) +/** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_X (BIT(0)) +#define CPU_APM_REGION4_R0_X_M (CPU_APM_REGION4_R0_X_V << CPU_APM_REGION4_R0_X_S) +#define CPU_APM_REGION4_R0_X_V 0x00000001U +#define CPU_APM_REGION4_R0_X_S 0 +/** CPU_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_W (BIT(1)) +#define CPU_APM_REGION4_R0_W_M (CPU_APM_REGION4_R0_W_V << CPU_APM_REGION4_R0_W_S) +#define CPU_APM_REGION4_R0_W_V 0x00000001U +#define CPU_APM_REGION4_R0_W_S 1 +/** CPU_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_R (BIT(2)) +#define CPU_APM_REGION4_R0_R_M (CPU_APM_REGION4_R0_R_V << CPU_APM_REGION4_R0_R_S) +#define CPU_APM_REGION4_R0_R_V 0x00000001U +#define CPU_APM_REGION4_R0_R_S 2 +/** CPU_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_X (BIT(4)) +#define CPU_APM_REGION4_R1_X_M (CPU_APM_REGION4_R1_X_V << CPU_APM_REGION4_R1_X_S) +#define CPU_APM_REGION4_R1_X_V 0x00000001U +#define CPU_APM_REGION4_R1_X_S 4 +/** CPU_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_W (BIT(5)) +#define CPU_APM_REGION4_R1_W_M (CPU_APM_REGION4_R1_W_V << CPU_APM_REGION4_R1_W_S) +#define CPU_APM_REGION4_R1_W_V 0x00000001U +#define CPU_APM_REGION4_R1_W_S 5 +/** CPU_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_R (BIT(6)) +#define CPU_APM_REGION4_R1_R_M (CPU_APM_REGION4_R1_R_V << CPU_APM_REGION4_R1_R_S) +#define CPU_APM_REGION4_R1_R_V 0x00000001U +#define CPU_APM_REGION4_R1_R_S 6 +/** CPU_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_X (BIT(8)) +#define CPU_APM_REGION4_R2_X_M (CPU_APM_REGION4_R2_X_V << CPU_APM_REGION4_R2_X_S) +#define CPU_APM_REGION4_R2_X_V 0x00000001U +#define CPU_APM_REGION4_R2_X_S 8 +/** CPU_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_W (BIT(9)) +#define CPU_APM_REGION4_R2_W_M (CPU_APM_REGION4_R2_W_V << CPU_APM_REGION4_R2_W_S) +#define CPU_APM_REGION4_R2_W_V 0x00000001U +#define CPU_APM_REGION4_R2_W_S 9 +/** CPU_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_R (BIT(10)) +#define CPU_APM_REGION4_R2_R_M (CPU_APM_REGION4_R2_R_V << CPU_APM_REGION4_R2_R_S) +#define CPU_APM_REGION4_R2_R_V 0x00000001U +#define CPU_APM_REGION4_R2_R_S 10 +/** CPU_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION4_LOCK (BIT(11)) +#define CPU_APM_REGION4_LOCK_M (CPU_APM_REGION4_LOCK_V << CPU_APM_REGION4_LOCK_S) +#define CPU_APM_REGION4_LOCK_V 0x00000001U +#define CPU_APM_REGION4_LOCK_S 11 + +/** CPU_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x40) +/** CPU_APM_REGION5_ADDR_START_L : HRO; bitpos: [12:0]; default: 0; + * Low 12 bit, start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START_L 0x00001FFFU +#define CPU_APM_REGION5_ADDR_START_L_M (CPU_APM_REGION5_ADDR_START_L_V << CPU_APM_REGION5_ADDR_START_L_S) +#define CPU_APM_REGION5_ADDR_START_L_V 0x00001FFFU +#define CPU_APM_REGION5_ADDR_START_L_S 0 +/** CPU_APM_REGION5_ADDR_START : R/W; bitpos: [24:13]; default: 0; + * Configures start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START 0x00000FFFU +#define CPU_APM_REGION5_ADDR_START_M (CPU_APM_REGION5_ADDR_START_V << CPU_APM_REGION5_ADDR_START_S) +#define CPU_APM_REGION5_ADDR_START_V 0x00000FFFU +#define CPU_APM_REGION5_ADDR_START_S 13 +/** CPU_APM_REGION5_ADDR_START_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START_H 0x0000007FU +#define CPU_APM_REGION5_ADDR_START_H_M (CPU_APM_REGION5_ADDR_START_H_V << CPU_APM_REGION5_ADDR_START_H_S) +#define CPU_APM_REGION5_ADDR_START_H_V 0x0000007FU +#define CPU_APM_REGION5_ADDR_START_H_S 25 + +/** CPU_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x44) +/** CPU_APM_REGION5_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191; + * Low 12 bit, end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END_L 0x00001FFFU +#define CPU_APM_REGION5_ADDR_END_L_M (CPU_APM_REGION5_ADDR_END_L_V << CPU_APM_REGION5_ADDR_END_L_S) +#define CPU_APM_REGION5_ADDR_END_L_V 0x00001FFFU +#define CPU_APM_REGION5_ADDR_END_L_S 0 +/** CPU_APM_REGION5_ADDR_END : R/W; bitpos: [24:13]; default: 4095; + * Configures end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END 0x00000FFFU +#define CPU_APM_REGION5_ADDR_END_M (CPU_APM_REGION5_ADDR_END_V << CPU_APM_REGION5_ADDR_END_S) +#define CPU_APM_REGION5_ADDR_END_V 0x00000FFFU +#define CPU_APM_REGION5_ADDR_END_S 13 +/** CPU_APM_REGION5_ADDR_END_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END_H 0x0000007FU +#define CPU_APM_REGION5_ADDR_END_H_M (CPU_APM_REGION5_ADDR_END_H_V << CPU_APM_REGION5_ADDR_END_H_S) +#define CPU_APM_REGION5_ADDR_END_H_V 0x0000007FU +#define CPU_APM_REGION5_ADDR_END_H_S 25 + +/** CPU_APM_REGION5_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_BASE + 0x48) +/** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_X (BIT(0)) +#define CPU_APM_REGION5_R0_X_M (CPU_APM_REGION5_R0_X_V << CPU_APM_REGION5_R0_X_S) +#define CPU_APM_REGION5_R0_X_V 0x00000001U +#define CPU_APM_REGION5_R0_X_S 0 +/** CPU_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_W (BIT(1)) +#define CPU_APM_REGION5_R0_W_M (CPU_APM_REGION5_R0_W_V << CPU_APM_REGION5_R0_W_S) +#define CPU_APM_REGION5_R0_W_V 0x00000001U +#define CPU_APM_REGION5_R0_W_S 1 +/** CPU_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_R (BIT(2)) +#define CPU_APM_REGION5_R0_R_M (CPU_APM_REGION5_R0_R_V << CPU_APM_REGION5_R0_R_S) +#define CPU_APM_REGION5_R0_R_V 0x00000001U +#define CPU_APM_REGION5_R0_R_S 2 +/** CPU_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_X (BIT(4)) +#define CPU_APM_REGION5_R1_X_M (CPU_APM_REGION5_R1_X_V << CPU_APM_REGION5_R1_X_S) +#define CPU_APM_REGION5_R1_X_V 0x00000001U +#define CPU_APM_REGION5_R1_X_S 4 +/** CPU_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_W (BIT(5)) +#define CPU_APM_REGION5_R1_W_M (CPU_APM_REGION5_R1_W_V << CPU_APM_REGION5_R1_W_S) +#define CPU_APM_REGION5_R1_W_V 0x00000001U +#define CPU_APM_REGION5_R1_W_S 5 +/** CPU_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_R (BIT(6)) +#define CPU_APM_REGION5_R1_R_M (CPU_APM_REGION5_R1_R_V << CPU_APM_REGION5_R1_R_S) +#define CPU_APM_REGION5_R1_R_V 0x00000001U +#define CPU_APM_REGION5_R1_R_S 6 +/** CPU_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_X (BIT(8)) +#define CPU_APM_REGION5_R2_X_M (CPU_APM_REGION5_R2_X_V << CPU_APM_REGION5_R2_X_S) +#define CPU_APM_REGION5_R2_X_V 0x00000001U +#define CPU_APM_REGION5_R2_X_S 8 +/** CPU_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_W (BIT(9)) +#define CPU_APM_REGION5_R2_W_M (CPU_APM_REGION5_R2_W_V << CPU_APM_REGION5_R2_W_S) +#define CPU_APM_REGION5_R2_W_V 0x00000001U +#define CPU_APM_REGION5_R2_W_S 9 +/** CPU_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_R (BIT(10)) +#define CPU_APM_REGION5_R2_R_M (CPU_APM_REGION5_R2_R_V << CPU_APM_REGION5_R2_R_S) +#define CPU_APM_REGION5_R2_R_V 0x00000001U +#define CPU_APM_REGION5_R2_R_S 10 +/** CPU_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION5_LOCK (BIT(11)) +#define CPU_APM_REGION5_LOCK_M (CPU_APM_REGION5_LOCK_V << CPU_APM_REGION5_LOCK_S) +#define CPU_APM_REGION5_LOCK_V 0x00000001U +#define CPU_APM_REGION5_LOCK_S 11 + +/** CPU_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4c) +/** CPU_APM_REGION6_ADDR_START_L : HRO; bitpos: [12:0]; default: 0; + * Low 12 bit, start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START_L 0x00001FFFU +#define CPU_APM_REGION6_ADDR_START_L_M (CPU_APM_REGION6_ADDR_START_L_V << CPU_APM_REGION6_ADDR_START_L_S) +#define CPU_APM_REGION6_ADDR_START_L_V 0x00001FFFU +#define CPU_APM_REGION6_ADDR_START_L_S 0 +/** CPU_APM_REGION6_ADDR_START : R/W; bitpos: [24:13]; default: 0; + * Configures start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START 0x00000FFFU +#define CPU_APM_REGION6_ADDR_START_M (CPU_APM_REGION6_ADDR_START_V << CPU_APM_REGION6_ADDR_START_S) +#define CPU_APM_REGION6_ADDR_START_V 0x00000FFFU +#define CPU_APM_REGION6_ADDR_START_S 13 +/** CPU_APM_REGION6_ADDR_START_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START_H 0x0000007FU +#define CPU_APM_REGION6_ADDR_START_H_M (CPU_APM_REGION6_ADDR_START_H_V << CPU_APM_REGION6_ADDR_START_H_S) +#define CPU_APM_REGION6_ADDR_START_H_V 0x0000007FU +#define CPU_APM_REGION6_ADDR_START_H_S 25 + +/** CPU_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x50) +/** CPU_APM_REGION6_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191; + * Low 12 bit, end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END_L 0x00001FFFU +#define CPU_APM_REGION6_ADDR_END_L_M (CPU_APM_REGION6_ADDR_END_L_V << CPU_APM_REGION6_ADDR_END_L_S) +#define CPU_APM_REGION6_ADDR_END_L_V 0x00001FFFU +#define CPU_APM_REGION6_ADDR_END_L_S 0 +/** CPU_APM_REGION6_ADDR_END : R/W; bitpos: [24:13]; default: 4095; + * Configures end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END 0x00000FFFU +#define CPU_APM_REGION6_ADDR_END_M (CPU_APM_REGION6_ADDR_END_V << CPU_APM_REGION6_ADDR_END_S) +#define CPU_APM_REGION6_ADDR_END_V 0x00000FFFU +#define CPU_APM_REGION6_ADDR_END_S 13 +/** CPU_APM_REGION6_ADDR_END_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END_H 0x0000007FU +#define CPU_APM_REGION6_ADDR_END_H_M (CPU_APM_REGION6_ADDR_END_H_V << CPU_APM_REGION6_ADDR_END_H_S) +#define CPU_APM_REGION6_ADDR_END_H_V 0x0000007FU +#define CPU_APM_REGION6_ADDR_END_H_S 25 + +/** CPU_APM_REGION6_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_BASE + 0x54) +/** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_X (BIT(0)) +#define CPU_APM_REGION6_R0_X_M (CPU_APM_REGION6_R0_X_V << CPU_APM_REGION6_R0_X_S) +#define CPU_APM_REGION6_R0_X_V 0x00000001U +#define CPU_APM_REGION6_R0_X_S 0 +/** CPU_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_W (BIT(1)) +#define CPU_APM_REGION6_R0_W_M (CPU_APM_REGION6_R0_W_V << CPU_APM_REGION6_R0_W_S) +#define CPU_APM_REGION6_R0_W_V 0x00000001U +#define CPU_APM_REGION6_R0_W_S 1 +/** CPU_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_R (BIT(2)) +#define CPU_APM_REGION6_R0_R_M (CPU_APM_REGION6_R0_R_V << CPU_APM_REGION6_R0_R_S) +#define CPU_APM_REGION6_R0_R_V 0x00000001U +#define CPU_APM_REGION6_R0_R_S 2 +/** CPU_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_X (BIT(4)) +#define CPU_APM_REGION6_R1_X_M (CPU_APM_REGION6_R1_X_V << CPU_APM_REGION6_R1_X_S) +#define CPU_APM_REGION6_R1_X_V 0x00000001U +#define CPU_APM_REGION6_R1_X_S 4 +/** CPU_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_W (BIT(5)) +#define CPU_APM_REGION6_R1_W_M (CPU_APM_REGION6_R1_W_V << CPU_APM_REGION6_R1_W_S) +#define CPU_APM_REGION6_R1_W_V 0x00000001U +#define CPU_APM_REGION6_R1_W_S 5 +/** CPU_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_R (BIT(6)) +#define CPU_APM_REGION6_R1_R_M (CPU_APM_REGION6_R1_R_V << CPU_APM_REGION6_R1_R_S) +#define CPU_APM_REGION6_R1_R_V 0x00000001U +#define CPU_APM_REGION6_R1_R_S 6 +/** CPU_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_X (BIT(8)) +#define CPU_APM_REGION6_R2_X_M (CPU_APM_REGION6_R2_X_V << CPU_APM_REGION6_R2_X_S) +#define CPU_APM_REGION6_R2_X_V 0x00000001U +#define CPU_APM_REGION6_R2_X_S 8 +/** CPU_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_W (BIT(9)) +#define CPU_APM_REGION6_R2_W_M (CPU_APM_REGION6_R2_W_V << CPU_APM_REGION6_R2_W_S) +#define CPU_APM_REGION6_R2_W_V 0x00000001U +#define CPU_APM_REGION6_R2_W_S 9 +/** CPU_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_R (BIT(10)) +#define CPU_APM_REGION6_R2_R_M (CPU_APM_REGION6_R2_R_V << CPU_APM_REGION6_R2_R_S) +#define CPU_APM_REGION6_R2_R_V 0x00000001U +#define CPU_APM_REGION6_R2_R_S 10 +/** CPU_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION6_LOCK (BIT(11)) +#define CPU_APM_REGION6_LOCK_M (CPU_APM_REGION6_LOCK_V << CPU_APM_REGION6_LOCK_S) +#define CPU_APM_REGION6_LOCK_V 0x00000001U +#define CPU_APM_REGION6_LOCK_S 11 + +/** CPU_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x58) +/** CPU_APM_REGION7_ADDR_START_L : HRO; bitpos: [12:0]; default: 0; + * Low 12 bit, start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START_L 0x00001FFFU +#define CPU_APM_REGION7_ADDR_START_L_M (CPU_APM_REGION7_ADDR_START_L_V << CPU_APM_REGION7_ADDR_START_L_S) +#define CPU_APM_REGION7_ADDR_START_L_V 0x00001FFFU +#define CPU_APM_REGION7_ADDR_START_L_S 0 +/** CPU_APM_REGION7_ADDR_START : R/W; bitpos: [24:13]; default: 0; + * Configures start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START 0x00000FFFU +#define CPU_APM_REGION7_ADDR_START_M (CPU_APM_REGION7_ADDR_START_V << CPU_APM_REGION7_ADDR_START_S) +#define CPU_APM_REGION7_ADDR_START_V 0x00000FFFU +#define CPU_APM_REGION7_ADDR_START_S 13 +/** CPU_APM_REGION7_ADDR_START_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START_H 0x0000007FU +#define CPU_APM_REGION7_ADDR_START_H_M (CPU_APM_REGION7_ADDR_START_H_V << CPU_APM_REGION7_ADDR_START_H_S) +#define CPU_APM_REGION7_ADDR_START_H_V 0x0000007FU +#define CPU_APM_REGION7_ADDR_START_H_S 25 + +/** CPU_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x5c) +/** CPU_APM_REGION7_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191; + * Low 12 bit, end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END_L 0x00001FFFU +#define CPU_APM_REGION7_ADDR_END_L_M (CPU_APM_REGION7_ADDR_END_L_V << CPU_APM_REGION7_ADDR_END_L_S) +#define CPU_APM_REGION7_ADDR_END_L_V 0x00001FFFU +#define CPU_APM_REGION7_ADDR_END_L_S 0 +/** CPU_APM_REGION7_ADDR_END : R/W; bitpos: [24:13]; default: 4095; + * Configures end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END 0x00000FFFU +#define CPU_APM_REGION7_ADDR_END_M (CPU_APM_REGION7_ADDR_END_V << CPU_APM_REGION7_ADDR_END_S) +#define CPU_APM_REGION7_ADDR_END_V 0x00000FFFU +#define CPU_APM_REGION7_ADDR_END_S 13 +/** CPU_APM_REGION7_ADDR_END_H : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END_H 0x0000007FU +#define CPU_APM_REGION7_ADDR_END_H_M (CPU_APM_REGION7_ADDR_END_H_V << CPU_APM_REGION7_ADDR_END_H_S) +#define CPU_APM_REGION7_ADDR_END_H_V 0x0000007FU +#define CPU_APM_REGION7_ADDR_END_H_S 25 + +/** CPU_APM_REGION7_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_BASE + 0x60) +/** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_X (BIT(0)) +#define CPU_APM_REGION7_R0_X_M (CPU_APM_REGION7_R0_X_V << CPU_APM_REGION7_R0_X_S) +#define CPU_APM_REGION7_R0_X_V 0x00000001U +#define CPU_APM_REGION7_R0_X_S 0 +/** CPU_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_W (BIT(1)) +#define CPU_APM_REGION7_R0_W_M (CPU_APM_REGION7_R0_W_V << CPU_APM_REGION7_R0_W_S) +#define CPU_APM_REGION7_R0_W_V 0x00000001U +#define CPU_APM_REGION7_R0_W_S 1 +/** CPU_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_R (BIT(2)) +#define CPU_APM_REGION7_R0_R_M (CPU_APM_REGION7_R0_R_V << CPU_APM_REGION7_R0_R_S) +#define CPU_APM_REGION7_R0_R_V 0x00000001U +#define CPU_APM_REGION7_R0_R_S 2 +/** CPU_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_X (BIT(4)) +#define CPU_APM_REGION7_R1_X_M (CPU_APM_REGION7_R1_X_V << CPU_APM_REGION7_R1_X_S) +#define CPU_APM_REGION7_R1_X_V 0x00000001U +#define CPU_APM_REGION7_R1_X_S 4 +/** CPU_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_W (BIT(5)) +#define CPU_APM_REGION7_R1_W_M (CPU_APM_REGION7_R1_W_V << CPU_APM_REGION7_R1_W_S) +#define CPU_APM_REGION7_R1_W_V 0x00000001U +#define CPU_APM_REGION7_R1_W_S 5 +/** CPU_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_R (BIT(6)) +#define CPU_APM_REGION7_R1_R_M (CPU_APM_REGION7_R1_R_V << CPU_APM_REGION7_R1_R_S) +#define CPU_APM_REGION7_R1_R_V 0x00000001U +#define CPU_APM_REGION7_R1_R_S 6 +/** CPU_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_X (BIT(8)) +#define CPU_APM_REGION7_R2_X_M (CPU_APM_REGION7_R2_X_V << CPU_APM_REGION7_R2_X_S) +#define CPU_APM_REGION7_R2_X_V 0x00000001U +#define CPU_APM_REGION7_R2_X_S 8 +/** CPU_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_W (BIT(9)) +#define CPU_APM_REGION7_R2_W_M (CPU_APM_REGION7_R2_W_V << CPU_APM_REGION7_R2_W_S) +#define CPU_APM_REGION7_R2_W_V 0x00000001U +#define CPU_APM_REGION7_R2_W_S 9 +/** CPU_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_R (BIT(10)) +#define CPU_APM_REGION7_R2_R_M (CPU_APM_REGION7_R2_R_V << CPU_APM_REGION7_R2_R_S) +#define CPU_APM_REGION7_R2_R_V 0x00000001U +#define CPU_APM_REGION7_R2_R_S 10 +/** CPU_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION7_LOCK (BIT(11)) +#define CPU_APM_REGION7_LOCK_M (CPU_APM_REGION7_LOCK_V << CPU_APM_REGION7_LOCK_S) +#define CPU_APM_REGION7_LOCK_V 0x00000001U +#define CPU_APM_REGION7_LOCK_S 11 + +/** CPU_APM_FUNC_CTRL_REG register + * APM function control register + */ +#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_BASE + 0xc4) +/** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define CPU_APM_M0_FUNC_EN (BIT(0)) +#define CPU_APM_M0_FUNC_EN_M (CPU_APM_M0_FUNC_EN_V << CPU_APM_M0_FUNC_EN_S) +#define CPU_APM_M0_FUNC_EN_V 0x00000001U +#define CPU_APM_M0_FUNC_EN_S 0 +/** CPU_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define CPU_APM_M1_FUNC_EN (BIT(1)) +#define CPU_APM_M1_FUNC_EN_M (CPU_APM_M1_FUNC_EN_V << CPU_APM_M1_FUNC_EN_S) +#define CPU_APM_M1_FUNC_EN_V 0x00000001U +#define CPU_APM_M1_FUNC_EN_S 1 +/** CPU_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ +#define CPU_APM_M2_FUNC_EN (BIT(2)) +#define CPU_APM_M2_FUNC_EN_M (CPU_APM_M2_FUNC_EN_V << CPU_APM_M2_FUNC_EN_S) +#define CPU_APM_M2_FUNC_EN_V 0x00000001U +#define CPU_APM_M2_FUNC_EN_S 2 +/** CPU_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ +#define CPU_APM_M3_FUNC_EN (BIT(3)) +#define CPU_APM_M3_FUNC_EN_M (CPU_APM_M3_FUNC_EN_V << CPU_APM_M3_FUNC_EN_S) +#define CPU_APM_M3_FUNC_EN_V 0x00000001U +#define CPU_APM_M3_FUNC_EN_S 3 + +/** CPU_APM_M0_STATUS_REG register + * M0 status register + */ +#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_BASE + 0xc8) +/** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M0_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M0_EXCEPTION_STATUS_M (CPU_APM_M0_EXCEPTION_STATUS_V << CPU_APM_M0_EXCEPTION_STATUS_S) +#define CPU_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M0_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xcc) +/** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_M (CPU_APM_M0_EXCEPTION_STATUS_CLR_V << CPU_APM_M0_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xd0) +/** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M0_EXCEPTION_REGION_M (CPU_APM_M0_EXCEPTION_REGION_V << CPU_APM_M0_EXCEPTION_REGION_S) +#define CPU_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M0_EXCEPTION_REGION_S 0 +/** CPU_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M0_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M0_EXCEPTION_MODE_M (CPU_APM_M0_EXCEPTION_MODE_V << CPU_APM_M0_EXCEPTION_MODE_S) +#define CPU_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M0_EXCEPTION_MODE_S 16 +/** CPU_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M0_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M0_EXCEPTION_ID_M (CPU_APM_M0_EXCEPTION_ID_V << CPU_APM_M0_EXCEPTION_ID_S) +#define CPU_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M0_EXCEPTION_ID_S 18 + +/** CPU_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xd4) +/** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M0_EXCEPTION_ADDR_M (CPU_APM_M0_EXCEPTION_ADDR_V << CPU_APM_M0_EXCEPTION_ADDR_S) +#define CPU_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M0_EXCEPTION_ADDR_S 0 + +/** CPU_APM_M1_STATUS_REG register + * M1 status register + */ +#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_BASE + 0xd8) +/** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M1_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M1_EXCEPTION_STATUS_M (CPU_APM_M1_EXCEPTION_STATUS_V << CPU_APM_M1_EXCEPTION_STATUS_S) +#define CPU_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M1_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xdc) +/** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M1_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_M (CPU_APM_M1_EXCEPTION_STATUS_CLR_V << CPU_APM_M1_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xe0) +/** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M1_EXCEPTION_REGION_M (CPU_APM_M1_EXCEPTION_REGION_V << CPU_APM_M1_EXCEPTION_REGION_S) +#define CPU_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M1_EXCEPTION_REGION_S 0 +/** CPU_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M1_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M1_EXCEPTION_MODE_M (CPU_APM_M1_EXCEPTION_MODE_V << CPU_APM_M1_EXCEPTION_MODE_S) +#define CPU_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M1_EXCEPTION_MODE_S 16 +/** CPU_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M1_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M1_EXCEPTION_ID_M (CPU_APM_M1_EXCEPTION_ID_V << CPU_APM_M1_EXCEPTION_ID_S) +#define CPU_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M1_EXCEPTION_ID_S 18 + +/** CPU_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xe4) +/** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M1_EXCEPTION_ADDR_M (CPU_APM_M1_EXCEPTION_ADDR_V << CPU_APM_M1_EXCEPTION_ADDR_S) +#define CPU_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M1_EXCEPTION_ADDR_S 0 + +/** CPU_APM_M2_STATUS_REG register + * M2 status register + */ +#define CPU_APM_M2_STATUS_REG (DR_REG_CPU_APM_BASE + 0xe8) +/** CPU_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M2_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M2_EXCEPTION_STATUS_M (CPU_APM_M2_EXCEPTION_STATUS_V << CPU_APM_M2_EXCEPTION_STATUS_S) +#define CPU_APM_M2_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M2_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M2_STATUS_CLR_REG register + * M2 status clear register + */ +#define CPU_APM_M2_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xec) +/** CPU_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M2_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M2_EXCEPTION_STATUS_CLR_M (CPU_APM_M2_EXCEPTION_STATUS_CLR_V << CPU_APM_M2_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M2_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M2_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M2_EXCEPTION_INFO0_REG register + * M2 exception_info0 register + */ +#define CPU_APM_M2_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xf0) +/** CPU_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M2_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M2_EXCEPTION_REGION_M (CPU_APM_M2_EXCEPTION_REGION_V << CPU_APM_M2_EXCEPTION_REGION_S) +#define CPU_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M2_EXCEPTION_REGION_S 0 +/** CPU_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M2_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M2_EXCEPTION_MODE_M (CPU_APM_M2_EXCEPTION_MODE_V << CPU_APM_M2_EXCEPTION_MODE_S) +#define CPU_APM_M2_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M2_EXCEPTION_MODE_S 16 +/** CPU_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M2_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M2_EXCEPTION_ID_M (CPU_APM_M2_EXCEPTION_ID_V << CPU_APM_M2_EXCEPTION_ID_S) +#define CPU_APM_M2_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M2_EXCEPTION_ID_S 18 + +/** CPU_APM_M2_EXCEPTION_INFO1_REG register + * M2 exception_info1 register + */ +#define CPU_APM_M2_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xf4) +/** CPU_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M2_EXCEPTION_ADDR_M (CPU_APM_M2_EXCEPTION_ADDR_V << CPU_APM_M2_EXCEPTION_ADDR_S) +#define CPU_APM_M2_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M2_EXCEPTION_ADDR_S 0 + +/** CPU_APM_M3_STATUS_REG register + * M3 status register + */ +#define CPU_APM_M3_STATUS_REG (DR_REG_CPU_APM_BASE + 0xf8) +/** CPU_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M3_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M3_EXCEPTION_STATUS_M (CPU_APM_M3_EXCEPTION_STATUS_V << CPU_APM_M3_EXCEPTION_STATUS_S) +#define CPU_APM_M3_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M3_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M3_STATUS_CLR_REG register + * M3 status clear register + */ +#define CPU_APM_M3_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xfc) +/** CPU_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M3_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M3_EXCEPTION_STATUS_CLR_M (CPU_APM_M3_EXCEPTION_STATUS_CLR_V << CPU_APM_M3_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M3_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M3_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M3_EXCEPTION_INFO0_REG register + * M3 exception_info0 register + */ +#define CPU_APM_M3_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0x100) +/** CPU_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M3_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M3_EXCEPTION_REGION_M (CPU_APM_M3_EXCEPTION_REGION_V << CPU_APM_M3_EXCEPTION_REGION_S) +#define CPU_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M3_EXCEPTION_REGION_S 0 +/** CPU_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M3_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M3_EXCEPTION_MODE_M (CPU_APM_M3_EXCEPTION_MODE_V << CPU_APM_M3_EXCEPTION_MODE_S) +#define CPU_APM_M3_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M3_EXCEPTION_MODE_S 16 +/** CPU_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M3_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M3_EXCEPTION_ID_M (CPU_APM_M3_EXCEPTION_ID_V << CPU_APM_M3_EXCEPTION_ID_S) +#define CPU_APM_M3_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M3_EXCEPTION_ID_S 18 + +/** CPU_APM_M3_EXCEPTION_INFO1_REG register + * M3 exception_info1 register + */ +#define CPU_APM_M3_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0x104) +/** CPU_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M3_EXCEPTION_ADDR_M (CPU_APM_M3_EXCEPTION_ADDR_V << CPU_APM_M3_EXCEPTION_ADDR_S) +#define CPU_APM_M3_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M3_EXCEPTION_ADDR_S 0 + +/** CPU_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_BASE + 0x118) +/** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M0_APM_INT_EN (BIT(0)) +#define CPU_APM_M0_APM_INT_EN_M (CPU_APM_M0_APM_INT_EN_V << CPU_APM_M0_APM_INT_EN_S) +#define CPU_APM_M0_APM_INT_EN_V 0x00000001U +#define CPU_APM_M0_APM_INT_EN_S 0 +/** CPU_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M1_APM_INT_EN (BIT(1)) +#define CPU_APM_M1_APM_INT_EN_M (CPU_APM_M1_APM_INT_EN_V << CPU_APM_M1_APM_INT_EN_S) +#define CPU_APM_M1_APM_INT_EN_V 0x00000001U +#define CPU_APM_M1_APM_INT_EN_S 1 +/** CPU_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; + * Configures to enable APM M2 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M2_APM_INT_EN (BIT(2)) +#define CPU_APM_M2_APM_INT_EN_M (CPU_APM_M2_APM_INT_EN_V << CPU_APM_M2_APM_INT_EN_S) +#define CPU_APM_M2_APM_INT_EN_V 0x00000001U +#define CPU_APM_M2_APM_INT_EN_S 2 +/** CPU_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; + * Configures to enable APM M3 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M3_APM_INT_EN (BIT(3)) +#define CPU_APM_M3_APM_INT_EN_M (CPU_APM_M3_APM_INT_EN_V << CPU_APM_M3_APM_INT_EN_S) +#define CPU_APM_M3_APM_INT_EN_V 0x00000001U +#define CPU_APM_M3_APM_INT_EN_S 3 + +/** CPU_APM_CLOCK_GATE_REG register + * Clock gating register + */ +#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_BASE + 0x7f8) +/** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ +#define CPU_APM_CLK_EN (BIT(0)) +#define CPU_APM_CLK_EN_M (CPU_APM_CLK_EN_V << CPU_APM_CLK_EN_S) +#define CPU_APM_CLK_EN_V 0x00000001U +#define CPU_APM_CLK_EN_S 0 + +/** CPU_APM_DATE_REG register + * Version control register + */ +#define CPU_APM_DATE_REG (DR_REG_CPU_APM_BASE + 0x7fc) +/** CPU_APM_DATE : R/W; bitpos: [27:0]; default: 38814240; + * Version control register. + */ +#define CPU_APM_DATE 0x0FFFFFFFU +#define CPU_APM_DATE_M (CPU_APM_DATE_V << CPU_APM_DATE_S) +#define CPU_APM_DATE_V 0x0FFFFFFFU +#define CPU_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_struct.h b/components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_struct.h new file mode 100644 index 0000000000..6107075fe9 --- /dev/null +++ b/components/soc/esp32h4/register/hw_ver_mp/soc/cpu_apm_struct.h @@ -0,0 +1,578 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** region_filter_en : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ + uint32_t region_filter_en:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} cpu_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of regionn_addr_start register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_start_l : HRO; bitpos: [12:0]; default: 0; + * Low 12 bit, start address of region n. + */ + uint32_t regionn_addr_start_l:13; + /** regionn_addr_start : R/W; bitpos: [24:13]; default: 0; + * Configures start address of region n. + */ + uint32_t regionn_addr_start:12; + /** regionn_addr_start_h : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, start address of region n. + */ + uint32_t regionn_addr_start_h:7; + }; + uint32_t val; +} cpu_apm_regionn_addr_start_reg_t; + +/** Type of regionn_addr_end register + * Region address register + */ +typedef union { + struct { + /** regionn_addr_end_l : HRO; bitpos: [12:0]; default: 8191; + * Low 12 bit, end address of region n. + */ + uint32_t regionn_addr_end_l:13; + /** regionn_addr_end : R/W; bitpos: [24:13]; default: 4095; + * Configures end address of region n. + */ + uint32_t regionn_addr_end:12; + /** regionn_addr_end_h : HRO; bitpos: [31:25]; default: 1; + * High 13 bit, end address of region n. + */ + uint32_t regionn_addr_end_h:7; + }; + uint32_t val; +} cpu_apm_regionn_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of regionn_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** regionn_r0_x : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_x:1; + /** regionn_r0_w : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_w:1; + /** regionn_r0_r : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region n. + */ + uint32_t regionn_r0_r:1; + uint32_t reserved_3:1; + /** regionn_r1_x : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_x:1; + /** regionn_r1_w : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_w:1; + /** regionn_r1_r : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region n. + */ + uint32_t regionn_r1_r:1; + uint32_t reserved_7:1; + /** regionn_r2_x : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_x:1; + /** regionn_r2_w : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_w:1; + /** regionn_r2_r : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region n. + */ + uint32_t regionn_r2_r:1; + /** regionn_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t regionn_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} cpu_apm_regionn_attr_reg_t; + + +/** Group: function control register */ +/** Type of func_ctrl register + * APM function control register + */ +typedef union { + struct { + /** m0_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t m0_func_en:1; + /** m1_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t m1_func_en:1; + /** m2_func_en : R/W; bitpos: [2]; default: 1; + * PMS M2 function enable + */ + uint32_t m2_func_en:1; + /** m3_func_en : R/W; bitpos: [3]; default: 1; + * PMS M3 function enable + */ + uint32_t m3_func_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} cpu_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of m0_status register + * M0 status register + */ +typedef union { + struct { + /** m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m0_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m0_exception_region:16; + /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m0_exception_mode:2; + /** m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m0_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of m1_status register + * M1 status register + */ +typedef union { + struct { + /** m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** m1_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m1_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m1_exception_region:16; + /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m1_exception_mode:2; + /** m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m1_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m1_exception_info1_reg_t; + + +/** Group: M2 status register */ +/** Type of m2_status register + * M2 status register + */ +typedef union { + struct { + /** m2_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m2_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m2_status_reg_t; + + +/** Group: M2 status clear register */ +/** Type of m2_status_clr register + * M2 status clear register + */ +typedef union { + struct { + /** m2_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m2_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m2_status_clr_reg_t; + + +/** Group: M2 exception_info0 register */ +/** Type of m2_exception_info0 register + * M2 exception_info0 register + */ +typedef union { + struct { + /** m2_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m2_exception_region:16; + /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m2_exception_mode:2; + /** m2_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m2_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m2_exception_info0_reg_t; + + +/** Group: M2 exception_info1 register */ +/** Type of m2_exception_info1 register + * M2 exception_info1 register + */ +typedef union { + struct { + /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m2_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m2_exception_info1_reg_t; + + +/** Group: M3 status register */ +/** Type of m3_status register + * M3 status register + */ +typedef union { + struct { + /** m3_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t m3_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m3_status_reg_t; + + +/** Group: M3 status clear register */ +/** Type of m3_status_clr register + * M3 status clear register + */ +typedef union { + struct { + /** m3_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t m3_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m3_status_clr_reg_t; + + +/** Group: M3 exception_info0 register */ +/** Type of m3_exception_info0 register + * M3 exception_info0 register + */ +typedef union { + struct { + /** m3_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t m3_exception_region:16; + /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t m3_exception_mode:2; + /** m3_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t m3_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m3_exception_info0_reg_t; + + +/** Group: M3 exception_info1 register */ +/** Type of m3_exception_info1 register + * M3 exception_info1 register + */ +typedef union { + struct { + /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t m3_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m3_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m0_apm_int_en:1; + /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m1_apm_int_en:1; + /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; + * Configures to enable APM M2 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m2_apm_int_en:1; + /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; + * Configures to enable APM M3 interrupt. + * 0: disable + * 1: enable + */ + uint32_t m3_apm_int_en:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} cpu_apm_int_en_reg_t; + + +/** Group: Clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 38814240; + * Version control register. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cpu_apm_date_reg_t; + + +typedef struct { + volatile cpu_apm_region_filter_en_reg_t region_filter_en; + volatile cpu_apm_regionn_addr_start_reg_t region0_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region0_addr_end; + volatile cpu_apm_regionn_attr_reg_t region0_attr; + volatile cpu_apm_regionn_addr_start_reg_t region1_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region1_addr_end; + volatile cpu_apm_regionn_attr_reg_t region1_attr; + volatile cpu_apm_regionn_addr_start_reg_t region2_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region2_addr_end; + volatile cpu_apm_regionn_attr_reg_t region2_attr; + volatile cpu_apm_regionn_addr_start_reg_t region3_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region3_addr_end; + volatile cpu_apm_regionn_attr_reg_t region3_attr; + volatile cpu_apm_regionn_addr_start_reg_t region4_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region4_addr_end; + volatile cpu_apm_regionn_attr_reg_t region4_attr; + volatile cpu_apm_regionn_addr_start_reg_t region5_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region5_addr_end; + volatile cpu_apm_regionn_attr_reg_t region5_attr; + volatile cpu_apm_regionn_addr_start_reg_t region6_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region6_addr_end; + volatile cpu_apm_regionn_attr_reg_t region6_attr; + volatile cpu_apm_regionn_addr_start_reg_t region7_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t region7_addr_end; + volatile cpu_apm_regionn_attr_reg_t region7_attr; + uint32_t reserved_064[24]; + volatile cpu_apm_func_ctrl_reg_t func_ctrl; + volatile cpu_apm_m0_status_reg_t m0_status; + volatile cpu_apm_m0_status_clr_reg_t m0_status_clr; + volatile cpu_apm_m0_exception_info0_reg_t m0_exception_info0; + volatile cpu_apm_m0_exception_info1_reg_t m0_exception_info1; + volatile cpu_apm_m1_status_reg_t m1_status; + volatile cpu_apm_m1_status_clr_reg_t m1_status_clr; + volatile cpu_apm_m1_exception_info0_reg_t m1_exception_info0; + volatile cpu_apm_m1_exception_info1_reg_t m1_exception_info1; + volatile cpu_apm_m2_status_reg_t m2_status; + volatile cpu_apm_m2_status_clr_reg_t m2_status_clr; + volatile cpu_apm_m2_exception_info0_reg_t m2_exception_info0; + volatile cpu_apm_m2_exception_info1_reg_t m2_exception_info1; + volatile cpu_apm_m3_status_reg_t m3_status; + volatile cpu_apm_m3_status_clr_reg_t m3_status_clr; + volatile cpu_apm_m3_exception_info0_reg_t m3_exception_info0; + volatile cpu_apm_m3_exception_info1_reg_t m3_exception_info1; + uint32_t reserved_108[4]; + volatile cpu_apm_int_en_reg_t int_en; + uint32_t reserved_11c[439]; + volatile cpu_apm_clock_gate_reg_t clock_gate; + volatile cpu_apm_date_reg_t date; +} cpu_apm_dev_t; + +extern cpu_apm_dev_t CPU_APM; + +#ifndef __cplusplus +_Static_assert(sizeof(cpu_apm_dev_t) == 0x800, "Invalid size of cpu_apm_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h b/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h new file mode 100644 index 0000000000..3271b064d8 --- /dev/null +++ b/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_reg.h @@ -0,0 +1,2045 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register + * WIFI_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) +/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register + * WIFI_MAC_NMI mapping register + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) +/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register + * WIFI_PWR_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) +/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register + * WIFI_BB_INTR mapping register + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) +/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S) +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register + * BT_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +/** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register + * BT_BB_INTR mapping register + */ +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +/** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_BB_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_M (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S) +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register + * BT_BB_NMI mapping register + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 +/** INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register + * LP_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) +/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_COEX_INTR_MAP_REG register + * COEX_INTR mapping register + */ +#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +/** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_COEX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_COEX_INTR_MAP_M (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S) +#define INTERRUPT_CORE0_COEX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_COEX_INTR_MAP_S 0 +/** INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register + * BLE_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register + * BLE_SEC_INTR mapping register + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S) +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register + * I2C_MST_INTR mapping register + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) +/** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register + * ZB_MAC_INTR mapping register + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S) +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG register + * MODEM_APB_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +/** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_MODEM_APB_TIMEOUT_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG register + * BT_MAC_INT1 mapping register + */ +#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +/** INTERRUPT_CORE0_BT_MAC_INT1_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BT_MAC_INT1_MAP 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_M (INTERRUPT_CORE0_BT_MAC_INT1_MAP_V << INTERRUPT_CORE0_BT_MAC_INT1_MAP_S) +#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BT_MAC_INT1_MAP_S 0 +/** INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_MAC_INT1_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_PMU_INTR_MAP_REG register + * PMU_INTR mapping register + */ +#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) +/** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PMU_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PMU_INTR_MAP_M (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S) +#define INTERRUPT_CORE0_PMU_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PMU_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register + * EFUSE_INTR mapping register + */ +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +/** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_EFUSE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_M (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S) +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register + * LP_RTC_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG register + * LP_RTC_BLE_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +/** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_RTC_BLE_TIMER_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register + * LP_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) +/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_TOUCH_INTR_MAP_REG register + * TOUCH_INTR mapping register + */ +#define INTERRUPT_CORE0_TOUCH_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +/** INTERRUPT_CORE0_TOUCH_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TOUCH_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TOUCH_INTR_MAP_M (INTERRUPT_CORE0_TOUCH_INTR_MAP_V << INTERRUPT_CORE0_TOUCH_INTR_MAP_S) +#define INTERRUPT_CORE0_TOUCH_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TOUCH_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TOUCH_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HUK_INTR_MAP_REG register + * HUK_INTR mapping register + */ +#define INTERRUPT_CORE0_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +/** INTERRUPT_CORE0_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HUK_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HUK_INTR_MAP_M (INTERRUPT_CORE0_HUK_INTR_MAP_V << INTERRUPT_CORE0_HUK_INTR_MAP_S) +#define INTERRUPT_CORE0_HUK_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HUK_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HUK_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_REG register + * LP_PERI_PMS_INTR mapping register + */ +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +/** INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_M (INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_S) +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_PERI_PMS_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_PERI_PMS_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_PERI_PMS_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_PERI_PMS_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register + * CPU_INTR_FROM_CPU_0 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register + * CPU_INTR_FROM_CPU_1 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register + * CPU_INTR_FROM_CPU_2 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register + * CPU_INTR_FROM_CPU_3 mapping register + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG register + * BUS_MONITOR_INTR mapping register + */ +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_M (INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S) +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG register + * CORE0_TRACE_INTR mapping register + */ +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_M (INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_S) +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG register + * CORE1_TRACE_INTR mapping register + */ +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_M (INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_V << INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_S) +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register + * CACHE_INTR mapping register + */ +#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CACHE_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INTR_MAP_M (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S) +#define INTERRUPT_CORE0_CACHE_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CACHE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register + * CPU_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register + * GPIO_INTERRUPT_PRO mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG register + * GPIO_INTERRUPT_2 mapping register + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +/** INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_MAP_S 0 +/** INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_M (INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPIO_INTERRUPT_2_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register + * PAU_INTR mapping register + */ +#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PAU_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PAU_INTR_MAP_M (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S) +#define INTERRUPT_CORE0_PAU_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PAU_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register + * HP_PERI_TIMEOUT_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register + * HP_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register + * HP_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register + * HP_APM_M2_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register + * HP_APM_M3_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) +/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register + * HP_APM_M4_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) +/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG register + * HP_MEM_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) +/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG register + * HP_MEM_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG register + * HP_MEM_APM_M2_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG register + * HP_MEM_APM_M3_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register + * CPU_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register + * CPU_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG register + * CPU_APM_M2_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG register + * CPU_APM_M3_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_REG register + * HP_PERI_PMS_INTR mapping register + */ +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +/** INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_S) +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_PERI_PMS_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_PERI_PMS_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_PERI_PMS_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_PERI_PMS_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_REG register + * MODEM_PERI_PMS_INTR mapping register + */ +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +/** INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_M (INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_S) +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_MAP_S 0 +/** INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_MODEM_PERI_PMS_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_REG register + * CPU_PERI_PMS_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +/** INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_PERI_PMS_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_PERI_PMS_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_PERI_PMS_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_PERI_PMS_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register + * MSPI_INTR mapping register + */ +#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +/** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_MSPI_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_MSPI_INTR_MAP_M (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S) +#define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0 +/** INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_I2S_INTR_MAP_REG register + * I2S_INTR mapping register + */ +#define INTERRUPT_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +/** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2S_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2S_INTR_MAP_M (INTERRUPT_CORE0_I2S_INTR_MAP_V << INTERRUPT_CORE0_I2S_INTR_MAP_S) +#define INTERRUPT_CORE0_I2S_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2S_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2S_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register + * UHCI0_INTR mapping register + */ +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UHCI0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register + * UART0_INTR mapping register + */ +#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UART0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART0_INTR_MAP_M (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S) +#define INTERRUPT_CORE0_UART0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register + * UART1_INTR mapping register + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S) +#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register + * LEDC_INTR mapping register + */ +#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +/** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_LEDC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INTR_MAP_M (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S) +#define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register + * CAN0_INTR mapping register + */ +#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +/** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CAN0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN0_INTR_MAP_M (INTERRUPT_CORE0_CAN0_INTR_MAP_V << INTERRUPT_CORE0_CAN0_INTR_MAP_S) +#define INTERRUPT_CORE0_CAN0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CAN0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CAN0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG register + * CAN0_TIMER_INTR mapping register + */ +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_M (INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_V << INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_S) +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register + * USB_SERIAL_JTAG_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_M (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S 0 +/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register + * RMT_INTR mapping register + */ +#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_RMT_INTR_MAP_M (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S) +#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_RMT_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register + * I2C_EXT0_INTR mapping register + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG register + * I2C_EXT1_INTR mapping register + */ +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +/** INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S) +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2C_EXT1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register + * TG0_T0_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register + * TG0_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register + * TG1_T0_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register + * TG1_WDT_INTR mapping register + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c) +/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S) +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register + * SYSTIMER_TARGET0_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register + * SYSTIMER_TARGET1_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register + * SYSTIMER_TARGET2_INTR mapping register + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register + * APB_ADC_INTR mapping register + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c) +/** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S) +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_PWM0_INTR_MAP_REG register + * PWM0_INTR mapping register + */ +#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +/** INTERRUPT_CORE0_PWM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PWM0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PWM0_INTR_MAP_M (INTERRUPT_CORE0_PWM0_INTR_MAP_V << INTERRUPT_CORE0_PWM0_INTR_MAP_S) +#define INTERRUPT_CORE0_PWM0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PWM0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PWM0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_PWM1_INTR_MAP_REG register + * PWM1_INTR mapping register + */ +#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +/** INTERRUPT_CORE0_PWM1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PWM1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PWM1_INTR_MAP_M (INTERRUPT_CORE0_PWM1_INTR_MAP_V << INTERRUPT_CORE0_PWM1_INTR_MAP_S) +#define INTERRUPT_CORE0_PWM1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PWM1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PWM1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_PCNT_INTR_MAP_REG register + * PCNT_INTR mapping register + */ +#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +/** INTERRUPT_CORE0_PCNT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PCNT_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PCNT_INTR_MAP_M (INTERRUPT_CORE0_PCNT_INTR_MAP_V << INTERRUPT_CORE0_PCNT_INTR_MAP_S) +#define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PCNT_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG register + * PARL_IO_TX_INTR mapping register + */ +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c) +/** INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S) +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PARL_IO_TX_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG register + * PARL_IO_RX_INTR mapping register + */ +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +/** INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_M (INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S) +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PARL_IO_RX_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG register + * USB_OTG11_INTR mapping register + */ +#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +/** INTERRUPT_CORE0_USB_OTG11_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG11_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG11_INTR_MAP_S) +#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_USB_OTG11_INTR_MAP_S 0 +/** INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_USB_OTG11_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG register + * ASRC_CHNL0_INTR mapping register + */ +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_M (INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_V << INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_S) +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG register + * ASRC_CHNL1_INTR mapping register + */ +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c) +/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_M (INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_V << INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_S) +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG register + * ZERO_DET_INTR mapping register + */ +#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_M (INTERRUPT_CORE0_ZERO_DET_INTR_MAP_V << INTERRUPT_CORE0_ZERO_DET_INTR_MAP_S) +#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register + * DMA_IN_CH0_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register + * DMA_IN_CH1_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register + * DMA_IN_CH2_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c) +/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG register + * DMA_IN_CH3_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +/** INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH3_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG register + * DMA_IN_CH4_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +/** INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH4_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register + * DMA_OUT_CH0_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register + * DMA_OUT_CH1_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c) +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register + * DMA_OUT_CH2_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG register + * DMA_OUT_CH3_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +/** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH3_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG register + * DMA_OUT_CH4_INTR mapping register + */ +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +/** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_S) +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH4_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register + * GPSPI2_INTR mapping register + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c) +/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S) +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG register + * GPSPI3_INTR mapping register + */ +#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) +/** INTERRUPT_CORE0_GPSPI3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_GPSPI3_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_M (INTERRUPT_CORE0_GPSPI3_INTR_MAP_V << INTERRUPT_CORE0_GPSPI3_INTR_MAP_S) +#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_GPSPI3_INTR_MAP_S 0 +/** INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPSPI3_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_AES_INTR_MAP_REG register + * AES_INTR mapping register + */ +#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_AES_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_AES_INTR_MAP_M (INTERRUPT_CORE0_AES_INTR_MAP_V << INTERRUPT_CORE0_AES_INTR_MAP_S) +#define INTERRUPT_CORE0_AES_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_AES_INTR_MAP_S 0 +/** INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_AES_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register + * SHA_INTR mapping register + */ +#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178) +/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SHA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SHA_INTR_MAP_M (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S) +#define INTERRUPT_CORE0_SHA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SHA_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register + * ECC_INTR mapping register + */ +#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c) +/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ECC_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECC_INTR_MAP_M (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S) +#define INTERRUPT_CORE0_ECC_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register + * ECDSA_INTR mapping register + */ +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180) +/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_ECDSA_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S) +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_KM_INTR_MAP_REG register + * KM_INTR mapping register + */ +#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184) +/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_KM_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_KM_INTR_MAP_M (INTERRUPT_CORE0_KM_INTR_MAP_V << INTERRUPT_CORE0_KM_INTR_MAP_S) +#define INTERRUPT_CORE0_KM_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_KM_INTR_MAP_S 0 +/** INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_KM_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register + * Status register for interrupt sources 0 ~ 31 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188) +/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. + * Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_0_M (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S) +#define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_0_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register + * Status register for interrupt sources 32 ~ 63 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c) +/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 32 ~ + * 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_1_M (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S) +#define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_1_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register + * Status register for interrupt sources 64 ~ 95 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190) +/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 64 ~ + * 95. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_2_M (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S) +#define INTERRUPT_CORE0_INT_STATUS_2_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_STATUS_2_S 0 + +/** INTERRUPT_CORE0_INT_STATUS_REG_3_REG register + * Status register for interrupt sources 96 ~ 97 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194) +/** INTERRUPT_CORE0_INT_STATUS_3 : RO; bitpos: [1:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 96 ~ + * 97. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_3 0x00000003U +#define INTERRUPT_CORE0_INT_STATUS_3_M (INTERRUPT_CORE0_INT_STATUS_3_V << INTERRUPT_CORE0_INT_STATUS_3_S) +#define INTERRUPT_CORE0_INT_STATUS_3_V 0x00000003U +#define INTERRUPT_CORE0_INT_STATUS_3_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG register + * PASS_IN_SEC status register for interrupt sources 0 ~ 31 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG register + * PASS_IN_SEC status register for interrupt sources 32 ~ 63 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG register + * PASS_IN_SEC status register for interrupt sources 64 ~ 95 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_3_REG register + * PASS_IN_SEC status register for interrupt sources 96 ~ 97 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3 : RO; bitpos: [1:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources with + * interrupt-index-range 96 ~ 97. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3 0x00000003U +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3_V 0x00000003U +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_3_S 0 + +/** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register + * reserved + */ +#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8) +/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0; + * reserved + */ +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC 0x0000003FU +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_M (INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V << INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S) +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V 0x0000003FU +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S 0 + +/** INTERRUPT_CORE0_SECURE_STATUS_REG register + * reserved + */ +#define INTERRUPT_CORE0_SECURE_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac) +/** INTERRUPT_CORE0_INT_SECURE_STATUS : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define INTERRUPT_CORE0_INT_SECURE_STATUS 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SECURE_STATUS_M (INTERRUPT_CORE0_INT_SECURE_STATUS_V << INTERRUPT_CORE0_INT_SECURE_STATUS_S) +#define INTERRUPT_CORE0_INT_SECURE_STATUS_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SECURE_STATUS_S 0 + +/** INTERRUPT_CORE0_CLOCK_GATE_REG register + * Interrupt clock gating configure register + */ +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0) +/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0; + * Interrupt clock gating configure register + */ +#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_REG_CLK_EN_M (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S) +#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U +#define INTERRUPT_CORE0_REG_CLK_EN_S 0 + +/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register + * Version control register + */ +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc) +/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 38813760; + * Version control register + */ +#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_DATE_M (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S) +#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0x0FFFFFFFU +#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_struct.h b/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_struct.h new file mode 100644 index 0000000000..b8a2b7dc0f --- /dev/null +++ b/components/soc/esp32h4/register/hw_ver_mp/soc/interrupt_matrix_struct.h @@ -0,0 +1,2189 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration Registers */ +/** Type of wifi_mac_intr_map register + * WIFI_MAC_INTR mapping register + */ +typedef union { + struct { + /** wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_mac_intr_map:6; + uint32_t reserved_6:2; + /** wifi_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t wifi_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_wifi_mac_intr_map_reg_t; + +/** Type of wifi_mac_nmi_map register + * WIFI_MAC_NMI mapping register + */ +typedef union { + struct { + /** wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_mac_nmi_map:6; + uint32_t reserved_6:2; + /** wifi_mac_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t wifi_mac_nmi_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_wifi_mac_nmi_map_reg_t; + +/** Type of wifi_pwr_intr_map register + * WIFI_PWR_INTR mapping register + */ +typedef union { + struct { + /** wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_pwr_intr_map:6; + uint32_t reserved_6:2; + /** wifi_pwr_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t wifi_pwr_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_wifi_pwr_intr_map_reg_t; + +/** Type of wifi_bb_intr_map register + * WIFI_BB_INTR mapping register + */ +typedef union { + struct { + /** wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t wifi_bb_intr_map:6; + uint32_t reserved_6:2; + /** wifi_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t wifi_bb_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_wifi_bb_intr_map_reg_t; + +/** Type of bt_mac_intr_map register + * BT_MAC_INTR mapping register + */ +typedef union { + struct { + /** bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_mac_intr_map:6; + uint32_t reserved_6:2; + /** bt_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t bt_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_bt_mac_intr_map_reg_t; + +/** Type of bt_bb_intr_map register + * BT_BB_INTR mapping register + */ +typedef union { + struct { + /** bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_bb_intr_map:6; + uint32_t reserved_6:2; + /** bt_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t bt_bb_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_bt_bb_intr_map_reg_t; + +/** Type of bt_bb_nmi_map register + * BT_BB_NMI mapping register + */ +typedef union { + struct { + /** bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_bb_nmi_map:6; + uint32_t reserved_6:2; + /** bt_bb_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t bt_bb_nmi_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_bt_bb_nmi_map_reg_t; + +/** Type of lp_timer_intr_map register + * LP_TIMER_INTR mapping register + */ +typedef union { + struct { + /** lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_timer_intr_map:6; + uint32_t reserved_6:2; + /** lp_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_lp_timer_intr_map_reg_t; + +/** Type of coex_intr_map register + * COEX_INTR mapping register + */ +typedef union { + struct { + /** coex_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t coex_intr_map:6; + uint32_t reserved_6:2; + /** coex_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t coex_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_coex_intr_map_reg_t; + +/** Type of ble_timer_intr_map register + * BLE_TIMER_INTR mapping register + */ +typedef union { + struct { + /** ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ble_timer_intr_map:6; + uint32_t reserved_6:2; + /** ble_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ble_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_ble_timer_intr_map_reg_t; + +/** Type of ble_sec_intr_map register + * BLE_SEC_INTR mapping register + */ +typedef union { + struct { + /** ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ble_sec_intr_map:6; + uint32_t reserved_6:2; + /** ble_sec_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ble_sec_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_ble_sec_intr_map_reg_t; + +/** Type of i2c_mst_intr_map register + * I2C_MST_INTR mapping register + */ +typedef union { + struct { + /** i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2c_mst_intr_map:6; + uint32_t reserved_6:2; + /** i2c_mst_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t i2c_mst_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_i2c_mst_intr_map_reg_t; + +/** Type of zb_mac_intr_map register + * ZB_MAC_INTR mapping register + */ +typedef union { + struct { + /** zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t zb_mac_intr_map:6; + uint32_t reserved_6:2; + /** zb_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t zb_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_zb_mac_intr_map_reg_t; + +/** Type of modem_apb_timeout_intr_map register + * MODEM_APB_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** modem_apb_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t modem_apb_timeout_intr_map:6; + uint32_t reserved_6:2; + /** modem_apb_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t modem_apb_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_modem_apb_timeout_intr_map_reg_t; + +/** Type of bt_mac_int1_map register + * BT_MAC_INT1 mapping register + */ +typedef union { + struct { + /** bt_mac_int1_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bt_mac_int1_map:6; + uint32_t reserved_6:2; + /** bt_mac_int1_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t bt_mac_int1_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_bt_mac_int1_map_reg_t; + +/** Type of pmu_intr_map register + * PMU_INTR mapping register + */ +typedef union { + struct { + /** pmu_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pmu_intr_map:6; + uint32_t reserved_6:2; + /** pmu_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t pmu_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_pmu_intr_map_reg_t; + +/** Type of efuse_intr_map register + * EFUSE_INTR mapping register + */ +typedef union { + struct { + /** efuse_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t efuse_intr_map:6; + uint32_t reserved_6:2; + /** efuse_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t efuse_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_efuse_intr_map_reg_t; + +/** Type of lp_rtc_timer_intr_map register + * LP_RTC_TIMER_INTR mapping register + */ +typedef union { + struct { + /** lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_rtc_timer_intr_map:6; + uint32_t reserved_6:2; + /** lp_rtc_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_rtc_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_lp_rtc_timer_intr_map_reg_t; + +/** Type of lp_rtc_ble_timer_intr_map register + * LP_RTC_BLE_TIMER_INTR mapping register + */ +typedef union { + struct { + /** lp_rtc_ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_rtc_ble_timer_intr_map:6; + uint32_t reserved_6:2; + /** lp_rtc_ble_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_rtc_ble_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_lp_rtc_ble_timer_intr_map_reg_t; + +/** Type of lp_wdt_intr_map register + * LP_WDT_INTR mapping register + */ +typedef union { + struct { + /** lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_wdt_intr_map:6; + uint32_t reserved_6:2; + /** lp_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_lp_wdt_intr_map_reg_t; + +/** Type of touch_intr_map register + * TOUCH_INTR mapping register + */ +typedef union { + struct { + /** touch_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t touch_intr_map:6; + uint32_t reserved_6:2; + /** touch_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t touch_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_touch_intr_map_reg_t; + +/** Type of huk_intr_map register + * HUK_INTR mapping register + */ +typedef union { + struct { + /** huk_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t huk_intr_map:6; + uint32_t reserved_6:2; + /** huk_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t huk_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_huk_intr_map_reg_t; + +/** Type of lp_peri_pms_intr_map register + * LP_PERI_PMS_INTR mapping register + */ +typedef union { + struct { + /** lp_peri_pms_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t lp_peri_pms_intr_map:6; + uint32_t reserved_6:2; + /** lp_peri_pms_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t lp_peri_pms_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_lp_peri_pms_intr_map_reg_t; + +/** Type of cpu_intr_from_cpu_0_map register + * CPU_INTR_FROM_CPU_0 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_0_map:6; + uint32_t reserved_6:2; + /** cpu_intr_from_cpu_0_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_intr_from_cpu_0_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_0_map_reg_t; + +/** Type of cpu_intr_from_cpu_1_map register + * CPU_INTR_FROM_CPU_1 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_1_map:6; + uint32_t reserved_6:2; + /** cpu_intr_from_cpu_1_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_intr_from_cpu_1_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_1_map_reg_t; + +/** Type of cpu_intr_from_cpu_2_map register + * CPU_INTR_FROM_CPU_2 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_2_map:6; + uint32_t reserved_6:2; + /** cpu_intr_from_cpu_2_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_intr_from_cpu_2_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_2_map_reg_t; + +/** Type of cpu_intr_from_cpu_3_map register + * CPU_INTR_FROM_CPU_3 mapping register + */ +typedef union { + struct { + /** cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_intr_from_cpu_3_map:6; + uint32_t reserved_6:2; + /** cpu_intr_from_cpu_3_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_intr_from_cpu_3_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_intr_from_cpu_3_map_reg_t; + +/** Type of bus_monitor_intr_map register + * BUS_MONITOR_INTR mapping register + */ +typedef union { + struct { + /** bus_monitor_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t bus_monitor_intr_map:6; + uint32_t reserved_6:2; + /** bus_monitor_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t bus_monitor_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_bus_monitor_intr_map_reg_t; + +/** Type of core0_trace_intr_map register + * CORE0_TRACE_INTR mapping register + */ +typedef union { + struct { + /** core0_trace_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core0_trace_intr_map:6; + uint32_t reserved_6:2; + /** core0_trace_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_trace_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_core0_trace_intr_map_reg_t; + +/** Type of core1_trace_intr_map register + * CORE1_TRACE_INTR mapping register + */ +typedef union { + struct { + /** core1_trace_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core1_trace_intr_map:6; + uint32_t reserved_6:2; + /** core1_trace_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core1_trace_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_core1_trace_intr_map_reg_t; + +/** Type of cache_intr_map register + * CACHE_INTR mapping register + */ +typedef union { + struct { + /** cache_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cache_intr_map:6; + uint32_t reserved_6:2; + /** cache_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cache_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cache_intr_map_reg_t; + +/** Type of cpu_peri_timeout_intr_map register + * CPU_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** cpu_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_peri_timeout_intr_map_reg_t; + +/** Type of gpio_interrupt_pro_map register + * GPIO_INTERRUPT_PRO mapping register + */ +typedef union { + struct { + /** gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_pro_map:6; + uint32_t reserved_6:2; + /** gpio_interrupt_pro_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t gpio_interrupt_pro_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_gpio_interrupt_pro_map_reg_t; + +/** Type of gpio_interrupt_2_map register + * GPIO_INTERRUPT_2 mapping register + */ +typedef union { + struct { + /** gpio_interrupt_2_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpio_interrupt_2_map:6; + uint32_t reserved_6:2; + /** gpio_interrupt_2_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t gpio_interrupt_2_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_gpio_interrupt_2_map_reg_t; + +/** Type of pau_intr_map register + * PAU_INTR mapping register + */ +typedef union { + struct { + /** pau_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pau_intr_map:6; + uint32_t reserved_6:2; + /** pau_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t pau_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_pau_intr_map_reg_t; + +/** Type of hp_peri_timeout_intr_map register + * HP_PERI_TIMEOUT_INTR mapping register + */ +typedef union { + struct { + /** hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** hp_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_peri_timeout_intr_map_reg_t; + +/** Type of hp_apm_m0_intr_map register + * HP_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** hp_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_apm_m0_intr_map_reg_t; + +/** Type of hp_apm_m1_intr_map register + * HP_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m1_intr_map:6; + uint32_t reserved_6:2; + /** hp_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_apm_m1_intr_map_reg_t; + +/** Type of hp_apm_m2_intr_map register + * HP_APM_M2_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m2_intr_map:6; + uint32_t reserved_6:2; + /** hp_apm_m2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m2_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_apm_m2_intr_map_reg_t; + +/** Type of hp_apm_m3_intr_map register + * HP_APM_M3_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m3_intr_map:6; + uint32_t reserved_6:2; + /** hp_apm_m3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m3_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_apm_m3_intr_map_reg_t; + +/** Type of hp_apm_m4_intr_map register + * HP_APM_M4_INTR mapping register + */ +typedef union { + struct { + /** hp_apm_m4_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_apm_m4_intr_map:6; + uint32_t reserved_6:2; + /** hp_apm_m4_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_apm_m4_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_apm_m4_intr_map_reg_t; + +/** Type of hp_mem_apm_m0_intr_map register + * HP_MEM_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** hp_mem_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_mem_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** hp_mem_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_mem_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_mem_apm_m0_intr_map_reg_t; + +/** Type of hp_mem_apm_m1_intr_map register + * HP_MEM_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** hp_mem_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_mem_apm_m1_intr_map:6; + uint32_t reserved_6:2; + /** hp_mem_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_mem_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_mem_apm_m1_intr_map_reg_t; + +/** Type of hp_mem_apm_m2_intr_map register + * HP_MEM_APM_M2_INTR mapping register + */ +typedef union { + struct { + /** hp_mem_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_mem_apm_m2_intr_map:6; + uint32_t reserved_6:2; + /** hp_mem_apm_m2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_mem_apm_m2_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_mem_apm_m2_intr_map_reg_t; + +/** Type of hp_mem_apm_m3_intr_map register + * HP_MEM_APM_M3_INTR mapping register + */ +typedef union { + struct { + /** hp_mem_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_mem_apm_m3_intr_map:6; + uint32_t reserved_6:2; + /** hp_mem_apm_m3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_mem_apm_m3_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_mem_apm_m3_intr_map_reg_t; + +/** Type of cpu_apm_m0_intr_map register + * CPU_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** cpu_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** cpu_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m0_intr_map_reg_t; + +/** Type of cpu_apm_m1_intr_map register + * CPU_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** cpu_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_apm_m1_intr_map:6; + uint32_t reserved_6:2; + /** cpu_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m1_intr_map_reg_t; + +/** Type of cpu_apm_m2_intr_map register + * CPU_APM_M2_INTR mapping register + */ +typedef union { + struct { + /** cpu_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_apm_m2_intr_map:6; + uint32_t reserved_6:2; + /** cpu_apm_m2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_apm_m2_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m2_intr_map_reg_t; + +/** Type of cpu_apm_m3_intr_map register + * CPU_APM_M3_INTR mapping register + */ +typedef union { + struct { + /** cpu_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_apm_m3_intr_map:6; + uint32_t reserved_6:2; + /** cpu_apm_m3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_apm_m3_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m3_intr_map_reg_t; + +/** Type of hp_peri_pms_intr_map register + * HP_PERI_PMS_INTR mapping register + */ +typedef union { + struct { + /** hp_peri_pms_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t hp_peri_pms_intr_map:6; + uint32_t reserved_6:2; + /** hp_peri_pms_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t hp_peri_pms_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_hp_peri_pms_intr_map_reg_t; + +/** Type of modem_peri_pms_intr_map register + * MODEM_PERI_PMS_INTR mapping register + */ +typedef union { + struct { + /** modem_peri_pms_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t modem_peri_pms_intr_map:6; + uint32_t reserved_6:2; + /** modem_peri_pms_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t modem_peri_pms_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_modem_peri_pms_intr_map_reg_t; + +/** Type of cpu_peri_pms_intr_map register + * CPU_PERI_PMS_INTR mapping register + */ +typedef union { + struct { + /** cpu_peri_pms_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t cpu_peri_pms_intr_map:6; + uint32_t reserved_6:2; + /** cpu_peri_pms_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t cpu_peri_pms_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_peri_pms_intr_map_reg_t; + +/** Type of mspi_intr_map register + * MSPI_INTR mapping register + */ +typedef union { + struct { + /** mspi_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t mspi_intr_map:6; + uint32_t reserved_6:2; + /** mspi_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t mspi_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_mspi_intr_map_reg_t; + +/** Type of i2s_intr_map register + * I2S_INTR mapping register + */ +typedef union { + struct { + /** i2s_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2s_intr_map:6; + uint32_t reserved_6:2; + /** i2s_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t i2s_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_i2s_intr_map_reg_t; + +/** Type of uhci0_intr_map register + * UHCI0_INTR mapping register + */ +typedef union { + struct { + /** uhci0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uhci0_intr_map:6; + uint32_t reserved_6:2; + /** uhci0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t uhci0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_uhci0_intr_map_reg_t; + +/** Type of uart0_intr_map register + * UART0_INTR mapping register + */ +typedef union { + struct { + /** uart0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uart0_intr_map:6; + uint32_t reserved_6:2; + /** uart0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t uart0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_uart0_intr_map_reg_t; + +/** Type of uart1_intr_map register + * UART1_INTR mapping register + */ +typedef union { + struct { + /** uart1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t uart1_intr_map:6; + uint32_t reserved_6:2; + /** uart1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t uart1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_uart1_intr_map_reg_t; + +/** Type of ledc_intr_map register + * LEDC_INTR mapping register + */ +typedef union { + struct { + /** ledc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ledc_intr_map:6; + uint32_t reserved_6:2; + /** ledc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ledc_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_ledc_intr_map_reg_t; + +/** Type of can0_intr_map register + * CAN0_INTR mapping register + */ +typedef union { + struct { + /** can0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t can0_intr_map:6; + uint32_t reserved_6:2; + /** can0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t can0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_can0_intr_map_reg_t; + +/** Type of can0_timer_intr_map register + * CAN0_TIMER_INTR mapping register + */ +typedef union { + struct { + /** can0_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t can0_timer_intr_map:6; + uint32_t reserved_6:2; + /** can0_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t can0_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_can0_timer_intr_map_reg_t; + +/** Type of usb_serial_jtag_intr_map register + * USB_SERIAL_JTAG_INTR mapping register + */ +typedef union { + struct { + /** usb_serial_jtag_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_serial_jtag_intr_map:6; + uint32_t reserved_6:2; + /** usb_serial_jtag_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t usb_serial_jtag_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_usb_serial_jtag_intr_map_reg_t; + +/** Type of rmt_intr_map register + * RMT_INTR mapping register + */ +typedef union { + struct { + /** rmt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t rmt_intr_map:6; + uint32_t reserved_6:2; + /** rmt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t rmt_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_rmt_intr_map_reg_t; + +/** Type of i2c_ext0_intr_map register + * I2C_EXT0_INTR mapping register + */ +typedef union { + struct { + /** i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2c_ext0_intr_map:6; + uint32_t reserved_6:2; + /** i2c_ext0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t i2c_ext0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_i2c_ext0_intr_map_reg_t; + +/** Type of i2c_ext1_intr_map register + * I2C_EXT1_INTR mapping register + */ +typedef union { + struct { + /** i2c_ext1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t i2c_ext1_intr_map:6; + uint32_t reserved_6:2; + /** i2c_ext1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t i2c_ext1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_i2c_ext1_intr_map_reg_t; + +/** Type of tg0_t0_intr_map register + * TG0_T0_INTR mapping register + */ +typedef union { + struct { + /** tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_t0_intr_map:6; + uint32_t reserved_6:2; + /** tg0_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t tg0_t0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_tg0_t0_intr_map_reg_t; + +/** Type of tg0_wdt_intr_map register + * TG0_WDT_INTR mapping register + */ +typedef union { + struct { + /** tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg0_wdt_intr_map:6; + uint32_t reserved_6:2; + /** tg0_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t tg0_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_tg0_wdt_intr_map_reg_t; + +/** Type of tg1_t0_intr_map register + * TG1_T0_INTR mapping register + */ +typedef union { + struct { + /** tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_t0_intr_map:6; + uint32_t reserved_6:2; + /** tg1_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t tg1_t0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_tg1_t0_intr_map_reg_t; + +/** Type of tg1_wdt_intr_map register + * TG1_WDT_INTR mapping register + */ +typedef union { + struct { + /** tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t tg1_wdt_intr_map:6; + uint32_t reserved_6:2; + /** tg1_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t tg1_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_tg1_wdt_intr_map_reg_t; + +/** Type of systimer_target0_intr_map register + * SYSTIMER_TARGET0_INTR mapping register + */ +typedef union { + struct { + /** systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target0_intr_map:6; + uint32_t reserved_6:2; + /** systimer_target0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t systimer_target0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_systimer_target0_intr_map_reg_t; + +/** Type of systimer_target1_intr_map register + * SYSTIMER_TARGET1_INTR mapping register + */ +typedef union { + struct { + /** systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target1_intr_map:6; + uint32_t reserved_6:2; + /** systimer_target1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t systimer_target1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_systimer_target1_intr_map_reg_t; + +/** Type of systimer_target2_intr_map register + * SYSTIMER_TARGET2_INTR mapping register + */ +typedef union { + struct { + /** systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t systimer_target2_intr_map:6; + uint32_t reserved_6:2; + /** systimer_target2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t systimer_target2_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_systimer_target2_intr_map_reg_t; + +/** Type of apb_adc_intr_map register + * APB_ADC_INTR mapping register + */ +typedef union { + struct { + /** apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t apb_adc_intr_map:6; + uint32_t reserved_6:2; + /** apb_adc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t apb_adc_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_apb_adc_intr_map_reg_t; + +/** Type of pwm0_intr_map register + * PWM0_INTR mapping register + */ +typedef union { + struct { + /** pwm0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pwm0_intr_map:6; + uint32_t reserved_6:2; + /** pwm0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t pwm0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_pwm0_intr_map_reg_t; + +/** Type of pwm1_intr_map register + * PWM1_INTR mapping register + */ +typedef union { + struct { + /** pwm1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pwm1_intr_map:6; + uint32_t reserved_6:2; + /** pwm1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t pwm1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_pwm1_intr_map_reg_t; + +/** Type of pcnt_intr_map register + * PCNT_INTR mapping register + */ +typedef union { + struct { + /** pcnt_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t pcnt_intr_map:6; + uint32_t reserved_6:2; + /** pcnt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t pcnt_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_pcnt_intr_map_reg_t; + +/** Type of parl_io_tx_intr_map register + * PARL_IO_TX_INTR mapping register + */ +typedef union { + struct { + /** parl_io_tx_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t parl_io_tx_intr_map:6; + uint32_t reserved_6:2; + /** parl_io_tx_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t parl_io_tx_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_parl_io_tx_intr_map_reg_t; + +/** Type of parl_io_rx_intr_map register + * PARL_IO_RX_INTR mapping register + */ +typedef union { + struct { + /** parl_io_rx_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t parl_io_rx_intr_map:6; + uint32_t reserved_6:2; + /** parl_io_rx_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t parl_io_rx_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_parl_io_rx_intr_map_reg_t; + +/** Type of usb_otg11_intr_map register + * USB_OTG11_INTR mapping register + */ +typedef union { + struct { + /** usb_otg11_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t usb_otg11_intr_map:6; + uint32_t reserved_6:2; + /** usb_otg11_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t usb_otg11_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_usb_otg11_intr_map_reg_t; + +/** Type of asrc_chnl0_intr_map register + * ASRC_CHNL0_INTR mapping register + */ +typedef union { + struct { + /** asrc_chnl0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t asrc_chnl0_intr_map:6; + uint32_t reserved_6:2; + /** asrc_chnl0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t asrc_chnl0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_asrc_chnl0_intr_map_reg_t; + +/** Type of asrc_chnl1_intr_map register + * ASRC_CHNL1_INTR mapping register + */ +typedef union { + struct { + /** asrc_chnl1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t asrc_chnl1_intr_map:6; + uint32_t reserved_6:2; + /** asrc_chnl1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t asrc_chnl1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_asrc_chnl1_intr_map_reg_t; + +/** Type of zero_det_intr_map register + * ZERO_DET_INTR mapping register + */ +typedef union { + struct { + /** zero_det_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t zero_det_intr_map:6; + uint32_t reserved_6:2; + /** zero_det_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t zero_det_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_zero_det_intr_map_reg_t; + +/** Type of dma_in_ch0_intr_map register + * DMA_IN_CH0_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch0_intr_map:6; + uint32_t reserved_6:2; + /** dma_in_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_in_ch0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_in_ch0_intr_map_reg_t; + +/** Type of dma_in_ch1_intr_map register + * DMA_IN_CH1_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch1_intr_map:6; + uint32_t reserved_6:2; + /** dma_in_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_in_ch1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_in_ch1_intr_map_reg_t; + +/** Type of dma_in_ch2_intr_map register + * DMA_IN_CH2_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch2_intr_map:6; + uint32_t reserved_6:2; + /** dma_in_ch2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_in_ch2_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_in_ch2_intr_map_reg_t; + +/** Type of dma_in_ch3_intr_map register + * DMA_IN_CH3_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch3_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch3_intr_map:6; + uint32_t reserved_6:2; + /** dma_in_ch3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_in_ch3_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_in_ch3_intr_map_reg_t; + +/** Type of dma_in_ch4_intr_map register + * DMA_IN_CH4_INTR mapping register + */ +typedef union { + struct { + /** dma_in_ch4_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_in_ch4_intr_map:6; + uint32_t reserved_6:2; + /** dma_in_ch4_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_in_ch4_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_in_ch4_intr_map_reg_t; + +/** Type of dma_out_ch0_intr_map register + * DMA_OUT_CH0_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch0_intr_map:6; + uint32_t reserved_6:2; + /** dma_out_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_out_ch0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_out_ch0_intr_map_reg_t; + +/** Type of dma_out_ch1_intr_map register + * DMA_OUT_CH1_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch1_intr_map:6; + uint32_t reserved_6:2; + /** dma_out_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_out_ch1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_out_ch1_intr_map_reg_t; + +/** Type of dma_out_ch2_intr_map register + * DMA_OUT_CH2_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch2_intr_map:6; + uint32_t reserved_6:2; + /** dma_out_ch2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_out_ch2_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_out_ch2_intr_map_reg_t; + +/** Type of dma_out_ch3_intr_map register + * DMA_OUT_CH3_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch3_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch3_intr_map:6; + uint32_t reserved_6:2; + /** dma_out_ch3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_out_ch3_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_out_ch3_intr_map_reg_t; + +/** Type of dma_out_ch4_intr_map register + * DMA_OUT_CH4_INTR mapping register + */ +typedef union { + struct { + /** dma_out_ch4_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t dma_out_ch4_intr_map:6; + uint32_t reserved_6:2; + /** dma_out_ch4_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t dma_out_ch4_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_dma_out_ch4_intr_map_reg_t; + +/** Type of gpspi2_intr_map register + * GPSPI2_INTR mapping register + */ +typedef union { + struct { + /** gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpspi2_intr_map:6; + uint32_t reserved_6:2; + /** gpspi2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t gpspi2_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_gpspi2_intr_map_reg_t; + +/** Type of gpspi3_intr_map register + * GPSPI3_INTR mapping register + */ +typedef union { + struct { + /** gpspi3_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t gpspi3_intr_map:6; + uint32_t reserved_6:2; + /** gpspi3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t gpspi3_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_gpspi3_intr_map_reg_t; + +/** Type of aes_intr_map register + * AES_INTR mapping register + */ +typedef union { + struct { + /** aes_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t aes_intr_map:6; + uint32_t reserved_6:2; + /** aes_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t aes_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_aes_intr_map_reg_t; + +/** Type of sha_intr_map register + * SHA_INTR mapping register + */ +typedef union { + struct { + /** sha_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t sha_intr_map:6; + uint32_t reserved_6:2; + /** sha_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t sha_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_sha_intr_map_reg_t; + +/** Type of ecc_intr_map register + * ECC_INTR mapping register + */ +typedef union { + struct { + /** ecc_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ecc_intr_map:6; + uint32_t reserved_6:2; + /** ecc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ecc_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_ecc_intr_map_reg_t; + +/** Type of ecdsa_intr_map register + * ECDSA_INTR mapping register + */ +typedef union { + struct { + /** ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t ecdsa_intr_map:6; + uint32_t reserved_6:2; + /** ecdsa_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t ecdsa_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_ecdsa_intr_map_reg_t; + +/** Type of km_intr_map register + * KM_INTR mapping register + */ +typedef union { + struct { + /** km_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t km_intr_map:6; + uint32_t reserved_6:2; + /** km_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t km_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_km_intr_map_reg_t; + +/** Type of sig_idx_assert_in_sec register + * reserved + */ +typedef union { + struct { + /** int_sig_idx_assert_in_sec : R/W; bitpos: [5:0]; default: 0; + * reserved + */ + uint32_t int_sig_idx_assert_in_sec:6; + uint32_t reserved_6:26; + }; + uint32_t val; +} interrupt_core0_sig_idx_assert_in_sec_reg_t; + +/** Type of clock_gate register + * Interrupt clock gating configure register + */ +typedef union { + struct { + /** reg_clk_en : R/W; bitpos: [0]; default: 0; + * Interrupt clock gating configure register + */ + uint32_t reg_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} interrupt_core0_clock_gate_reg_t; + + +/** Group: Status Registers */ +/** Type of int_status_reg_0 register + * Status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** int_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. + * Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_0:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_0_reg_t; + +/** Type of int_status_reg_1 register + * Status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** int_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 32 ~ + * 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_1:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_1_reg_t; + +/** Type of int_status_reg_2 register + * Status register for interrupt sources 64 ~ 95 + */ +typedef union { + struct { + /** int_status_2 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 64 ~ + * 95. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_2:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_2_reg_t; + +/** Type of int_status_reg_3 register + * Status register for interrupt sources 96 ~ 97 + */ +typedef union { + struct { + /** int_status_3 : RO; bitpos: [1:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 96 ~ + * 97. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t int_status_3:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} interrupt_core0_int_status_reg_3_reg_t; + +/** Type of src_pass_in_sec_status_0 register + * PASS_IN_SEC status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** int_src_pass_in_sec_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t int_src_pass_in_sec_status_0:32; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_0_reg_t; + +/** Type of src_pass_in_sec_status_1 register + * PASS_IN_SEC status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** int_src_pass_in_sec_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t int_src_pass_in_sec_status_1:32; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_1_reg_t; + +/** Type of src_pass_in_sec_status_2 register + * PASS_IN_SEC status register for interrupt sources 64 ~ 95 + */ +typedef union { + struct { + /** int_src_pass_in_sec_status_2 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t int_src_pass_in_sec_status_2:32; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_2_reg_t; + +/** Type of src_pass_in_sec_status_3 register + * PASS_IN_SEC status register for interrupt sources 96 ~ 97 + */ +typedef union { + struct { + /** int_src_pass_in_sec_status_3 : RO; bitpos: [1:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources with + * interrupt-index-range 96 ~ 97. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t int_src_pass_in_sec_status_3:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_3_reg_t; + +/** Type of secure_status register + * reserved + */ +typedef union { + struct { + /** int_secure_status : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t int_secure_status:32; + }; + uint32_t val; +} interrupt_core0_secure_status_reg_t; + + +/** Group: Version Register */ +/** Type of interrupt_date register + * Version control register + */ +typedef union { + struct { + /** interrupt_date : R/W; bitpos: [27:0]; default: 38813760; + * Version control register + */ + uint32_t interrupt_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} interrupt_core0_interrupt_date_reg_t; + + +typedef struct { + volatile interrupt_core0_wifi_mac_intr_map_reg_t wifi_mac_intr_map; + volatile interrupt_core0_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map; + volatile interrupt_core0_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map; + volatile interrupt_core0_wifi_bb_intr_map_reg_t wifi_bb_intr_map; + volatile interrupt_core0_bt_mac_intr_map_reg_t bt_mac_intr_map; + volatile interrupt_core0_bt_bb_intr_map_reg_t bt_bb_intr_map; + volatile interrupt_core0_bt_bb_nmi_map_reg_t bt_bb_nmi_map; + volatile interrupt_core0_lp_timer_intr_map_reg_t lp_timer_intr_map; + volatile interrupt_core0_coex_intr_map_reg_t coex_intr_map; + volatile interrupt_core0_ble_timer_intr_map_reg_t ble_timer_intr_map; + volatile interrupt_core0_ble_sec_intr_map_reg_t ble_sec_intr_map; + volatile interrupt_core0_i2c_mst_intr_map_reg_t i2c_mst_intr_map; + volatile interrupt_core0_zb_mac_intr_map_reg_t zb_mac_intr_map; + volatile interrupt_core0_modem_apb_timeout_intr_map_reg_t modem_apb_timeout_intr_map; + volatile interrupt_core0_bt_mac_int1_map_reg_t bt_mac_int1_map; + volatile interrupt_core0_pmu_intr_map_reg_t pmu_intr_map; + volatile interrupt_core0_efuse_intr_map_reg_t efuse_intr_map; + volatile interrupt_core0_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map; + volatile interrupt_core0_lp_rtc_ble_timer_intr_map_reg_t lp_rtc_ble_timer_intr_map; + volatile interrupt_core0_lp_wdt_intr_map_reg_t lp_wdt_intr_map; + volatile interrupt_core0_touch_intr_map_reg_t touch_intr_map; + volatile interrupt_core0_huk_intr_map_reg_t huk_intr_map; + volatile interrupt_core0_lp_peri_pms_intr_map_reg_t lp_peri_pms_intr_map; + volatile interrupt_core0_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map; + volatile interrupt_core0_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map; + volatile interrupt_core0_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map; + volatile interrupt_core0_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map; + volatile interrupt_core0_bus_monitor_intr_map_reg_t bus_monitor_intr_map; + volatile interrupt_core0_core0_trace_intr_map_reg_t core0_trace_intr_map; + volatile interrupt_core0_core1_trace_intr_map_reg_t core1_trace_intr_map; + volatile interrupt_core0_cache_intr_map_reg_t cache_intr_map; + volatile interrupt_core0_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map; + volatile interrupt_core0_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map; + volatile interrupt_core0_gpio_interrupt_2_map_reg_t gpio_interrupt_2_map; + volatile interrupt_core0_pau_intr_map_reg_t pau_intr_map; + volatile interrupt_core0_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map; + volatile interrupt_core0_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map; + volatile interrupt_core0_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map; + volatile interrupt_core0_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map; + volatile interrupt_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; + volatile interrupt_core0_hp_apm_m4_intr_map_reg_t hp_apm_m4_intr_map; + volatile interrupt_core0_hp_mem_apm_m0_intr_map_reg_t hp_mem_apm_m0_intr_map; + volatile interrupt_core0_hp_mem_apm_m1_intr_map_reg_t hp_mem_apm_m1_intr_map; + volatile interrupt_core0_hp_mem_apm_m2_intr_map_reg_t hp_mem_apm_m2_intr_map; + volatile interrupt_core0_hp_mem_apm_m3_intr_map_reg_t hp_mem_apm_m3_intr_map; + volatile interrupt_core0_cpu_apm_m0_intr_map_reg_t cpu_apm_m0_intr_map; + volatile interrupt_core0_cpu_apm_m1_intr_map_reg_t cpu_apm_m1_intr_map; + volatile interrupt_core0_cpu_apm_m2_intr_map_reg_t cpu_apm_m2_intr_map; + volatile interrupt_core0_cpu_apm_m3_intr_map_reg_t cpu_apm_m3_intr_map; + volatile interrupt_core0_hp_peri_pms_intr_map_reg_t hp_peri_pms_intr_map; + volatile interrupt_core0_modem_peri_pms_intr_map_reg_t modem_peri_pms_intr_map; + volatile interrupt_core0_cpu_peri_pms_intr_map_reg_t cpu_peri_pms_intr_map; + volatile interrupt_core0_mspi_intr_map_reg_t mspi_intr_map; + volatile interrupt_core0_i2s_intr_map_reg_t i2s_intr_map; + volatile interrupt_core0_uhci0_intr_map_reg_t uhci0_intr_map; + volatile interrupt_core0_uart0_intr_map_reg_t uart0_intr_map; + volatile interrupt_core0_uart1_intr_map_reg_t uart1_intr_map; + volatile interrupt_core0_ledc_intr_map_reg_t ledc_intr_map; + volatile interrupt_core0_can0_intr_map_reg_t can0_intr_map; + volatile interrupt_core0_can0_timer_intr_map_reg_t can0_timer_intr_map; + volatile interrupt_core0_usb_serial_jtag_intr_map_reg_t usb_serial_jtag_intr_map; + volatile interrupt_core0_rmt_intr_map_reg_t rmt_intr_map; + volatile interrupt_core0_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map; + volatile interrupt_core0_i2c_ext1_intr_map_reg_t i2c_ext1_intr_map; + volatile interrupt_core0_tg0_t0_intr_map_reg_t tg0_t0_intr_map; + volatile interrupt_core0_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map; + volatile interrupt_core0_tg1_t0_intr_map_reg_t tg1_t0_intr_map; + volatile interrupt_core0_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map; + volatile interrupt_core0_systimer_target0_intr_map_reg_t systimer_target0_intr_map; + volatile interrupt_core0_systimer_target1_intr_map_reg_t systimer_target1_intr_map; + volatile interrupt_core0_systimer_target2_intr_map_reg_t systimer_target2_intr_map; + volatile interrupt_core0_apb_adc_intr_map_reg_t apb_adc_intr_map; + volatile interrupt_core0_pwm0_intr_map_reg_t pwm0_intr_map; + volatile interrupt_core0_pwm1_intr_map_reg_t pwm1_intr_map; + volatile interrupt_core0_pcnt_intr_map_reg_t pcnt_intr_map; + volatile interrupt_core0_parl_io_tx_intr_map_reg_t parl_io_tx_intr_map; + volatile interrupt_core0_parl_io_rx_intr_map_reg_t parl_io_rx_intr_map; + volatile interrupt_core0_usb_otg11_intr_map_reg_t usb_otg11_intr_map; + volatile interrupt_core0_asrc_chnl0_intr_map_reg_t asrc_chnl0_intr_map; + volatile interrupt_core0_asrc_chnl1_intr_map_reg_t asrc_chnl1_intr_map; + volatile interrupt_core0_zero_det_intr_map_reg_t zero_det_intr_map; + volatile interrupt_core0_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; + volatile interrupt_core0_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; + volatile interrupt_core0_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map; + volatile interrupt_core0_dma_in_ch3_intr_map_reg_t dma_in_ch3_intr_map; + volatile interrupt_core0_dma_in_ch4_intr_map_reg_t dma_in_ch4_intr_map; + volatile interrupt_core0_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map; + volatile interrupt_core0_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map; + volatile interrupt_core0_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map; + volatile interrupt_core0_dma_out_ch3_intr_map_reg_t dma_out_ch3_intr_map; + volatile interrupt_core0_dma_out_ch4_intr_map_reg_t dma_out_ch4_intr_map; + volatile interrupt_core0_gpspi2_intr_map_reg_t gpspi2_intr_map; + volatile interrupt_core0_gpspi3_intr_map_reg_t gpspi3_intr_map; + volatile interrupt_core0_aes_intr_map_reg_t aes_intr_map; + volatile interrupt_core0_sha_intr_map_reg_t sha_intr_map; + volatile interrupt_core0_ecc_intr_map_reg_t ecc_intr_map; + volatile interrupt_core0_ecdsa_intr_map_reg_t ecdsa_intr_map; + volatile interrupt_core0_km_intr_map_reg_t km_intr_map; + volatile interrupt_core0_int_status_reg_0_reg_t int_status_reg_0; + volatile interrupt_core0_int_status_reg_1_reg_t int_status_reg_1; + volatile interrupt_core0_int_status_reg_2_reg_t int_status_reg_2; + volatile interrupt_core0_int_status_reg_3_reg_t int_status_reg_3; + volatile interrupt_core0_src_pass_in_sec_status_0_reg_t src_pass_in_sec_status_0; + volatile interrupt_core0_src_pass_in_sec_status_1_reg_t src_pass_in_sec_status_1; + volatile interrupt_core0_src_pass_in_sec_status_2_reg_t src_pass_in_sec_status_2; + volatile interrupt_core0_src_pass_in_sec_status_3_reg_t src_pass_in_sec_status_3; + volatile interrupt_core0_sig_idx_assert_in_sec_reg_t sig_idx_assert_in_sec; + volatile interrupt_core0_secure_status_reg_t secure_status; + volatile interrupt_core0_clock_gate_reg_t clock_gate; + uint32_t reserved_1b4[402]; + volatile interrupt_core0_interrupt_date_reg_t interrupt_date; +} interrupt_core0_dev_t; + +extern interrupt_core0_dev_t INTMTX0; +extern interrupt_core0_dev_t INTMTX1; + +#ifndef __cplusplus +_Static_assert(sizeof(interrupt_core0_dev_t) == 0x800, "Invalid size of interrupt_core0_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/tee_reg.h b/components/soc/esp32h4/register/hw_ver_mp/soc/tee_reg.h new file mode 100644 index 0000000000..b11d4d5cda --- /dev/null +++ b/components/soc/esp32h4/register/hw_ver_mp/soc/tee_reg.h @@ -0,0 +1,4565 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** TEE_M0_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) +/** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M0 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M0_MODE 0x00000003U +#define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) +#define TEE_M0_MODE_V 0x00000003U +#define TEE_M0_MODE_S 0 +/** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M0_LOCK (BIT(2)) +#define TEE_M0_LOCK_M (TEE_M0_LOCK_V << TEE_M0_LOCK_S) +#define TEE_M0_LOCK_V 0x00000001U +#define TEE_M0_LOCK_S 2 + +/** TEE_M1_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) +/** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M1 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M1_MODE 0x00000003U +#define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) +#define TEE_M1_MODE_V 0x00000003U +#define TEE_M1_MODE_S 0 +/** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M1_LOCK (BIT(2)) +#define TEE_M1_LOCK_M (TEE_M1_LOCK_V << TEE_M1_LOCK_S) +#define TEE_M1_LOCK_V 0x00000001U +#define TEE_M1_LOCK_S 2 + +/** TEE_M2_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) +/** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M2 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M2_MODE 0x00000003U +#define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) +#define TEE_M2_MODE_V 0x00000003U +#define TEE_M2_MODE_S 0 +/** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M2_LOCK (BIT(2)) +#define TEE_M2_LOCK_M (TEE_M2_LOCK_V << TEE_M2_LOCK_S) +#define TEE_M2_LOCK_V 0x00000001U +#define TEE_M2_LOCK_S 2 + +/** TEE_M3_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) +/** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M3 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M3_MODE 0x00000003U +#define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) +#define TEE_M3_MODE_V 0x00000003U +#define TEE_M3_MODE_S 0 +/** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M3_LOCK (BIT(2)) +#define TEE_M3_LOCK_M (TEE_M3_LOCK_V << TEE_M3_LOCK_S) +#define TEE_M3_LOCK_V 0x00000001U +#define TEE_M3_LOCK_S 2 + +/** TEE_M4_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) +/** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M4 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M4_MODE 0x00000003U +#define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) +#define TEE_M4_MODE_V 0x00000003U +#define TEE_M4_MODE_S 0 +/** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M4_LOCK (BIT(2)) +#define TEE_M4_LOCK_M (TEE_M4_LOCK_V << TEE_M4_LOCK_S) +#define TEE_M4_LOCK_V 0x00000001U +#define TEE_M4_LOCK_S 2 + +/** TEE_M5_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) +/** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M5 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M5_MODE 0x00000003U +#define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) +#define TEE_M5_MODE_V 0x00000003U +#define TEE_M5_MODE_S 0 +/** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M5_LOCK (BIT(2)) +#define TEE_M5_LOCK_M (TEE_M5_LOCK_V << TEE_M5_LOCK_S) +#define TEE_M5_LOCK_V 0x00000001U +#define TEE_M5_LOCK_S 2 + +/** TEE_M6_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) +/** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M6 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M6_MODE 0x00000003U +#define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) +#define TEE_M6_MODE_V 0x00000003U +#define TEE_M6_MODE_S 0 +/** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M6_LOCK (BIT(2)) +#define TEE_M6_LOCK_M (TEE_M6_LOCK_V << TEE_M6_LOCK_S) +#define TEE_M6_LOCK_V 0x00000001U +#define TEE_M6_LOCK_S 2 + +/** TEE_M7_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) +/** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M7 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M7_MODE 0x00000003U +#define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) +#define TEE_M7_MODE_V 0x00000003U +#define TEE_M7_MODE_S 0 +/** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M7_LOCK (BIT(2)) +#define TEE_M7_LOCK_M (TEE_M7_LOCK_V << TEE_M7_LOCK_S) +#define TEE_M7_LOCK_V 0x00000001U +#define TEE_M7_LOCK_S 2 + +/** TEE_M8_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) +/** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M8 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M8_MODE 0x00000003U +#define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) +#define TEE_M8_MODE_V 0x00000003U +#define TEE_M8_MODE_S 0 +/** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M8_LOCK (BIT(2)) +#define TEE_M8_LOCK_M (TEE_M8_LOCK_V << TEE_M8_LOCK_S) +#define TEE_M8_LOCK_V 0x00000001U +#define TEE_M8_LOCK_S 2 + +/** TEE_M9_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) +/** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M9 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M9_MODE 0x00000003U +#define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) +#define TEE_M9_MODE_V 0x00000003U +#define TEE_M9_MODE_S 0 +/** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M9_LOCK (BIT(2)) +#define TEE_M9_LOCK_M (TEE_M9_LOCK_V << TEE_M9_LOCK_S) +#define TEE_M9_LOCK_V 0x00000001U +#define TEE_M9_LOCK_S 2 + +/** TEE_M10_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) +/** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M10 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M10_MODE 0x00000003U +#define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) +#define TEE_M10_MODE_V 0x00000003U +#define TEE_M10_MODE_S 0 +/** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M10_LOCK (BIT(2)) +#define TEE_M10_LOCK_M (TEE_M10_LOCK_V << TEE_M10_LOCK_S) +#define TEE_M10_LOCK_V 0x00000001U +#define TEE_M10_LOCK_S 2 + +/** TEE_M11_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) +/** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M11 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M11_MODE 0x00000003U +#define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) +#define TEE_M11_MODE_V 0x00000003U +#define TEE_M11_MODE_S 0 +/** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M11_LOCK (BIT(2)) +#define TEE_M11_LOCK_M (TEE_M11_LOCK_V << TEE_M11_LOCK_S) +#define TEE_M11_LOCK_V 0x00000001U +#define TEE_M11_LOCK_S 2 + +/** TEE_M12_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) +/** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M12 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M12_MODE 0x00000003U +#define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) +#define TEE_M12_MODE_V 0x00000003U +#define TEE_M12_MODE_S 0 +/** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M12_LOCK (BIT(2)) +#define TEE_M12_LOCK_M (TEE_M12_LOCK_V << TEE_M12_LOCK_S) +#define TEE_M12_LOCK_V 0x00000001U +#define TEE_M12_LOCK_S 2 + +/** TEE_M13_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) +/** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M13 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M13_MODE 0x00000003U +#define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) +#define TEE_M13_MODE_V 0x00000003U +#define TEE_M13_MODE_S 0 +/** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M13_LOCK (BIT(2)) +#define TEE_M13_LOCK_M (TEE_M13_LOCK_V << TEE_M13_LOCK_S) +#define TEE_M13_LOCK_V 0x00000001U +#define TEE_M13_LOCK_S 2 + +/** TEE_M14_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) +/** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M14 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M14_MODE 0x00000003U +#define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) +#define TEE_M14_MODE_V 0x00000003U +#define TEE_M14_MODE_S 0 +/** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M14_LOCK (BIT(2)) +#define TEE_M14_LOCK_M (TEE_M14_LOCK_V << TEE_M14_LOCK_S) +#define TEE_M14_LOCK_V 0x00000001U +#define TEE_M14_LOCK_S 2 + +/** TEE_M15_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) +/** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M15 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M15_MODE 0x00000003U +#define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) +#define TEE_M15_MODE_V 0x00000003U +#define TEE_M15_MODE_S 0 +/** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M15_LOCK (BIT(2)) +#define TEE_M15_LOCK_M (TEE_M15_LOCK_V << TEE_M15_LOCK_S) +#define TEE_M15_LOCK_V 0x00000001U +#define TEE_M15_LOCK_S 2 + +/** TEE_M16_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) +/** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M16 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M16_MODE 0x00000003U +#define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) +#define TEE_M16_MODE_V 0x00000003U +#define TEE_M16_MODE_S 0 +/** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M16_LOCK (BIT(2)) +#define TEE_M16_LOCK_M (TEE_M16_LOCK_V << TEE_M16_LOCK_S) +#define TEE_M16_LOCK_V 0x00000001U +#define TEE_M16_LOCK_S 2 + +/** TEE_M17_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) +/** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M17 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M17_MODE 0x00000003U +#define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) +#define TEE_M17_MODE_V 0x00000003U +#define TEE_M17_MODE_S 0 +/** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M17_LOCK (BIT(2)) +#define TEE_M17_LOCK_M (TEE_M17_LOCK_V << TEE_M17_LOCK_S) +#define TEE_M17_LOCK_V 0x00000001U +#define TEE_M17_LOCK_S 2 + +/** TEE_M18_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) +/** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M18 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M18_MODE 0x00000003U +#define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) +#define TEE_M18_MODE_V 0x00000003U +#define TEE_M18_MODE_S 0 +/** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M18_LOCK (BIT(2)) +#define TEE_M18_LOCK_M (TEE_M18_LOCK_V << TEE_M18_LOCK_S) +#define TEE_M18_LOCK_V 0x00000001U +#define TEE_M18_LOCK_S 2 + +/** TEE_M19_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) +/** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M19 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M19_MODE 0x00000003U +#define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) +#define TEE_M19_MODE_V 0x00000003U +#define TEE_M19_MODE_S 0 +/** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M19_LOCK (BIT(2)) +#define TEE_M19_LOCK_M (TEE_M19_LOCK_V << TEE_M19_LOCK_S) +#define TEE_M19_LOCK_V 0x00000001U +#define TEE_M19_LOCK_S 2 + +/** TEE_M20_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) +/** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M20 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M20_MODE 0x00000003U +#define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) +#define TEE_M20_MODE_V 0x00000003U +#define TEE_M20_MODE_S 0 +/** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M20_LOCK (BIT(2)) +#define TEE_M20_LOCK_M (TEE_M20_LOCK_V << TEE_M20_LOCK_S) +#define TEE_M20_LOCK_V 0x00000001U +#define TEE_M20_LOCK_S 2 + +/** TEE_M21_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) +/** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M21 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M21_MODE 0x00000003U +#define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) +#define TEE_M21_MODE_V 0x00000003U +#define TEE_M21_MODE_S 0 +/** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M21_LOCK (BIT(2)) +#define TEE_M21_LOCK_M (TEE_M21_LOCK_V << TEE_M21_LOCK_S) +#define TEE_M21_LOCK_V 0x00000001U +#define TEE_M21_LOCK_S 2 + +/** TEE_M22_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) +/** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M22 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M22_MODE 0x00000003U +#define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) +#define TEE_M22_MODE_V 0x00000003U +#define TEE_M22_MODE_S 0 +/** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M22_LOCK (BIT(2)) +#define TEE_M22_LOCK_M (TEE_M22_LOCK_V << TEE_M22_LOCK_S) +#define TEE_M22_LOCK_V 0x00000001U +#define TEE_M22_LOCK_S 2 + +/** TEE_M23_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) +/** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M23 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M23_MODE 0x00000003U +#define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) +#define TEE_M23_MODE_V 0x00000003U +#define TEE_M23_MODE_S 0 +/** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M23_LOCK (BIT(2)) +#define TEE_M23_LOCK_M (TEE_M23_LOCK_V << TEE_M23_LOCK_S) +#define TEE_M23_LOCK_V 0x00000001U +#define TEE_M23_LOCK_S 2 + +/** TEE_M24_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) +/** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M24 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M24_MODE 0x00000003U +#define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) +#define TEE_M24_MODE_V 0x00000003U +#define TEE_M24_MODE_S 0 +/** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M24_LOCK (BIT(2)) +#define TEE_M24_LOCK_M (TEE_M24_LOCK_V << TEE_M24_LOCK_S) +#define TEE_M24_LOCK_V 0x00000001U +#define TEE_M24_LOCK_S 2 + +/** TEE_M25_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) +/** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M25 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M25_MODE 0x00000003U +#define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) +#define TEE_M25_MODE_V 0x00000003U +#define TEE_M25_MODE_S 0 +/** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M25_LOCK (BIT(2)) +#define TEE_M25_LOCK_M (TEE_M25_LOCK_V << TEE_M25_LOCK_S) +#define TEE_M25_LOCK_V 0x00000001U +#define TEE_M25_LOCK_S 2 + +/** TEE_M26_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) +/** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M26 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M26_MODE 0x00000003U +#define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) +#define TEE_M26_MODE_V 0x00000003U +#define TEE_M26_MODE_S 0 +/** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M26_LOCK (BIT(2)) +#define TEE_M26_LOCK_M (TEE_M26_LOCK_V << TEE_M26_LOCK_S) +#define TEE_M26_LOCK_V 0x00000001U +#define TEE_M26_LOCK_S 2 + +/** TEE_M27_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) +/** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M27 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M27_MODE 0x00000003U +#define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) +#define TEE_M27_MODE_V 0x00000003U +#define TEE_M27_MODE_S 0 +/** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M27_LOCK (BIT(2)) +#define TEE_M27_LOCK_M (TEE_M27_LOCK_V << TEE_M27_LOCK_S) +#define TEE_M27_LOCK_V 0x00000001U +#define TEE_M27_LOCK_S 2 + +/** TEE_M28_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) +/** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M28 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M28_MODE 0x00000003U +#define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) +#define TEE_M28_MODE_V 0x00000003U +#define TEE_M28_MODE_S 0 +/** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M28_LOCK (BIT(2)) +#define TEE_M28_LOCK_M (TEE_M28_LOCK_V << TEE_M28_LOCK_S) +#define TEE_M28_LOCK_V 0x00000001U +#define TEE_M28_LOCK_S 2 + +/** TEE_M29_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) +/** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M29 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M29_MODE 0x00000003U +#define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) +#define TEE_M29_MODE_V 0x00000003U +#define TEE_M29_MODE_S 0 +/** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M29_LOCK (BIT(2)) +#define TEE_M29_LOCK_M (TEE_M29_LOCK_V << TEE_M29_LOCK_S) +#define TEE_M29_LOCK_V 0x00000001U +#define TEE_M29_LOCK_S 2 + +/** TEE_M30_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) +/** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M30 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M30_MODE 0x00000003U +#define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) +#define TEE_M30_MODE_V 0x00000003U +#define TEE_M30_MODE_S 0 +/** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M30_LOCK (BIT(2)) +#define TEE_M30_LOCK_M (TEE_M30_LOCK_V << TEE_M30_LOCK_S) +#define TEE_M30_LOCK_V 0x00000001U +#define TEE_M30_LOCK_S 2 + +/** TEE_M31_MODE_CTRL_REG register + * TEE mode control register + */ +#define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) +/** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 0; + * Configures M31 security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ +#define TEE_M31_MODE 0x00000003U +#define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) +#define TEE_M31_MODE_V 0x00000003U +#define TEE_M31_MODE_S 0 +/** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ +#define TEE_M31_LOCK (BIT(2)) +#define TEE_M31_LOCK_M (TEE_M31_LOCK_V << TEE_M31_LOCK_S) +#define TEE_M31_LOCK_V 0x00000001U +#define TEE_M31_LOCK_S 2 + +/** TEE_GPSPI0_CTRL_REG register + * gpspi0 read/write control register + */ +#define TEE_GPSPI0_CTRL_REG (DR_REG_TEE_BASE + 0x80) +/** TEE_READ_TEE_GPSPI0 : R/W; bitpos: [0]; default: 1; + * Configures gpspi0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_GPSPI0 (BIT(0)) +#define TEE_READ_TEE_GPSPI0_M (TEE_READ_TEE_GPSPI0_V << TEE_READ_TEE_GPSPI0_S) +#define TEE_READ_TEE_GPSPI0_V 0x00000001U +#define TEE_READ_TEE_GPSPI0_S 0 +/** TEE_READ_REE0_GPSPI0 : R/W; bitpos: [1]; default: 0; + * Configures gpspi0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_GPSPI0 (BIT(1)) +#define TEE_READ_REE0_GPSPI0_M (TEE_READ_REE0_GPSPI0_V << TEE_READ_REE0_GPSPI0_S) +#define TEE_READ_REE0_GPSPI0_V 0x00000001U +#define TEE_READ_REE0_GPSPI0_S 1 +/** TEE_READ_REE1_GPSPI0 : R/W; bitpos: [2]; default: 0; + * Configures gpspi0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_GPSPI0 (BIT(2)) +#define TEE_READ_REE1_GPSPI0_M (TEE_READ_REE1_GPSPI0_V << TEE_READ_REE1_GPSPI0_S) +#define TEE_READ_REE1_GPSPI0_V 0x00000001U +#define TEE_READ_REE1_GPSPI0_S 2 +/** TEE_READ_REE2_GPSPI0 : R/W; bitpos: [3]; default: 0; + * Configures gpspi0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_GPSPI0 (BIT(3)) +#define TEE_READ_REE2_GPSPI0_M (TEE_READ_REE2_GPSPI0_V << TEE_READ_REE2_GPSPI0_S) +#define TEE_READ_REE2_GPSPI0_V 0x00000001U +#define TEE_READ_REE2_GPSPI0_S 3 +/** TEE_WRITE_TEE_GPSPI0 : R/W; bitpos: [4]; default: 1; + * Configures gpspi0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_GPSPI0 (BIT(4)) +#define TEE_WRITE_TEE_GPSPI0_M (TEE_WRITE_TEE_GPSPI0_V << TEE_WRITE_TEE_GPSPI0_S) +#define TEE_WRITE_TEE_GPSPI0_V 0x00000001U +#define TEE_WRITE_TEE_GPSPI0_S 4 +/** TEE_WRITE_REE0_GPSPI0 : R/W; bitpos: [5]; default: 0; + * Configures gpspi0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_GPSPI0 (BIT(5)) +#define TEE_WRITE_REE0_GPSPI0_M (TEE_WRITE_REE0_GPSPI0_V << TEE_WRITE_REE0_GPSPI0_S) +#define TEE_WRITE_REE0_GPSPI0_V 0x00000001U +#define TEE_WRITE_REE0_GPSPI0_S 5 +/** TEE_WRITE_REE1_GPSPI0 : R/W; bitpos: [6]; default: 0; + * Configures gpspi0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_GPSPI0 (BIT(6)) +#define TEE_WRITE_REE1_GPSPI0_M (TEE_WRITE_REE1_GPSPI0_V << TEE_WRITE_REE1_GPSPI0_S) +#define TEE_WRITE_REE1_GPSPI0_V 0x00000001U +#define TEE_WRITE_REE1_GPSPI0_S 6 +/** TEE_WRITE_REE2_GPSPI0 : R/W; bitpos: [7]; default: 0; + * Configures gpspi0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_GPSPI0 (BIT(7)) +#define TEE_WRITE_REE2_GPSPI0_M (TEE_WRITE_REE2_GPSPI0_V << TEE_WRITE_REE2_GPSPI0_S) +#define TEE_WRITE_REE2_GPSPI0_V 0x00000001U +#define TEE_WRITE_REE2_GPSPI0_S 7 + +/** TEE_GPSPI1_CTRL_REG register + * gpspi1 read/write control register + */ +#define TEE_GPSPI1_CTRL_REG (DR_REG_TEE_BASE + 0x84) +/** TEE_READ_TEE_GPSPI1 : R/W; bitpos: [0]; default: 1; + * Configures gpspi1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_GPSPI1 (BIT(0)) +#define TEE_READ_TEE_GPSPI1_M (TEE_READ_TEE_GPSPI1_V << TEE_READ_TEE_GPSPI1_S) +#define TEE_READ_TEE_GPSPI1_V 0x00000001U +#define TEE_READ_TEE_GPSPI1_S 0 +/** TEE_READ_REE0_GPSPI1 : R/W; bitpos: [1]; default: 0; + * Configures gpspi1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_GPSPI1 (BIT(1)) +#define TEE_READ_REE0_GPSPI1_M (TEE_READ_REE0_GPSPI1_V << TEE_READ_REE0_GPSPI1_S) +#define TEE_READ_REE0_GPSPI1_V 0x00000001U +#define TEE_READ_REE0_GPSPI1_S 1 +/** TEE_READ_REE1_GPSPI1 : R/W; bitpos: [2]; default: 0; + * Configures gpspi1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_GPSPI1 (BIT(2)) +#define TEE_READ_REE1_GPSPI1_M (TEE_READ_REE1_GPSPI1_V << TEE_READ_REE1_GPSPI1_S) +#define TEE_READ_REE1_GPSPI1_V 0x00000001U +#define TEE_READ_REE1_GPSPI1_S 2 +/** TEE_READ_REE2_GPSPI1 : R/W; bitpos: [3]; default: 0; + * Configures gpspi1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_GPSPI1 (BIT(3)) +#define TEE_READ_REE2_GPSPI1_M (TEE_READ_REE2_GPSPI1_V << TEE_READ_REE2_GPSPI1_S) +#define TEE_READ_REE2_GPSPI1_V 0x00000001U +#define TEE_READ_REE2_GPSPI1_S 3 +/** TEE_WRITE_TEE_GPSPI1 : R/W; bitpos: [4]; default: 1; + * Configures gpspi1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_GPSPI1 (BIT(4)) +#define TEE_WRITE_TEE_GPSPI1_M (TEE_WRITE_TEE_GPSPI1_V << TEE_WRITE_TEE_GPSPI1_S) +#define TEE_WRITE_TEE_GPSPI1_V 0x00000001U +#define TEE_WRITE_TEE_GPSPI1_S 4 +/** TEE_WRITE_REE0_GPSPI1 : R/W; bitpos: [5]; default: 0; + * Configures gpspi1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_GPSPI1 (BIT(5)) +#define TEE_WRITE_REE0_GPSPI1_M (TEE_WRITE_REE0_GPSPI1_V << TEE_WRITE_REE0_GPSPI1_S) +#define TEE_WRITE_REE0_GPSPI1_V 0x00000001U +#define TEE_WRITE_REE0_GPSPI1_S 5 +/** TEE_WRITE_REE1_GPSPI1 : R/W; bitpos: [6]; default: 0; + * Configures gpspi1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_GPSPI1 (BIT(6)) +#define TEE_WRITE_REE1_GPSPI1_M (TEE_WRITE_REE1_GPSPI1_V << TEE_WRITE_REE1_GPSPI1_S) +#define TEE_WRITE_REE1_GPSPI1_V 0x00000001U +#define TEE_WRITE_REE1_GPSPI1_S 6 +/** TEE_WRITE_REE2_GPSPI1 : R/W; bitpos: [7]; default: 0; + * Configures gpspi1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_GPSPI1 (BIT(7)) +#define TEE_WRITE_REE2_GPSPI1_M (TEE_WRITE_REE2_GPSPI1_V << TEE_WRITE_REE2_GPSPI1_S) +#define TEE_WRITE_REE2_GPSPI1_V 0x00000001U +#define TEE_WRITE_REE2_GPSPI1_S 7 + +/** TEE_UART0_CTRL_REG register + * uart0 read/write control register + */ +#define TEE_UART0_CTRL_REG (DR_REG_TEE_BASE + 0x88) +/** TEE_READ_TEE_UART0 : R/W; bitpos: [0]; default: 1; + * Configures uart0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_UART0 (BIT(0)) +#define TEE_READ_TEE_UART0_M (TEE_READ_TEE_UART0_V << TEE_READ_TEE_UART0_S) +#define TEE_READ_TEE_UART0_V 0x00000001U +#define TEE_READ_TEE_UART0_S 0 +/** TEE_READ_REE0_UART0 : R/W; bitpos: [1]; default: 0; + * Configures uart0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_UART0 (BIT(1)) +#define TEE_READ_REE0_UART0_M (TEE_READ_REE0_UART0_V << TEE_READ_REE0_UART0_S) +#define TEE_READ_REE0_UART0_V 0x00000001U +#define TEE_READ_REE0_UART0_S 1 +/** TEE_READ_REE1_UART0 : R/W; bitpos: [2]; default: 0; + * Configures uart0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_UART0 (BIT(2)) +#define TEE_READ_REE1_UART0_M (TEE_READ_REE1_UART0_V << TEE_READ_REE1_UART0_S) +#define TEE_READ_REE1_UART0_V 0x00000001U +#define TEE_READ_REE1_UART0_S 2 +/** TEE_READ_REE2_UART0 : R/W; bitpos: [3]; default: 0; + * Configures uart0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_UART0 (BIT(3)) +#define TEE_READ_REE2_UART0_M (TEE_READ_REE2_UART0_V << TEE_READ_REE2_UART0_S) +#define TEE_READ_REE2_UART0_V 0x00000001U +#define TEE_READ_REE2_UART0_S 3 +/** TEE_WRITE_TEE_UART0 : R/W; bitpos: [4]; default: 1; + * Configures uart0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_UART0 (BIT(4)) +#define TEE_WRITE_TEE_UART0_M (TEE_WRITE_TEE_UART0_V << TEE_WRITE_TEE_UART0_S) +#define TEE_WRITE_TEE_UART0_V 0x00000001U +#define TEE_WRITE_TEE_UART0_S 4 +/** TEE_WRITE_REE0_UART0 : R/W; bitpos: [5]; default: 0; + * Configures uart0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_UART0 (BIT(5)) +#define TEE_WRITE_REE0_UART0_M (TEE_WRITE_REE0_UART0_V << TEE_WRITE_REE0_UART0_S) +#define TEE_WRITE_REE0_UART0_V 0x00000001U +#define TEE_WRITE_REE0_UART0_S 5 +/** TEE_WRITE_REE1_UART0 : R/W; bitpos: [6]; default: 0; + * Configures uart0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_UART0 (BIT(6)) +#define TEE_WRITE_REE1_UART0_M (TEE_WRITE_REE1_UART0_V << TEE_WRITE_REE1_UART0_S) +#define TEE_WRITE_REE1_UART0_V 0x00000001U +#define TEE_WRITE_REE1_UART0_S 6 +/** TEE_WRITE_REE2_UART0 : R/W; bitpos: [7]; default: 0; + * Configures uart0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_UART0 (BIT(7)) +#define TEE_WRITE_REE2_UART0_M (TEE_WRITE_REE2_UART0_V << TEE_WRITE_REE2_UART0_S) +#define TEE_WRITE_REE2_UART0_V 0x00000001U +#define TEE_WRITE_REE2_UART0_S 7 + +/** TEE_UART1_CTRL_REG register + * uart1 read/write control register + */ +#define TEE_UART1_CTRL_REG (DR_REG_TEE_BASE + 0x8c) +/** TEE_READ_TEE_UART1 : R/W; bitpos: [0]; default: 1; + * Configures uart1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_UART1 (BIT(0)) +#define TEE_READ_TEE_UART1_M (TEE_READ_TEE_UART1_V << TEE_READ_TEE_UART1_S) +#define TEE_READ_TEE_UART1_V 0x00000001U +#define TEE_READ_TEE_UART1_S 0 +/** TEE_READ_REE0_UART1 : R/W; bitpos: [1]; default: 0; + * Configures uart1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_UART1 (BIT(1)) +#define TEE_READ_REE0_UART1_M (TEE_READ_REE0_UART1_V << TEE_READ_REE0_UART1_S) +#define TEE_READ_REE0_UART1_V 0x00000001U +#define TEE_READ_REE0_UART1_S 1 +/** TEE_READ_REE1_UART1 : R/W; bitpos: [2]; default: 0; + * Configures uart1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_UART1 (BIT(2)) +#define TEE_READ_REE1_UART1_M (TEE_READ_REE1_UART1_V << TEE_READ_REE1_UART1_S) +#define TEE_READ_REE1_UART1_V 0x00000001U +#define TEE_READ_REE1_UART1_S 2 +/** TEE_READ_REE2_UART1 : R/W; bitpos: [3]; default: 0; + * Configures uart1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_UART1 (BIT(3)) +#define TEE_READ_REE2_UART1_M (TEE_READ_REE2_UART1_V << TEE_READ_REE2_UART1_S) +#define TEE_READ_REE2_UART1_V 0x00000001U +#define TEE_READ_REE2_UART1_S 3 +/** TEE_WRITE_TEE_UART1 : R/W; bitpos: [4]; default: 1; + * Configures uart1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_UART1 (BIT(4)) +#define TEE_WRITE_TEE_UART1_M (TEE_WRITE_TEE_UART1_V << TEE_WRITE_TEE_UART1_S) +#define TEE_WRITE_TEE_UART1_V 0x00000001U +#define TEE_WRITE_TEE_UART1_S 4 +/** TEE_WRITE_REE0_UART1 : R/W; bitpos: [5]; default: 0; + * Configures uart1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_UART1 (BIT(5)) +#define TEE_WRITE_REE0_UART1_M (TEE_WRITE_REE0_UART1_V << TEE_WRITE_REE0_UART1_S) +#define TEE_WRITE_REE0_UART1_V 0x00000001U +#define TEE_WRITE_REE0_UART1_S 5 +/** TEE_WRITE_REE1_UART1 : R/W; bitpos: [6]; default: 0; + * Configures uart1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_UART1 (BIT(6)) +#define TEE_WRITE_REE1_UART1_M (TEE_WRITE_REE1_UART1_V << TEE_WRITE_REE1_UART1_S) +#define TEE_WRITE_REE1_UART1_V 0x00000001U +#define TEE_WRITE_REE1_UART1_S 6 +/** TEE_WRITE_REE2_UART1 : R/W; bitpos: [7]; default: 0; + * Configures uart1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_UART1 (BIT(7)) +#define TEE_WRITE_REE2_UART1_M (TEE_WRITE_REE2_UART1_V << TEE_WRITE_REE2_UART1_S) +#define TEE_WRITE_REE2_UART1_V 0x00000001U +#define TEE_WRITE_REE2_UART1_S 7 + +/** TEE_UHCI_CTRL_REG register + * uhci read/write control register + */ +#define TEE_UHCI_CTRL_REG (DR_REG_TEE_BASE + 0x90) +/** TEE_READ_TEE_UHCI : R/W; bitpos: [0]; default: 1; + * Configures uhci registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_UHCI (BIT(0)) +#define TEE_READ_TEE_UHCI_M (TEE_READ_TEE_UHCI_V << TEE_READ_TEE_UHCI_S) +#define TEE_READ_TEE_UHCI_V 0x00000001U +#define TEE_READ_TEE_UHCI_S 0 +/** TEE_READ_REE0_UHCI : R/W; bitpos: [1]; default: 0; + * Configures uhci registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_UHCI (BIT(1)) +#define TEE_READ_REE0_UHCI_M (TEE_READ_REE0_UHCI_V << TEE_READ_REE0_UHCI_S) +#define TEE_READ_REE0_UHCI_V 0x00000001U +#define TEE_READ_REE0_UHCI_S 1 +/** TEE_READ_REE1_UHCI : R/W; bitpos: [2]; default: 0; + * Configures uhci registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_UHCI (BIT(2)) +#define TEE_READ_REE1_UHCI_M (TEE_READ_REE1_UHCI_V << TEE_READ_REE1_UHCI_S) +#define TEE_READ_REE1_UHCI_V 0x00000001U +#define TEE_READ_REE1_UHCI_S 2 +/** TEE_READ_REE2_UHCI : R/W; bitpos: [3]; default: 0; + * Configures uhci registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_UHCI (BIT(3)) +#define TEE_READ_REE2_UHCI_M (TEE_READ_REE2_UHCI_V << TEE_READ_REE2_UHCI_S) +#define TEE_READ_REE2_UHCI_V 0x00000001U +#define TEE_READ_REE2_UHCI_S 3 +/** TEE_WRITE_TEE_UHCI : R/W; bitpos: [4]; default: 1; + * Configures uhci registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_UHCI (BIT(4)) +#define TEE_WRITE_TEE_UHCI_M (TEE_WRITE_TEE_UHCI_V << TEE_WRITE_TEE_UHCI_S) +#define TEE_WRITE_TEE_UHCI_V 0x00000001U +#define TEE_WRITE_TEE_UHCI_S 4 +/** TEE_WRITE_REE0_UHCI : R/W; bitpos: [5]; default: 0; + * Configures uhci registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_UHCI (BIT(5)) +#define TEE_WRITE_REE0_UHCI_M (TEE_WRITE_REE0_UHCI_V << TEE_WRITE_REE0_UHCI_S) +#define TEE_WRITE_REE0_UHCI_V 0x00000001U +#define TEE_WRITE_REE0_UHCI_S 5 +/** TEE_WRITE_REE1_UHCI : R/W; bitpos: [6]; default: 0; + * Configures uhci registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_UHCI (BIT(6)) +#define TEE_WRITE_REE1_UHCI_M (TEE_WRITE_REE1_UHCI_V << TEE_WRITE_REE1_UHCI_S) +#define TEE_WRITE_REE1_UHCI_V 0x00000001U +#define TEE_WRITE_REE1_UHCI_S 6 +/** TEE_WRITE_REE2_UHCI : R/W; bitpos: [7]; default: 0; + * Configures uhci registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_UHCI (BIT(7)) +#define TEE_WRITE_REE2_UHCI_M (TEE_WRITE_REE2_UHCI_V << TEE_WRITE_REE2_UHCI_S) +#define TEE_WRITE_REE2_UHCI_V 0x00000001U +#define TEE_WRITE_REE2_UHCI_S 7 + +/** TEE_I2C0_CTRL_REG register + * i2c0 read/write control register + */ +#define TEE_I2C0_CTRL_REG (DR_REG_TEE_BASE + 0x94) +/** TEE_READ_TEE_I2C0 : R/W; bitpos: [0]; default: 1; + * Configures i2c0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_I2C0 (BIT(0)) +#define TEE_READ_TEE_I2C0_M (TEE_READ_TEE_I2C0_V << TEE_READ_TEE_I2C0_S) +#define TEE_READ_TEE_I2C0_V 0x00000001U +#define TEE_READ_TEE_I2C0_S 0 +/** TEE_READ_REE0_I2C0 : R/W; bitpos: [1]; default: 0; + * Configures i2c0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_I2C0 (BIT(1)) +#define TEE_READ_REE0_I2C0_M (TEE_READ_REE0_I2C0_V << TEE_READ_REE0_I2C0_S) +#define TEE_READ_REE0_I2C0_V 0x00000001U +#define TEE_READ_REE0_I2C0_S 1 +/** TEE_READ_REE1_I2C0 : R/W; bitpos: [2]; default: 0; + * Configures i2c0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_I2C0 (BIT(2)) +#define TEE_READ_REE1_I2C0_M (TEE_READ_REE1_I2C0_V << TEE_READ_REE1_I2C0_S) +#define TEE_READ_REE1_I2C0_V 0x00000001U +#define TEE_READ_REE1_I2C0_S 2 +/** TEE_READ_REE2_I2C0 : R/W; bitpos: [3]; default: 0; + * Configures i2c0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_I2C0 (BIT(3)) +#define TEE_READ_REE2_I2C0_M (TEE_READ_REE2_I2C0_V << TEE_READ_REE2_I2C0_S) +#define TEE_READ_REE2_I2C0_V 0x00000001U +#define TEE_READ_REE2_I2C0_S 3 +/** TEE_WRITE_TEE_I2C0 : R/W; bitpos: [4]; default: 1; + * Configures i2c0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_I2C0 (BIT(4)) +#define TEE_WRITE_TEE_I2C0_M (TEE_WRITE_TEE_I2C0_V << TEE_WRITE_TEE_I2C0_S) +#define TEE_WRITE_TEE_I2C0_V 0x00000001U +#define TEE_WRITE_TEE_I2C0_S 4 +/** TEE_WRITE_REE0_I2C0 : R/W; bitpos: [5]; default: 0; + * Configures i2c0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_I2C0 (BIT(5)) +#define TEE_WRITE_REE0_I2C0_M (TEE_WRITE_REE0_I2C0_V << TEE_WRITE_REE0_I2C0_S) +#define TEE_WRITE_REE0_I2C0_V 0x00000001U +#define TEE_WRITE_REE0_I2C0_S 5 +/** TEE_WRITE_REE1_I2C0 : R/W; bitpos: [6]; default: 0; + * Configures i2c0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_I2C0 (BIT(6)) +#define TEE_WRITE_REE1_I2C0_M (TEE_WRITE_REE1_I2C0_V << TEE_WRITE_REE1_I2C0_S) +#define TEE_WRITE_REE1_I2C0_V 0x00000001U +#define TEE_WRITE_REE1_I2C0_S 6 +/** TEE_WRITE_REE2_I2C0 : R/W; bitpos: [7]; default: 0; + * Configures i2c0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_I2C0 (BIT(7)) +#define TEE_WRITE_REE2_I2C0_M (TEE_WRITE_REE2_I2C0_V << TEE_WRITE_REE2_I2C0_S) +#define TEE_WRITE_REE2_I2C0_V 0x00000001U +#define TEE_WRITE_REE2_I2C0_S 7 + +/** TEE_I2C1_CTRL_REG register + * i2c1 read/write control register + */ +#define TEE_I2C1_CTRL_REG (DR_REG_TEE_BASE + 0x98) +/** TEE_READ_TEE_I2C1 : R/W; bitpos: [0]; default: 1; + * Configures i2c1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_I2C1 (BIT(0)) +#define TEE_READ_TEE_I2C1_M (TEE_READ_TEE_I2C1_V << TEE_READ_TEE_I2C1_S) +#define TEE_READ_TEE_I2C1_V 0x00000001U +#define TEE_READ_TEE_I2C1_S 0 +/** TEE_READ_REE0_I2C1 : R/W; bitpos: [1]; default: 0; + * Configures i2c1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_I2C1 (BIT(1)) +#define TEE_READ_REE0_I2C1_M (TEE_READ_REE0_I2C1_V << TEE_READ_REE0_I2C1_S) +#define TEE_READ_REE0_I2C1_V 0x00000001U +#define TEE_READ_REE0_I2C1_S 1 +/** TEE_READ_REE1_I2C1 : R/W; bitpos: [2]; default: 0; + * Configures i2c1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_I2C1 (BIT(2)) +#define TEE_READ_REE1_I2C1_M (TEE_READ_REE1_I2C1_V << TEE_READ_REE1_I2C1_S) +#define TEE_READ_REE1_I2C1_V 0x00000001U +#define TEE_READ_REE1_I2C1_S 2 +/** TEE_READ_REE2_I2C1 : R/W; bitpos: [3]; default: 0; + * Configures i2c1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_I2C1 (BIT(3)) +#define TEE_READ_REE2_I2C1_M (TEE_READ_REE2_I2C1_V << TEE_READ_REE2_I2C1_S) +#define TEE_READ_REE2_I2C1_V 0x00000001U +#define TEE_READ_REE2_I2C1_S 3 +/** TEE_WRITE_TEE_I2C1 : R/W; bitpos: [4]; default: 1; + * Configures i2c1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_I2C1 (BIT(4)) +#define TEE_WRITE_TEE_I2C1_M (TEE_WRITE_TEE_I2C1_V << TEE_WRITE_TEE_I2C1_S) +#define TEE_WRITE_TEE_I2C1_V 0x00000001U +#define TEE_WRITE_TEE_I2C1_S 4 +/** TEE_WRITE_REE0_I2C1 : R/W; bitpos: [5]; default: 0; + * Configures i2c1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_I2C1 (BIT(5)) +#define TEE_WRITE_REE0_I2C1_M (TEE_WRITE_REE0_I2C1_V << TEE_WRITE_REE0_I2C1_S) +#define TEE_WRITE_REE0_I2C1_V 0x00000001U +#define TEE_WRITE_REE0_I2C1_S 5 +/** TEE_WRITE_REE1_I2C1 : R/W; bitpos: [6]; default: 0; + * Configures i2c1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_I2C1 (BIT(6)) +#define TEE_WRITE_REE1_I2C1_M (TEE_WRITE_REE1_I2C1_V << TEE_WRITE_REE1_I2C1_S) +#define TEE_WRITE_REE1_I2C1_V 0x00000001U +#define TEE_WRITE_REE1_I2C1_S 6 +/** TEE_WRITE_REE2_I2C1 : R/W; bitpos: [7]; default: 0; + * Configures i2c1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_I2C1 (BIT(7)) +#define TEE_WRITE_REE2_I2C1_M (TEE_WRITE_REE2_I2C1_V << TEE_WRITE_REE2_I2C1_S) +#define TEE_WRITE_REE2_I2C1_V 0x00000001U +#define TEE_WRITE_REE2_I2C1_S 7 + +/** TEE_I2S_CTRL_REG register + * i2s read/write control register + */ +#define TEE_I2S_CTRL_REG (DR_REG_TEE_BASE + 0x9c) +/** TEE_READ_TEE_I2S : R/W; bitpos: [0]; default: 1; + * Configures i2s registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_I2S (BIT(0)) +#define TEE_READ_TEE_I2S_M (TEE_READ_TEE_I2S_V << TEE_READ_TEE_I2S_S) +#define TEE_READ_TEE_I2S_V 0x00000001U +#define TEE_READ_TEE_I2S_S 0 +/** TEE_READ_REE0_I2S : R/W; bitpos: [1]; default: 0; + * Configures i2s registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_I2S (BIT(1)) +#define TEE_READ_REE0_I2S_M (TEE_READ_REE0_I2S_V << TEE_READ_REE0_I2S_S) +#define TEE_READ_REE0_I2S_V 0x00000001U +#define TEE_READ_REE0_I2S_S 1 +/** TEE_READ_REE1_I2S : R/W; bitpos: [2]; default: 0; + * Configures i2s registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_I2S (BIT(2)) +#define TEE_READ_REE1_I2S_M (TEE_READ_REE1_I2S_V << TEE_READ_REE1_I2S_S) +#define TEE_READ_REE1_I2S_V 0x00000001U +#define TEE_READ_REE1_I2S_S 2 +/** TEE_READ_REE2_I2S : R/W; bitpos: [3]; default: 0; + * Configures i2s registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_I2S (BIT(3)) +#define TEE_READ_REE2_I2S_M (TEE_READ_REE2_I2S_V << TEE_READ_REE2_I2S_S) +#define TEE_READ_REE2_I2S_V 0x00000001U +#define TEE_READ_REE2_I2S_S 3 +/** TEE_WRITE_TEE_I2S : R/W; bitpos: [4]; default: 1; + * Configures i2s registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_I2S (BIT(4)) +#define TEE_WRITE_TEE_I2S_M (TEE_WRITE_TEE_I2S_V << TEE_WRITE_TEE_I2S_S) +#define TEE_WRITE_TEE_I2S_V 0x00000001U +#define TEE_WRITE_TEE_I2S_S 4 +/** TEE_WRITE_REE0_I2S : R/W; bitpos: [5]; default: 0; + * Configures i2s registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_I2S (BIT(5)) +#define TEE_WRITE_REE0_I2S_M (TEE_WRITE_REE0_I2S_V << TEE_WRITE_REE0_I2S_S) +#define TEE_WRITE_REE0_I2S_V 0x00000001U +#define TEE_WRITE_REE0_I2S_S 5 +/** TEE_WRITE_REE1_I2S : R/W; bitpos: [6]; default: 0; + * Configures i2s registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_I2S (BIT(6)) +#define TEE_WRITE_REE1_I2S_M (TEE_WRITE_REE1_I2S_V << TEE_WRITE_REE1_I2S_S) +#define TEE_WRITE_REE1_I2S_V 0x00000001U +#define TEE_WRITE_REE1_I2S_S 6 +/** TEE_WRITE_REE2_I2S : R/W; bitpos: [7]; default: 0; + * Configures i2s registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_I2S (BIT(7)) +#define TEE_WRITE_REE2_I2S_M (TEE_WRITE_REE2_I2S_V << TEE_WRITE_REE2_I2S_S) +#define TEE_WRITE_REE2_I2S_V 0x00000001U +#define TEE_WRITE_REE2_I2S_S 7 + +/** TEE_PARL_IO_CTRL_REG register + * parl_io read/write control register + */ +#define TEE_PARL_IO_CTRL_REG (DR_REG_TEE_BASE + 0xa0) +/** TEE_READ_TEE_PARL_IO : R/W; bitpos: [0]; default: 1; + * Configures parl_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PARL_IO (BIT(0)) +#define TEE_READ_TEE_PARL_IO_M (TEE_READ_TEE_PARL_IO_V << TEE_READ_TEE_PARL_IO_S) +#define TEE_READ_TEE_PARL_IO_V 0x00000001U +#define TEE_READ_TEE_PARL_IO_S 0 +/** TEE_READ_REE0_PARL_IO : R/W; bitpos: [1]; default: 0; + * Configures parl_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PARL_IO (BIT(1)) +#define TEE_READ_REE0_PARL_IO_M (TEE_READ_REE0_PARL_IO_V << TEE_READ_REE0_PARL_IO_S) +#define TEE_READ_REE0_PARL_IO_V 0x00000001U +#define TEE_READ_REE0_PARL_IO_S 1 +/** TEE_READ_REE1_PARL_IO : R/W; bitpos: [2]; default: 0; + * Configures parl_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PARL_IO (BIT(2)) +#define TEE_READ_REE1_PARL_IO_M (TEE_READ_REE1_PARL_IO_V << TEE_READ_REE1_PARL_IO_S) +#define TEE_READ_REE1_PARL_IO_V 0x00000001U +#define TEE_READ_REE1_PARL_IO_S 2 +/** TEE_READ_REE2_PARL_IO : R/W; bitpos: [3]; default: 0; + * Configures parl_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PARL_IO (BIT(3)) +#define TEE_READ_REE2_PARL_IO_M (TEE_READ_REE2_PARL_IO_V << TEE_READ_REE2_PARL_IO_S) +#define TEE_READ_REE2_PARL_IO_V 0x00000001U +#define TEE_READ_REE2_PARL_IO_S 3 +/** TEE_WRITE_TEE_PARL_IO : R/W; bitpos: [4]; default: 1; + * Configures parl_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PARL_IO (BIT(4)) +#define TEE_WRITE_TEE_PARL_IO_M (TEE_WRITE_TEE_PARL_IO_V << TEE_WRITE_TEE_PARL_IO_S) +#define TEE_WRITE_TEE_PARL_IO_V 0x00000001U +#define TEE_WRITE_TEE_PARL_IO_S 4 +/** TEE_WRITE_REE0_PARL_IO : R/W; bitpos: [5]; default: 0; + * Configures parl_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PARL_IO (BIT(5)) +#define TEE_WRITE_REE0_PARL_IO_M (TEE_WRITE_REE0_PARL_IO_V << TEE_WRITE_REE0_PARL_IO_S) +#define TEE_WRITE_REE0_PARL_IO_V 0x00000001U +#define TEE_WRITE_REE0_PARL_IO_S 5 +/** TEE_WRITE_REE1_PARL_IO : R/W; bitpos: [6]; default: 0; + * Configures parl_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PARL_IO (BIT(6)) +#define TEE_WRITE_REE1_PARL_IO_M (TEE_WRITE_REE1_PARL_IO_V << TEE_WRITE_REE1_PARL_IO_S) +#define TEE_WRITE_REE1_PARL_IO_V 0x00000001U +#define TEE_WRITE_REE1_PARL_IO_S 6 +/** TEE_WRITE_REE2_PARL_IO : R/W; bitpos: [7]; default: 0; + * Configures parl_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PARL_IO (BIT(7)) +#define TEE_WRITE_REE2_PARL_IO_M (TEE_WRITE_REE2_PARL_IO_V << TEE_WRITE_REE2_PARL_IO_S) +#define TEE_WRITE_REE2_PARL_IO_V 0x00000001U +#define TEE_WRITE_REE2_PARL_IO_S 7 + +/** TEE_PWM0_CTRL_REG register + * pwm0 read/write control register + */ +#define TEE_PWM0_CTRL_REG (DR_REG_TEE_BASE + 0xa4) +/** TEE_READ_TEE_PWM0 : R/W; bitpos: [0]; default: 1; + * Configures pwm0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PWM0 (BIT(0)) +#define TEE_READ_TEE_PWM0_M (TEE_READ_TEE_PWM0_V << TEE_READ_TEE_PWM0_S) +#define TEE_READ_TEE_PWM0_V 0x00000001U +#define TEE_READ_TEE_PWM0_S 0 +/** TEE_READ_REE0_PWM0 : R/W; bitpos: [1]; default: 0; + * Configures pwm0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PWM0 (BIT(1)) +#define TEE_READ_REE0_PWM0_M (TEE_READ_REE0_PWM0_V << TEE_READ_REE0_PWM0_S) +#define TEE_READ_REE0_PWM0_V 0x00000001U +#define TEE_READ_REE0_PWM0_S 1 +/** TEE_READ_REE1_PWM0 : R/W; bitpos: [2]; default: 0; + * Configures pwm0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PWM0 (BIT(2)) +#define TEE_READ_REE1_PWM0_M (TEE_READ_REE1_PWM0_V << TEE_READ_REE1_PWM0_S) +#define TEE_READ_REE1_PWM0_V 0x00000001U +#define TEE_READ_REE1_PWM0_S 2 +/** TEE_READ_REE2_PWM0 : R/W; bitpos: [3]; default: 0; + * Configures pwm0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PWM0 (BIT(3)) +#define TEE_READ_REE2_PWM0_M (TEE_READ_REE2_PWM0_V << TEE_READ_REE2_PWM0_S) +#define TEE_READ_REE2_PWM0_V 0x00000001U +#define TEE_READ_REE2_PWM0_S 3 +/** TEE_WRITE_TEE_PWM0 : R/W; bitpos: [4]; default: 1; + * Configures pwm0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PWM0 (BIT(4)) +#define TEE_WRITE_TEE_PWM0_M (TEE_WRITE_TEE_PWM0_V << TEE_WRITE_TEE_PWM0_S) +#define TEE_WRITE_TEE_PWM0_V 0x00000001U +#define TEE_WRITE_TEE_PWM0_S 4 +/** TEE_WRITE_REE0_PWM0 : R/W; bitpos: [5]; default: 0; + * Configures pwm0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PWM0 (BIT(5)) +#define TEE_WRITE_REE0_PWM0_M (TEE_WRITE_REE0_PWM0_V << TEE_WRITE_REE0_PWM0_S) +#define TEE_WRITE_REE0_PWM0_V 0x00000001U +#define TEE_WRITE_REE0_PWM0_S 5 +/** TEE_WRITE_REE1_PWM0 : R/W; bitpos: [6]; default: 0; + * Configures pwm0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PWM0 (BIT(6)) +#define TEE_WRITE_REE1_PWM0_M (TEE_WRITE_REE1_PWM0_V << TEE_WRITE_REE1_PWM0_S) +#define TEE_WRITE_REE1_PWM0_V 0x00000001U +#define TEE_WRITE_REE1_PWM0_S 6 +/** TEE_WRITE_REE2_PWM0 : R/W; bitpos: [7]; default: 0; + * Configures pwm0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PWM0 (BIT(7)) +#define TEE_WRITE_REE2_PWM0_M (TEE_WRITE_REE2_PWM0_V << TEE_WRITE_REE2_PWM0_S) +#define TEE_WRITE_REE2_PWM0_V 0x00000001U +#define TEE_WRITE_REE2_PWM0_S 7 + +/** TEE_PWM1_CTRL_REG register + * pwm1 read/write control register + */ +#define TEE_PWM1_CTRL_REG (DR_REG_TEE_BASE + 0xa8) +/** TEE_READ_TEE_PWM1 : R/W; bitpos: [0]; default: 1; + * Configures pwm1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PWM1 (BIT(0)) +#define TEE_READ_TEE_PWM1_M (TEE_READ_TEE_PWM1_V << TEE_READ_TEE_PWM1_S) +#define TEE_READ_TEE_PWM1_V 0x00000001U +#define TEE_READ_TEE_PWM1_S 0 +/** TEE_READ_REE0_PWM1 : R/W; bitpos: [1]; default: 0; + * Configures pwm1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PWM1 (BIT(1)) +#define TEE_READ_REE0_PWM1_M (TEE_READ_REE0_PWM1_V << TEE_READ_REE0_PWM1_S) +#define TEE_READ_REE0_PWM1_V 0x00000001U +#define TEE_READ_REE0_PWM1_S 1 +/** TEE_READ_REE1_PWM1 : R/W; bitpos: [2]; default: 0; + * Configures pwm1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PWM1 (BIT(2)) +#define TEE_READ_REE1_PWM1_M (TEE_READ_REE1_PWM1_V << TEE_READ_REE1_PWM1_S) +#define TEE_READ_REE1_PWM1_V 0x00000001U +#define TEE_READ_REE1_PWM1_S 2 +/** TEE_READ_REE2_PWM1 : R/W; bitpos: [3]; default: 0; + * Configures pwm1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PWM1 (BIT(3)) +#define TEE_READ_REE2_PWM1_M (TEE_READ_REE2_PWM1_V << TEE_READ_REE2_PWM1_S) +#define TEE_READ_REE2_PWM1_V 0x00000001U +#define TEE_READ_REE2_PWM1_S 3 +/** TEE_WRITE_TEE_PWM1 : R/W; bitpos: [4]; default: 1; + * Configures pwm1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PWM1 (BIT(4)) +#define TEE_WRITE_TEE_PWM1_M (TEE_WRITE_TEE_PWM1_V << TEE_WRITE_TEE_PWM1_S) +#define TEE_WRITE_TEE_PWM1_V 0x00000001U +#define TEE_WRITE_TEE_PWM1_S 4 +/** TEE_WRITE_REE0_PWM1 : R/W; bitpos: [5]; default: 0; + * Configures pwm1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PWM1 (BIT(5)) +#define TEE_WRITE_REE0_PWM1_M (TEE_WRITE_REE0_PWM1_V << TEE_WRITE_REE0_PWM1_S) +#define TEE_WRITE_REE0_PWM1_V 0x00000001U +#define TEE_WRITE_REE0_PWM1_S 5 +/** TEE_WRITE_REE1_PWM1 : R/W; bitpos: [6]; default: 0; + * Configures pwm1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PWM1 (BIT(6)) +#define TEE_WRITE_REE1_PWM1_M (TEE_WRITE_REE1_PWM1_V << TEE_WRITE_REE1_PWM1_S) +#define TEE_WRITE_REE1_PWM1_V 0x00000001U +#define TEE_WRITE_REE1_PWM1_S 6 +/** TEE_WRITE_REE2_PWM1 : R/W; bitpos: [7]; default: 0; + * Configures pwm1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PWM1 (BIT(7)) +#define TEE_WRITE_REE2_PWM1_M (TEE_WRITE_REE2_PWM1_V << TEE_WRITE_REE2_PWM1_S) +#define TEE_WRITE_REE2_PWM1_V 0x00000001U +#define TEE_WRITE_REE2_PWM1_S 7 + +/** TEE_LEDC_CTRL_REG register + * ledc read/write control register + */ +#define TEE_LEDC_CTRL_REG (DR_REG_TEE_BASE + 0xac) +/** TEE_READ_TEE_LEDC : R/W; bitpos: [0]; default: 1; + * Configures ledc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_LEDC (BIT(0)) +#define TEE_READ_TEE_LEDC_M (TEE_READ_TEE_LEDC_V << TEE_READ_TEE_LEDC_S) +#define TEE_READ_TEE_LEDC_V 0x00000001U +#define TEE_READ_TEE_LEDC_S 0 +/** TEE_READ_REE0_LEDC : R/W; bitpos: [1]; default: 0; + * Configures ledc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_LEDC (BIT(1)) +#define TEE_READ_REE0_LEDC_M (TEE_READ_REE0_LEDC_V << TEE_READ_REE0_LEDC_S) +#define TEE_READ_REE0_LEDC_V 0x00000001U +#define TEE_READ_REE0_LEDC_S 1 +/** TEE_READ_REE1_LEDC : R/W; bitpos: [2]; default: 0; + * Configures ledc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_LEDC (BIT(2)) +#define TEE_READ_REE1_LEDC_M (TEE_READ_REE1_LEDC_V << TEE_READ_REE1_LEDC_S) +#define TEE_READ_REE1_LEDC_V 0x00000001U +#define TEE_READ_REE1_LEDC_S 2 +/** TEE_READ_REE2_LEDC : R/W; bitpos: [3]; default: 0; + * Configures ledc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_LEDC (BIT(3)) +#define TEE_READ_REE2_LEDC_M (TEE_READ_REE2_LEDC_V << TEE_READ_REE2_LEDC_S) +#define TEE_READ_REE2_LEDC_V 0x00000001U +#define TEE_READ_REE2_LEDC_S 3 +/** TEE_WRITE_TEE_LEDC : R/W; bitpos: [4]; default: 1; + * Configures ledc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_LEDC (BIT(4)) +#define TEE_WRITE_TEE_LEDC_M (TEE_WRITE_TEE_LEDC_V << TEE_WRITE_TEE_LEDC_S) +#define TEE_WRITE_TEE_LEDC_V 0x00000001U +#define TEE_WRITE_TEE_LEDC_S 4 +/** TEE_WRITE_REE0_LEDC : R/W; bitpos: [5]; default: 0; + * Configures ledc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_LEDC (BIT(5)) +#define TEE_WRITE_REE0_LEDC_M (TEE_WRITE_REE0_LEDC_V << TEE_WRITE_REE0_LEDC_S) +#define TEE_WRITE_REE0_LEDC_V 0x00000001U +#define TEE_WRITE_REE0_LEDC_S 5 +/** TEE_WRITE_REE1_LEDC : R/W; bitpos: [6]; default: 0; + * Configures ledc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_LEDC (BIT(6)) +#define TEE_WRITE_REE1_LEDC_M (TEE_WRITE_REE1_LEDC_V << TEE_WRITE_REE1_LEDC_S) +#define TEE_WRITE_REE1_LEDC_V 0x00000001U +#define TEE_WRITE_REE1_LEDC_S 6 +/** TEE_WRITE_REE2_LEDC : R/W; bitpos: [7]; default: 0; + * Configures ledc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_LEDC (BIT(7)) +#define TEE_WRITE_REE2_LEDC_M (TEE_WRITE_REE2_LEDC_V << TEE_WRITE_REE2_LEDC_S) +#define TEE_WRITE_REE2_LEDC_V 0x00000001U +#define TEE_WRITE_REE2_LEDC_S 7 + +/** TEE_CAN_CTRL_REG register + * can read/write control register + */ +#define TEE_CAN_CTRL_REG (DR_REG_TEE_BASE + 0xb0) +/** TEE_READ_TEE_CAN : R/W; bitpos: [0]; default: 1; + * Configures can registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CAN (BIT(0)) +#define TEE_READ_TEE_CAN_M (TEE_READ_TEE_CAN_V << TEE_READ_TEE_CAN_S) +#define TEE_READ_TEE_CAN_V 0x00000001U +#define TEE_READ_TEE_CAN_S 0 +/** TEE_READ_REE0_CAN : R/W; bitpos: [1]; default: 0; + * Configures can registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CAN (BIT(1)) +#define TEE_READ_REE0_CAN_M (TEE_READ_REE0_CAN_V << TEE_READ_REE0_CAN_S) +#define TEE_READ_REE0_CAN_V 0x00000001U +#define TEE_READ_REE0_CAN_S 1 +/** TEE_READ_REE1_CAN : R/W; bitpos: [2]; default: 0; + * Configures can registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CAN (BIT(2)) +#define TEE_READ_REE1_CAN_M (TEE_READ_REE1_CAN_V << TEE_READ_REE1_CAN_S) +#define TEE_READ_REE1_CAN_V 0x00000001U +#define TEE_READ_REE1_CAN_S 2 +/** TEE_READ_REE2_CAN : R/W; bitpos: [3]; default: 0; + * Configures can registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CAN (BIT(3)) +#define TEE_READ_REE2_CAN_M (TEE_READ_REE2_CAN_V << TEE_READ_REE2_CAN_S) +#define TEE_READ_REE2_CAN_V 0x00000001U +#define TEE_READ_REE2_CAN_S 3 +/** TEE_WRITE_TEE_CAN : R/W; bitpos: [4]; default: 1; + * Configures can registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CAN (BIT(4)) +#define TEE_WRITE_TEE_CAN_M (TEE_WRITE_TEE_CAN_V << TEE_WRITE_TEE_CAN_S) +#define TEE_WRITE_TEE_CAN_V 0x00000001U +#define TEE_WRITE_TEE_CAN_S 4 +/** TEE_WRITE_REE0_CAN : R/W; bitpos: [5]; default: 0; + * Configures can registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CAN (BIT(5)) +#define TEE_WRITE_REE0_CAN_M (TEE_WRITE_REE0_CAN_V << TEE_WRITE_REE0_CAN_S) +#define TEE_WRITE_REE0_CAN_V 0x00000001U +#define TEE_WRITE_REE0_CAN_S 5 +/** TEE_WRITE_REE1_CAN : R/W; bitpos: [6]; default: 0; + * Configures can registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CAN (BIT(6)) +#define TEE_WRITE_REE1_CAN_M (TEE_WRITE_REE1_CAN_V << TEE_WRITE_REE1_CAN_S) +#define TEE_WRITE_REE1_CAN_V 0x00000001U +#define TEE_WRITE_REE1_CAN_S 6 +/** TEE_WRITE_REE2_CAN : R/W; bitpos: [7]; default: 0; + * Configures can registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CAN (BIT(7)) +#define TEE_WRITE_REE2_CAN_M (TEE_WRITE_REE2_CAN_V << TEE_WRITE_REE2_CAN_S) +#define TEE_WRITE_REE2_CAN_V 0x00000001U +#define TEE_WRITE_REE2_CAN_S 7 + +/** TEE_USB_SERIAL_JTAG_CTRL_REG register + * usb_serial_jtag read/write control register + */ +#define TEE_USB_SERIAL_JTAG_CTRL_REG (DR_REG_TEE_BASE + 0xb4) +/** TEE_READ_TEE_USB_SERIAL_JTAG : R/W; bitpos: [0]; default: 1; + * Configures usb_serial_jtag registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_USB_SERIAL_JTAG (BIT(0)) +#define TEE_READ_TEE_USB_SERIAL_JTAG_M (TEE_READ_TEE_USB_SERIAL_JTAG_V << TEE_READ_TEE_USB_SERIAL_JTAG_S) +#define TEE_READ_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_TEE_USB_SERIAL_JTAG_S 0 +/** TEE_READ_REE0_USB_SERIAL_JTAG : R/W; bitpos: [1]; default: 0; + * Configures usb_serial_jtag registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_USB_SERIAL_JTAG (BIT(1)) +#define TEE_READ_REE0_USB_SERIAL_JTAG_M (TEE_READ_REE0_USB_SERIAL_JTAG_V << TEE_READ_REE0_USB_SERIAL_JTAG_S) +#define TEE_READ_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE0_USB_SERIAL_JTAG_S 1 +/** TEE_READ_REE1_USB_SERIAL_JTAG : R/W; bitpos: [2]; default: 0; + * Configures usb_serial_jtag registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_USB_SERIAL_JTAG (BIT(2)) +#define TEE_READ_REE1_USB_SERIAL_JTAG_M (TEE_READ_REE1_USB_SERIAL_JTAG_V << TEE_READ_REE1_USB_SERIAL_JTAG_S) +#define TEE_READ_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE1_USB_SERIAL_JTAG_S 2 +/** TEE_READ_REE2_USB_SERIAL_JTAG : R/W; bitpos: [3]; default: 0; + * Configures usb_serial_jtag registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_USB_SERIAL_JTAG (BIT(3)) +#define TEE_READ_REE2_USB_SERIAL_JTAG_M (TEE_READ_REE2_USB_SERIAL_JTAG_V << TEE_READ_REE2_USB_SERIAL_JTAG_S) +#define TEE_READ_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE2_USB_SERIAL_JTAG_S 3 +/** TEE_WRITE_TEE_USB_SERIAL_JTAG : R/W; bitpos: [4]; default: 1; + * Configures usb_serial_jtag registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_USB_SERIAL_JTAG (BIT(4)) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_M (TEE_WRITE_TEE_USB_SERIAL_JTAG_V << TEE_WRITE_TEE_USB_SERIAL_JTAG_S) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_S 4 +/** TEE_WRITE_REE0_USB_SERIAL_JTAG : R/W; bitpos: [5]; default: 0; + * Configures usb_serial_jtag registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_USB_SERIAL_JTAG (BIT(5)) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_M (TEE_WRITE_REE0_USB_SERIAL_JTAG_V << TEE_WRITE_REE0_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_S 5 +/** TEE_WRITE_REE1_USB_SERIAL_JTAG : R/W; bitpos: [6]; default: 0; + * Configures usb_serial_jtag registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_USB_SERIAL_JTAG (BIT(6)) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_M (TEE_WRITE_REE1_USB_SERIAL_JTAG_V << TEE_WRITE_REE1_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_S 6 +/** TEE_WRITE_REE2_USB_SERIAL_JTAG : R/W; bitpos: [7]; default: 0; + * Configures usb_serial_jtag registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_USB_SERIAL_JTAG (BIT(7)) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_M (TEE_WRITE_REE2_USB_SERIAL_JTAG_V << TEE_WRITE_REE2_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_S 7 + +/** TEE_RMT_CTRL_REG register + * rmt read/write control register + */ +#define TEE_RMT_CTRL_REG (DR_REG_TEE_BASE + 0xb8) +/** TEE_READ_TEE_RMT : R/W; bitpos: [0]; default: 1; + * Configures rmt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_RMT (BIT(0)) +#define TEE_READ_TEE_RMT_M (TEE_READ_TEE_RMT_V << TEE_READ_TEE_RMT_S) +#define TEE_READ_TEE_RMT_V 0x00000001U +#define TEE_READ_TEE_RMT_S 0 +/** TEE_READ_REE0_RMT : R/W; bitpos: [1]; default: 0; + * Configures rmt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_RMT (BIT(1)) +#define TEE_READ_REE0_RMT_M (TEE_READ_REE0_RMT_V << TEE_READ_REE0_RMT_S) +#define TEE_READ_REE0_RMT_V 0x00000001U +#define TEE_READ_REE0_RMT_S 1 +/** TEE_READ_REE1_RMT : R/W; bitpos: [2]; default: 0; + * Configures rmt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_RMT (BIT(2)) +#define TEE_READ_REE1_RMT_M (TEE_READ_REE1_RMT_V << TEE_READ_REE1_RMT_S) +#define TEE_READ_REE1_RMT_V 0x00000001U +#define TEE_READ_REE1_RMT_S 2 +/** TEE_READ_REE2_RMT : R/W; bitpos: [3]; default: 0; + * Configures rmt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_RMT (BIT(3)) +#define TEE_READ_REE2_RMT_M (TEE_READ_REE2_RMT_V << TEE_READ_REE2_RMT_S) +#define TEE_READ_REE2_RMT_V 0x00000001U +#define TEE_READ_REE2_RMT_S 3 +/** TEE_WRITE_TEE_RMT : R/W; bitpos: [4]; default: 1; + * Configures rmt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_RMT (BIT(4)) +#define TEE_WRITE_TEE_RMT_M (TEE_WRITE_TEE_RMT_V << TEE_WRITE_TEE_RMT_S) +#define TEE_WRITE_TEE_RMT_V 0x00000001U +#define TEE_WRITE_TEE_RMT_S 4 +/** TEE_WRITE_REE0_RMT : R/W; bitpos: [5]; default: 0; + * Configures rmt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_RMT (BIT(5)) +#define TEE_WRITE_REE0_RMT_M (TEE_WRITE_REE0_RMT_V << TEE_WRITE_REE0_RMT_S) +#define TEE_WRITE_REE0_RMT_V 0x00000001U +#define TEE_WRITE_REE0_RMT_S 5 +/** TEE_WRITE_REE1_RMT : R/W; bitpos: [6]; default: 0; + * Configures rmt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_RMT (BIT(6)) +#define TEE_WRITE_REE1_RMT_M (TEE_WRITE_REE1_RMT_V << TEE_WRITE_REE1_RMT_S) +#define TEE_WRITE_REE1_RMT_V 0x00000001U +#define TEE_WRITE_REE1_RMT_S 6 +/** TEE_WRITE_REE2_RMT : R/W; bitpos: [7]; default: 0; + * Configures rmt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_RMT (BIT(7)) +#define TEE_WRITE_REE2_RMT_M (TEE_WRITE_REE2_RMT_V << TEE_WRITE_REE2_RMT_S) +#define TEE_WRITE_REE2_RMT_V 0x00000001U +#define TEE_WRITE_REE2_RMT_S 7 + +/** TEE_GDMA_CTRL_REG register + * gdma read/write control register + */ +#define TEE_GDMA_CTRL_REG (DR_REG_TEE_BASE + 0xbc) +/** TEE_READ_TEE_GDMA : R/W; bitpos: [0]; default: 1; + * Configures gdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_GDMA (BIT(0)) +#define TEE_READ_TEE_GDMA_M (TEE_READ_TEE_GDMA_V << TEE_READ_TEE_GDMA_S) +#define TEE_READ_TEE_GDMA_V 0x00000001U +#define TEE_READ_TEE_GDMA_S 0 +/** TEE_READ_REE0_GDMA : R/W; bitpos: [1]; default: 0; + * Configures gdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_GDMA (BIT(1)) +#define TEE_READ_REE0_GDMA_M (TEE_READ_REE0_GDMA_V << TEE_READ_REE0_GDMA_S) +#define TEE_READ_REE0_GDMA_V 0x00000001U +#define TEE_READ_REE0_GDMA_S 1 +/** TEE_READ_REE1_GDMA : R/W; bitpos: [2]; default: 0; + * Configures gdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_GDMA (BIT(2)) +#define TEE_READ_REE1_GDMA_M (TEE_READ_REE1_GDMA_V << TEE_READ_REE1_GDMA_S) +#define TEE_READ_REE1_GDMA_V 0x00000001U +#define TEE_READ_REE1_GDMA_S 2 +/** TEE_READ_REE2_GDMA : R/W; bitpos: [3]; default: 0; + * Configures gdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_GDMA (BIT(3)) +#define TEE_READ_REE2_GDMA_M (TEE_READ_REE2_GDMA_V << TEE_READ_REE2_GDMA_S) +#define TEE_READ_REE2_GDMA_V 0x00000001U +#define TEE_READ_REE2_GDMA_S 3 +/** TEE_WRITE_TEE_GDMA : R/W; bitpos: [4]; default: 1; + * Configures gdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_GDMA (BIT(4)) +#define TEE_WRITE_TEE_GDMA_M (TEE_WRITE_TEE_GDMA_V << TEE_WRITE_TEE_GDMA_S) +#define TEE_WRITE_TEE_GDMA_V 0x00000001U +#define TEE_WRITE_TEE_GDMA_S 4 +/** TEE_WRITE_REE0_GDMA : R/W; bitpos: [5]; default: 0; + * Configures gdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_GDMA (BIT(5)) +#define TEE_WRITE_REE0_GDMA_M (TEE_WRITE_REE0_GDMA_V << TEE_WRITE_REE0_GDMA_S) +#define TEE_WRITE_REE0_GDMA_V 0x00000001U +#define TEE_WRITE_REE0_GDMA_S 5 +/** TEE_WRITE_REE1_GDMA : R/W; bitpos: [6]; default: 0; + * Configures gdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_GDMA (BIT(6)) +#define TEE_WRITE_REE1_GDMA_M (TEE_WRITE_REE1_GDMA_V << TEE_WRITE_REE1_GDMA_S) +#define TEE_WRITE_REE1_GDMA_V 0x00000001U +#define TEE_WRITE_REE1_GDMA_S 6 +/** TEE_WRITE_REE2_GDMA : R/W; bitpos: [7]; default: 0; + * Configures gdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_GDMA (BIT(7)) +#define TEE_WRITE_REE2_GDMA_M (TEE_WRITE_REE2_GDMA_V << TEE_WRITE_REE2_GDMA_S) +#define TEE_WRITE_REE2_GDMA_V 0x00000001U +#define TEE_WRITE_REE2_GDMA_S 7 + +/** TEE_REGDMA_CTRL_REG register + * regdma read/write control register + */ +#define TEE_REGDMA_CTRL_REG (DR_REG_TEE_BASE + 0xc0) +/** TEE_READ_TEE_REGDMA : R/W; bitpos: [0]; default: 1; + * Configures regdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_REGDMA (BIT(0)) +#define TEE_READ_TEE_REGDMA_M (TEE_READ_TEE_REGDMA_V << TEE_READ_TEE_REGDMA_S) +#define TEE_READ_TEE_REGDMA_V 0x00000001U +#define TEE_READ_TEE_REGDMA_S 0 +/** TEE_READ_REE0_REGDMA : R/W; bitpos: [1]; default: 0; + * Configures regdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_REGDMA (BIT(1)) +#define TEE_READ_REE0_REGDMA_M (TEE_READ_REE0_REGDMA_V << TEE_READ_REE0_REGDMA_S) +#define TEE_READ_REE0_REGDMA_V 0x00000001U +#define TEE_READ_REE0_REGDMA_S 1 +/** TEE_READ_REE1_REGDMA : R/W; bitpos: [2]; default: 0; + * Configures regdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_REGDMA (BIT(2)) +#define TEE_READ_REE1_REGDMA_M (TEE_READ_REE1_REGDMA_V << TEE_READ_REE1_REGDMA_S) +#define TEE_READ_REE1_REGDMA_V 0x00000001U +#define TEE_READ_REE1_REGDMA_S 2 +/** TEE_READ_REE2_REGDMA : R/W; bitpos: [3]; default: 0; + * Configures regdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_REGDMA (BIT(3)) +#define TEE_READ_REE2_REGDMA_M (TEE_READ_REE2_REGDMA_V << TEE_READ_REE2_REGDMA_S) +#define TEE_READ_REE2_REGDMA_V 0x00000001U +#define TEE_READ_REE2_REGDMA_S 3 +/** TEE_WRITE_TEE_REGDMA : R/W; bitpos: [4]; default: 1; + * Configures regdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_REGDMA (BIT(4)) +#define TEE_WRITE_TEE_REGDMA_M (TEE_WRITE_TEE_REGDMA_V << TEE_WRITE_TEE_REGDMA_S) +#define TEE_WRITE_TEE_REGDMA_V 0x00000001U +#define TEE_WRITE_TEE_REGDMA_S 4 +/** TEE_WRITE_REE0_REGDMA : R/W; bitpos: [5]; default: 0; + * Configures regdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_REGDMA (BIT(5)) +#define TEE_WRITE_REE0_REGDMA_M (TEE_WRITE_REE0_REGDMA_V << TEE_WRITE_REE0_REGDMA_S) +#define TEE_WRITE_REE0_REGDMA_V 0x00000001U +#define TEE_WRITE_REE0_REGDMA_S 5 +/** TEE_WRITE_REE1_REGDMA : R/W; bitpos: [6]; default: 0; + * Configures regdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_REGDMA (BIT(6)) +#define TEE_WRITE_REE1_REGDMA_M (TEE_WRITE_REE1_REGDMA_V << TEE_WRITE_REE1_REGDMA_S) +#define TEE_WRITE_REE1_REGDMA_V 0x00000001U +#define TEE_WRITE_REE1_REGDMA_S 6 +/** TEE_WRITE_REE2_REGDMA : R/W; bitpos: [7]; default: 0; + * Configures regdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_REGDMA (BIT(7)) +#define TEE_WRITE_REE2_REGDMA_M (TEE_WRITE_REE2_REGDMA_V << TEE_WRITE_REE2_REGDMA_S) +#define TEE_WRITE_REE2_REGDMA_V 0x00000001U +#define TEE_WRITE_REE2_REGDMA_S 7 + +/** TEE_ETM_CTRL_REG register + * etm read/write control register + */ +#define TEE_ETM_CTRL_REG (DR_REG_TEE_BASE + 0xc4) +/** TEE_READ_TEE_ETM : R/W; bitpos: [0]; default: 1; + * Configures etm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_ETM (BIT(0)) +#define TEE_READ_TEE_ETM_M (TEE_READ_TEE_ETM_V << TEE_READ_TEE_ETM_S) +#define TEE_READ_TEE_ETM_V 0x00000001U +#define TEE_READ_TEE_ETM_S 0 +/** TEE_READ_REE0_ETM : R/W; bitpos: [1]; default: 0; + * Configures etm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_ETM (BIT(1)) +#define TEE_READ_REE0_ETM_M (TEE_READ_REE0_ETM_V << TEE_READ_REE0_ETM_S) +#define TEE_READ_REE0_ETM_V 0x00000001U +#define TEE_READ_REE0_ETM_S 1 +/** TEE_READ_REE1_ETM : R/W; bitpos: [2]; default: 0; + * Configures etm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_ETM (BIT(2)) +#define TEE_READ_REE1_ETM_M (TEE_READ_REE1_ETM_V << TEE_READ_REE1_ETM_S) +#define TEE_READ_REE1_ETM_V 0x00000001U +#define TEE_READ_REE1_ETM_S 2 +/** TEE_READ_REE2_ETM : R/W; bitpos: [3]; default: 0; + * Configures etm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_ETM (BIT(3)) +#define TEE_READ_REE2_ETM_M (TEE_READ_REE2_ETM_V << TEE_READ_REE2_ETM_S) +#define TEE_READ_REE2_ETM_V 0x00000001U +#define TEE_READ_REE2_ETM_S 3 +/** TEE_WRITE_TEE_ETM : R/W; bitpos: [4]; default: 1; + * Configures etm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_ETM (BIT(4)) +#define TEE_WRITE_TEE_ETM_M (TEE_WRITE_TEE_ETM_V << TEE_WRITE_TEE_ETM_S) +#define TEE_WRITE_TEE_ETM_V 0x00000001U +#define TEE_WRITE_TEE_ETM_S 4 +/** TEE_WRITE_REE0_ETM : R/W; bitpos: [5]; default: 0; + * Configures etm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_ETM (BIT(5)) +#define TEE_WRITE_REE0_ETM_M (TEE_WRITE_REE0_ETM_V << TEE_WRITE_REE0_ETM_S) +#define TEE_WRITE_REE0_ETM_V 0x00000001U +#define TEE_WRITE_REE0_ETM_S 5 +/** TEE_WRITE_REE1_ETM : R/W; bitpos: [6]; default: 0; + * Configures etm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_ETM (BIT(6)) +#define TEE_WRITE_REE1_ETM_M (TEE_WRITE_REE1_ETM_V << TEE_WRITE_REE1_ETM_S) +#define TEE_WRITE_REE1_ETM_V 0x00000001U +#define TEE_WRITE_REE1_ETM_S 6 +/** TEE_WRITE_REE2_ETM : R/W; bitpos: [7]; default: 0; + * Configures etm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_ETM (BIT(7)) +#define TEE_WRITE_REE2_ETM_M (TEE_WRITE_REE2_ETM_V << TEE_WRITE_REE2_ETM_S) +#define TEE_WRITE_REE2_ETM_V 0x00000001U +#define TEE_WRITE_REE2_ETM_S 7 + +/** TEE_INTMTX_CORE0_CTRL_REG register + * intmtx_core0 read/write control register + */ +#define TEE_INTMTX_CORE0_CTRL_REG (DR_REG_TEE_BASE + 0xc8) +/** TEE_READ_TEE_INTMTX_CORE0 : R/W; bitpos: [0]; default: 1; + * Configures intmtx_core0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_INTMTX_CORE0 (BIT(0)) +#define TEE_READ_TEE_INTMTX_CORE0_M (TEE_READ_TEE_INTMTX_CORE0_V << TEE_READ_TEE_INTMTX_CORE0_S) +#define TEE_READ_TEE_INTMTX_CORE0_V 0x00000001U +#define TEE_READ_TEE_INTMTX_CORE0_S 0 +/** TEE_READ_REE0_INTMTX_CORE0 : R/W; bitpos: [1]; default: 0; + * Configures intmtx_core0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_INTMTX_CORE0 (BIT(1)) +#define TEE_READ_REE0_INTMTX_CORE0_M (TEE_READ_REE0_INTMTX_CORE0_V << TEE_READ_REE0_INTMTX_CORE0_S) +#define TEE_READ_REE0_INTMTX_CORE0_V 0x00000001U +#define TEE_READ_REE0_INTMTX_CORE0_S 1 +/** TEE_READ_REE1_INTMTX_CORE0 : R/W; bitpos: [2]; default: 0; + * Configures intmtx_core0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_INTMTX_CORE0 (BIT(2)) +#define TEE_READ_REE1_INTMTX_CORE0_M (TEE_READ_REE1_INTMTX_CORE0_V << TEE_READ_REE1_INTMTX_CORE0_S) +#define TEE_READ_REE1_INTMTX_CORE0_V 0x00000001U +#define TEE_READ_REE1_INTMTX_CORE0_S 2 +/** TEE_READ_REE2_INTMTX_CORE0 : R/W; bitpos: [3]; default: 0; + * Configures intmtx_core0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_INTMTX_CORE0 (BIT(3)) +#define TEE_READ_REE2_INTMTX_CORE0_M (TEE_READ_REE2_INTMTX_CORE0_V << TEE_READ_REE2_INTMTX_CORE0_S) +#define TEE_READ_REE2_INTMTX_CORE0_V 0x00000001U +#define TEE_READ_REE2_INTMTX_CORE0_S 3 +/** TEE_WRITE_TEE_INTMTX_CORE0 : R/W; bitpos: [4]; default: 1; + * Configures intmtx_core0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_INTMTX_CORE0 (BIT(4)) +#define TEE_WRITE_TEE_INTMTX_CORE0_M (TEE_WRITE_TEE_INTMTX_CORE0_V << TEE_WRITE_TEE_INTMTX_CORE0_S) +#define TEE_WRITE_TEE_INTMTX_CORE0_V 0x00000001U +#define TEE_WRITE_TEE_INTMTX_CORE0_S 4 +/** TEE_WRITE_REE0_INTMTX_CORE0 : R/W; bitpos: [5]; default: 0; + * Configures intmtx_core0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_INTMTX_CORE0 (BIT(5)) +#define TEE_WRITE_REE0_INTMTX_CORE0_M (TEE_WRITE_REE0_INTMTX_CORE0_V << TEE_WRITE_REE0_INTMTX_CORE0_S) +#define TEE_WRITE_REE0_INTMTX_CORE0_V 0x00000001U +#define TEE_WRITE_REE0_INTMTX_CORE0_S 5 +/** TEE_WRITE_REE1_INTMTX_CORE0 : R/W; bitpos: [6]; default: 0; + * Configures intmtx_core0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_INTMTX_CORE0 (BIT(6)) +#define TEE_WRITE_REE1_INTMTX_CORE0_M (TEE_WRITE_REE1_INTMTX_CORE0_V << TEE_WRITE_REE1_INTMTX_CORE0_S) +#define TEE_WRITE_REE1_INTMTX_CORE0_V 0x00000001U +#define TEE_WRITE_REE1_INTMTX_CORE0_S 6 +/** TEE_WRITE_REE2_INTMTX_CORE0 : R/W; bitpos: [7]; default: 0; + * Configures intmtx_core0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_INTMTX_CORE0 (BIT(7)) +#define TEE_WRITE_REE2_INTMTX_CORE0_M (TEE_WRITE_REE2_INTMTX_CORE0_V << TEE_WRITE_REE2_INTMTX_CORE0_S) +#define TEE_WRITE_REE2_INTMTX_CORE0_V 0x00000001U +#define TEE_WRITE_REE2_INTMTX_CORE0_S 7 + +/** TEE_INTMTX_CORE1_CTRL_REG register + * intmtx_core1 read/write control register + */ +#define TEE_INTMTX_CORE1_CTRL_REG (DR_REG_TEE_BASE + 0xcc) +/** TEE_READ_TEE_INTMTX_CORE1 : R/W; bitpos: [0]; default: 1; + * Configures intmtx_core1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_INTMTX_CORE1 (BIT(0)) +#define TEE_READ_TEE_INTMTX_CORE1_M (TEE_READ_TEE_INTMTX_CORE1_V << TEE_READ_TEE_INTMTX_CORE1_S) +#define TEE_READ_TEE_INTMTX_CORE1_V 0x00000001U +#define TEE_READ_TEE_INTMTX_CORE1_S 0 +/** TEE_READ_REE0_INTMTX_CORE1 : R/W; bitpos: [1]; default: 0; + * Configures intmtx_core1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_INTMTX_CORE1 (BIT(1)) +#define TEE_READ_REE0_INTMTX_CORE1_M (TEE_READ_REE0_INTMTX_CORE1_V << TEE_READ_REE0_INTMTX_CORE1_S) +#define TEE_READ_REE0_INTMTX_CORE1_V 0x00000001U +#define TEE_READ_REE0_INTMTX_CORE1_S 1 +/** TEE_READ_REE1_INTMTX_CORE1 : R/W; bitpos: [2]; default: 0; + * Configures intmtx_core1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_INTMTX_CORE1 (BIT(2)) +#define TEE_READ_REE1_INTMTX_CORE1_M (TEE_READ_REE1_INTMTX_CORE1_V << TEE_READ_REE1_INTMTX_CORE1_S) +#define TEE_READ_REE1_INTMTX_CORE1_V 0x00000001U +#define TEE_READ_REE1_INTMTX_CORE1_S 2 +/** TEE_READ_REE2_INTMTX_CORE1 : R/W; bitpos: [3]; default: 0; + * Configures intmtx_core1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_INTMTX_CORE1 (BIT(3)) +#define TEE_READ_REE2_INTMTX_CORE1_M (TEE_READ_REE2_INTMTX_CORE1_V << TEE_READ_REE2_INTMTX_CORE1_S) +#define TEE_READ_REE2_INTMTX_CORE1_V 0x00000001U +#define TEE_READ_REE2_INTMTX_CORE1_S 3 +/** TEE_WRITE_TEE_INTMTX_CORE1 : R/W; bitpos: [4]; default: 1; + * Configures intmtx_core1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_INTMTX_CORE1 (BIT(4)) +#define TEE_WRITE_TEE_INTMTX_CORE1_M (TEE_WRITE_TEE_INTMTX_CORE1_V << TEE_WRITE_TEE_INTMTX_CORE1_S) +#define TEE_WRITE_TEE_INTMTX_CORE1_V 0x00000001U +#define TEE_WRITE_TEE_INTMTX_CORE1_S 4 +/** TEE_WRITE_REE0_INTMTX_CORE1 : R/W; bitpos: [5]; default: 0; + * Configures intmtx_core1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_INTMTX_CORE1 (BIT(5)) +#define TEE_WRITE_REE0_INTMTX_CORE1_M (TEE_WRITE_REE0_INTMTX_CORE1_V << TEE_WRITE_REE0_INTMTX_CORE1_S) +#define TEE_WRITE_REE0_INTMTX_CORE1_V 0x00000001U +#define TEE_WRITE_REE0_INTMTX_CORE1_S 5 +/** TEE_WRITE_REE1_INTMTX_CORE1 : R/W; bitpos: [6]; default: 0; + * Configures intmtx_core1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_INTMTX_CORE1 (BIT(6)) +#define TEE_WRITE_REE1_INTMTX_CORE1_M (TEE_WRITE_REE1_INTMTX_CORE1_V << TEE_WRITE_REE1_INTMTX_CORE1_S) +#define TEE_WRITE_REE1_INTMTX_CORE1_V 0x00000001U +#define TEE_WRITE_REE1_INTMTX_CORE1_S 6 +/** TEE_WRITE_REE2_INTMTX_CORE1 : R/W; bitpos: [7]; default: 0; + * Configures intmtx_core1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_INTMTX_CORE1 (BIT(7)) +#define TEE_WRITE_REE2_INTMTX_CORE1_M (TEE_WRITE_REE2_INTMTX_CORE1_V << TEE_WRITE_REE2_INTMTX_CORE1_S) +#define TEE_WRITE_REE2_INTMTX_CORE1_V 0x00000001U +#define TEE_WRITE_REE2_INTMTX_CORE1_S 7 + +/** TEE_APB_ADC_CTRL_REG register + * apb_adc read/write control register + */ +#define TEE_APB_ADC_CTRL_REG (DR_REG_TEE_BASE + 0xd0) +/** TEE_READ_TEE_APB_ADC : R/W; bitpos: [0]; default: 1; + * Configures apb_adc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_APB_ADC (BIT(0)) +#define TEE_READ_TEE_APB_ADC_M (TEE_READ_TEE_APB_ADC_V << TEE_READ_TEE_APB_ADC_S) +#define TEE_READ_TEE_APB_ADC_V 0x00000001U +#define TEE_READ_TEE_APB_ADC_S 0 +/** TEE_READ_REE0_APB_ADC : R/W; bitpos: [1]; default: 0; + * Configures apb_adc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_APB_ADC (BIT(1)) +#define TEE_READ_REE0_APB_ADC_M (TEE_READ_REE0_APB_ADC_V << TEE_READ_REE0_APB_ADC_S) +#define TEE_READ_REE0_APB_ADC_V 0x00000001U +#define TEE_READ_REE0_APB_ADC_S 1 +/** TEE_READ_REE1_APB_ADC : R/W; bitpos: [2]; default: 0; + * Configures apb_adc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_APB_ADC (BIT(2)) +#define TEE_READ_REE1_APB_ADC_M (TEE_READ_REE1_APB_ADC_V << TEE_READ_REE1_APB_ADC_S) +#define TEE_READ_REE1_APB_ADC_V 0x00000001U +#define TEE_READ_REE1_APB_ADC_S 2 +/** TEE_READ_REE2_APB_ADC : R/W; bitpos: [3]; default: 0; + * Configures apb_adc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_APB_ADC (BIT(3)) +#define TEE_READ_REE2_APB_ADC_M (TEE_READ_REE2_APB_ADC_V << TEE_READ_REE2_APB_ADC_S) +#define TEE_READ_REE2_APB_ADC_V 0x00000001U +#define TEE_READ_REE2_APB_ADC_S 3 +/** TEE_WRITE_TEE_APB_ADC : R/W; bitpos: [4]; default: 1; + * Configures apb_adc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_APB_ADC (BIT(4)) +#define TEE_WRITE_TEE_APB_ADC_M (TEE_WRITE_TEE_APB_ADC_V << TEE_WRITE_TEE_APB_ADC_S) +#define TEE_WRITE_TEE_APB_ADC_V 0x00000001U +#define TEE_WRITE_TEE_APB_ADC_S 4 +/** TEE_WRITE_REE0_APB_ADC : R/W; bitpos: [5]; default: 0; + * Configures apb_adc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_APB_ADC (BIT(5)) +#define TEE_WRITE_REE0_APB_ADC_M (TEE_WRITE_REE0_APB_ADC_V << TEE_WRITE_REE0_APB_ADC_S) +#define TEE_WRITE_REE0_APB_ADC_V 0x00000001U +#define TEE_WRITE_REE0_APB_ADC_S 5 +/** TEE_WRITE_REE1_APB_ADC : R/W; bitpos: [6]; default: 0; + * Configures apb_adc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_APB_ADC (BIT(6)) +#define TEE_WRITE_REE1_APB_ADC_M (TEE_WRITE_REE1_APB_ADC_V << TEE_WRITE_REE1_APB_ADC_S) +#define TEE_WRITE_REE1_APB_ADC_V 0x00000001U +#define TEE_WRITE_REE1_APB_ADC_S 6 +/** TEE_WRITE_REE2_APB_ADC : R/W; bitpos: [7]; default: 0; + * Configures apb_adc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_APB_ADC (BIT(7)) +#define TEE_WRITE_REE2_APB_ADC_M (TEE_WRITE_REE2_APB_ADC_V << TEE_WRITE_REE2_APB_ADC_S) +#define TEE_WRITE_REE2_APB_ADC_V 0x00000001U +#define TEE_WRITE_REE2_APB_ADC_S 7 + +/** TEE_TIMERGROUP0_CTRL_REG register + * timergroup0 read/write control register + */ +#define TEE_TIMERGROUP0_CTRL_REG (DR_REG_TEE_BASE + 0xd4) +/** TEE_READ_TEE_TIMERGROUP0 : R/W; bitpos: [0]; default: 1; + * Configures timergroup0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TIMERGROUP0 (BIT(0)) +#define TEE_READ_TEE_TIMERGROUP0_M (TEE_READ_TEE_TIMERGROUP0_V << TEE_READ_TEE_TIMERGROUP0_S) +#define TEE_READ_TEE_TIMERGROUP0_V 0x00000001U +#define TEE_READ_TEE_TIMERGROUP0_S 0 +/** TEE_READ_REE0_TIMERGROUP0 : R/W; bitpos: [1]; default: 0; + * Configures timergroup0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TIMERGROUP0 (BIT(1)) +#define TEE_READ_REE0_TIMERGROUP0_M (TEE_READ_REE0_TIMERGROUP0_V << TEE_READ_REE0_TIMERGROUP0_S) +#define TEE_READ_REE0_TIMERGROUP0_V 0x00000001U +#define TEE_READ_REE0_TIMERGROUP0_S 1 +/** TEE_READ_REE1_TIMERGROUP0 : R/W; bitpos: [2]; default: 0; + * Configures timergroup0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TIMERGROUP0 (BIT(2)) +#define TEE_READ_REE1_TIMERGROUP0_M (TEE_READ_REE1_TIMERGROUP0_V << TEE_READ_REE1_TIMERGROUP0_S) +#define TEE_READ_REE1_TIMERGROUP0_V 0x00000001U +#define TEE_READ_REE1_TIMERGROUP0_S 2 +/** TEE_READ_REE2_TIMERGROUP0 : R/W; bitpos: [3]; default: 0; + * Configures timergroup0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TIMERGROUP0 (BIT(3)) +#define TEE_READ_REE2_TIMERGROUP0_M (TEE_READ_REE2_TIMERGROUP0_V << TEE_READ_REE2_TIMERGROUP0_S) +#define TEE_READ_REE2_TIMERGROUP0_V 0x00000001U +#define TEE_READ_REE2_TIMERGROUP0_S 3 +/** TEE_WRITE_TEE_TIMERGROUP0 : R/W; bitpos: [4]; default: 1; + * Configures timergroup0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TIMERGROUP0 (BIT(4)) +#define TEE_WRITE_TEE_TIMERGROUP0_M (TEE_WRITE_TEE_TIMERGROUP0_V << TEE_WRITE_TEE_TIMERGROUP0_S) +#define TEE_WRITE_TEE_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_TEE_TIMERGROUP0_S 4 +/** TEE_WRITE_REE0_TIMERGROUP0 : R/W; bitpos: [5]; default: 0; + * Configures timergroup0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TIMERGROUP0 (BIT(5)) +#define TEE_WRITE_REE0_TIMERGROUP0_M (TEE_WRITE_REE0_TIMERGROUP0_V << TEE_WRITE_REE0_TIMERGROUP0_S) +#define TEE_WRITE_REE0_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_REE0_TIMERGROUP0_S 5 +/** TEE_WRITE_REE1_TIMERGROUP0 : R/W; bitpos: [6]; default: 0; + * Configures timergroup0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TIMERGROUP0 (BIT(6)) +#define TEE_WRITE_REE1_TIMERGROUP0_M (TEE_WRITE_REE1_TIMERGROUP0_V << TEE_WRITE_REE1_TIMERGROUP0_S) +#define TEE_WRITE_REE1_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_REE1_TIMERGROUP0_S 6 +/** TEE_WRITE_REE2_TIMERGROUP0 : R/W; bitpos: [7]; default: 0; + * Configures timergroup0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TIMERGROUP0 (BIT(7)) +#define TEE_WRITE_REE2_TIMERGROUP0_M (TEE_WRITE_REE2_TIMERGROUP0_V << TEE_WRITE_REE2_TIMERGROUP0_S) +#define TEE_WRITE_REE2_TIMERGROUP0_V 0x00000001U +#define TEE_WRITE_REE2_TIMERGROUP0_S 7 + +/** TEE_TIMERGROUP1_CTRL_REG register + * timergroup1 read/write control register + */ +#define TEE_TIMERGROUP1_CTRL_REG (DR_REG_TEE_BASE + 0xd8) +/** TEE_READ_TEE_TIMERGROUP1 : R/W; bitpos: [0]; default: 1; + * Configures timergroup1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TIMERGROUP1 (BIT(0)) +#define TEE_READ_TEE_TIMERGROUP1_M (TEE_READ_TEE_TIMERGROUP1_V << TEE_READ_TEE_TIMERGROUP1_S) +#define TEE_READ_TEE_TIMERGROUP1_V 0x00000001U +#define TEE_READ_TEE_TIMERGROUP1_S 0 +/** TEE_READ_REE0_TIMERGROUP1 : R/W; bitpos: [1]; default: 0; + * Configures timergroup1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TIMERGROUP1 (BIT(1)) +#define TEE_READ_REE0_TIMERGROUP1_M (TEE_READ_REE0_TIMERGROUP1_V << TEE_READ_REE0_TIMERGROUP1_S) +#define TEE_READ_REE0_TIMERGROUP1_V 0x00000001U +#define TEE_READ_REE0_TIMERGROUP1_S 1 +/** TEE_READ_REE1_TIMERGROUP1 : R/W; bitpos: [2]; default: 0; + * Configures timergroup1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TIMERGROUP1 (BIT(2)) +#define TEE_READ_REE1_TIMERGROUP1_M (TEE_READ_REE1_TIMERGROUP1_V << TEE_READ_REE1_TIMERGROUP1_S) +#define TEE_READ_REE1_TIMERGROUP1_V 0x00000001U +#define TEE_READ_REE1_TIMERGROUP1_S 2 +/** TEE_READ_REE2_TIMERGROUP1 : R/W; bitpos: [3]; default: 0; + * Configures timergroup1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TIMERGROUP1 (BIT(3)) +#define TEE_READ_REE2_TIMERGROUP1_M (TEE_READ_REE2_TIMERGROUP1_V << TEE_READ_REE2_TIMERGROUP1_S) +#define TEE_READ_REE2_TIMERGROUP1_V 0x00000001U +#define TEE_READ_REE2_TIMERGROUP1_S 3 +/** TEE_WRITE_TEE_TIMERGROUP1 : R/W; bitpos: [4]; default: 1; + * Configures timergroup1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TIMERGROUP1 (BIT(4)) +#define TEE_WRITE_TEE_TIMERGROUP1_M (TEE_WRITE_TEE_TIMERGROUP1_V << TEE_WRITE_TEE_TIMERGROUP1_S) +#define TEE_WRITE_TEE_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_TEE_TIMERGROUP1_S 4 +/** TEE_WRITE_REE0_TIMERGROUP1 : R/W; bitpos: [5]; default: 0; + * Configures timergroup1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TIMERGROUP1 (BIT(5)) +#define TEE_WRITE_REE0_TIMERGROUP1_M (TEE_WRITE_REE0_TIMERGROUP1_V << TEE_WRITE_REE0_TIMERGROUP1_S) +#define TEE_WRITE_REE0_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_REE0_TIMERGROUP1_S 5 +/** TEE_WRITE_REE1_TIMERGROUP1 : R/W; bitpos: [6]; default: 0; + * Configures timergroup1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TIMERGROUP1 (BIT(6)) +#define TEE_WRITE_REE1_TIMERGROUP1_M (TEE_WRITE_REE1_TIMERGROUP1_V << TEE_WRITE_REE1_TIMERGROUP1_S) +#define TEE_WRITE_REE1_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_REE1_TIMERGROUP1_S 6 +/** TEE_WRITE_REE2_TIMERGROUP1 : R/W; bitpos: [7]; default: 0; + * Configures timergroup1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TIMERGROUP1 (BIT(7)) +#define TEE_WRITE_REE2_TIMERGROUP1_M (TEE_WRITE_REE2_TIMERGROUP1_V << TEE_WRITE_REE2_TIMERGROUP1_S) +#define TEE_WRITE_REE2_TIMERGROUP1_V 0x00000001U +#define TEE_WRITE_REE2_TIMERGROUP1_S 7 + +/** TEE_SYSTIMER_CTRL_REG register + * systimer read/write control register + */ +#define TEE_SYSTIMER_CTRL_REG (DR_REG_TEE_BASE + 0xdc) +/** TEE_READ_TEE_SYSTIMER : R/W; bitpos: [0]; default: 1; + * Configures systimer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_SYSTIMER (BIT(0)) +#define TEE_READ_TEE_SYSTIMER_M (TEE_READ_TEE_SYSTIMER_V << TEE_READ_TEE_SYSTIMER_S) +#define TEE_READ_TEE_SYSTIMER_V 0x00000001U +#define TEE_READ_TEE_SYSTIMER_S 0 +/** TEE_READ_REE0_SYSTIMER : R/W; bitpos: [1]; default: 0; + * Configures systimer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_SYSTIMER (BIT(1)) +#define TEE_READ_REE0_SYSTIMER_M (TEE_READ_REE0_SYSTIMER_V << TEE_READ_REE0_SYSTIMER_S) +#define TEE_READ_REE0_SYSTIMER_V 0x00000001U +#define TEE_READ_REE0_SYSTIMER_S 1 +/** TEE_READ_REE1_SYSTIMER : R/W; bitpos: [2]; default: 0; + * Configures systimer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_SYSTIMER (BIT(2)) +#define TEE_READ_REE1_SYSTIMER_M (TEE_READ_REE1_SYSTIMER_V << TEE_READ_REE1_SYSTIMER_S) +#define TEE_READ_REE1_SYSTIMER_V 0x00000001U +#define TEE_READ_REE1_SYSTIMER_S 2 +/** TEE_READ_REE2_SYSTIMER : R/W; bitpos: [3]; default: 0; + * Configures systimer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_SYSTIMER (BIT(3)) +#define TEE_READ_REE2_SYSTIMER_M (TEE_READ_REE2_SYSTIMER_V << TEE_READ_REE2_SYSTIMER_S) +#define TEE_READ_REE2_SYSTIMER_V 0x00000001U +#define TEE_READ_REE2_SYSTIMER_S 3 +/** TEE_WRITE_TEE_SYSTIMER : R/W; bitpos: [4]; default: 1; + * Configures systimer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_SYSTIMER (BIT(4)) +#define TEE_WRITE_TEE_SYSTIMER_M (TEE_WRITE_TEE_SYSTIMER_V << TEE_WRITE_TEE_SYSTIMER_S) +#define TEE_WRITE_TEE_SYSTIMER_V 0x00000001U +#define TEE_WRITE_TEE_SYSTIMER_S 4 +/** TEE_WRITE_REE0_SYSTIMER : R/W; bitpos: [5]; default: 0; + * Configures systimer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_SYSTIMER (BIT(5)) +#define TEE_WRITE_REE0_SYSTIMER_M (TEE_WRITE_REE0_SYSTIMER_V << TEE_WRITE_REE0_SYSTIMER_S) +#define TEE_WRITE_REE0_SYSTIMER_V 0x00000001U +#define TEE_WRITE_REE0_SYSTIMER_S 5 +/** TEE_WRITE_REE1_SYSTIMER : R/W; bitpos: [6]; default: 0; + * Configures systimer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_SYSTIMER (BIT(6)) +#define TEE_WRITE_REE1_SYSTIMER_M (TEE_WRITE_REE1_SYSTIMER_V << TEE_WRITE_REE1_SYSTIMER_S) +#define TEE_WRITE_REE1_SYSTIMER_V 0x00000001U +#define TEE_WRITE_REE1_SYSTIMER_S 6 +/** TEE_WRITE_REE2_SYSTIMER : R/W; bitpos: [7]; default: 0; + * Configures systimer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_SYSTIMER (BIT(7)) +#define TEE_WRITE_REE2_SYSTIMER_M (TEE_WRITE_REE2_SYSTIMER_V << TEE_WRITE_REE2_SYSTIMER_S) +#define TEE_WRITE_REE2_SYSTIMER_V 0x00000001U +#define TEE_WRITE_REE2_SYSTIMER_S 7 + +/** TEE_MISC_CTRL_REG register + * misc read/write control register + */ +#define TEE_MISC_CTRL_REG (DR_REG_TEE_BASE + 0xe0) +/** TEE_READ_TEE_MISC : R/W; bitpos: [0]; default: 1; + * Configures misc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MISC (BIT(0)) +#define TEE_READ_TEE_MISC_M (TEE_READ_TEE_MISC_V << TEE_READ_TEE_MISC_S) +#define TEE_READ_TEE_MISC_V 0x00000001U +#define TEE_READ_TEE_MISC_S 0 +/** TEE_READ_REE0_MISC : R/W; bitpos: [1]; default: 0; + * Configures misc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MISC (BIT(1)) +#define TEE_READ_REE0_MISC_M (TEE_READ_REE0_MISC_V << TEE_READ_REE0_MISC_S) +#define TEE_READ_REE0_MISC_V 0x00000001U +#define TEE_READ_REE0_MISC_S 1 +/** TEE_READ_REE1_MISC : R/W; bitpos: [2]; default: 0; + * Configures misc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MISC (BIT(2)) +#define TEE_READ_REE1_MISC_M (TEE_READ_REE1_MISC_V << TEE_READ_REE1_MISC_S) +#define TEE_READ_REE1_MISC_V 0x00000001U +#define TEE_READ_REE1_MISC_S 2 +/** TEE_READ_REE2_MISC : R/W; bitpos: [3]; default: 0; + * Configures misc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MISC (BIT(3)) +#define TEE_READ_REE2_MISC_M (TEE_READ_REE2_MISC_V << TEE_READ_REE2_MISC_S) +#define TEE_READ_REE2_MISC_V 0x00000001U +#define TEE_READ_REE2_MISC_S 3 +/** TEE_WRITE_TEE_MISC : R/W; bitpos: [4]; default: 1; + * Configures misc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MISC (BIT(4)) +#define TEE_WRITE_TEE_MISC_M (TEE_WRITE_TEE_MISC_V << TEE_WRITE_TEE_MISC_S) +#define TEE_WRITE_TEE_MISC_V 0x00000001U +#define TEE_WRITE_TEE_MISC_S 4 +/** TEE_WRITE_REE0_MISC : R/W; bitpos: [5]; default: 0; + * Configures misc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MISC (BIT(5)) +#define TEE_WRITE_REE0_MISC_M (TEE_WRITE_REE0_MISC_V << TEE_WRITE_REE0_MISC_S) +#define TEE_WRITE_REE0_MISC_V 0x00000001U +#define TEE_WRITE_REE0_MISC_S 5 +/** TEE_WRITE_REE1_MISC : R/W; bitpos: [6]; default: 0; + * Configures misc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MISC (BIT(6)) +#define TEE_WRITE_REE1_MISC_M (TEE_WRITE_REE1_MISC_V << TEE_WRITE_REE1_MISC_S) +#define TEE_WRITE_REE1_MISC_V 0x00000001U +#define TEE_WRITE_REE1_MISC_S 6 +/** TEE_WRITE_REE2_MISC : R/W; bitpos: [7]; default: 0; + * Configures misc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MISC (BIT(7)) +#define TEE_WRITE_REE2_MISC_M (TEE_WRITE_REE2_MISC_V << TEE_WRITE_REE2_MISC_S) +#define TEE_WRITE_REE2_MISC_V 0x00000001U +#define TEE_WRITE_REE2_MISC_S 7 + +/** TEE_SRC_CTRL_REG register + * src read/write control register + */ +#define TEE_SRC_CTRL_REG (DR_REG_TEE_BASE + 0xe4) +/** TEE_READ_TEE_SRC : R/W; bitpos: [0]; default: 1; + * Configures src registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_SRC (BIT(0)) +#define TEE_READ_TEE_SRC_M (TEE_READ_TEE_SRC_V << TEE_READ_TEE_SRC_S) +#define TEE_READ_TEE_SRC_V 0x00000001U +#define TEE_READ_TEE_SRC_S 0 +/** TEE_READ_REE0_SRC : R/W; bitpos: [1]; default: 0; + * Configures src registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_SRC (BIT(1)) +#define TEE_READ_REE0_SRC_M (TEE_READ_REE0_SRC_V << TEE_READ_REE0_SRC_S) +#define TEE_READ_REE0_SRC_V 0x00000001U +#define TEE_READ_REE0_SRC_S 1 +/** TEE_READ_REE1_SRC : R/W; bitpos: [2]; default: 0; + * Configures src registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_SRC (BIT(2)) +#define TEE_READ_REE1_SRC_M (TEE_READ_REE1_SRC_V << TEE_READ_REE1_SRC_S) +#define TEE_READ_REE1_SRC_V 0x00000001U +#define TEE_READ_REE1_SRC_S 2 +/** TEE_READ_REE2_SRC : R/W; bitpos: [3]; default: 0; + * Configures src registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_SRC (BIT(3)) +#define TEE_READ_REE2_SRC_M (TEE_READ_REE2_SRC_V << TEE_READ_REE2_SRC_S) +#define TEE_READ_REE2_SRC_V 0x00000001U +#define TEE_READ_REE2_SRC_S 3 +/** TEE_WRITE_TEE_SRC : R/W; bitpos: [4]; default: 1; + * Configures src registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_SRC (BIT(4)) +#define TEE_WRITE_TEE_SRC_M (TEE_WRITE_TEE_SRC_V << TEE_WRITE_TEE_SRC_S) +#define TEE_WRITE_TEE_SRC_V 0x00000001U +#define TEE_WRITE_TEE_SRC_S 4 +/** TEE_WRITE_REE0_SRC : R/W; bitpos: [5]; default: 0; + * Configures src registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_SRC (BIT(5)) +#define TEE_WRITE_REE0_SRC_M (TEE_WRITE_REE0_SRC_V << TEE_WRITE_REE0_SRC_S) +#define TEE_WRITE_REE0_SRC_V 0x00000001U +#define TEE_WRITE_REE0_SRC_S 5 +/** TEE_WRITE_REE1_SRC : R/W; bitpos: [6]; default: 0; + * Configures src registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_SRC (BIT(6)) +#define TEE_WRITE_REE1_SRC_M (TEE_WRITE_REE1_SRC_V << TEE_WRITE_REE1_SRC_S) +#define TEE_WRITE_REE1_SRC_V 0x00000001U +#define TEE_WRITE_REE1_SRC_S 6 +/** TEE_WRITE_REE2_SRC : R/W; bitpos: [7]; default: 0; + * Configures src registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_SRC (BIT(7)) +#define TEE_WRITE_REE2_SRC_M (TEE_WRITE_REE2_SRC_V << TEE_WRITE_REE2_SRC_S) +#define TEE_WRITE_REE2_SRC_V 0x00000001U +#define TEE_WRITE_REE2_SRC_S 7 + +/** TEE_USB_OTG_FS_CORE_CTRL_REG register + * usb_otg_fs_core read/write control register + */ +#define TEE_USB_OTG_FS_CORE_CTRL_REG (DR_REG_TEE_BASE + 0xe8) +/** TEE_READ_TEE_USB_OTG_FS_CORE : R/W; bitpos: [0]; default: 1; + * Configures usb_otg_fs_core registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_USB_OTG_FS_CORE (BIT(0)) +#define TEE_READ_TEE_USB_OTG_FS_CORE_M (TEE_READ_TEE_USB_OTG_FS_CORE_V << TEE_READ_TEE_USB_OTG_FS_CORE_S) +#define TEE_READ_TEE_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_READ_TEE_USB_OTG_FS_CORE_S 0 +/** TEE_READ_REE0_USB_OTG_FS_CORE : R/W; bitpos: [1]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_USB_OTG_FS_CORE (BIT(1)) +#define TEE_READ_REE0_USB_OTG_FS_CORE_M (TEE_READ_REE0_USB_OTG_FS_CORE_V << TEE_READ_REE0_USB_OTG_FS_CORE_S) +#define TEE_READ_REE0_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_READ_REE0_USB_OTG_FS_CORE_S 1 +/** TEE_READ_REE1_USB_OTG_FS_CORE : R/W; bitpos: [2]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_USB_OTG_FS_CORE (BIT(2)) +#define TEE_READ_REE1_USB_OTG_FS_CORE_M (TEE_READ_REE1_USB_OTG_FS_CORE_V << TEE_READ_REE1_USB_OTG_FS_CORE_S) +#define TEE_READ_REE1_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_READ_REE1_USB_OTG_FS_CORE_S 2 +/** TEE_READ_REE2_USB_OTG_FS_CORE : R/W; bitpos: [3]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_USB_OTG_FS_CORE (BIT(3)) +#define TEE_READ_REE2_USB_OTG_FS_CORE_M (TEE_READ_REE2_USB_OTG_FS_CORE_V << TEE_READ_REE2_USB_OTG_FS_CORE_S) +#define TEE_READ_REE2_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_READ_REE2_USB_OTG_FS_CORE_S 3 +/** TEE_WRITE_TEE_USB_OTG_FS_CORE : R/W; bitpos: [4]; default: 1; + * Configures usb_otg_fs_core registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_USB_OTG_FS_CORE (BIT(4)) +#define TEE_WRITE_TEE_USB_OTG_FS_CORE_M (TEE_WRITE_TEE_USB_OTG_FS_CORE_V << TEE_WRITE_TEE_USB_OTG_FS_CORE_S) +#define TEE_WRITE_TEE_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_WRITE_TEE_USB_OTG_FS_CORE_S 4 +/** TEE_WRITE_REE0_USB_OTG_FS_CORE : R/W; bitpos: [5]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_USB_OTG_FS_CORE (BIT(5)) +#define TEE_WRITE_REE0_USB_OTG_FS_CORE_M (TEE_WRITE_REE0_USB_OTG_FS_CORE_V << TEE_WRITE_REE0_USB_OTG_FS_CORE_S) +#define TEE_WRITE_REE0_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_WRITE_REE0_USB_OTG_FS_CORE_S 5 +/** TEE_WRITE_REE1_USB_OTG_FS_CORE : R/W; bitpos: [6]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_USB_OTG_FS_CORE (BIT(6)) +#define TEE_WRITE_REE1_USB_OTG_FS_CORE_M (TEE_WRITE_REE1_USB_OTG_FS_CORE_V << TEE_WRITE_REE1_USB_OTG_FS_CORE_S) +#define TEE_WRITE_REE1_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_WRITE_REE1_USB_OTG_FS_CORE_S 6 +/** TEE_WRITE_REE2_USB_OTG_FS_CORE : R/W; bitpos: [7]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_USB_OTG_FS_CORE (BIT(7)) +#define TEE_WRITE_REE2_USB_OTG_FS_CORE_M (TEE_WRITE_REE2_USB_OTG_FS_CORE_V << TEE_WRITE_REE2_USB_OTG_FS_CORE_S) +#define TEE_WRITE_REE2_USB_OTG_FS_CORE_V 0x00000001U +#define TEE_WRITE_REE2_USB_OTG_FS_CORE_S 7 + +/** TEE_USB_OTG_FS_PHY_CTRL_REG register + * usb_otg_fs_phy read/write control register + */ +#define TEE_USB_OTG_FS_PHY_CTRL_REG (DR_REG_TEE_BASE + 0xec) +/** TEE_READ_TEE_USB_OTG_FS_PHY : R/W; bitpos: [0]; default: 1; + * Configures usb_otg_fs_phy registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_USB_OTG_FS_PHY (BIT(0)) +#define TEE_READ_TEE_USB_OTG_FS_PHY_M (TEE_READ_TEE_USB_OTG_FS_PHY_V << TEE_READ_TEE_USB_OTG_FS_PHY_S) +#define TEE_READ_TEE_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_READ_TEE_USB_OTG_FS_PHY_S 0 +/** TEE_READ_REE0_USB_OTG_FS_PHY : R/W; bitpos: [1]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_USB_OTG_FS_PHY (BIT(1)) +#define TEE_READ_REE0_USB_OTG_FS_PHY_M (TEE_READ_REE0_USB_OTG_FS_PHY_V << TEE_READ_REE0_USB_OTG_FS_PHY_S) +#define TEE_READ_REE0_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_READ_REE0_USB_OTG_FS_PHY_S 1 +/** TEE_READ_REE1_USB_OTG_FS_PHY : R/W; bitpos: [2]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_USB_OTG_FS_PHY (BIT(2)) +#define TEE_READ_REE1_USB_OTG_FS_PHY_M (TEE_READ_REE1_USB_OTG_FS_PHY_V << TEE_READ_REE1_USB_OTG_FS_PHY_S) +#define TEE_READ_REE1_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_READ_REE1_USB_OTG_FS_PHY_S 2 +/** TEE_READ_REE2_USB_OTG_FS_PHY : R/W; bitpos: [3]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_USB_OTG_FS_PHY (BIT(3)) +#define TEE_READ_REE2_USB_OTG_FS_PHY_M (TEE_READ_REE2_USB_OTG_FS_PHY_V << TEE_READ_REE2_USB_OTG_FS_PHY_S) +#define TEE_READ_REE2_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_READ_REE2_USB_OTG_FS_PHY_S 3 +/** TEE_WRITE_TEE_USB_OTG_FS_PHY : R/W; bitpos: [4]; default: 1; + * Configures usb_otg_fs_phy registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_USB_OTG_FS_PHY (BIT(4)) +#define TEE_WRITE_TEE_USB_OTG_FS_PHY_M (TEE_WRITE_TEE_USB_OTG_FS_PHY_V << TEE_WRITE_TEE_USB_OTG_FS_PHY_S) +#define TEE_WRITE_TEE_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_WRITE_TEE_USB_OTG_FS_PHY_S 4 +/** TEE_WRITE_REE0_USB_OTG_FS_PHY : R/W; bitpos: [5]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_USB_OTG_FS_PHY (BIT(5)) +#define TEE_WRITE_REE0_USB_OTG_FS_PHY_M (TEE_WRITE_REE0_USB_OTG_FS_PHY_V << TEE_WRITE_REE0_USB_OTG_FS_PHY_S) +#define TEE_WRITE_REE0_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_WRITE_REE0_USB_OTG_FS_PHY_S 5 +/** TEE_WRITE_REE1_USB_OTG_FS_PHY : R/W; bitpos: [6]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_USB_OTG_FS_PHY (BIT(6)) +#define TEE_WRITE_REE1_USB_OTG_FS_PHY_M (TEE_WRITE_REE1_USB_OTG_FS_PHY_V << TEE_WRITE_REE1_USB_OTG_FS_PHY_S) +#define TEE_WRITE_REE1_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_WRITE_REE1_USB_OTG_FS_PHY_S 6 +/** TEE_WRITE_REE2_USB_OTG_FS_PHY : R/W; bitpos: [7]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_USB_OTG_FS_PHY (BIT(7)) +#define TEE_WRITE_REE2_USB_OTG_FS_PHY_M (TEE_WRITE_REE2_USB_OTG_FS_PHY_V << TEE_WRITE_REE2_USB_OTG_FS_PHY_S) +#define TEE_WRITE_REE2_USB_OTG_FS_PHY_V 0x00000001U +#define TEE_WRITE_REE2_USB_OTG_FS_PHY_S 7 + +/** TEE_PVT_MONITOR_CTRL_REG register + * pvt_monitor read/write control register + */ +#define TEE_PVT_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xf0) +/** TEE_READ_TEE_PVT_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures pvt_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PVT_MONITOR (BIT(0)) +#define TEE_READ_TEE_PVT_MONITOR_M (TEE_READ_TEE_PVT_MONITOR_V << TEE_READ_TEE_PVT_MONITOR_S) +#define TEE_READ_TEE_PVT_MONITOR_V 0x00000001U +#define TEE_READ_TEE_PVT_MONITOR_S 0 +/** TEE_READ_REE0_PVT_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures pvt_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PVT_MONITOR (BIT(1)) +#define TEE_READ_REE0_PVT_MONITOR_M (TEE_READ_REE0_PVT_MONITOR_V << TEE_READ_REE0_PVT_MONITOR_S) +#define TEE_READ_REE0_PVT_MONITOR_V 0x00000001U +#define TEE_READ_REE0_PVT_MONITOR_S 1 +/** TEE_READ_REE1_PVT_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures pvt_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PVT_MONITOR (BIT(2)) +#define TEE_READ_REE1_PVT_MONITOR_M (TEE_READ_REE1_PVT_MONITOR_V << TEE_READ_REE1_PVT_MONITOR_S) +#define TEE_READ_REE1_PVT_MONITOR_V 0x00000001U +#define TEE_READ_REE1_PVT_MONITOR_S 2 +/** TEE_READ_REE2_PVT_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures pvt_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PVT_MONITOR (BIT(3)) +#define TEE_READ_REE2_PVT_MONITOR_M (TEE_READ_REE2_PVT_MONITOR_V << TEE_READ_REE2_PVT_MONITOR_S) +#define TEE_READ_REE2_PVT_MONITOR_V 0x00000001U +#define TEE_READ_REE2_PVT_MONITOR_S 3 +/** TEE_WRITE_TEE_PVT_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures pvt_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PVT_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_PVT_MONITOR_M (TEE_WRITE_TEE_PVT_MONITOR_V << TEE_WRITE_TEE_PVT_MONITOR_S) +#define TEE_WRITE_TEE_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_PVT_MONITOR_S 4 +/** TEE_WRITE_REE0_PVT_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures pvt_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PVT_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_PVT_MONITOR_M (TEE_WRITE_REE0_PVT_MONITOR_V << TEE_WRITE_REE0_PVT_MONITOR_S) +#define TEE_WRITE_REE0_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_PVT_MONITOR_S 5 +/** TEE_WRITE_REE1_PVT_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures pvt_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PVT_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_PVT_MONITOR_M (TEE_WRITE_REE1_PVT_MONITOR_V << TEE_WRITE_REE1_PVT_MONITOR_S) +#define TEE_WRITE_REE1_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_PVT_MONITOR_S 6 +/** TEE_WRITE_REE2_PVT_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures pvt_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PVT_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_PVT_MONITOR_M (TEE_WRITE_REE2_PVT_MONITOR_V << TEE_WRITE_REE2_PVT_MONITOR_S) +#define TEE_WRITE_REE2_PVT_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_PVT_MONITOR_S 7 + +/** TEE_PCNT_CTRL_REG register + * pcnt read/write control register + */ +#define TEE_PCNT_CTRL_REG (DR_REG_TEE_BASE + 0xf4) +/** TEE_READ_TEE_PCNT : R/W; bitpos: [0]; default: 1; + * Configures pcnt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PCNT (BIT(0)) +#define TEE_READ_TEE_PCNT_M (TEE_READ_TEE_PCNT_V << TEE_READ_TEE_PCNT_S) +#define TEE_READ_TEE_PCNT_V 0x00000001U +#define TEE_READ_TEE_PCNT_S 0 +/** TEE_READ_REE0_PCNT : R/W; bitpos: [1]; default: 0; + * Configures pcnt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PCNT (BIT(1)) +#define TEE_READ_REE0_PCNT_M (TEE_READ_REE0_PCNT_V << TEE_READ_REE0_PCNT_S) +#define TEE_READ_REE0_PCNT_V 0x00000001U +#define TEE_READ_REE0_PCNT_S 1 +/** TEE_READ_REE1_PCNT : R/W; bitpos: [2]; default: 0; + * Configures pcnt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PCNT (BIT(2)) +#define TEE_READ_REE1_PCNT_M (TEE_READ_REE1_PCNT_V << TEE_READ_REE1_PCNT_S) +#define TEE_READ_REE1_PCNT_V 0x00000001U +#define TEE_READ_REE1_PCNT_S 2 +/** TEE_READ_REE2_PCNT : R/W; bitpos: [3]; default: 0; + * Configures pcnt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PCNT (BIT(3)) +#define TEE_READ_REE2_PCNT_M (TEE_READ_REE2_PCNT_V << TEE_READ_REE2_PCNT_S) +#define TEE_READ_REE2_PCNT_V 0x00000001U +#define TEE_READ_REE2_PCNT_S 3 +/** TEE_WRITE_TEE_PCNT : R/W; bitpos: [4]; default: 1; + * Configures pcnt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PCNT (BIT(4)) +#define TEE_WRITE_TEE_PCNT_M (TEE_WRITE_TEE_PCNT_V << TEE_WRITE_TEE_PCNT_S) +#define TEE_WRITE_TEE_PCNT_V 0x00000001U +#define TEE_WRITE_TEE_PCNT_S 4 +/** TEE_WRITE_REE0_PCNT : R/W; bitpos: [5]; default: 0; + * Configures pcnt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PCNT (BIT(5)) +#define TEE_WRITE_REE0_PCNT_M (TEE_WRITE_REE0_PCNT_V << TEE_WRITE_REE0_PCNT_S) +#define TEE_WRITE_REE0_PCNT_V 0x00000001U +#define TEE_WRITE_REE0_PCNT_S 5 +/** TEE_WRITE_REE1_PCNT : R/W; bitpos: [6]; default: 0; + * Configures pcnt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PCNT (BIT(6)) +#define TEE_WRITE_REE1_PCNT_M (TEE_WRITE_REE1_PCNT_V << TEE_WRITE_REE1_PCNT_S) +#define TEE_WRITE_REE1_PCNT_V 0x00000001U +#define TEE_WRITE_REE1_PCNT_S 6 +/** TEE_WRITE_REE2_PCNT : R/W; bitpos: [7]; default: 0; + * Configures pcnt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PCNT (BIT(7)) +#define TEE_WRITE_REE2_PCNT_M (TEE_WRITE_REE2_PCNT_V << TEE_WRITE_REE2_PCNT_S) +#define TEE_WRITE_REE2_PCNT_V 0x00000001U +#define TEE_WRITE_REE2_PCNT_S 7 + +/** TEE_IOMUX_CTRL_REG register + * iomux read/write control register + */ +#define TEE_IOMUX_CTRL_REG (DR_REG_TEE_BASE + 0xf8) +/** TEE_READ_TEE_IOMUX : R/W; bitpos: [0]; default: 1; + * Configures iomux registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_IOMUX (BIT(0)) +#define TEE_READ_TEE_IOMUX_M (TEE_READ_TEE_IOMUX_V << TEE_READ_TEE_IOMUX_S) +#define TEE_READ_TEE_IOMUX_V 0x00000001U +#define TEE_READ_TEE_IOMUX_S 0 +/** TEE_READ_REE0_IOMUX : R/W; bitpos: [1]; default: 0; + * Configures iomux registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_IOMUX (BIT(1)) +#define TEE_READ_REE0_IOMUX_M (TEE_READ_REE0_IOMUX_V << TEE_READ_REE0_IOMUX_S) +#define TEE_READ_REE0_IOMUX_V 0x00000001U +#define TEE_READ_REE0_IOMUX_S 1 +/** TEE_READ_REE1_IOMUX : R/W; bitpos: [2]; default: 0; + * Configures iomux registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_IOMUX (BIT(2)) +#define TEE_READ_REE1_IOMUX_M (TEE_READ_REE1_IOMUX_V << TEE_READ_REE1_IOMUX_S) +#define TEE_READ_REE1_IOMUX_V 0x00000001U +#define TEE_READ_REE1_IOMUX_S 2 +/** TEE_READ_REE2_IOMUX : R/W; bitpos: [3]; default: 0; + * Configures iomux registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_IOMUX (BIT(3)) +#define TEE_READ_REE2_IOMUX_M (TEE_READ_REE2_IOMUX_V << TEE_READ_REE2_IOMUX_S) +#define TEE_READ_REE2_IOMUX_V 0x00000001U +#define TEE_READ_REE2_IOMUX_S 3 +/** TEE_WRITE_TEE_IOMUX : R/W; bitpos: [4]; default: 1; + * Configures iomux registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_IOMUX (BIT(4)) +#define TEE_WRITE_TEE_IOMUX_M (TEE_WRITE_TEE_IOMUX_V << TEE_WRITE_TEE_IOMUX_S) +#define TEE_WRITE_TEE_IOMUX_V 0x00000001U +#define TEE_WRITE_TEE_IOMUX_S 4 +/** TEE_WRITE_REE0_IOMUX : R/W; bitpos: [5]; default: 0; + * Configures iomux registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_IOMUX (BIT(5)) +#define TEE_WRITE_REE0_IOMUX_M (TEE_WRITE_REE0_IOMUX_V << TEE_WRITE_REE0_IOMUX_S) +#define TEE_WRITE_REE0_IOMUX_V 0x00000001U +#define TEE_WRITE_REE0_IOMUX_S 5 +/** TEE_WRITE_REE1_IOMUX : R/W; bitpos: [6]; default: 0; + * Configures iomux registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_IOMUX (BIT(6)) +#define TEE_WRITE_REE1_IOMUX_M (TEE_WRITE_REE1_IOMUX_V << TEE_WRITE_REE1_IOMUX_S) +#define TEE_WRITE_REE1_IOMUX_V 0x00000001U +#define TEE_WRITE_REE1_IOMUX_S 6 +/** TEE_WRITE_REE2_IOMUX : R/W; bitpos: [7]; default: 0; + * Configures iomux registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_IOMUX (BIT(7)) +#define TEE_WRITE_REE2_IOMUX_M (TEE_WRITE_REE2_IOMUX_V << TEE_WRITE_REE2_IOMUX_S) +#define TEE_WRITE_REE2_IOMUX_V 0x00000001U +#define TEE_WRITE_REE2_IOMUX_S 7 + +/** TEE_PSRAM_MEM_MONITOR_CTRL_REG register + * psram_mem_monitor read/write control register + */ +#define TEE_PSRAM_MEM_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xfc) +/** TEE_READ_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures psram_mem_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PSRAM_MEM_MONITOR (BIT(0)) +#define TEE_READ_TEE_PSRAM_MEM_MONITOR_M (TEE_READ_TEE_PSRAM_MEM_MONITOR_V << TEE_READ_TEE_PSRAM_MEM_MONITOR_S) +#define TEE_READ_TEE_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_TEE_PSRAM_MEM_MONITOR_S 0 +/** TEE_READ_REE0_PSRAM_MEM_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures psram_mem_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PSRAM_MEM_MONITOR (BIT(1)) +#define TEE_READ_REE0_PSRAM_MEM_MONITOR_M (TEE_READ_REE0_PSRAM_MEM_MONITOR_V << TEE_READ_REE0_PSRAM_MEM_MONITOR_S) +#define TEE_READ_REE0_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_REE0_PSRAM_MEM_MONITOR_S 1 +/** TEE_READ_REE1_PSRAM_MEM_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures psram_mem_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PSRAM_MEM_MONITOR (BIT(2)) +#define TEE_READ_REE1_PSRAM_MEM_MONITOR_M (TEE_READ_REE1_PSRAM_MEM_MONITOR_V << TEE_READ_REE1_PSRAM_MEM_MONITOR_S) +#define TEE_READ_REE1_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_REE1_PSRAM_MEM_MONITOR_S 2 +/** TEE_READ_REE2_PSRAM_MEM_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures psram_mem_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PSRAM_MEM_MONITOR (BIT(3)) +#define TEE_READ_REE2_PSRAM_MEM_MONITOR_M (TEE_READ_REE2_PSRAM_MEM_MONITOR_V << TEE_READ_REE2_PSRAM_MEM_MONITOR_S) +#define TEE_READ_REE2_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_READ_REE2_PSRAM_MEM_MONITOR_S 3 +/** TEE_WRITE_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures psram_mem_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_M (TEE_WRITE_TEE_PSRAM_MEM_MONITOR_V << TEE_WRITE_TEE_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_PSRAM_MEM_MONITOR_S 4 +/** TEE_WRITE_REE0_PSRAM_MEM_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures psram_mem_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_M (TEE_WRITE_REE0_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE0_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_PSRAM_MEM_MONITOR_S 5 +/** TEE_WRITE_REE1_PSRAM_MEM_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures psram_mem_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_M (TEE_WRITE_REE1_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE1_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_PSRAM_MEM_MONITOR_S 6 +/** TEE_WRITE_REE2_PSRAM_MEM_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures psram_mem_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_M (TEE_WRITE_REE2_PSRAM_MEM_MONITOR_V << TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S) +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S 7 + +/** TEE_MEM_ACS_MONITOR_CTRL_REG register + * mem_acs_monitor read/write control register + */ +#define TEE_MEM_ACS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x100) +/** TEE_READ_TEE_MEM_ACS_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures mem_acs_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MEM_ACS_MONITOR (BIT(0)) +#define TEE_READ_TEE_MEM_ACS_MONITOR_M (TEE_READ_TEE_MEM_ACS_MONITOR_V << TEE_READ_TEE_MEM_ACS_MONITOR_S) +#define TEE_READ_TEE_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_TEE_MEM_ACS_MONITOR_S 0 +/** TEE_READ_REE0_MEM_ACS_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures mem_acs_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MEM_ACS_MONITOR (BIT(1)) +#define TEE_READ_REE0_MEM_ACS_MONITOR_M (TEE_READ_REE0_MEM_ACS_MONITOR_V << TEE_READ_REE0_MEM_ACS_MONITOR_S) +#define TEE_READ_REE0_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_REE0_MEM_ACS_MONITOR_S 1 +/** TEE_READ_REE1_MEM_ACS_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures mem_acs_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MEM_ACS_MONITOR (BIT(2)) +#define TEE_READ_REE1_MEM_ACS_MONITOR_M (TEE_READ_REE1_MEM_ACS_MONITOR_V << TEE_READ_REE1_MEM_ACS_MONITOR_S) +#define TEE_READ_REE1_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_REE1_MEM_ACS_MONITOR_S 2 +/** TEE_READ_REE2_MEM_ACS_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures mem_acs_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MEM_ACS_MONITOR (BIT(3)) +#define TEE_READ_REE2_MEM_ACS_MONITOR_M (TEE_READ_REE2_MEM_ACS_MONITOR_V << TEE_READ_REE2_MEM_ACS_MONITOR_S) +#define TEE_READ_REE2_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_READ_REE2_MEM_ACS_MONITOR_S 3 +/** TEE_WRITE_TEE_MEM_ACS_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures mem_acs_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MEM_ACS_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_MEM_ACS_MONITOR_M (TEE_WRITE_TEE_MEM_ACS_MONITOR_V << TEE_WRITE_TEE_MEM_ACS_MONITOR_S) +#define TEE_WRITE_TEE_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_MEM_ACS_MONITOR_S 4 +/** TEE_WRITE_REE0_MEM_ACS_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures mem_acs_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MEM_ACS_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_MEM_ACS_MONITOR_M (TEE_WRITE_REE0_MEM_ACS_MONITOR_V << TEE_WRITE_REE0_MEM_ACS_MONITOR_S) +#define TEE_WRITE_REE0_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_MEM_ACS_MONITOR_S 5 +/** TEE_WRITE_REE1_MEM_ACS_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures mem_acs_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MEM_ACS_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_MEM_ACS_MONITOR_M (TEE_WRITE_REE1_MEM_ACS_MONITOR_V << TEE_WRITE_REE1_MEM_ACS_MONITOR_S) +#define TEE_WRITE_REE1_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_MEM_ACS_MONITOR_S 6 +/** TEE_WRITE_REE2_MEM_ACS_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures mem_acs_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MEM_ACS_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_MEM_ACS_MONITOR_M (TEE_WRITE_REE2_MEM_ACS_MONITOR_V << TEE_WRITE_REE2_MEM_ACS_MONITOR_S) +#define TEE_WRITE_REE2_MEM_ACS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_MEM_ACS_MONITOR_S 7 + +/** TEE_HP_SYSTEM_REG_CTRL_REG register + * hp_system_reg read/write control register + */ +#define TEE_HP_SYSTEM_REG_CTRL_REG (DR_REG_TEE_BASE + 0x104) +/** TEE_READ_TEE_HP_SYSTEM_REG : R/W; bitpos: [0]; default: 1; + * Configures hp_system_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_HP_SYSTEM_REG (BIT(0)) +#define TEE_READ_TEE_HP_SYSTEM_REG_M (TEE_READ_TEE_HP_SYSTEM_REG_V << TEE_READ_TEE_HP_SYSTEM_REG_S) +#define TEE_READ_TEE_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_TEE_HP_SYSTEM_REG_S 0 +/** TEE_READ_REE0_HP_SYSTEM_REG : R/W; bitpos: [1]; default: 0; + * Configures hp_system_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_HP_SYSTEM_REG (BIT(1)) +#define TEE_READ_REE0_HP_SYSTEM_REG_M (TEE_READ_REE0_HP_SYSTEM_REG_V << TEE_READ_REE0_HP_SYSTEM_REG_S) +#define TEE_READ_REE0_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_REE0_HP_SYSTEM_REG_S 1 +/** TEE_READ_REE1_HP_SYSTEM_REG : R/W; bitpos: [2]; default: 0; + * Configures hp_system_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_HP_SYSTEM_REG (BIT(2)) +#define TEE_READ_REE1_HP_SYSTEM_REG_M (TEE_READ_REE1_HP_SYSTEM_REG_V << TEE_READ_REE1_HP_SYSTEM_REG_S) +#define TEE_READ_REE1_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_REE1_HP_SYSTEM_REG_S 2 +/** TEE_READ_REE2_HP_SYSTEM_REG : R/W; bitpos: [3]; default: 0; + * Configures hp_system_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_HP_SYSTEM_REG (BIT(3)) +#define TEE_READ_REE2_HP_SYSTEM_REG_M (TEE_READ_REE2_HP_SYSTEM_REG_V << TEE_READ_REE2_HP_SYSTEM_REG_S) +#define TEE_READ_REE2_HP_SYSTEM_REG_V 0x00000001U +#define TEE_READ_REE2_HP_SYSTEM_REG_S 3 +/** TEE_WRITE_TEE_HP_SYSTEM_REG : R/W; bitpos: [4]; default: 1; + * Configures hp_system_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_HP_SYSTEM_REG (BIT(4)) +#define TEE_WRITE_TEE_HP_SYSTEM_REG_M (TEE_WRITE_TEE_HP_SYSTEM_REG_V << TEE_WRITE_TEE_HP_SYSTEM_REG_S) +#define TEE_WRITE_TEE_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_TEE_HP_SYSTEM_REG_S 4 +/** TEE_WRITE_REE0_HP_SYSTEM_REG : R/W; bitpos: [5]; default: 0; + * Configures hp_system_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_HP_SYSTEM_REG (BIT(5)) +#define TEE_WRITE_REE0_HP_SYSTEM_REG_M (TEE_WRITE_REE0_HP_SYSTEM_REG_V << TEE_WRITE_REE0_HP_SYSTEM_REG_S) +#define TEE_WRITE_REE0_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_REE0_HP_SYSTEM_REG_S 5 +/** TEE_WRITE_REE1_HP_SYSTEM_REG : R/W; bitpos: [6]; default: 0; + * Configures hp_system_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_HP_SYSTEM_REG (BIT(6)) +#define TEE_WRITE_REE1_HP_SYSTEM_REG_M (TEE_WRITE_REE1_HP_SYSTEM_REG_V << TEE_WRITE_REE1_HP_SYSTEM_REG_S) +#define TEE_WRITE_REE1_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_REE1_HP_SYSTEM_REG_S 6 +/** TEE_WRITE_REE2_HP_SYSTEM_REG : R/W; bitpos: [7]; default: 0; + * Configures hp_system_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_HP_SYSTEM_REG (BIT(7)) +#define TEE_WRITE_REE2_HP_SYSTEM_REG_M (TEE_WRITE_REE2_HP_SYSTEM_REG_V << TEE_WRITE_REE2_HP_SYSTEM_REG_S) +#define TEE_WRITE_REE2_HP_SYSTEM_REG_V 0x00000001U +#define TEE_WRITE_REE2_HP_SYSTEM_REG_S 7 + +/** TEE_PCR_REG_CTRL_REG register + * pcr_reg read/write control register + */ +#define TEE_PCR_REG_CTRL_REG (DR_REG_TEE_BASE + 0x108) +/** TEE_READ_TEE_PCR_REG : R/W; bitpos: [0]; default: 1; + * Configures pcr_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_PCR_REG (BIT(0)) +#define TEE_READ_TEE_PCR_REG_M (TEE_READ_TEE_PCR_REG_V << TEE_READ_TEE_PCR_REG_S) +#define TEE_READ_TEE_PCR_REG_V 0x00000001U +#define TEE_READ_TEE_PCR_REG_S 0 +/** TEE_READ_REE0_PCR_REG : R/W; bitpos: [1]; default: 0; + * Configures pcr_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_PCR_REG (BIT(1)) +#define TEE_READ_REE0_PCR_REG_M (TEE_READ_REE0_PCR_REG_V << TEE_READ_REE0_PCR_REG_S) +#define TEE_READ_REE0_PCR_REG_V 0x00000001U +#define TEE_READ_REE0_PCR_REG_S 1 +/** TEE_READ_REE1_PCR_REG : R/W; bitpos: [2]; default: 0; + * Configures pcr_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_PCR_REG (BIT(2)) +#define TEE_READ_REE1_PCR_REG_M (TEE_READ_REE1_PCR_REG_V << TEE_READ_REE1_PCR_REG_S) +#define TEE_READ_REE1_PCR_REG_V 0x00000001U +#define TEE_READ_REE1_PCR_REG_S 2 +/** TEE_READ_REE2_PCR_REG : R/W; bitpos: [3]; default: 0; + * Configures pcr_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_PCR_REG (BIT(3)) +#define TEE_READ_REE2_PCR_REG_M (TEE_READ_REE2_PCR_REG_V << TEE_READ_REE2_PCR_REG_S) +#define TEE_READ_REE2_PCR_REG_V 0x00000001U +#define TEE_READ_REE2_PCR_REG_S 3 +/** TEE_WRITE_TEE_PCR_REG : R/W; bitpos: [4]; default: 1; + * Configures pcr_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_PCR_REG (BIT(4)) +#define TEE_WRITE_TEE_PCR_REG_M (TEE_WRITE_TEE_PCR_REG_V << TEE_WRITE_TEE_PCR_REG_S) +#define TEE_WRITE_TEE_PCR_REG_V 0x00000001U +#define TEE_WRITE_TEE_PCR_REG_S 4 +/** TEE_WRITE_REE0_PCR_REG : R/W; bitpos: [5]; default: 0; + * Configures pcr_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_PCR_REG (BIT(5)) +#define TEE_WRITE_REE0_PCR_REG_M (TEE_WRITE_REE0_PCR_REG_V << TEE_WRITE_REE0_PCR_REG_S) +#define TEE_WRITE_REE0_PCR_REG_V 0x00000001U +#define TEE_WRITE_REE0_PCR_REG_S 5 +/** TEE_WRITE_REE1_PCR_REG : R/W; bitpos: [6]; default: 0; + * Configures pcr_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_PCR_REG (BIT(6)) +#define TEE_WRITE_REE1_PCR_REG_M (TEE_WRITE_REE1_PCR_REG_V << TEE_WRITE_REE1_PCR_REG_S) +#define TEE_WRITE_REE1_PCR_REG_V 0x00000001U +#define TEE_WRITE_REE1_PCR_REG_S 6 +/** TEE_WRITE_REE2_PCR_REG : R/W; bitpos: [7]; default: 0; + * Configures pcr_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_PCR_REG (BIT(7)) +#define TEE_WRITE_REE2_PCR_REG_M (TEE_WRITE_REE2_PCR_REG_V << TEE_WRITE_REE2_PCR_REG_S) +#define TEE_WRITE_REE2_PCR_REG_V 0x00000001U +#define TEE_WRITE_REE2_PCR_REG_S 7 + +/** TEE_MSPI_CTRL_REG register + * mspi read/write control register + */ +#define TEE_MSPI_CTRL_REG (DR_REG_TEE_BASE + 0x10c) +/** TEE_READ_TEE_MSPI : R/W; bitpos: [0]; default: 1; + * Configures mspi registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MSPI (BIT(0)) +#define TEE_READ_TEE_MSPI_M (TEE_READ_TEE_MSPI_V << TEE_READ_TEE_MSPI_S) +#define TEE_READ_TEE_MSPI_V 0x00000001U +#define TEE_READ_TEE_MSPI_S 0 +/** TEE_READ_REE0_MSPI : R/W; bitpos: [1]; default: 0; + * Configures mspi registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MSPI (BIT(1)) +#define TEE_READ_REE0_MSPI_M (TEE_READ_REE0_MSPI_V << TEE_READ_REE0_MSPI_S) +#define TEE_READ_REE0_MSPI_V 0x00000001U +#define TEE_READ_REE0_MSPI_S 1 +/** TEE_READ_REE1_MSPI : R/W; bitpos: [2]; default: 0; + * Configures mspi registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MSPI (BIT(2)) +#define TEE_READ_REE1_MSPI_M (TEE_READ_REE1_MSPI_V << TEE_READ_REE1_MSPI_S) +#define TEE_READ_REE1_MSPI_V 0x00000001U +#define TEE_READ_REE1_MSPI_S 2 +/** TEE_READ_REE2_MSPI : R/W; bitpos: [3]; default: 0; + * Configures mspi registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MSPI (BIT(3)) +#define TEE_READ_REE2_MSPI_M (TEE_READ_REE2_MSPI_V << TEE_READ_REE2_MSPI_S) +#define TEE_READ_REE2_MSPI_V 0x00000001U +#define TEE_READ_REE2_MSPI_S 3 +/** TEE_WRITE_TEE_MSPI : R/W; bitpos: [4]; default: 1; + * Configures mspi registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MSPI (BIT(4)) +#define TEE_WRITE_TEE_MSPI_M (TEE_WRITE_TEE_MSPI_V << TEE_WRITE_TEE_MSPI_S) +#define TEE_WRITE_TEE_MSPI_V 0x00000001U +#define TEE_WRITE_TEE_MSPI_S 4 +/** TEE_WRITE_REE0_MSPI : R/W; bitpos: [5]; default: 0; + * Configures mspi registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MSPI (BIT(5)) +#define TEE_WRITE_REE0_MSPI_M (TEE_WRITE_REE0_MSPI_V << TEE_WRITE_REE0_MSPI_S) +#define TEE_WRITE_REE0_MSPI_V 0x00000001U +#define TEE_WRITE_REE0_MSPI_S 5 +/** TEE_WRITE_REE1_MSPI : R/W; bitpos: [6]; default: 0; + * Configures mspi registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MSPI (BIT(6)) +#define TEE_WRITE_REE1_MSPI_M (TEE_WRITE_REE1_MSPI_V << TEE_WRITE_REE1_MSPI_S) +#define TEE_WRITE_REE1_MSPI_V 0x00000001U +#define TEE_WRITE_REE1_MSPI_S 6 +/** TEE_WRITE_REE2_MSPI : R/W; bitpos: [7]; default: 0; + * Configures mspi registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MSPI (BIT(7)) +#define TEE_WRITE_REE2_MSPI_M (TEE_WRITE_REE2_MSPI_V << TEE_WRITE_REE2_MSPI_S) +#define TEE_WRITE_REE2_MSPI_V 0x00000001U +#define TEE_WRITE_REE2_MSPI_S 7 + +/** TEE_HP_APM_CTRL_REG register + * hp_apm read/write control register + */ +#define TEE_HP_APM_CTRL_REG (DR_REG_TEE_BASE + 0x110) +/** TEE_READ_TEE_HP_APM : R/W; bitpos: [0]; default: 1; + * Configures hp_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_HP_APM (BIT(0)) +#define TEE_READ_TEE_HP_APM_M (TEE_READ_TEE_HP_APM_V << TEE_READ_TEE_HP_APM_S) +#define TEE_READ_TEE_HP_APM_V 0x00000001U +#define TEE_READ_TEE_HP_APM_S 0 +/** TEE_READ_REE0_HP_APM : HRO; bitpos: [1]; default: 0; + * Configures hp_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_HP_APM (BIT(1)) +#define TEE_READ_REE0_HP_APM_M (TEE_READ_REE0_HP_APM_V << TEE_READ_REE0_HP_APM_S) +#define TEE_READ_REE0_HP_APM_V 0x00000001U +#define TEE_READ_REE0_HP_APM_S 1 +/** TEE_READ_REE1_HP_APM : HRO; bitpos: [2]; default: 0; + * Configures hp_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_HP_APM (BIT(2)) +#define TEE_READ_REE1_HP_APM_M (TEE_READ_REE1_HP_APM_V << TEE_READ_REE1_HP_APM_S) +#define TEE_READ_REE1_HP_APM_V 0x00000001U +#define TEE_READ_REE1_HP_APM_S 2 +/** TEE_READ_REE2_HP_APM : HRO; bitpos: [3]; default: 0; + * Configures hp_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_HP_APM (BIT(3)) +#define TEE_READ_REE2_HP_APM_M (TEE_READ_REE2_HP_APM_V << TEE_READ_REE2_HP_APM_S) +#define TEE_READ_REE2_HP_APM_V 0x00000001U +#define TEE_READ_REE2_HP_APM_S 3 +/** TEE_WRITE_TEE_HP_APM : R/W; bitpos: [4]; default: 1; + * Configures hp_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_HP_APM (BIT(4)) +#define TEE_WRITE_TEE_HP_APM_M (TEE_WRITE_TEE_HP_APM_V << TEE_WRITE_TEE_HP_APM_S) +#define TEE_WRITE_TEE_HP_APM_V 0x00000001U +#define TEE_WRITE_TEE_HP_APM_S 4 +/** TEE_WRITE_REE0_HP_APM : HRO; bitpos: [5]; default: 0; + * Configures hp_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_HP_APM (BIT(5)) +#define TEE_WRITE_REE0_HP_APM_M (TEE_WRITE_REE0_HP_APM_V << TEE_WRITE_REE0_HP_APM_S) +#define TEE_WRITE_REE0_HP_APM_V 0x00000001U +#define TEE_WRITE_REE0_HP_APM_S 5 +/** TEE_WRITE_REE1_HP_APM : HRO; bitpos: [6]; default: 0; + * Configures hp_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_HP_APM (BIT(6)) +#define TEE_WRITE_REE1_HP_APM_M (TEE_WRITE_REE1_HP_APM_V << TEE_WRITE_REE1_HP_APM_S) +#define TEE_WRITE_REE1_HP_APM_V 0x00000001U +#define TEE_WRITE_REE1_HP_APM_S 6 +/** TEE_WRITE_REE2_HP_APM : HRO; bitpos: [7]; default: 0; + * Configures hp_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_HP_APM (BIT(7)) +#define TEE_WRITE_REE2_HP_APM_M (TEE_WRITE_REE2_HP_APM_V << TEE_WRITE_REE2_HP_APM_S) +#define TEE_WRITE_REE2_HP_APM_V 0x00000001U +#define TEE_WRITE_REE2_HP_APM_S 7 + +/** TEE_HP_MEM_APM_CTRL_REG register + * hp_mem_apm read/write control register + */ +#define TEE_HP_MEM_APM_CTRL_REG (DR_REG_TEE_BASE + 0x114) +/** TEE_READ_TEE_HP_MEM_APM : R/W; bitpos: [0]; default: 1; + * Configures hp_mem_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_HP_MEM_APM (BIT(0)) +#define TEE_READ_TEE_HP_MEM_APM_M (TEE_READ_TEE_HP_MEM_APM_V << TEE_READ_TEE_HP_MEM_APM_S) +#define TEE_READ_TEE_HP_MEM_APM_V 0x00000001U +#define TEE_READ_TEE_HP_MEM_APM_S 0 +/** TEE_READ_REE0_HP_MEM_APM : HRO; bitpos: [1]; default: 0; + * Configures hp_mem_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_HP_MEM_APM (BIT(1)) +#define TEE_READ_REE0_HP_MEM_APM_M (TEE_READ_REE0_HP_MEM_APM_V << TEE_READ_REE0_HP_MEM_APM_S) +#define TEE_READ_REE0_HP_MEM_APM_V 0x00000001U +#define TEE_READ_REE0_HP_MEM_APM_S 1 +/** TEE_READ_REE1_HP_MEM_APM : HRO; bitpos: [2]; default: 0; + * Configures hp_mem_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_HP_MEM_APM (BIT(2)) +#define TEE_READ_REE1_HP_MEM_APM_M (TEE_READ_REE1_HP_MEM_APM_V << TEE_READ_REE1_HP_MEM_APM_S) +#define TEE_READ_REE1_HP_MEM_APM_V 0x00000001U +#define TEE_READ_REE1_HP_MEM_APM_S 2 +/** TEE_READ_REE2_HP_MEM_APM : HRO; bitpos: [3]; default: 0; + * Configures hp_mem_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_HP_MEM_APM (BIT(3)) +#define TEE_READ_REE2_HP_MEM_APM_M (TEE_READ_REE2_HP_MEM_APM_V << TEE_READ_REE2_HP_MEM_APM_S) +#define TEE_READ_REE2_HP_MEM_APM_V 0x00000001U +#define TEE_READ_REE2_HP_MEM_APM_S 3 +/** TEE_WRITE_TEE_HP_MEM_APM : R/W; bitpos: [4]; default: 1; + * Configures hp_mem_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_HP_MEM_APM (BIT(4)) +#define TEE_WRITE_TEE_HP_MEM_APM_M (TEE_WRITE_TEE_HP_MEM_APM_V << TEE_WRITE_TEE_HP_MEM_APM_S) +#define TEE_WRITE_TEE_HP_MEM_APM_V 0x00000001U +#define TEE_WRITE_TEE_HP_MEM_APM_S 4 +/** TEE_WRITE_REE0_HP_MEM_APM : HRO; bitpos: [5]; default: 0; + * Configures hp_mem_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_HP_MEM_APM (BIT(5)) +#define TEE_WRITE_REE0_HP_MEM_APM_M (TEE_WRITE_REE0_HP_MEM_APM_V << TEE_WRITE_REE0_HP_MEM_APM_S) +#define TEE_WRITE_REE0_HP_MEM_APM_V 0x00000001U +#define TEE_WRITE_REE0_HP_MEM_APM_S 5 +/** TEE_WRITE_REE1_HP_MEM_APM : HRO; bitpos: [6]; default: 0; + * Configures hp_mem_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_HP_MEM_APM (BIT(6)) +#define TEE_WRITE_REE1_HP_MEM_APM_M (TEE_WRITE_REE1_HP_MEM_APM_V << TEE_WRITE_REE1_HP_MEM_APM_S) +#define TEE_WRITE_REE1_HP_MEM_APM_V 0x00000001U +#define TEE_WRITE_REE1_HP_MEM_APM_S 6 +/** TEE_WRITE_REE2_HP_MEM_APM : HRO; bitpos: [7]; default: 0; + * Configures hp_mem_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_HP_MEM_APM (BIT(7)) +#define TEE_WRITE_REE2_HP_MEM_APM_M (TEE_WRITE_REE2_HP_MEM_APM_V << TEE_WRITE_REE2_HP_MEM_APM_S) +#define TEE_WRITE_REE2_HP_MEM_APM_V 0x00000001U +#define TEE_WRITE_REE2_HP_MEM_APM_S 7 + +/** TEE_CPU_APM_CTRL_REG register + * cpu_apm read/write control register + */ +#define TEE_CPU_APM_CTRL_REG (DR_REG_TEE_BASE + 0x118) +/** TEE_READ_TEE_CPU_APM : R/W; bitpos: [0]; default: 1; + * Configures cpu_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CPU_APM (BIT(0)) +#define TEE_READ_TEE_CPU_APM_M (TEE_READ_TEE_CPU_APM_V << TEE_READ_TEE_CPU_APM_S) +#define TEE_READ_TEE_CPU_APM_V 0x00000001U +#define TEE_READ_TEE_CPU_APM_S 0 +/** TEE_READ_REE0_CPU_APM : HRO; bitpos: [1]; default: 0; + * Configures cpu_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CPU_APM (BIT(1)) +#define TEE_READ_REE0_CPU_APM_M (TEE_READ_REE0_CPU_APM_V << TEE_READ_REE0_CPU_APM_S) +#define TEE_READ_REE0_CPU_APM_V 0x00000001U +#define TEE_READ_REE0_CPU_APM_S 1 +/** TEE_READ_REE1_CPU_APM : HRO; bitpos: [2]; default: 0; + * Configures cpu_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CPU_APM (BIT(2)) +#define TEE_READ_REE1_CPU_APM_M (TEE_READ_REE1_CPU_APM_V << TEE_READ_REE1_CPU_APM_S) +#define TEE_READ_REE1_CPU_APM_V 0x00000001U +#define TEE_READ_REE1_CPU_APM_S 2 +/** TEE_READ_REE2_CPU_APM : HRO; bitpos: [3]; default: 0; + * Configures cpu_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CPU_APM (BIT(3)) +#define TEE_READ_REE2_CPU_APM_M (TEE_READ_REE2_CPU_APM_V << TEE_READ_REE2_CPU_APM_S) +#define TEE_READ_REE2_CPU_APM_V 0x00000001U +#define TEE_READ_REE2_CPU_APM_S 3 +/** TEE_WRITE_TEE_CPU_APM : R/W; bitpos: [4]; default: 1; + * Configures cpu_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CPU_APM (BIT(4)) +#define TEE_WRITE_TEE_CPU_APM_M (TEE_WRITE_TEE_CPU_APM_V << TEE_WRITE_TEE_CPU_APM_S) +#define TEE_WRITE_TEE_CPU_APM_V 0x00000001U +#define TEE_WRITE_TEE_CPU_APM_S 4 +/** TEE_WRITE_REE0_CPU_APM : HRO; bitpos: [5]; default: 0; + * Configures cpu_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CPU_APM (BIT(5)) +#define TEE_WRITE_REE0_CPU_APM_M (TEE_WRITE_REE0_CPU_APM_V << TEE_WRITE_REE0_CPU_APM_S) +#define TEE_WRITE_REE0_CPU_APM_V 0x00000001U +#define TEE_WRITE_REE0_CPU_APM_S 5 +/** TEE_WRITE_REE1_CPU_APM : HRO; bitpos: [6]; default: 0; + * Configures cpu_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CPU_APM (BIT(6)) +#define TEE_WRITE_REE1_CPU_APM_M (TEE_WRITE_REE1_CPU_APM_V << TEE_WRITE_REE1_CPU_APM_S) +#define TEE_WRITE_REE1_CPU_APM_V 0x00000001U +#define TEE_WRITE_REE1_CPU_APM_S 6 +/** TEE_WRITE_REE2_CPU_APM : HRO; bitpos: [7]; default: 0; + * Configures cpu_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CPU_APM (BIT(7)) +#define TEE_WRITE_REE2_CPU_APM_M (TEE_WRITE_REE2_CPU_APM_V << TEE_WRITE_REE2_CPU_APM_S) +#define TEE_WRITE_REE2_CPU_APM_V 0x00000001U +#define TEE_WRITE_REE2_CPU_APM_S 7 + +/** TEE_TEE_CTRL_REG register + * tee read/write control register + */ +#define TEE_TEE_CTRL_REG (DR_REG_TEE_BASE + 0x11c) +/** TEE_READ_TEE_TEE : R/W; bitpos: [0]; default: 1; + * Configures tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_TEE (BIT(0)) +#define TEE_READ_TEE_TEE_M (TEE_READ_TEE_TEE_V << TEE_READ_TEE_TEE_S) +#define TEE_READ_TEE_TEE_V 0x00000001U +#define TEE_READ_TEE_TEE_S 0 +/** TEE_READ_REE0_TEE : HRO; bitpos: [1]; default: 0; + * Configures tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_TEE (BIT(1)) +#define TEE_READ_REE0_TEE_M (TEE_READ_REE0_TEE_V << TEE_READ_REE0_TEE_S) +#define TEE_READ_REE0_TEE_V 0x00000001U +#define TEE_READ_REE0_TEE_S 1 +/** TEE_READ_REE1_TEE : HRO; bitpos: [2]; default: 0; + * Configures tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_TEE (BIT(2)) +#define TEE_READ_REE1_TEE_M (TEE_READ_REE1_TEE_V << TEE_READ_REE1_TEE_S) +#define TEE_READ_REE1_TEE_V 0x00000001U +#define TEE_READ_REE1_TEE_S 2 +/** TEE_READ_REE2_TEE : HRO; bitpos: [3]; default: 0; + * Configures tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_TEE (BIT(3)) +#define TEE_READ_REE2_TEE_M (TEE_READ_REE2_TEE_V << TEE_READ_REE2_TEE_S) +#define TEE_READ_REE2_TEE_V 0x00000001U +#define TEE_READ_REE2_TEE_S 3 +/** TEE_WRITE_TEE_TEE : R/W; bitpos: [4]; default: 1; + * Configures tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_TEE (BIT(4)) +#define TEE_WRITE_TEE_TEE_M (TEE_WRITE_TEE_TEE_V << TEE_WRITE_TEE_TEE_S) +#define TEE_WRITE_TEE_TEE_V 0x00000001U +#define TEE_WRITE_TEE_TEE_S 4 +/** TEE_WRITE_REE0_TEE : HRO; bitpos: [5]; default: 0; + * Configures tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_TEE (BIT(5)) +#define TEE_WRITE_REE0_TEE_M (TEE_WRITE_REE0_TEE_V << TEE_WRITE_REE0_TEE_S) +#define TEE_WRITE_REE0_TEE_V 0x00000001U +#define TEE_WRITE_REE0_TEE_S 5 +/** TEE_WRITE_REE1_TEE : HRO; bitpos: [6]; default: 0; + * Configures tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_TEE (BIT(6)) +#define TEE_WRITE_REE1_TEE_M (TEE_WRITE_REE1_TEE_V << TEE_WRITE_REE1_TEE_S) +#define TEE_WRITE_REE1_TEE_V 0x00000001U +#define TEE_WRITE_REE1_TEE_S 6 +/** TEE_WRITE_REE2_TEE : HRO; bitpos: [7]; default: 0; + * Configures tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_TEE (BIT(7)) +#define TEE_WRITE_REE2_TEE_M (TEE_WRITE_REE2_TEE_V << TEE_WRITE_REE2_TEE_S) +#define TEE_WRITE_REE2_TEE_V 0x00000001U +#define TEE_WRITE_REE2_TEE_S 7 + +/** TEE_KM_CTRL_REG register + * crypt read/write control register + */ +#define TEE_KM_CTRL_REG (DR_REG_TEE_BASE + 0x120) +/** TEE_READ_TEE_KM : R/W; bitpos: [0]; default: 1; + * Configures km registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_KM (BIT(0)) +#define TEE_READ_TEE_KM_M (TEE_READ_TEE_KM_V << TEE_READ_TEE_KM_S) +#define TEE_READ_TEE_KM_V 0x00000001U +#define TEE_READ_TEE_KM_S 0 +/** TEE_READ_REE0_KM : R/W; bitpos: [1]; default: 0; + * Configures km registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_KM (BIT(1)) +#define TEE_READ_REE0_KM_M (TEE_READ_REE0_KM_V << TEE_READ_REE0_KM_S) +#define TEE_READ_REE0_KM_V 0x00000001U +#define TEE_READ_REE0_KM_S 1 +/** TEE_READ_REE1_KM : R/W; bitpos: [2]; default: 0; + * Configures km registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_KM (BIT(2)) +#define TEE_READ_REE1_KM_M (TEE_READ_REE1_KM_V << TEE_READ_REE1_KM_S) +#define TEE_READ_REE1_KM_V 0x00000001U +#define TEE_READ_REE1_KM_S 2 +/** TEE_READ_REE2_KM : R/W; bitpos: [3]; default: 0; + * Configures km registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_KM (BIT(3)) +#define TEE_READ_REE2_KM_M (TEE_READ_REE2_KM_V << TEE_READ_REE2_KM_S) +#define TEE_READ_REE2_KM_V 0x00000001U +#define TEE_READ_REE2_KM_S 3 +/** TEE_WRITE_TEE_KM : R/W; bitpos: [4]; default: 1; + * Configures km registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_KM (BIT(4)) +#define TEE_WRITE_TEE_KM_M (TEE_WRITE_TEE_KM_V << TEE_WRITE_TEE_KM_S) +#define TEE_WRITE_TEE_KM_V 0x00000001U +#define TEE_WRITE_TEE_KM_S 4 +/** TEE_WRITE_REE0_KM : R/W; bitpos: [5]; default: 0; + * Configures km registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_KM (BIT(5)) +#define TEE_WRITE_REE0_KM_M (TEE_WRITE_REE0_KM_V << TEE_WRITE_REE0_KM_S) +#define TEE_WRITE_REE0_KM_V 0x00000001U +#define TEE_WRITE_REE0_KM_S 5 +/** TEE_WRITE_REE1_KM : R/W; bitpos: [6]; default: 0; + * Configures km registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_KM (BIT(6)) +#define TEE_WRITE_REE1_KM_M (TEE_WRITE_REE1_KM_V << TEE_WRITE_REE1_KM_S) +#define TEE_WRITE_REE1_KM_V 0x00000001U +#define TEE_WRITE_REE1_KM_S 6 +/** TEE_WRITE_REE2_KM : R/W; bitpos: [7]; default: 0; + * Configures km registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_KM (BIT(7)) +#define TEE_WRITE_REE2_KM_M (TEE_WRITE_REE2_KM_V << TEE_WRITE_REE2_KM_S) +#define TEE_WRITE_REE2_KM_V 0x00000001U +#define TEE_WRITE_REE2_KM_S 7 + +/** TEE_CRYPT_CTRL_REG register + * crypt read/write control register + */ +#define TEE_CRYPT_CTRL_REG (DR_REG_TEE_BASE + 0x124) +/** TEE_READ_TEE_CRYPT : R/W; bitpos: [0]; default: 1; + * Configures crypt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CRYPT (BIT(0)) +#define TEE_READ_TEE_CRYPT_M (TEE_READ_TEE_CRYPT_V << TEE_READ_TEE_CRYPT_S) +#define TEE_READ_TEE_CRYPT_V 0x00000001U +#define TEE_READ_TEE_CRYPT_S 0 +/** TEE_READ_REE0_CRYPT : R/W; bitpos: [1]; default: 0; + * Configures crypt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CRYPT (BIT(1)) +#define TEE_READ_REE0_CRYPT_M (TEE_READ_REE0_CRYPT_V << TEE_READ_REE0_CRYPT_S) +#define TEE_READ_REE0_CRYPT_V 0x00000001U +#define TEE_READ_REE0_CRYPT_S 1 +/** TEE_READ_REE1_CRYPT : R/W; bitpos: [2]; default: 0; + * Configures crypt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CRYPT (BIT(2)) +#define TEE_READ_REE1_CRYPT_M (TEE_READ_REE1_CRYPT_V << TEE_READ_REE1_CRYPT_S) +#define TEE_READ_REE1_CRYPT_V 0x00000001U +#define TEE_READ_REE1_CRYPT_S 2 +/** TEE_READ_REE2_CRYPT : R/W; bitpos: [3]; default: 0; + * Configures crypt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CRYPT (BIT(3)) +#define TEE_READ_REE2_CRYPT_M (TEE_READ_REE2_CRYPT_V << TEE_READ_REE2_CRYPT_S) +#define TEE_READ_REE2_CRYPT_V 0x00000001U +#define TEE_READ_REE2_CRYPT_S 3 +/** TEE_WRITE_TEE_CRYPT : R/W; bitpos: [4]; default: 1; + * Configures crypt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CRYPT (BIT(4)) +#define TEE_WRITE_TEE_CRYPT_M (TEE_WRITE_TEE_CRYPT_V << TEE_WRITE_TEE_CRYPT_S) +#define TEE_WRITE_TEE_CRYPT_V 0x00000001U +#define TEE_WRITE_TEE_CRYPT_S 4 +/** TEE_WRITE_REE0_CRYPT : R/W; bitpos: [5]; default: 0; + * Configures crypt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CRYPT (BIT(5)) +#define TEE_WRITE_REE0_CRYPT_M (TEE_WRITE_REE0_CRYPT_V << TEE_WRITE_REE0_CRYPT_S) +#define TEE_WRITE_REE0_CRYPT_V 0x00000001U +#define TEE_WRITE_REE0_CRYPT_S 5 +/** TEE_WRITE_REE1_CRYPT : R/W; bitpos: [6]; default: 0; + * Configures crypt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CRYPT (BIT(6)) +#define TEE_WRITE_REE1_CRYPT_M (TEE_WRITE_REE1_CRYPT_V << TEE_WRITE_REE1_CRYPT_S) +#define TEE_WRITE_REE1_CRYPT_V 0x00000001U +#define TEE_WRITE_REE1_CRYPT_S 6 +/** TEE_WRITE_REE2_CRYPT : R/W; bitpos: [7]; default: 0; + * Configures crypt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CRYPT (BIT(7)) +#define TEE_WRITE_REE2_CRYPT_M (TEE_WRITE_REE2_CRYPT_V << TEE_WRITE_REE2_CRYPT_S) +#define TEE_WRITE_REE2_CRYPT_V 0x00000001U +#define TEE_WRITE_REE2_CRYPT_S 7 + +/** TEE_CORE0_TRACE_CTRL_REG register + * core0_trace read/write control register + */ +#define TEE_CORE0_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x128) +/** TEE_READ_TEE_CORE0_TRACE : R/W; bitpos: [0]; default: 1; + * Configures core0_trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CORE0_TRACE (BIT(0)) +#define TEE_READ_TEE_CORE0_TRACE_M (TEE_READ_TEE_CORE0_TRACE_V << TEE_READ_TEE_CORE0_TRACE_S) +#define TEE_READ_TEE_CORE0_TRACE_V 0x00000001U +#define TEE_READ_TEE_CORE0_TRACE_S 0 +/** TEE_READ_REE0_CORE0_TRACE : R/W; bitpos: [1]; default: 0; + * Configures core0_trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CORE0_TRACE (BIT(1)) +#define TEE_READ_REE0_CORE0_TRACE_M (TEE_READ_REE0_CORE0_TRACE_V << TEE_READ_REE0_CORE0_TRACE_S) +#define TEE_READ_REE0_CORE0_TRACE_V 0x00000001U +#define TEE_READ_REE0_CORE0_TRACE_S 1 +/** TEE_READ_REE1_CORE0_TRACE : R/W; bitpos: [2]; default: 0; + * Configures core0_trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CORE0_TRACE (BIT(2)) +#define TEE_READ_REE1_CORE0_TRACE_M (TEE_READ_REE1_CORE0_TRACE_V << TEE_READ_REE1_CORE0_TRACE_S) +#define TEE_READ_REE1_CORE0_TRACE_V 0x00000001U +#define TEE_READ_REE1_CORE0_TRACE_S 2 +/** TEE_READ_REE2_CORE0_TRACE : R/W; bitpos: [3]; default: 0; + * Configures core0_trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CORE0_TRACE (BIT(3)) +#define TEE_READ_REE2_CORE0_TRACE_M (TEE_READ_REE2_CORE0_TRACE_V << TEE_READ_REE2_CORE0_TRACE_S) +#define TEE_READ_REE2_CORE0_TRACE_V 0x00000001U +#define TEE_READ_REE2_CORE0_TRACE_S 3 +/** TEE_WRITE_TEE_CORE0_TRACE : R/W; bitpos: [4]; default: 1; + * Configures core0_trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CORE0_TRACE (BIT(4)) +#define TEE_WRITE_TEE_CORE0_TRACE_M (TEE_WRITE_TEE_CORE0_TRACE_V << TEE_WRITE_TEE_CORE0_TRACE_S) +#define TEE_WRITE_TEE_CORE0_TRACE_V 0x00000001U +#define TEE_WRITE_TEE_CORE0_TRACE_S 4 +/** TEE_WRITE_REE0_CORE0_TRACE : R/W; bitpos: [5]; default: 0; + * Configures core0_trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CORE0_TRACE (BIT(5)) +#define TEE_WRITE_REE0_CORE0_TRACE_M (TEE_WRITE_REE0_CORE0_TRACE_V << TEE_WRITE_REE0_CORE0_TRACE_S) +#define TEE_WRITE_REE0_CORE0_TRACE_V 0x00000001U +#define TEE_WRITE_REE0_CORE0_TRACE_S 5 +/** TEE_WRITE_REE1_CORE0_TRACE : R/W; bitpos: [6]; default: 0; + * Configures core0_trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CORE0_TRACE (BIT(6)) +#define TEE_WRITE_REE1_CORE0_TRACE_M (TEE_WRITE_REE1_CORE0_TRACE_V << TEE_WRITE_REE1_CORE0_TRACE_S) +#define TEE_WRITE_REE1_CORE0_TRACE_V 0x00000001U +#define TEE_WRITE_REE1_CORE0_TRACE_S 6 +/** TEE_WRITE_REE2_CORE0_TRACE : R/W; bitpos: [7]; default: 0; + * Configures core0_trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CORE0_TRACE (BIT(7)) +#define TEE_WRITE_REE2_CORE0_TRACE_M (TEE_WRITE_REE2_CORE0_TRACE_V << TEE_WRITE_REE2_CORE0_TRACE_S) +#define TEE_WRITE_REE2_CORE0_TRACE_V 0x00000001U +#define TEE_WRITE_REE2_CORE0_TRACE_S 7 + +/** TEE_CORE1_TRACE_CTRL_REG register + * core1_trace read/write control register + */ +#define TEE_CORE1_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x12c) +/** TEE_READ_TEE_CORE1_TRACE : R/W; bitpos: [0]; default: 1; + * Configures core1_trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CORE1_TRACE (BIT(0)) +#define TEE_READ_TEE_CORE1_TRACE_M (TEE_READ_TEE_CORE1_TRACE_V << TEE_READ_TEE_CORE1_TRACE_S) +#define TEE_READ_TEE_CORE1_TRACE_V 0x00000001U +#define TEE_READ_TEE_CORE1_TRACE_S 0 +/** TEE_READ_REE0_CORE1_TRACE : R/W; bitpos: [1]; default: 0; + * Configures core1_trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CORE1_TRACE (BIT(1)) +#define TEE_READ_REE0_CORE1_TRACE_M (TEE_READ_REE0_CORE1_TRACE_V << TEE_READ_REE0_CORE1_TRACE_S) +#define TEE_READ_REE0_CORE1_TRACE_V 0x00000001U +#define TEE_READ_REE0_CORE1_TRACE_S 1 +/** TEE_READ_REE1_CORE1_TRACE : R/W; bitpos: [2]; default: 0; + * Configures core1_trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CORE1_TRACE (BIT(2)) +#define TEE_READ_REE1_CORE1_TRACE_M (TEE_READ_REE1_CORE1_TRACE_V << TEE_READ_REE1_CORE1_TRACE_S) +#define TEE_READ_REE1_CORE1_TRACE_V 0x00000001U +#define TEE_READ_REE1_CORE1_TRACE_S 2 +/** TEE_READ_REE2_CORE1_TRACE : R/W; bitpos: [3]; default: 0; + * Configures core1_trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CORE1_TRACE (BIT(3)) +#define TEE_READ_REE2_CORE1_TRACE_M (TEE_READ_REE2_CORE1_TRACE_V << TEE_READ_REE2_CORE1_TRACE_S) +#define TEE_READ_REE2_CORE1_TRACE_V 0x00000001U +#define TEE_READ_REE2_CORE1_TRACE_S 3 +/** TEE_WRITE_TEE_CORE1_TRACE : R/W; bitpos: [4]; default: 1; + * Configures core1_trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CORE1_TRACE (BIT(4)) +#define TEE_WRITE_TEE_CORE1_TRACE_M (TEE_WRITE_TEE_CORE1_TRACE_V << TEE_WRITE_TEE_CORE1_TRACE_S) +#define TEE_WRITE_TEE_CORE1_TRACE_V 0x00000001U +#define TEE_WRITE_TEE_CORE1_TRACE_S 4 +/** TEE_WRITE_REE0_CORE1_TRACE : R/W; bitpos: [5]; default: 0; + * Configures core1_trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CORE1_TRACE (BIT(5)) +#define TEE_WRITE_REE0_CORE1_TRACE_M (TEE_WRITE_REE0_CORE1_TRACE_V << TEE_WRITE_REE0_CORE1_TRACE_S) +#define TEE_WRITE_REE0_CORE1_TRACE_V 0x00000001U +#define TEE_WRITE_REE0_CORE1_TRACE_S 5 +/** TEE_WRITE_REE1_CORE1_TRACE : R/W; bitpos: [6]; default: 0; + * Configures core1_trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CORE1_TRACE (BIT(6)) +#define TEE_WRITE_REE1_CORE1_TRACE_M (TEE_WRITE_REE1_CORE1_TRACE_V << TEE_WRITE_REE1_CORE1_TRACE_S) +#define TEE_WRITE_REE1_CORE1_TRACE_V 0x00000001U +#define TEE_WRITE_REE1_CORE1_TRACE_S 6 +/** TEE_WRITE_REE2_CORE1_TRACE : R/W; bitpos: [7]; default: 0; + * Configures core1_trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CORE1_TRACE (BIT(7)) +#define TEE_WRITE_REE2_CORE1_TRACE_M (TEE_WRITE_REE2_CORE1_TRACE_V << TEE_WRITE_REE2_CORE1_TRACE_S) +#define TEE_WRITE_REE2_CORE1_TRACE_V 0x00000001U +#define TEE_WRITE_REE2_CORE1_TRACE_S 7 + +/** TEE_CPU_BUS_MONITOR_CTRL_REG register + * cpu_bus_monitor read/write control register + */ +#define TEE_CPU_BUS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x130) +/** TEE_READ_TEE_CPU_BUS_MONITOR : R/W; bitpos: [0]; default: 1; + * Configures cpu_bus_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CPU_BUS_MONITOR (BIT(0)) +#define TEE_READ_TEE_CPU_BUS_MONITOR_M (TEE_READ_TEE_CPU_BUS_MONITOR_V << TEE_READ_TEE_CPU_BUS_MONITOR_S) +#define TEE_READ_TEE_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_TEE_CPU_BUS_MONITOR_S 0 +/** TEE_READ_REE0_CPU_BUS_MONITOR : R/W; bitpos: [1]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CPU_BUS_MONITOR (BIT(1)) +#define TEE_READ_REE0_CPU_BUS_MONITOR_M (TEE_READ_REE0_CPU_BUS_MONITOR_V << TEE_READ_REE0_CPU_BUS_MONITOR_S) +#define TEE_READ_REE0_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_REE0_CPU_BUS_MONITOR_S 1 +/** TEE_READ_REE1_CPU_BUS_MONITOR : R/W; bitpos: [2]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CPU_BUS_MONITOR (BIT(2)) +#define TEE_READ_REE1_CPU_BUS_MONITOR_M (TEE_READ_REE1_CPU_BUS_MONITOR_V << TEE_READ_REE1_CPU_BUS_MONITOR_S) +#define TEE_READ_REE1_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_REE1_CPU_BUS_MONITOR_S 2 +/** TEE_READ_REE2_CPU_BUS_MONITOR : R/W; bitpos: [3]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CPU_BUS_MONITOR (BIT(3)) +#define TEE_READ_REE2_CPU_BUS_MONITOR_M (TEE_READ_REE2_CPU_BUS_MONITOR_V << TEE_READ_REE2_CPU_BUS_MONITOR_S) +#define TEE_READ_REE2_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_READ_REE2_CPU_BUS_MONITOR_S 3 +/** TEE_WRITE_TEE_CPU_BUS_MONITOR : R/W; bitpos: [4]; default: 1; + * Configures cpu_bus_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CPU_BUS_MONITOR (BIT(4)) +#define TEE_WRITE_TEE_CPU_BUS_MONITOR_M (TEE_WRITE_TEE_CPU_BUS_MONITOR_V << TEE_WRITE_TEE_CPU_BUS_MONITOR_S) +#define TEE_WRITE_TEE_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_TEE_CPU_BUS_MONITOR_S 4 +/** TEE_WRITE_REE0_CPU_BUS_MONITOR : R/W; bitpos: [5]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CPU_BUS_MONITOR (BIT(5)) +#define TEE_WRITE_REE0_CPU_BUS_MONITOR_M (TEE_WRITE_REE0_CPU_BUS_MONITOR_V << TEE_WRITE_REE0_CPU_BUS_MONITOR_S) +#define TEE_WRITE_REE0_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE0_CPU_BUS_MONITOR_S 5 +/** TEE_WRITE_REE1_CPU_BUS_MONITOR : R/W; bitpos: [6]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CPU_BUS_MONITOR (BIT(6)) +#define TEE_WRITE_REE1_CPU_BUS_MONITOR_M (TEE_WRITE_REE1_CPU_BUS_MONITOR_V << TEE_WRITE_REE1_CPU_BUS_MONITOR_S) +#define TEE_WRITE_REE1_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE1_CPU_BUS_MONITOR_S 6 +/** TEE_WRITE_REE2_CPU_BUS_MONITOR : R/W; bitpos: [7]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CPU_BUS_MONITOR (BIT(7)) +#define TEE_WRITE_REE2_CPU_BUS_MONITOR_M (TEE_WRITE_REE2_CPU_BUS_MONITOR_V << TEE_WRITE_REE2_CPU_BUS_MONITOR_S) +#define TEE_WRITE_REE2_CPU_BUS_MONITOR_V 0x00000001U +#define TEE_WRITE_REE2_CPU_BUS_MONITOR_S 7 + +/** TEE_INTPRI_REG_CTRL_REG register + * intpri_reg read/write control register + */ +#define TEE_INTPRI_REG_CTRL_REG (DR_REG_TEE_BASE + 0x134) +/** TEE_READ_TEE_INTPRI_REG : R/W; bitpos: [0]; default: 1; + * Configures intpri_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_INTPRI_REG (BIT(0)) +#define TEE_READ_TEE_INTPRI_REG_M (TEE_READ_TEE_INTPRI_REG_V << TEE_READ_TEE_INTPRI_REG_S) +#define TEE_READ_TEE_INTPRI_REG_V 0x00000001U +#define TEE_READ_TEE_INTPRI_REG_S 0 +/** TEE_READ_REE0_INTPRI_REG : R/W; bitpos: [1]; default: 0; + * Configures intpri_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_INTPRI_REG (BIT(1)) +#define TEE_READ_REE0_INTPRI_REG_M (TEE_READ_REE0_INTPRI_REG_V << TEE_READ_REE0_INTPRI_REG_S) +#define TEE_READ_REE0_INTPRI_REG_V 0x00000001U +#define TEE_READ_REE0_INTPRI_REG_S 1 +/** TEE_READ_REE1_INTPRI_REG : R/W; bitpos: [2]; default: 0; + * Configures intpri_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_INTPRI_REG (BIT(2)) +#define TEE_READ_REE1_INTPRI_REG_M (TEE_READ_REE1_INTPRI_REG_V << TEE_READ_REE1_INTPRI_REG_S) +#define TEE_READ_REE1_INTPRI_REG_V 0x00000001U +#define TEE_READ_REE1_INTPRI_REG_S 2 +/** TEE_READ_REE2_INTPRI_REG : R/W; bitpos: [3]; default: 0; + * Configures intpri_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_INTPRI_REG (BIT(3)) +#define TEE_READ_REE2_INTPRI_REG_M (TEE_READ_REE2_INTPRI_REG_V << TEE_READ_REE2_INTPRI_REG_S) +#define TEE_READ_REE2_INTPRI_REG_V 0x00000001U +#define TEE_READ_REE2_INTPRI_REG_S 3 +/** TEE_WRITE_TEE_INTPRI_REG : R/W; bitpos: [4]; default: 1; + * Configures intpri_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_INTPRI_REG (BIT(4)) +#define TEE_WRITE_TEE_INTPRI_REG_M (TEE_WRITE_TEE_INTPRI_REG_V << TEE_WRITE_TEE_INTPRI_REG_S) +#define TEE_WRITE_TEE_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_TEE_INTPRI_REG_S 4 +/** TEE_WRITE_REE0_INTPRI_REG : R/W; bitpos: [5]; default: 0; + * Configures intpri_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_INTPRI_REG (BIT(5)) +#define TEE_WRITE_REE0_INTPRI_REG_M (TEE_WRITE_REE0_INTPRI_REG_V << TEE_WRITE_REE0_INTPRI_REG_S) +#define TEE_WRITE_REE0_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_REE0_INTPRI_REG_S 5 +/** TEE_WRITE_REE1_INTPRI_REG : R/W; bitpos: [6]; default: 0; + * Configures intpri_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_INTPRI_REG (BIT(6)) +#define TEE_WRITE_REE1_INTPRI_REG_M (TEE_WRITE_REE1_INTPRI_REG_V << TEE_WRITE_REE1_INTPRI_REG_S) +#define TEE_WRITE_REE1_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_REE1_INTPRI_REG_S 6 +/** TEE_WRITE_REE2_INTPRI_REG : R/W; bitpos: [7]; default: 0; + * Configures intpri_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_INTPRI_REG (BIT(7)) +#define TEE_WRITE_REE2_INTPRI_REG_M (TEE_WRITE_REE2_INTPRI_REG_V << TEE_WRITE_REE2_INTPRI_REG_S) +#define TEE_WRITE_REE2_INTPRI_REG_V 0x00000001U +#define TEE_WRITE_REE2_INTPRI_REG_S 7 + +/** TEE_CACHE_CFG_CTRL_REG register + * cache_cfg read/write control register + */ +#define TEE_CACHE_CFG_CTRL_REG (DR_REG_TEE_BASE + 0x138) +/** TEE_READ_TEE_CACHE_CFG : R/W; bitpos: [0]; default: 1; + * Configures cache_cfg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_CACHE_CFG (BIT(0)) +#define TEE_READ_TEE_CACHE_CFG_M (TEE_READ_TEE_CACHE_CFG_V << TEE_READ_TEE_CACHE_CFG_S) +#define TEE_READ_TEE_CACHE_CFG_V 0x00000001U +#define TEE_READ_TEE_CACHE_CFG_S 0 +/** TEE_READ_REE0_CACHE_CFG : R/W; bitpos: [1]; default: 0; + * Configures cache_cfg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_CACHE_CFG (BIT(1)) +#define TEE_READ_REE0_CACHE_CFG_M (TEE_READ_REE0_CACHE_CFG_V << TEE_READ_REE0_CACHE_CFG_S) +#define TEE_READ_REE0_CACHE_CFG_V 0x00000001U +#define TEE_READ_REE0_CACHE_CFG_S 1 +/** TEE_READ_REE1_CACHE_CFG : R/W; bitpos: [2]; default: 0; + * Configures cache_cfg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_CACHE_CFG (BIT(2)) +#define TEE_READ_REE1_CACHE_CFG_M (TEE_READ_REE1_CACHE_CFG_V << TEE_READ_REE1_CACHE_CFG_S) +#define TEE_READ_REE1_CACHE_CFG_V 0x00000001U +#define TEE_READ_REE1_CACHE_CFG_S 2 +/** TEE_READ_REE2_CACHE_CFG : R/W; bitpos: [3]; default: 0; + * Configures cache_cfg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_CACHE_CFG (BIT(3)) +#define TEE_READ_REE2_CACHE_CFG_M (TEE_READ_REE2_CACHE_CFG_V << TEE_READ_REE2_CACHE_CFG_S) +#define TEE_READ_REE2_CACHE_CFG_V 0x00000001U +#define TEE_READ_REE2_CACHE_CFG_S 3 +/** TEE_WRITE_TEE_CACHE_CFG : R/W; bitpos: [4]; default: 1; + * Configures cache_cfg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_CACHE_CFG (BIT(4)) +#define TEE_WRITE_TEE_CACHE_CFG_M (TEE_WRITE_TEE_CACHE_CFG_V << TEE_WRITE_TEE_CACHE_CFG_S) +#define TEE_WRITE_TEE_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_TEE_CACHE_CFG_S 4 +/** TEE_WRITE_REE0_CACHE_CFG : R/W; bitpos: [5]; default: 0; + * Configures cache_cfg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_CACHE_CFG (BIT(5)) +#define TEE_WRITE_REE0_CACHE_CFG_M (TEE_WRITE_REE0_CACHE_CFG_V << TEE_WRITE_REE0_CACHE_CFG_S) +#define TEE_WRITE_REE0_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_REE0_CACHE_CFG_S 5 +/** TEE_WRITE_REE1_CACHE_CFG : R/W; bitpos: [6]; default: 0; + * Configures cache_cfg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_CACHE_CFG (BIT(6)) +#define TEE_WRITE_REE1_CACHE_CFG_M (TEE_WRITE_REE1_CACHE_CFG_V << TEE_WRITE_REE1_CACHE_CFG_S) +#define TEE_WRITE_REE1_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_REE1_CACHE_CFG_S 6 +/** TEE_WRITE_REE2_CACHE_CFG : R/W; bitpos: [7]; default: 0; + * Configures cache_cfg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_CACHE_CFG (BIT(7)) +#define TEE_WRITE_REE2_CACHE_CFG_M (TEE_WRITE_REE2_CACHE_CFG_V << TEE_WRITE_REE2_CACHE_CFG_S) +#define TEE_WRITE_REE2_CACHE_CFG_V 0x00000001U +#define TEE_WRITE_REE2_CACHE_CFG_S 7 + +/** TEE_MODEM_CTRL_REG register + * modem read/write control register + */ +#define TEE_MODEM_CTRL_REG (DR_REG_TEE_BASE + 0x13c) +/** TEE_READ_TEE_MODEM : R/W; bitpos: [0]; default: 1; + * Configures modem registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_MODEM (BIT(0)) +#define TEE_READ_TEE_MODEM_M (TEE_READ_TEE_MODEM_V << TEE_READ_TEE_MODEM_S) +#define TEE_READ_TEE_MODEM_V 0x00000001U +#define TEE_READ_TEE_MODEM_S 0 +/** TEE_READ_REE0_MODEM : R/W; bitpos: [1]; default: 0; + * Configures modem registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_MODEM (BIT(1)) +#define TEE_READ_REE0_MODEM_M (TEE_READ_REE0_MODEM_V << TEE_READ_REE0_MODEM_S) +#define TEE_READ_REE0_MODEM_V 0x00000001U +#define TEE_READ_REE0_MODEM_S 1 +/** TEE_READ_REE1_MODEM : R/W; bitpos: [2]; default: 0; + * Configures modem registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_MODEM (BIT(2)) +#define TEE_READ_REE1_MODEM_M (TEE_READ_REE1_MODEM_V << TEE_READ_REE1_MODEM_S) +#define TEE_READ_REE1_MODEM_V 0x00000001U +#define TEE_READ_REE1_MODEM_S 2 +/** TEE_READ_REE2_MODEM : R/W; bitpos: [3]; default: 0; + * Configures modem registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_MODEM (BIT(3)) +#define TEE_READ_REE2_MODEM_M (TEE_READ_REE2_MODEM_V << TEE_READ_REE2_MODEM_S) +#define TEE_READ_REE2_MODEM_V 0x00000001U +#define TEE_READ_REE2_MODEM_S 3 +/** TEE_WRITE_TEE_MODEM : R/W; bitpos: [4]; default: 1; + * Configures modem registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_MODEM (BIT(4)) +#define TEE_WRITE_TEE_MODEM_M (TEE_WRITE_TEE_MODEM_V << TEE_WRITE_TEE_MODEM_S) +#define TEE_WRITE_TEE_MODEM_V 0x00000001U +#define TEE_WRITE_TEE_MODEM_S 4 +/** TEE_WRITE_REE0_MODEM : R/W; bitpos: [5]; default: 0; + * Configures modem registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_MODEM (BIT(5)) +#define TEE_WRITE_REE0_MODEM_M (TEE_WRITE_REE0_MODEM_V << TEE_WRITE_REE0_MODEM_S) +#define TEE_WRITE_REE0_MODEM_V 0x00000001U +#define TEE_WRITE_REE0_MODEM_S 5 +/** TEE_WRITE_REE1_MODEM : R/W; bitpos: [6]; default: 0; + * Configures modem registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_MODEM (BIT(6)) +#define TEE_WRITE_REE1_MODEM_M (TEE_WRITE_REE1_MODEM_V << TEE_WRITE_REE1_MODEM_S) +#define TEE_WRITE_REE1_MODEM_V 0x00000001U +#define TEE_WRITE_REE1_MODEM_S 6 +/** TEE_WRITE_REE2_MODEM : R/W; bitpos: [7]; default: 0; + * Configures modem registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_MODEM (BIT(7)) +#define TEE_WRITE_REE2_MODEM_M (TEE_WRITE_REE2_MODEM_V << TEE_WRITE_REE2_MODEM_S) +#define TEE_WRITE_REE2_MODEM_V 0x00000001U +#define TEE_WRITE_REE2_MODEM_S 7 + +/** TEE_ZERO_DET_CTRL_REG register + * zero_det read/write control register + */ +#define TEE_ZERO_DET_CTRL_REG (DR_REG_TEE_BASE + 0x140) +/** TEE_READ_TEE_ZERO_DET : R/W; bitpos: [0]; default: 1; + * Configures zero_det registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_TEE_ZERO_DET (BIT(0)) +#define TEE_READ_TEE_ZERO_DET_M (TEE_READ_TEE_ZERO_DET_V << TEE_READ_TEE_ZERO_DET_S) +#define TEE_READ_TEE_ZERO_DET_V 0x00000001U +#define TEE_READ_TEE_ZERO_DET_S 0 +/** TEE_READ_REE0_ZERO_DET : R/W; bitpos: [1]; default: 0; + * Configures zero_det registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE0_ZERO_DET (BIT(1)) +#define TEE_READ_REE0_ZERO_DET_M (TEE_READ_REE0_ZERO_DET_V << TEE_READ_REE0_ZERO_DET_S) +#define TEE_READ_REE0_ZERO_DET_V 0x00000001U +#define TEE_READ_REE0_ZERO_DET_S 1 +/** TEE_READ_REE1_ZERO_DET : R/W; bitpos: [2]; default: 0; + * Configures zero_det registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE1_ZERO_DET (BIT(2)) +#define TEE_READ_REE1_ZERO_DET_M (TEE_READ_REE1_ZERO_DET_V << TEE_READ_REE1_ZERO_DET_S) +#define TEE_READ_REE1_ZERO_DET_V 0x00000001U +#define TEE_READ_REE1_ZERO_DET_S 2 +/** TEE_READ_REE2_ZERO_DET : R/W; bitpos: [3]; default: 0; + * Configures zero_det registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ +#define TEE_READ_REE2_ZERO_DET (BIT(3)) +#define TEE_READ_REE2_ZERO_DET_M (TEE_READ_REE2_ZERO_DET_V << TEE_READ_REE2_ZERO_DET_S) +#define TEE_READ_REE2_ZERO_DET_V 0x00000001U +#define TEE_READ_REE2_ZERO_DET_S 3 +/** TEE_WRITE_TEE_ZERO_DET : R/W; bitpos: [4]; default: 1; + * Configures zero_det registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_TEE_ZERO_DET (BIT(4)) +#define TEE_WRITE_TEE_ZERO_DET_M (TEE_WRITE_TEE_ZERO_DET_V << TEE_WRITE_TEE_ZERO_DET_S) +#define TEE_WRITE_TEE_ZERO_DET_V 0x00000001U +#define TEE_WRITE_TEE_ZERO_DET_S 4 +/** TEE_WRITE_REE0_ZERO_DET : R/W; bitpos: [5]; default: 0; + * Configures zero_det registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE0_ZERO_DET (BIT(5)) +#define TEE_WRITE_REE0_ZERO_DET_M (TEE_WRITE_REE0_ZERO_DET_V << TEE_WRITE_REE0_ZERO_DET_S) +#define TEE_WRITE_REE0_ZERO_DET_V 0x00000001U +#define TEE_WRITE_REE0_ZERO_DET_S 5 +/** TEE_WRITE_REE1_ZERO_DET : R/W; bitpos: [6]; default: 0; + * Configures zero_det registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE1_ZERO_DET (BIT(6)) +#define TEE_WRITE_REE1_ZERO_DET_M (TEE_WRITE_REE1_ZERO_DET_V << TEE_WRITE_REE1_ZERO_DET_S) +#define TEE_WRITE_REE1_ZERO_DET_V 0x00000001U +#define TEE_WRITE_REE1_ZERO_DET_S 6 +/** TEE_WRITE_REE2_ZERO_DET : R/W; bitpos: [7]; default: 0; + * Configures zero_det registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ +#define TEE_WRITE_REE2_ZERO_DET (BIT(7)) +#define TEE_WRITE_REE2_ZERO_DET_M (TEE_WRITE_REE2_ZERO_DET_V << TEE_WRITE_REE2_ZERO_DET_S) +#define TEE_WRITE_REE2_ZERO_DET_V 0x00000001U +#define TEE_WRITE_REE2_ZERO_DET_S 7 + +/** TEE_BUS_ERR_CONF_REG register + * Clock gating register + */ +#define TEE_BUS_ERR_CONF_REG (DR_REG_TEE_BASE + 0xff0) +/** TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ +#define TEE_BUS_ERR_RESP_EN (BIT(0)) +#define TEE_BUS_ERR_RESP_EN_M (TEE_BUS_ERR_RESP_EN_V << TEE_BUS_ERR_RESP_EN_S) +#define TEE_BUS_ERR_RESP_EN_V 0x00000001U +#define TEE_BUS_ERR_RESP_EN_S 0 + +/** TEE_CLOCK_GATE_REG register + * Clock gating register + */ +#define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0xff8) +/** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ +#define TEE_CLK_EN (BIT(0)) +#define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) +#define TEE_CLK_EN_V 0x00000001U +#define TEE_CLK_EN_S 0 + +/** TEE_DATE_REG register + * Version control register + */ +#define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) +/** TEE_DATE : R/W; bitpos: [27:0]; default: 38810240; + * Version control register + */ +#define TEE_DATE 0x0FFFFFFFU +#define TEE_DATE_M (TEE_DATE_V << TEE_DATE_S) +#define TEE_DATE_V 0x0FFFFFFFU +#define TEE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h4/register/hw_ver_mp/soc/tee_struct.h b/components/soc/esp32h4/register/hw_ver_mp/soc/tee_struct.h new file mode 100644 index 0000000000..02b8a757c5 --- /dev/null +++ b/components/soc/esp32h4/register/hw_ver_mp/soc/tee_struct.h @@ -0,0 +1,2999 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Tee mode control register */ +/** Type of mn_mode_ctrl register + * TEE mode control register + */ +typedef union { + struct { + /** mn_mode : R/W; bitpos: [1:0]; default: 0; + * Configures Mn security level mode. + * 0: tee_mode + * 1: ree_mode0 + * 2: ree_mode1 + * 3: ree_mode2 + */ + uint32_t mn_mode:2; + /** mn_lock : R/W; bitpos: [2]; default: 0; + * Set 1 to lock m0 tee configuration + */ + uint32_t mn_lock:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} tee_mn_mode_ctrl_reg_t; + + +/** Group: read write control register */ +/** Type of gpspi0_ctrl register + * gpspi0 read/write control register + */ +typedef union { + struct { + /** read_tee_gpspi0 : R/W; bitpos: [0]; default: 1; + * Configures gpspi0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_gpspi0:1; + /** read_ree0_gpspi0 : R/W; bitpos: [1]; default: 0; + * Configures gpspi0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_gpspi0:1; + /** read_ree1_gpspi0 : R/W; bitpos: [2]; default: 0; + * Configures gpspi0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_gpspi0:1; + /** read_ree2_gpspi0 : R/W; bitpos: [3]; default: 0; + * Configures gpspi0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_gpspi0:1; + /** write_tee_gpspi0 : R/W; bitpos: [4]; default: 1; + * Configures gpspi0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_gpspi0:1; + /** write_ree0_gpspi0 : R/W; bitpos: [5]; default: 0; + * Configures gpspi0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_gpspi0:1; + /** write_ree1_gpspi0 : R/W; bitpos: [6]; default: 0; + * Configures gpspi0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_gpspi0:1; + /** write_ree2_gpspi0 : R/W; bitpos: [7]; default: 0; + * Configures gpspi0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_gpspi0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_gpspi0_ctrl_reg_t; + +/** Type of gpspi1_ctrl register + * gpspi1 read/write control register + */ +typedef union { + struct { + /** read_tee_gpspi1 : R/W; bitpos: [0]; default: 1; + * Configures gpspi1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_gpspi1:1; + /** read_ree0_gpspi1 : R/W; bitpos: [1]; default: 0; + * Configures gpspi1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_gpspi1:1; + /** read_ree1_gpspi1 : R/W; bitpos: [2]; default: 0; + * Configures gpspi1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_gpspi1:1; + /** read_ree2_gpspi1 : R/W; bitpos: [3]; default: 0; + * Configures gpspi1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_gpspi1:1; + /** write_tee_gpspi1 : R/W; bitpos: [4]; default: 1; + * Configures gpspi1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_gpspi1:1; + /** write_ree0_gpspi1 : R/W; bitpos: [5]; default: 0; + * Configures gpspi1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_gpspi1:1; + /** write_ree1_gpspi1 : R/W; bitpos: [6]; default: 0; + * Configures gpspi1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_gpspi1:1; + /** write_ree2_gpspi1 : R/W; bitpos: [7]; default: 0; + * Configures gpspi1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_gpspi1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_gpspi1_ctrl_reg_t; + +/** Type of uart0_ctrl register + * uart0 read/write control register + */ +typedef union { + struct { + /** read_tee_uart0 : R/W; bitpos: [0]; default: 1; + * Configures uart0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uart0:1; + /** read_ree0_uart0 : R/W; bitpos: [1]; default: 0; + * Configures uart0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uart0:1; + /** read_ree1_uart0 : R/W; bitpos: [2]; default: 0; + * Configures uart0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uart0:1; + /** read_ree2_uart0 : R/W; bitpos: [3]; default: 0; + * Configures uart0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uart0:1; + /** write_tee_uart0 : R/W; bitpos: [4]; default: 1; + * Configures uart0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uart0:1; + /** write_ree0_uart0 : R/W; bitpos: [5]; default: 0; + * Configures uart0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uart0:1; + /** write_ree1_uart0 : R/W; bitpos: [6]; default: 0; + * Configures uart0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uart0:1; + /** write_ree2_uart0 : R/W; bitpos: [7]; default: 0; + * Configures uart0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uart0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_uart0_ctrl_reg_t; + +/** Type of uart1_ctrl register + * uart1 read/write control register + */ +typedef union { + struct { + /** read_tee_uart1 : R/W; bitpos: [0]; default: 1; + * Configures uart1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uart1:1; + /** read_ree0_uart1 : R/W; bitpos: [1]; default: 0; + * Configures uart1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uart1:1; + /** read_ree1_uart1 : R/W; bitpos: [2]; default: 0; + * Configures uart1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uart1:1; + /** read_ree2_uart1 : R/W; bitpos: [3]; default: 0; + * Configures uart1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uart1:1; + /** write_tee_uart1 : R/W; bitpos: [4]; default: 1; + * Configures uart1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uart1:1; + /** write_ree0_uart1 : R/W; bitpos: [5]; default: 0; + * Configures uart1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uart1:1; + /** write_ree1_uart1 : R/W; bitpos: [6]; default: 0; + * Configures uart1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uart1:1; + /** write_ree2_uart1 : R/W; bitpos: [7]; default: 0; + * Configures uart1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uart1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_uart1_ctrl_reg_t; + +/** Type of uhci_ctrl register + * uhci read/write control register + */ +typedef union { + struct { + /** read_tee_uhci : R/W; bitpos: [0]; default: 1; + * Configures uhci registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_uhci:1; + /** read_ree0_uhci : R/W; bitpos: [1]; default: 0; + * Configures uhci registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_uhci:1; + /** read_ree1_uhci : R/W; bitpos: [2]; default: 0; + * Configures uhci registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_uhci:1; + /** read_ree2_uhci : R/W; bitpos: [3]; default: 0; + * Configures uhci registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_uhci:1; + /** write_tee_uhci : R/W; bitpos: [4]; default: 1; + * Configures uhci registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_uhci:1; + /** write_ree0_uhci : R/W; bitpos: [5]; default: 0; + * Configures uhci registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_uhci:1; + /** write_ree1_uhci : R/W; bitpos: [6]; default: 0; + * Configures uhci registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_uhci:1; + /** write_ree2_uhci : R/W; bitpos: [7]; default: 0; + * Configures uhci registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_uhci:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_uhci_ctrl_reg_t; + +/** Type of i2c0_ctrl register + * i2c0 read/write control register + */ +typedef union { + struct { + /** read_tee_i2c0 : R/W; bitpos: [0]; default: 1; + * Configures i2c0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2c0:1; + /** read_ree0_i2c0 : R/W; bitpos: [1]; default: 0; + * Configures i2c0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2c0:1; + /** read_ree1_i2c0 : R/W; bitpos: [2]; default: 0; + * Configures i2c0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2c0:1; + /** read_ree2_i2c0 : R/W; bitpos: [3]; default: 0; + * Configures i2c0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2c0:1; + /** write_tee_i2c0 : R/W; bitpos: [4]; default: 1; + * Configures i2c0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2c0:1; + /** write_ree0_i2c0 : R/W; bitpos: [5]; default: 0; + * Configures i2c0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2c0:1; + /** write_ree1_i2c0 : R/W; bitpos: [6]; default: 0; + * Configures i2c0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2c0:1; + /** write_ree2_i2c0 : R/W; bitpos: [7]; default: 0; + * Configures i2c0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2c0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_i2c0_ctrl_reg_t; + +/** Type of i2c1_ctrl register + * i2c1 read/write control register + */ +typedef union { + struct { + /** read_tee_i2c1 : R/W; bitpos: [0]; default: 1; + * Configures i2c1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2c1:1; + /** read_ree0_i2c1 : R/W; bitpos: [1]; default: 0; + * Configures i2c1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2c1:1; + /** read_ree1_i2c1 : R/W; bitpos: [2]; default: 0; + * Configures i2c1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2c1:1; + /** read_ree2_i2c1 : R/W; bitpos: [3]; default: 0; + * Configures i2c1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2c1:1; + /** write_tee_i2c1 : R/W; bitpos: [4]; default: 1; + * Configures i2c1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2c1:1; + /** write_ree0_i2c1 : R/W; bitpos: [5]; default: 0; + * Configures i2c1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2c1:1; + /** write_ree1_i2c1 : R/W; bitpos: [6]; default: 0; + * Configures i2c1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2c1:1; + /** write_ree2_i2c1 : R/W; bitpos: [7]; default: 0; + * Configures i2c1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2c1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_i2c1_ctrl_reg_t; + +/** Type of i2s_ctrl register + * i2s read/write control register + */ +typedef union { + struct { + /** read_tee_i2s : R/W; bitpos: [0]; default: 1; + * Configures i2s registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_i2s:1; + /** read_ree0_i2s : R/W; bitpos: [1]; default: 0; + * Configures i2s registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_i2s:1; + /** read_ree1_i2s : R/W; bitpos: [2]; default: 0; + * Configures i2s registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_i2s:1; + /** read_ree2_i2s : R/W; bitpos: [3]; default: 0; + * Configures i2s registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_i2s:1; + /** write_tee_i2s : R/W; bitpos: [4]; default: 1; + * Configures i2s registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_i2s:1; + /** write_ree0_i2s : R/W; bitpos: [5]; default: 0; + * Configures i2s registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_i2s:1; + /** write_ree1_i2s : R/W; bitpos: [6]; default: 0; + * Configures i2s registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_i2s:1; + /** write_ree2_i2s : R/W; bitpos: [7]; default: 0; + * Configures i2s registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_i2s:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_i2s_ctrl_reg_t; + +/** Type of parl_io_ctrl register + * parl_io read/write control register + */ +typedef union { + struct { + /** read_tee_parl_io : R/W; bitpos: [0]; default: 1; + * Configures parl_io registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_parl_io:1; + /** read_ree0_parl_io : R/W; bitpos: [1]; default: 0; + * Configures parl_io registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_parl_io:1; + /** read_ree1_parl_io : R/W; bitpos: [2]; default: 0; + * Configures parl_io registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_parl_io:1; + /** read_ree2_parl_io : R/W; bitpos: [3]; default: 0; + * Configures parl_io registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_parl_io:1; + /** write_tee_parl_io : R/W; bitpos: [4]; default: 1; + * Configures parl_io registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_parl_io:1; + /** write_ree0_parl_io : R/W; bitpos: [5]; default: 0; + * Configures parl_io registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_parl_io:1; + /** write_ree1_parl_io : R/W; bitpos: [6]; default: 0; + * Configures parl_io registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_parl_io:1; + /** write_ree2_parl_io : R/W; bitpos: [7]; default: 0; + * Configures parl_io registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_parl_io:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_parl_io_ctrl_reg_t; + +/** Type of pwm0_ctrl register + * pwm0 read/write control register + */ +typedef union { + struct { + /** read_tee_pwm0 : R/W; bitpos: [0]; default: 1; + * Configures pwm0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pwm0:1; + /** read_ree0_pwm0 : R/W; bitpos: [1]; default: 0; + * Configures pwm0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pwm0:1; + /** read_ree1_pwm0 : R/W; bitpos: [2]; default: 0; + * Configures pwm0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pwm0:1; + /** read_ree2_pwm0 : R/W; bitpos: [3]; default: 0; + * Configures pwm0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pwm0:1; + /** write_tee_pwm0 : R/W; bitpos: [4]; default: 1; + * Configures pwm0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pwm0:1; + /** write_ree0_pwm0 : R/W; bitpos: [5]; default: 0; + * Configures pwm0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pwm0:1; + /** write_ree1_pwm0 : R/W; bitpos: [6]; default: 0; + * Configures pwm0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pwm0:1; + /** write_ree2_pwm0 : R/W; bitpos: [7]; default: 0; + * Configures pwm0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pwm0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pwm0_ctrl_reg_t; + +/** Type of pwm1_ctrl register + * pwm1 read/write control register + */ +typedef union { + struct { + /** read_tee_pwm1 : R/W; bitpos: [0]; default: 1; + * Configures pwm1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pwm1:1; + /** read_ree0_pwm1 : R/W; bitpos: [1]; default: 0; + * Configures pwm1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pwm1:1; + /** read_ree1_pwm1 : R/W; bitpos: [2]; default: 0; + * Configures pwm1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pwm1:1; + /** read_ree2_pwm1 : R/W; bitpos: [3]; default: 0; + * Configures pwm1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pwm1:1; + /** write_tee_pwm1 : R/W; bitpos: [4]; default: 1; + * Configures pwm1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pwm1:1; + /** write_ree0_pwm1 : R/W; bitpos: [5]; default: 0; + * Configures pwm1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pwm1:1; + /** write_ree1_pwm1 : R/W; bitpos: [6]; default: 0; + * Configures pwm1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pwm1:1; + /** write_ree2_pwm1 : R/W; bitpos: [7]; default: 0; + * Configures pwm1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pwm1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pwm1_ctrl_reg_t; + +/** Type of ledc_ctrl register + * ledc read/write control register + */ +typedef union { + struct { + /** read_tee_ledc : R/W; bitpos: [0]; default: 1; + * Configures ledc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_ledc:1; + /** read_ree0_ledc : R/W; bitpos: [1]; default: 0; + * Configures ledc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_ledc:1; + /** read_ree1_ledc : R/W; bitpos: [2]; default: 0; + * Configures ledc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_ledc:1; + /** read_ree2_ledc : R/W; bitpos: [3]; default: 0; + * Configures ledc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_ledc:1; + /** write_tee_ledc : R/W; bitpos: [4]; default: 1; + * Configures ledc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_ledc:1; + /** write_ree0_ledc : R/W; bitpos: [5]; default: 0; + * Configures ledc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_ledc:1; + /** write_ree1_ledc : R/W; bitpos: [6]; default: 0; + * Configures ledc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_ledc:1; + /** write_ree2_ledc : R/W; bitpos: [7]; default: 0; + * Configures ledc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_ledc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_ledc_ctrl_reg_t; + +/** Type of can_ctrl register + * can read/write control register + */ +typedef union { + struct { + /** read_tee_can : R/W; bitpos: [0]; default: 1; + * Configures can registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_can:1; + /** read_ree0_can : R/W; bitpos: [1]; default: 0; + * Configures can registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_can:1; + /** read_ree1_can : R/W; bitpos: [2]; default: 0; + * Configures can registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_can:1; + /** read_ree2_can : R/W; bitpos: [3]; default: 0; + * Configures can registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_can:1; + /** write_tee_can : R/W; bitpos: [4]; default: 1; + * Configures can registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_can:1; + /** write_ree0_can : R/W; bitpos: [5]; default: 0; + * Configures can registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_can:1; + /** write_ree1_can : R/W; bitpos: [6]; default: 0; + * Configures can registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_can:1; + /** write_ree2_can : R/W; bitpos: [7]; default: 0; + * Configures can registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_can:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_can_ctrl_reg_t; + +/** Type of usb_serial_jtag_ctrl register + * usb_serial_jtag read/write control register + */ +typedef union { + struct { + /** read_tee_usb_serial_jtag : R/W; bitpos: [0]; default: 1; + * Configures usb_serial_jtag registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_usb_serial_jtag:1; + /** read_ree0_usb_serial_jtag : R/W; bitpos: [1]; default: 0; + * Configures usb_serial_jtag registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_usb_serial_jtag:1; + /** read_ree1_usb_serial_jtag : R/W; bitpos: [2]; default: 0; + * Configures usb_serial_jtag registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_usb_serial_jtag:1; + /** read_ree2_usb_serial_jtag : R/W; bitpos: [3]; default: 0; + * Configures usb_serial_jtag registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_usb_serial_jtag:1; + /** write_tee_usb_serial_jtag : R/W; bitpos: [4]; default: 1; + * Configures usb_serial_jtag registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_usb_serial_jtag:1; + /** write_ree0_usb_serial_jtag : R/W; bitpos: [5]; default: 0; + * Configures usb_serial_jtag registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_usb_serial_jtag:1; + /** write_ree1_usb_serial_jtag : R/W; bitpos: [6]; default: 0; + * Configures usb_serial_jtag registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_usb_serial_jtag:1; + /** write_ree2_usb_serial_jtag : R/W; bitpos: [7]; default: 0; + * Configures usb_serial_jtag registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_usb_serial_jtag:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_usb_serial_jtag_ctrl_reg_t; + +/** Type of rmt_ctrl register + * rmt read/write control register + */ +typedef union { + struct { + /** read_tee_rmt : R/W; bitpos: [0]; default: 1; + * Configures rmt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_rmt:1; + /** read_ree0_rmt : R/W; bitpos: [1]; default: 0; + * Configures rmt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_rmt:1; + /** read_ree1_rmt : R/W; bitpos: [2]; default: 0; + * Configures rmt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_rmt:1; + /** read_ree2_rmt : R/W; bitpos: [3]; default: 0; + * Configures rmt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_rmt:1; + /** write_tee_rmt : R/W; bitpos: [4]; default: 1; + * Configures rmt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_rmt:1; + /** write_ree0_rmt : R/W; bitpos: [5]; default: 0; + * Configures rmt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_rmt:1; + /** write_ree1_rmt : R/W; bitpos: [6]; default: 0; + * Configures rmt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_rmt:1; + /** write_ree2_rmt : R/W; bitpos: [7]; default: 0; + * Configures rmt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_rmt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_rmt_ctrl_reg_t; + +/** Type of gdma_ctrl register + * gdma read/write control register + */ +typedef union { + struct { + /** read_tee_gdma : R/W; bitpos: [0]; default: 1; + * Configures gdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_gdma:1; + /** read_ree0_gdma : R/W; bitpos: [1]; default: 0; + * Configures gdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_gdma:1; + /** read_ree1_gdma : R/W; bitpos: [2]; default: 0; + * Configures gdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_gdma:1; + /** read_ree2_gdma : R/W; bitpos: [3]; default: 0; + * Configures gdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_gdma:1; + /** write_tee_gdma : R/W; bitpos: [4]; default: 1; + * Configures gdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_gdma:1; + /** write_ree0_gdma : R/W; bitpos: [5]; default: 0; + * Configures gdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_gdma:1; + /** write_ree1_gdma : R/W; bitpos: [6]; default: 0; + * Configures gdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_gdma:1; + /** write_ree2_gdma : R/W; bitpos: [7]; default: 0; + * Configures gdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_gdma:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_gdma_ctrl_reg_t; + +/** Type of regdma_ctrl register + * regdma read/write control register + */ +typedef union { + struct { + /** read_tee_regdma : R/W; bitpos: [0]; default: 1; + * Configures regdma registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_regdma:1; + /** read_ree0_regdma : R/W; bitpos: [1]; default: 0; + * Configures regdma registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_regdma:1; + /** read_ree1_regdma : R/W; bitpos: [2]; default: 0; + * Configures regdma registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_regdma:1; + /** read_ree2_regdma : R/W; bitpos: [3]; default: 0; + * Configures regdma registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_regdma:1; + /** write_tee_regdma : R/W; bitpos: [4]; default: 1; + * Configures regdma registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_regdma:1; + /** write_ree0_regdma : R/W; bitpos: [5]; default: 0; + * Configures regdma registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_regdma:1; + /** write_ree1_regdma : R/W; bitpos: [6]; default: 0; + * Configures regdma registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_regdma:1; + /** write_ree2_regdma : R/W; bitpos: [7]; default: 0; + * Configures regdma registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_regdma:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_regdma_ctrl_reg_t; + +/** Type of etm_ctrl register + * etm read/write control register + */ +typedef union { + struct { + /** read_tee_etm : R/W; bitpos: [0]; default: 1; + * Configures etm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_etm:1; + /** read_ree0_etm : R/W; bitpos: [1]; default: 0; + * Configures etm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_etm:1; + /** read_ree1_etm : R/W; bitpos: [2]; default: 0; + * Configures etm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_etm:1; + /** read_ree2_etm : R/W; bitpos: [3]; default: 0; + * Configures etm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_etm:1; + /** write_tee_etm : R/W; bitpos: [4]; default: 1; + * Configures etm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_etm:1; + /** write_ree0_etm : R/W; bitpos: [5]; default: 0; + * Configures etm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_etm:1; + /** write_ree1_etm : R/W; bitpos: [6]; default: 0; + * Configures etm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_etm:1; + /** write_ree2_etm : R/W; bitpos: [7]; default: 0; + * Configures etm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_etm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_etm_ctrl_reg_t; + +/** Type of intmtx_core0_ctrl register + * intmtx_core0 read/write control register + */ +typedef union { + struct { + /** read_tee_intmtx_core0 : R/W; bitpos: [0]; default: 1; + * Configures intmtx_core0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_intmtx_core0:1; + /** read_ree0_intmtx_core0 : R/W; bitpos: [1]; default: 0; + * Configures intmtx_core0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_intmtx_core0:1; + /** read_ree1_intmtx_core0 : R/W; bitpos: [2]; default: 0; + * Configures intmtx_core0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_intmtx_core0:1; + /** read_ree2_intmtx_core0 : R/W; bitpos: [3]; default: 0; + * Configures intmtx_core0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_intmtx_core0:1; + /** write_tee_intmtx_core0 : R/W; bitpos: [4]; default: 1; + * Configures intmtx_core0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_intmtx_core0:1; + /** write_ree0_intmtx_core0 : R/W; bitpos: [5]; default: 0; + * Configures intmtx_core0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_intmtx_core0:1; + /** write_ree1_intmtx_core0 : R/W; bitpos: [6]; default: 0; + * Configures intmtx_core0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_intmtx_core0:1; + /** write_ree2_intmtx_core0 : R/W; bitpos: [7]; default: 0; + * Configures intmtx_core0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_intmtx_core0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_intmtx_core0_ctrl_reg_t; + +/** Type of intmtx_core1_ctrl register + * intmtx_core1 read/write control register + */ +typedef union { + struct { + /** read_tee_intmtx_core1 : R/W; bitpos: [0]; default: 1; + * Configures intmtx_core1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_intmtx_core1:1; + /** read_ree0_intmtx_core1 : R/W; bitpos: [1]; default: 0; + * Configures intmtx_core1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_intmtx_core1:1; + /** read_ree1_intmtx_core1 : R/W; bitpos: [2]; default: 0; + * Configures intmtx_core1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_intmtx_core1:1; + /** read_ree2_intmtx_core1 : R/W; bitpos: [3]; default: 0; + * Configures intmtx_core1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_intmtx_core1:1; + /** write_tee_intmtx_core1 : R/W; bitpos: [4]; default: 1; + * Configures intmtx_core1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_intmtx_core1:1; + /** write_ree0_intmtx_core1 : R/W; bitpos: [5]; default: 0; + * Configures intmtx_core1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_intmtx_core1:1; + /** write_ree1_intmtx_core1 : R/W; bitpos: [6]; default: 0; + * Configures intmtx_core1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_intmtx_core1:1; + /** write_ree2_intmtx_core1 : R/W; bitpos: [7]; default: 0; + * Configures intmtx_core1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_intmtx_core1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_intmtx_core1_ctrl_reg_t; + +/** Type of apb_adc_ctrl register + * apb_adc read/write control register + */ +typedef union { + struct { + /** read_tee_apb_adc : R/W; bitpos: [0]; default: 1; + * Configures apb_adc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_apb_adc:1; + /** read_ree0_apb_adc : R/W; bitpos: [1]; default: 0; + * Configures apb_adc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_apb_adc:1; + /** read_ree1_apb_adc : R/W; bitpos: [2]; default: 0; + * Configures apb_adc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_apb_adc:1; + /** read_ree2_apb_adc : R/W; bitpos: [3]; default: 0; + * Configures apb_adc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_apb_adc:1; + /** write_tee_apb_adc : R/W; bitpos: [4]; default: 1; + * Configures apb_adc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_apb_adc:1; + /** write_ree0_apb_adc : R/W; bitpos: [5]; default: 0; + * Configures apb_adc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_apb_adc:1; + /** write_ree1_apb_adc : R/W; bitpos: [6]; default: 0; + * Configures apb_adc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_apb_adc:1; + /** write_ree2_apb_adc : R/W; bitpos: [7]; default: 0; + * Configures apb_adc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_apb_adc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_apb_adc_ctrl_reg_t; + +/** Type of timergroup0_ctrl register + * timergroup0 read/write control register + */ +typedef union { + struct { + /** read_tee_timergroup0 : R/W; bitpos: [0]; default: 1; + * Configures timergroup0 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_timergroup0:1; + /** read_ree0_timergroup0 : R/W; bitpos: [1]; default: 0; + * Configures timergroup0 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_timergroup0:1; + /** read_ree1_timergroup0 : R/W; bitpos: [2]; default: 0; + * Configures timergroup0 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_timergroup0:1; + /** read_ree2_timergroup0 : R/W; bitpos: [3]; default: 0; + * Configures timergroup0 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_timergroup0:1; + /** write_tee_timergroup0 : R/W; bitpos: [4]; default: 1; + * Configures timergroup0 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_timergroup0:1; + /** write_ree0_timergroup0 : R/W; bitpos: [5]; default: 0; + * Configures timergroup0 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_timergroup0:1; + /** write_ree1_timergroup0 : R/W; bitpos: [6]; default: 0; + * Configures timergroup0 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_timergroup0:1; + /** write_ree2_timergroup0 : R/W; bitpos: [7]; default: 0; + * Configures timergroup0 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_timergroup0:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_timergroup0_ctrl_reg_t; + +/** Type of timergroup1_ctrl register + * timergroup1 read/write control register + */ +typedef union { + struct { + /** read_tee_timergroup1 : R/W; bitpos: [0]; default: 1; + * Configures timergroup1 registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_timergroup1:1; + /** read_ree0_timergroup1 : R/W; bitpos: [1]; default: 0; + * Configures timergroup1 registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_timergroup1:1; + /** read_ree1_timergroup1 : R/W; bitpos: [2]; default: 0; + * Configures timergroup1 registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_timergroup1:1; + /** read_ree2_timergroup1 : R/W; bitpos: [3]; default: 0; + * Configures timergroup1 registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_timergroup1:1; + /** write_tee_timergroup1 : R/W; bitpos: [4]; default: 1; + * Configures timergroup1 registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_timergroup1:1; + /** write_ree0_timergroup1 : R/W; bitpos: [5]; default: 0; + * Configures timergroup1 registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_timergroup1:1; + /** write_ree1_timergroup1 : R/W; bitpos: [6]; default: 0; + * Configures timergroup1 registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_timergroup1:1; + /** write_ree2_timergroup1 : R/W; bitpos: [7]; default: 0; + * Configures timergroup1 registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_timergroup1:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_timergroup1_ctrl_reg_t; + +/** Type of systimer_ctrl register + * systimer read/write control register + */ +typedef union { + struct { + /** read_tee_systimer : R/W; bitpos: [0]; default: 1; + * Configures systimer registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_systimer:1; + /** read_ree0_systimer : R/W; bitpos: [1]; default: 0; + * Configures systimer registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_systimer:1; + /** read_ree1_systimer : R/W; bitpos: [2]; default: 0; + * Configures systimer registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_systimer:1; + /** read_ree2_systimer : R/W; bitpos: [3]; default: 0; + * Configures systimer registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_systimer:1; + /** write_tee_systimer : R/W; bitpos: [4]; default: 1; + * Configures systimer registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_systimer:1; + /** write_ree0_systimer : R/W; bitpos: [5]; default: 0; + * Configures systimer registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_systimer:1; + /** write_ree1_systimer : R/W; bitpos: [6]; default: 0; + * Configures systimer registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_systimer:1; + /** write_ree2_systimer : R/W; bitpos: [7]; default: 0; + * Configures systimer registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_systimer:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_systimer_ctrl_reg_t; + +/** Type of misc_ctrl register + * misc read/write control register + */ +typedef union { + struct { + /** read_tee_misc : R/W; bitpos: [0]; default: 1; + * Configures misc registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_misc:1; + /** read_ree0_misc : R/W; bitpos: [1]; default: 0; + * Configures misc registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_misc:1; + /** read_ree1_misc : R/W; bitpos: [2]; default: 0; + * Configures misc registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_misc:1; + /** read_ree2_misc : R/W; bitpos: [3]; default: 0; + * Configures misc registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_misc:1; + /** write_tee_misc : R/W; bitpos: [4]; default: 1; + * Configures misc registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_misc:1; + /** write_ree0_misc : R/W; bitpos: [5]; default: 0; + * Configures misc registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_misc:1; + /** write_ree1_misc : R/W; bitpos: [6]; default: 0; + * Configures misc registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_misc:1; + /** write_ree2_misc : R/W; bitpos: [7]; default: 0; + * Configures misc registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_misc:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_misc_ctrl_reg_t; + +/** Type of src_ctrl register + * src read/write control register + */ +typedef union { + struct { + /** read_tee_src : R/W; bitpos: [0]; default: 1; + * Configures src registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_src:1; + /** read_ree0_src : R/W; bitpos: [1]; default: 0; + * Configures src registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_src:1; + /** read_ree1_src : R/W; bitpos: [2]; default: 0; + * Configures src registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_src:1; + /** read_ree2_src : R/W; bitpos: [3]; default: 0; + * Configures src registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_src:1; + /** write_tee_src : R/W; bitpos: [4]; default: 1; + * Configures src registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_src:1; + /** write_ree0_src : R/W; bitpos: [5]; default: 0; + * Configures src registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_src:1; + /** write_ree1_src : R/W; bitpos: [6]; default: 0; + * Configures src registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_src:1; + /** write_ree2_src : R/W; bitpos: [7]; default: 0; + * Configures src registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_src:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_src_ctrl_reg_t; + +/** Type of usb_otg_fs_core_ctrl register + * usb_otg_fs_core read/write control register + */ +typedef union { + struct { + /** read_tee_usb_otg_fs_core : R/W; bitpos: [0]; default: 1; + * Configures usb_otg_fs_core registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_usb_otg_fs_core:1; + /** read_ree0_usb_otg_fs_core : R/W; bitpos: [1]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_usb_otg_fs_core:1; + /** read_ree1_usb_otg_fs_core : R/W; bitpos: [2]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_usb_otg_fs_core:1; + /** read_ree2_usb_otg_fs_core : R/W; bitpos: [3]; default: 0; + * Configures usb_otg_fs_core registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_usb_otg_fs_core:1; + /** write_tee_usb_otg_fs_core : R/W; bitpos: [4]; default: 1; + * Configures usb_otg_fs_core registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_usb_otg_fs_core:1; + /** write_ree0_usb_otg_fs_core : R/W; bitpos: [5]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_usb_otg_fs_core:1; + /** write_ree1_usb_otg_fs_core : R/W; bitpos: [6]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_usb_otg_fs_core:1; + /** write_ree2_usb_otg_fs_core : R/W; bitpos: [7]; default: 0; + * Configures usb_otg_fs_core registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_usb_otg_fs_core:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_usb_otg_fs_core_ctrl_reg_t; + +/** Type of usb_otg_fs_phy_ctrl register + * usb_otg_fs_phy read/write control register + */ +typedef union { + struct { + /** read_tee_usb_otg_fs_phy : R/W; bitpos: [0]; default: 1; + * Configures usb_otg_fs_phy registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_usb_otg_fs_phy:1; + /** read_ree0_usb_otg_fs_phy : R/W; bitpos: [1]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_usb_otg_fs_phy:1; + /** read_ree1_usb_otg_fs_phy : R/W; bitpos: [2]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_usb_otg_fs_phy:1; + /** read_ree2_usb_otg_fs_phy : R/W; bitpos: [3]; default: 0; + * Configures usb_otg_fs_phy registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_usb_otg_fs_phy:1; + /** write_tee_usb_otg_fs_phy : R/W; bitpos: [4]; default: 1; + * Configures usb_otg_fs_phy registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_usb_otg_fs_phy:1; + /** write_ree0_usb_otg_fs_phy : R/W; bitpos: [5]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_usb_otg_fs_phy:1; + /** write_ree1_usb_otg_fs_phy : R/W; bitpos: [6]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_usb_otg_fs_phy:1; + /** write_ree2_usb_otg_fs_phy : R/W; bitpos: [7]; default: 0; + * Configures usb_otg_fs_phy registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_usb_otg_fs_phy:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_usb_otg_fs_phy_ctrl_reg_t; + +/** Type of pvt_monitor_ctrl register + * pvt_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_pvt_monitor : R/W; bitpos: [0]; default: 1; + * Configures pvt_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pvt_monitor:1; + /** read_ree0_pvt_monitor : R/W; bitpos: [1]; default: 0; + * Configures pvt_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pvt_monitor:1; + /** read_ree1_pvt_monitor : R/W; bitpos: [2]; default: 0; + * Configures pvt_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pvt_monitor:1; + /** read_ree2_pvt_monitor : R/W; bitpos: [3]; default: 0; + * Configures pvt_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pvt_monitor:1; + /** write_tee_pvt_monitor : R/W; bitpos: [4]; default: 1; + * Configures pvt_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pvt_monitor:1; + /** write_ree0_pvt_monitor : R/W; bitpos: [5]; default: 0; + * Configures pvt_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pvt_monitor:1; + /** write_ree1_pvt_monitor : R/W; bitpos: [6]; default: 0; + * Configures pvt_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pvt_monitor:1; + /** write_ree2_pvt_monitor : R/W; bitpos: [7]; default: 0; + * Configures pvt_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pvt_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pvt_monitor_ctrl_reg_t; + +/** Type of pcnt_ctrl register + * pcnt read/write control register + */ +typedef union { + struct { + /** read_tee_pcnt : R/W; bitpos: [0]; default: 1; + * Configures pcnt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pcnt:1; + /** read_ree0_pcnt : R/W; bitpos: [1]; default: 0; + * Configures pcnt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pcnt:1; + /** read_ree1_pcnt : R/W; bitpos: [2]; default: 0; + * Configures pcnt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pcnt:1; + /** read_ree2_pcnt : R/W; bitpos: [3]; default: 0; + * Configures pcnt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pcnt:1; + /** write_tee_pcnt : R/W; bitpos: [4]; default: 1; + * Configures pcnt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pcnt:1; + /** write_ree0_pcnt : R/W; bitpos: [5]; default: 0; + * Configures pcnt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pcnt:1; + /** write_ree1_pcnt : R/W; bitpos: [6]; default: 0; + * Configures pcnt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pcnt:1; + /** write_ree2_pcnt : R/W; bitpos: [7]; default: 0; + * Configures pcnt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pcnt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pcnt_ctrl_reg_t; + +/** Type of iomux_ctrl register + * iomux read/write control register + */ +typedef union { + struct { + /** read_tee_iomux : R/W; bitpos: [0]; default: 1; + * Configures iomux registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_iomux:1; + /** read_ree0_iomux : R/W; bitpos: [1]; default: 0; + * Configures iomux registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_iomux:1; + /** read_ree1_iomux : R/W; bitpos: [2]; default: 0; + * Configures iomux registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_iomux:1; + /** read_ree2_iomux : R/W; bitpos: [3]; default: 0; + * Configures iomux registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_iomux:1; + /** write_tee_iomux : R/W; bitpos: [4]; default: 1; + * Configures iomux registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_iomux:1; + /** write_ree0_iomux : R/W; bitpos: [5]; default: 0; + * Configures iomux registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_iomux:1; + /** write_ree1_iomux : R/W; bitpos: [6]; default: 0; + * Configures iomux registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_iomux:1; + /** write_ree2_iomux : R/W; bitpos: [7]; default: 0; + * Configures iomux registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_iomux:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_iomux_ctrl_reg_t; + +/** Type of psram_mem_monitor_ctrl register + * psram_mem_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_psram_mem_monitor : R/W; bitpos: [0]; default: 1; + * Configures psram_mem_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_psram_mem_monitor:1; + /** read_ree0_psram_mem_monitor : R/W; bitpos: [1]; default: 0; + * Configures psram_mem_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_psram_mem_monitor:1; + /** read_ree1_psram_mem_monitor : R/W; bitpos: [2]; default: 0; + * Configures psram_mem_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_psram_mem_monitor:1; + /** read_ree2_psram_mem_monitor : R/W; bitpos: [3]; default: 0; + * Configures psram_mem_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_psram_mem_monitor:1; + /** write_tee_psram_mem_monitor : R/W; bitpos: [4]; default: 1; + * Configures psram_mem_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_psram_mem_monitor:1; + /** write_ree0_psram_mem_monitor : R/W; bitpos: [5]; default: 0; + * Configures psram_mem_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_psram_mem_monitor:1; + /** write_ree1_psram_mem_monitor : R/W; bitpos: [6]; default: 0; + * Configures psram_mem_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_psram_mem_monitor:1; + /** write_ree2_psram_mem_monitor : R/W; bitpos: [7]; default: 0; + * Configures psram_mem_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_psram_mem_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_psram_mem_monitor_ctrl_reg_t; + +/** Type of mem_acs_monitor_ctrl register + * mem_acs_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_mem_acs_monitor : R/W; bitpos: [0]; default: 1; + * Configures mem_acs_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_mem_acs_monitor:1; + /** read_ree0_mem_acs_monitor : R/W; bitpos: [1]; default: 0; + * Configures mem_acs_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_mem_acs_monitor:1; + /** read_ree1_mem_acs_monitor : R/W; bitpos: [2]; default: 0; + * Configures mem_acs_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_mem_acs_monitor:1; + /** read_ree2_mem_acs_monitor : R/W; bitpos: [3]; default: 0; + * Configures mem_acs_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_mem_acs_monitor:1; + /** write_tee_mem_acs_monitor : R/W; bitpos: [4]; default: 1; + * Configures mem_acs_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_mem_acs_monitor:1; + /** write_ree0_mem_acs_monitor : R/W; bitpos: [5]; default: 0; + * Configures mem_acs_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_mem_acs_monitor:1; + /** write_ree1_mem_acs_monitor : R/W; bitpos: [6]; default: 0; + * Configures mem_acs_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_mem_acs_monitor:1; + /** write_ree2_mem_acs_monitor : R/W; bitpos: [7]; default: 0; + * Configures mem_acs_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_mem_acs_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_mem_acs_monitor_ctrl_reg_t; + +/** Type of hp_system_reg_ctrl register + * hp_system_reg read/write control register + */ +typedef union { + struct { + /** read_tee_hp_system_reg : R/W; bitpos: [0]; default: 1; + * Configures hp_system_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_hp_system_reg:1; + /** read_ree0_hp_system_reg : R/W; bitpos: [1]; default: 0; + * Configures hp_system_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_hp_system_reg:1; + /** read_ree1_hp_system_reg : R/W; bitpos: [2]; default: 0; + * Configures hp_system_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_hp_system_reg:1; + /** read_ree2_hp_system_reg : R/W; bitpos: [3]; default: 0; + * Configures hp_system_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_hp_system_reg:1; + /** write_tee_hp_system_reg : R/W; bitpos: [4]; default: 1; + * Configures hp_system_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_hp_system_reg:1; + /** write_ree0_hp_system_reg : R/W; bitpos: [5]; default: 0; + * Configures hp_system_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_hp_system_reg:1; + /** write_ree1_hp_system_reg : R/W; bitpos: [6]; default: 0; + * Configures hp_system_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_hp_system_reg:1; + /** write_ree2_hp_system_reg : R/W; bitpos: [7]; default: 0; + * Configures hp_system_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_hp_system_reg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_hp_system_reg_ctrl_reg_t; + +/** Type of pcr_reg_ctrl register + * pcr_reg read/write control register + */ +typedef union { + struct { + /** read_tee_pcr_reg : R/W; bitpos: [0]; default: 1; + * Configures pcr_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_pcr_reg:1; + /** read_ree0_pcr_reg : R/W; bitpos: [1]; default: 0; + * Configures pcr_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_pcr_reg:1; + /** read_ree1_pcr_reg : R/W; bitpos: [2]; default: 0; + * Configures pcr_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_pcr_reg:1; + /** read_ree2_pcr_reg : R/W; bitpos: [3]; default: 0; + * Configures pcr_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_pcr_reg:1; + /** write_tee_pcr_reg : R/W; bitpos: [4]; default: 1; + * Configures pcr_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_pcr_reg:1; + /** write_ree0_pcr_reg : R/W; bitpos: [5]; default: 0; + * Configures pcr_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_pcr_reg:1; + /** write_ree1_pcr_reg : R/W; bitpos: [6]; default: 0; + * Configures pcr_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_pcr_reg:1; + /** write_ree2_pcr_reg : R/W; bitpos: [7]; default: 0; + * Configures pcr_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_pcr_reg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_pcr_reg_ctrl_reg_t; + +/** Type of mspi_ctrl register + * mspi read/write control register + */ +typedef union { + struct { + /** read_tee_mspi : R/W; bitpos: [0]; default: 1; + * Configures mspi registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_mspi:1; + /** read_ree0_mspi : R/W; bitpos: [1]; default: 0; + * Configures mspi registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_mspi:1; + /** read_ree1_mspi : R/W; bitpos: [2]; default: 0; + * Configures mspi registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_mspi:1; + /** read_ree2_mspi : R/W; bitpos: [3]; default: 0; + * Configures mspi registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_mspi:1; + /** write_tee_mspi : R/W; bitpos: [4]; default: 1; + * Configures mspi registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_mspi:1; + /** write_ree0_mspi : R/W; bitpos: [5]; default: 0; + * Configures mspi registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_mspi:1; + /** write_ree1_mspi : R/W; bitpos: [6]; default: 0; + * Configures mspi registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_mspi:1; + /** write_ree2_mspi : R/W; bitpos: [7]; default: 0; + * Configures mspi registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_mspi:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_mspi_ctrl_reg_t; + +/** Type of hp_apm_ctrl register + * hp_apm read/write control register + */ +typedef union { + struct { + /** read_tee_hp_apm : R/W; bitpos: [0]; default: 1; + * Configures hp_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_hp_apm:1; + /** read_ree0_hp_apm : HRO; bitpos: [1]; default: 0; + * Configures hp_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_hp_apm:1; + /** read_ree1_hp_apm : HRO; bitpos: [2]; default: 0; + * Configures hp_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_hp_apm:1; + /** read_ree2_hp_apm : HRO; bitpos: [3]; default: 0; + * Configures hp_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_hp_apm:1; + /** write_tee_hp_apm : R/W; bitpos: [4]; default: 1; + * Configures hp_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_hp_apm:1; + /** write_ree0_hp_apm : HRO; bitpos: [5]; default: 0; + * Configures hp_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_hp_apm:1; + /** write_ree1_hp_apm : HRO; bitpos: [6]; default: 0; + * Configures hp_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_hp_apm:1; + /** write_ree2_hp_apm : HRO; bitpos: [7]; default: 0; + * Configures hp_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_hp_apm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_hp_apm_ctrl_reg_t; + +/** Type of hp_mem_apm_ctrl register + * hp_mem_apm read/write control register + */ +typedef union { + struct { + /** read_tee_hp_mem_apm : R/W; bitpos: [0]; default: 1; + * Configures hp_mem_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_hp_mem_apm:1; + /** read_ree0_hp_mem_apm : HRO; bitpos: [1]; default: 0; + * Configures hp_mem_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_hp_mem_apm:1; + /** read_ree1_hp_mem_apm : HRO; bitpos: [2]; default: 0; + * Configures hp_mem_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_hp_mem_apm:1; + /** read_ree2_hp_mem_apm : HRO; bitpos: [3]; default: 0; + * Configures hp_mem_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_hp_mem_apm:1; + /** write_tee_hp_mem_apm : R/W; bitpos: [4]; default: 1; + * Configures hp_mem_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_hp_mem_apm:1; + /** write_ree0_hp_mem_apm : HRO; bitpos: [5]; default: 0; + * Configures hp_mem_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_hp_mem_apm:1; + /** write_ree1_hp_mem_apm : HRO; bitpos: [6]; default: 0; + * Configures hp_mem_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_hp_mem_apm:1; + /** write_ree2_hp_mem_apm : HRO; bitpos: [7]; default: 0; + * Configures hp_mem_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_hp_mem_apm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_hp_mem_apm_ctrl_reg_t; + +/** Type of cpu_apm_ctrl register + * cpu_apm read/write control register + */ +typedef union { + struct { + /** read_tee_cpu_apm : R/W; bitpos: [0]; default: 1; + * Configures cpu_apm registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_cpu_apm:1; + /** read_ree0_cpu_apm : HRO; bitpos: [1]; default: 0; + * Configures cpu_apm registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_cpu_apm:1; + /** read_ree1_cpu_apm : HRO; bitpos: [2]; default: 0; + * Configures cpu_apm registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_cpu_apm:1; + /** read_ree2_cpu_apm : HRO; bitpos: [3]; default: 0; + * Configures cpu_apm registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_cpu_apm:1; + /** write_tee_cpu_apm : R/W; bitpos: [4]; default: 1; + * Configures cpu_apm registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_cpu_apm:1; + /** write_ree0_cpu_apm : HRO; bitpos: [5]; default: 0; + * Configures cpu_apm registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_cpu_apm:1; + /** write_ree1_cpu_apm : HRO; bitpos: [6]; default: 0; + * Configures cpu_apm registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_cpu_apm:1; + /** write_ree2_cpu_apm : HRO; bitpos: [7]; default: 0; + * Configures cpu_apm registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_cpu_apm:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_cpu_apm_ctrl_reg_t; + +/** Type of tee_ctrl register + * tee read/write control register + */ +typedef union { + struct { + /** read_tee_tee : R/W; bitpos: [0]; default: 1; + * Configures tee registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_tee:1; + /** read_ree0_tee : HRO; bitpos: [1]; default: 0; + * Configures tee registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_tee:1; + /** read_ree1_tee : HRO; bitpos: [2]; default: 0; + * Configures tee registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_tee:1; + /** read_ree2_tee : HRO; bitpos: [3]; default: 0; + * Configures tee registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_tee:1; + /** write_tee_tee : R/W; bitpos: [4]; default: 1; + * Configures tee registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_tee:1; + /** write_ree0_tee : HRO; bitpos: [5]; default: 0; + * Configures tee registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_tee:1; + /** write_ree1_tee : HRO; bitpos: [6]; default: 0; + * Configures tee registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_tee:1; + /** write_ree2_tee : HRO; bitpos: [7]; default: 0; + * Configures tee registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_tee:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_tee_ctrl_reg_t; + +/** Type of km_ctrl register + * crypt read/write control register + */ +typedef union { + struct { + /** read_tee_km : R/W; bitpos: [0]; default: 1; + * Configures km registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_km:1; + /** read_ree0_km : R/W; bitpos: [1]; default: 0; + * Configures km registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_km:1; + /** read_ree1_km : R/W; bitpos: [2]; default: 0; + * Configures km registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_km:1; + /** read_ree2_km : R/W; bitpos: [3]; default: 0; + * Configures km registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_km:1; + /** write_tee_km : R/W; bitpos: [4]; default: 1; + * Configures km registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_km:1; + /** write_ree0_km : R/W; bitpos: [5]; default: 0; + * Configures km registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_km:1; + /** write_ree1_km : R/W; bitpos: [6]; default: 0; + * Configures km registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_km:1; + /** write_ree2_km : R/W; bitpos: [7]; default: 0; + * Configures km registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_km:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_km_ctrl_reg_t; + +/** Type of crypt_ctrl register + * crypt read/write control register + */ +typedef union { + struct { + /** read_tee_crypt : R/W; bitpos: [0]; default: 1; + * Configures crypt registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_crypt:1; + /** read_ree0_crypt : R/W; bitpos: [1]; default: 0; + * Configures crypt registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_crypt:1; + /** read_ree1_crypt : R/W; bitpos: [2]; default: 0; + * Configures crypt registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_crypt:1; + /** read_ree2_crypt : R/W; bitpos: [3]; default: 0; + * Configures crypt registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_crypt:1; + /** write_tee_crypt : R/W; bitpos: [4]; default: 1; + * Configures crypt registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_crypt:1; + /** write_ree0_crypt : R/W; bitpos: [5]; default: 0; + * Configures crypt registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_crypt:1; + /** write_ree1_crypt : R/W; bitpos: [6]; default: 0; + * Configures crypt registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_crypt:1; + /** write_ree2_crypt : R/W; bitpos: [7]; default: 0; + * Configures crypt registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_crypt:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_crypt_ctrl_reg_t; + +/** Type of core0_trace_ctrl register + * core0_trace read/write control register + */ +typedef union { + struct { + /** read_tee_core0_trace : R/W; bitpos: [0]; default: 1; + * Configures core0_trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_core0_trace:1; + /** read_ree0_core0_trace : R/W; bitpos: [1]; default: 0; + * Configures core0_trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_core0_trace:1; + /** read_ree1_core0_trace : R/W; bitpos: [2]; default: 0; + * Configures core0_trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_core0_trace:1; + /** read_ree2_core0_trace : R/W; bitpos: [3]; default: 0; + * Configures core0_trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_core0_trace:1; + /** write_tee_core0_trace : R/W; bitpos: [4]; default: 1; + * Configures core0_trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_core0_trace:1; + /** write_ree0_core0_trace : R/W; bitpos: [5]; default: 0; + * Configures core0_trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_core0_trace:1; + /** write_ree1_core0_trace : R/W; bitpos: [6]; default: 0; + * Configures core0_trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_core0_trace:1; + /** write_ree2_core0_trace : R/W; bitpos: [7]; default: 0; + * Configures core0_trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_core0_trace:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_core0_trace_ctrl_reg_t; + +/** Type of core1_trace_ctrl register + * core1_trace read/write control register + */ +typedef union { + struct { + /** read_tee_core1_trace : R/W; bitpos: [0]; default: 1; + * Configures core1_trace registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_core1_trace:1; + /** read_ree0_core1_trace : R/W; bitpos: [1]; default: 0; + * Configures core1_trace registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_core1_trace:1; + /** read_ree1_core1_trace : R/W; bitpos: [2]; default: 0; + * Configures core1_trace registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_core1_trace:1; + /** read_ree2_core1_trace : R/W; bitpos: [3]; default: 0; + * Configures core1_trace registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_core1_trace:1; + /** write_tee_core1_trace : R/W; bitpos: [4]; default: 1; + * Configures core1_trace registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_core1_trace:1; + /** write_ree0_core1_trace : R/W; bitpos: [5]; default: 0; + * Configures core1_trace registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_core1_trace:1; + /** write_ree1_core1_trace : R/W; bitpos: [6]; default: 0; + * Configures core1_trace registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_core1_trace:1; + /** write_ree2_core1_trace : R/W; bitpos: [7]; default: 0; + * Configures core1_trace registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_core1_trace:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_core1_trace_ctrl_reg_t; + +/** Type of cpu_bus_monitor_ctrl register + * cpu_bus_monitor read/write control register + */ +typedef union { + struct { + /** read_tee_cpu_bus_monitor : R/W; bitpos: [0]; default: 1; + * Configures cpu_bus_monitor registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_cpu_bus_monitor:1; + /** read_ree0_cpu_bus_monitor : R/W; bitpos: [1]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_cpu_bus_monitor:1; + /** read_ree1_cpu_bus_monitor : R/W; bitpos: [2]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_cpu_bus_monitor:1; + /** read_ree2_cpu_bus_monitor : R/W; bitpos: [3]; default: 0; + * Configures cpu_bus_monitor registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_cpu_bus_monitor:1; + /** write_tee_cpu_bus_monitor : R/W; bitpos: [4]; default: 1; + * Configures cpu_bus_monitor registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_cpu_bus_monitor:1; + /** write_ree0_cpu_bus_monitor : R/W; bitpos: [5]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_cpu_bus_monitor:1; + /** write_ree1_cpu_bus_monitor : R/W; bitpos: [6]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_cpu_bus_monitor:1; + /** write_ree2_cpu_bus_monitor : R/W; bitpos: [7]; default: 0; + * Configures cpu_bus_monitor registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_cpu_bus_monitor:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_cpu_bus_monitor_ctrl_reg_t; + +/** Type of intpri_reg_ctrl register + * intpri_reg read/write control register + */ +typedef union { + struct { + /** read_tee_intpri_reg : R/W; bitpos: [0]; default: 1; + * Configures intpri_reg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_intpri_reg:1; + /** read_ree0_intpri_reg : R/W; bitpos: [1]; default: 0; + * Configures intpri_reg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_intpri_reg:1; + /** read_ree1_intpri_reg : R/W; bitpos: [2]; default: 0; + * Configures intpri_reg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_intpri_reg:1; + /** read_ree2_intpri_reg : R/W; bitpos: [3]; default: 0; + * Configures intpri_reg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_intpri_reg:1; + /** write_tee_intpri_reg : R/W; bitpos: [4]; default: 1; + * Configures intpri_reg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_intpri_reg:1; + /** write_ree0_intpri_reg : R/W; bitpos: [5]; default: 0; + * Configures intpri_reg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_intpri_reg:1; + /** write_ree1_intpri_reg : R/W; bitpos: [6]; default: 0; + * Configures intpri_reg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_intpri_reg:1; + /** write_ree2_intpri_reg : R/W; bitpos: [7]; default: 0; + * Configures intpri_reg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_intpri_reg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_intpri_reg_ctrl_reg_t; + +/** Type of cache_cfg_ctrl register + * cache_cfg read/write control register + */ +typedef union { + struct { + /** read_tee_cache_cfg : R/W; bitpos: [0]; default: 1; + * Configures cache_cfg registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_cache_cfg:1; + /** read_ree0_cache_cfg : R/W; bitpos: [1]; default: 0; + * Configures cache_cfg registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_cache_cfg:1; + /** read_ree1_cache_cfg : R/W; bitpos: [2]; default: 0; + * Configures cache_cfg registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_cache_cfg:1; + /** read_ree2_cache_cfg : R/W; bitpos: [3]; default: 0; + * Configures cache_cfg registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_cache_cfg:1; + /** write_tee_cache_cfg : R/W; bitpos: [4]; default: 1; + * Configures cache_cfg registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_cache_cfg:1; + /** write_ree0_cache_cfg : R/W; bitpos: [5]; default: 0; + * Configures cache_cfg registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_cache_cfg:1; + /** write_ree1_cache_cfg : R/W; bitpos: [6]; default: 0; + * Configures cache_cfg registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_cache_cfg:1; + /** write_ree2_cache_cfg : R/W; bitpos: [7]; default: 0; + * Configures cache_cfg registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_cache_cfg:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_cache_cfg_ctrl_reg_t; + +/** Type of modem_ctrl register + * modem read/write control register + */ +typedef union { + struct { + /** read_tee_modem : R/W; bitpos: [0]; default: 1; + * Configures modem registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_modem:1; + /** read_ree0_modem : R/W; bitpos: [1]; default: 0; + * Configures modem registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_modem:1; + /** read_ree1_modem : R/W; bitpos: [2]; default: 0; + * Configures modem registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_modem:1; + /** read_ree2_modem : R/W; bitpos: [3]; default: 0; + * Configures modem registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_modem:1; + /** write_tee_modem : R/W; bitpos: [4]; default: 1; + * Configures modem registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_modem:1; + /** write_ree0_modem : R/W; bitpos: [5]; default: 0; + * Configures modem registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_modem:1; + /** write_ree1_modem : R/W; bitpos: [6]; default: 0; + * Configures modem registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_modem:1; + /** write_ree2_modem : R/W; bitpos: [7]; default: 0; + * Configures modem registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_modem:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_modem_ctrl_reg_t; + +/** Type of zero_det_ctrl register + * zero_det read/write control register + */ +typedef union { + struct { + /** read_tee_zero_det : R/W; bitpos: [0]; default: 1; + * Configures zero_det registers read permission in tee mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_tee_zero_det:1; + /** read_ree0_zero_det : R/W; bitpos: [1]; default: 0; + * Configures zero_det registers read permission in ree0 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree0_zero_det:1; + /** read_ree1_zero_det : R/W; bitpos: [2]; default: 0; + * Configures zero_det registers read permission in ree1 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree1_zero_det:1; + /** read_ree2_zero_det : R/W; bitpos: [3]; default: 0; + * Configures zero_det registers read permission in ree2 mode. + * 0: can not be read + * 1: can be read + */ + uint32_t read_ree2_zero_det:1; + /** write_tee_zero_det : R/W; bitpos: [4]; default: 1; + * Configures zero_det registers write permission in tee mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_tee_zero_det:1; + /** write_ree0_zero_det : R/W; bitpos: [5]; default: 0; + * Configures zero_det registers write permission in ree0 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree0_zero_det:1; + /** write_ree1_zero_det : R/W; bitpos: [6]; default: 0; + * Configures zero_det registers write permission in ree1 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree1_zero_det:1; + /** write_ree2_zero_det : R/W; bitpos: [7]; default: 0; + * Configures zero_det registers write permission in ree2 mode. + * 0: can not be write + * 1: can be write + */ + uint32_t write_ree2_zero_det:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} tee_zero_det_ctrl_reg_t; + + +/** Group: config register */ +/** Type of bus_err_conf register + * Clock gating register + */ +typedef union { + struct { + /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; + * Configures whether return error response to cpu when access blocked + * 0: disable error response + * 1: enable error response + */ + uint32_t bus_err_resp_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_bus_err_conf_reg_t; + + +/** Group: clock gating register */ +/** Type of clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ + uint32_t clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} tee_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of date register + * Version control register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 38810240; + * Version control register + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} tee_date_reg_t; + + +typedef struct { + volatile tee_mn_mode_ctrl_reg_t mn_mode_ctrl[32]; + volatile tee_gpspi0_ctrl_reg_t gpspi0_ctrl; + volatile tee_gpspi1_ctrl_reg_t gpspi1_ctrl; + volatile tee_uart0_ctrl_reg_t uart0_ctrl; + volatile tee_uart1_ctrl_reg_t uart1_ctrl; + volatile tee_uhci_ctrl_reg_t uhci_ctrl; + volatile tee_i2c0_ctrl_reg_t i2c0_ctrl; + volatile tee_i2c1_ctrl_reg_t i2c1_ctrl; + volatile tee_i2s_ctrl_reg_t i2s_ctrl; + volatile tee_parl_io_ctrl_reg_t parl_io_ctrl; + volatile tee_pwm0_ctrl_reg_t pwm0_ctrl; + volatile tee_pwm1_ctrl_reg_t pwm1_ctrl; + volatile tee_ledc_ctrl_reg_t ledc_ctrl; + volatile tee_can_ctrl_reg_t can_ctrl; + volatile tee_usb_serial_jtag_ctrl_reg_t usb_serial_jtag_ctrl; + volatile tee_rmt_ctrl_reg_t rmt_ctrl; + volatile tee_gdma_ctrl_reg_t gdma_ctrl; + volatile tee_regdma_ctrl_reg_t regdma_ctrl; + volatile tee_etm_ctrl_reg_t etm_ctrl; + volatile tee_intmtx_core0_ctrl_reg_t intmtx_core0_ctrl; + volatile tee_intmtx_core1_ctrl_reg_t intmtx_core1_ctrl; + volatile tee_apb_adc_ctrl_reg_t apb_adc_ctrl; + volatile tee_timergroup0_ctrl_reg_t timergroup0_ctrl; + volatile tee_timergroup1_ctrl_reg_t timergroup1_ctrl; + volatile tee_systimer_ctrl_reg_t systimer_ctrl; + volatile tee_misc_ctrl_reg_t misc_ctrl; + volatile tee_src_ctrl_reg_t src_ctrl; + volatile tee_usb_otg_fs_core_ctrl_reg_t usb_otg_fs_core_ctrl; + volatile tee_usb_otg_fs_phy_ctrl_reg_t usb_otg_fs_phy_ctrl; + volatile tee_pvt_monitor_ctrl_reg_t pvt_monitor_ctrl; + volatile tee_pcnt_ctrl_reg_t pcnt_ctrl; + volatile tee_iomux_ctrl_reg_t iomux_ctrl; + volatile tee_psram_mem_monitor_ctrl_reg_t psram_mem_monitor_ctrl; + volatile tee_mem_acs_monitor_ctrl_reg_t mem_acs_monitor_ctrl; + volatile tee_hp_system_reg_ctrl_reg_t hp_system_reg_ctrl; + volatile tee_pcr_reg_ctrl_reg_t pcr_reg_ctrl; + volatile tee_mspi_ctrl_reg_t mspi_ctrl; + volatile tee_hp_apm_ctrl_reg_t hp_apm_ctrl; + volatile tee_hp_mem_apm_ctrl_reg_t hp_mem_apm_ctrl; + volatile tee_cpu_apm_ctrl_reg_t cpu_apm_ctrl; + volatile tee_tee_ctrl_reg_t tee_ctrl; + volatile tee_km_ctrl_reg_t km_ctrl; + volatile tee_crypt_ctrl_reg_t crypt_ctrl; + volatile tee_core0_trace_ctrl_reg_t core0_trace_ctrl; + volatile tee_core1_trace_ctrl_reg_t core1_trace_ctrl; + volatile tee_cpu_bus_monitor_ctrl_reg_t cpu_bus_monitor_ctrl; + volatile tee_intpri_reg_ctrl_reg_t intpri_reg_ctrl; + volatile tee_cache_cfg_ctrl_reg_t cache_cfg_ctrl; + volatile tee_modem_ctrl_reg_t modem_ctrl; + volatile tee_zero_det_ctrl_reg_t zero_det_ctrl; + uint32_t reserved_144[939]; + volatile tee_bus_err_conf_reg_t bus_err_conf; + uint32_t reserved_ff4; + volatile tee_clock_gate_reg_t clock_gate; + volatile tee_date_reg_t date; +} tee_dev_t; + +extern tee_dev_t TEE; + +#ifndef __cplusplus +_Static_assert(sizeof(tee_dev_t) == 0x1000, "Invalid size of tee_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif