diff --git a/components/soc/esp32h21/register/soc/ecdsa_reg.h b/components/soc/esp32h21/register/soc/ecdsa_reg.h index 5584ad5d7b..a2f0cdea61 100644 --- a/components/soc/esp32h21/register/soc/ecdsa_reg.h +++ b/components/soc/esp32h21/register/soc/ecdsa_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,62 +12,66 @@ extern "C" { #endif /** ECDSA_CONF_REG register - * ECDSA configure register + * ECDSA configuration register */ #define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) /** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0; - * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature - * Generate Mode. 2: Export Public Key Mode. 3: invalid. + * Configures the working mode of ECDSA accelerator. + * 0: Signature Verification Mode + * 1: Signature Generation Mode + * 2: Public Key Export Mode + * 3: Invalid */ #define ECDSA_WORK_MODE 0x00000003U #define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) #define ECDSA_WORK_MODE_V 0x00000003U #define ECDSA_WORK_MODE_S 0 /** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + * Configures the elliptic curve used. + * 0: P-192 + * 1: P-256 */ #define ECDSA_ECC_CURVE (BIT(2)) #define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) #define ECDSA_ECC_CURVE_V 0x00000001U #define ECDSA_ECC_CURVE_S 2 /** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0; - * The source of k select bit. 0: k is automatically generated by hardware. 1: k is - * written by software. + * Configures the generation source of k. + * 0: k is automatically generated by hardware + * 1: k is written by software */ #define ECDSA_SOFTWARE_SET_K (BIT(3)) #define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) #define ECDSA_SOFTWARE_SET_K_V 0x00000001U #define ECDSA_SOFTWARE_SET_K_S 3 /** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0; - * The source of z select bit. 0: z is generated from SHA result. 1: z is written by - * software. + * Configures how the parameter $z$ is set. + * 0: Generated from SHA result + * 1: Written by software */ #define ECDSA_SOFTWARE_SET_Z (BIT(4)) #define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) #define ECDSA_SOFTWARE_SET_Z_V 0x00000001U #define ECDSA_SOFTWARE_SET_Z_S 4 /** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0; - * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by - * deterministic derivation algorithm. + * + * Configures how the parameter $k$ is set. + * 0: Automatically generated by TRNG + * 1: Generated by the deterministic derivation algorithm */ #define ECDSA_DETERMINISTIC_K (BIT(5)) #define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S) #define ECDSA_DETERMINISTIC_K_V 0x00000001U #define ECDSA_DETERMINISTIC_K_S 5 -/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0; - * The (loop number - 1) value in the deterministic derivation algorithm to derive k. - */ -#define ECDSA_DETERMINISTIC_LOOP 0x0000FFFFU -#define ECDSA_DETERMINISTIC_LOOP_M (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S) -#define ECDSA_DETERMINISTIC_LOOP_V 0x0000FFFFU -#define ECDSA_DETERMINISTIC_LOOP_S 6 /** ECDSA_CLK_REG register * ECDSA clock gate register */ #define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) /** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; - * Write 1 to force on register clock gate. + * Configures whether to force on ECDSA memory clock gate. + * 0: No effect + * 1: Force on */ #define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) #define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) @@ -75,32 +79,32 @@ extern "C" { #define ECDSA_CLK_GATE_FORCE_ON_S 0 /** ECDSA_INT_RAW_REG register - * ECDSA interrupt raw register, valid in level. + * ECDSA interrupt raw register */ #define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) -/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the ecdsa_prep_done_int interrupt +/** ECDSA_PREP_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of the ECDSA_PREP_DONE_INT interrupt. */ #define ECDSA_PREP_DONE_INT_RAW (BIT(0)) #define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S) #define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U #define ECDSA_PREP_DONE_INT_RAW_S 0 -/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the ecdsa_proc_done_int interrupt +/** ECDSA_PROC_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status of the ECDSA_PROC_DONE_INT interrupt. */ #define ECDSA_PROC_DONE_INT_RAW (BIT(1)) #define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S) #define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U #define ECDSA_PROC_DONE_INT_RAW_S 1 -/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the ecdsa_post_done_int interrupt +/** ECDSA_POST_DONE_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of the ECDSA_POST_DONE_INT interrupt. */ #define ECDSA_POST_DONE_INT_RAW (BIT(2)) #define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S) #define ECDSA_POST_DONE_INT_RAW_V 0x00000001U #define ECDSA_POST_DONE_INT_RAW_S 2 -/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status bit for the ecdsa_sha_release_int interrupt +/** ECDSA_SHA_RELEASE_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the ECDSA_SHA_RELEASE_INT interrupt. */ #define ECDSA_SHA_RELEASE_INT_RAW (BIT(3)) #define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) @@ -108,32 +112,32 @@ extern "C" { #define ECDSA_SHA_RELEASE_INT_RAW_S 3 /** ECDSA_INT_ST_REG register - * ECDSA interrupt status register. + * ECDSA interrupt status register */ #define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) /** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the ecdsa_prep_done_int interrupt + * The masked interrupt status of the ECDSA_PREP_DONE_INT interrupt. */ #define ECDSA_PREP_DONE_INT_ST (BIT(0)) #define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S) #define ECDSA_PREP_DONE_INT_ST_V 0x00000001U #define ECDSA_PREP_DONE_INT_ST_S 0 /** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the ecdsa_proc_done_int interrupt + * The masked interrupt status of the ECDSA_PROC_DONE_INT interrupt. */ #define ECDSA_PROC_DONE_INT_ST (BIT(1)) #define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S) #define ECDSA_PROC_DONE_INT_ST_V 0x00000001U #define ECDSA_PROC_DONE_INT_ST_S 1 /** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the ecdsa_post_done_int interrupt + * The masked interrupt status of the ECDSA_POST_DONE_INT interrupt. */ #define ECDSA_POST_DONE_INT_ST (BIT(2)) #define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S) #define ECDSA_POST_DONE_INT_ST_V 0x00000001U #define ECDSA_POST_DONE_INT_ST_S 2 /** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + * The masked interrupt status of the ECDSA_SHA_RELEASE_INT interrupt. */ #define ECDSA_SHA_RELEASE_INT_ST (BIT(3)) #define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) @@ -141,32 +145,32 @@ extern "C" { #define ECDSA_SHA_RELEASE_INT_ST_S 3 /** ECDSA_INT_ENA_REG register - * ECDSA interrupt enable register. + * ECDSA interrupt enable register */ #define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) /** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the ecdsa_prep_done_int interrupt + * Write 1 to enable the ECDSA_PREP_DONE_INT interrupt. */ #define ECDSA_PREP_DONE_INT_ENA (BIT(0)) #define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S) #define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U #define ECDSA_PREP_DONE_INT_ENA_S 0 /** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the ecdsa_proc_done_int interrupt + * Write 1 to enable the ECDSA_PROC_DONE_INT interrupt. */ #define ECDSA_PROC_DONE_INT_ENA (BIT(1)) #define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S) #define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U #define ECDSA_PROC_DONE_INT_ENA_S 1 /** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the ecdsa_post_done_int interrupt + * Write 1 to enable the ECDSA_POST_DONE_INT interrupt. */ #define ECDSA_POST_DONE_INT_ENA (BIT(2)) #define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S) #define ECDSA_POST_DONE_INT_ENA_V 0x00000001U #define ECDSA_POST_DONE_INT_ENA_S 2 /** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the ecdsa_sha_release_int interrupt + * Write 1 to enable the ECDSA_SHA_RELEASE_INT interrupt. */ #define ECDSA_SHA_RELEASE_INT_ENA (BIT(3)) #define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) @@ -174,32 +178,32 @@ extern "C" { #define ECDSA_SHA_RELEASE_INT_ENA_S 3 /** ECDSA_INT_CLR_REG register - * ECDSA interrupt clear register. + * ECDSA interrupt clear register */ #define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) /** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the ecdsa_prep_done_int interrupt + * Write 1 to clear the ECDSA_PREP_DONE_INT interrupt. */ #define ECDSA_PREP_DONE_INT_CLR (BIT(0)) #define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S) #define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U #define ECDSA_PREP_DONE_INT_CLR_S 0 /** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the ecdsa_proc_done_int interrupt + * Write 1 to clear the ECDSA_PROC_DONE_INT interrupt. */ #define ECDSA_PROC_DONE_INT_CLR (BIT(1)) #define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S) #define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U #define ECDSA_PROC_DONE_INT_CLR_S 1 /** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the ecdsa_post_done_int interrupt + * Write 1 to clear the ECDSA_POST_DONE_INT interrupt. */ #define ECDSA_POST_DONE_INT_CLR (BIT(2)) #define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S) #define ECDSA_POST_DONE_INT_CLR_V 0x00000001U #define ECDSA_POST_DONE_INT_CLR_S 2 /** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the ecdsa_sha_release_int interrupt + * Write 1 to clear the ECDSA_SHA_RELEASE_INT interrupt. */ #define ECDSA_SHA_RELEASE_INT_CLR (BIT(3)) #define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) @@ -211,24 +215,26 @@ extern "C" { */ #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) /** ECDSA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared + * Configures whether to start the ECDSA operation. This bit will be self-cleared * after configuration. + * 0: No effect + * 1: Start the ECDSA operation */ #define ECDSA_START (BIT(0)) #define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) #define ECDSA_START_V 0x00000001U #define ECDSA_START_S 0 /** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; - * Write 1 to input load done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. + * Write 1 to generate a signal indicating the ECDSA accelerator's LOAD operation is + * done. This bit will be self-cleared after configuration. */ #define ECDSA_LOAD_DONE (BIT(1)) #define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) #define ECDSA_LOAD_DONE_V 0x00000001U #define ECDSA_LOAD_DONE_S 1 /** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; - * Write 1 to input get done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. + * Write 1 to generate a signal indicating the ECDSA accelerator's GAIN operation is + * done. This bit will be self-cleared after configuration. */ #define ECDSA_GET_DONE (BIT(2)) #define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) @@ -240,8 +246,11 @@ extern "C" { */ #define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) /** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; - * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY - * state. + * Represents the working status of the ECDSA accelerator. + * 0: IDLE + * 1: LOAD + * 2: GAIN + * 3: BUSY */ #define ECDSA_BUSY 0x00000003U #define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) @@ -253,28 +262,22 @@ extern "C" { */ #define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) /** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; - * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is - * done. + * Indicates if the ECDSA operation is successful. + * 0: Not successful + * 1: Successful + * Only valid when the ECDSA operation is done. */ #define ECDSA_OPERATION_RESULT (BIT(0)) #define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) #define ECDSA_OPERATION_RESULT_V 0x00000001U #define ECDSA_OPERATION_RESULT_S 0 -/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0; - * The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the - * curve order, then actually taken k = k mod n. - */ -#define ECDSA_K_VALUE_WARNING (BIT(1)) -#define ECDSA_K_VALUE_WARNING_M (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S) -#define ECDSA_K_VALUE_WARNING_V 0x00000001U -#define ECDSA_K_VALUE_WARNING_S 1 /** ECDSA_DATE_REG register * Version control register */ #define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) /** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37761312; - * ECDSA version control register + * The ECDSA version control register. */ #define ECDSA_DATE 0x0FFFFFFFU #define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) @@ -282,12 +285,14 @@ extern "C" { #define ECDSA_DATE_S 0 /** ECDSA_SHA_MODE_REG register - * ECDSA control SHA register + * ECDSA SHA-control register (Hash algrithm) */ #define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) /** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. - * Others: invalid. + * Configures SHA algorithms for message hash. + * 1: SHA-224 + * 2: SHA-256 + * Others: invalid */ #define ECDSA_SHA_MODE 0x00000007U #define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) @@ -295,12 +300,12 @@ extern "C" { #define ECDSA_SHA_MODE_S 0 /** ECDSA_SHA_START_REG register - * ECDSA control SHA register + * ECDSA SHA-control register (operation) */ #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; - * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. + * Write 1 to start the first SHA operation in the ECDSA process. This bit will be + * self-cleared after configuration. */ #define ECDSA_SHA_START (BIT(0)) #define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) @@ -308,12 +313,12 @@ extern "C" { #define ECDSA_SHA_START_S 0 /** ECDSA_SHA_CONTINUE_REG register - * ECDSA control SHA register + * ECDSA SHA-control register (operation) */ #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. + * Write 1 to start the latter SHA operation in the ECDSA process. This bit will be + * self-cleared after configuration. */ #define ECDSA_SHA_CONTINUE (BIT(0)) #define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) @@ -321,12 +326,13 @@ extern "C" { #define ECDSA_SHA_CONTINUE_S 0 /** ECDSA_SHA_BUSY_REG register - * ECDSA status register + * ECDSA SHA-control status register */ #define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) /** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; - * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in - * calculation. 0: SHA is idle. + * Represents the working status of the SHA accelerator in the ECDSA process. + * 0: IDLE + * 1: BUSY */ #define ECDSA_SHA_BUSY (BIT(0)) #define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) diff --git a/components/soc/esp32h21/register/soc/ecdsa_struct.h b/components/soc/esp32h21/register/soc/ecdsa_struct.h index e42cb6b07e..ba497265c3 100644 --- a/components/soc/esp32h21/register/soc/ecdsa_struct.h +++ b/components/soc/esp32h21/register/soc/ecdsa_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,34 +12,43 @@ extern "C" { /** Group: Data Memory */ -/** Group: Configuration registers */ +/** Group: Configuration Registers */ /** Type of conf register - * ECDSA configure register + * ECDSA configuration register */ typedef union { struct { /** work_mode : R/W; bitpos: [1:0]; default: 0; - * The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature - * Generate Mode. 2: Export Public Key Mode. 3: invalid. + * Configures the working mode of ECDSA accelerator. + * 0: Signature Verification Mode + * 1: Signature Generation Mode + * 2: Public Key Export Mode + * 3: Invalid */ uint32_t work_mode:2; /** ecc_curve : R/W; bitpos: [2]; default: 0; - * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. + * Configures the elliptic curve used. + * 0: P-192 + * 1: P-256 */ uint32_t ecc_curve:1; /** software_set_k : R/W; bitpos: [3]; default: 0; - * The source of k select bit. 0: k is automatically generated by hardware. 1: k is - * written by software. + * Configures the generation source of k. + * 0: k is automatically generated by hardware + * 1: k is written by software */ uint32_t software_set_k:1; /** software_set_z : R/W; bitpos: [4]; default: 0; - * The source of z select bit. 0: z is generated from SHA result. 1: z is written by - * software. + * Configures how the parameter $z$ is set. + * 0: Generated from SHA result + * 1: Written by software */ uint32_t software_set_z:1; /** deterministic_k : R/W; bitpos: [5]; default: 0; - * The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by - * deterministic derivation algorithm. + * + * Configures how the parameter $k$ is set. + * 0: Automatically generated by TRNG + * 1: Generated by the deterministic derivation algorithm */ uint32_t deterministic_k:1; uint32_t reserved_6:26; @@ -53,18 +62,20 @@ typedef union { typedef union { struct { /** start : WT; bitpos: [0]; default: 0; - * Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared + * Configures whether to start the ECDSA operation. This bit will be self-cleared * after configuration. + * 0: No effect + * 1: Start the ECDSA operation */ uint32_t start:1; /** load_done : WT; bitpos: [1]; default: 0; - * Write 1 to input load done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. + * Write 1 to generate a signal indicating the ECDSA accelerator's LOAD operation is + * done. This bit will be self-cleared after configuration. */ uint32_t load_done:1; /** get_done : WT; bitpos: [2]; default: 0; - * Write 1 to input get done signal of ECDSA Accelerator. This bit will be - * self-cleared after configuration. + * Write 1 to generate a signal indicating the ECDSA accelerator's GAIN operation is + * done. This bit will be self-cleared after configuration. */ uint32_t get_done:1; uint32_t reserved_3:29; @@ -73,14 +84,16 @@ typedef union { } ecdsa_start_reg_t; -/** Group: Clock and reset registers */ +/** Group: Clock and Reset Register */ /** Type of clk register * ECDSA clock gate register */ typedef union { struct { /** clk_gate_force_on : R/W; bitpos: [0]; default: 0; - * Write 1 to force on register clock gate. + * Configures whether to force on ECDSA memory clock gate. + * 0: No effect + * 1: Force on */ uint32_t clk_gate_force_on:1; uint32_t reserved_1:31; @@ -89,26 +102,26 @@ typedef union { } ecdsa_clk_reg_t; -/** Group: Interrupt registers */ +/** Group: Interrupt Registers */ /** Type of int_raw register - * ECDSA interrupt raw register, valid in level. + * ECDSA interrupt raw register */ typedef union { struct { - /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the ecdsa_prep_done_int interrupt + /** prep_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt status of the ECDSA_PREP_DONE_INT interrupt. */ uint32_t prep_done_int_raw:1; - /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the ecdsa_proc_done_int interrupt + /** proc_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0; + * The raw interrupt status of the ECDSA_PROC_DONE_INT interrupt. */ uint32_t proc_done_int_raw:1; - /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the ecdsa_post_done_int interrupt + /** post_done_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt status of the ECDSA_POST_DONE_INT interrupt. */ uint32_t post_done_int_raw:1; - /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt status bit for the ecdsa_sha_release_int interrupt + /** sha_release_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt status of the ECDSA_SHA_RELEASE_INT interrupt. */ uint32_t sha_release_int_raw:1; uint32_t reserved_4:28; @@ -117,24 +130,24 @@ typedef union { } ecdsa_int_raw_reg_t; /** Type of int_st register - * ECDSA interrupt status register. + * ECDSA interrupt status register */ typedef union { struct { /** prep_done_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the ecdsa_prep_done_int interrupt + * The masked interrupt status of the ECDSA_PREP_DONE_INT interrupt. */ uint32_t prep_done_int_st:1; /** proc_done_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the ecdsa_proc_done_int interrupt + * The masked interrupt status of the ECDSA_PROC_DONE_INT interrupt. */ uint32_t proc_done_int_st:1; /** post_done_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the ecdsa_post_done_int interrupt + * The masked interrupt status of the ECDSA_POST_DONE_INT interrupt. */ uint32_t post_done_int_st:1; /** sha_release_int_st : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the ecdsa_sha_release_int interrupt + * The masked interrupt status of the ECDSA_SHA_RELEASE_INT interrupt. */ uint32_t sha_release_int_st:1; uint32_t reserved_4:28; @@ -143,24 +156,24 @@ typedef union { } ecdsa_int_st_reg_t; /** Type of int_ena register - * ECDSA interrupt enable register. + * ECDSA interrupt enable register */ typedef union { struct { /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the ecdsa_prep_done_int interrupt + * Write 1 to enable the ECDSA_PREP_DONE_INT interrupt. */ uint32_t prep_done_int_ena:1; /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the ecdsa_proc_done_int interrupt + * Write 1 to enable the ECDSA_PROC_DONE_INT interrupt. */ uint32_t proc_done_int_ena:1; /** post_done_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the ecdsa_post_done_int interrupt + * Write 1 to enable the ECDSA_POST_DONE_INT interrupt. */ uint32_t post_done_int_ena:1; /** sha_release_int_ena : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the ecdsa_sha_release_int interrupt + * Write 1 to enable the ECDSA_SHA_RELEASE_INT interrupt. */ uint32_t sha_release_int_ena:1; uint32_t reserved_4:28; @@ -169,24 +182,24 @@ typedef union { } ecdsa_int_ena_reg_t; /** Type of int_clr register - * ECDSA interrupt clear register. + * ECDSA interrupt clear register */ typedef union { struct { /** prep_done_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the ecdsa_prep_done_int interrupt + * Write 1 to clear the ECDSA_PREP_DONE_INT interrupt. */ uint32_t prep_done_int_clr:1; /** proc_done_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the ecdsa_proc_done_int interrupt + * Write 1 to clear the ECDSA_PROC_DONE_INT interrupt. */ uint32_t proc_done_int_clr:1; /** post_done_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the ecdsa_post_done_int interrupt + * Write 1 to clear the ECDSA_POST_DONE_INT interrupt. */ uint32_t post_done_int_clr:1; /** sha_release_int_clr : WT; bitpos: [3]; default: 0; - * Set this bit to clear the ecdsa_sha_release_int interrupt + * Write 1 to clear the ECDSA_SHA_RELEASE_INT interrupt. */ uint32_t sha_release_int_clr:1; uint32_t reserved_4:28; @@ -195,15 +208,18 @@ typedef union { } ecdsa_int_clr_reg_t; -/** Group: Status registers */ +/** Group: Status Registers */ /** Type of state register * ECDSA status register */ typedef union { struct { /** busy : RO; bitpos: [1:0]; default: 0; - * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY - * state. + * Represents the working status of the ECDSA accelerator. + * 0: IDLE + * 1: LOAD + * 2: GAIN + * 3: BUSY */ uint32_t busy:2; uint32_t reserved_2:30; @@ -212,15 +228,17 @@ typedef union { } ecdsa_state_reg_t; -/** Group: Result registers */ +/** Group: Result Register */ /** Type of result register * ECDSA result register */ typedef union { struct { /** operation_result : RO/SS; bitpos: [0]; default: 0; - * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is - * done. + * Indicates if the ECDSA operation is successful. + * 0: Not successful + * 1: Successful + * Only valid when the ECDSA operation is done. */ uint32_t operation_result:1; uint32_t reserved_1:31; @@ -229,15 +247,17 @@ typedef union { } ecdsa_result_reg_t; -/** Group: SHA register */ +/** Group: SHA Registers */ /** Type of sha_mode register - * ECDSA control SHA register + * ECDSA SHA-control register (Hash algrithm) */ typedef union { struct { /** sha_mode : R/W; bitpos: [2:0]; default: 0; - * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. - * Others: invalid. + * Configures SHA algorithms for message hash. + * 1: SHA-224 + * 2: SHA-256 + * Others: invalid */ uint32_t sha_mode:3; uint32_t reserved_3:29; @@ -246,13 +266,13 @@ typedef union { } ecdsa_sha_mode_reg_t; /** Type of sha_start register - * ECDSA control SHA register + * ECDSA SHA-control register (operation) */ typedef union { struct { /** sha_start : WT; bitpos: [0]; default: 0; - * Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. + * Write 1 to start the first SHA operation in the ECDSA process. This bit will be + * self-cleared after configuration. */ uint32_t sha_start:1; uint32_t reserved_1:31; @@ -261,13 +281,13 @@ typedef union { } ecdsa_sha_start_reg_t; /** Type of sha_continue register - * ECDSA control SHA register + * ECDSA SHA-control register (operation) */ typedef union { struct { /** sha_continue : WT; bitpos: [0]; default: 0; - * Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This - * bit will be self-cleared after configuration. + * Write 1 to start the latter SHA operation in the ECDSA process. This bit will be + * self-cleared after configuration. */ uint32_t sha_continue:1; uint32_t reserved_1:31; @@ -276,13 +296,14 @@ typedef union { } ecdsa_sha_continue_reg_t; /** Type of sha_busy register - * ECDSA status register + * ECDSA SHA-control status register */ typedef union { struct { /** sha_busy : RO; bitpos: [0]; default: 0; - * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in - * calculation. 0: SHA is idle. + * Represents the working status of the SHA accelerator in the ECDSA process. + * 0: IDLE + * 1: BUSY */ uint32_t sha_busy:1; uint32_t reserved_1:31; @@ -291,14 +312,14 @@ typedef union { } ecdsa_sha_busy_reg_t; -/** Group: Version register */ +/** Group: Version Register */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 37761312; - * ECDSA version control register + * The ECDSA version control register. */ uint32_t date:28; uint32_t reserved_28:4;