fix(gpio): fix 8/16-bit gpio, rtc/lp_io register access

components/esp_driver_gpio/test_apps/gpio/CMakeLists.txt

@@ -19,3 +19,13 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
                       DEPENDS ${elf}
                       )
 endif()
+
+include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
+message(STATUS "Checking gpio registers are not read-write by half-word")
+check_register_rw_half_word(SOC_MODULES "gpio" "io_mux" "rtc_cntl" "rtc_io" "pcr" "hp_sys_clkrst" "hp_system"
+                                        "lp_aon" "lp_iomux" "pmu"
+                            HAL_MODULES "gpio")
+
+message(STATUS "Checking rtcio registers are not read-write by half-word")
+check_register_rw_half_word(SOC_MODULES "rtc_io" "sens" "pcr" "lp_aon" "lp_io" "lp_gpio" "lp_iomux" "lpperi" "pmu"
+                            HAL_MODULES "rtc_io")

components/esp_driver_gpio/test_apps/gpio_extensions/main/CMakeLists.txt

@@ -21,3 +21,8 @@ endif()
 idf_component_register(SRCS ${srcs}
                        PRIV_REQUIRES unity esp_driver_gpio
                        WHOLE_ARCHIVE)
+
+message(STATUS "Checking gpio_ext registers are not read-write by half-word")
+include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
+check_register_rw_half_word(SOC_MODULES "gpio_ext"
+                            HAL_MODULES "gpio_etm" "gpio_glitch_filter")

components/esp_driver_sdm/test_apps/sigma_delta/CMakeLists.txt

@@ -19,3 +19,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
                       DEPENDS ${elf}
                       )
 endif()
+
+message(STATUS "Checking sdm registers are not read-write by half-word")
+include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
+check_register_rw_half_word(SOC_MODULES "gpio_ext" "gpio_sd"
+                            HAL_MODULES "sdm")

components/hal/esp32c2/include/hal/gpio_ll.h

@@ -21,6 +21,7 @@
 #include "soc/rtc_cntl_reg.h"
 #include "hal/gpio_types.h"
 #include "hal/assert.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -60,7 +61,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
     *od = hw->pin[gpio_num].pad_driver;
     *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
     *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
-    *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
+    *sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
     *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
 }
 
@@ -300,10 +301,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    gpio_func_out_sel_cfg_reg_t reg = {
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
-      .func_sel = SIG_GPIO_OUT_IDX,
-    };
-    hw->func_out_sel_cfg[gpio_num].val = reg.val;
 }
 
 /**
@@ -553,7 +551,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 {
     gpio_func_in_sel_cfg_reg_t reg;
     reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
-    return (reg.sig_in_sel ? reg.func_sel : -1);
+    return (reg.sig_in_sel ? reg.in_sel : -1);
 }
 
 /**

components/hal/esp32c3/include/hal/gpio_ll.h

@@ -23,6 +23,7 @@
 #include "soc/usb_serial_jtag_reg.h"
 #include "hal/gpio_types.h"
 #include "hal/assert.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -544,7 +545,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
 {
     typeof(hw->func_in_sel_cfg[in_sig_idx]) reg;
     reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
-    return (reg.sig_in_sel ? reg.func_sel : -1);
+    return (reg.sig_in_sel ? reg.in_sel : -1);
 }
 
 /**
@@ -766,7 +767,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
     *od = hw->pin[gpio_num].pad_driver;
     gpio_ll_get_drive_capability(hw, gpio_num, (gpio_drive_cap_t *)drv); // specific workaround in the LL
     *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
-    *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
+    *sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
     *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
 }
 

components/hal/esp32c5/include/hal/gpio_ll.h

@@ -27,7 +27,6 @@
 #include "soc/usb_serial_jtag_struct.h"
 #include "hal/gpio_types.h"
 #include "hal/assert.h"
-#include "soc/lp_gpio_struct.h"
 
 #ifdef __cplusplus
 extern "C" {

components/hal/esp32c5/include/hal/rtc_io_ll.h

@@ -115,7 +115,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
  */
 static inline void rtcio_ll_output_enable(int rtcio_num)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, enable_w1ts, BIT(rtcio_num));
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, out_enable_w1ts, BIT(rtcio_num));
 }
 
 /**
@@ -125,7 +125,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
  */
 static inline void rtcio_ll_output_disable(int rtcio_num)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, enable_w1tc, BIT(rtcio_num));
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, out_enable_w1tc, BIT(rtcio_num));
 }
 
 /**
@@ -137,9 +137,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
 static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
 {
     if (level) {
-        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_w1ts, BIT(rtcio_num));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_data_w1ts, BIT(rtcio_num));
     } else {
-        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_w1tc, BIT(rtcio_num));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_data_w1tc, BIT(rtcio_num));
     }
 }
 
@@ -357,7 +357,7 @@ static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type
     LP_GPIO.pinn[rtcio_num].pinn_int_type = type;
 
     /* Work around for HW issue,
-       need to also enable this clk, so that LP_GPIO.status.status_interrupt can get updated,
+       need to also enable this clk, so that (LP_GPIO.status, status_interrupt) can get updated,
        and trigger the interrupt on the LP Core
     */
     LP_GPIO.clock_gate.clk_en = 1;
@@ -450,7 +450,7 @@ static inline  uint32_t rtcio_ll_get_interrupt_status(void)
  */
 static inline  void rtcio_ll_clear_interrupt_status(void)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_w1tc, 0xff);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_intr_w1tc, 0xff);
 }
 
 #ifdef __cplusplus

components/hal/esp32c6/include/hal/gpio_ll.h

@@ -20,13 +20,13 @@
 #include "soc/gpio_periph.h"
 #include "soc/gpio_struct.h"
 #include "soc/lp_aon_struct.h"
-#include "soc/lp_io_struct.h"
 #include "soc/pmu_struct.h"
 #include "soc/usb_serial_jtag_reg.h"
 #include "soc/pcr_struct.h"
 #include "soc/clk_tree_defs.h"
 #include "hal/gpio_types.h"
 #include "hal/assert.h"
+#include "hal/misc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -66,7 +66,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
     *od = hw->pin[gpio_num].pad_driver;
     *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
     *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
-    *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
+    *sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
     *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
 }
 
@@ -315,10 +315,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    gpio_func_out_sel_cfg_reg_t reg = {
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
-      .out_sel = SIG_GPIO_OUT_IDX,
-    };
-    hw->func_out_sel_cfg[gpio_num].val = reg.val;
 }
 
 /**

components/hal/esp32c6/include/hal/rtc_io_ll.h

@@ -136,9 +136,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
 static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
 {
     if (level) {
-        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_data_w1ts, BIT(rtcio_num));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_w1ts, BIT(rtcio_num));
     } else {
-        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_data_w1tc, BIT(rtcio_num));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_w1tc, BIT(rtcio_num));
     }
 }
 
@@ -364,7 +364,7 @@ static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type
     LP_IO.pin[rtcio_num].int_type = type;
 
     /* Work around for HW issue,
-       need to also enable this clk, so that LP_IO.status.status_interrupt can get updated,
+       need to also enable this clk, so that (LP_IO.status, status_interrupt) can get updated,
        and trigger the interrupt on the LP Core
     */
     LP_IO.date.clk_en = 1;
@@ -457,7 +457,7 @@ static inline  uint32_t rtcio_ll_get_interrupt_status(void)
  */
 static inline  void rtcio_ll_clear_interrupt_status(void)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_w1tc, 0xff);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_intr_w1tc, 0xff);
 }
 
 #ifdef __cplusplus

components/hal/esp32h2/include/hal/gpio_ll.h

@@ -66,7 +66,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
     *od = hw->pin[gpio_num].pad_driver;
     *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
     *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
-    *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
+    *sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
     *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
 }
 
@@ -360,10 +360,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    gpio_func_out_sel_cfg_reg_t reg = {
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
-      .out_sel = SIG_GPIO_OUT_IDX,
-    };
-    hw->func_out_sel_cfg[gpio_num].val = reg.val;
 }
 
 /**

components/hal/esp32p4/include/hal/gpio_ll.h

@@ -285,7 +285,9 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
     uint64_t bit_mask = 1ULL << gpio_num;
     if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
         // GPIO0-15
-        LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys |= bit_mask;
+        uint32_t hys_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys);
+        hys_mask |= bit_mask;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys, hys_mask);
     } else {
         if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
             // GPIO 16-47
@@ -308,7 +310,9 @@ static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t
     uint64_t bit_mask = 1ULL << gpio_num;
     if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
         // GPIO0-15
-        LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys &= ~bit_mask;
+        uint32_t hys_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys);
+        hys_mask &= ~bit_mask;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys, hys_mask);
     } else {
         if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
             // GPIO 16-47

components/hal/esp32s2/include/hal/gpio_ll.h

@@ -18,7 +18,6 @@
 #include "soc/soc.h"
 #include "soc/gpio_periph.h"
 #include "soc/rtc_cntl_reg.h"
-#include "soc/rtc_io_reg.h"
 #include "soc/gpio_struct.h"
 #include "hal/gpio_types.h"
 #include "hal/assert.h"

components/hal/esp32s3/include/hal/gpio_ll.h

@@ -18,7 +18,6 @@
 #include "soc/soc.h"
 #include "soc/gpio_periph.h"
 #include "soc/rtc_cntl_reg.h"
-#include "soc/rtc_io_reg.h"
 #include "soc/usb_serial_jtag_reg.h"
 #include "hal/gpio_types.h"
 #include "soc/gpio_struct.h"

components/soc/esp32c2/register/soc/gpio_struct.h

@@ -301,7 +301,7 @@ typedef union {
          *  set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
          *  high level. s=0x3C: set this port always low level.
          */
-        uint32_t func_sel:5;
+        uint32_t in_sel:5;
         /** in_inv_sel : R/W; bitpos: [5]; default: 0;
          *  set this bit to invert input signal. 1:invert. 0:not invert.
          */
@@ -325,7 +325,7 @@ typedef union {
          *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
          *  GPIO_OUT_REG[n].
          */
-        uint32_t func_sel:8;
+        uint32_t out_sel:8;
         /** out_inv_sel : R/W; bitpos: [8]; default: 0;
          *  set this bit to invert output signal.1:invert.0:not invert.
          */

components/soc/esp32c3/register/soc/gpio_struct.h

@@ -182,7 +182,7 @@ typedef volatile struct gpio_dev_s {
     uint32_t reserved_150;
     union {
         struct {
-            uint32_t func_sel:         5;
+            uint32_t in_sel:           5;
             uint32_t sig_in_inv:       1;
             uint32_t sig_in_sel:       1;
             uint32_t reserved7:       25;
@@ -319,7 +319,7 @@ typedef volatile struct gpio_dev_s {
     uint32_t reserved_550;
     union {
         struct {
-            uint32_t func_sel:          8;
+            uint32_t out_sel:           8;
             uint32_t inv_sel:           1;
             uint32_t oen_sel:           1;
             uint32_t oen_inv_sel:       1;

components/soc/esp32c5/register/soc/lp_gpio_struct.h

@@ -33,7 +33,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** out_w1ts : WT; bitpos: [7:0]; default: 0;
+        /** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
          *  Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0 ~
          *  GPIO7.\\
          *
@@ -42,7 +42,7 @@ typedef union {
          *  will be set to 1.
          *  - Recommended operation: use this register to set LP_IO_OUT_REG.
          */
-        uint32_t out_w1ts:8;
+        uint32_t out_data_w1ts:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
@@ -53,7 +53,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** out_w1tc : WT; bitpos: [7:0]; default: 0;
+        /** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
          *  Configures whether or not to clear the output register LP_IO_OUT_REG of GPIO0 ~
          *  GPIO7.\\
          *
@@ -62,7 +62,7 @@ typedef union {
          *  will be cleared.
          *  - Recommended operation: use this register to clear LP_IO_OUT_REG.
          */
-        uint32_t out_w1tc:8;
+        uint32_t out_data_w1tc:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
@@ -90,7 +90,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** enable_w1ts : WT; bitpos: [7:0]; default: 0;
+        /** out_enable_w1ts : WT; bitpos: [7:0]; default: 0;
          *  Configures whether or not to set the output enable register LP_IO_ENABLE_REG of
          *  GPIO0 ~ GPIO7.\\
          *
@@ -99,7 +99,7 @@ typedef union {
          *  LP_IO_ENABLE_REG will be set to 1.
          *  - Recommended operation: use this register to set LP_IO_ENABLE_REG.
          */
-        uint32_t enable_w1ts:8;
+        uint32_t out_enable_w1ts:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
@@ -110,7 +110,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** enable_w1tc : WT; bitpos: [7:0]; default: 0;
+        /** out_enable_w1tc : WT; bitpos: [7:0]; default: 0;
          *  Configures whether or not to clear the output enable register LP_IO_ENABLE_REG of
          *  GPIO0 ~ GPIO7.\\
          *
@@ -119,7 +119,7 @@ typedef union {
          *  LP_IO_ENABLE_REG will be cleared.
          *  - Recommended operation: use this register to clear LP_IO_ENABLE_REG.
          */
-        uint32_t enable_w1tc:8;
+        uint32_t out_enable_w1tc:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
@@ -165,7 +165,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** status_w1ts : WT; bitpos: [7:0]; default: 0;
+        /** status_intr_w1ts : WT; bitpos: [7:0]; default: 0;
          *  Configures whether or not to set the interrupt status register LP_IO_STATUS_INT of
          *  GPIO0 ~ GPIO7.\\
          *
@@ -174,7 +174,7 @@ typedef union {
          *  LP_IO_STATUS_INT will be set to 1.
          *  - Recommended operation: use this register to set LP_IO_STATUS_INT.
          */
-        uint32_t status_w1ts:8;
+        uint32_t status_intr_w1ts:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
@@ -185,7 +185,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** status_w1tc : WT; bitpos: [7:0]; default: 0;
+        /** status_intr_w1tc : WT; bitpos: [7:0]; default: 0;
          *  Configures whether or not to clear the interrupt status register LP_IO_STATUS_INT
          *  of GPIO0 ~ GPIO7. \\
          *
@@ -194,7 +194,7 @@ typedef union {
          *  LP_IO_STATUS_INT will be cleared
          *  - ecommended operation: use this register to clear LP_IO_STATUS_INT.
          */
-        uint32_t status_w1tc:8;
+        uint32_t status_intr_w1tc:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;

components/soc/esp32c6/register/soc/lp_io_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -30,10 +30,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
+        /** out_w1ts : WT; bitpos: [7:0]; default: 0;
          *  set one time output data
          */
-        uint32_t out_data_w1ts:8;
+        uint32_t out_w1ts:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
@@ -44,10 +44,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
+        /** out_w1tc : WT; bitpos: [7:0]; default: 0;
          *  clear one time output data
          */
-        uint32_t out_data_w1tc:8;
+        uint32_t out_w1tc:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
@@ -114,10 +114,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** status_w1ts : WT; bitpos: [7:0]; default: 0;
+        /** status_intr_w1ts : WT; bitpos: [7:0]; default: 0;
          *  set one time output data
          */
-        uint32_t status_w1ts:8;
+        uint32_t status_intr_w1ts:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;
@@ -128,10 +128,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** status_w1tc : WT; bitpos: [7:0]; default: 0;
+        /** status_intr_w1tc : WT; bitpos: [7:0]; default: 0;
          *  clear one time output data
          */
-        uint32_t status_w1tc:8;
+        uint32_t status_intr_w1tc:8;
         uint32_t reserved_8:24;
     };
     uint32_t val;