mirror of
https://github.com/espressif/esp-idf.git
synced 2025-07-30 18:57:19 +02:00
fix(gpio): fix 8/16-bit gpio, rtc/lp_io register access
This commit is contained in:
@ -19,3 +19,13 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
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DEPENDS ${elf}
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)
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endif()
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include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
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message(STATUS "Checking gpio registers are not read-write by half-word")
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check_register_rw_half_word(SOC_MODULES "gpio" "io_mux" "rtc_cntl" "rtc_io" "pcr" "hp_sys_clkrst" "hp_system"
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"lp_aon" "lp_iomux" "pmu"
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HAL_MODULES "gpio")
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message(STATUS "Checking rtcio registers are not read-write by half-word")
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check_register_rw_half_word(SOC_MODULES "rtc_io" "sens" "pcr" "lp_aon" "lp_io" "lp_gpio" "lp_iomux" "lpperi" "pmu"
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HAL_MODULES "rtc_io")
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@ -21,3 +21,8 @@ endif()
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idf_component_register(SRCS ${srcs}
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PRIV_REQUIRES unity esp_driver_gpio
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WHOLE_ARCHIVE)
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message(STATUS "Checking gpio_ext registers are not read-write by half-word")
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include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
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check_register_rw_half_word(SOC_MODULES "gpio_ext"
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HAL_MODULES "gpio_etm" "gpio_glitch_filter")
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@ -19,3 +19,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
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DEPENDS ${elf}
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)
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endif()
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message(STATUS "Checking sdm registers are not read-write by half-word")
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include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
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check_register_rw_half_word(SOC_MODULES "gpio_ext" "gpio_sd"
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HAL_MODULES "sdm")
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@ -21,6 +21,7 @@
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#include "soc/rtc_cntl_reg.h"
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#include "hal/gpio_types.h"
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#include "hal/assert.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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@ -60,7 +61,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
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*od = hw->pin[gpio_num].pad_driver;
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*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
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*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
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*sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
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*sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
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*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
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}
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@ -300,10 +301,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
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__attribute__((always_inline))
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static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
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{
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gpio_func_out_sel_cfg_reg_t reg = {
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.func_sel = SIG_GPIO_OUT_IDX,
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};
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hw->func_out_sel_cfg[gpio_num].val = reg.val;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
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}
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/**
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@ -553,7 +551,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
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{
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gpio_func_in_sel_cfg_reg_t reg;
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reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
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return (reg.sig_in_sel ? reg.func_sel : -1);
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return (reg.sig_in_sel ? reg.in_sel : -1);
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}
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/**
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@ -23,6 +23,7 @@
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#include "soc/usb_serial_jtag_reg.h"
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#include "hal/gpio_types.h"
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#include "hal/assert.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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@ -544,7 +545,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
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{
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typeof(hw->func_in_sel_cfg[in_sig_idx]) reg;
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reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
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return (reg.sig_in_sel ? reg.func_sel : -1);
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return (reg.sig_in_sel ? reg.in_sel : -1);
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}
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/**
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@ -766,7 +767,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
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*od = hw->pin[gpio_num].pad_driver;
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gpio_ll_get_drive_capability(hw, gpio_num, (gpio_drive_cap_t *)drv); // specific workaround in the LL
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*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
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*sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
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*sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
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*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
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}
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@ -27,7 +27,6 @@
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#include "soc/usb_serial_jtag_struct.h"
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#include "hal/gpio_types.h"
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#include "hal/assert.h"
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#include "soc/lp_gpio_struct.h"
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#ifdef __cplusplus
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extern "C" {
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@ -115,7 +115,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
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*/
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static inline void rtcio_ll_output_enable(int rtcio_num)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, enable_w1ts, BIT(rtcio_num));
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, out_enable_w1ts, BIT(rtcio_num));
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}
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/**
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@ -125,7 +125,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num)
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*/
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static inline void rtcio_ll_output_disable(int rtcio_num)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, enable_w1tc, BIT(rtcio_num));
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, out_enable_w1tc, BIT(rtcio_num));
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}
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/**
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@ -137,9 +137,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
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static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
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{
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if (level) {
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_w1ts, BIT(rtcio_num));
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, out_data_w1ts, BIT(rtcio_num));
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} else {
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_w1tc, BIT(rtcio_num));
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, out_data_w1tc, BIT(rtcio_num));
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}
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}
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@ -357,7 +357,7 @@ static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type
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LP_GPIO.pinn[rtcio_num].pinn_int_type = type;
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/* Work around for HW issue,
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need to also enable this clk, so that LP_GPIO.status.status_interrupt can get updated,
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need to also enable this clk, so that (LP_GPIO.status, status_interrupt) can get updated,
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and trigger the interrupt on the LP Core
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*/
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LP_GPIO.clock_gate.clk_en = 1;
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@ -450,7 +450,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
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*/
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static inline void rtcio_ll_clear_interrupt_status(void)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_w1tc, 0xff);
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, status_intr_w1tc, 0xff);
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}
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#ifdef __cplusplus
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@ -20,13 +20,13 @@
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#include "soc/gpio_periph.h"
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#include "soc/gpio_struct.h"
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#include "soc/lp_aon_struct.h"
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#include "soc/lp_io_struct.h"
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#include "soc/pmu_struct.h"
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#include "soc/usb_serial_jtag_reg.h"
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#include "soc/pcr_struct.h"
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#include "soc/clk_tree_defs.h"
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#include "hal/gpio_types.h"
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#include "hal/assert.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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@ -66,7 +66,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
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*od = hw->pin[gpio_num].pad_driver;
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*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
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*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
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*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
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*sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
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*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
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}
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@ -315,10 +315,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, uint32_t gpio_num)
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__attribute__((always_inline))
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static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
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{
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gpio_func_out_sel_cfg_reg_t reg = {
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.out_sel = SIG_GPIO_OUT_IDX,
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};
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hw->func_out_sel_cfg[gpio_num].val = reg.val;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
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}
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/**
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@ -136,9 +136,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num)
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static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level)
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{
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if (level) {
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_data_w1ts, BIT(rtcio_num));
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_w1ts, BIT(rtcio_num));
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} else {
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_data_w1tc, BIT(rtcio_num));
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_w1tc, BIT(rtcio_num));
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}
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}
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@ -364,7 +364,7 @@ static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type
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LP_IO.pin[rtcio_num].int_type = type;
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/* Work around for HW issue,
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need to also enable this clk, so that LP_IO.status.status_interrupt can get updated,
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need to also enable this clk, so that (LP_IO.status, status_interrupt) can get updated,
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and trigger the interrupt on the LP Core
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*/
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LP_IO.date.clk_en = 1;
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@ -457,7 +457,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void)
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*/
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static inline void rtcio_ll_clear_interrupt_status(void)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_w1tc, 0xff);
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_intr_w1tc, 0xff);
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}
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#ifdef __cplusplus
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@ -66,7 +66,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
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*od = hw->pin[gpio_num].pad_driver;
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*drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
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*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
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*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
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*sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
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*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
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}
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@ -360,10 +360,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
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__attribute__((always_inline))
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static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
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{
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gpio_func_out_sel_cfg_reg_t reg = {
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.out_sel = SIG_GPIO_OUT_IDX,
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};
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hw->func_out_sel_cfg[gpio_num].val = reg.val;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
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}
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/**
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@ -285,7 +285,9 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
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uint64_t bit_mask = 1ULL << gpio_num;
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if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
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// GPIO0-15
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LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys |= bit_mask;
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uint32_t hys_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys);
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hys_mask |= bit_mask;
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys, hys_mask);
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} else {
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if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
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// GPIO 16-47
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@ -308,7 +310,9 @@ static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t
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uint64_t bit_mask = 1ULL << gpio_num;
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if (!(bit_mask & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK)) {
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// GPIO0-15
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LP_IOMUX.lp_pad_hys.reg_lp_gpio_hys &= ~bit_mask;
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uint32_t hys_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys);
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hys_mask &= ~bit_mask;
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IOMUX.lp_pad_hys, reg_lp_gpio_hys, hys_mask);
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} else {
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if (gpio_num < 32 + SOC_RTCIO_PIN_COUNT) {
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// GPIO 16-47
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@ -18,7 +18,6 @@
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#include "soc/soc.h"
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#include "soc/gpio_periph.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/rtc_io_reg.h"
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#include "soc/gpio_struct.h"
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#include "hal/gpio_types.h"
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#include "hal/assert.h"
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@ -18,7 +18,6 @@
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#include "soc/soc.h"
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#include "soc/gpio_periph.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/rtc_io_reg.h"
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#include "soc/usb_serial_jtag_reg.h"
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#include "hal/gpio_types.h"
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#include "soc/gpio_struct.h"
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@ -301,7 +301,7 @@ typedef union {
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* set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always
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* high level. s=0x3C: set this port always low level.
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*/
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uint32_t func_sel:5;
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uint32_t in_sel:5;
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/** in_inv_sel : R/W; bitpos: [5]; default: 0;
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* set this bit to invert input signal. 1:invert. 0:not invert.
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*/
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@ -325,7 +325,7 @@ typedef union {
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* output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
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* GPIO_OUT_REG[n].
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*/
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uint32_t func_sel:8;
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uint32_t out_sel:8;
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/** out_inv_sel : R/W; bitpos: [8]; default: 0;
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* set this bit to invert output signal.1:invert.0:not invert.
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*/
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@ -182,7 +182,7 @@ typedef volatile struct gpio_dev_s {
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uint32_t reserved_150;
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union {
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struct {
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uint32_t func_sel: 5;
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uint32_t in_sel: 5;
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uint32_t sig_in_inv: 1;
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uint32_t sig_in_sel: 1;
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uint32_t reserved7: 25;
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@ -319,7 +319,7 @@ typedef volatile struct gpio_dev_s {
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uint32_t reserved_550;
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union {
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struct {
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uint32_t func_sel: 8;
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uint32_t out_sel: 8;
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uint32_t inv_sel: 1;
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uint32_t oen_sel: 1;
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uint32_t oen_inv_sel: 1;
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@ -33,7 +33,7 @@ typedef union {
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*/
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typedef union {
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struct {
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/** out_w1ts : WT; bitpos: [7:0]; default: 0;
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/** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
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* Configures whether or not to enable the output register LP_IO_OUT_REG of GPIO0 ~
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* GPIO7.\\
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*
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@ -42,7 +42,7 @@ typedef union {
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* will be set to 1.
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* - Recommended operation: use this register to set LP_IO_OUT_REG.
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*/
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uint32_t out_w1ts:8;
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uint32_t out_data_w1ts:8;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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@ -53,7 +53,7 @@ typedef union {
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*/
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typedef union {
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struct {
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/** out_w1tc : WT; bitpos: [7:0]; default: 0;
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/** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
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* Configures whether or not to clear the output register LP_IO_OUT_REG of GPIO0 ~
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* GPIO7.\\
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*
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@ -62,7 +62,7 @@ typedef union {
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* will be cleared.
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* - Recommended operation: use this register to clear LP_IO_OUT_REG.
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*/
|
||||
uint32_t out_w1tc:8;
|
||||
uint32_t out_data_w1tc:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -90,7 +90,7 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** enable_w1ts : WT; bitpos: [7:0]; default: 0;
|
||||
/** out_enable_w1ts : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures whether or not to set the output enable register LP_IO_ENABLE_REG of
|
||||
* GPIO0 ~ GPIO7.\\
|
||||
*
|
||||
@ -99,7 +99,7 @@ typedef union {
|
||||
* LP_IO_ENABLE_REG will be set to 1.
|
||||
* - Recommended operation: use this register to set LP_IO_ENABLE_REG.
|
||||
*/
|
||||
uint32_t enable_w1ts:8;
|
||||
uint32_t out_enable_w1ts:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -110,7 +110,7 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** enable_w1tc : WT; bitpos: [7:0]; default: 0;
|
||||
/** out_enable_w1tc : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures whether or not to clear the output enable register LP_IO_ENABLE_REG of
|
||||
* GPIO0 ~ GPIO7.\\
|
||||
*
|
||||
@ -119,7 +119,7 @@ typedef union {
|
||||
* LP_IO_ENABLE_REG will be cleared.
|
||||
* - Recommended operation: use this register to clear LP_IO_ENABLE_REG.
|
||||
*/
|
||||
uint32_t enable_w1tc:8;
|
||||
uint32_t out_enable_w1tc:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -165,7 +165,7 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** status_w1ts : WT; bitpos: [7:0]; default: 0;
|
||||
/** status_intr_w1ts : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures whether or not to set the interrupt status register LP_IO_STATUS_INT of
|
||||
* GPIO0 ~ GPIO7.\\
|
||||
*
|
||||
@ -174,7 +174,7 @@ typedef union {
|
||||
* LP_IO_STATUS_INT will be set to 1.
|
||||
* - Recommended operation: use this register to set LP_IO_STATUS_INT.
|
||||
*/
|
||||
uint32_t status_w1ts:8;
|
||||
uint32_t status_intr_w1ts:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -185,7 +185,7 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** status_w1tc : WT; bitpos: [7:0]; default: 0;
|
||||
/** status_intr_w1tc : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures whether or not to clear the interrupt status register LP_IO_STATUS_INT
|
||||
* of GPIO0 ~ GPIO7. \\
|
||||
*
|
||||
@ -194,7 +194,7 @@ typedef union {
|
||||
* LP_IO_STATUS_INT will be cleared
|
||||
* - ecommended operation: use this register to clear LP_IO_STATUS_INT.
|
||||
*/
|
||||
uint32_t status_w1tc:8;
|
||||
uint32_t status_intr_w1tc:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
|
@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -30,10 +30,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** out_data_w1ts : WT; bitpos: [7:0]; default: 0;
|
||||
/** out_w1ts : WT; bitpos: [7:0]; default: 0;
|
||||
* set one time output data
|
||||
*/
|
||||
uint32_t out_data_w1ts:8;
|
||||
uint32_t out_w1ts:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -44,10 +44,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** out_data_w1tc : WT; bitpos: [7:0]; default: 0;
|
||||
/** out_w1tc : WT; bitpos: [7:0]; default: 0;
|
||||
* clear one time output data
|
||||
*/
|
||||
uint32_t out_data_w1tc:8;
|
||||
uint32_t out_w1tc:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -114,10 +114,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** status_w1ts : WT; bitpos: [7:0]; default: 0;
|
||||
/** status_intr_w1ts : WT; bitpos: [7:0]; default: 0;
|
||||
* set one time output data
|
||||
*/
|
||||
uint32_t status_w1ts:8;
|
||||
uint32_t status_intr_w1ts:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -128,10 +128,10 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** status_w1tc : WT; bitpos: [7:0]; default: 0;
|
||||
/** status_intr_w1tc : WT; bitpos: [7:0]; default: 0;
|
||||
* clear one time output data
|
||||
*/
|
||||
uint32_t status_w1tc:8;
|
||||
uint32_t status_intr_w1tc:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
|
Reference in New Issue
Block a user