From f1d1dfd1ef36d25a67dc441a4d98778c833cbbb4 Mon Sep 17 00:00:00 2001 From: "chaijie@espressif.com" Date: Tue, 7 May 2024 18:10:09 +0800 Subject: [PATCH 1/2] feat(esp32p4_eco1): modify cpll and spll config --- .../src/esp32p4/bootloader_esp32p4.c | 17 +++--- .../esp_hw_support/port/esp32p4/pmu_sleep.c | 8 ++- .../hal/esp32p4/include/hal/clk_tree_ll.h | 52 ++++++++++++++----- 3 files changed, 55 insertions(+), 22 deletions(-) diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c index 544fcd1ad4..c26c83381e 100644 --- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c +++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c @@ -91,13 +91,16 @@ static inline void bootloader_hardware_init(void) { // regi2c is enabled by default on ESP32P4, do nothing - // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader - // And we are fixing SPLL to be 480MHz at all runtime - // Suppose to fix the issue on ECO1, will check when chip comes back - // TODO: IDF-8939 - REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M - REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M - esp_rom_delay_us(100); + unsigned chip_version = efuse_hal_chip_revision(); + if (chip_version == 0) { + // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader + // And we are fixing SPLL to be 480MHz at all runtime + // Suppose to fix the issue on ECO1, will check when chip comes back + // TODO: IDF-8939 + REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M + REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M + esp_rom_delay_us(100); + } REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10); REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10); } diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c index 919197fb48..391d80597d 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c @@ -27,6 +27,7 @@ #include "pmu_param.h" #include "esp_rom_sys.h" #include "esp_rom_uart.h" +#include "hal/efuse_hal.h" #define HP(state) (PMU_MODE_HP_ ## state) #define LP(state) (PMU_MODE_LP_ ## state) @@ -317,8 +318,11 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(void) } pmu_sleep_shutdown_ldo(); - REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M - REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M + unsigned chip_version = efuse_hal_chip_revision(); + if (chip_version == 0) { + REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M + REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M + } return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev); } diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h index f504917fe7..0e65f9e6b6 100644 --- a/components/hal/esp32p4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h @@ -22,6 +22,7 @@ #include "hal/log.h" #include "esp32p4/rom/rtc.h" #include "hal/misc.h" +#include "hal/efuse_hal.h" #ifdef __cplusplus extern "C" { @@ -309,7 +310,13 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(u { uint8_t div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0); uint8_t ref_div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_REF_DIV); - return xtal_freq_mhz * (div + 4) / (ref_div + 1); +#if !ESP_CHIP_REV_ABOVE(ESP_HAL_CHIP_REV_MIN, 1) + unsigned chip_version = efuse_hal_chip_revision(); + if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) { + return xtal_freq_mhz * (div + 4) / (ref_div + 1); + } else +#endif + return xtal_freq_mhz * div / (ref_div + 1); } /** @@ -336,22 +343,41 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_ uint8_t dchgp = 5; uint8_t dcur = 3; uint8_t oc_enb_fcal = 0; + unsigned chip_version = efuse_hal_chip_revision(); // Currently, only supporting 40MHz XTAL HAL_ASSERT(xtal_freq_mhz == SOC_XTAL_FREQ_40M); - switch (cpll_freq_mhz) { - case CLK_LL_PLL_400M_FREQ_MHZ: - /* Configure 400M CPLL */ - div7_0 = 6; - div_ref = 0; - break; - case CLK_LL_PLL_360M_FREQ_MHZ: - default: - /* Configure 360M CPLL */ - div7_0 = 5; - div_ref = 0; - break; + if (chip_version == 0) { + switch (cpll_freq_mhz) { + case CLK_LL_PLL_400M_FREQ_MHZ: + /* Configure 400M CPLL */ + div7_0 = 6; + div_ref = 0; + break; + case CLK_LL_PLL_360M_FREQ_MHZ: + default: + /* Configure 360M CPLL */ + div7_0 = 5; + div_ref = 0; + break; + } + } else { + /*div7_0 bit2 & bit3 will swap from ECO1*/ + switch (cpll_freq_mhz) { + case CLK_LL_PLL_400M_FREQ_MHZ: + /* Configure 400M CPLL */ + div7_0 = 10; + div_ref = 0; + break; + case CLK_LL_PLL_360M_FREQ_MHZ: + default: + /* Configure 360M CPLL */ + div7_0 = 9; + div_ref = 0; + break; + } } + uint8_t i2c_cpll_lref = (oc_enb_fcal << I2C_CPLL_OC_ENB_FCAL_LSB) | (dchgp << I2C_CPLL_OC_DCHGP_LSB) | (div_ref); uint8_t i2c_cpll_div_7_0 = div7_0; uint8_t i2c_cpll_dcur = (1 << I2C_CPLL_OC_DLREF_SEL_LSB ) | (3 << I2C_CPLL_OC_DHREF_SEL_LSB) | dcur; From cbcd3461712158a71accc3b98aa90a0c7e2bfb37 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Thu, 9 May 2024 17:04:45 +0800 Subject: [PATCH 2/2] feat(esp32p4): add eco1 revision config option --- .../src/esp32p4/bootloader_esp32p4.c | 12 +++++------- .../esp_hw_support/port/esp32p4/Kconfig.hw_support | 3 +++ components/esp_hw_support/port/esp32p4/pmu_sleep.c | 3 ++- components/hal/esp32p4/include/hal/clk_tree_ll.h | 11 ++++++----- 4 files changed, 16 insertions(+), 13 deletions(-) diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c index c26c83381e..f04a921698 100644 --- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c +++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -29,6 +29,7 @@ #include "bootloader_flash_config.h" #include "bootloader_mem.h" #include "esp_private/regi2c_ctrl.h" +#include "soc/chip_revision.h" #include "soc/regi2c_lp_bias.h" #include "soc/regi2c_bias.h" #include "bootloader_console.h" @@ -90,13 +91,10 @@ static void bootloader_super_wdt_auto_feed(void) static inline void bootloader_hardware_init(void) { // regi2c is enabled by default on ESP32P4, do nothing - unsigned chip_version = efuse_hal_chip_revision(); - if (chip_version == 0) { + if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) { // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader - // And we are fixing SPLL to be 480MHz at all runtime - // Suppose to fix the issue on ECO1, will check when chip comes back - // TODO: IDF-8939 + // And we are fixing SPLL to be 480MHz after app is up REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M esp_rom_delay_us(100); @@ -173,7 +171,7 @@ esp_err_t bootloader_init(void) } #endif // !CONFIG_APP_BUILD_TYPE_RAM - // check whether a WDT reset happend + // check whether a WDT reset happened bootloader_check_wdt_reset(); // config WDT bootloader_config_wdt(); diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support index a7c2840267..49b77c0ccf 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support @@ -11,11 +11,14 @@ choice ESP32P4_REV_MIN config ESP32P4_REV_MIN_0 bool "Rev v0.0" + config ESP32P4_REV_MIN_1 + bool "Rev v0.1" endchoice config ESP32P4_REV_MIN_FULL int default 0 if ESP32P4_REV_MIN_0 + default 1 if ESP32P4_REV_MIN_1 config ESP_REV_MIN_FULL int diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c index 391d80597d..ca93907ae5 100644 --- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c @@ -12,6 +12,7 @@ #include "esp_err.h" #include "esp_attr.h" #include "esp_private/regi2c_ctrl.h" +#include "soc/chip_revision.h" #include "soc/soc.h" #include "soc/regi2c_syspll.h" #include "soc/regi2c_cpll.h" @@ -319,7 +320,7 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(void) pmu_sleep_shutdown_ldo(); unsigned chip_version = efuse_hal_chip_revision(); - if (chip_version == 0) { + if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) { REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M } diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h index 0e65f9e6b6..1dd5efd021 100644 --- a/components/hal/esp32p4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h @@ -9,6 +9,7 @@ #include #include "soc/clkout_channel.h" #include "soc/soc.h" +#include "soc/chip_revision.h" #include "soc/clk_tree_defs.h" #include "soc/hp_sys_clkrst_reg.h" #include "soc/hp_sys_clkrst_struct.h" @@ -24,6 +25,7 @@ #include "hal/misc.h" #include "hal/efuse_hal.h" + #ifdef __cplusplus extern "C" { #endif @@ -310,12 +312,10 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(u { uint8_t div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0); uint8_t ref_div = REGI2C_READ_MASK(I2C_CPLL, I2C_CPLL_OC_REF_DIV); -#if !ESP_CHIP_REV_ABOVE(ESP_HAL_CHIP_REV_MIN, 1) unsigned chip_version = efuse_hal_chip_revision(); if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) { return xtal_freq_mhz * (div + 4) / (ref_div + 1); } else -#endif return xtal_freq_mhz * div / (ref_div + 1); } @@ -343,11 +343,12 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_ uint8_t dchgp = 5; uint8_t dcur = 3; uint8_t oc_enb_fcal = 0; - unsigned chip_version = efuse_hal_chip_revision(); // Currently, only supporting 40MHz XTAL HAL_ASSERT(xtal_freq_mhz == SOC_XTAL_FREQ_40M); - if (chip_version == 0) { + + unsigned chip_version = efuse_hal_chip_revision(); + if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) { switch (cpll_freq_mhz) { case CLK_LL_PLL_400M_FREQ_MHZ: /* Configure 400M CPLL */ @@ -362,7 +363,7 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_set_config(uint32_ break; } } else { - /*div7_0 bit2 & bit3 will swap from ECO1*/ + /*div7_0 bit2 & bit3 is swapped from ECO1*/ switch (cpll_freq_mhz) { case CLK_LL_PLL_400M_FREQ_MHZ: /* Configure 400M CPLL */