mirror of
https://github.com/espressif/esp-idf.git
synced 2025-12-01 06:39:27 +01:00
spi_slave_hd: new driver for spi slave in half duplex mode
This commit is contained in:
Michael (XIAO Xufeng)
@@ -28,6 +28,7 @@
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#include "esp_types.h"
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#include "soc/spi_periph.h"
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#include "esp32s2/rom/lldesc.h"
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#include "esp_attr.h"
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#ifdef __cplusplus
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extern "C" {
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@@ -64,6 +65,34 @@ typedef enum {
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SPI_LL_INT_TYPE_SEG = 1, ///< Wait for DMA signals
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} spi_ll_slave_intr_type;
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/// Type definition of all supported interrupts
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typedef enum {
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SPI_LL_INTR_TRANS_DONE = BIT(0), ///< A transaction has done
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SPI_LL_INTR_IN_SUC_EOF = BIT(1), ///< DMA in_suc_eof triggered
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SPI_LL_INTR_OUT_EOF = BIT(2), ///< DMA out_eof triggered
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SPI_LL_INTR_OUT_TOTAL_EOF = BIT(3), ///< DMA out_total_eof triggered
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SPI_LL_INTR_IN_FULL = BIT(4), ///< DMA in_full error happened
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SPI_LL_INTR_OUT_EMPTY = BIT(5), ///< DMA out_empty error happened
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SPI_LL_INTR_RDBUF = BIT(6), ///< Has received RDBUF command. Only available in slave HD.
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SPI_LL_INTR_WRBUF = BIT(7), ///< Has received WRBUF command. Only available in slave HD.
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SPI_LL_INTR_RDDMA = BIT(8), ///< Has received RDDMA command. Only available in slave HD.
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SPI_LL_INTR_WRDMA = BIT(9), ///< Has received WRDMA command. Only available in slave HD.
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SPI_LL_INTR_WR_DONE = BIT(10), ///< Has received WR_DONE command. Only available in slave HD.
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SPI_LL_INTR_CMD8 = BIT(11), ///< Has received CMD8 command. Only available in slave HD.
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SPI_LL_INTR_CMD9 = BIT(12), ///< Has received CMD9 command. Only available in slave HD.
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SPI_LL_INTR_CMDA = BIT(13), ///< Has received CMDA command. Only available in slave HD.
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SPI_LL_INTR_SEG_DONE = BIT(14),
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} spi_ll_intr_t;
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FLAG_ATTR(spi_ll_intr_t)
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///< Flags for conditions under which the transaction length should be recorded
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typedef enum {
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SPI_LL_TRANS_LEN_COND_WRBUF = BIT(0), ///< WRBUF length will be recorded
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SPI_LL_TRANS_LEN_COND_RDBUF = BIT(1), ///< RDBUF length will be recorded
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SPI_LL_TRANS_LEN_COND_WRDMA = BIT(2), ///< WRDMA length will be recorded
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SPI_LL_TRANS_LEN_COND_RDDMA = BIT(3), ///< RDDMA length will be recorded
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} spi_ll_trans_len_cond_t;
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FLAG_ATTR(spi_ll_trans_len_cond_t)
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/*------------------------------------------------------------------------------
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* Control
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@@ -125,6 +154,76 @@ static inline void spi_ll_slave_init(spi_dev_t *hw)
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hw->dma_int_ena.val = 0;
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}
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static inline void spi_ll_slave_hd_init(spi_dev_t* hw)
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{
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hw->clock.val = 0;
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hw->user.val = 0;
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hw->ctrl.val = 0;
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hw->user.sio = 0;
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//hw->user.tx_start_bit = 7;
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hw->slave.soft_reset = 1;
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hw->slave.soft_reset = 0;
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//Reset DMA
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hw->dma_conf.val |= SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST;
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hw->dma_out_link.start = 0;
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hw->dma_in_link.start = 0;
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hw->dma_conf.val &= ~(SPI_OUT_RST | SPI_IN_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST);
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if (hw == &GPSPI2) {
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hw->dma_conf.out_data_burst_en = 1;
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} else {
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hw->dma_conf.out_data_burst_en = 0;
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}
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hw->dma_conf.outdscr_burst_en = 1;
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hw->dma_conf.indscr_burst_en = 1;
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hw->dma_conf.rx_eof_en = 0;
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hw->dma_conf.out_eof_mode = 1;
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hw->dma_conf.out_auto_wrback = 1;
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hw->user.doutdin = 0; //we only support full duplex
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hw->slave.slave_mode = 1;
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}
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/**
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* Check whether user-defined transaction is done.
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*
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* @param hw Beginning address of the peripheral registers.
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*
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* @return true if transaction is done, otherwise false.
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*/
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static inline bool spi_ll_usr_is_done(spi_dev_t *hw)
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{
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return hw->slave.trans_done;
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}
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/**
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* Trigger start of user-defined transaction.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_user_start(spi_dev_t *hw)
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{
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hw->cmd.usr = 1;
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}
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/**
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* Get current running command bit-mask. (Preview)
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*
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* @param hw Beginning address of the peripheral registers.
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*
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* @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command.
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*/
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static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw)
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{
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return hw->cmd.val;
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}
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/*------------------------------------------------------------------------------
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* DMA
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*----------------------------------------------------------------------------*/
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/**
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* Reset TX and RX DMAs.
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*
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@@ -168,6 +267,62 @@ static inline void spi_ll_txdma_start(spi_dev_t *hw, lldesc_t *addr)
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hw->dma_out_link.start = 1;
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}
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static inline void spi_ll_rxdma_reset(spi_dev_t* hw)
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{
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hw->dma_conf.in_rst = 1;
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hw->dma_conf.in_rst = 0;
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hw->dma_conf.infifo_full_clr = 1;
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hw->dma_conf.infifo_full_clr = 0;
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}
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static inline void spi_ll_txdma_reset(spi_dev_t* hw)
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{
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hw->dma_conf.out_rst = 1;
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hw->dma_conf.out_rst = 0;
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hw->dma_conf.outfifo_empty_clr = 1;
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hw->dma_conf.outfifo_empty_clr = 0;
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}
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static inline void spi_ll_rxdma_restart(spi_dev_t* hw)
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{
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hw->dma_in_link.restart = 1;
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}
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static inline void spi_ll_txdma_restart(spi_dev_t* hw)
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{
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hw->dma_out_link.restart = 1;
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}
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static inline void spi_ll_rxdma_disable(spi_dev_t* hw)
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{
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hw->dma_in_link.dma_rx_ena = 0;
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}
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static inline void spi_ll_txdma_disable(spi_dev_t* hw)
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{
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hw->dma_out_link.dma_tx_ena = 0;
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hw->dma_out_link.stop = 1;
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}
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static inline void spi_ll_rxdma_clr_err(spi_dev_t* hw)
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{
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hw->dma_conf.infifo_full_clr = 1;
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hw->dma_conf.infifo_full_clr = 0;
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}
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static inline void spi_ll_txdma_clr_err(spi_dev_t* hw)
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{
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hw->dma_int_clr.outfifo_empty_err= 1;
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}
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static inline bool spi_ll_txdma_get_empty_err(spi_dev_t* hw)
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{
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return hw->dma_int_raw.outfifo_empty_err;
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}
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/*------------------------------------------------------------------------------
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* Buffer
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*----------------------------------------------------------------------------*/
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/**
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* Write to SPI buffer.
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*
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@@ -205,99 +360,43 @@ static inline void spi_ll_read_buffer(spi_dev_t *hw, uint8_t *buffer_to_rcv, siz
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}
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}
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/**
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* Check whether user-defined transaction is done.
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*
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* @param hw Beginning address of the peripheral registers.
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*
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* @return true if transaction is done, otherwise false.
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*/
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static inline bool spi_ll_usr_is_done(spi_dev_t *hw)
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static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_addr, uint8_t *out_data, int len)
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{
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return hw->slave.trans_done;
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while (len>0) {
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uint32_t word = hw->data_buf[byte_addr/4];
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int offset = byte_addr % 4;
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int copy_len = 4 - offset;
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if (copy_len > len) copy_len = len;
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memcpy(out_data, ((uint8_t*)&word)+offset, copy_len);
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byte_addr += copy_len;
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out_data += copy_len;
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len -= copy_len;
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}
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}
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/**
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* Trigger start of user-defined transaction.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_user_start(spi_dev_t *hw)
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static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_addr, uint8_t *data, int len)
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{
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hw->cmd.usr = 1;
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}
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assert( byte_addr + len <= 72);
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assert(len > 0);
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assert(byte_addr >= 0);
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/**
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* Get current running command bit-mask. (Preview)
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*
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* @param hw Beginning address of the peripheral registers.
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*
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* @return Bitmask of running command, see ``SPI_CMD_REG``. 0 if no in-flight command.
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*/
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static inline uint32_t spi_ll_get_running_cmd(spi_dev_t *hw)
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{
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return hw->cmd.val;
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}
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while (len > 0) {
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uint32_t word;
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int offset = byte_addr % 4;
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/**
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* Disable the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_disable_int(spi_dev_t *hw)
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{
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hw->slave.int_trans_done_en = 0;
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}
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int copy_len = 4 - offset;
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if (copy_len > len) copy_len = len;
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/**
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* Clear the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
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{
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hw->slave.trans_done = 0;
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hw->dma_int_clr.val = UINT32_MAX;
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}
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//read-modify-write
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if (copy_len != 4) word = hw->data_buf[byte_addr / 4];
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/**
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* Set the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_set_int_stat(spi_dev_t *hw)
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{
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hw->slave.trans_done = 1;
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}
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/**
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* Enable the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_enable_int(spi_dev_t *hw)
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{
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hw->slave.int_trans_done_en = 1;
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}
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/**
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* Set different interrupt types for the slave.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param int_type Interrupt type
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*/
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static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_type int_type)
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{
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switch (int_type) {
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case SPI_LL_INT_TYPE_SEG:
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hw->dma_int_ena.in_suc_eof = 1;
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hw->dma_int_ena.out_total_eof = 1;
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hw->slave.int_trans_done_en = 0;
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break;
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default:
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hw->dma_int_ena.in_suc_eof = 0;
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hw->dma_int_ena.out_total_eof = 0;
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hw->slave.int_trans_done_en = 1;
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memcpy(((uint8_t *)&word) + offset, data, copy_len);
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hw->data_buf[byte_addr / 4] = word;
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data += copy_len;
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byte_addr += copy_len;
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len -= copy_len;
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}
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}
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@@ -460,6 +559,12 @@ static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_
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}
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}
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static inline void spi_ll_slave_set_seg_mode(spi_dev_t* hw, bool seg_trans)
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{
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hw->dma_conf.dma_seg_trans_en = seg_trans;
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hw->dma_conf.rx_eof_en = seg_trans;
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}
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/**
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* Select one of the CS to use in current transaction.
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*
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@@ -859,7 +964,150 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
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return hw->slv_rd_byte.data_bytelen * 8;
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}
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/*------------------------------------------------------------------------------
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* Interrupts
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*----------------------------------------------------------------------------*/
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//helper macros to generate code for each interrupts
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#define FOR_EACH_ITEM(op, list) do { list(op) } while(0)
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#define INTR_LIST(item) \
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item(SPI_LL_INTR_TRANS_DONE, slave.int_trans_done_en, slave.trans_done, slave.trans_done=0) \
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item(SPI_LL_INTR_RDBUF, slave.int_rd_buf_done_en, slv_rdbuf_dlen.rd_buf_done, slv_rdbuf_dlen.rd_buf_done=0) \
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item(SPI_LL_INTR_WRBUF, slave.int_wr_buf_done_en, slv_wrbuf_dlen.wr_buf_done, slv_wrbuf_dlen.wr_buf_done=0) \
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item(SPI_LL_INTR_RDDMA, slave.int_rd_dma_done_en, slv_rd_byte.rd_dma_done, slv_rd_byte.rd_dma_done=0) \
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item(SPI_LL_INTR_WRDMA, slave.int_wr_dma_done_en, slave1.wr_dma_done, slave1.wr_dma_done=0) \
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item(SPI_LL_INTR_IN_SUC_EOF, dma_int_ena.in_suc_eof, dma_int_raw.in_suc_eof, dma_int_clr.in_suc_eof=1) \
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item(SPI_LL_INTR_OUT_EOF, dma_int_ena.out_eof, dma_int_raw.out_eof, dma_int_clr.out_eof=1) \
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item(SPI_LL_INTR_OUT_TOTAL_EOF, dma_int_ena.out_total_eof, dma_int_raw.out_total_eof, dma_int_clr.out_total_eof=1) \
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item(SPI_LL_INTR_SEG_DONE, slave.int_dma_seg_trans_en, hold.dma_seg_trans_done, hold.dma_seg_trans_done=0) \
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item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err, dma_int_raw.infifo_full_err, dma_int_clr.infifo_full_err=1) \
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item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err, dma_int_raw.outfifo_empty_err, dma_int_clr.outfifo_empty_err=1) \
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item(SPI_LL_INTR_WR_DONE, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \
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item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8=1) \
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item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9=1) \
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item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda=1)
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static inline void spi_ll_enable_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask)
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{
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#define ENA_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 1;
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FOR_EACH_ITEM(ENA_INTR, INTR_LIST);
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#undef ENA_INTR
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}
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static inline void spi_ll_disable_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask)
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{
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#define DIS_INTR(intr_bit, en_reg, ...) if (intr_mask & (intr_bit)) hw->en_reg = 0;
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FOR_EACH_ITEM(DIS_INTR, INTR_LIST);
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#undef DIS_INTR
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}
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static inline void spi_ll_set_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask)
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{
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#define SET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit)) hw->st_reg = 1;
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FOR_EACH_ITEM(SET_INTR, INTR_LIST);
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#undef SET_INTR
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}
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static inline void spi_ll_clear_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask)
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{
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#define CLR_INTR(intr_bit, _, __, clr_op) if (intr_mask & (intr_bit)) hw->clr_op;
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FOR_EACH_ITEM(CLR_INTR, INTR_LIST);
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#undef CLR_INTR
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}
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static inline bool spi_ll_get_intr(spi_dev_t* hw, spi_ll_intr_t intr_mask)
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{
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#define GET_INTR(intr_bit, _, st_reg, ...) if (intr_mask & (intr_bit) && hw->st_reg) return true;
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FOR_EACH_ITEM(GET_INTR, INTR_LIST);
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return false;
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#undef GET_INTR
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}
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#undef FOR_EACH_ITEM
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#undef INTR_LIST
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/**
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* Disable the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_disable_int(spi_dev_t *hw)
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{
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hw->slave.int_trans_done_en = 0;
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}
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/**
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* Clear the trans_done interrupt.
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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static inline void spi_ll_clear_int_stat(spi_dev_t *hw)
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{
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hw->slave.trans_done = 0;
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hw->dma_int_clr.val = UINT32_MAX;
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}
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/**
|
||||
* Set the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_set_int_stat(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.trans_done = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable the trans_done interrupt.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
*/
|
||||
static inline void spi_ll_enable_int(spi_dev_t *hw)
|
||||
{
|
||||
hw->slave.int_trans_done_en = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set different interrupt types for the slave.
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers.
|
||||
* @param int_type Interrupt type
|
||||
*/
|
||||
static inline void spi_ll_slave_set_int_type(spi_dev_t *hw, spi_ll_slave_intr_type int_type)
|
||||
{
|
||||
switch (int_type) {
|
||||
case SPI_LL_INT_TYPE_SEG:
|
||||
hw->dma_int_ena.in_suc_eof = 1;
|
||||
hw->dma_int_ena.out_total_eof = 1;
|
||||
hw->slave.int_trans_done_en = 0;
|
||||
break;
|
||||
default:
|
||||
hw->dma_int_ena.in_suc_eof = 0;
|
||||
hw->dma_int_ena.out_total_eof = 0;
|
||||
hw->slave.int_trans_done_en = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Slave HD
|
||||
*----------------------------------------------------------------------------*/
|
||||
static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t* hw, spi_ll_trans_len_cond_t cond_mask)
|
||||
{
|
||||
hw->slv_rd_byte.rdbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0;
|
||||
hw->slv_rd_byte.wrbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0;
|
||||
hw->slv_rd_byte.rddma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0;
|
||||
hw->slv_rd_byte.wrdma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t* hw)
|
||||
{
|
||||
return hw->slv_rd_byte.data_bytelen;
|
||||
}
|
||||
|
||||
static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t* hw)
|
||||
{
|
||||
return hw->slave1.last_addr;
|
||||
}
|
||||
#undef SPI_LL_RST_MASK
|
||||
#undef SPI_LL_UNUSED_INT_MASK
|
||||
|
||||
|
||||
Reference in New Issue
Block a user