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fix(esp32c5): add CLIC interrupt controller support for the ESP32-C5

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This commit is contained in:
Omar Chebib
2024-02-27 12:29:13 +08:00
parent 46e0760619
commit f6e935e013
15 changed files with 658 additions and 629 deletions
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281
components/soc/esp32c5/beta3/include/soc/interrupt_matrix_reg.h
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@@ -1,12 +1,11 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -395,34 +394,22 @@ extern "C" {
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
* GPIO_INTERRUPT_PRO_NMI mapping register
/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG register
* GPIO_INTERRUPT_EXT mapping register
*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
/** INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_REG register
* GPIO_INTERRUPT_SD mapping register
*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
/** INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_S 0
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S 0
/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register
* PAU_INTR mapping register
*/
#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -434,7 +421,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
* HP_PERI_TIMEOUT_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -446,7 +433,7 @@ extern "C" {
/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
* MODEM_PERI_TIMEOUT_INTR mapping register
*/
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -458,7 +445,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register
* HP_APM_M0_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -470,7 +457,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register
* HP_APM_M1_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -482,7 +469,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register
* HP_APM_M2_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -494,7 +481,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register
* HP_APM_M3_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -503,6 +490,18 @@ extern "C" {
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0
/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register
* HP_APM_M4_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S 0
/** INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG register
* LP_APM0_INTR mapping register
*/
@@ -527,17 +526,17 @@ extern "C" {
#define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0
/** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register
* I2S1_INTR mapping register
/** INTERRUPT_CORE0_I2S_INTR_MAP_REG register
* I2S_INTR mapping register
*/
#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
/** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
/** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_I2S1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_I2S1_INTR_MAP_M (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S)
#define INTERRUPT_CORE0_I2S1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_I2S1_INTR_MAP_S 0
#define INTERRUPT_CORE0_I2S_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_I2S_INTR_MAP_M (INTERRUPT_CORE0_I2S_INTR_MAP_V << INTERRUPT_CORE0_I2S_INTR_MAP_S)
#define INTERRUPT_CORE0_I2S_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_I2S_INTR_MAP_S 0
/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register
* UHCI0_INTR mapping register
@@ -587,46 +586,70 @@ extern "C" {
#define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0
/** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register
* CAN0_INTR mapping register
/** INTERRUPT_CORE0_TWAI0_INTR_MAP_REG register
* TWAI0_INTR mapping register
*/
#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
/** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
/** INTERRUPT_CORE0_TWAI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_CAN0_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_CAN0_INTR_MAP_M (INTERRUPT_CORE0_CAN0_INTR_MAP_V << INTERRUPT_CORE0_CAN0_INTR_MAP_S)
#define INTERRUPT_CORE0_CAN0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_CAN0_INTR_MAP_S 0
#define INTERRUPT_CORE0_TWAI0_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_M (INTERRUPT_CORE0_TWAI0_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_INTR_MAP_S)
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_S 0
/** INTERRUPT_CORE0_CAN1_INTR_MAP_REG register
* CAN1_INTR mapping register
/** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG register
* TWAI0_TIMER_INTR mapping register
*/
#define INTERRUPT_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
/** INTERRUPT_CORE0_CAN1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
/** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_CAN1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_CAN1_INTR_MAP_M (INTERRUPT_CORE0_CAN1_INTR_MAP_V << INTERRUPT_CORE0_CAN1_INTR_MAP_S)
#define INTERRUPT_CORE0_CAN1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_CAN1_INTR_MAP_S 0
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_M (INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S)
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_INTR_MAP_REG register
* USB_INTR mapping register
/** INTERRUPT_CORE0_TWAI1_INTR_MAP_REG register
* TWAI1_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
/** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
/** INTERRUPT_CORE0_TWAI1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_INTR_MAP_M (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_INTR_MAP_S 0
#define INTERRUPT_CORE0_TWAI1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_M (INTERRUPT_CORE0_TWAI1_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_INTR_MAP_S)
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_S 0
/** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG register
* TWAI1_TIMER_INTR mapping register
*/
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
/** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_M (INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S)
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register
* USB_SERIAL_JTAG_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_M (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S 0
/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register
* RMT_INTR mapping register
*/
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -638,7 +661,7 @@ extern "C" {
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register
* I2C_EXT0_INTR mapping register
*/
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -650,7 +673,7 @@ extern "C" {
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register
* TG0_T0_INTR mapping register
*/
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -659,22 +682,10 @@ extern "C" {
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0
/** INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG register
* TG0_T1_INTR mapping register
*/
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
/** INTERRUPT_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_M (INTERRUPT_CORE0_TG0_T1_INTR_MAP_V << INTERRUPT_CORE0_TG0_T1_INTR_MAP_S)
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_S 0
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register
* TG0_WDT_INTR mapping register
*/
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -686,7 +697,7 @@ extern "C" {
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register
* TG1_T0_INTR mapping register
*/
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -695,18 +706,6 @@ extern "C" {
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0
/** INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG register
* TG1_T1_INTR mapping register
*/
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
/** INTERRUPT_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_M (INTERRUPT_CORE0_TG1_T1_INTR_MAP_V << INTERRUPT_CORE0_TG1_T1_INTR_MAP_S)
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_S 0
/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register
* TG1_WDT_INTR mapping register
*/
@@ -815,70 +814,10 @@ extern "C" {
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S 0
/** INTERRUPT_CORE0_SLC0_INTR_MAP_REG register
* SLC0_INTR mapping register
*/
#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
/** INTERRUPT_CORE0_SLC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_SLC0_INTR_MAP_M (INTERRUPT_CORE0_SLC0_INTR_MAP_V << INTERRUPT_CORE0_SLC0_INTR_MAP_S)
#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0
/** INTERRUPT_CORE0_SLC1_INTR_MAP_REG register
* SLC1_INTR mapping register
*/
#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/** INTERRUPT_CORE0_SLC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_SLC1_INTR_MAP_M (INTERRUPT_CORE0_SLC1_INTR_MAP_V << INTERRUPT_CORE0_SLC1_INTR_MAP_S)
#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_OTG20_INTR_MAP_REG register
* USB_OTG20_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/** INTERRUPT_CORE0_USB_OTG20_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_REG register
* USB_OTG20_MULTI_PROC_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/** INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_REG register
* USB_OTG20_MISC_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
/** INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_S 0
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register
* DMA_IN_CH0_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -890,7 +829,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register
* DMA_IN_CH1_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -902,7 +841,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register
* DMA_IN_CH2_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -914,7 +853,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
* DMA_OUT_CH0_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -926,7 +865,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
* DMA_OUT_CH1_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -938,7 +877,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
* DMA_OUT_CH2_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -950,7 +889,7 @@ extern "C" {
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register
* GPSPI2_INTR mapping register
*/
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -962,7 +901,7 @@ extern "C" {
/** INTERRUPT_CORE0_AES_INTR_MAP_REG register
* AES_INTR mapping register
*/
#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -974,7 +913,7 @@ extern "C" {
/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register
* SHA_INTR mapping register
*/
#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -986,7 +925,7 @@ extern "C" {
/** INTERRUPT_CORE0_RSA_INTR_MAP_REG register
* RSA_INTR mapping register
*/
#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
/** INTERRUPT_CORE0_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -998,7 +937,7 @@ extern "C" {
/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register
* ECC_INTR mapping register
*/
#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -1010,7 +949,7 @@ extern "C" {
/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register
* ECDSA_INTR mapping register
*/
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -1022,7 +961,7 @@ extern "C" {
/** INTERRUPT_CORE0_KM_INTR_MAP_REG register
* KM_INTR mapping register
*/
#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@@ -1031,10 +970,10 @@ extern "C" {
#define INTERRUPT_CORE0_KM_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_KM_INTR_MAP_S 0
/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register
/** INTERRUPT_CORE0_INT_STATUS_0_REG register
* Status register for interrupt sources 0 ~ 31
*/
#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
#define INTERRUPT_CORE0_INT_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* Represents the status of the interrupt sources numbered from .Each bit corresponds
* to one interrupt source
@@ -1046,10 +985,10 @@ extern "C" {
#define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_0_S 0
/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register
/** INTERRUPT_CORE0_INT_STATUS_1_REG register
* Status register for interrupt sources 32 ~ 63
*/
#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
#define INTERRUPT_CORE0_INT_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* Represents the status of the interrupt sources numbered from .Each bit corresponds
* to one interrupt source
@@ -1061,10 +1000,10 @@ extern "C" {
#define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_1_S 0
/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register
/** INTERRUPT_CORE0_INT_STATUS_2_REG register
* Status register for interrupt sources 64 ~ 95
*/
#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c)
#define INTERRUPT_CORE0_INT_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* Represents the status of the interrupt sources numbered from .Each bit corresponds
* to one interrupt source
@@ -1079,7 +1018,7 @@ extern "C" {
/** INTERRUPT_CORE0_CLOCK_GATE_REG register
* Interrupt clock gating configure register
*/
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
* Interrupt clock gating configure register
*/
@@ -1092,7 +1031,7 @@ extern "C" {
* Version control register
*/
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc)
/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36717104;
/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36773985;
* Version control register
*/
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU

2
components/soc/esp32c5/beta3/include/soc/interrupt_reg.h
View File

@@ -16,8 +16,8 @@ extern "C" {
* ESP32C5 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y)
*/
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF)
/* We only have a single core on the C5, CORE0 */
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG
#ifdef __cplusplus

106
components/soc/esp32c5/beta3/include/soc/interrupts.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,25 +12,24 @@ extern "C"
{
#endif
// TODO: [ESP32C5] IDF-8654 need update for MP version
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE,
ETS_WIFI_MAC_NMI_SOURCE,
ETS_WIFI_PWR_INTR_SOURCE,
ETS_WIFI_BB_INTR_SOURCE,
ETS_BT_MAC_INTR_SOURCE,
ETS_BT_BB_INTR_SOURCE,
ETS_BT_BB_NMI_SOURCE,
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibration*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
ETS_LP_TIMER_INTR_SOURCE,
ETS_COEX_INTR_SOURCE,
ETS_BLE_TIMER_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_I2C_MST_INTR_SOURCE,
ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
ETS_ZB_MAC_INTR_SOURCE,
ETS_PMU_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_LP_RTC_TIMER_INTR_SOURCE,
ETS_LP_UART_INTR_SOURCE,
ETS_LP_I2C_INTR_SOURCE,
@@ -39,17 +38,16 @@ typedef enum {
ETS_LP_APM_M0_INTR_SOURCE,
ETS_LP_APM_M1_INTR_SOURCE,
ETS_HUK_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE,
ETS_FROM_CPU_INTR1_SOURCE,
ETS_FROM_CPU_INTR2_SOURCE,
ETS_FROM_CPU_INTR3_SOURCE,
ETS_ASSIST_DEBUG_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_TRACE_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE,
ETS_GPIO_NMI_SOURCE,
ETS_GPIO_PAD_COMP_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
@@ -57,52 +55,48 @@ typedef enum {
ETS_HP_APM_M1_INTR_SOURCE,
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_HP_APM_M4_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE,
ETS_UHCI0_INTR_SOURCE,
ETS_UART0_INTR_SOURCE,
ETS_UART1_INTR_SOURCE,
ETS_LEDC_INTR_SOURCE,
ETS_TWAI0_INTR_SOURCE,
ETS_TWAI1_INTR_SOURCE,
ETS_USB_INTR_SOURCE,
ETS_RMT_INTR_SOURCE,
ETS_I2C_EXT0_INTR_SOURCE,
ETS_TG0_T0_LEVEL_INTR_SOURCE,
ETS_TG0_T1_LEVEL_INTR_SOURCE,
ETS_TG0_WDT_LEVEL_INTR_SOURCE,
ETS_TG1_T0_LEVEL_INTR_SOURCE,
ETS_TG1_T1_LEVEL_INTR_SOURCE,
ETS_TG1_WDT_LEVEL_INTR_SOURCE,
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
ETS_APB_ADC_INTR_SOURCE,
ETS_PWM_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/
ETS_TWAI0_TIMER_INTR_SOURCE, /**< interrupt of can0 timer, level*/
ETS_TWAI1_INTR_SOURCE, /**< interrupt of can1, level*/
ETS_TWAI1_TIMER_INTR_SOURCE, /**< interrupt of can0 timer, level*/
ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
ETS_PARL_IO_RX_INTR_SOURCE,
ETS_SLC0_INTR_SOURCE,
ETS_SLC1_INTR_SOURCE,
ETS_USB_OTG20_INTR_SOURCE,
ETS_USB_OTG20_MULTI_PROC_INTR_SOURCE,
ETS_USB_OTG20_MISC_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE,
ETS_DMA_IN_CH1_INTR_SOURCE,
ETS_DMA_IN_CH2_INTR_SOURCE,
ETS_DMA_OUT_CH0_INTR_SOURCE,
ETS_DMA_OUT_CH1_INTR_SOURCE,
ETS_DMA_OUT_CH2_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/
ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/
ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/
ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/
ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/
ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/
ETS_GPSPI2_INTR_SOURCE,
ETS_AES_INTR_SOURCE,
ETS_SHA_INTR_SOURCE,
ETS_RSA_INTR_SOURCE,
ETS_ECC_INTR_SOURCE,
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/
ETS_ECDSA_INTR_SOURCE,
ETS_KM_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrput_t;
} periph_interrupt_t;
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];