diff --git a/components/soc/esp32p4/include/soc/dma_pms_reg.h b/components/soc/esp32p4/include/soc/dma_pms_reg.h
index 273935329d..d985c15a13 100644
--- a/components/soc/esp32p4/include/soc/dma_pms_reg.h
+++ b/components/soc/esp32p4/include/soc/dma_pms_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** PMS_DMA_DATE_REG register
  *  Version control register
  */
-#define PMS_DMA_DATE_REG (DR_REG_PMS_DMA_BASE + 0x0)
+#define PMS_DMA_DATE_REG (DR_REG_DMA_PMS_BASE + 0x0)
 /** PMS_DMA_DATE : R/W; bitpos: [31:0]; default: 539165460;
  *  Version control register.
  */
@@ -26,7 +26,7 @@ extern "C" {
 /** PMS_DMA_CLK_EN_REG register
  *  Clock gating register
  */
-#define PMS_DMA_CLK_EN_REG (DR_REG_PMS_DMA_BASE + 0x4)
+#define PMS_DMA_CLK_EN_REG (DR_REG_DMA_PMS_BASE + 0x4)
 /** PMS_DMA_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Configures whether to keep the clock always on.
  *  0: Enable automatic clock gating.
@@ -40,7 +40,7 @@ extern "C" {
 /** PMS_DMA_REGION0_LOW_REG register
  *  Region0 start address configuration register
  */
-#define PMS_DMA_REGION0_LOW_REG (DR_REG_PMS_DMA_BASE + 0x8)
+#define PMS_DMA_REGION0_LOW_REG (DR_REG_DMA_PMS_BASE + 0x8)
 /** PMS_DMA_REGION0_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region0.
  */
@@ -52,7 +52,7 @@ extern "C" {
 /** PMS_DMA_REGION0_HIGH_REG register
  *  Region0 end address configuration register
  */
-#define PMS_DMA_REGION0_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xc)
+#define PMS_DMA_REGION0_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xc)
 /** PMS_DMA_REGION0_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region0.
  */
@@ -64,7 +64,7 @@ extern "C" {
 /** PMS_DMA_REGION1_LOW_REG register
  *  Region1 start address configuration register
  */
-#define PMS_DMA_REGION1_LOW_REG (DR_REG_PMS_DMA_BASE + 0x10)
+#define PMS_DMA_REGION1_LOW_REG (DR_REG_DMA_PMS_BASE + 0x10)
 /** PMS_DMA_REGION1_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region1.
  */
@@ -76,7 +76,7 @@ extern "C" {
 /** PMS_DMA_REGION1_HIGH_REG register
  *  Region1 end address configuration register
  */
-#define PMS_DMA_REGION1_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x14)
+#define PMS_DMA_REGION1_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x14)
 /** PMS_DMA_REGION1_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region1.
  */
@@ -88,7 +88,7 @@ extern "C" {
 /** PMS_DMA_REGION2_LOW_REG register
  *  Region2 start address configuration register
  */
-#define PMS_DMA_REGION2_LOW_REG (DR_REG_PMS_DMA_BASE + 0x18)
+#define PMS_DMA_REGION2_LOW_REG (DR_REG_DMA_PMS_BASE + 0x18)
 /** PMS_DMA_REGION2_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region2.
  */
@@ -100,7 +100,7 @@ extern "C" {
 /** PMS_DMA_REGION2_HIGH_REG register
  *  Region2 end address configuration register
  */
-#define PMS_DMA_REGION2_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x1c)
+#define PMS_DMA_REGION2_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x1c)
 /** PMS_DMA_REGION2_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region2.
  */
@@ -112,7 +112,7 @@ extern "C" {
 /** PMS_DMA_REGION3_LOW_REG register
  *  Region3 start address configuration register
  */
-#define PMS_DMA_REGION3_LOW_REG (DR_REG_PMS_DMA_BASE + 0x20)
+#define PMS_DMA_REGION3_LOW_REG (DR_REG_DMA_PMS_BASE + 0x20)
 /** PMS_DMA_REGION3_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region3.
  */
@@ -124,7 +124,7 @@ extern "C" {
 /** PMS_DMA_REGION3_HIGH_REG register
  *  Region3 end address configuration register
  */
-#define PMS_DMA_REGION3_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x24)
+#define PMS_DMA_REGION3_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x24)
 /** PMS_DMA_REGION3_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region3.
  */
@@ -136,7 +136,7 @@ extern "C" {
 /** PMS_DMA_REGION4_LOW_REG register
  *  Region4 start address configuration register
  */
-#define PMS_DMA_REGION4_LOW_REG (DR_REG_PMS_DMA_BASE + 0x28)
+#define PMS_DMA_REGION4_LOW_REG (DR_REG_DMA_PMS_BASE + 0x28)
 /** PMS_DMA_REGION4_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region4.
  */
@@ -148,7 +148,7 @@ extern "C" {
 /** PMS_DMA_REGION4_HIGH_REG register
  *  Region4 end address configuration register
  */
-#define PMS_DMA_REGION4_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x2c)
+#define PMS_DMA_REGION4_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x2c)
 /** PMS_DMA_REGION4_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region4.
  */
@@ -160,7 +160,7 @@ extern "C" {
 /** PMS_DMA_REGION5_LOW_REG register
  *  Region5 start address configuration register
  */
-#define PMS_DMA_REGION5_LOW_REG (DR_REG_PMS_DMA_BASE + 0x30)
+#define PMS_DMA_REGION5_LOW_REG (DR_REG_DMA_PMS_BASE + 0x30)
 /** PMS_DMA_REGION5_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region5.
  */
@@ -172,7 +172,7 @@ extern "C" {
 /** PMS_DMA_REGION5_HIGH_REG register
  *  Region5 end address configuration register
  */
-#define PMS_DMA_REGION5_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x34)
+#define PMS_DMA_REGION5_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x34)
 /** PMS_DMA_REGION5_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region5.
  */
@@ -184,7 +184,7 @@ extern "C" {
 /** PMS_DMA_REGION6_LOW_REG register
  *  Region6 start address configuration register
  */
-#define PMS_DMA_REGION6_LOW_REG (DR_REG_PMS_DMA_BASE + 0x38)
+#define PMS_DMA_REGION6_LOW_REG (DR_REG_DMA_PMS_BASE + 0x38)
 /** PMS_DMA_REGION6_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region6.
  */
@@ -196,7 +196,7 @@ extern "C" {
 /** PMS_DMA_REGION6_HIGH_REG register
  *  Region6 end address configuration register
  */
-#define PMS_DMA_REGION6_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x3c)
+#define PMS_DMA_REGION6_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x3c)
 /** PMS_DMA_REGION6_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region6.
  */
@@ -208,7 +208,7 @@ extern "C" {
 /** PMS_DMA_REGION7_LOW_REG register
  *  Region7 start address configuration register
  */
-#define PMS_DMA_REGION7_LOW_REG (DR_REG_PMS_DMA_BASE + 0x40)
+#define PMS_DMA_REGION7_LOW_REG (DR_REG_DMA_PMS_BASE + 0x40)
 /** PMS_DMA_REGION7_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region7.
  */
@@ -220,7 +220,7 @@ extern "C" {
 /** PMS_DMA_REGION7_HIGH_REG register
  *  Region7 end address configuration register
  */
-#define PMS_DMA_REGION7_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x44)
+#define PMS_DMA_REGION7_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x44)
 /** PMS_DMA_REGION7_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region7.
  */
@@ -232,7 +232,7 @@ extern "C" {
 /** PMS_DMA_REGION8_LOW_REG register
  *  Region8 start address configuration register
  */
-#define PMS_DMA_REGION8_LOW_REG (DR_REG_PMS_DMA_BASE + 0x48)
+#define PMS_DMA_REGION8_LOW_REG (DR_REG_DMA_PMS_BASE + 0x48)
 /** PMS_DMA_REGION8_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region8.
  */
@@ -244,7 +244,7 @@ extern "C" {
 /** PMS_DMA_REGION8_HIGH_REG register
  *  Region8 end address configuration register
  */
-#define PMS_DMA_REGION8_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x4c)
+#define PMS_DMA_REGION8_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x4c)
 /** PMS_DMA_REGION8_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region8.
  */
@@ -256,7 +256,7 @@ extern "C" {
 /** PMS_DMA_REGION9_LOW_REG register
  *  Region9 start address configuration register
  */
-#define PMS_DMA_REGION9_LOW_REG (DR_REG_PMS_DMA_BASE + 0x50)
+#define PMS_DMA_REGION9_LOW_REG (DR_REG_DMA_PMS_BASE + 0x50)
 /** PMS_DMA_REGION9_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region9.
  */
@@ -268,7 +268,7 @@ extern "C" {
 /** PMS_DMA_REGION9_HIGH_REG register
  *  Region9 end address configuration register
  */
-#define PMS_DMA_REGION9_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x54)
+#define PMS_DMA_REGION9_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x54)
 /** PMS_DMA_REGION9_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region9.
  */
@@ -280,7 +280,7 @@ extern "C" {
 /** PMS_DMA_REGION10_LOW_REG register
  *  Region10 start address configuration register
  */
-#define PMS_DMA_REGION10_LOW_REG (DR_REG_PMS_DMA_BASE + 0x58)
+#define PMS_DMA_REGION10_LOW_REG (DR_REG_DMA_PMS_BASE + 0x58)
 /** PMS_DMA_REGION10_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region10.
  */
@@ -292,7 +292,7 @@ extern "C" {
 /** PMS_DMA_REGION10_HIGH_REG register
  *  Region10 end address configuration register
  */
-#define PMS_DMA_REGION10_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x5c)
+#define PMS_DMA_REGION10_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x5c)
 /** PMS_DMA_REGION10_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region10.
  */
@@ -304,7 +304,7 @@ extern "C" {
 /** PMS_DMA_REGION11_LOW_REG register
  *  Region11 start address configuration register
  */
-#define PMS_DMA_REGION11_LOW_REG (DR_REG_PMS_DMA_BASE + 0x60)
+#define PMS_DMA_REGION11_LOW_REG (DR_REG_DMA_PMS_BASE + 0x60)
 /** PMS_DMA_REGION11_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region11.
  */
@@ -316,7 +316,7 @@ extern "C" {
 /** PMS_DMA_REGION11_HIGH_REG register
  *  Region11 end address configuration register
  */
-#define PMS_DMA_REGION11_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x64)
+#define PMS_DMA_REGION11_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x64)
 /** PMS_DMA_REGION11_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region11.
  */
@@ -328,7 +328,7 @@ extern "C" {
 /** PMS_DMA_REGION12_LOW_REG register
  *  Region12 start address configuration register
  */
-#define PMS_DMA_REGION12_LOW_REG (DR_REG_PMS_DMA_BASE + 0x68)
+#define PMS_DMA_REGION12_LOW_REG (DR_REG_DMA_PMS_BASE + 0x68)
 /** PMS_DMA_REGION12_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region12.
  */
@@ -340,7 +340,7 @@ extern "C" {
 /** PMS_DMA_REGION12_HIGH_REG register
  *  Region12 end address configuration register
  */
-#define PMS_DMA_REGION12_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x6c)
+#define PMS_DMA_REGION12_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x6c)
 /** PMS_DMA_REGION12_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region12.
  */
@@ -352,7 +352,7 @@ extern "C" {
 /** PMS_DMA_REGION13_LOW_REG register
  *  Region13 start address configuration register
  */
-#define PMS_DMA_REGION13_LOW_REG (DR_REG_PMS_DMA_BASE + 0x70)
+#define PMS_DMA_REGION13_LOW_REG (DR_REG_DMA_PMS_BASE + 0x70)
 /** PMS_DMA_REGION13_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region13.
  */
@@ -364,7 +364,7 @@ extern "C" {
 /** PMS_DMA_REGION13_HIGH_REG register
  *  Region13 end address configuration register
  */
-#define PMS_DMA_REGION13_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x74)
+#define PMS_DMA_REGION13_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x74)
 /** PMS_DMA_REGION13_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region13.
  */
@@ -376,7 +376,7 @@ extern "C" {
 /** PMS_DMA_REGION14_LOW_REG register
  *  Region14 start address configuration register
  */
-#define PMS_DMA_REGION14_LOW_REG (DR_REG_PMS_DMA_BASE + 0x78)
+#define PMS_DMA_REGION14_LOW_REG (DR_REG_DMA_PMS_BASE + 0x78)
 /** PMS_DMA_REGION14_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region14.
  */
@@ -388,7 +388,7 @@ extern "C" {
 /** PMS_DMA_REGION14_HIGH_REG register
  *  Region14 end address configuration register
  */
-#define PMS_DMA_REGION14_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x7c)
+#define PMS_DMA_REGION14_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x7c)
 /** PMS_DMA_REGION14_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region14.
  */
@@ -400,7 +400,7 @@ extern "C" {
 /** PMS_DMA_REGION15_LOW_REG register
  *  Region15 start address configuration register
  */
-#define PMS_DMA_REGION15_LOW_REG (DR_REG_PMS_DMA_BASE + 0x80)
+#define PMS_DMA_REGION15_LOW_REG (DR_REG_DMA_PMS_BASE + 0x80)
 /** PMS_DMA_REGION15_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region15.
  */
@@ -412,7 +412,7 @@ extern "C" {
 /** PMS_DMA_REGION15_HIGH_REG register
  *  Region15 end address configuration register
  */
-#define PMS_DMA_REGION15_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x84)
+#define PMS_DMA_REGION15_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x84)
 /** PMS_DMA_REGION15_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region15.
  */
@@ -424,7 +424,7 @@ extern "C" {
 /** PMS_DMA_REGION16_LOW_REG register
  *  Region16 start address configuration register
  */
-#define PMS_DMA_REGION16_LOW_REG (DR_REG_PMS_DMA_BASE + 0x88)
+#define PMS_DMA_REGION16_LOW_REG (DR_REG_DMA_PMS_BASE + 0x88)
 /** PMS_DMA_REGION16_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region16.
  */
@@ -436,7 +436,7 @@ extern "C" {
 /** PMS_DMA_REGION16_HIGH_REG register
  *  Region16 end address configuration register
  */
-#define PMS_DMA_REGION16_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x8c)
+#define PMS_DMA_REGION16_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x8c)
 /** PMS_DMA_REGION16_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region16.
  */
@@ -448,7 +448,7 @@ extern "C" {
 /** PMS_DMA_REGION17_LOW_REG register
  *  Region17 start address configuration register
  */
-#define PMS_DMA_REGION17_LOW_REG (DR_REG_PMS_DMA_BASE + 0x90)
+#define PMS_DMA_REGION17_LOW_REG (DR_REG_DMA_PMS_BASE + 0x90)
 /** PMS_DMA_REGION17_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region17.
  */
@@ -460,7 +460,7 @@ extern "C" {
 /** PMS_DMA_REGION17_HIGH_REG register
  *  Region17 end address configuration register
  */
-#define PMS_DMA_REGION17_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x94)
+#define PMS_DMA_REGION17_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x94)
 /** PMS_DMA_REGION17_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region17.
  */
@@ -472,7 +472,7 @@ extern "C" {
 /** PMS_DMA_REGION18_LOW_REG register
  *  Region18 start address configuration register
  */
-#define PMS_DMA_REGION18_LOW_REG (DR_REG_PMS_DMA_BASE + 0x98)
+#define PMS_DMA_REGION18_LOW_REG (DR_REG_DMA_PMS_BASE + 0x98)
 /** PMS_DMA_REGION18_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region18.
  */
@@ -484,7 +484,7 @@ extern "C" {
 /** PMS_DMA_REGION18_HIGH_REG register
  *  Region18 end address configuration register
  */
-#define PMS_DMA_REGION18_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x9c)
+#define PMS_DMA_REGION18_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x9c)
 /** PMS_DMA_REGION18_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region18.
  */
@@ -496,7 +496,7 @@ extern "C" {
 /** PMS_DMA_REGION19_LOW_REG register
  *  Region19 start address configuration register
  */
-#define PMS_DMA_REGION19_LOW_REG (DR_REG_PMS_DMA_BASE + 0xa0)
+#define PMS_DMA_REGION19_LOW_REG (DR_REG_DMA_PMS_BASE + 0xa0)
 /** PMS_DMA_REGION19_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region19.
  */
@@ -508,7 +508,7 @@ extern "C" {
 /** PMS_DMA_REGION19_HIGH_REG register
  *  Region19 end address configuration register
  */
-#define PMS_DMA_REGION19_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xa4)
+#define PMS_DMA_REGION19_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xa4)
 /** PMS_DMA_REGION19_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region19.
  */
@@ -520,7 +520,7 @@ extern "C" {
 /** PMS_DMA_REGION20_LOW_REG register
  *  Region20 start address configuration register
  */
-#define PMS_DMA_REGION20_LOW_REG (DR_REG_PMS_DMA_BASE + 0xa8)
+#define PMS_DMA_REGION20_LOW_REG (DR_REG_DMA_PMS_BASE + 0xa8)
 /** PMS_DMA_REGION20_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region20.
  */
@@ -532,7 +532,7 @@ extern "C" {
 /** PMS_DMA_REGION20_HIGH_REG register
  *  Region20 end address configuration register
  */
-#define PMS_DMA_REGION20_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xac)
+#define PMS_DMA_REGION20_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xac)
 /** PMS_DMA_REGION20_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region20.
  */
@@ -544,7 +544,7 @@ extern "C" {
 /** PMS_DMA_REGION21_LOW_REG register
  *  Region21 start address configuration register
  */
-#define PMS_DMA_REGION21_LOW_REG (DR_REG_PMS_DMA_BASE + 0xb0)
+#define PMS_DMA_REGION21_LOW_REG (DR_REG_DMA_PMS_BASE + 0xb0)
 /** PMS_DMA_REGION21_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region21.
  */
@@ -556,7 +556,7 @@ extern "C" {
 /** PMS_DMA_REGION21_HIGH_REG register
  *  Region21 end address configuration register
  */
-#define PMS_DMA_REGION21_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xb4)
+#define PMS_DMA_REGION21_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xb4)
 /** PMS_DMA_REGION21_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region21.
  */
@@ -568,7 +568,7 @@ extern "C" {
 /** PMS_DMA_REGION22_LOW_REG register
  *  Region22 start address configuration register
  */
-#define PMS_DMA_REGION22_LOW_REG (DR_REG_PMS_DMA_BASE + 0xb8)
+#define PMS_DMA_REGION22_LOW_REG (DR_REG_DMA_PMS_BASE + 0xb8)
 /** PMS_DMA_REGION22_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region22.
  */
@@ -580,7 +580,7 @@ extern "C" {
 /** PMS_DMA_REGION22_HIGH_REG register
  *  Region22 end address configuration register
  */
-#define PMS_DMA_REGION22_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xbc)
+#define PMS_DMA_REGION22_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xbc)
 /** PMS_DMA_REGION22_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region22.
  */
@@ -592,7 +592,7 @@ extern "C" {
 /** PMS_DMA_REGION23_LOW_REG register
  *  Region23 start address configuration register
  */
-#define PMS_DMA_REGION23_LOW_REG (DR_REG_PMS_DMA_BASE + 0xc0)
+#define PMS_DMA_REGION23_LOW_REG (DR_REG_DMA_PMS_BASE + 0xc0)
 /** PMS_DMA_REGION23_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region23.
  */
@@ -604,7 +604,7 @@ extern "C" {
 /** PMS_DMA_REGION23_HIGH_REG register
  *  Region23 end address configuration register
  */
-#define PMS_DMA_REGION23_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xc4)
+#define PMS_DMA_REGION23_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xc4)
 /** PMS_DMA_REGION23_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region23.
  */
@@ -616,7 +616,7 @@ extern "C" {
 /** PMS_DMA_REGION24_LOW_REG register
  *  Region24 start address configuration register
  */
-#define PMS_DMA_REGION24_LOW_REG (DR_REG_PMS_DMA_BASE + 0xc8)
+#define PMS_DMA_REGION24_LOW_REG (DR_REG_DMA_PMS_BASE + 0xc8)
 /** PMS_DMA_REGION24_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region24.
  */
@@ -628,7 +628,7 @@ extern "C" {
 /** PMS_DMA_REGION24_HIGH_REG register
  *  Region24 end address configuration register
  */
-#define PMS_DMA_REGION24_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xcc)
+#define PMS_DMA_REGION24_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xcc)
 /** PMS_DMA_REGION24_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region24.
  */
@@ -640,7 +640,7 @@ extern "C" {
 /** PMS_DMA_REGION25_LOW_REG register
  *  Region25 start address configuration register
  */
-#define PMS_DMA_REGION25_LOW_REG (DR_REG_PMS_DMA_BASE + 0xd0)
+#define PMS_DMA_REGION25_LOW_REG (DR_REG_DMA_PMS_BASE + 0xd0)
 /** PMS_DMA_REGION25_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region25.
  */
@@ -652,7 +652,7 @@ extern "C" {
 /** PMS_DMA_REGION25_HIGH_REG register
  *  Region25 end address configuration register
  */
-#define PMS_DMA_REGION25_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xd4)
+#define PMS_DMA_REGION25_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xd4)
 /** PMS_DMA_REGION25_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region25.
  */
@@ -664,7 +664,7 @@ extern "C" {
 /** PMS_DMA_REGION26_LOW_REG register
  *  Region26 start address configuration register
  */
-#define PMS_DMA_REGION26_LOW_REG (DR_REG_PMS_DMA_BASE + 0xd8)
+#define PMS_DMA_REGION26_LOW_REG (DR_REG_DMA_PMS_BASE + 0xd8)
 /** PMS_DMA_REGION26_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region26.
  */
@@ -676,7 +676,7 @@ extern "C" {
 /** PMS_DMA_REGION26_HIGH_REG register
  *  Region26 end address configuration register
  */
-#define PMS_DMA_REGION26_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xdc)
+#define PMS_DMA_REGION26_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xdc)
 /** PMS_DMA_REGION26_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region26.
  */
@@ -688,7 +688,7 @@ extern "C" {
 /** PMS_DMA_REGION27_LOW_REG register
  *  Region27 start address configuration register
  */
-#define PMS_DMA_REGION27_LOW_REG (DR_REG_PMS_DMA_BASE + 0xe0)
+#define PMS_DMA_REGION27_LOW_REG (DR_REG_DMA_PMS_BASE + 0xe0)
 /** PMS_DMA_REGION27_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region27.
  */
@@ -700,7 +700,7 @@ extern "C" {
 /** PMS_DMA_REGION27_HIGH_REG register
  *  Region27 end address configuration register
  */
-#define PMS_DMA_REGION27_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xe4)
+#define PMS_DMA_REGION27_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xe4)
 /** PMS_DMA_REGION27_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region27.
  */
@@ -712,7 +712,7 @@ extern "C" {
 /** PMS_DMA_REGION28_LOW_REG register
  *  Region28 start address configuration register
  */
-#define PMS_DMA_REGION28_LOW_REG (DR_REG_PMS_DMA_BASE + 0xe8)
+#define PMS_DMA_REGION28_LOW_REG (DR_REG_DMA_PMS_BASE + 0xe8)
 /** PMS_DMA_REGION28_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region28.
  */
@@ -724,7 +724,7 @@ extern "C" {
 /** PMS_DMA_REGION28_HIGH_REG register
  *  Region28 end address configuration register
  */
-#define PMS_DMA_REGION28_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xec)
+#define PMS_DMA_REGION28_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xec)
 /** PMS_DMA_REGION28_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region28.
  */
@@ -736,7 +736,7 @@ extern "C" {
 /** PMS_DMA_REGION29_LOW_REG register
  *  Region29 start address configuration register
  */
-#define PMS_DMA_REGION29_LOW_REG (DR_REG_PMS_DMA_BASE + 0xf0)
+#define PMS_DMA_REGION29_LOW_REG (DR_REG_DMA_PMS_BASE + 0xf0)
 /** PMS_DMA_REGION29_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region29.
  */
@@ -748,7 +748,7 @@ extern "C" {
 /** PMS_DMA_REGION29_HIGH_REG register
  *  Region29 end address configuration register
  */
-#define PMS_DMA_REGION29_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xf4)
+#define PMS_DMA_REGION29_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xf4)
 /** PMS_DMA_REGION29_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region29.
  */
@@ -760,7 +760,7 @@ extern "C" {
 /** PMS_DMA_REGION30_LOW_REG register
  *  Region30 start address configuration register
  */
-#define PMS_DMA_REGION30_LOW_REG (DR_REG_PMS_DMA_BASE + 0xf8)
+#define PMS_DMA_REGION30_LOW_REG (DR_REG_DMA_PMS_BASE + 0xf8)
 /** PMS_DMA_REGION30_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region30.
  */
@@ -772,7 +772,7 @@ extern "C" {
 /** PMS_DMA_REGION30_HIGH_REG register
  *  Region30 end address configuration register
  */
-#define PMS_DMA_REGION30_HIGH_REG (DR_REG_PMS_DMA_BASE + 0xfc)
+#define PMS_DMA_REGION30_HIGH_REG (DR_REG_DMA_PMS_BASE + 0xfc)
 /** PMS_DMA_REGION30_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region30.
  */
@@ -784,7 +784,7 @@ extern "C" {
 /** PMS_DMA_REGION31_LOW_REG register
  *  Region31 start address configuration register
  */
-#define PMS_DMA_REGION31_LOW_REG (DR_REG_PMS_DMA_BASE + 0x100)
+#define PMS_DMA_REGION31_LOW_REG (DR_REG_DMA_PMS_BASE + 0x100)
 /** PMS_DMA_REGION31_LOW : R/W; bitpos: [31:12]; default: 0;
  *  Configures the high 20 bits of the start address for region31.
  */
@@ -796,7 +796,7 @@ extern "C" {
 /** PMS_DMA_REGION31_HIGH_REG register
  *  Region31 end address configuration register
  */
-#define PMS_DMA_REGION31_HIGH_REG (DR_REG_PMS_DMA_BASE + 0x104)
+#define PMS_DMA_REGION31_HIGH_REG (DR_REG_DMA_PMS_BASE + 0x104)
 /** PMS_DMA_REGION31_HIGH : R/W; bitpos: [31:12]; default: 1048575;
  *  Configures the high 20 bits of the end address for region31.
  */
@@ -808,7 +808,7 @@ extern "C" {
 /** PMS_DMA_GDMA_CH0_R_PMS_REG register
  *  GDMA ch0 read permission control register
  */
-#define PMS_DMA_GDMA_CH0_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x108)
+#define PMS_DMA_GDMA_CH0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x108)
 /** PMS_DMA_GDMA_CH0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures the permission for GDMA ch0 to read 32 address regions. Bit 0
  *  corresponds to region0, and so on.
@@ -823,7 +823,7 @@ extern "C" {
 /** PMS_DMA_GDMA_CH0_W_PMS_REG register
  *  GDMA ch0 write permission control register
  */
-#define PMS_DMA_GDMA_CH0_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x10c)
+#define PMS_DMA_GDMA_CH0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x10c)
 /** PMS_DMA_GDMA_CH0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures the permission for GDMA ch0 to write 32 address regions. Bit 0
  *  corresponds to region0, and so on.
@@ -838,7 +838,7 @@ extern "C" {
 /** PMS_DMA_GDMA_CH1_R_PMS_REG register
  *  GDMA ch1 read permission control register
  */
-#define PMS_DMA_GDMA_CH1_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x110)
+#define PMS_DMA_GDMA_CH1_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x110)
 /** PMS_DMA_GDMA_CH1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures the permission for GDMA ch1 to read 32 address regions. Bit 0
  *  corresponds to region0, and so on.
@@ -853,7 +853,7 @@ extern "C" {
 /** PMS_DMA_GDMA_CH1_W_PMS_REG register
  *  GDMA ch1 write permission control register
  */
-#define PMS_DMA_GDMA_CH1_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x114)
+#define PMS_DMA_GDMA_CH1_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x114)
 /** PMS_DMA_GDMA_CH1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures the permission for GDMA ch1 to write 32 address regions. Bit 0
  *  corresponds to region0, and so on.
@@ -868,7 +868,7 @@ extern "C" {
 /** PMS_DMA_GDMA_CH2_R_PMS_REG register
  *  GDMA ch2 read permission control register
  */
-#define PMS_DMA_GDMA_CH2_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x118)
+#define PMS_DMA_GDMA_CH2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x118)
 /** PMS_DMA_GDMA_CH2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures the permission for GDMA ch2 to read 32 address regions. Bit 0
  *  corresponds to region0, and so on.
@@ -883,7 +883,7 @@ extern "C" {
 /** PMS_DMA_GDMA_CH2_W_PMS_REG register
  *  GDMA ch2 write permission control register
  */
-#define PMS_DMA_GDMA_CH2_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x11c)
+#define PMS_DMA_GDMA_CH2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x11c)
 /** PMS_DMA_GDMA_CH2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures the permission for GDMA ch2 to write 32 address regions. Bit 0
  *  corresponds to region0, and so on.
@@ -898,7 +898,7 @@ extern "C" {
 /** PMS_DMA_GDMA_CH3_R_PMS_REG register
  *  GDMA ch3 read permission control register
  */
-#define PMS_DMA_GDMA_CH3_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x120)
+#define PMS_DMA_GDMA_CH3_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x120)
 /** PMS_DMA_GDMA_CH3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures the permission for GDMA ch3 to read 32 address regions. Bit 0
  *  corresponds to region0, and so on.
@@ -913,7 +913,7 @@ extern "C" {
 /** PMS_DMA_GDMA_CH3_W_PMS_REG register
  *  GDMA ch3 write permission control register
  */
-#define PMS_DMA_GDMA_CH3_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x124)
+#define PMS_DMA_GDMA_CH3_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x124)
 /** PMS_DMA_GDMA_CH3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures the permission for GDMA ch3 to write 32 address regions. Bit 0
  *  corresponds to region0, and so on.
@@ -928,7 +928,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_ADC_R_PMS_REG register
  *  GDMA-AHB ADC read permission control register
  */
-#define PMS_DMA_AHB_PDMA_ADC_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x128)
+#define PMS_DMA_AHB_PDMA_ADC_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x128)
 /** PMS_DMA_AHB_PDMA_ADC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to read 32 address ranges requested by ADC. Bit 0
  *  corresponds to region0, and so on.
@@ -943,7 +943,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_ADC_W_PMS_REG register
  *  GDMA-AHB ADC write permission control register
  */
-#define PMS_DMA_AHB_PDMA_ADC_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x12c)
+#define PMS_DMA_AHB_PDMA_ADC_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x12c)
 /** PMS_DMA_AHB_PDMA_ADC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to write 32 address ranges requested by ADC. Bit 0
  *  corresponds to region0, and so on.
@@ -958,7 +958,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG register
  *  GDMA-AHB I2S0 read permission control register
  */
-#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x130)
+#define PMS_DMA_AHB_PDMA_I2S0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x130)
 /** PMS_DMA_AHB_PDMA_I2S0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to read 32 address ranges requested by I2S0. Bit 0
  *  corresponds to region0, and so on.
@@ -973,7 +973,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG register
  *  GDMA-AHB I2S0 write permission control register
  */
-#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x134)
+#define PMS_DMA_AHB_PDMA_I2S0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x134)
 /** PMS_DMA_AHB_PDMA_I2S0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to write 32 address ranges requested by I2S0. Bit 0
  *  corresponds to region0, and so on.
@@ -988,7 +988,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG register
  *  GDMA-AHB I2S1 read permission control register
  */
-#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x138)
+#define PMS_DMA_AHB_PDMA_I2S1_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x138)
 /** PMS_DMA_AHB_PDMA_I2S1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to read 32 address ranges requested by I2S1. Bit 0
  *  corresponds to region0, and so on.
@@ -1003,7 +1003,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG register
  *  GDMA-AHB I2S1 write permission control register
  */
-#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x13c)
+#define PMS_DMA_AHB_PDMA_I2S1_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x13c)
 /** PMS_DMA_AHB_PDMA_I2S1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to write 32 address ranges requested by I2S1. Bit 0
  *  corresponds to region0, and so on.
@@ -1018,7 +1018,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG register
  *  GDMA-AHB I2S2 read permission control register
  */
-#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x140)
+#define PMS_DMA_AHB_PDMA_I2S2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x140)
 /** PMS_DMA_AHB_PDMA_I2S2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to read 32 address ranges requested by I2S2. Bit 0
  *  corresponds to region0, and so on.
@@ -1033,7 +1033,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG register
  *  GDMA-AHB I2S2 write permission control register
  */
-#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x144)
+#define PMS_DMA_AHB_PDMA_I2S2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x144)
 /** PMS_DMA_AHB_PDMA_I2S2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to write 32 address ranges requested by I2S2. Bit 0
  *  corresponds to region0, and so on.
@@ -1048,7 +1048,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG register
  *  GDMA-AHB I3C MST read permission control register
  */
-#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x148)
+#define PMS_DMA_AHB_PDMA_I3C_MST_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x148)
 /** PMS_DMA_AHB_PDMA_I3C_MST_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to read 32 address ranges requested by I3C  master.
  *  Bit 0 corresponds to region0, and so on.
@@ -1063,7 +1063,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG register
  *  GDMA-AHB I3C MST write permission control register
  */
-#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x14c)
+#define PMS_DMA_AHB_PDMA_I3C_MST_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x14c)
 /** PMS_DMA_AHB_PDMA_I3C_MST_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to write 32 address ranges requested by I3C  master.
  *  Bit 0 corresponds to region0, and so on.
@@ -1078,7 +1078,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG register
  *  GDMA-AHB UHCI read permission control register
  */
-#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x150)
+#define PMS_DMA_AHB_PDMA_UHCI0_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x150)
 /** PMS_DMA_AHB_PDMA_UHCI0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to read 32 address ranges requested by UHCI. Bit 0
  *  corresponds to region0, and so on.
@@ -1093,7 +1093,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG register
  *  GDMA-AHB UHCI write permission control register
  */
-#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x154)
+#define PMS_DMA_AHB_PDMA_UHCI0_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x154)
 /** PMS_DMA_AHB_PDMA_UHCI0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to write 32 address ranges requested by UHCI. Bit 0
  *  corresponds to region0, and so on.
@@ -1108,7 +1108,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_RMT_R_PMS_REG register
  *  GDMA-AHB RMT read permission control register
  */
-#define PMS_DMA_AHB_PDMA_RMT_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x158)
+#define PMS_DMA_AHB_PDMA_RMT_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x158)
 /** PMS_DMA_AHB_PDMA_RMT_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to read 32 address ranges requested by RMT. Bit 0
  *  corresponds to region0, and so on.
@@ -1123,7 +1123,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_RMT_W_PMS_REG register
  *  GDMA-AHB RMT write permission control register
  */
-#define PMS_DMA_AHB_PDMA_RMT_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x170)
+#define PMS_DMA_AHB_PDMA_RMT_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x170)
 /** PMS_DMA_AHB_PDMA_RMT_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to write 32 address ranges requested by RMT. Bit 0
  *  corresponds to region0, and so on.
@@ -1138,7 +1138,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG register
  *  GDMA-AXI LCD_CAM read permission control register
  */
-#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x174)
+#define PMS_DMA_AXI_PDMA_LCDCAM_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x174)
 /** PMS_DMA_AXI_PDMA_LCDCAM_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to read 32 address ranges requested by LCD_CAM. Bit
  *  0 corresponds to region0, and so on.
@@ -1153,7 +1153,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG register
  *  GDMA-AXI LCD_CAM write permission control register
  */
-#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x178)
+#define PMS_DMA_AXI_PDMA_LCDCAM_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x178)
 /** PMS_DMA_AXI_PDMA_LCDCAM_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to write 32 address ranges requested by LCD_CAM. Bit
  *  0 corresponds to region0, and so on.
@@ -1168,7 +1168,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG register
  *  GDMA-AXI GPSPI2 read permission control register
  */
-#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x17c)
+#define PMS_DMA_AXI_PDMA_GPSPI2_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x17c)
 /** PMS_DMA_AXI_PDMA_GPSPI2_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI2. Bit
  *  0 corresponds to region0, and so on.
@@ -1183,7 +1183,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG register
  *  GDMA-AXI GPSPI2 write permission control register
  */
-#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x180)
+#define PMS_DMA_AXI_PDMA_GPSPI2_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x180)
 /** PMS_DMA_AXI_PDMA_GPSPI2_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI2. Bit
  *  0 corresponds to region0, and so on.
@@ -1198,7 +1198,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG register
  *  GDMA-AXI GPSPI3 read permission control register
  */
-#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x184)
+#define PMS_DMA_AXI_PDMA_GPSPI3_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x184)
 /** PMS_DMA_AXI_PDMA_GPSPI3_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to read 32 address ranges requested by GP-SPI3. Bit
  *  0 corresponds to region0, and so on.
@@ -1213,7 +1213,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG register
  *  AXI PDMA GPSPI3 write permission control register
  */
-#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x188)
+#define PMS_DMA_AXI_PDMA_GPSPI3_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x188)
 /** PMS_DMA_AXI_PDMA_GPSPI3_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to write 32 address ranges requested by GP-SPI3. Bit
  *  0 corresponds to region0, and so on.
@@ -1228,7 +1228,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG register
  *  GDMA-AXI PARLIO read permission control register
  */
-#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x18c)
+#define PMS_DMA_AXI_PDMA_PARLIO_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x18c)
 /** PMS_DMA_AXI_PDMA_PARLIO_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to read 32 address ranges requested by PARLIO
  *  (Parallel IO Controller). Bit 0 corresponds to region0, and so on.
@@ -1243,7 +1243,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG register
  *  GDMA-AXI PARLIO write permission control register
  */
-#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x190)
+#define PMS_DMA_AXI_PDMA_PARLIO_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x190)
 /** PMS_DMA_AXI_PDMA_PARLIO_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to write 32 address ranges requested by PARLIO. Bit
  *  0 corresponds to region0, and so on.
@@ -1258,7 +1258,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_AES_R_PMS_REG register
  *  GDMA-AXI AES read permission control register
  */
-#define PMS_DMA_AXI_PDMA_AES_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x194)
+#define PMS_DMA_AXI_PDMA_AES_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x194)
 /** PMS_DMA_AXI_PDMA_AES_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to read 32 address ranges requested by AES. Bit 0
  *  corresponds to region0, and so on.
@@ -1273,7 +1273,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_AES_W_PMS_REG register
  *  GDMA-AXI AES write permission control register
  */
-#define PMS_DMA_AXI_PDMA_AES_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x198)
+#define PMS_DMA_AXI_PDMA_AES_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x198)
 /** PMS_DMA_AXI_PDMA_AES_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to write 32 address ranges requested by AES. Bit 0
  *  corresponds to region0, and so on.
@@ -1288,7 +1288,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_SHA_R_PMS_REG register
  *  GDMA-AXI SHA read permission control register
  */
-#define PMS_DMA_AXI_PDMA_SHA_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x19c)
+#define PMS_DMA_AXI_PDMA_SHA_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x19c)
 /** PMS_DMA_AXI_PDMA_SHA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to read 32 address ranges requested by SHA. Bit 0
  *  corresponds to region0, and so on.
@@ -1303,7 +1303,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_SHA_W_PMS_REG register
  *  GDMA-AXI SHA write permission control register
  */
-#define PMS_DMA_AXI_PDMA_SHA_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x1a0)
+#define PMS_DMA_AXI_PDMA_SHA_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x1a0)
 /** PMS_DMA_AXI_PDMA_SHA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to write 32 address ranges requested by SHA. Bit 0
  *  corresponds to region0, and so on.
@@ -1318,7 +1318,7 @@ extern "C" {
 /** PMS_DMA_DMA2D_JPEG_PMS_R_REG register
  *  2D-DMA JPEG read permission control register
  */
-#define PMS_DMA_DMA2D_JPEG_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1a4)
+#define PMS_DMA_DMA2D_JPEG_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1a4)
 /** PMS_DMA_DMA2D_JPEG_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures 2D-DMA permission to read 32 address ranges requested by JPEG. Bit 0
  *  corresponds to region0, and so on.
@@ -1333,7 +1333,7 @@ extern "C" {
 /** PMS_DMA_DMA2D_JPEG_PMS_W_REG register
  *  2D-DMA JPEG write permission control register
  */
-#define PMS_DMA_DMA2D_JPEG_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1a8)
+#define PMS_DMA_DMA2D_JPEG_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1a8)
 /** PMS_DMA_DMA2D_JPEG_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures 2D-DMA permission to write 32 address ranges requested by JPEG. Bit 0
  *  corresponds to region0, and so on.
@@ -1348,7 +1348,7 @@ extern "C" {
 /** PMS_DMA_USB_PMS_R_REG register
  *  High-speed USB 2.0 OTG read permission control register
  */
-#define PMS_DMA_USB_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1ac)
+#define PMS_DMA_USB_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ac)
 /** PMS_DMA_USB_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for high-speed USB 2.0 OTG to access 32 address ranges.
  *  Bit 0 corresponds to region0, and so on.
@@ -1363,7 +1363,7 @@ extern "C" {
 /** PMS_DMA_USB_PMS_W_REG register
  *  High-speed USB 2.0 OTG write permission control register
  */
-#define PMS_DMA_USB_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1b0)
+#define PMS_DMA_USB_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1b0)
 /** PMS_DMA_USB_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for high-speed USB 2.0 OTG to access 32 address ranges.
  *  Bit 0 corresponds to region0, and so on.
@@ -1378,7 +1378,7 @@ extern "C" {
 /** PMS_DMA_GMAC_PMS_R_REG register
  *  EMAC read permission control register
  */
-#define PMS_DMA_GMAC_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1b4)
+#define PMS_DMA_GMAC_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1b4)
 /** PMS_DMA_GMAC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for EMAC to access 32 address ranges. Bit 0 corresponds
  *  to region0, and so on.
@@ -1393,7 +1393,7 @@ extern "C" {
 /** PMS_DMA_GMAC_PMS_W_REG register
  *  EMAC write permission control register
  */
-#define PMS_DMA_GMAC_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1b8)
+#define PMS_DMA_GMAC_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1b8)
 /** PMS_DMA_GMAC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for EMAC to access 32 address ranges. Bit 0 corresponds
  *  to region0, and so on.
@@ -1408,7 +1408,7 @@ extern "C" {
 /** PMS_DMA_SDMMC_PMS_R_REG register
  *  SDMMC read permission control register
  */
-#define PMS_DMA_SDMMC_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1bc)
+#define PMS_DMA_SDMMC_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1bc)
 /** PMS_DMA_SDMMC_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for SDMMC to access 32 address ranges. Bit 0 corresponds
  *  to region0, and so on.
@@ -1423,7 +1423,7 @@ extern "C" {
 /** PMS_DMA_SDMMC_PMS_W_REG register
  *  SDMMC write permission control register
  */
-#define PMS_DMA_SDMMC_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1c0)
+#define PMS_DMA_SDMMC_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1c0)
 /** PMS_DMA_SDMMC_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for SDMMC to access 32 address ranges. Bit 0
  *  corresponds to region0, and so on.
@@ -1438,7 +1438,7 @@ extern "C" {
 /** PMS_DMA_USBOTG11_PMS_R_REG register
  *  Full-speed USB 2.0 OTG full-speed read permission control register
  */
-#define PMS_DMA_USBOTG11_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1c4)
+#define PMS_DMA_USBOTG11_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1c4)
 /** PMS_DMA_USBOTG11_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for full-speed USB 2.0 OTG to access 32 address ranges.
  *  Bit 0 corresponds to region0, and so on.
@@ -1453,7 +1453,7 @@ extern "C" {
 /** PMS_DMA_USBOTG11_PMS_W_REG register
  *  Full-speed USB 2.0 OTG full-speed write permission control register
  */
-#define PMS_DMA_USBOTG11_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1c8)
+#define PMS_DMA_USBOTG11_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1c8)
 /** PMS_DMA_USBOTG11_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for full-speed USB 2.0 OTG to access 32 address ranges.
  *  Bit 0 corresponds to region0, and so on.
@@ -1468,7 +1468,7 @@ extern "C" {
 /** PMS_DMA_TRACE0_PMS_R_REG register
  *  TRACE0 read permission control register
  */
-#define PMS_DMA_TRACE0_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1cc)
+#define PMS_DMA_TRACE0_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1cc)
 /** PMS_DMA_TRACE0_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for TRACE0 to access 32 address ranges. Bit 0
  *  corresponds to region0, and so on.
@@ -1483,7 +1483,7 @@ extern "C" {
 /** PMS_DMA_TRACE0_PMS_W_REG register
  *  TRACE0 write permission control register
  */
-#define PMS_DMA_TRACE0_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1d0)
+#define PMS_DMA_TRACE0_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1d0)
 /** PMS_DMA_TRACE0_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for TRACE0 to access 32 address ranges. Bit 0
  *  corresponds to region0, and so on.
@@ -1498,7 +1498,7 @@ extern "C" {
 /** PMS_DMA_TRACE1_PMS_R_REG register
  *  TRACE1 read permission control register
  */
-#define PMS_DMA_TRACE1_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1d4)
+#define PMS_DMA_TRACE1_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1d4)
 /** PMS_DMA_TRACE1_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for TRACE1 to access 32 address ranges. Bit 0
  *  corresponds to region0, and so on.
@@ -1513,7 +1513,7 @@ extern "C" {
 /** PMS_DMA_TRACE1_PMS_W_REG register
  *  TRACE1 write permission control register
  */
-#define PMS_DMA_TRACE1_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1d8)
+#define PMS_DMA_TRACE1_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1d8)
 /** PMS_DMA_TRACE1_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for TRACE1 to access 32 address ranges. Bit 0
  *  corresponds to region0, and so on.
@@ -1528,7 +1528,7 @@ extern "C" {
 /** PMS_DMA_L2MEM_MON_PMS_R_REG register
  *  L2MEM Monitor read permission control register
  */
-#define PMS_DMA_L2MEM_MON_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1dc)
+#define PMS_DMA_L2MEM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1dc)
 /** PMS_DMA_L2MEM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for L2MEM MON. Each bit corresponds to a region. Bit 0
  *  corresponds to region0, and so on.
@@ -1543,7 +1543,7 @@ extern "C" {
 /** PMS_DMA_L2MEM_MON_PMS_W_REG register
  *  L2MEM Monitor write permission control register
  */
-#define PMS_DMA_L2MEM_MON_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1e0)
+#define PMS_DMA_L2MEM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e0)
 /** PMS_DMA_L2MEM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for L2MEM monitor to access 32 address ranges. Bit 0
  *  corresponds to region0, and so on.
@@ -1558,7 +1558,7 @@ extern "C" {
 /** PMS_DMA_TCM_MON_PMS_R_REG register
  *  TCM Monitor read permission control register
  */
-#define PMS_DMA_TCM_MON_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1e4)
+#define PMS_DMA_TCM_MON_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1e4)
 /** PMS_DMA_TCM_MON_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for TCM MON. Each bit corresponds to a region. Bit 0
  *  corresponds to region0, and so on.
@@ -1573,7 +1573,7 @@ extern "C" {
 /** PMS_DMA_TCM_MON_PMS_W_REG register
  *  TCM Monitor write permission control register
  */
-#define PMS_DMA_TCM_MON_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1e8)
+#define PMS_DMA_TCM_MON_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1e8)
 /** PMS_DMA_TCM_MON_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for TCM monitor to access 32 address ranges. Bit 0
  *  corresponds to region0, and so on.
@@ -1588,7 +1588,7 @@ extern "C" {
 /** PMS_DMA_REGDMA_PMS_R_REG register
  *  REGDMA read permission control register
  */
-#define PMS_DMA_REGDMA_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1ec)
+#define PMS_DMA_REGDMA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1ec)
 /** PMS_DMA_REGDMA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for REGDMA. Each bit corresponds to a region. Bit 0
  *  corresponds to region0, and so on.
@@ -1603,7 +1603,7 @@ extern "C" {
 /** PMS_DMA_REGDMA_PMS_W_REG register
  *  REGDMA write permission control register
  */
-#define PMS_DMA_REGDMA_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x1f0)
+#define PMS_DMA_REGDMA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x1f0)
 /** PMS_DMA_REGDMA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for REGDMA. Each bit corresponds to a region. Bit 0
  *  corresponds to region0, and so on.
@@ -1618,7 +1618,7 @@ extern "C" {
 /** PMS_DMA_H264_PMS_R_REG register
  *  H264 DMA read permission control register
  */
-#define PMS_DMA_H264_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x1fc)
+#define PMS_DMA_H264_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x1fc)
 /** PMS_DMA_H264_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures read permission for H264 DMA to access 32 address ranges. Bit 0
  *  corresponds to region0, and so on.
@@ -1633,7 +1633,7 @@ extern "C" {
 /** PMS_DMA_H264_PMS_W_REG register
  *  H264 DMA write permission control register
  */
-#define PMS_DMA_H264_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x200)
+#define PMS_DMA_H264_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x200)
 /** PMS_DMA_H264_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures write permission for H264 DMA to access 32 address ranges. Bit 0
  *  corresponds to region0, and so on.
@@ -1648,7 +1648,7 @@ extern "C" {
 /** PMS_DMA_DMA2D_PPA_PMS_R_REG register
  *  2D-DMA PPA read permission control register
  */
-#define PMS_DMA_DMA2D_PPA_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x204)
+#define PMS_DMA_DMA2D_PPA_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x204)
 /** PMS_DMA_DMA2D_PPA_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures 2D-DMA permission to read 32 address ranges requested by PPA
  *  (Pixel-Processing Accelerator). Bit 0 corresponds to region0, and so on.
@@ -1663,7 +1663,7 @@ extern "C" {
 /** PMS_DMA_DMA2D_PPA_PMS_W_REG register
  *  2D-DMA PPA write permission control register
  */
-#define PMS_DMA_DMA2D_PPA_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x208)
+#define PMS_DMA_DMA2D_PPA_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x208)
 /** PMS_DMA_DMA2D_PPA_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures 2D-DMA permission to write 32 address ranges requested by PPA. Bit 0
  *  corresponds to region0, and so on.
@@ -1678,7 +1678,7 @@ extern "C" {
 /** PMS_DMA_DMA2D_DUMMY_PMS_R_REG register
  *  2D-DMA dummy read permission control register
  */
-#define PMS_DMA_DMA2D_DUMMY_PMS_R_REG (DR_REG_PMS_DMA_BASE + 0x20c)
+#define PMS_DMA_DMA2D_DUMMY_PMS_R_REG (DR_REG_DMA_PMS_BASE + 0x20c)
 /** PMS_DMA_DMA2D_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures 2D-DMA permission to read 32 address ranges requested by Dummy. Bit 0
  *  corresponds to region0, and so on.
@@ -1693,7 +1693,7 @@ extern "C" {
 /** PMS_DMA_DMA2D_DUMMY_PMS_W_REG register
  *  2D-DMA dummy write permission control register
  */
-#define PMS_DMA_DMA2D_DUMMY_PMS_W_REG (DR_REG_PMS_DMA_BASE + 0x210)
+#define PMS_DMA_DMA2D_DUMMY_PMS_W_REG (DR_REG_DMA_PMS_BASE + 0x210)
 /** PMS_DMA_DMA2D_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures 2D-DMA permission to write 32 address ranges requested by Dummy. Bit 0
  *  corresponds to region0, and so on.
@@ -1708,7 +1708,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG register
  *  GDMA-AHB dummy read permission control register
  */
-#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x214)
+#define PMS_DMA_AHB_PDMA_DUMMY_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x214)
 /** PMS_DMA_AHB_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to read 32 address ranges requested by Dummy. Bit 0
  *  corresponds to region0, and so on.
@@ -1723,7 +1723,7 @@ extern "C" {
 /** PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG register
  *  GDMA-AHB dummy write permission control register
  */
-#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x218)
+#define PMS_DMA_AHB_PDMA_DUMMY_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x218)
 /** PMS_DMA_AHB_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AHB permission to write 32 address ranges requested by Dummy. Bit 0
  *  corresponds to region0, and so on.
@@ -1738,7 +1738,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG register
  *  GDMA-AXI dummy read permission control register
  */
-#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG (DR_REG_PMS_DMA_BASE + 0x21c)
+#define PMS_DMA_AXI_PDMA_DUMMY_R_PMS_REG (DR_REG_DMA_PMS_BASE + 0x21c)
 /** PMS_DMA_AXI_PDMA_DUMMY_R_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to read 32 address ranges requested by Dummy. Bit 0
  *  corresponds to region0, and so on.
@@ -1753,7 +1753,7 @@ extern "C" {
 /** PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG register
  *  GDMA-AXI dummy write permission control register
  */
-#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG (DR_REG_PMS_DMA_BASE + 0x220)
+#define PMS_DMA_AXI_PDMA_DUMMY_W_PMS_REG (DR_REG_DMA_PMS_BASE + 0x220)
 /** PMS_DMA_AXI_PDMA_DUMMY_W_PMS : R/W; bitpos: [31:0]; default: 4294967295;
  *  Configures GDMA-AXI permission to write 32 address ranges requested by Dummy. Bit 0
  *  corresponds to region0, and so on.
diff --git a/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h b/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h
index e4135f4f89..903bfc178b 100644
--- a/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h
+++ b/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** PMS_HP2LP_PERI_PMS_DATE_REG register
  *  Version control register
  */
-#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
+#define PMS_HP2LP_PERI_PMS_DATE_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x0)
 /** PMS_HP2LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
  *  Version control register
  */
@@ -26,7 +26,7 @@ extern "C" {
 /** PMS_HP2LP_PERI_PMS_CLK_EN_REG register
  *  Clock gating register
  */
-#define PMS_HP2LP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
+#define PMS_HP2LP_PERI_PMS_CLK_EN_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x4)
 /** PMS_HP2LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Configures whether to keep the clock always on.
  *  0: Enable automatic clock gating
@@ -40,7 +40,7 @@ extern "C" {
 /** PMS_HP_CORE0_MM_PMS_REG0_REG register
  *  Permission control register0 for HP CPU0 in machine mode
  */
-#define PMS_HP_CORE0_MM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
+#define PMS_HP_CORE0_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x8)
 /** PMS_HP_CORE0_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in machine mode has permission to access LP System
  *  Registers.
@@ -267,7 +267,7 @@ extern "C" {
 /** PMS_HP_CORE0_UM_PMS_REG0_REG register
  *  Permission control register0 for HP CPU0 in user mode
  */
-#define PMS_HP_CORE0_UM_PMS_REG0_REG (DR_REG_PMS_BASE + 0xc)
+#define PMS_HP_CORE0_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0xc)
 /** PMS_HP_CORE0_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in user mode has permission to access LP System
  *  Registers.
@@ -492,7 +492,7 @@ extern "C" {
 /** PMS_HP_CORE1_MM_PMS_REG0_REG register
  *  Permission control register0 for HP CPU1 in machine mode
  */
-#define PMS_HP_CORE1_MM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x10)
+#define PMS_HP_CORE1_MM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x10)
 /** PMS_HP_CORE1_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in machine mode has permission to access LP System
  *  Registers.
@@ -719,7 +719,7 @@ extern "C" {
 /** PMS_HP_CORE1_UM_PMS_REG0_REG register
  *  Permission control register0 for HP CPU1 in user mode
  */
-#define PMS_HP_CORE1_UM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x14)
+#define PMS_HP_CORE1_UM_PMS_REG0_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x14)
 /** PMS_HP_CORE1_UM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in user mode has permission to access LP System
  *  Registers.
@@ -944,7 +944,7 @@ extern "C" {
 /** PMS_REGDMA_LP_PERI_PMS_REG register
  *  LP Peripheral Permission register for REGDMA
  */
-#define PMS_REGDMA_LP_PERI_PMS_REG (DR_REG_PMS_BASE + 0x18)
+#define PMS_REGDMA_LP_PERI_PMS_REG (DR_REG_HP2LP_PERI_PMS_BASE + 0x18)
 /** PMS_REGDMA_PERI_LP_SRAM_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether REGDMA has permission to access LP SRAM.
  *  0: Not allowed
diff --git a/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h
index c7c82bec2f..a097d8e43f 100644
--- a/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h
+++ b/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** PMS_HP_PERI_PMS_DATE_REG register
  *  Version control register
  */
-#define PMS_HP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
+#define PMS_HP_PERI_PMS_DATE_REG (DR_REG_HP_PERI_PMS_BASE + 0x0)
 /** PMS_HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
  *  Version control register.
  */
@@ -26,7 +26,7 @@ extern "C" {
 /** PMS_HP_PERI_PMS_CLK_EN_REG register
  *  Clock gating register
  */
-#define PMS_HP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
+#define PMS_HP_PERI_PMS_CLK_EN_REG (DR_REG_HP_PERI_PMS_BASE + 0x4)
 /** PMS_HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Configures whether to keep the clock always on.
  *  0: Enable automatic clock gating
@@ -40,7 +40,7 @@ extern "C" {
 /** PMS_CORE0_MM_HP_PERI_PMS_REG0_REG register
  *  Permission control register0 for HP CPU0 in machine mode
  */
-#define PMS_CORE0_MM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
+#define PMS_CORE0_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x8)
 /** PMS_CORE0_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in machine mode has permission to access external RAM
  *  without going through cache.
@@ -140,7 +140,7 @@ extern "C" {
 /** PMS_CORE0_MM_HP_PERI_PMS_REG1_REG register
  *  Permission control register1 for HP CPU0 in machine mode
  */
-#define PMS_CORE0_MM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0xc)
+#define PMS_CORE0_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0xc)
 /** PMS_CORE0_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in machine mode has permission to access HP high-speed
  *  USB 2.0 OTG.
@@ -421,7 +421,7 @@ extern "C" {
 /** PMS_CORE0_MM_HP_PERI_PMS_REG2_REG register
  *  Permission control register2 for HP CPU0 in machine mode
  */
-#define PMS_CORE0_MM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x10)
+#define PMS_CORE0_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x10)
 /** PMS_CORE0_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in machine mode has permission to access HP MCPWM0.
  *  0: Not allowed
@@ -702,7 +702,7 @@ extern "C" {
 /** PMS_CORE0_MM_HP_PERI_PMS_REG3_REG register
  *  Permission control register3 for HP CPU0 in machine mode
  */
-#define PMS_CORE0_MM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x14)
+#define PMS_CORE0_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x14)
 /** PMS_CORE0_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in machine mode has permission to access HP GPIO Matrix.
  *  0: Not allowed
@@ -754,7 +754,7 @@ extern "C" {
 /** PMS_CORE0_UM_HP_PERI_PMS_REG0_REG register
  *  Permission control register0 for HP CPU0 in user mode
  */
-#define PMS_CORE0_UM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x18)
+#define PMS_CORE0_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x18)
 /** PMS_CORE0_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in user mode has permission to access external RAM
  *  without going through cache.
@@ -853,7 +853,7 @@ extern "C" {
 /** PMS_CORE0_UM_HP_PERI_PMS_REG1_REG register
  *  Permission control register1 for HP CPU0 in user mode
  */
-#define PMS_CORE0_UM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0x1c)
+#define PMS_CORE0_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x1c)
 /** PMS_CORE0_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in user mode has permission to access HP high-speed USB
  *  2.0 OTG.
@@ -1128,7 +1128,7 @@ extern "C" {
 /** PMS_CORE0_UM_HP_PERI_PMS_REG2_REG register
  *  Permission control register2 for HP CPU0 in user mode
  */
-#define PMS_CORE0_UM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x20)
+#define PMS_CORE0_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x20)
 /** PMS_CORE0_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in user mode has permission to access HP MCPWM0.
  *  0: Not allowed
@@ -1407,7 +1407,7 @@ extern "C" {
 /** PMS_CORE0_UM_HP_PERI_PMS_REG3_REG register
  *  Permission control register3 for HP CPU0 in user mode
  */
-#define PMS_CORE0_UM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x24)
+#define PMS_CORE0_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x24)
 /** PMS_CORE0_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU0 in user mode has permission to access HP GPIO Matrix.
  *  0: Not allowed
@@ -1458,7 +1458,7 @@ extern "C" {
 /** PMS_CORE1_MM_HP_PERI_PMS_REG0_REG register
  *  Permission control register0 for HP CPU1 in machine mode
  */
-#define PMS_CORE1_MM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x28)
+#define PMS_CORE1_MM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x28)
 /** PMS_CORE1_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in machine mode has permission to access external RAM
  *  without going through cache.
@@ -1558,7 +1558,7 @@ extern "C" {
 /** PMS_CORE1_MM_HP_PERI_PMS_REG1_REG register
  *  Permission control register1 for HP CPU1 in machine mode
  */
-#define PMS_CORE1_MM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0x2c)
+#define PMS_CORE1_MM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x2c)
 /** PMS_CORE1_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in machine mode has permission to access HP high-speed
  *  USB 2.0 OTG.
@@ -1839,7 +1839,7 @@ extern "C" {
 /** PMS_CORE1_MM_HP_PERI_PMS_REG2_REG register
  *  Permission control register2 for HP CPU1 in machine mode
  */
-#define PMS_CORE1_MM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x30)
+#define PMS_CORE1_MM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x30)
 /** PMS_CORE1_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in machine mode has permission to access HP MCPWM0.
  *  0: Not allowed
@@ -2120,7 +2120,7 @@ extern "C" {
 /** PMS_CORE1_MM_HP_PERI_PMS_REG3_REG register
  *  Permission control register3 for HP CPU1 in machine mode
  */
-#define PMS_CORE1_MM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x34)
+#define PMS_CORE1_MM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x34)
 /** PMS_CORE1_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in machine mode has permission to access HP GPIO Matrix.
  *  0: Not allowed
@@ -2172,7 +2172,7 @@ extern "C" {
 /** PMS_CORE1_UM_HP_PERI_PMS_REG0_REG register
  *  Permission control register0 for HP CPU1 in user mode
  */
-#define PMS_CORE1_UM_HP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x38)
+#define PMS_CORE1_UM_HP_PERI_PMS_REG0_REG (DR_REG_HP_PERI_PMS_BASE + 0x38)
 /** PMS_CORE1_UM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in user mode has permission to access external RAM
  *  without going through cache.
@@ -2271,7 +2271,7 @@ extern "C" {
 /** PMS_CORE1_UM_HP_PERI_PMS_REG1_REG register
  *  Permission control register1 for HP CPU1 in user mode
  */
-#define PMS_CORE1_UM_HP_PERI_PMS_REG1_REG (DR_REG_PMS_BASE + 0x3c)
+#define PMS_CORE1_UM_HP_PERI_PMS_REG1_REG (DR_REG_HP_PERI_PMS_BASE + 0x3c)
 /** PMS_CORE1_UM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in user mode has permission to access HP high-speed USB
  *  2.0 OTG.
@@ -2546,7 +2546,7 @@ extern "C" {
 /** PMS_CORE1_UM_HP_PERI_PMS_REG2_REG register
  *  Permission control register2 for HP CPU1 in user mode
  */
-#define PMS_CORE1_UM_HP_PERI_PMS_REG2_REG (DR_REG_PMS_BASE + 0x40)
+#define PMS_CORE1_UM_HP_PERI_PMS_REG2_REG (DR_REG_HP_PERI_PMS_BASE + 0x40)
 /** PMS_CORE1_UM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in user mode has permission to access HP MCPWM0.
  *  0: Not allowed
@@ -2825,7 +2825,7 @@ extern "C" {
 /** PMS_CORE1_UM_HP_PERI_PMS_REG3_REG register
  *  Permission control register3 for HP CPU1 in user mode
  */
-#define PMS_CORE1_UM_HP_PERI_PMS_REG3_REG (DR_REG_PMS_BASE + 0x44)
+#define PMS_CORE1_UM_HP_PERI_PMS_REG3_REG (DR_REG_HP_PERI_PMS_BASE + 0x44)
 /** PMS_CORE1_UM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether HP CPU1 in user mode has permission to access HP GPIO Matrix.
  *  0: Not allowed
@@ -2876,7 +2876,7 @@ extern "C" {
 /** PMS_REGDMA_PERI_PMS_REG register
  *  Permission register for REGDMA
  */
-#define PMS_REGDMA_PERI_PMS_REG (DR_REG_PMS_BASE + 0x48)
+#define PMS_REGDMA_PERI_PMS_REG (DR_REG_HP_PERI_PMS_BASE + 0x48)
 /** PMS_REGDMA_PERI_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether REGDMA has permission to access all HP peripheral (including CPU
  *  peripherals).
diff --git a/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h b/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h
index 6e115cb703..ba58a6cfde 100644
--- a/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h
+++ b/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** PMS_LP2HP_PERI_PMS_DATE_REG register
  *  Version control register
  */
-#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
+#define PMS_LP2HP_PERI_PMS_DATE_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x0)
 /** PMS_LP2HP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294790;
  *  Version control register.
  */
@@ -26,7 +26,7 @@ extern "C" {
 /** PMS_LP2HP_PERI_PMS_CLK_EN_REG register
  *  Clock gating register
  */
-#define PMS_LP2HP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
+#define PMS_LP2HP_PERI_PMS_CLK_EN_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x4)
 /** PMS_LP2HP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Configures whether to keep the clock always on.
  *  0: Enable automatic clock gating.
@@ -40,7 +40,7 @@ extern "C" {
 /** PMS_LP_MM_PMS_REG0_REG register
  *  Permission control register0 for the LP CPU in machine mode
  */
-#define PMS_LP_MM_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
+#define PMS_LP_MM_PMS_REG0_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x8)
 /** PMS_LP_MM_PSRAM_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether the LP CPU in machine mode has permission to access external RAM
  *  without going through cache.
@@ -141,7 +141,7 @@ extern "C" {
 /** PMS_LP_MM_PMS_REG1_REG register
  *  Permission control register1 for the LP CPU in machine mode
  */
-#define PMS_LP_MM_PMS_REG1_REG (DR_REG_PMS_BASE + 0x30)
+#define PMS_LP_MM_PMS_REG1_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x30)
 /** PMS_LP_MM_HP_USBOTG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether the LP CPU in machine mode has permission to access HP
  *  high-speed USB 2.0 OTG.
@@ -422,7 +422,7 @@ extern "C" {
 /** PMS_LP_MM_PMS_REG2_REG register
  *  Permission control register2 for the LP CPU in machine mode
  */
-#define PMS_LP_MM_PMS_REG2_REG (DR_REG_PMS_BASE + 0xa4)
+#define PMS_LP_MM_PMS_REG2_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0xa4)
 /** PMS_LP_MM_HP_MCPWM0_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether the LP CPU in machine mode has permission to access HP MCPWM0.
  *  0: Not allowed
@@ -703,7 +703,7 @@ extern "C" {
 /** PMS_LP_MM_PMS_REG3_REG register
  *  Permission control register3 for the LP CPU in machine mode
  */
-#define PMS_LP_MM_PMS_REG3_REG (DR_REG_PMS_BASE + 0x11c)
+#define PMS_LP_MM_PMS_REG3_REG (DR_REG_LP2HP_PERI_PMS_BASE + 0x11c)
 /** PMS_LP_MM_HP_GPIO_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether the LP CPU in machine mode has permission to access HP GPIO
  *  Matrix.
diff --git a/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h b/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h
index f95a5a3b85..7074bc5236 100644
--- a/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h
+++ b/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h
@@ -14,7 +14,7 @@ extern "C" {
 /** PMS_LP_PERI_PMS_DATE_REG register
  *  Version control register
  */
-#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_PMS_BASE + 0x0)
+#define PMS_LP_PERI_PMS_DATE_REG (DR_REG_LP_PERI_PMS_BASE + 0x0)
 /** PMS_LP_PERI_PMS_DATE : R/W; bitpos: [31:0]; default: 2294537;
  *  Version control register
  */
@@ -26,7 +26,7 @@ extern "C" {
 /** PMS_LP_PERI_PMS_CLK_EN_REG register
  *  Clock gating register
  */
-#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_PMS_BASE + 0x4)
+#define PMS_LP_PERI_PMS_CLK_EN_REG (DR_REG_LP_PERI_PMS_BASE + 0x4)
 /** PMS_LP_PERI_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Configures whether to keep the clock always on.
  *  0: Enable automatic clock gating
@@ -40,7 +40,7 @@ extern "C" {
 /** PMS_LP_MM_LP_PERI_PMS_REG0_REG register
  *  Permission control register0 for LP CPU in machine mode
  */
-#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_PMS_BASE + 0x8)
+#define PMS_LP_MM_LP_PERI_PMS_REG0_REG (DR_REG_LP_PERI_PMS_BASE + 0x8)
 /** PMS_LP_MM_LP_SYSREG_ALLOW : R/W; bitpos: [0]; default: 1;
  *  Configures whether LP CPU in machine mode has permission to access LP system
  *  registers.
@@ -272,7 +272,7 @@ extern "C" {
 /** PMS_PERI_REGION0_LOW_REG register
  *  Region0 start address configuration register
  */
-#define PMS_PERI_REGION0_LOW_REG (DR_REG_PMS_BASE + 0xc)
+#define PMS_PERI_REGION0_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0xc)
 /** PMS_PERI_REGION0_LOW : R/W; bitpos: [31:2]; default: 0;
  *  Configures the high 30 bits of the start address of peripheral register's region0.
  */
@@ -284,7 +284,7 @@ extern "C" {
 /** PMS_PERI_REGION0_HIGH_REG register
  *  Region0 end address configuration register
  */
-#define PMS_PERI_REGION0_HIGH_REG (DR_REG_PMS_BASE + 0x10)
+#define PMS_PERI_REGION0_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x10)
 /** PMS_PERI_REGION0_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
  *  Configures the high 30 bits of the end address of peripheral register's region0.
  */
@@ -296,7 +296,7 @@ extern "C" {
 /** PMS_PERI_REGION1_LOW_REG register
  *  Region1 start address configuration register
  */
-#define PMS_PERI_REGION1_LOW_REG (DR_REG_PMS_BASE + 0x14)
+#define PMS_PERI_REGION1_LOW_REG (DR_REG_LP_PERI_PMS_BASE + 0x14)
 /** PMS_PERI_REGION1_LOW : R/W; bitpos: [31:2]; default: 0;
  *  Configures the high 30 bits of the start address of peripheral register's region1.
  */
@@ -308,7 +308,7 @@ extern "C" {
 /** PMS_PERI_REGION1_HIGH_REG register
  *  Region1 end address configuration register
  */
-#define PMS_PERI_REGION1_HIGH_REG (DR_REG_PMS_BASE + 0x18)
+#define PMS_PERI_REGION1_HIGH_REG (DR_REG_LP_PERI_PMS_BASE + 0x18)
 /** PMS_PERI_REGION1_HIGH : R/W; bitpos: [31:2]; default: 1073741823;
  *  Configures the high 30 bits of the end address of peripheral register's region1.
  */
@@ -320,7 +320,7 @@ extern "C" {
 /** PMS_PERI_REGION_PMS_REG register
  *  Permission register of  region
  */
-#define PMS_PERI_REGION_PMS_REG (DR_REG_PMS_BASE + 0x1c)
+#define PMS_PERI_REGION_PMS_REG (DR_REG_LP_PERI_PMS_BASE + 0x1c)
 /** PMS_LP_CORE_REGION_PMS : R/W; bitpos: [1:0]; default: 3;
  *  Configures whether LP core in machine mode has permission to access address region0
  *  and address region1. Bit0 corresponds to region0 and bit1 corresponds to region1.