Merge branch 'bugfix/efuse_timesettings_for_esp32s3_v4.4' into 'release/v4.4'

efuse: Fixes eFuse timesettings issue on esp32S3 (v4.4)

See merge request espressif/esp-idf!17177

components/efuse/esp32s3/esp_efuse_utility.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -51,19 +51,44 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = {
     {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
 };
 
-#ifndef CONFIG_EFUSE_VIRTUAL
 // Update Efuse timing configuration
 static esp_err_t esp_efuse_set_timing(void)
 {
-    uint32_t clock_hz = esp_clk_apb_freq();
+    REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x190);
-    return ets_efuse_set_timing(clock_hz) ? ESP_FAIL : ESP_OK;
+    return ESP_OK;
+}
+
+static void efuse_read(void)
+{
+    esp_efuse_set_timing();
+    REG_WRITE(EFUSE_CONF_REG, EFUSE_READ_OP_CODE);
+    REG_WRITE(EFUSE_CMD_REG, EFUSE_READ_CMD);
+
+    while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { }
+    /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
+    while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_READ_CMD) != 0) { }
+}
+
+#ifndef CONFIG_EFUSE_VIRTUAL
+static void efuse_program(esp_efuse_block_t block)
+{
+    esp_efuse_set_timing();
+
+    REG_WRITE(EFUSE_CONF_REG, EFUSE_WRITE_OP_CODE);
+
+    REG_WRITE(EFUSE_CMD_REG, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
+
+    while (REG_GET_BIT(EFUSE_CMD_REG, EFUSE_PGM_CMD) != 0) { };
+
+    ets_efuse_clear_program_registers();
+    efuse_read();
 }
 #endif // ifndef CONFIG_EFUSE_VIRTUAL
 
 // Efuse read operation: copies data from physical efuses to efuse read registers.
 void esp_efuse_utility_clear_program_registers(void)
 {
-    ets_efuse_read();
+    efuse_read();
     ets_efuse_clear_program_registers();
 }
 
@@ -97,7 +122,7 @@ void esp_efuse_utility_burn_chip(void)
                     }
                     int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
                     memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
-                    ets_efuse_program(num_block);
+                    efuse_program(num_block);
                     break;
                 }
             }

components/esptool_py/project_include.cmake

@@ -6,6 +6,9 @@ idf_build_get_property(python PYTHON)
 idf_build_get_property(idf_path IDF_PATH)
 
 set(chip_model ${target})
+if(target STREQUAL "esp32h2")
+    set(chip_model esp32h2beta1)
+endif()
 
 set(ESPTOOLPY ${python} "$ENV{ESPTOOL_WRAPPER}" "${CMAKE_CURRENT_LIST_DIR}/esptool/esptool.py" --chip ${chip_model})
 set(ESPSECUREPY ${python} "${CMAKE_CURRENT_LIST_DIR}/esptool/espsecure.py")

components/soc/esp32s3/include/soc/efuse_reg.h

@@ -1,16 +1,8 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 #ifndef _SOC_EFUSE_REG_H_
 #define _SOC_EFUSE_REG_H_
 
@@ -1748,6 +1740,9 @@ ing user data failed and the number of error bytes is over 6..*/
 #define EFUSE_OP_CODE_V  0xFFFF
 #define EFUSE_OP_CODE_S  0
 
+#define EFUSE_WRITE_OP_CODE 0x5a5a
+#define EFUSE_READ_OP_CODE  0x5aa5
+
 #define EFUSE_STATUS_REG          (DR_REG_EFUSE_BASE + 0x1D0)
 /* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */
 /*description: Indicates the number of error bits during programming BLOCK0..*/