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fix(esp_system): fix possible cache_error by another core accessing flash in esp_restart

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wuzhenghui
2025-03-06 21:02:37 +08:00
parent 31d1ceb29b
commit f99c3c6343
1 changed files with 5 additions and 5 deletions
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10
components/esp_system/port/soc/esp32s3/system_internal.c
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@ -1,6 +1,6 @@
/* /*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -101,10 +101,6 @@ void IRAM_ATTR esp_restart_noos(void)
} }
#endif #endif
// Disable cache
Cache_Disable_ICache();
Cache_Disable_DCache();
// Reset and stall the other CPU. // Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i // CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter // instruction. This would cause memory pool to be locked by arbiter
@ -116,6 +112,10 @@ void IRAM_ATTR esp_restart_noos(void)
esp_cpu_stall(other_core_id); esp_cpu_stall(other_core_id);
#endif #endif
// Disable cache
Cache_Disable_ICache();
Cache_Disable_DCache();
// 2nd stage bootloader reconfigures SPI flash signals. // 2nd stage bootloader reconfigures SPI flash signals.
// Reset them to the defaults expected by ROM. // Reset them to the defaults expected by ROM.
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);