diff --git a/components/esp_system/include/esp_private/panic_internal.h b/components/esp_system/include/esp_private/panic_internal.h index d9fadc3360..3cb356f54c 100644 --- a/components/esp_system/include/esp_private/panic_internal.h +++ b/components/esp_system/include/esp_private/panic_internal.h @@ -88,6 +88,8 @@ uint32_t panic_get_cause(const void* frame); void panic_prepare_frame_from_ctx(void* frame); +void panic_clear_active_interrupts(const void* frame); + #ifdef __cplusplus } #endif diff --git a/components/esp_system/panic.c b/components/esp_system/panic.c index e9defe2006..4e0afbe5c9 100644 --- a/components/esp_system/panic.c +++ b/components/esp_system/panic.c @@ -391,6 +391,9 @@ void esp_panic_handler(panic_info_t *info) PANIC_INFO_DUMP(info, state); panic_print_str("\r\n"); + // Now, after all panic info was printed we can clear active interrupts + panic_clear_active_interrupts(info->frame); + /* No matter if we come here from abort or an exception, this variable must be reset. * Else, any exception/error occurring during the current panic handler would considered * an abort. Do this after PANIC_INFO_DUMP(info, state) as it also checks this variable. diff --git a/components/esp_system/port/arch/riscv/panic_arch.c b/components/esp_system/port/arch/riscv/panic_arch.c index 78040cffe4..e76942d93a 100644 --- a/components/esp_system/port/arch/riscv/panic_arch.c +++ b/components/esp_system/port/arch/riscv/panic_arch.c @@ -374,3 +374,10 @@ void panic_prepare_frame_from_ctx(void* frame) ((RvExcFrame *)frame)->mhartid = RV_READ_CSR(mhartid); } + +void panic_clear_active_interrupts(const void *frame) +{ + if (((RvExcFrame *)frame)->mcause == ETS_CACHEERR_INUM) { + esp_cache_err_clear_active_err(); + } +} diff --git a/components/esp_system/port/arch/xtensa/panic_arch.c b/components/esp_system/port/arch/xtensa/panic_arch.c index 89656c284d..078e1609a2 100644 --- a/components/esp_system/port/arch/xtensa/panic_arch.c +++ b/components/esp_system/port/arch/xtensa/panic_arch.c @@ -343,3 +343,9 @@ void panic_prepare_frame_from_ctx(void* frame) /* Nothing to cleanup on xtensa */ (void)frame; } + +void panic_clear_active_interrupts(const void *frame) +{ + /* Nothing to cleanup on xtensa */ + (void)frame; +} diff --git a/components/esp_system/port/include/private/esp_private/cache_err_int.h b/components/esp_system/port/include/private/esp_private/cache_err_int.h index c359ea7d5a..a1c1acfe5a 100644 --- a/components/esp_system/port/include/private/esp_private/cache_err_int.h +++ b/components/esp_system/port/include/private/esp_private/cache_err_int.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -58,6 +58,12 @@ void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info); */ bool esp_cache_err_has_active_err(void); +/** + * @brief Clear any cache errors interrupt + * + */ +void esp_cache_err_clear_active_err(void); + #if SOC_CACHE_ACS_INVALID_STATE_ON_PANIC /** * @brief Saves and clears active access errors diff --git a/components/esp_system/port/soc/esp32c2/cache_err_int.c b/components/esp_system/port/soc/esp32c2/cache_err_int.c index 24f264eef1..a674d40a4a 100644 --- a/components/esp_system/port/soc/esp32c2/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c2/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -134,6 +134,12 @@ bool esp_cache_err_has_active_err(void) return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK) || cache_ll_l1_get_illegal_error_intr_status(0, CACHE_LL_L1_ILG_EVENT_MASK); } +void esp_cache_err_clear_active_err(void) +{ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32c3/cache_err_int.c b/components/esp_system/port/soc/esp32c3/cache_err_int.c index 2c8e560804..befe0fe4f2 100644 --- a/components/esp_system/port/soc/esp32c3/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c3/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -134,6 +134,12 @@ bool esp_cache_err_has_active_err(void) return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK) || cache_ll_l1_get_illegal_error_intr_status(0, CACHE_LL_L1_ILG_EVENT_MASK); } +void esp_cache_err_clear_active_err(void) +{ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32c5/cache_err_int.c b/components/esp_system/port/soc/esp32c5/cache_err_int.c index 10f0cdd45a..96b8447a04 100644 --- a/components/esp_system/port/soc/esp32c5/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c5/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,6 +40,11 @@ bool esp_cache_err_has_active_err(void) return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); } +void esp_cache_err_clear_active_err(void) +{ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32c6/cache_err_int.c b/components/esp_system/port/soc/esp32c6/cache_err_int.c index 5cc77ed1ac..b254e34bfe 100644 --- a/components/esp_system/port/soc/esp32c6/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c6/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -39,6 +39,11 @@ bool esp_cache_err_has_active_err(void) return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); } +void esp_cache_err_clear_active_err(void) +{ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32c61/cache_err_int.c b/components/esp_system/port/soc/esp32c61/cache_err_int.c index 7dd5661632..b180395065 100644 --- a/components/esp_system/port/soc/esp32c61/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c61/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -39,6 +39,11 @@ bool esp_cache_err_has_active_err(void) return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); } +void esp_cache_err_clear_active_err(void) +{ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32h2/cache_err_int.c b/components/esp_system/port/soc/esp32h2/cache_err_int.c index e4b0b03d4f..e9758a320e 100644 --- a/components/esp_system/port/soc/esp32h2/cache_err_int.c +++ b/components/esp_system/port/soc/esp32h2/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -39,6 +39,11 @@ bool esp_cache_err_has_active_err(void) return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); } +void esp_cache_err_clear_active_err(void) +{ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32h21/cache_err_int.c b/components/esp_system/port/soc/esp32h21/cache_err_int.c index 4b9d86e859..75e0b5b512 100644 --- a/components/esp_system/port/soc/esp32h21/cache_err_int.c +++ b/components/esp_system/port/soc/esp32h21/cache_err_int.c @@ -39,6 +39,11 @@ bool esp_cache_err_has_active_err(void) return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); } +void esp_cache_err_clear_active_err(void) +{ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32h4/cache_err_int.c b/components/esp_system/port/soc/esp32h4/cache_err_int.c index 7a598319e9..827b9cff64 100644 --- a/components/esp_system/port/soc/esp32h4/cache_err_int.c +++ b/components/esp_system/port/soc/esp32h4/cache_err_int.c @@ -39,6 +39,11 @@ bool esp_cache_err_has_active_err(void) return cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK); } +void esp_cache_err_clear_active_err(void) +{ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0; diff --git a/components/esp_system/port/soc/esp32p4/cache_err_int.c b/components/esp_system/port/soc/esp32p4/cache_err_int.c index 8bd4960f5f..3abe9015fb 100644 --- a/components/esp_system/port/soc/esp32p4/cache_err_int.c +++ b/components/esp_system/port/soc/esp32p4/cache_err_int.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -41,6 +41,12 @@ bool esp_cache_err_has_active_err(void) return has_active_err; } +void esp_cache_err_clear_active_err(void) +{ + cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK); + cache_ll_l2_clear_access_error_intr(0, CACHE_LL_L2_ACCESS_EVENT_MASK); +} + void esp_cache_err_int_init(void) { const uint32_t core_id = 0;