From 37d25de5313b7e07e98ce43ee0275be4ca9f4fc9 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 27 Jun 2025 20:04:13 +0800 Subject: [PATCH] fix(esp_system): force enable uart0 sclk in esp_restart --- components/esp_system/port/soc/esp32c5/system_internal.c | 5 +++++ components/esp_system/port/soc/esp32c6/system_internal.c | 5 +++++ components/esp_system/port/soc/esp32c61/system_internal.c | 5 +++++ components/esp_system/port/soc/esp32h2/system_internal.c | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c index 76d7037d8c..4afbaf9c49 100644 --- a/components/esp_system/port/soc/esp32c5/system_internal.c +++ b/components/esp_system/port/soc/esp32c5/system_internal.c @@ -22,6 +22,7 @@ #include "soc/rtc_periph.h" #include "soc/uart_reg.h" #include "hal/wdt_hal.h" +#include "hal/uart_ll.h" #if SOC_MODEM_CLOCK_SUPPORTED #include "hal/modem_syscon_ll.h" #include "hal/modem_lpcon_ll.h" @@ -78,6 +79,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c index 9a7bd4189f..5d4bf93131 100644 --- a/components/esp_system/port/soc/esp32c6/system_internal.c +++ b/components/esp_system/port/soc/esp32c6/system_internal.c @@ -20,6 +20,7 @@ #include "esp_private/rtc_clk.h" #include "soc/rtc_periph.h" #include "soc/uart_reg.h" +#include "hal/uart_ll.h" #include "hal/wdt_hal.h" #include "hal/modem_syscon_ll.h" #include "hal/modem_lpcon_ll.h" @@ -75,6 +76,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c index dac6f93816..bfe80c1055 100644 --- a/components/esp_system/port/soc/esp32c61/system_internal.c +++ b/components/esp_system/port/soc/esp32c61/system_internal.c @@ -20,6 +20,7 @@ #include "esp_private/rtc_clk.h" #include "soc/rtc_periph.h" #include "soc/uart_reg.h" +#include "hal/uart_ll.h" #include "hal/wdt_hal.h" #include "esp_private/cache_err_int.h" @@ -78,6 +79,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c index 4942551182..e08beb85ea 100644 --- a/components/esp_system/port/soc/esp32h2/system_internal.c +++ b/components/esp_system/port/soc/esp32h2/system_internal.c @@ -23,6 +23,7 @@ #include "soc/uart_reg.h" #include "hal/wdt_hal.h" #include "hal/spimem_flash_ll.h" +#include "hal/uart_ll.h" #include "esp_private/cache_err_int.h" #include "esp_private/mspi_timing_tuning.h" @@ -73,6 +74,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN); CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN); CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN); + + // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling + // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM. + uart_ll_sclk_enable(&UART0); } /* "inner" restart function for after RTOS, interrupts & anything else on this