diff --git a/components/driver/test/test_gpio.c b/components/driver/test/test_gpio.c
index 57da8b7614..3098a4cb89 100644
--- a/components/driver/test/test_gpio.c
+++ b/components/driver/test/test_gpio.c
@@ -25,34 +25,48 @@
 #define WAKE_UP_IGNORE 1  // gpio_wakeup function development is not completed yet, set it deprecated.
 
 #if CONFIG_IDF_TARGET_ESP32
-#define TEST_GPIO_EXT_OUT_IO        18  // default output GPIO
-#define TEST_GPIO_EXT_IN_IO         19  // default input GPIO
-#define TEST_GPIO_OUTPUT_PIN        23
-#define TEST_GPIO_INPUT_ONLY_PIN    34
-#define TEST_GPIO_OUTPUT_MAX        GPIO_NUM_34
+#define TEST_GPIO_EXT_OUT_IO            18  // default output GPIO
+#define TEST_GPIO_EXT_IN_IO             19  // default input GPIO
+#define TEST_GPIO_OUTPUT_PIN            23
+#define TEST_GPIO_INPUT_ONLY_PIN        34
+#define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_34
+#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN  2
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN   4
 #elif CONFIG_IDF_TARGET_ESP32S2
 // ESP32_S2 DEVKIC uses IO19 and IO20 as USB functions, so it is necessary to avoid using IO19, otherwise GPIO io pull up/down function cannot pass
 // Also the first version of ESP32-S2-Saola has pullup issue on GPIO18, which is tied to 3V3 on the
 // runner. Also avoid using GPIO18.
-#define TEST_GPIO_EXT_OUT_IO        17  // default output GPIO
-#define TEST_GPIO_EXT_IN_IO         21  // default input GPIO
-#define TEST_GPIO_OUTPUT_PIN        12
-#define TEST_GPIO_INPUT_ONLY_PIN    46
-#define TEST_GPIO_OUTPUT_MAX        GPIO_NUM_46
+#define TEST_GPIO_EXT_OUT_IO            17  // default output GPIO
+#define TEST_GPIO_EXT_IN_IO             21  // default input GPIO
+#define TEST_GPIO_OUTPUT_PIN            12
+#define TEST_GPIO_INPUT_ONLY_PIN        46
+#define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_46
+#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN  17
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN   1
 #elif CONFIG_IDF_TARGET_ESP32S3
-//  IO19 and IO20 are connected as USB functions and should be avoided for testing
-#define TEST_GPIO_EXT_OUT_IO        17  // default output GPIO
-#define TEST_GPIO_EXT_IN_IO         21  // default input GPIO
-#define TEST_GPIO_OUTPUT_PIN        12
-#define TEST_GPIO_INPUT_ONLY_PIN    46
-#define TEST_GPIO_OUTPUT_MAX        GPIO_NUM_MAX
+//  IO19 and IO20 are connected as USB functions.
+#define TEST_GPIO_EXT_OUT_IO            17  // default output GPIO
+#define TEST_GPIO_EXT_IN_IO             21  // default input GPIO
+#define TEST_GPIO_OUTPUT_PIN            12
+#define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_MAX
+#define TEST_GPIO_USB_DM_IO             19  // USB D- GPIO
+#define TEST_GPIO_USB_DP_IO             20  // USB D+ GPIO
+#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN  17
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN   1
 #elif CONFIG_IDF_TARGET_ESP32C3
-#define TEST_GPIO_EXT_OUT_IO        2  // default output GPIO
-#define TEST_GPIO_EXT_IN_IO         3  // default input GPIO
-#define TEST_GPIO_OUTPUT_PIN        1
-#define TEST_GPIO_OUTPUT_MAX        GPIO_NUM_21
+#define TEST_GPIO_EXT_OUT_IO            2  // default output GPIO
+#define TEST_GPIO_EXT_IN_IO             3  // default input GPIO
+#define TEST_GPIO_OUTPUT_PIN            1
+#define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_21
+#define TEST_GPIO_USB_DM_IO             18  // USB D- GPIO
+#define TEST_GPIO_USB_DP_IO             19  // USB D+ GPIO
+#define TEST_GPIO_INPUT_LEVEL_HIGH_PIN  10
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN   1
 #endif
 
+// If there is any input-only pin, enable input-only pin part of some tests.
+#define SOC_HAS_INPUT_ONLY_PIN (CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2)
+
 // define public test io on all boards(esp32, esp32s2, esp32s3, esp32c3)
 #define TEST_IO_9 GPIO_NUM_9
 #define TEST_IO_10 GPIO_NUM_10
@@ -82,18 +96,18 @@ static gpio_config_t init_io(gpio_num_t num)
     return io_conf;
 }
 
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
-//No runners
 // edge interrupt event
-static void gpio_isr_edge_handler(void* arg)
+__attribute__((unused)) static void gpio_isr_edge_handler(void *arg)
 {
     uint32_t gpio_num = (uint32_t) arg;
     esp_rom_printf("GPIO[%d] intr, val: %d\n", gpio_num, gpio_get_level(gpio_num));
     edge_intr_times++;
 }
 
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
+//No runners
 // level interrupt event with "gpio_intr_disable"
-static void gpio_isr_level_handler(void* arg)
+static void gpio_isr_level_handler(void *arg)
 {
     uint32_t gpio_num = (uint32_t) arg;
     disable_intr_times++;
@@ -102,14 +116,14 @@ static void gpio_isr_level_handler(void* arg)
 }
 
 // level interrupt event
-static void gpio_isr_level_handler2(void* arg)
+static void gpio_isr_level_handler2(void *arg)
 {
     uint32_t gpio_num = (uint32_t) arg;
     level_intr_times++;
     esp_rom_printf("GPIO[%d] intr, val: %d\n", gpio_num, gpio_get_level(gpio_num));
-    if(gpio_get_level(gpio_num)) {
+    if (gpio_get_level(gpio_num)) {
         gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0);
-    }else{
+    } else {
         gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1);
     }
     esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", TEST_GPIO_EXT_OUT_IO, gpio_get_level(TEST_GPIO_EXT_OUT_IO), level_intr_times);
@@ -136,22 +150,22 @@ static void trigger_wake_up(void *arg)
     gpio_config(&io_config);
     gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0);
     gpio_install_isr_service(0);
-    gpio_isr_handler_add(TEST_GPIO_EXT_OUT_IO, gpio_isr_level_handler, (void*) TEST_GPIO_EXT_IN_IO);
+    gpio_isr_handler_add(TEST_GPIO_EXT_OUT_IO, gpio_isr_level_handler, (void *) TEST_GPIO_EXT_IN_IO);
     gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1);
     vTaskDelay(100 / portTICK_RATE_MS);
 }
 #endif //!WAKE_UP_IGNORE
 
-static void prompt_to_continue(const char* str)
+static void prompt_to_continue(const char *str)
 {
     printf("%s , please press \"Enter\" to go on!\n", str);
     char sign[5] = {0};
-    while(strlen(sign) == 0) {
+    while (strlen(sign) == 0) {
         /* Flush anything already in the RX buffer */
-        while(esp_rom_uart_rx_one_char((uint8_t *) sign) == ETS_OK) {
+        while (esp_rom_uart_rx_one_char((uint8_t *) sign) == ETS_OK) {
         }
         /* Read line */
-        esp_rom_uart_rx_string((uint8_t*) sign, sizeof(sign) - 1);
+        esp_rom_uart_rx_string((uint8_t *) sign, sizeof(sign) - 1);
     }
 }
 
@@ -172,32 +186,32 @@ static void drive_capability_set_get(gpio_num_t num, gpio_drive_cap_t capability
 TEST_CASE("GPIO config parameters test", "[gpio]")
 {
     //error param test
-    //ESP32 test 41 bit, ESP32-S2 test 48 bit, ESP32-S3 test 49 bit
+    //ESP32 test 41 bit, ESP32-S2 test 48 bit, ESP32-S3 test 50 bit
     gpio_config_t io_config = { 0 };
     io_config.intr_type = GPIO_INTR_DISABLE;
-    io_config.pin_bit_mask = ((uint64_t)1<<(GPIO_NUM_MAX+1));
+    io_config.pin_bit_mask = ((uint64_t)1 << (GPIO_NUM_MAX + 1));
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
 
     // test 0
     io_config.pin_bit_mask = 0;
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
 
-    //ESP32 test 40 bit, ESP32-S2 test 47 bit, ESP32-S3 test 48 bit
-    io_config.pin_bit_mask = ((uint64_t)1<<GPIO_NUM_MAX);
+    //ESP32 test 40 bit, ESP32-S2 test 47 bit, ESP32-S3 test 49 bit
+    io_config.pin_bit_mask = ((uint64_t)1 << GPIO_NUM_MAX);
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
 
-    io_config.pin_bit_mask = ((uint64_t)1<<TEST_GPIO_OUTPUT_PIN);
+    io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_OUTPUT_PIN);
     TEST_ESP_OK(gpio_config(&io_config));
 
-    //This IO is just used for input, C3 doesn't have input only pin.
-#if !CONFIG_IDF_TARGET_ESP32C3
+    //This IO is just used for input, C3 and S3 doesn't have input only pin.
+#if SOC_HAS_INPUT_ONLY_PIN
     io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN);
     io_config.mode = GPIO_MODE_INPUT;
     TEST_ESP_OK(gpio_config(&io_config));
     io_config.mode = GPIO_MODE_OUTPUT;
     // The pin is input only, once set as output should log something
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
-#endif //!CONFIG_IDF_TARGET_ESP32C3
+#endif // SOC_HAS_INPUT_ONLY_PIN
 }
 
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
@@ -218,7 +232,7 @@ TEST_CASE("GPIO rising edge interrupt test", "[gpio][test_env=UT_T1_GPIO]")
     //rising edge intr
     TEST_ESP_OK(gpio_set_intr_type(TEST_GPIO_EXT_IN_IO, GPIO_INTR_POSEDGE));
     TEST_ESP_OK(gpio_install_isr_service(0));
-    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_edge_handler, (void*)TEST_GPIO_EXT_IN_IO);
+    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_edge_handler, (void *)TEST_GPIO_EXT_IN_IO);
     TEST_ESP_OK(gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1));
     TEST_ASSERT_EQUAL_INT(edge_intr_times, 1);
     vTaskDelay(100 / portTICK_RATE_MS);
@@ -240,7 +254,7 @@ TEST_CASE("GPIO falling edge interrupt test", "[gpio][test_env=UT_T1_GPIO]")
 
     gpio_set_intr_type(TEST_GPIO_EXT_IN_IO, GPIO_INTR_NEGEDGE);
     gpio_install_isr_service(0);
-    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_edge_handler, (void*) TEST_GPIO_EXT_IN_IO);
+    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_edge_handler, (void *) TEST_GPIO_EXT_IN_IO);
     gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0);
     vTaskDelay(100 / portTICK_RATE_MS);
     TEST_ASSERT_EQUAL_INT(edge_intr_times, 1);
@@ -264,22 +278,22 @@ TEST_CASE("GPIO both rising and falling edge interrupt test", "[gpio][test_env=U
 
     gpio_set_intr_type(TEST_GPIO_EXT_IN_IO, GPIO_INTR_ANYEDGE);
     gpio_install_isr_service(0);
-    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_edge_handler, (void*) TEST_GPIO_EXT_IN_IO);
+    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_edge_handler, (void *) TEST_GPIO_EXT_IN_IO);
     // for rising edge in GPIO_INTR_ANYEDGE
-    while(1) {
+    while (1) {
         level = level + 1;
-        gpio_set_level(TEST_GPIO_EXT_OUT_IO, level*0.2);
-        if(level > 10) {
+        gpio_set_level(TEST_GPIO_EXT_OUT_IO, level * 0.2);
+        if (level > 10) {
             break;
         }
         vTaskDelay(100 / portTICK_RATE_MS);
     }
     vTaskDelay(100 / portTICK_RATE_MS);
     // for falling rdge in GPIO_INTR_ANYEDGE
-    while(1) {
+    while (1) {
         level = level - 1;
-        gpio_set_level(TEST_GPIO_EXT_OUT_IO, level/5);
-        if(level < 0) {
+        gpio_set_level(TEST_GPIO_EXT_OUT_IO, level / 5);
+        if (level < 0) {
             break;
         }
         vTaskDelay(100 / portTICK_RATE_MS);
@@ -293,7 +307,7 @@ TEST_CASE("GPIO both rising and falling edge interrupt test", "[gpio][test_env=U
 
 TEST_CASE("GPIO input high level trigger, cut the interrupt source exit interrupt test", "[gpio][test_env=UT_T1_GPIO]")
 {
-    level_intr_times=0;
+    level_intr_times = 0;
     gpio_config_t output_io = init_io(TEST_GPIO_EXT_OUT_IO);
     gpio_config_t input_io = init_io(TEST_GPIO_EXT_IN_IO);
     input_io.intr_type = GPIO_INTR_POSEDGE;
@@ -305,7 +319,7 @@ TEST_CASE("GPIO input high level trigger, cut the interrupt source exit interrup
 
     gpio_set_intr_type(TEST_GPIO_EXT_IN_IO, GPIO_INTR_HIGH_LEVEL);
     gpio_install_isr_service(0);
-    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler2, (void*) TEST_GPIO_EXT_IN_IO);
+    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler2, (void *) TEST_GPIO_EXT_IN_IO);
     gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1);
     vTaskDelay(100 / portTICK_RATE_MS);
     TEST_ASSERT_EQUAL_INT_MESSAGE(level_intr_times, 1, "go into high-level interrupt more than once with cur interrupt source way");
@@ -316,7 +330,7 @@ TEST_CASE("GPIO input high level trigger, cut the interrupt source exit interrup
 
 TEST_CASE("GPIO low level interrupt test", "[gpio][test_env=UT_T1_GPIO]")
 {
-    disable_intr_times=0;
+    disable_intr_times = 0;
     gpio_config_t output_io = init_io(TEST_GPIO_EXT_OUT_IO);
     gpio_config_t input_io = init_io(TEST_GPIO_EXT_IN_IO);
     input_io.intr_type = GPIO_INTR_POSEDGE;
@@ -328,9 +342,9 @@ TEST_CASE("GPIO low level interrupt test", "[gpio][test_env=UT_T1_GPIO]")
 
     gpio_set_intr_type(TEST_GPIO_EXT_IN_IO, GPIO_INTR_LOW_LEVEL);
     gpio_install_isr_service(0);
-    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler, (void*) TEST_GPIO_EXT_IN_IO);
+    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler, (void *) TEST_GPIO_EXT_IN_IO);
     gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0);
-    printf("get level:%d\n",gpio_get_level(TEST_GPIO_EXT_IN_IO));
+    printf("get level:%d\n", gpio_get_level(TEST_GPIO_EXT_IN_IO));
     vTaskDelay(100 / portTICK_RATE_MS);
     TEST_ASSERT_EQUAL_INT_MESSAGE(disable_intr_times, 1, "go into low-level interrupt more than once with disable way");
     gpio_isr_handler_remove(TEST_GPIO_EXT_IN_IO);
@@ -339,7 +353,7 @@ TEST_CASE("GPIO low level interrupt test", "[gpio][test_env=UT_T1_GPIO]")
 
 TEST_CASE("GPIO multi-level interrupt test, to cut the interrupt source exit interrupt ", "[gpio][test_env=UT_T1_GPIO]")
 {
-    level_intr_times=0;
+    level_intr_times = 0;
     gpio_config_t output_io = init_io(TEST_GPIO_EXT_OUT_IO);
     gpio_config_t input_io = init_io(TEST_GPIO_EXT_IN_IO);
     input_io.intr_type = GPIO_INTR_POSEDGE;
@@ -351,7 +365,7 @@ TEST_CASE("GPIO multi-level interrupt test, to cut the interrupt source exit int
 
     gpio_set_intr_type(TEST_GPIO_EXT_IN_IO, GPIO_INTR_HIGH_LEVEL);
     gpio_install_isr_service(0);
-    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler2, (void*) TEST_GPIO_EXT_IN_IO);
+    gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler2, (void *) TEST_GPIO_EXT_IN_IO);
     gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1);
     vTaskDelay(100 / portTICK_RATE_MS);
     TEST_ASSERT_EQUAL_INT_MESSAGE(level_intr_times, 1, "go into high-level interrupt more than once with cur interrupt source way");
@@ -376,7 +390,7 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
     TEST_ESP_OK(gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0)); // Because of GPIO_INTR_HIGH_LEVEL interrupt, 0 must be set first
     TEST_ESP_OK(gpio_set_intr_type(TEST_GPIO_EXT_IN_IO, GPIO_INTR_HIGH_LEVEL));
     TEST_ESP_OK(gpio_install_isr_service(0));
-    TEST_ESP_OK(gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler, (void*) TEST_GPIO_EXT_IN_IO));
+    TEST_ESP_OK(gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler, (void *) TEST_GPIO_EXT_IN_IO));
     TEST_ESP_OK(gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1));
     TEST_ESP_OK(gpio_isr_handler_remove(TEST_GPIO_EXT_IN_IO));
     TEST_ESP_OK(gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0));
@@ -389,25 +403,25 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
     TEST_ASSERT_EQUAL_INT_MESSAGE(disable_intr_times, 1, "disable interrupt does not work, still go into interrupt!");
 
     gpio_uninstall_isr_service();  //uninstall the service
-    TEST_ASSERT(gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler, (void*) TEST_GPIO_EXT_IN_IO) == ESP_ERR_INVALID_STATE);
+    TEST_ASSERT(gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_level_handler, (void *) TEST_GPIO_EXT_IN_IO) == ESP_ERR_INVALID_STATE);
     TEST_ASSERT(gpio_isr_handler_remove(TEST_GPIO_EXT_IN_IO) == ESP_ERR_INVALID_STATE);
 }
 #endif //DISABLED_FOR_TARGETS(ESP32S2, ESP32S3, ESP32C3)
 
 // ESP32 Connect GPIO18 with GPIO19, ESP32-S2 Connect GPIO17 with GPIO21,
-// ESP32-S3 Connect GPIO19 with GPIO20, ESP32C3 Connect GPIO2 with GPIO3
+// ESP32-S3 Connect GPIO17 with GPIO21, ESP32C3 Connect GPIO2 with GPIO3
 // use multimeter to test the voltage, so it is ignored in CI
-TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]")
+TEST_CASE("GPIO set gpio output level test", "[gpio][ignore][UT_T1_GPIO]")
 {
     gpio_config_t io_conf;
     io_conf.intr_type = GPIO_INTR_DISABLE;
     io_conf.mode = GPIO_MODE_OUTPUT;
-    io_conf.pin_bit_mask = ((uint64_t)1<<TEST_GPIO_EXT_OUT_IO);
+    io_conf.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_EXT_OUT_IO);
     io_conf.pull_down_en = 0;
     io_conf.pull_up_en = 0;
     gpio_config(&io_conf);
 
-    io_conf.pin_bit_mask = ((uint64_t)1<<TEST_GPIO_EXT_IN_IO);
+    io_conf.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_EXT_IN_IO);
     io_conf.mode = GPIO_MODE_INPUT;
     gpio_config(&io_conf);
 
@@ -419,30 +433,30 @@ TEST_CASE("GPIO set gpio output level test", "[gpio][ignore]")
     // tested voltage is around 3.3v
     TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(TEST_GPIO_EXT_IN_IO), 1, "get level error! the level should be high!");
 
-    //This IO is just used for input, C3 doesn't have input only pin.
-#if !CONFIG_IDF_TARGET_ESP32C3
-    io_conf.pin_bit_mask = ((uint64_t)1<<TEST_GPIO_INPUT_ONLY_PIN);
+    //This IO is just used for input, C3 and S3 doesn't have input only pin.
+#if SOC_HAS_INPUT_ONLY_PIN
+    io_conf.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN);
     io_conf.mode = GPIO_MODE_OUTPUT;
     gpio_config(&io_conf);
     TEST_ASSERT(gpio_config(&io_conf) == ESP_ERR_INVALID_ARG);
-#endif //!CONFIG_IDF_TARGET_ESP32C3
+#endif // SOC_HAS_INPUT_ONLY_PIN
 }
 
-// gpio17 connects to 3.3v pin, gpio19 connects to the GND pin
+// TEST_GPIO_INPUT_LEVEL_HIGH_PIN connects to 3.3v pin, TEST_GPIO_INPUT_LEVEL_LOW_PIN connects to the GND pin
 // use multimeter to test the voltage, so it is ignored in CI
 TEST_CASE("GPIO get input level test", "[gpio][ignore]")
 {
-    gpio_num_t num = 17;
-    int level = gpio_get_level(num);
-    printf("gpio17's level is: %d\n", level);
-    TEST_ASSERT_EQUAL_INT_MESSAGE(level, 1, "get level error! the level should be high!");
+    gpio_num_t num1 = TEST_GPIO_INPUT_LEVEL_HIGH_PIN;
+    int level1 = gpio_get_level(num1);
+    printf("TEST_GPIO_INPUT_LEVEL_HIGH_PIN's level is: %d\n", level1);
+    TEST_ASSERT_EQUAL_INT_MESSAGE(level1, 1, "get level error! the level should be high!");
 
-    gpio_num_t num2 = 19;
+    gpio_num_t num2 = TEST_GPIO_INPUT_LEVEL_LOW_PIN;
     int level2 = gpio_get_level(num2);
-    printf("gpio19's level is: %d\n", level2);
+    printf("TEST_GPIO_INPUT_LEVEL_LOW_PIN's level is: %d\n", level2);
     TEST_ASSERT_EQUAL_INT_MESSAGE(level2, 0, "get level error! the level should be low!");
     printf("the memory get: %d\n", esp_get_free_heap_size());
-    //when case finish, get the result from multimeter, the pin17 is 3.3v, the pin19 is 0.00v
+    //when case finish, get the result from multimeter, the TEST_GPIO_INPUT_LEVEL_HIGH_PIN is 3.3v, the TEST_GPIO_INPUT_LEVEL_LOW_PIN is 0.00v
 }
 
 TEST_CASE("GPIO io pull up/down function", "[gpio]")
@@ -472,7 +486,7 @@ TEST_CASE("GPIO io pull up/down function", "[gpio]")
 //No runners
 TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]")
 {
-    //ESP32 connect io18 and io19, ESP32-S2 connect io17 and io21, ESP32-S3 connect io19 and io20, ESP32C3 Connect GPIO2 with GPIO3
+    //ESP32 connect io18 and io19, ESP32-S2 connect io17 and io21, ESP32-S3 connect io17 and io21, ESP32C3 Connect GPIO2 with GPIO3
     gpio_config_t output_io = init_io(TEST_GPIO_EXT_OUT_IO);
     gpio_config_t input_io = init_io(TEST_GPIO_EXT_IN_IO);
     gpio_config(&output_io);
@@ -519,7 +533,7 @@ TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]")
     TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(TEST_GPIO_EXT_IN_IO), !level, "direction set error, it can't output");
 }
 
-TEST_CASE("GPIO repeate call service and isr has no memory leak test","[gpio][test_env=UT_T1_GPIO][timeout=90]")
+TEST_CASE("GPIO repeate call service and isr has no memory leak test", "[gpio][test_env=UT_T1_GPIO][timeout=90]")
 {
     gpio_config_t output_io = init_io(TEST_GPIO_EXT_OUT_IO);
     gpio_config_t input_io = init_io(TEST_GPIO_EXT_IN_IO);
@@ -531,10 +545,10 @@ TEST_CASE("GPIO repeate call service and isr has no memory leak test","[gpio][te
     TEST_ESP_OK(gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0));
     //rising edge
     uint32_t size = esp_get_free_heap_size();
-    for(int i=0;i<1000;i++) {
+    for (int i = 0; i < 1000; i++) {
         TEST_ESP_OK(gpio_set_intr_type(TEST_GPIO_EXT_IN_IO, GPIO_INTR_POSEDGE));
         TEST_ESP_OK(gpio_install_isr_service(0));
-        TEST_ESP_OK(gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_edge_handler, (void*)TEST_GPIO_EXT_IN_IO));
+        TEST_ESP_OK(gpio_isr_handler_add(TEST_GPIO_EXT_IN_IO, gpio_isr_edge_handler, (void *)TEST_GPIO_EXT_IN_IO));
         gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1);
         TEST_ESP_OK(gpio_isr_handler_remove(TEST_GPIO_EXT_IN_IO));
         gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0);
@@ -668,7 +682,6 @@ TEST_CASE("GPIO drive capability test", "[gpio][ignore]")
 }
 
 #if !CONFIG_FREERTOS_UNICORE
-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
 void gpio_enable_task(void *param)
 {
     int gpio_num = (int)param;
@@ -698,7 +711,7 @@ TEST_CASE("GPIO Enable/Disable interrupt on multiple cores", "[gpio][ignore]")
     TEST_ESP_OK(gpio_config(&io_conf));
     TEST_ESP_OK(gpio_set_level(TEST_IO_9, 0));
     TEST_ESP_OK(gpio_install_isr_service(0));
-    TEST_ESP_OK(gpio_isr_handler_add(TEST_IO_9, gpio_isr_edge_handler, (void*) TEST_IO_9));
+    TEST_ESP_OK(gpio_isr_handler_add(TEST_IO_9, gpio_isr_edge_handler, (void *) TEST_IO_9));
     vTaskDelay(1000 / portTICK_RATE_MS);
     TEST_ESP_OK(gpio_set_level(TEST_IO_9, 1));
     vTaskDelay(100 / portTICK_RATE_MS);
@@ -706,7 +719,7 @@ TEST_CASE("GPIO Enable/Disable interrupt on multiple cores", "[gpio][ignore]")
     vTaskDelay(100 / portTICK_RATE_MS);
     TEST_ESP_OK(gpio_intr_disable(TEST_IO_9));
     TEST_ASSERT(edge_intr_times == 1);
-    xTaskCreatePinnedToCore(gpio_enable_task, "gpio_enable_task", 1024*4, (void*)TEST_IO_9, 8, NULL, (xPortGetCoreID() == 0));
+    xTaskCreatePinnedToCore(gpio_enable_task, "gpio_enable_task", 1024 * 4, (void *)TEST_IO_9, 8, NULL, (xPortGetCoreID() == 0));
     vTaskDelay(1000 / portTICK_RATE_MS);
     TEST_ESP_OK(gpio_set_level(TEST_IO_9, 1));
     vTaskDelay(100 / portTICK_RATE_MS);
@@ -717,7 +730,6 @@ TEST_CASE("GPIO Enable/Disable interrupt on multiple cores", "[gpio][ignore]")
     gpio_uninstall_isr_service();
     TEST_ASSERT(edge_intr_times == 2);
 }
-#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
 #endif //!CONFIG_FREERTOS_UNICORE
 
 typedef struct {
@@ -725,7 +737,7 @@ typedef struct {
     int isr_cnt;
 } gpio_isr_param_t;
 
-static void gpio_isr_handler(void* arg)
+static void gpio_isr_handler(void *arg)
 {
     gpio_isr_param_t *param = (gpio_isr_param_t *)arg;
     esp_rom_printf("GPIO[%d] intr, val: %d\n", param->gpio_num, gpio_get_level(param->gpio_num));
@@ -764,8 +776,8 @@ TEST_CASE("GPIO ISR service test", "[gpio][ignore]")
     TEST_ESP_OK(gpio_install_isr_service(0));
     TEST_ESP_OK(gpio_set_intr_type(TEST_IO_9, GPIO_INTR_ANYEDGE));
     TEST_ESP_OK(gpio_set_intr_type(TEST_IO_10, GPIO_INTR_NEGEDGE));
-    TEST_ESP_OK(gpio_isr_handler_add(TEST_IO_9, gpio_isr_handler, (void*)&io9_param));
-    TEST_ESP_OK(gpio_isr_handler_add(TEST_IO_10, gpio_isr_handler, (void*)&io10_param));
+    TEST_ESP_OK(gpio_isr_handler_add(TEST_IO_9, gpio_isr_handler, (void *)&io9_param));
+    TEST_ESP_OK(gpio_isr_handler_add(TEST_IO_10, gpio_isr_handler, (void *)&io10_param));
     printf("Triggering the interrupt of GPIO9\n");
     vTaskDelay(1000 / portTICK_RATE_MS);
     //Rising edge
@@ -790,3 +802,38 @@ TEST_CASE("GPIO ISR service test", "[gpio][ignore]")
     gpio_uninstall_isr_service();
     TEST_ASSERT((io9_param.isr_cnt == 1) && (io10_param.isr_cnt == 1));
 }
+
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
+TEST_CASE("GPIO input and output of USB pins test", "[gpio]")
+{
+    const int test_pins[] = {TEST_GPIO_USB_DP_IO, TEST_GPIO_USB_DM_IO};
+    gpio_config_t io_conf = {
+        .intr_type = GPIO_INTR_DISABLE,
+        .mode = GPIO_MODE_INPUT_OUTPUT,
+        .pin_bit_mask = (BIT64(test_pins[0]) | BIT64(test_pins[1])),
+        .pull_down_en = 0,
+        .pull_up_en = 0,
+    };
+    gpio_config(&io_conf);
+
+    for (int i = 0; i < sizeof(test_pins) / sizeof(int); i++) {
+        int pin = test_pins[i];
+        // test pin
+        gpio_set_level(pin, 0);
+        // tested voltage is around 0v
+        TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 0, "get level error! the level should be low!");
+        vTaskDelay(1000 / portTICK_RATE_MS);
+        gpio_set_level(pin, 1);
+        // tested voltage is around 3.3v
+        TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 1, "get level error! the level should be high!");
+        vTaskDelay(1000 / portTICK_RATE_MS);
+        gpio_set_level(pin, 0);
+        // tested voltage is around 0v
+        TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 0, "get level error! the level should be low!");
+        vTaskDelay(1000 / portTICK_RATE_MS);
+        gpio_set_level(pin, 1);
+        // tested voltage is around 3.3v
+        TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(pin), 1, "get level error! the level should be high!");
+    }
+}
+#endif //CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
diff --git a/components/driver/test/test_sigmadelta.c b/components/driver/test/test_sigmadelta.c
index 26b9ee04f5..a5f4a7c9b5 100644
--- a/components/driver/test/test_sigmadelta.c
+++ b/components/driver/test/test_sigmadelta.c
@@ -41,7 +41,7 @@ TEST_CASE("SigmaDelta pin, duty, prescale set", "[sigma_delta][ignore]")
     int8_t duty = 0;
     int inc = 1;
     for (int i = 0; i < 1000; i++) {
-        sigmadelta_set_duty(0, duty);
+        sigmadelta_set_duty(sigmadelta_cfg.channel, duty);
         vTaskDelay(10 / portTICK_PERIOD_MS);
 
         duty += inc;
@@ -52,7 +52,7 @@ TEST_CASE("SigmaDelta pin, duty, prescale set", "[sigma_delta][ignore]")
 
     TEST_ESP_OK(sigmadelta_set_prescale(0, 200));
     for (int i = 0; i < 1000; i++) {
-        sigmadelta_set_duty(0, duty);
+        sigmadelta_set_duty(sigmadelta_cfg.channel, duty);
         vTaskDelay(10 / portTICK_PERIOD_MS);
 
         duty += inc;
@@ -61,6 +61,6 @@ TEST_CASE("SigmaDelta pin, duty, prescale set", "[sigma_delta][ignore]")
         }
     }
 
-    TEST_ESP_OK(sigmadelta_set_pin(0, 5));
+    TEST_ESP_OK(sigmadelta_set_pin(sigmadelta_cfg.channel, 5));
     vTaskDelay(3000 / portTICK_PERIOD_MS);
 }
diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c
index 2a1bc3144f..1a180cff0f 100644
--- a/components/driver/test/test_spi_master.c
+++ b/components/driver/test/test_spi_master.c
@@ -32,55 +32,58 @@
 
 const static char TAG[] = "test_spi";
 
+// There is no input-only pin on esp32c3 and esp32s3
+#define TEST_SOC_HAS_INPUT_ONLY_PINS  (!DISABLED_FOR_TARGETS(ESP32C3, ESP32S3))
+
 static void check_spi_pre_n_for(int clk, int pre, int n)
 {
     esp_err_t ret;
     spi_device_handle_t handle;
 
-    spi_device_interface_config_t devcfg={
-        .command_bits=0,
-        .address_bits=0,
-        .dummy_bits=0,
-        .clock_speed_hz=clk,
-        .duty_cycle_pos=128,
-        .mode=0,
-        .spics_io_num=PIN_NUM_CS,
-        .queue_size=3
+    spi_device_interface_config_t devcfg = {
+        .command_bits = 0,
+        .address_bits = 0,
+        .dummy_bits = 0,
+        .clock_speed_hz = clk,
+        .duty_cycle_pos = 128,
+        .mode = 0,
+        .spics_io_num = PIN_NUM_CS,
+        .queue_size = 3
     };
-    char sendbuf[16]="";
+    char sendbuf[16] = "";
     spi_transaction_t t;
     memset(&t, 0, sizeof(t));
 
-    ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle);
-    TEST_ASSERT(ret==ESP_OK);
+    ret = spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle);
+    TEST_ASSERT(ret == ESP_OK);
 
-    t.length=16*8;
-    t.tx_buffer=sendbuf;
-    ret=spi_device_transmit(handle, &t);
+    t.length = 16 * 8;
+    t.tx_buffer = sendbuf;
+    ret = spi_device_transmit(handle, &t);
 
-    spi_dev_t* hw = spi_periph_signal[TEST_SPI_HOST].hw;
+    spi_dev_t *hw = spi_periph_signal[TEST_SPI_HOST].hw;
 
-    printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, hw->clock.clkdiv_pre+1, hw->clock.clkcnt_n+1);
+    printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, hw->clock.clkdiv_pre + 1, hw->clock.clkcnt_n + 1);
 
-    TEST_ASSERT(hw->clock.clkcnt_n+1==n);
-    TEST_ASSERT(hw->clock.clkdiv_pre+1==pre);
+    TEST_ASSERT(hw->clock.clkcnt_n + 1 == n);
+    TEST_ASSERT(hw->clock.clkdiv_pre + 1 == pre);
 
-    ret=spi_bus_remove_device(handle);
-    TEST_ASSERT(ret==ESP_OK);
+    ret = spi_bus_remove_device(handle);
+    TEST_ASSERT(ret == ESP_OK);
 }
 
 TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
 {
-    spi_bus_config_t buscfg={
-        .mosi_io_num=PIN_NUM_MOSI,
-        .miso_io_num=PIN_NUM_MISO,
-        .sclk_io_num=PIN_NUM_CLK,
-        .quadwp_io_num=-1,
-        .quadhd_io_num=-1
+    spi_bus_config_t buscfg = {
+        .mosi_io_num = PIN_NUM_MOSI,
+        .miso_io_num = PIN_NUM_MISO,
+        .sclk_io_num = PIN_NUM_CLK,
+        .quadwp_io_num = -1,
+        .quadhd_io_num = -1
     };
     esp_err_t ret;
     ret = spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO);
-    TEST_ASSERT(ret==ESP_OK);
+    TEST_ASSERT(ret == ESP_OK);
 
     check_spi_pre_n_for(26000000, 1, 3);
     check_spi_pre_n_for(20000000, 1, 4);
@@ -92,28 +95,29 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
     check_spi_pre_n_for(1, SOC_SPI_MAX_PRE_DIVIDER, 64); //Actually should generate the minimum clock speed, 152Hz
     check_spi_pre_n_for(26000000, 1, 3);
 
-    ret=spi_bus_free(TEST_SPI_HOST);
-    TEST_ASSERT(ret==ESP_OK);
+    ret = spi_bus_free(TEST_SPI_HOST);
+    TEST_ASSERT(ret == ESP_OK);
 }
 
-static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) {
-    spi_bus_config_t buscfg={
-        .mosi_io_num=PIN_NUM_MOSI,
-        .miso_io_num=PIN_NUM_MOSI,
-        .sclk_io_num=PIN_NUM_CLK,
-        .quadwp_io_num=-1,
-        .quadhd_io_num=-1,
-        .max_transfer_sz=4096*3
+static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma)
+{
+    spi_bus_config_t buscfg = {
+        .mosi_io_num = PIN_NUM_MOSI,
+        .miso_io_num = PIN_NUM_MOSI,
+        .sclk_io_num = PIN_NUM_CLK,
+        .quadwp_io_num = -1,
+        .quadhd_io_num = -1,
+        .max_transfer_sz = 4096 * 3
     };
-    spi_device_interface_config_t devcfg={
-        .command_bits=0,
-        .address_bits=0,
-        .dummy_bits=0,
-        .clock_speed_hz=clkspeed,
-        .duty_cycle_pos=128,
-        .mode=0,
-        .spics_io_num=PIN_NUM_CS,
-        .queue_size=3,
+    spi_device_interface_config_t devcfg = {
+        .command_bits = 0,
+        .address_bits = 0,
+        .dummy_bits = 0,
+        .clock_speed_hz = clkspeed,
+        .duty_cycle_pos = 128,
+        .mode = 0,
+        .spics_io_num = PIN_NUM_CS,
+        .queue_size = 3,
     };
     spi_device_handle_t handle;
 
@@ -125,54 +129,65 @@ static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) {
     return handle;
 }
 
-static int spi_test(spi_device_handle_t handle, int num_bytes) {
+static int spi_test(spi_device_handle_t handle, int num_bytes)
+{
     esp_err_t ret;
     int x;
     bool success = true;
     srand(num_bytes);
-    char *sendbuf=heap_caps_malloc((num_bytes+3)&(~3), MALLOC_CAP_DMA);
-    char *recvbuf=heap_caps_malloc((num_bytes+3)&(~3), MALLOC_CAP_DMA);
-    for (x=0; x<num_bytes; x++) {
-        sendbuf[x]=rand()&0xff;
-        recvbuf[x]=0x55;
+    char *sendbuf = heap_caps_malloc((num_bytes + 3) & (~3), MALLOC_CAP_DMA);
+    char *recvbuf = heap_caps_malloc((num_bytes + 3) & (~3), MALLOC_CAP_DMA);
+    for (x = 0; x < num_bytes; x++) {
+        sendbuf[x] = rand() & 0xff;
+        recvbuf[x] = 0x55;
     }
 
     spi_transaction_t t;
     memset(&t, 0, sizeof(t));
-    t.length=num_bytes*8;
-    t.tx_buffer=sendbuf;
-    t.rx_buffer=recvbuf;
-    t.addr=0xA00000000000000FL;
-    t.cmd=0x55;
+    t.length = num_bytes * 8;
+    t.tx_buffer = sendbuf;
+    t.rx_buffer = recvbuf;
+    t.addr = 0xA00000000000000FL;
+    t.cmd = 0x55;
 
     printf("Transmitting %d bytes...\n", num_bytes);
-    ret=spi_device_transmit(handle, &t);
-    TEST_ASSERT(ret==ESP_OK);
+    ret = spi_device_transmit(handle, &t);
+    TEST_ASSERT(ret == ESP_OK);
 
     srand(num_bytes);
-    for (x=0; x<num_bytes; x++) {
-        if (sendbuf[x]!=(rand()&0xff)) {
+    for (x = 0; x < num_bytes; x++) {
+        if (sendbuf[x] != (rand() & 0xff)) {
             printf("Huh? Sendbuf corrupted at byte %d\n", x);
             TEST_ASSERT(0);
         }
-        if (sendbuf[x]!=recvbuf[x]) break;
+        if (sendbuf[x] != recvbuf[x]) {
+            break;
+        }
     }
-    if (x!=num_bytes) {
-        int from=x-16;
-        if (from<0) from=0;
+    if (x != num_bytes) {
+        int from = x - 16;
+        if (from < 0) {
+            from = 0;
+        }
         success = false;
-        printf("Error at %d! Sent vs recved: (starting from %d)\n" , x, from);
-        for (int i=0; i<32; i++) {
-            if (i+from<num_bytes) printf("%02X ", sendbuf[from+i]);
+        printf("Error at %d! Sent vs recved: (starting from %d)\n", x, from);
+        for (int i = 0; i < 32; i++) {
+            if (i + from < num_bytes) {
+                printf("%02X ", sendbuf[from + i]);
+            }
         }
         printf("\n");
-        for (int i=0; i<32; i++) {
-            if (i+from<num_bytes) printf("%02X ", recvbuf[from+i]);
+        for (int i = 0; i < 32; i++) {
+            if (i + from < num_bytes) {
+                printf("%02X ", recvbuf[from + i]);
+            }
         }
         printf("\n");
     }
 
-    if (success) printf("Success!\n");
+    if (success) {
+        printf("Success!\n");
+    }
     free(sendbuf);
     free(recvbuf);
     return success;
@@ -182,20 +197,20 @@ TEST_CASE("SPI Master test", "[spi]")
 {
     bool success = true;
     printf("Testing bus at 80KHz\n");
-    spi_device_handle_t handle=setup_spi_bus_loopback(80000, true);
+    spi_device_handle_t handle = setup_spi_bus_loopback(80000, true);
     success &= spi_test(handle, 16); //small
     success &= spi_test(handle, 21); //small, unaligned
     success &= spi_test(handle, 36); //aligned
     success &= spi_test(handle, 128); //aligned
     success &= spi_test(handle, 129); //unaligned
-    success &= spi_test(handle, 4096-2); //multiple descs, edge case 1
-    success &= spi_test(handle, 4096-1); //multiple descs, edge case 2
-    success &= spi_test(handle, 4096*3); //multiple descs
+    success &= spi_test(handle, 4096 - 2); //multiple descs, edge case 1
+    success &= spi_test(handle, 4096 - 1); //multiple descs, edge case 2
+    success &= spi_test(handle, 4096 * 3); //multiple descs
 
     master_free_device_bus(handle);
 
     printf("Testing bus at 80KHz, non-DMA\n");
-    handle=setup_spi_bus_loopback(80000, false);
+    handle = setup_spi_bus_loopback(80000, false);
     success &= spi_test(handle, 4); //aligned
     success &= spi_test(handle, 16); //small
     success &= spi_test(handle, 21); //small, unaligned
@@ -207,36 +222,37 @@ TEST_CASE("SPI Master test", "[spi]")
     master_free_device_bus(handle);
 
     printf("Testing bus at 26MHz\n");
-    handle=setup_spi_bus_loopback(20000000, true);
+    handle = setup_spi_bus_loopback(20000000, true);
 
     success &= spi_test(handle, 128); //DMA, aligned
-    success &= spi_test(handle, 4096*3); //DMA, multiple descs
+    success &= spi_test(handle, 4096 * 3); //DMA, multiple descs
     master_free_device_bus(handle);
 
     printf("Testing bus at 900KHz\n");
-    handle=setup_spi_bus_loopback(9000000, true);
+    handle = setup_spi_bus_loopback(9000000, true);
 
     success &= spi_test(handle, 128); //DMA, aligned
-    success &= spi_test(handle, 4096*3); //DMA, multiple descs
+    success &= spi_test(handle, 4096 * 3); //DMA, multiple descs
     master_free_device_bus(handle);
     TEST_ASSERT(success);
 }
 
 
-TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") {
+TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]")
+{
     esp_err_t ret;
     bool success = true;
-    spi_device_interface_config_t devcfg={
-        .command_bits=0,
-        .address_bits=0,
-        .dummy_bits=0,
-        .clock_speed_hz=1000000,
-        .duty_cycle_pos=128,
-        .mode=0,
-        .spics_io_num=PIN_NUM_CS,
-        .queue_size=3,
+    spi_device_interface_config_t devcfg = {
+        .command_bits = 0,
+        .address_bits = 0,
+        .dummy_bits = 0,
+        .clock_speed_hz = 1000000,
+        .duty_cycle_pos = 128,
+        .mode = 0,
+        .spics_io_num = PIN_NUM_CS,
+        .queue_size = 3,
     };
-    spi_device_handle_t handle1=setup_spi_bus_loopback(80000, true);
+    spi_device_handle_t handle1 = setup_spi_bus_loopback(80000, true);
     spi_device_handle_t handle2;
     spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle2);
 
@@ -260,13 +276,13 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") {
     success &= spi_test(handle2, 5000);
 
 
-    ret=spi_bus_remove_device(handle2);
-    TEST_ASSERT(ret==ESP_OK);
+    ret = spi_bus_remove_device(handle2);
+    TEST_ASSERT(ret == ESP_OK);
     master_free_device_bus(handle1);
     TEST_ASSERT(success);
 }
 
-#if !DISABLED_FOR_TARGETS(ESP32C3)  //There is no input-only pin on esp32c3, so this test could be ignored.
+#if TEST_SOC_HAS_INPUT_ONLY_PINS  //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
 static esp_err_t test_master_pins(int mosi, int miso, int sclk, int cs)
 {
     esp_err_t ret;
@@ -328,8 +344,8 @@ TEST_CASE("spi placed on input-only pins", "[spi]")
     TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, INPUT_ONLY_PIN));
 }
 
-//There is no input-only pin on esp32c3, so this test could be ignored.
-#endif  //#if !DISABLED_FOR_TARGETS(ESP32C3)
+//There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
+#endif  //#if TEST_SOC_HAS_INPUT_ONLY_PINS
 
 TEST_CASE("spi bus setting with different pin configs", "[spi]")
 {
@@ -339,144 +355,184 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
 
     ESP_LOGI(TAG, "test 6 iomux output pins...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_QUAD;
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
     ESP_LOGI(TAG, "test 4 iomux output pins...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL;
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
     ESP_LOGI(TAG, "test 6 output pins...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD | SPICOMMON_BUSFLAG_GPIO_PINS;
     //swap MOSI and MISO
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
     ESP_LOGI(TAG, "test 4 output pins...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO |  SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS;
     //swap MOSI and MISO
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
-#if !DISABLED_FOR_TARGETS(ESP32C3)  //There is no input-only pin on esp32c3, so this test could be ignored.
+#if TEST_SOC_HAS_INPUT_ONLY_PINS  //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
     ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS;
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
     ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD | SPICOMMON_BUSFLAG_GPIO_PINS;
-    cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
     ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS;
 
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
 
     ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_GPIO_PINS;
-    cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
     TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
-#endif
+//There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
+#endif //#if TEST_SOC_HAS_INPUT_ONLY_PINS
 
     ESP_LOGI(TAG, "check native flag for 6 output pins...");
     flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
     //swap MOSI and MISO
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check native flag for 4 output pins...");
     flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
     //swap MOSI and MISO
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
-#if !DISABLED_FOR_TARGETS(ESP32C3)  //There is no input-only pin on esp32c3, so this test could be ignored.
+#if TEST_SOC_HAS_INPUT_ONLY_PINS  //There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
     ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS;
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
-    cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin...");
     flags_expected = SPICOMMON_BUSFLAG_DUAL | SPICOMMON_BUSFLAG_GPIO_PINS;
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
-    cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
-#endif
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+//There is no input-only pin on esp32c3 and esp32s3, so this test could be ignored.
+#endif //#if TEST_SOC_HAS_INPUT_ONLY_PINS
 
     ESP_LOGI(TAG, "check sclk flag...");
     flags_expected = SPICOMMON_BUSFLAG_SCLK;
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check mosi flag...");
     flags_expected = SPICOMMON_BUSFLAG_MOSI;
-    cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = -1, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check miso flag...");
     flags_expected = SPICOMMON_BUSFLAG_MISO;
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 
     ESP_LOGI(TAG, "check quad flag...");
     flags_expected = SPICOMMON_BUSFLAG_QUAD;
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
-    cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1,
-        .max_transfer_sz = 8, .flags = flags_expected};
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
-    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1,
+        .max_transfer_sz = 8, .flags = flags_expected
+    };
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
 }
 
 TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)", "[spi]")
@@ -537,19 +593,19 @@ TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)"
     TEST_ESP_OK(spi_bus_free(host));
 }
 
-DRAM_ATTR  static uint32_t data_dram[80]={0};
+DRAM_ATTR  static uint32_t data_dram[80] = {0};
 //force to place in code area.
-static const uint8_t data_drom[320+3] = {
-0xD8, 0xD1, 0x0A, 0xB8, 0xCE, 0x67, 0x1B, 0x11, 0x17, 0xA0, 0xDA, 0x89, 0x55, 0xC1, 0x40, 0x0F, 0x55, 0xEB, 0xF7, 0xEC, 0xF0, 0x3C, 0x0F, 0x4D, 0x2B, 0x9E, 0xBF, 0xCD, 0x57, 0x2C, 0x48, 0x1A,
-0x8B, 0x47, 0xC5, 0x01, 0x0C, 0x05, 0x80, 0x30, 0xF4, 0xEA, 0xE5, 0x92, 0x56, 0x97, 0x98, 0x78, 0x21, 0x34, 0xA1, 0xBC, 0xAE, 0x93, 0x7E, 0x96, 0x08, 0xE6, 0x54, 0x6A, 0x6C, 0x67, 0xCF, 0x58,
-0xEE, 0x15, 0xA8, 0xB6, 0x32, 0x8C, 0x85, 0xF7, 0xE9, 0x88, 0x5E, 0xB1, 0x76, 0xE4, 0xB2, 0xC7, 0x0F, 0x57, 0x51, 0x7A, 0x2F, 0xAB, 0x12, 0xC3, 0x37, 0x99, 0x4E, 0x67, 0x75, 0x28, 0xE4, 0x1D,
-0xF8, 0xBA, 0x22, 0xCB, 0xA1, 0x18, 0x4C, 0xAB, 0x5F, 0xC9, 0xF3, 0xA2, 0x39, 0x92, 0x44, 0xE6, 0x7B, 0xE3, 0xD0, 0x16, 0xC5, 0xC2, 0xCB, 0xD9, 0xC0, 0x7F, 0x06, 0xBF, 0x3E, 0xCE, 0xE1, 0x26,
-0xD5, 0x3C, 0xAD, 0x0E, 0xC1, 0xC7, 0x7D, 0x0D, 0x56, 0x85, 0x6F, 0x32, 0xC8, 0x63, 0x8D, 0x12, 0xAB, 0x1E, 0x81, 0x7B, 0xF4, 0xF1, 0xA9, 0xAF, 0xD9, 0x74, 0x60, 0x05, 0x3D, 0xCC, 0x0C, 0x34,
-0x11, 0x44, 0xAE, 0x2A, 0x13, 0x2F, 0x04, 0xC3, 0x59, 0xF0, 0x54, 0x07, 0xBA, 0x26, 0xD9, 0xFB, 0x80, 0x95, 0xC0, 0x14, 0xFA, 0x27, 0xEF, 0xD3, 0x58, 0xB8, 0xE4, 0xA2, 0xE3, 0x5E, 0x94, 0xB3,
-0xCD, 0x2C, 0x4F, 0xAC, 0x3B, 0xD1, 0xCA, 0xBE, 0x61, 0x71, 0x7B, 0x62, 0xEB, 0xF0, 0xFC, 0xEF, 0x22, 0xB7, 0x3F, 0x56, 0x65, 0x19, 0x61, 0x73, 0x1A, 0x4D, 0xE4, 0x23, 0xE5, 0x3A, 0x91, 0x5C,
-0xE6, 0x1B, 0x5F, 0x0E, 0x10, 0x94, 0x7C, 0x9F, 0xCF, 0x75, 0xB3, 0xEB, 0x42, 0x4C, 0xCF, 0xFE, 0xAF, 0x68, 0x62, 0x3F, 0x9A, 0x3C, 0x81, 0x3E, 0x7A, 0x45, 0x92, 0x79, 0x91, 0x4F, 0xFF, 0xDE,
-0x25, 0x18, 0x33, 0xB9, 0xA9, 0x3A, 0x3F, 0x1F, 0x4F, 0x4B, 0x5C, 0x71, 0x82, 0x75, 0xB0, 0x1F, 0xE9, 0x98, 0xA3, 0xE2, 0x65, 0xBB, 0xCA, 0x4F, 0xB7, 0x1D, 0x23, 0x43, 0x16, 0x73, 0xBD, 0x83,
-0x70, 0x22, 0x7D, 0x0A, 0x6D, 0xD3, 0x77, 0x73, 0xD0, 0xF4, 0x06, 0xB2, 0x19, 0x8C, 0xFF, 0x58, 0xE4, 0xDB, 0xE9, 0xEC, 0x89, 0x6A, 0xF4, 0x0E, 0x67, 0x12, 0xEC, 0x11, 0xD2, 0x1F, 0x8D, 0xD7,
+static const uint8_t data_drom[320 + 3] = {
+    0xD8, 0xD1, 0x0A, 0xB8, 0xCE, 0x67, 0x1B, 0x11, 0x17, 0xA0, 0xDA, 0x89, 0x55, 0xC1, 0x40, 0x0F, 0x55, 0xEB, 0xF7, 0xEC, 0xF0, 0x3C, 0x0F, 0x4D, 0x2B, 0x9E, 0xBF, 0xCD, 0x57, 0x2C, 0x48, 0x1A,
+    0x8B, 0x47, 0xC5, 0x01, 0x0C, 0x05, 0x80, 0x30, 0xF4, 0xEA, 0xE5, 0x92, 0x56, 0x97, 0x98, 0x78, 0x21, 0x34, 0xA1, 0xBC, 0xAE, 0x93, 0x7E, 0x96, 0x08, 0xE6, 0x54, 0x6A, 0x6C, 0x67, 0xCF, 0x58,
+    0xEE, 0x15, 0xA8, 0xB6, 0x32, 0x8C, 0x85, 0xF7, 0xE9, 0x88, 0x5E, 0xB1, 0x76, 0xE4, 0xB2, 0xC7, 0x0F, 0x57, 0x51, 0x7A, 0x2F, 0xAB, 0x12, 0xC3, 0x37, 0x99, 0x4E, 0x67, 0x75, 0x28, 0xE4, 0x1D,
+    0xF8, 0xBA, 0x22, 0xCB, 0xA1, 0x18, 0x4C, 0xAB, 0x5F, 0xC9, 0xF3, 0xA2, 0x39, 0x92, 0x44, 0xE6, 0x7B, 0xE3, 0xD0, 0x16, 0xC5, 0xC2, 0xCB, 0xD9, 0xC0, 0x7F, 0x06, 0xBF, 0x3E, 0xCE, 0xE1, 0x26,
+    0xD5, 0x3C, 0xAD, 0x0E, 0xC1, 0xC7, 0x7D, 0x0D, 0x56, 0x85, 0x6F, 0x32, 0xC8, 0x63, 0x8D, 0x12, 0xAB, 0x1E, 0x81, 0x7B, 0xF4, 0xF1, 0xA9, 0xAF, 0xD9, 0x74, 0x60, 0x05, 0x3D, 0xCC, 0x0C, 0x34,
+    0x11, 0x44, 0xAE, 0x2A, 0x13, 0x2F, 0x04, 0xC3, 0x59, 0xF0, 0x54, 0x07, 0xBA, 0x26, 0xD9, 0xFB, 0x80, 0x95, 0xC0, 0x14, 0xFA, 0x27, 0xEF, 0xD3, 0x58, 0xB8, 0xE4, 0xA2, 0xE3, 0x5E, 0x94, 0xB3,
+    0xCD, 0x2C, 0x4F, 0xAC, 0x3B, 0xD1, 0xCA, 0xBE, 0x61, 0x71, 0x7B, 0x62, 0xEB, 0xF0, 0xFC, 0xEF, 0x22, 0xB7, 0x3F, 0x56, 0x65, 0x19, 0x61, 0x73, 0x1A, 0x4D, 0xE4, 0x23, 0xE5, 0x3A, 0x91, 0x5C,
+    0xE6, 0x1B, 0x5F, 0x0E, 0x10, 0x94, 0x7C, 0x9F, 0xCF, 0x75, 0xB3, 0xEB, 0x42, 0x4C, 0xCF, 0xFE, 0xAF, 0x68, 0x62, 0x3F, 0x9A, 0x3C, 0x81, 0x3E, 0x7A, 0x45, 0x92, 0x79, 0x91, 0x4F, 0xFF, 0xDE,
+    0x25, 0x18, 0x33, 0xB9, 0xA9, 0x3A, 0x3F, 0x1F, 0x4F, 0x4B, 0x5C, 0x71, 0x82, 0x75, 0xB0, 0x1F, 0xE9, 0x98, 0xA3, 0xE2, 0x65, 0xBB, 0xCA, 0x4F, 0xB7, 0x1D, 0x23, 0x43, 0x16, 0x73, 0xBD, 0x83,
+    0x70, 0x22, 0x7D, 0x0A, 0x6D, 0xD3, 0x77, 0x73, 0xD0, 0xF4, 0x06, 0xB2, 0x19, 0x8C, 0xFF, 0x58, 0xE4, 0xDB, 0xE9, 0xEC, 0x89, 0x6A, 0xF4, 0x0E, 0x67, 0x12, 0xEC, 0x11, 0xD2, 0x1F, 0x8D, 0xD7,
 };
 
 TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
@@ -557,10 +613,10 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
 #ifdef CONFIG_SPIRAM
     //test psram if enabled
     ESP_LOGI(TAG, "testing PSRAM...");
-    uint32_t* data_malloc = (uint32_t*)heap_caps_malloc(324, MALLOC_CAP_SPIRAM);
+    uint32_t *data_malloc = (uint32_t *)heap_caps_malloc(324, MALLOC_CAP_SPIRAM);
     TEST_ASSERT(esp_ptr_external_ram(data_malloc));
 #else
-    uint32_t* data_malloc = (uint32_t*)heap_caps_malloc(324, MALLOC_CAP_DMA);
+    uint32_t *data_malloc = (uint32_t *)heap_caps_malloc(324, MALLOC_CAP_DMA);
     TEST_ASSERT(esp_ptr_in_dram(data_malloc));
 #endif
     TEST_ASSERT(data_malloc != NULL);
@@ -570,14 +626,14 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
     ESP_LOGI(TAG, "drom: %p, malloc: %p", data_drom, data_malloc);
 
 #ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
-    uint32_t* data_iram = (uint32_t*)heap_caps_malloc(324, MALLOC_CAP_EXEC);
+    uint32_t *data_iram = (uint32_t *)heap_caps_malloc(324, MALLOC_CAP_EXEC);
     TEST_ASSERT(data_iram != NULL);
     TEST_ASSERT(esp_ptr_executable(data_iram) || esp_ptr_in_iram(data_iram) || esp_ptr_in_diram_iram(data_iram));
     ESP_LOGI(TAG, "iram: %p", data_iram);
 #endif
 
     srand(52);
-    for (int i = 0; i < 320/4; i++) {
+    for (int i = 0; i < 320 / 4; i++) {
 #ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
         data_iram[i] = rand();
 #endif
@@ -587,9 +643,9 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
 
     esp_err_t ret;
     spi_device_handle_t spi;
-    spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG();
+    spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
     buscfg.miso_io_num = PIN_NUM_MOSI;
-    spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG();
+    spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
 
     //Initialize the SPI bus
     TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
@@ -604,43 +660,43 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
     memset(trans, 0, sizeof(trans));
 
 #ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
-    trans[0].length = 320*8,
-    trans[0].tx_buffer = data_iram;
-    trans[0].rx_buffer = data_malloc+1;
+    trans[0].length = 320 * 8,
+            trans[0].tx_buffer = data_iram;
+    trans[0].rx_buffer = data_malloc + 1;
 
-    trans[1].length = 320*8,
-    trans[1].tx_buffer = data_dram;
+    trans[1].length = 320 * 8,
+            trans[1].tx_buffer = data_dram;
     trans[1].rx_buffer = data_iram;
 
-    trans[2].length = 320*8,
-    trans[2].tx_buffer = data_drom;
+    trans[2].length = 320 * 8,
+            trans[2].tx_buffer = data_drom;
     trans[2].rx_buffer = data_iram;
 #endif
 
-    trans[3].length = 320*8,
-    trans[3].tx_buffer = data_malloc+2;
+    trans[3].length = 320 * 8,
+            trans[3].tx_buffer = data_malloc + 2;
     trans[3].rx_buffer = data_dram;
 
-    trans[4].length = 4*8,
-    trans[4].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA;
-    uint32_t* ptr = (uint32_t*)trans[4].rx_data;
+    trans[4].length = 4 * 8,
+            trans[4].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA;
+    uint32_t *ptr = (uint32_t *)trans[4].rx_data;
     *ptr = 0x54545454;
-    ptr = (uint32_t*)trans[4].tx_data;
+    ptr = (uint32_t *)trans[4].tx_data;
     *ptr = 0xbc124960;
 
     //Queue all transactions.
 #ifndef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
-    for (x=0; x<TEST_REGION_SIZE; x++) {
+    for (x = 0; x < TEST_REGION_SIZE; x++) {
 #else
-    for (x=3; x<TEST_REGION_SIZE; x++) {
+    for (x = 3; x < TEST_REGION_SIZE; x++) {
 #endif
         ESP_LOGI(TAG, "transmitting %d...", x);
-        ret=spi_device_transmit(spi,&trans[x]);
-        TEST_ASSERT(ret==ESP_OK);
+        ret = spi_device_transmit(spi, &trans[x]);
+        TEST_ASSERT(ret == ESP_OK);
         if (trans[x].flags & SPI_TRANS_USE_RXDATA) {
             TEST_ASSERT_EQUAL_HEX8_ARRAY(trans[x].tx_data, trans[x].rx_data, 4);
         } else {
-            TEST_ASSERT_EQUAL_HEX32_ARRAY(trans[x].tx_buffer, trans[x].rx_buffer, trans[x].length / 8 /4);
+            TEST_ASSERT_EQUAL_HEX32_ARRAY(trans[x].tx_buffer, trans[x].rx_buffer, trans[x].length / 8 / 4);
         }
     }
     TEST_ASSERT(spi_bus_remove_device(spi) == ESP_OK);
@@ -657,23 +713,23 @@ TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]")
 // 3. setting rx_length != length
 TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
 {
-    uint8_t tx_buf[320]={0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43};
+    uint8_t tx_buf[320] = {0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43};
     uint8_t rx_buf[320];
 
     spi_device_handle_t spi;
-    spi_bus_config_t buscfg={
-        .miso_io_num=PIN_NUM_MOSI,
-        .mosi_io_num=PIN_NUM_MOSI,
-        .sclk_io_num=PIN_NUM_CLK,
-        .quadwp_io_num=-1,
-        .quadhd_io_num=-1
+    spi_bus_config_t buscfg = {
+        .miso_io_num = PIN_NUM_MOSI,
+        .mosi_io_num = PIN_NUM_MOSI,
+        .sclk_io_num = PIN_NUM_CLK,
+        .quadwp_io_num = -1,
+        .quadhd_io_num = -1
     };
-    spi_device_interface_config_t devcfg={
-        .clock_speed_hz=10*1000*1000,               //Clock out at 10 MHz
-        .mode=0,                                //SPI mode 0
-        .spics_io_num=PIN_NUM_CS,               //CS pin
-        .queue_size=7,                          //We want to be able to queue 7 transactions at a time
-        .pre_cb=NULL,
+    spi_device_interface_config_t devcfg = {
+        .clock_speed_hz = 10 * 1000 * 1000,         //Clock out at 10 MHz
+        .mode = 0,                              //SPI mode 0
+        .spics_io_num = PIN_NUM_CS,             //CS pin
+        .queue_size = 7,                        //We want to be able to queue 7 transactions at a time
+        .pre_cb = NULL,
     };
     //Initialize the SPI bus
     TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
@@ -689,9 +745,9 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
         memset( rx_buf, 0x66, sizeof(rx_buf));
 
         spi_transaction_t t = {};
-        t.length = 8*(i+1);
+        t.length = 8 * (i + 1);
         t.rxlength = 0;
-        t.tx_buffer = tx_buf+2*i;
+        t.tx_buffer = tx_buf + 2 * i;
         t.rx_buffer = rx_buf + i;
 
         if ( i == 1 ) {
@@ -703,7 +759,7 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
         }
         spi_device_transmit( spi, &t );
 
-        for( int i = 0; i < 16; i ++ ) {
+        for ( int i = 0; i < 16; i ++ ) {
             printf("%02X ", rx_buf[i]);
         }
         printf("\n");
@@ -712,10 +768,10 @@ TEST_CASE("SPI Master DMA test: length, start, not aligned", "[spi]")
             // no rx, skip check
         } else if ( i == 2 ) {
             //test rx length = tx length-1
-            TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length/8-1 );
+            TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length / 8 - 1 );
         } else {
             //normal check
-            TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length/8 );
+            TEST_ASSERT_EQUAL_HEX8_ARRAY(t.tx_buffer, t.rx_buffer, t.length / 8 );
         }
     }
 
@@ -730,7 +786,9 @@ static uint8_t bitswap(uint8_t in)
     uint8_t out = 0;
     for (int i = 0; i < 8; i++) {
         out = out >> 1;
-        if (in&0x80) out |= 0x80;
+        if (in & 0x80) {
+            out |= 0x80;
+        }
         in = in << 1;
     }
     return out;
@@ -740,15 +798,17 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
 {
     spi_device_handle_t spi;
 
-    ESP_LOGI(MASTER_TAG, ">>>>>>>>> TEST %s FIRST <<<<<<<<<<<", lsb_first?"LSB":"MSB");
+    ESP_LOGI(MASTER_TAG, ">>>>>>>>> TEST %s FIRST <<<<<<<<<<<", lsb_first ? "LSB" : "MSB");
 
     //initial master, mode 0, 1MHz
-    spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG();
+    spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
     buscfg.quadhd_io_num = UNCONNECTED_PIN;
     TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
-    spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG();
-    devcfg.clock_speed_hz = 1*1000*1000;
-    if (lsb_first) devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST;
+    spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
+    devcfg.clock_speed_hz = 1 * 1000 * 1000;
+    if (lsb_first) {
+        devcfg.flags |= SPI_DEVICE_BIT_LSBFIRST;
+    }
     TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &spi));
 
     //connecting pins to two peripherals breaks the output, fix it.
@@ -757,25 +817,25 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
     spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[0]);
     spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out);
 
-    for (int i= 0; i < 8; i++) {
+    for (int i = 0; i < 8; i++) {
         //prepare slave tx data
         slave_txdata_t slave_txdata = (slave_txdata_t) {
-            .start = spitest_slave_send + 4*(i%3),
+            .start = spitest_slave_send + 4 * (i % 3),
             .len = 256,
         };
         xQueueSend(slave_context->data_to_send, &slave_txdata, portMAX_DELAY);
 
         vTaskDelay(50);
         //prepare master tx data
-        int cmd_bits = (i+1)*2;
+        int cmd_bits = (i + 1) * 2;
         int addr_bits =
 #ifdef CONFIG_IDF_TARGET_ESP32
-                56-8*i;
+            56 - 8 * i;
 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
-        //ESP32S2 only supportes up to 32 bits address
-                28-4*i;
+            //ESP32S2 only supportes up to 32 bits address
+            28 - 4 * i;
 #endif
-        int round_up = (cmd_bits+addr_bits+7)/8*8;
+        int round_up = (cmd_bits + addr_bits + 7) / 8 * 8;
         addr_bits = round_up - cmd_bits;
 
         spi_transaction_ext_t trans = (spi_transaction_ext_t) {
@@ -790,51 +850,53 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
 
         ESP_LOGI( MASTER_TAG, "===== test%d =====", i );
         ESP_LOGI(MASTER_TAG, "cmd_bits: %d, addr_bits: %d", cmd_bits, addr_bits);
-        TEST_ESP_OK(spi_device_transmit(spi, (spi_transaction_t*)&trans));
+        TEST_ESP_OK(spi_device_transmit(spi, (spi_transaction_t *)&trans));
         //wait for both master and slave end
 
         size_t rcv_len;
         slave_rxdata_t *rcv_data = xRingbufferReceive(slave_context->data_received, &rcv_len, portMAX_DELAY);
-        rcv_len-=8;
+        rcv_len -= 8;
         uint8_t *buffer = rcv_data->data;
 
         ESP_LOGI(SLAVE_TAG, "trans_len: %d", rcv_len);
-        TEST_ASSERT_EQUAL(rcv_len, (rcv_data->len+7)/8);
-        TEST_ASSERT_EQUAL(rcv_data->len, cmd_bits+addr_bits);
+        TEST_ASSERT_EQUAL(rcv_len, (rcv_data->len + 7) / 8);
+        TEST_ASSERT_EQUAL(rcv_data->len, cmd_bits + addr_bits);
         ESP_LOG_BUFFER_HEX("slave rx", buffer, rcv_len);
 
         uint16_t cmd_expected = trans.base.cmd & (BIT(cmd_bits) - 1);
-        uint64_t addr_expected = trans.base.addr & ((1ULL<<addr_bits) - 1);
+        uint64_t addr_expected = trans.base.addr & ((1ULL << addr_bits) - 1);
 
         uint8_t *data_ptr = buffer;
-        uint16_t cmd_got = *(uint16_t*)data_ptr;
-        data_ptr += cmd_bits/8;
+        uint16_t cmd_got = *(uint16_t *)data_ptr;
+        data_ptr += cmd_bits / 8;
         cmd_got = __builtin_bswap16(cmd_got);
-        cmd_got = cmd_got >> (16-cmd_bits);
+        cmd_got = cmd_got >> (16 - cmd_bits);
         int remain_bits = cmd_bits % 8;
 
-        uint64_t addr_got = *(uint64_t*)data_ptr;
+        uint64_t addr_got = *(uint64_t *)data_ptr;
         data_ptr += 8;
         addr_got = __builtin_bswap64(addr_got);
         addr_got = (addr_got << remain_bits);
-        addr_got |= (*data_ptr >> (8-remain_bits));
-        addr_got = addr_got >> (64-addr_bits);
+        addr_got |= (*data_ptr >> (8 - remain_bits));
+        addr_got = addr_got >> (64 - addr_bits);
 
         if (lsb_first) {
             cmd_got = __builtin_bswap16(cmd_got);
             addr_got = __builtin_bswap64(addr_got);
 
-            uint8_t *swap_ptr = (uint8_t*)&cmd_got;
+            uint8_t *swap_ptr = (uint8_t *)&cmd_got;
             swap_ptr[0] = bitswap(swap_ptr[0]);
             swap_ptr[1] = bitswap(swap_ptr[1]);
-            cmd_got = cmd_got >> (16-cmd_bits);
+            cmd_got = cmd_got >> (16 - cmd_bits);
 
-            swap_ptr = (uint8_t*)&addr_got;
-            for (int j = 0; j < 8; j++) swap_ptr[j] = bitswap(swap_ptr[j]);
-            addr_got = addr_got >> (64-addr_bits);
+            swap_ptr = (uint8_t *)&addr_got;
+            for (int j = 0; j < 8; j++) {
+                swap_ptr[j] = bitswap(swap_ptr[j]);
+            }
+            addr_got = addr_got >> (64 - addr_bits);
         }
 
-        ESP_LOGI(SLAVE_TAG, "cmd_got: %04X, addr_got: %08X%08X", cmd_got, (uint32_t)(addr_got>>32), (uint32_t)addr_got);
+        ESP_LOGI(SLAVE_TAG, "cmd_got: %04X, addr_got: %08X%08X", cmd_got, (uint32_t)(addr_got >> 32), (uint32_t)addr_got);
 
         TEST_ASSERT_EQUAL_HEX16(cmd_expected, cmd_got);
         if (addr_bits > 0) {
@@ -850,7 +912,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)
     TEST_ASSERT(spi_bus_free(TEST_SPI_HOST) == ESP_OK);
 }
 
-TEST_CASE("SPI master variable cmd & addr test","[spi]")
+TEST_CASE("SPI master variable cmd & addr test", "[spi]")
 {
     spi_slave_task_context_t slave_context = {};
     esp_err_t err = init_slave_context( &slave_context );
@@ -861,8 +923,8 @@ TEST_CASE("SPI master variable cmd & addr test","[spi]")
     //initial slave, mode 0, no dma
     int dma_chan = 0;
     int slave_mode = 0;
-    spi_bus_config_t slv_buscfg=SPI_BUS_TEST_DEFAULT_CONFIG();
-    spi_slave_interface_config_t slvcfg=SPI_SLAVE_TEST_DEFAULT_CONFIG();
+    spi_bus_config_t slv_buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
+    spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
     slvcfg.mode = slave_mode;
     //Initialize SPI slave interface
     TEST_ESP_OK( spi_slave_initialize(TEST_SLAVE_HOST, &slv_buscfg, &slvcfg, dma_chan) );
@@ -880,14 +942,14 @@ TEST_CASE("SPI master variable cmd & addr test","[spi]")
     ESP_LOGI(MASTER_TAG, "test passed.");
 }
 
-void test_dummy(spi_device_handle_t spi, int dummy_n, uint8_t* data_to_send, int len)
+void test_dummy(spi_device_handle_t spi, int dummy_n, uint8_t *data_to_send, int len)
 {
     ESP_LOGI(TAG, "testing dummy n=%d", dummy_n);
-    WORD_ALIGNED_ATTR uint8_t slave_buffer[len+(dummy_n+7)/8];
+    WORD_ALIGNED_ATTR uint8_t slave_buffer[len + (dummy_n + 7) / 8];
     spi_slave_transaction_t slave_t = {
         .tx_buffer = slave_buffer,
         .rx_buffer = slave_buffer,
-        .length = len*8+((dummy_n+7)&(~8))+32,  //receive more bytes to avoid slave discarding data
+        .length = len * 8 + ((dummy_n + 7) & (~8)) + 32, //receive more bytes to avoid slave discarding data
     };
     TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_t, portMAX_DELAY));
 
@@ -896,24 +958,24 @@ void test_dummy(spi_device_handle_t spi, int dummy_n, uint8_t* data_to_send, int
     spi_transaction_ext_t t = {
         .base = {
             .tx_buffer = data_to_send,
-            .length = (len+1)*8,    //send one more byte force slave receive all data
+            .length = (len + 1) * 8, //send one more byte force slave receive all data
             .flags = SPI_TRANS_VARIABLE_DUMMY,
         },
         .dummy_bits = dummy_n,
     };
-    TEST_ESP_OK(spi_device_transmit(spi, (spi_transaction_t*)&t));
+    TEST_ESP_OK(spi_device_transmit(spi, (spi_transaction_t *)&t));
 
     spi_slave_transaction_t *ret_slave;
     TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_slave, portMAX_DELAY));
     TEST_ASSERT(ret_slave == &slave_t);
 
-    ESP_LOG_BUFFER_HEXDUMP("rcv", slave_buffer, len+4, ESP_LOG_INFO);
-    int skip_cnt = dummy_n/8;
+    ESP_LOG_BUFFER_HEXDUMP("rcv", slave_buffer, len + 4, ESP_LOG_INFO);
+    int skip_cnt = dummy_n / 8;
     int dummy_remain = dummy_n % 8;
     uint8_t *slave_ptr = slave_buffer;
     if (dummy_remain > 0) {
         for (int i = 0; i < len; i++) {
-            slave_ptr[0] = (slave_ptr[skip_cnt] << dummy_remain) | (slave_ptr[skip_cnt+1] >> (8-dummy_remain));
+            slave_ptr[0] = (slave_ptr[skip_cnt] << dummy_remain) | (slave_ptr[skip_cnt + 1] >> (8 - dummy_remain));
             slave_ptr++;
         }
     } else {
@@ -978,7 +1040,7 @@ TEST_CASE("SPI master hd dma TX without RX test", "[spi]")
     spi_device_handle_t spi;
     spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
     dev_cfg.flags = SPI_DEVICE_HALFDUPLEX;
-    dev_cfg.clock_speed_hz = 4*1000*1000;
+    dev_cfg.clock_speed_hz = 4 * 1000 * 1000;
     TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
 
     spi_slave_interface_config_t slave_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
@@ -1070,31 +1132,33 @@ TEST_CASE("SPI master hd dma TX without RX test", "[spi]")
 #define GET_US_BY_CCOUNT(t) ((double)t/CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ)
 #endif
 
-static void speed_setup(spi_device_handle_t* spi, bool use_dma)
+static void speed_setup(spi_device_handle_t *spi, bool use_dma)
 {
-    spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG();
-    spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG();
-    devcfg.queue_size=8;       //We want to be able to queue 7 transactions at a time
+    spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
+    spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
+    devcfg.queue_size = 8;     //We want to be able to queue 7 transactions at a time
 
     //Initialize the SPI bus and the device to test
     TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma ? SPI_DMA_CH_AUTO : 0)));
     TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi));
 }
 
-static void sorted_array_insert(uint32_t* array, int* size, uint32_t item)
+static void sorted_array_insert(uint32_t *array, int *size, uint32_t item)
 {
     int pos;
-    for (pos = *size; pos>0; pos--) {
-        if (array[pos-1] < item) break;
-        array[pos] = array[pos-1];
+    for (pos = *size; pos > 0; pos--) {
+        if (array[pos - 1] < item) {
+            break;
+        }
+        array[pos] = array[pos - 1];
     }
-    array[pos]=item;
+    array[pos] = item;
     (*size)++;
 }
 
 #define TEST_TIMES  11
 
-static IRAM_ATTR NOINLINE_ATTR void spi_transmit_measure(spi_device_handle_t spi, spi_transaction_t* trans, uint32_t* t_flight)
+static IRAM_ATTR NOINLINE_ATTR void spi_transmit_measure(spi_device_handle_t spi, spi_transaction_t *trans, uint32_t *t_flight)
 {
     RECORD_TIME_PREPARE();
     spi_device_transmit(spi, trans); // prime the flash cache
@@ -1103,7 +1167,7 @@ static IRAM_ATTR NOINLINE_ATTR void spi_transmit_measure(spi_device_handle_t spi
     RECORD_TIME_END(t_flight);
 }
 
-static IRAM_ATTR NOINLINE_ATTR void spi_transmit_polling_measure(spi_device_handle_t spi, spi_transaction_t* trans, uint32_t* t_flight)
+static IRAM_ATTR NOINLINE_ATTR void spi_transmit_polling_measure(spi_device_handle_t spi, spi_transaction_t *trans, uint32_t *t_flight)
 {
     spi_flash_disable_interrupts_caches_and_other_cpu();    //this can test the code are all in the IRAM at the same time
     RECORD_TIME_PREPARE();
@@ -1114,7 +1178,7 @@ static IRAM_ATTR NOINLINE_ATTR void spi_transmit_polling_measure(spi_device_hand
     spi_flash_enable_interrupts_caches_and_other_cpu();
 }
 
-TEST_CASE("spi_speed","[spi]")
+TEST_CASE("spi_speed", "[spi]")
 {
     uint32_t t_flight;
     //to get rid of the influence of randomly interrupts, we measured the performance by median value
@@ -1125,7 +1189,7 @@ TEST_CASE("spi_speed","[spi]")
     spi_device_handle_t spi;
     const bool use_dma = true;
     WORD_ALIGNED_ATTR spi_transaction_t trans = {
-        .length = 1*8,
+        .length = 1 * 8,
         .flags = SPI_TRANS_USE_TXDATA,
     };
 
@@ -1142,7 +1206,7 @@ TEST_CASE("spi_speed","[spi]")
         ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
     }
 #ifndef CONFIG_SPIRAM
-    TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
+    TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif
 
     //acquire the bus to send polling transactions faster
@@ -1159,7 +1223,7 @@ TEST_CASE("spi_speed","[spi]")
         ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
     }
 #ifndef CONFIG_SPIRAM
-    TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
+    TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif
 
     //release the bus
@@ -1179,7 +1243,7 @@ TEST_CASE("spi_speed","[spi]")
         ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
     }
 #ifndef CONFIG_SPIRAM
-    TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
+    TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_NO_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif
 
     //acquire the bus to send polling transactions faster
@@ -1195,7 +1259,7 @@ TEST_CASE("spi_speed","[spi]")
         ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
     }
 #ifndef CONFIG_SPIRAM
-    TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES+1)/2]));
+    TEST_PERFORMANCE_LESS_THAN(SPI_PER_TRANS_POLLING_NO_DMA, "%d us", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif
 
     //release the bus
diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h
index 234b477578..c02bb1d4c0 100644
--- a/components/hal/esp32s3/include/hal/gpio_ll.h
+++ b/components/hal/esp32s3/include/hal/gpio_ll.h
@@ -26,6 +26,7 @@
 #include "soc/gpio_periph.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/rtc_io_reg.h"
+#include "soc/usb_serial_jtag_reg.h"
 #include "hal/gpio_types.h"
 
 #ifdef __cplusplus
@@ -399,6 +400,9 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
  */
 static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
 {
+    if (pin_name == IO_MUX_GPIO19_REG || pin_name == IO_MUX_GPIO20_REG) {
+        CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
+    }
     PIN_FUNC_SELECT(pin_name, func);
 }
 
diff --git a/components/hal/include/hal/gpio_types.h b/components/hal/include/hal/gpio_types.h
index 8f795e6a65..53f20662da 100644
--- a/components/hal/include/hal/gpio_types.h
+++ b/components/hal/include/hal/gpio_types.h
@@ -78,6 +78,7 @@ typedef enum {
 #define GPIO_SEL_46             ((uint64_t)(((uint64_t)1)<<46))  /*!< Pin 46 selected */
 #if CONFIG_IDF_TARGET_ESP32S3
 #define GPIO_SEL_47             ((uint64_t)(((uint64_t)1)<<47))  /*!< Pin 47 selected */
+#define GPIO_SEL_48             ((uint64_t)(((uint64_t)1)<<48))  /*!< Pin 48 selected */
 #endif
 #endif
 
@@ -129,6 +130,7 @@ typedef enum {
 #define GPIO_PIN_REG_45          IO_MUX_GPIO45_REG
 #define GPIO_PIN_REG_46          IO_MUX_GPIO46_REG
 #define GPIO_PIN_REG_47          IO_MUX_GPIO47_REG
+#define GPIO_PIN_REG_48          IO_MUX_GPIO48_REG
 
 #if CONFIG_IDF_TARGET_ESP32
 typedef enum {
@@ -269,8 +271,9 @@ typedef enum {
     GPIO_NUM_43 = 43,   /*!< GPIO43, input and output */
     GPIO_NUM_44 = 44,   /*!< GPIO44, input and output */
     GPIO_NUM_45 = 45,   /*!< GPIO45, input and output */
-    GPIO_NUM_46 = 46,   /*!< GPIO46, input mode only */
+    GPIO_NUM_46 = 46,   /*!< GPIO46, input and output */
     GPIO_NUM_47 = 47,   /*!< GPIO47, input and output */
+    GPIO_NUM_48 = 48,   /*!< GPIO48, input and output */
     GPIO_NUM_MAX,
 /** @endcond */
 } gpio_num_t;
diff --git a/components/soc/esp32s3/gpio_periph.c b/components/soc/esp32s3/gpio_periph.c
index 751c79e901..143f02f1fb 100644
--- a/components/soc/esp32s3/gpio_periph.c
+++ b/components/soc/esp32s3/gpio_periph.c
@@ -63,6 +63,7 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
     IO_MUX_GPIO45_REG,
     IO_MUX_GPIO46_REG,
     IO_MUX_GPIO47_REG,
+    IO_MUX_GPIO48_REG,
 };
 
 const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
diff --git a/components/soc/esp32s3/include/soc/gpio_caps.h b/components/soc/esp32s3/include/soc/gpio_caps.h
index 5ccac017df..68b64dc1dd 100644
--- a/components/soc/esp32s3/include/soc/gpio_caps.h
+++ b/components/soc/esp32s3/include/soc/gpio_caps.h
@@ -20,17 +20,17 @@ extern "C" {
 
 // ESP32-S3 has 1 GPIO peripheral
 #define SOC_GPIO_PORT           (1)
-#define SOC_GPIO_PIN_COUNT      (48)
+#define SOC_GPIO_PIN_COUNT      (49)
 
 // On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
 #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
 // Force hold is a new function of ESP32-S3
 #define SOC_GPIO_SUPPORT_FORCE_HOLD      (1)
 
-// 0~47 except from 22~25 are valid
-#define SOC_GPIO_VALID_GPIO_MASK         (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
-// GPIO 46 is input only
-#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK  (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46))
+// 0~48 except from 22~25 are valid
+#define SOC_GPIO_VALID_GPIO_MASK         (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
+// No GPIO is input only
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK  (SOC_GPIO_VALID_GPIO_MASK)
 
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32s3/rtc_io_periph.c b/components/soc/esp32s3/rtc_io_periph.c
index 47f502feb9..6ba215d9c2 100644
--- a/components/soc/esp32s3/rtc_io_periph.c
+++ b/components/soc/esp32s3/rtc_io_periph.c
@@ -63,6 +63,7 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
     -1,//GPIO45
     -1,//GPIO46
     -1,//GPIO47
+    -1,//GPIO48
 };
 
 //Reg,Mux,Fun,IE,Up,Down,Rtc_number
diff --git a/docs/en/api-reference/peripherals/gpio.rst b/docs/en/api-reference/peripherals/gpio.rst
index 5a379a8b77..2f3d0ce214 100644
--- a/docs/en/api-reference/peripherals/gpio.rst
+++ b/docs/en/api-reference/peripherals/gpio.rst
@@ -6,7 +6,7 @@ Overview
 
 .. only:: esp32
 
-    The {IDF_TARGET_NAME} chip features 40 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal.
+    The {IDF_TARGET_NAME} chip features 34 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal.
 
     - Note that GPIO6-11 are usually used for SPI flash.
     - GPIO34-39 can only be set as input mode and do not have software pullup or pulldown functions.
@@ -26,6 +26,14 @@ Overview
     - Note that GPIO 18 and 19 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers.
     - {IDF_TARGET_NAME} doesn't have separate "RTC GPIO" support. However, GPIO0-5 keep the rtc feature, which can be used for power-management and analog subsystem.
 
+.. only:: esp32s3
+
+    The {IDF_TARGET_NAME} chip features 45 physical GPIO pads. Some GPIO pads cannot be used or do not have the corresponding pin on the chip package. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. Each pad can be used as a general purpose I/O or can be connected to an internal peripheral signal.
+
+    - Note that GPIO26-32 are usually used for SPI flash.
+    - Note that GPIO 19 and 20 are used by USB-JTAG by default. In order to use them as GPIOs, USB-JTAG will be disabled by the drivers.
+    - Note that when using SPI eight-line mode, GPIO33~37 are connected to IO4~IO7 and DQS. On ESP32-S3R8 / ESP32-S3R8V board GPIO33~37 are not recommended for other uses.
+
 .. only:: SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 
     There is also separate "RTC GPIO" support, which functions when GPIOs are routed to the "RTC" low-power and analog subsystem. These pin functions can be used when:
diff --git a/docs/en/api-reference/peripherals/sigmadelta.rst b/docs/en/api-reference/peripherals/sigmadelta.rst
index 17d635d098..f3c45472ed 100644
--- a/docs/en/api-reference/peripherals/sigmadelta.rst
+++ b/docs/en/api-reference/peripherals/sigmadelta.rst
@@ -1,6 +1,8 @@
 Sigma-delta Modulation
 ======================
 
+{IDF_TARGET_SIGMA_DELTA_MODULATION_CHANNEL_NUM:default="8", esp32c3="4"}
+
 Introduction
 ------------
 
@@ -9,13 +11,7 @@ Introduction
 Functionality Overview
 ----------------------
 
-.. only:: esp32 or esp32s2
-
-    There are eight independent sigma-delta modulation channels identified with :cpp:type:`sigmadelta_channel_t`. Each channel is capable to output the binary, hardware generated signal with the sigma-delta modulation.
-
-.. only:: esp32c3
-
-    There are four independent sigma-delta modulation channels identified with :cpp:type:`sigmadelta_channel_t`. Each channel is capable to output the binary, hardware generated signal with the sigma-delta modulation.
+There are {IDF_TARGET_SIGMA_DELTA_MODULATION_CHANNEL_NUM} independent sigma-delta modulation channels identified with :cpp:type:`sigmadelta_channel_t`. Each channel is capable to output the binary, hardware generated signal with the sigma-delta modulation.
 
 Selected channel should be set up by providing configuration parameters in :cpp:type:`sigmadelta_config_t` and then applying this configuration with :cpp:func:`sigmadelta_config`.