From 232da4ca72b7b4582d1f22021639e69470f1ad42 Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Tue, 10 Jan 2023 19:52:03 +0800 Subject: [PATCH 1/5] flash mmap: more config option for flash mmap test app --- .../test_apps/flash_mmap/pytest_flash_mmap.py | 46 +++++++++++++++++-- .../flash_mmap/sdkconfig.ci.rom_impl | 1 + .../flash_mmap/sdkconfig.ci.xip_psram | 2 + .../sdkconfig.ci.xip_psram_with_rom_impl | 4 ++ 4 files changed, 50 insertions(+), 3 deletions(-) create mode 100644 components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.rom_impl create mode 100644 components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram create mode 100644 components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram_with_rom_impl diff --git a/components/spi_flash/test_apps/flash_mmap/pytest_flash_mmap.py b/components/spi_flash/test_apps/flash_mmap/pytest_flash_mmap.py index 94e8364213..ce5fb64224 100644 --- a/components/spi_flash/test_apps/flash_mmap/pytest_flash_mmap.py +++ b/components/spi_flash/test_apps/flash_mmap/pytest_flash_mmap.py @@ -16,6 +16,46 @@ from pytest_embedded import Dut indirect=True, ) def test_flash_mmap(dut: Dut) -> None: - dut.expect_exact('Press ENTER to see the list of tests') - dut.write('*') - dut.expect_unity_test_output(timeout=120) + dut.run_all_single_board_cases(timeout=30) + + +@pytest.mark.esp32s3 +@pytest.mark.esp32c3 +@pytest.mark.esp32c2 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'rom_impl', + ], + indirect=True, +) +def test_flash_mmap_rom_impl(dut: Dut) -> None: + dut.run_all_single_board_cases(timeout=30) + + +@pytest.mark.esp32s2 +@pytest.mark.esp32s3 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'xip_psram', + ], + indirect=True, +) +def test_flash_mmap_xip_psram(dut: Dut) -> None: + dut.run_all_single_board_cases(timeout=30) + + +@pytest.mark.esp32s3 +@pytest.mark.generic +@pytest.mark.parametrize( + 'config', + [ + 'xip_psram_with_rom_impl', + ], + indirect=True, +) +def test_flash_mmap_xip_psram_rom_impl(dut: Dut) -> None: + dut.run_all_single_board_cases(timeout=30) diff --git a/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.rom_impl b/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.rom_impl new file mode 100644 index 0000000000..edd9b33ea8 --- /dev/null +++ b/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.rom_impl @@ -0,0 +1 @@ +CONFIG_SPI_FLASH_ROM_IMPL=y diff --git a/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram b/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram new file mode 100644 index 0000000000..e5e840609e --- /dev/null +++ b/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram @@ -0,0 +1,2 @@ +CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y +CONFIG_SPIRAM_RODATA=y diff --git a/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram_with_rom_impl b/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram_with_rom_impl new file mode 100644 index 0000000000..2bca42b0de --- /dev/null +++ b/components/spi_flash/test_apps/flash_mmap/sdkconfig.ci.xip_psram_with_rom_impl @@ -0,0 +1,4 @@ +CONFIG_IDF_TARGET="esp32s3" +CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y +CONFIG_SPIRAM_RODATA=y +CONFIG_SPI_FLASH_ROM_IMPL=y From 5414eda027e7b20ab7b89cf745d735b3f3697659 Mon Sep 17 00:00:00 2001 From: Jiang Guang Ming Date: Fri, 3 Mar 2023 02:21:31 -0800 Subject: [PATCH 2/5] flash mmap: disable `mmap into instruction address` when SPI_FLASH_ROM_IMPL enabled --- components/esp_system/port/cpu_start.c | 20 +++++++++++-------- .../flash_mmap/main/test_flash_mmap.c | 2 ++ 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index c2aba37a42..b3917d0411 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -112,6 +112,11 @@ extern int _bss_end; extern int _rtc_bss_start; extern int _rtc_bss_end; +extern int _instruction_reserved_start; +extern int _instruction_reserved_end; +extern int _rodata_reserved_start; +extern int _rodata_reserved_end; + extern int _vector_table; static const char *TAG = "cpu_start"; @@ -359,17 +364,16 @@ void IRAM_ATTR call_start_cpu0(void) } #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 - /* Configure the Cache MMU size for instruction and rodata in flash. */ - extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); - extern int _rodata_reserved_start; - uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(SPI_FLASH_MMU_PAGE_SIZE - 1); - uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); + uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start; + uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start; + uint32_t cache_mmu_irom_size = ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); #if CONFIG_IDF_TARGET_ESP32S3 - extern int _rodata_reserved_end; - uint32_t cache_mmu_drom_size = (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); -#endif + uint32_t cache_mmu_drom_size = ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); +#endif // CONFIG_IDF_TARGET_ESP32S3 + /* Configure the Cache MMU size for instruction and rodata in flash. */ + extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); #endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 diff --git a/components/spi_flash/test_apps/flash_mmap/main/test_flash_mmap.c b/components/spi_flash/test_apps/flash_mmap/main/test_flash_mmap.c index 3849a61d33..836aa6c674 100644 --- a/components/spi_flash/test_apps/flash_mmap/main/test_flash_mmap.c +++ b/components/spi_flash/test_apps/flash_mmap/main/test_flash_mmap.c @@ -159,6 +159,7 @@ TEST_CASE("Can mmap into data address space", "[spi_flash][mmap]") TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA)); } +#if !CONFIG_SPI_FLASH_ROM_IMPL //flash mmap API in ROM does not support mmap into instruction address TEST_CASE("Can mmap into instruction address space", "[spi_flash][mmap]") { setup_mmap_tests(); @@ -205,6 +206,7 @@ TEST_CASE("Can mmap into instruction address space", "[spi_flash][mmap]") printf("Unmapping handle3\n"); spi_flash_munmap(handle3); } +#endif // !CONFIG_SPI_FLASH_ROM_IMPL TEST_CASE("Can mmap unordered pages into contiguous memory", "[spi_flash][mmap]") { From 344d30c18e9e3ec0639781c8d0ff698c94e4c1f7 Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Mon, 6 Mar 2023 16:49:10 +0800 Subject: [PATCH 3/5] esp_rom: add macro ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE for S3/C3/C2/C6/H2/H4 --- components/esp_rom/esp32c2/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32c2/esp_rom_caps.h | 1 + components/esp_rom/esp32c3/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32c3/esp_rom_caps.h | 1 + components/esp_rom/esp32c6/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32c6/esp_rom_caps.h | 1 + components/esp_rom/esp32h2/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32h2/esp_rom_caps.h | 1 + components/esp_rom/esp32h4/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32h4/esp_rom_caps.h | 1 + components/esp_rom/esp32s3/Kconfig.soc_caps.in | 4 ++++ components/esp_rom/esp32s3/esp_rom_caps.h | 1 + 12 files changed, 30 insertions(+) diff --git a/components/esp_rom/esp32c2/Kconfig.soc_caps.in b/components/esp_rom/esp32c2/Kconfig.soc_caps.in index 1160680f5e..49ad3e6c89 100644 --- a/components/esp_rom/esp32c2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c2/Kconfig.soc_caps.in @@ -54,3 +54,7 @@ config ESP_ROM_HAS_SPI_FLASH config ESP_ROM_HAS_NEWLIB_NANO_FORMAT bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32c2/esp_rom_caps.h b/components/esp_rom/esp32c2/esp_rom_caps.h index 302f85b320..0f1b77fcd0 100644 --- a/components/esp_rom/esp32c2/esp_rom_caps.h +++ b/components/esp_rom/esp32c2/esp_rom_caps.h @@ -19,3 +19,4 @@ #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/esp32c3/Kconfig.soc_caps.in b/components/esp_rom/esp32c3/Kconfig.soc_caps.in index 1c3af487c5..66727ba21e 100644 --- a/components/esp_rom/esp32c3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c3/Kconfig.soc_caps.in @@ -58,3 +58,7 @@ config ESP_ROM_HAS_ETS_PRINTF_BUG config ESP_ROM_HAS_NEWLIB_NANO_FORMAT bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h index ab81bb0fd0..06f2765cea 100644 --- a/components/esp_rom/esp32c3/esp_rom_caps.h +++ b/components/esp_rom/esp32c3/esp_rom_caps.h @@ -20,3 +20,4 @@ #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver #define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/esp32c6/Kconfig.soc_caps.in b/components/esp_rom/esp32c6/Kconfig.soc_caps.in index 9fa93d6570..565d50aacf 100644 --- a/components/esp_rom/esp32c6/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c6/Kconfig.soc_caps.in @@ -70,3 +70,7 @@ config ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE config ESP_ROM_WDT_INIT_PATCH bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32c6/esp_rom_caps.h b/components/esp_rom/esp32c6/esp_rom_caps.h index 1439185aba..46cebc153b 100644 --- a/components/esp_rom/esp32c6/esp_rom_caps.h +++ b/components/esp_rom/esp32c6/esp_rom_caps.h @@ -23,3 +23,4 @@ #define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions) #define ESP_ROM_REV0_HAS_NO_ECDSA_INTERFACE (1) // ECO 0 does not have ets_ecdsa_verify symbol, future revision will have it #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/esp32h2/Kconfig.soc_caps.in b/components/esp_rom/esp32h2/Kconfig.soc_caps.in index 78e4def69c..0e0ffe6666 100644 --- a/components/esp_rom/esp32h2/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h2/Kconfig.soc_caps.in @@ -58,3 +58,7 @@ config ESP_ROM_HAS_NEWLIB_NANO_FORMAT config ESP_ROM_WDT_INIT_PATCH bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h index 76f940a93f..ab907de2a3 100644 --- a/components/esp_rom/esp32h2/esp_rom_caps.h +++ b/components/esp_rom/esp32h2/esp_rom_caps.h @@ -20,3 +20,4 @@ #define ESP_ROM_WITHOUT_REGI2C (1) // ROM has no regi2c APIs #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano versions of formatting functions #define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/esp32h4/Kconfig.soc_caps.in b/components/esp_rom/esp32h4/Kconfig.soc_caps.in index 4fe0f15e6d..819d7f3757 100644 --- a/components/esp_rom/esp32h4/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32h4/Kconfig.soc_caps.in @@ -50,3 +50,7 @@ config ESP_ROM_HAS_ETS_PRINTF_BUG config ESP_ROM_HAS_NEWLIB_NANO_FORMAT bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32h4/esp_rom_caps.h b/components/esp_rom/esp32h4/esp_rom_caps.h index 32f210e3e4..52bb54d36b 100644 --- a/components/esp_rom/esp32h4/esp_rom_caps.h +++ b/components/esp_rom/esp32h4/esp_rom_caps.h @@ -18,3 +18,4 @@ #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap diff --git a/components/esp_rom/esp32s3/Kconfig.soc_caps.in b/components/esp_rom/esp32s3/Kconfig.soc_caps.in index 14684fe262..f64587e996 100644 --- a/components/esp_rom/esp32s3/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32s3/Kconfig.soc_caps.in @@ -62,3 +62,7 @@ config ESP_ROM_HAS_ETS_PRINTF_BUG config ESP_ROM_HAS_NEWLIB_NANO_FORMAT bool default y + +config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + bool + default y diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h index c716de7613..a7c0460da9 100644 --- a/components/esp_rom/esp32s3/esp_rom_caps.h +++ b/components/esp_rom/esp32s3/esp_rom_caps.h @@ -21,3 +21,4 @@ #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver #define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT (1) // ROM has the newlib nano version of formatting functions +#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap From 91b86f55d53fb11e0250e8e826384de411b123aa Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Mon, 6 Mar 2023 17:20:56 +0800 Subject: [PATCH 4/5] esp_system: use ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE instead of IDF_TARGET_XXX --- components/esp_system/port/cpu_start.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index b3917d0411..a015a2f305 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -363,19 +363,19 @@ void IRAM_ATTR call_start_cpu0(void) esp_restart(); } -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 +#if CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start; - uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start; uint32_t cache_mmu_irom_size = ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); #if CONFIG_IDF_TARGET_ESP32S3 + uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start; uint32_t cache_mmu_drom_size = ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); #endif // CONFIG_IDF_TARGET_ESP32S3 /* Configure the Cache MMU size for instruction and rodata in flash. */ extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); -#endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 +#endif // CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE && CONFIG_SPI_FLASH_ROM_IMPL #if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT bool efuse_opflash_en = efuse_ll_get_flash_type(); @@ -477,7 +477,7 @@ void IRAM_ATTR call_start_cpu0(void) (uint32_t)&_rodata_reserved_end, \ s_instr_flash2spiram_off, \ s_rodata_flash2spiram_off); -#endif +#endif // CONFIG_IDF_TARGET_ESP32S3 #if CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S2_DATA_CACHE_WRAP || \ CONFIG_ESP32S3_INSTRUCTION_CACHE_WRAP || CONFIG_ESP32S3_DATA_CACHE_WRAP From 87f2eb9e2a0195a1c261631f163f3834ad54e589 Mon Sep 17 00:00:00 2001 From: jiangguangming Date: Mon, 6 Mar 2023 17:55:16 +0800 Subject: [PATCH 5/5] esp_rom: put rom cache related functions to cache.h --- .../esp_rom/esp32h2/ld/esp32h2.rom.api.ld | 1 - .../esp32h4/ld/rev1/esp32h4.rom.api.ld | 1 - .../esp32h4/ld/rev2/esp32h4.rom.api.ld | 1 - .../esp_rom/include/esp32c2/rom/cache.h | 8 ++++ .../esp_rom/include/esp32c3/rom/cache.h | 8 ++++ .../esp_rom/include/esp32c6/rom/cache.h | 8 ++++ .../esp_rom/include/esp32h2/rom/cache.h | 8 ++++ .../esp_rom/include/esp32h4/rom/cache.h | 8 ++++ .../esp_rom/include/esp32s3/rom/cache.h | 38 ++++++++++++------- components/esp_system/port/cpu_start.c | 12 ++---- tools/ci/check_copyright_ignore.txt | 1 - 11 files changed, 68 insertions(+), 26 deletions(-) diff --git a/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld index 325d969404..e6b948b6a3 100644 --- a/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/esp32h2.rom.api.ld @@ -31,7 +31,6 @@ PROVIDE ( esp_rom_uart_rx_string = UartRxString ); PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); - PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); diff --git a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld index a108eb5b36..8a1eb5afe0 100644 --- a/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld +++ b/components/esp_rom/esp32h4/ld/rev1/esp32h4.rom.api.ld @@ -33,7 +33,6 @@ PROVIDE ( esp_rom_uart_rx_string = UartRxString ); PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); - PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); diff --git a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld index a12e1c2c5a..7c821b46b1 100644 --- a/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld +++ b/components/esp_rom/esp32h4/ld/rev2/esp32h4.rom.api.ld @@ -33,7 +33,6 @@ PROVIDE ( esp_rom_uart_rx_string = UartRxString ); PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch ); PROVIDE ( esp_rom_uart_putc = ets_write_char_uart ); - PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); diff --git a/components/esp_rom/include/esp32c2/rom/cache.h b/components/esp_rom/include/esp32c2/rom/cache.h index 30664e5809..ccde7d8a07 100644 --- a/components/esp_rom/include/esp32c2/rom/cache.h +++ b/components/esp_rom/include/esp32c2/rom/cache.h @@ -503,6 +503,14 @@ uint32_t Cache_Get_IROM_MMU_End(void); */ uint32_t Cache_Get_DROM_MMU_End(void); +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + #ifdef __cplusplus } #endif diff --git a/components/esp_rom/include/esp32c3/rom/cache.h b/components/esp_rom/include/esp32c3/rom/cache.h index a35d992c63..8e4bbb9acd 100644 --- a/components/esp_rom/include/esp32c3/rom/cache.h +++ b/components/esp_rom/include/esp32c3/rom/cache.h @@ -663,6 +663,14 @@ uint32_t Cache_Get_IROM_MMU_End(void); */ uint32_t Cache_Get_DROM_MMU_End(void); +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + /** * @brief Lock the permission control section configuration. After lock, any * configuration modification will be bypass. Digital reset will clear the lock! diff --git a/components/esp_rom/include/esp32c6/rom/cache.h b/components/esp_rom/include/esp32c6/rom/cache.h index 03e32c2ece..53c228ef47 100644 --- a/components/esp_rom/include/esp32c6/rom/cache.h +++ b/components/esp_rom/include/esp32c6/rom/cache.h @@ -584,6 +584,14 @@ uint32_t Cache_Get_IROM_MMU_End(void); */ uint32_t Cache_Get_DROM_MMU_End(void); +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed) diff --git a/components/esp_rom/include/esp32h2/rom/cache.h b/components/esp_rom/include/esp32h2/rom/cache.h index 1b5589b301..e253e91d32 100644 --- a/components/esp_rom/include/esp32h2/rom/cache.h +++ b/components/esp_rom/include/esp32h2/rom/cache.h @@ -587,6 +587,14 @@ uint32_t Cache_Get_IROM_MMU_End(void); */ uint32_t Cache_Get_DROM_MMU_End(void); +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed) diff --git a/components/esp_rom/include/esp32h4/rom/cache.h b/components/esp_rom/include/esp32h4/rom/cache.h index b9504ab942..7295ed82f6 100644 --- a/components/esp_rom/include/esp32h4/rom/cache.h +++ b/components/esp_rom/include/esp32h4/rom/cache.h @@ -663,6 +663,14 @@ uint32_t Cache_Get_IROM_MMU_End(void); */ uint32_t Cache_Get_DROM_MMU_End(void); +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + /** * @brief Lock the permission control section configuration. After lock, any * configuration modification will be bypass. Digital reset will clear the lock! diff --git a/components/esp_rom/include/esp32s3/rom/cache.h b/components/esp_rom/include/esp32s3/rom/cache.h index 27780446fe..8cf46815d3 100644 --- a/components/esp_rom/include/esp32s3/rom/cache.h +++ b/components/esp_rom/include/esp32s3/rom/cache.h @@ -1,16 +1,8 @@ -// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -1162,6 +1154,26 @@ uint32_t Cache_Get_IROM_MMU_End(void); */ uint32_t Cache_Get_DROM_MMU_End(void); +/** + * @brief Configure cache MMU page size according to instruction and rodata size + * + * @param irom_size The instruction cache MMU page size + * @param drom_size The rodata data cache MMU page size + */ +void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); + +/** + * @brief Configure cache MMU page information + * + * @param instr_page_num The instruction cache MMU page num + * @param rodata_page_num The rodata cache MMU page num + * @param rodata_start The rodata start cache address + * @param rodata_end The rodata end cache address + * @param i_off The offset of instruction when instruction copied from flash to xip_psram + * @param ro_off The offset of rodata when rodata copied from flash to xip_psram + */ +void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, uint32_t rodata_start, uint32_t rodata_end, int i_off, int ro_off); + /** * @brief Used by SPI flash mmap * diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index a015a2f305..af4a9ce0db 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -71,6 +71,7 @@ #include "esp_private/esp_mmu_map_private.h" #if CONFIG_SPIRAM #include "esp_psram.h" +#include "esp_private/mmu_psram_flash.h" #include "esp_private/esp_psram_extram.h" #endif @@ -367,15 +368,12 @@ void IRAM_ATTR call_start_cpu0(void) uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end - (uint32_t)&_instruction_reserved_start; uint32_t cache_mmu_irom_size = ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); -#if CONFIG_IDF_TARGET_ESP32S3 uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - (uint32_t)&_rodata_reserved_start; - uint32_t cache_mmu_drom_size = ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); -#endif // CONFIG_IDF_TARGET_ESP32S3 + __attribute__((unused)) uint32_t cache_mmu_drom_size = ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); /* Configure the Cache MMU size for instruction and rodata in flash. */ - extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); -#endif // CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE && CONFIG_SPI_FLASH_ROM_IMPL +#endif // CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE #if CONFIG_ESPTOOLPY_OCT_FLASH && !CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT bool efuse_opflash_en = efuse_ll_get_flash_type(); @@ -462,15 +460,11 @@ void IRAM_ATTR call_start_cpu0(void) int s_instr_flash2spiram_off = 0; int s_rodata_flash2spiram_off = 0; #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS - extern int instruction_flash2spiram_offset(void); s_instr_flash2spiram_off = instruction_flash2spiram_offset(); #endif #if CONFIG_SPIRAM_RODATA - extern int rodata_flash2spiram_offset(void); s_rodata_flash2spiram_off = rodata_flash2spiram_offset(); #endif - - extern void Cache_Set_IDROM_MMU_Info(uint32_t instr_page_num, uint32_t rodata_page_num, uint32_t rodata_start, uint32_t rodata_end, int i_off, int ro_off); Cache_Set_IDROM_MMU_Info(cache_mmu_irom_size / sizeof(uint32_t), \ cache_mmu_drom_size / sizeof(uint32_t), \ (uint32_t)&_rodata_reserved_start, \ diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 0a8421c2e7..39d178fc0d 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -515,7 +515,6 @@ components/esp_rom/include/esp32s2/rom/usb/usb_dfu.h components/esp_rom/include/esp32s2/rom/usb/usb_os_glue.h components/esp_rom/include/esp32s2/rom/usb/usb_persist.h components/esp_rom/include/esp32s3/rom/bigint.h -components/esp_rom/include/esp32s3/rom/cache.h components/esp_rom/include/esp32s3/rom/crc.h components/esp_rom/include/esp32s3/rom/digital_signature.h components/esp_rom/include/esp32s3/rom/hmac.h