Merge branch 'feature/h4_spi_support' into 'master'

feat(driver_spi): support esp32h4 spi driver Closes IDF-12362, IDF-12364, IDF-12366, and IDF-11521 See merge request espressif/esp-idf!40862
2025-10-02 18:10:57 +02:00 · 2025-08-06 16:26:34 +08:00
parent d622116355 37c6608ab3
commit fe3c676d13
54 changed files with 1716 additions and 231 deletions
--- a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h
+++ b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -74,7 +74,7 @@
 #define ESP_SPI_SLAVE_TV        (12.5*3.5)
 #define WIRE_DELAY              12.5

-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32H4
 #define SLAVE_IOMUX_PIN_MISO    -1
 #define SLAVE_IOMUX_PIN_MOSI    -1
 #define SLAVE_IOMUX_PIN_SCLK    -1
@@ -82,7 +82,11 @@
 #define SLAVE_IOMUX_PIN_WP      -1
 #define SLAVE_IOMUX_PIN_HD      -1

+#if CONFIG_IDF_TARGET_ESP32H4
+#define UNCONNECTED_PIN         27
+#else
 #define UNCONNECTED_PIN         41
+#endif
 #define INPUT_ONLY_PIN          46
 #define GPIO_DELAY              0
 #define ESP_SPI_SLAVE_TV        0
@@ -113,22 +117,6 @@
 #define MAX_TEST_SIZE           16  ///< in this test we run several transactions, this is the maximum trans that can be run
 #define PSET_NAME_LEN           30  ///< length of each param set name

-//test low frequency, high frequency until freq limit for worst case (both GPIO)
-#define TEST_FREQ_DEFAULT(){    \
-         1 * 1000 * 1000,       \
-         8 * 1000 * 1000,       \
-         9 * 1000 * 1000,       \
-        10 * 1000 * 1000,       \
-        11 * 1000 * 1000,       \
-        13 * 1000 * 1000,       \
-        16 * 1000 * 1000,       \
-        20 * 1000 * 1000,       \
-        26 * 1000 * 1000,       \
-        40 * 1000 * 1000,       \
-        80 * 1000 * 1000,       \
-        0,\
-    }
-
 //default bus config for tests
 #define SPI_BUS_TEST_DEFAULT_CONFIG() {\
        .miso_io_num=PIN_NUM_MISO, \
@@ -234,9 +222,6 @@ typedef struct {
    slave_txdata_t slave_trans[MAX_TEST_SIZE];
 } spitest_context_t;

-// fill default value of spitest_param_set_t
-void spitest_def_param(void* arg);
-
 // functions for slave task
 esp_err_t init_slave_context(spi_slave_task_context_t *context, spi_host_device_t host);
 void deinit_slave_context(spi_slave_task_context_t *context);
--- a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c
+++ b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -12,8 +12,6 @@
 #include "hal/spi_ll.h"
 #include "esp_rom_gpio.h"

-int test_freq_default[] = TEST_FREQ_DEFAULT();
-
 const char MASTER_TAG[] = "test_master";
 const char SLAVE_TAG[] = "test_slave";

@@ -34,15 +32,6 @@ DRAM_ATTR uint8_t spitest_slave_send[] = {
    0xda,
 };

-void spitest_def_param(void* arg)
-{
-    spitest_param_set_t *param_set = (spitest_param_set_t*)arg;
-    param_set->test_size = 8;
-    if (param_set->freq_list == NULL) {
-        param_set->freq_list = test_freq_default;
-    }
-}
-
 /**********************************************************************************
 * functions for slave task
 *********************************************************************************/
--- a/components/esp_driver_sdspi/test_apps/sdspi/README.md
+++ b/components/esp_driver_sdspi/test_apps/sdspi/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/include/esp_private/spi_common_internal.h
+++ b/components/esp_driver_spi/include/esp_private/spi_common_internal.h
@@ -80,6 +80,23 @@ typedef struct {
 /// Destructor called when a bus is deinitialized.
 typedef esp_err_t (*spi_destroy_func_t)(void*);

+/**
+ * @brief Allocate a SPI bus
+ *
+ * @param host_id SPI host ID
+ * @param name Name of the bus
+ * @return ESP_OK on success, ESP_ERR_NO_MEM if no memory is available
+ */
+esp_err_t spicommon_bus_alloc(spi_host_device_t host_id, const char *name);
+
+/**
+ * @brief Free a SPI bus
+ *
+ * @param host_id SPI host ID
+ * @return ESP_OK on success, ESP_ERR_INVALID_STATE if the bus is not allocated
+ */
+esp_err_t spicommon_bus_free(spi_host_device_t host_id);
+
 /**
 * @brief Alloc DMA channel for SPI
 *
--- a/components/esp_driver_spi/src/gpspi/spi_common.c
+++ b/components/esp_driver_spi/src/gpspi/spi_common.c
@@ -29,6 +29,12 @@
 #include "soc/dport_reg.h"
 #endif

+#if SOC_PERIPH_CLK_CTRL_SHARED
+#define SPI_COMMON_PERI_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define SPI_COMMON_PERI_CLOCK_ATOMIC()
+#endif
+
 #if CONFIG_SPI_MASTER_ISR_IN_IRAM || CONFIG_SPI_SLAVE_ISR_IN_IRAM
 #define SPI_COMMON_ISR_ATTR IRAM_ATTR
 #else
@@ -87,6 +93,9 @@ esp_err_t spicommon_bus_alloc(spi_host_device_t host_id, const char *name)
        spicommon_periph_free(host_id);
        return ESP_ERR_NO_MEM;
    }
+    SPI_COMMON_PERI_CLOCK_ATOMIC() {
+        spi_ll_enable_clock(host_id, true);
+    }
    ctx->host_id = host_id;
    bus_ctx[host_id] = ctx;
    return ESP_OK;
@@ -96,6 +105,9 @@ esp_err_t spicommon_bus_free(spi_host_device_t host_id)
 {
    assert(bus_ctx[host_id]);
    spicommon_periph_free(host_id);
+    SPI_COMMON_PERI_CLOCK_ATOMIC() {
+        spi_ll_enable_clock(host_id, false);
+    }
    free(bus_ctx[host_id]);
    bus_ctx[host_id] = NULL;
    return ESP_OK;
--- a/components/esp_driver_spi/src/gpspi/spi_master.c
+++ b/components/esp_driver_spi/src/gpspi/spi_master.c
@@ -318,9 +318,6 @@ static esp_err_t spi_master_init_driver(spi_host_device_t host_id)
        }
    }

-    SPI_MASTER_PERI_CLOCK_ATOMIC() {
-        spi_ll_enable_clock(host_id, true);
-    }
    spi_hal_init(&host->hal, host_id);
    spi_hal_config_io_default_level(&host->hal, bus_attr->bus_cfg.data_io_default_level);

@@ -406,7 +403,7 @@ static uint32_t s_spi_find_clock_src_pre_div(uint32_t src_freq, uint32_t target_

    uint32_t total_div = src_freq / target_freq;
    // Loop the `div` to find a divisible value of `total_div`
-    for (uint32_t pre_div = min_div; pre_div <= total_div; pre_div += 2) {
+    for (uint32_t pre_div = min_div; pre_div <= MIN(total_div, SPI_LL_SRC_PRE_DIV_MAX); pre_div += 2) {
        if ((total_div % pre_div) || (total_div / pre_div) > SPI_LL_PERIPH_CLK_DIV_MAX) {
            continue;
        }
@@ -1529,8 +1526,8 @@ static SPI_MASTER_ISR_ATTR spi_dma_desc_t *s_sct_setup_desc_anywhere(spi_dma_des
 {
    while (len) {
        int dmachunklen = len;
-        if (dmachunklen > LLDESC_MAX_NUM_PER_DESC) {
-            dmachunklen = LLDESC_MAX_NUM_PER_DESC;
+        if (dmachunklen > DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED) {
+            dmachunklen = DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
        }
        if (is_rx) {
            //Receive needs DMA length rounded to next 32-bit boundary
@@ -1557,7 +1554,7 @@ static SPI_MASTER_ISR_ATTR spi_dma_desc_t *s_sct_setup_desc_anywhere(spi_dma_des

 static SPI_MASTER_ISR_ATTR int s_sct_desc_get_required_num(uint32_t bytes_len)
 {
-    return (bytes_len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
+    return (bytes_len + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
 }
 /*-------------------------
 *            TX
--- a/components/esp_driver_spi/src/gpspi/spi_slave.c
+++ b/components/esp_driver_spi/src/gpspi/spi_slave.c
@@ -167,7 +167,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
        SPI_CHECK(slave_config->post_trans_cb != NULL, "use feature flag 'SPI_SLAVE_NO_RETURN_RESULT' but no post_trans_cb function sets", ESP_ERR_INVALID_ARG);
    }

-    SPI_CHECK(spicommon_periph_claim(host, "spi slave"), "host already in use", ESP_ERR_INVALID_STATE);
+    SPI_CHECK(ESP_OK == spicommon_bus_alloc(host, "spi slave"), "host already in use", ESP_ERR_INVALID_STATE);
    // spi_slave_t contains atomic variable, memory must be allocated from internal memory
    spihost[host] = heap_caps_calloc(1, sizeof(spi_slave_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
    if (spihost[host] == NULL) {
@@ -355,7 +355,7 @@ esp_err_t spi_slave_free(spi_host_device_t host)
 #endif //CONFIG_PM_ENABLE
    free(spihost[host]);
    spihost[host] = NULL;
-    spicommon_periph_free(host);
+    spicommon_bus_free(host);
    return ESP_OK;
 }

--- a/components/esp_driver_spi/src/gpspi/spi_slave_hd.c
+++ b/components/esp_driver_spi/src/gpspi/spi_slave_hd.c
@@ -117,7 +117,7 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
    SPIHD_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG);
 #endif

-    SPIHD_CHECK(spicommon_periph_claim(host_id, "slave_hd"), "host already in use", ESP_ERR_INVALID_STATE);
+    SPIHD_CHECK(ESP_OK == spicommon_bus_alloc(host_id, "slave_hd"), "host already in use", ESP_ERR_INVALID_STATE);
    // spi_slave_hd_slot_t contains atomic variable, memory must be allocated from internal memory
    spi_slave_hd_slot_t *host = heap_caps_calloc(1, sizeof(spi_slave_hd_slot_t), MALLOC_CAP_INTERNAL);
    if (host == NULL) {
@@ -351,7 +351,7 @@ esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id)

    spicommon_bus_free_io_cfg(&host->bus_config, &host->gpio_reserve);
    spicommon_cs_free_io(host->cs_io_num, &host->gpio_reserve);
-    spicommon_periph_free(host_id);
+    spicommon_bus_free(host_id);
    free(host->dma_ctx->dmadesc_tx);
    free(host->dma_ctx->dmadesc_rx);
    free(host->hal.dmadesc_tx);
@@ -756,7 +756,7 @@ esp_err_t s_spi_slave_hd_append_txdma(spi_slave_hd_slot_t *host, uint8_t *data,
    spi_slave_hd_hal_context_t *hal = &host->hal;

    //Check if there are enough available DMA descriptors for software to use
-    int num_required = (len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
+    int num_required = (len + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
    int available_desc_num = hal->dma_desc_num - hal->tx_used_desc_cnt;
    if (num_required > available_desc_num) {
        return ESP_ERR_INVALID_STATE;
@@ -797,7 +797,7 @@ esp_err_t s_spi_slave_hd_append_rxdma(spi_slave_hd_slot_t *host, uint8_t *data,
    spi_slave_hd_hal_context_t *hal = &host->hal;

    //Check if there are enough available dma descriptors for software to use
-    int num_required = (len + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
+    int num_required = (len + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
    int available_desc_num = hal->dma_desc_num - hal->rx_used_desc_cnt;
    if (num_required > available_desc_num) {
        return ESP_ERR_INVALID_STATE;
--- a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
+++ b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
@@ -89,21 +89,17 @@
 #define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          14

 #elif CONFIG_IDF_TARGET_ESP32H21
-#if SOC_CLK_TREE_SUPPORTED
-//TODO: [ESP32H21] IDF-11521 update perform data according to `TEST_CASE("spi_speed", "[spi]")`
-//Also update this value in doc spi_master.rst:535
 #define IDF_TARGET_MAX_SPI_CLK_FREQ                 32*1000*1000
-#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          0   // need update to real_val + 3
-#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          0   // need update to real_val + 3
-#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          0   // need update to real_val + 3
-#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          0   // need update to real_val + 3
-#else
-// Remove after SOC_CLK_TREE_SUPPORTED
-#define IDF_TARGET_MAX_SPI_CLK_FREQ                 32*1000*1000
-#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          1000
-#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          1000
-#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          1000
-#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          1000
-#endif
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          60
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          32
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          55
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          26
+
+#elif CONFIG_IDF_TARGET_ESP32H4
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 24*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          70
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          35
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          60
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          25

 #endif
--- a/components/esp_driver_spi/test_apps/master/README.md
+++ b/components/esp_driver_spi/test_apps/master/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
+++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
@@ -82,12 +82,13 @@ static void check_spi_pre_n_for(int clk, int pre, int n)
 */
 #define TEST_CLK_TIMES     8
 uint32_t clk_param_80m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} };
-uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 8, 60}, {333333, 3, 48}, {800000, 1, 60}, {5000000, 1, 10}, {12000000, 1, 4}, {18000000, 1, 3}, {26000000, 1, 2} };
 uint32_t clk_param_160m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 16, 50}, {333333, 4, 60}, {800000, 2, 50}, {900000, 2, 44}, {8000000, 1, 10}, {20000000, 1, 4}, {26000000, 1, 3} };
 #if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV
 uint32_t clk_param_40m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 4, 50}, {333333, 1, 60}, {800000, 1, 25}, {2000000, 1, 10}, {5000000, 1,  4}, {12000000, 1, 2}, {18000000, 1, 1} };
+uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 4, 60}, {333333, 2, 36}, {800000, 1, 30}, {5000000, 1, 5}, {12000000, 1, 2}, {18000000, 1, 2}, {24000000, 1, 1} };
 #else
 uint32_t clk_param_40m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 8, 50}, {333333, 2, 60}, {800000, 1, 50}, {2000000, 1, 20}, {5000000, 1,  8}, {12000000, 1, 3}, {18000000, 1, 2} };
+uint32_t clk_param_48m[TEST_CLK_TIMES][3] = {{1, SOC_SPI_MAX_PRE_DIVIDER, 64}, {100000, 8, 60}, {333333, 3, 48}, {800000, 1, 60}, {5000000, 1, 10}, {12000000, 1, 4}, {18000000, 1, 3}, {26000000, 1, 2} };
 #endif

 TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")
@@ -173,7 +174,7 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
            int real_freq_khz;
            spi_device_get_actual_freq(handle, &real_freq_khz);
            // (byte_len * 8 / real_freq_hz) * 1000 000, (unit)us
-            int trans_cost_us_predict = (float)TEST_CLK_BYTE_LEN * 8 * 1000 / real_freq_khz + IDF_TARGET_MAX_TRANS_TIME_POLL_DMA;
+            int trans_cost_us_predict = (float)TEST_CLK_BYTE_LEN * 8 * 1000 / real_freq_khz;

            // transaction and measure time
            start = esp_timer_get_time();
@@ -355,8 +356,8 @@ TEST_CASE("SPI Master test", "[spi]")
    master_free_device_bus(handle);
    TEST_ASSERT(success);

-    printf("Testing bus at 20MHz\n");
-    handle = setup_spi_bus_loopback(20000000, true);
+    printf("Testing bus at %dMHz\n", IDF_TARGET_MAX_SPI_CLK_FREQ / 1000000);
+    handle = setup_spi_bus_loopback(IDF_TARGET_MAX_SPI_CLK_FREQ, true);
    success &= spi_test(handle, 128); //DMA, aligned
    success &= spi_test(handle, 4096 * 3); //DMA, multiple descs
    master_free_device_bus(handle);
@@ -1470,7 +1471,7 @@ TEST_CASE("spi_speed", "[spi]")
        ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
    }
 #ifndef CONFIG_SPIRAM
-    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_NO_POLLING", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
+    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_INTR_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
    TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_INTR_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif

@@ -1488,7 +1489,7 @@ TEST_CASE("spi_speed", "[spi]")
        ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
    }
 #ifndef CONFIG_SPIRAM
-    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLLING", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
+    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLL_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
    TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_POLL_DMA, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif

@@ -1508,7 +1509,7 @@ TEST_CASE("spi_speed", "[spi]")
        ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
    }
 #ifndef CONFIG_SPIRAM
-    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_NO_POLLING_NO_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
+    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_INTR_CPU", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
    TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_INTR_CPU, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif

@@ -1526,7 +1527,7 @@ TEST_CASE("spi_speed", "[spi]")
        ESP_LOGI(TAG, "%.2lf", GET_US_BY_CCOUNT(t_flight_sorted[i]));
    }
 #ifndef CONFIG_SPIRAM
-    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLLING_NO_DMA", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
+    printf("[Performance][%s]: %d us\n", "SPI_PER_TRANS_POLL_CPU", (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
    TEST_ASSERT_LESS_THAN_INT(IDF_TARGET_MAX_TRANS_TIME_POLL_CPU, (int)GET_US_BY_CCOUNT(t_flight_sorted[(TEST_TIMES + 1) / 2]));
 #endif

--- a/components/esp_driver_spi/test_apps/param/README.md
+++ b/components/esp_driver_spi/test_apps/param/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
+++ b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
@@ -19,6 +19,27 @@
 #include "driver/spi_slave_hd.h"
 #endif

+//test low frequency, high frequency until freq limit for worst case (both GPIO)
+static int test_freq_default[] = {
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 100,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 50,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 16,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 7,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 3,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 2,
+    IDF_TARGET_MAX_SPI_CLK_FREQ,
+    0,
+};
+
+static void spitest_def_param(void* arg)
+{
+    spitest_param_set_t *param_set = (spitest_param_set_t*)arg;
+    param_set->test_size = 8;
+    if (param_set->freq_list == NULL) {
+        param_set->freq_list = test_freq_default;
+    }
+}
+
 #if (TEST_SPI_PERIPH_NUM >= 2)
 //These will only be enabled on chips with 2 or more SPI peripherals

@@ -337,16 +358,6 @@ TEST_SPI_LOCAL(TIMING, timing_pgroup)

 /************ Mode Test ***********************************************/
 #define FREQ_LIMIT_MODE 16 * 1000 * 1000
-static int test_freq_mode_local[] = {
-    1 * 1000 * 1000,
-    9 * 1000 * 1000, //maximum freq MISO stable before next latch edge
-    13 * 1000 * 1000,
-    16 * 1000 * 1000,
-    20 * 1000 * 1000,
-    26 * 1000 * 1000,
-    40 * 1000 * 1000,
-    0,
-};

 //signals are not fed to peripherals through iomux if the functions are not selected to iomux
 #ifdef CONFIG_IDF_TARGET_ESP32
@@ -377,7 +388,7 @@ static int test_freq_mode_local[] = {
 static spitest_param_set_t mode_pgroup[] = {
    {
        .pset_name = "Mode 0",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .master_limit = 13 * 1000 * 1000,
        .dup = FULL_DUPLEX,
        .mode = 0,
@@ -387,7 +398,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "Mode 1",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .freq_limit = 26 * 1000 * 1000,
        .master_limit = 13 * 1000 * 1000,
        .dup = FULL_DUPLEX,
@@ -398,7 +409,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "Mode 2",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .master_limit = 13 * 1000 * 1000,
        .dup = FULL_DUPLEX,
        .mode = 2,
@@ -408,7 +419,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "Mode 3",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .freq_limit = 26 * 1000 * 1000,
        .master_limit = 13 * 1000 * 1000,
        .dup = FULL_DUPLEX,
@@ -419,7 +430,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "Mode 0, DMA",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .master_limit = 13 * 1000 * 1000,
        .dup = FULL_DUPLEX,
        .mode = 0,
@@ -431,7 +442,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "Mode 1, DMA",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .freq_limit = 26 * 1000 * 1000,
        .master_limit = 13 * 1000 * 1000,
        .dup = FULL_DUPLEX,
@@ -444,7 +455,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "Mode 2, DMA",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .master_limit = 13 * 1000 * 1000,
        .dup = FULL_DUPLEX,
        .mode = 2,
@@ -456,7 +467,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "Mode 3, DMA",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .freq_limit = 26 * 1000 * 1000,
        .master_limit = 13 * 1000 * 1000,
        .dup = FULL_DUPLEX,
@@ -470,7 +481,7 @@ static spitest_param_set_t mode_pgroup[] = {
    /////////////////////////// MISO ////////////////////////////////////
    {
        .pset_name = "MISO, Mode 0",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .dup = HALF_DUPLEX_MISO,
        .mode = 0,
        .master_iomux = false,
@@ -479,7 +490,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "MISO, Mode 1",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .dup = HALF_DUPLEX_MISO,
        .mode = 1,
        .master_iomux = false,
@@ -488,7 +499,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "MISO, Mode 2",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .dup = HALF_DUPLEX_MISO,
        .mode = 2,
        .master_iomux = false,
@@ -497,7 +508,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "MISO, Mode 3",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .dup = HALF_DUPLEX_MISO,
        .mode = 3,
        .master_iomux = false,
@@ -506,7 +517,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "MISO, Mode 0, DMA",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .dup = HALF_DUPLEX_MISO,
        .mode = 0,
        .slave_dma_chan = SPI_DMA_CH_AUTO,
@@ -517,7 +528,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "MISO, Mode 1, DMA",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .dup = HALF_DUPLEX_MISO,
        .mode = 1,
        .slave_dma_chan = SPI_DMA_CH_AUTO,
@@ -528,7 +539,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "MISO, Mode 2, DMA",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .dup = HALF_DUPLEX_MISO,
        .mode = 2,
        .slave_dma_chan = SPI_DMA_CH_AUTO,
@@ -539,7 +550,7 @@ static spitest_param_set_t mode_pgroup[] = {
    },
    {
        .pset_name = "MISO, Mode 3, DMA",
-        .freq_list = test_freq_mode_local,
+        .freq_list = test_freq_default,
        .dup = HALF_DUPLEX_MISO,
        .mode = 3,
        .slave_dma_chan = SPI_DMA_CH_AUTO,
@@ -1047,19 +1058,6 @@ TEST_SPI_MASTER_SLAVE(TIMING, timing_conf, "")
 //Set to this input delay so that the master will read with delay until 7M
 #define DELAY_HCLK_UNTIL_7M    12.5*3

-static int test_freq_mode_ms[] = {
-    100 * 1000,
-    6 * 1000 * 1000,
-    7 * 1000 * 1000,
-    8 * 1000 * 1000, //maximum freq MISO stable before next latch edge
-    9 * 1000 * 1000, //maximum freq MISO stable before next latch edge
-    10 * 1000 * 1000,
-    11 * 1000 * 1000,
-    13 * 1000 * 1000,
-    16 * 1000 * 1000,
-    20 * 1000 * 1000,
-    0,
-};
 static int test_freq_20M_only[] = {
    20 * 1000 * 1000,
    0,
@@ -1069,7 +1067,7 @@ spitest_param_set_t mode_conf[] = {
    //non-DMA tests
    {
        .pset_name = "mode 0, no DMA",
-        .freq_list = test_freq_mode_ms,
+        .freq_list = test_freq_default,
        .master_limit = FREQ_LIMIT_MODE,
        .dup = FULL_DUPLEX,
        .master_iomux = true,
@@ -1079,7 +1077,7 @@ spitest_param_set_t mode_conf[] = {
    },
    {
        .pset_name = "mode 1, no DMA",
-        .freq_list = test_freq_mode_ms,
+        .freq_list = test_freq_default,
        .master_limit = FREQ_LIMIT_MODE,
        .dup = FULL_DUPLEX,
        .master_iomux = true,
@@ -1089,7 +1087,7 @@ spitest_param_set_t mode_conf[] = {
    },
    {
        .pset_name = "mode 2, no DMA",
-        .freq_list = test_freq_mode_ms,
+        .freq_list = test_freq_default,
        .master_limit = FREQ_LIMIT_MODE,
        .dup = FULL_DUPLEX,
        .master_iomux = true,
@@ -1099,7 +1097,7 @@ spitest_param_set_t mode_conf[] = {
    },
    {
        .pset_name = "mode 3, no DMA",
-        .freq_list = test_freq_mode_ms,
+        .freq_list = test_freq_default,
        .master_limit = FREQ_LIMIT_MODE,
        .dup = FULL_DUPLEX,
        .master_iomux = true,
@@ -1147,7 +1145,7 @@ spitest_param_set_t mode_conf[] = {
    //DMA tests
    {
        .pset_name = "mode 0, DMA",
-        .freq_list = test_freq_mode_ms,
+        .freq_list = test_freq_default,
        .master_limit = FREQ_LIMIT_MODE,
        .dup = FULL_DUPLEX,
        .master_iomux = true,
@@ -1160,7 +1158,7 @@ spitest_param_set_t mode_conf[] = {
    },
    {
        .pset_name = "mode 1, DMA",
-        .freq_list = test_freq_mode_ms,
+        .freq_list = test_freq_default,
        .master_limit = FREQ_LIMIT_MODE,
        .dup = FULL_DUPLEX,
        .master_iomux = true,
@@ -1173,7 +1171,7 @@ spitest_param_set_t mode_conf[] = {
    },
    {
        .pset_name = "mode 2, DMA",
-        .freq_list = test_freq_mode_ms,
+        .freq_list = test_freq_default,
        .master_limit = FREQ_LIMIT_MODE,
        .dup = FULL_DUPLEX,
        .master_iomux = true,
@@ -1186,7 +1184,7 @@ spitest_param_set_t mode_conf[] = {
    },
    {
        .pset_name = "mode 3, DMA",
-        .freq_list = test_freq_mode_ms,
+        .freq_list = test_freq_default,
        .master_limit = FREQ_LIMIT_MODE,
        .dup = FULL_DUPLEX,
        .master_iomux = true,
--- a/components/esp_driver_spi/test_apps/slave/README.md
+++ b/components/esp_driver_spi/test_apps/slave/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c
+++ b/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c
@@ -231,7 +231,7 @@ TEST_CASE("test fullduplex slave with only TX direction", "[spi]")
            t.tx_buffer = NULL;
            t.rx_buffer = master_rxbuf;
        }
-        spi_device_transmit(spi, (spi_transaction_t *)&t);
+        spi_device_transmit(spi, &t);

        //wait for end
        TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &out, portMAX_DELAY));
--- a/components/esp_driver_spi/test_apps/slave_hd/README.md
+++ b/components/esp_driver_spi/test_apps/slave_hd/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
--- a/components/esp_driver_spi/test_apps/slave_hd/main/idf_component.yml
+++ b/components/esp_driver_spi/test_apps/slave_hd/main/idf_component.yml
@@ -1,6 +1,8 @@
 dependencies:
+  espressif/esp_serial_slave_link: "^1.1.0"
  test_utils:
    path: ${IDF_PATH}/tools/test_apps/components/test_utils
  test_driver_utils:
    path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils
-  espressif/esp_serial_slave_link: "^1.1.0"
+  spi_bench_mark:
+    path: ${IDF_PATH}/components/esp_driver_spi/test_apps/components/spi_bench_mark
--- a/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c
+++ b/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c
@@ -19,6 +19,7 @@
 #include "esp_private/sleep_cpu.h"
 #include "esp_private/esp_sleep_internal.h"
 #include "esp_private/esp_pmu.h"
+#include "spi_performance.h"
 #include "esp_rom_gpio.h"

 #define TEST_BUFFER_SIZE    256     ///< buffer size of each wrdma buffer in fifo mode
@@ -433,6 +434,27 @@ static void test_hd_loop(const void* arg1, void* arg2)
    }
 }

+//test low frequency, high frequency until freq limit for worst case (both GPIO)
+static int test_freq_default[] = {
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 100,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 50,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 10,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 7,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 4,
+    IDF_TARGET_MAX_SPI_CLK_FREQ / 2,
+    IDF_TARGET_MAX_SPI_CLK_FREQ,
+    0,
+};
+
+static void spitest_def_param(void* arg)
+{
+    spitest_param_set_t *param_set = (spitest_param_set_t*)arg;
+    param_set->test_size = 8;
+    if (param_set->freq_list == NULL) {
+        param_set->freq_list = test_freq_default;
+    }
+}
+
 static const ptest_func_t hd_test_func = {
    .pre_test = test_hd_init,
    .post_test = test_hd_deinit,
@@ -446,9 +468,8 @@ static const ptest_func_t hd_test_func = {

 static int test_freq_hd[] = {
    500 * 1000,
-    10 * 1000 * 1000, //maximum freq MISO stable before next latch edge
-    20 * 1000 * 1000, //maximum freq MISO stable before next latch edge
-    // 40 * 1000 * 1000, //maximum freq MISO stable before next latch edge
+    10 * 1000 * 1000,               //maximum freq MISO stable before next latch edge
+    IDF_TARGET_MAX_SPI_CLK_FREQ,    //maximum freq MISO stable before next latch edge
    0,
 };

--- a/components/esp_lcd/test_apps/spi_lcd/README.md
+++ b/components/esp_lcd/test_apps/spi_lcd/README.md
@@ -1,4 +1,4 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 This test app is used to test LCDs with SPI interface.
--- a/components/hal/esp32c2/include/hal/spi_ll.h
+++ b/components/hal/esp32c2/include/hal/spi_ll.h
@@ -21,7 +21,6 @@
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
 #include "soc/system_struct.h"
-#include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/spi_types.h"
--- a/components/hal/esp32c3/include/hal/spi_ll.h
+++ b/components/hal/esp32c3/include/hal/spi_ll.h
@@ -21,7 +21,6 @@
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
 #include "soc/system_struct.h"
-#include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/spi_types.h"
--- a/components/hal/esp32c5/include/hal/spi_ll.h
+++ b/components/hal/esp32c5/include/hal/spi_ll.h
@@ -17,12 +17,12 @@
 #include "esp_types.h"
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
-#include "soc/lldesc.h"
 #include "soc/clk_tree_defs.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/spi_types.h"
 #include "soc/pcr_struct.h"
+#include "soc/pcr_reg.h"

 #ifdef __cplusplus
 extern "C" {
@@ -41,6 +41,7 @@ extern "C" {
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
 #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV      1  //clock source have divider before peripheral
+#define SPI_LL_SRC_PRE_DIV_MAX    (PCR_SPI2_CLKM_DIV_NUM + 1)   //source pre divider max
 #define SPI_LL_PERIPH_CLK_DIV_MAX   ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider

 /**
--- a/components/hal/esp32c6/include/hal/spi_ll.h
+++ b/components/hal/esp32c6/include/hal/spi_ll.h
@@ -20,7 +20,6 @@
 #include "esp_types.h"
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
-#include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/spi_types.h"
@@ -183,8 +182,6 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
    hw->slave.val = 0;
    hw->user.val = 0;

-    PCR.spi2_clkm_conf.spi2_clkm_sel = 1;
-
    hw->dma_conf.val = 0;
    hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
    hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
--- a/components/hal/esp32c61/include/hal/spi_ll.h
+++ b/components/hal/esp32c61/include/hal/spi_ll.h
@@ -18,11 +18,11 @@
 #include "esp_types.h"
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
-#include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/spi_types.h"
 #include "soc/pcr_struct.h"
+#include "soc/pcr_reg.h"

 #ifdef __cplusplus
 extern "C" {
@@ -41,6 +41,7 @@ extern "C" {
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized
 #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV      1  //clock source have divider before peripheral
+#define SPI_LL_SRC_PRE_DIV_MAX    (PCR_SPI2_CLKM_DIV_NUM + 1)   //source pre divider max
 #define SPI_LL_PERIPH_CLK_DIV_MAX   ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider

 /**
@@ -205,8 +206,6 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
    hw->slave.val = 0;
    hw->user.val = 0;

-    PCR.spi2_clkm_conf.spi2_clkm_sel = 1;
-
    hw->dma_conf.val = 0;
    hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
    hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
--- a/components/hal/esp32h2/include/hal/spi_ll.h
+++ b/components/hal/esp32h2/include/hal/spi_ll.h
@@ -22,7 +22,6 @@
 #include "soc/spi_struct.h"
 #include "soc/chip_revision.h"
 #include "soc/pcr_struct.h"
-#include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/efuse_hal.h"
@@ -184,8 +183,6 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
    hw->slave.val = 0;
    hw->user.val = 0;

-    PCR.spi2_clkm_conf.spi2_clkm_sel = 0;
-
    hw->dma_conf.val = 0;
    hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
    hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
--- a/components/hal/esp32h21/include/hal/spi_ll.h
+++ b/components/hal/esp32h21/include/hal/spi_ll.h
@@ -20,7 +20,6 @@
 #include "soc/spi_struct.h"
 #include "soc/chip_revision.h"
 #include "soc/pcr_struct.h"
-#include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/efuse_hal.h"
@@ -170,8 +169,6 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
    hw->slave.val = 0;
    hw->user.val = 0;

-    PCR.spi2_clkm_conf.spi2_clkm_sel = 0;
-
    hw->dma_conf.val = 0;
    hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
    hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
--- a/components/hal/esp32h4/include/hal/gpspi_flash_ll.h
+++ b/components/hal/esp32h4/include/hal/gpspi_flash_ll.h
@@ -386,6 +386,21 @@ static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
    abort();
 }

+/**
+ * Set D/Q output level during dummy phase
+ *
+ * @param dev Beginning address of the peripheral registers.
+ * @param out_en whether to enable IO output for dummy phase
+ * @param out_level dummy output level
+ */
+static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en, uint32_t out_lev)
+{
+    // dev->ctrl.dummy_out = out_en;
+    // dev->ctrl.q_pol = out_lev;
+    // dev->ctrl.d_pol = out_lev;
+    abort();
+}
+
 /**
 * Set extra hold time of CS after the clocks.
 *
--- a/components/hal/esp32h4/include/hal/spi_ll.h
+++ b/components/hal/esp32h4/include/hal/spi_ll.h
--- a/components/hal/esp32p4/include/hal/spi_ll.h
+++ b/components/hal/esp32p4/include/hal/spi_ll.h
@@ -19,11 +19,11 @@
 #include "esp_types.h"
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
-#include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/spi_types.h"
 #include "soc/hp_sys_clkrst_struct.h"
+#include "soc/hp_sys_clkrst_reg.h"

 #ifdef __cplusplus
 extern "C" {
@@ -41,6 +41,7 @@ extern "C" {
 #define SPI_LL_DMA_MAX_BIT_LEN    SPI_MS_DATA_BITLEN
 #define SPI_LL_CPU_MAX_BIT_LEN    (16 * 32)    //Fifo len: 16 words
 #define SPI_LL_SUPPORT_CLK_SRC_PRE_DIV      1  //clock source have divider before peripheral
+#define SPI_LL_SRC_PRE_DIV_MAX    (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM + 1)   //source pre divider max
 #define SPI_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
 #define SPI_LL_MOSI_FREE_LEVEL    1            //Default level after bus initialized

--- a/components/hal/esp32s3/include/hal/spi_ll.h
+++ b/components/hal/esp32s3/include/hal/spi_ll.h
@@ -21,7 +21,6 @@
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
 #include "soc/system_struct.h"
-#include "soc/lldesc.h"
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "hal/spi_types.h"
--- a/components/soc/esp32h21/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32h21/include/soc/clk_tree_defs.h
@@ -280,11 +280,7 @@ typedef enum {
 * @brief Type of SPI clock source.
 */
 typedef enum {
-#if SOC_CLK_TREE_SUPPORTED
    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,     /*!< Select PLL_48M as SPI source clock */
-#else
-    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as SPI source clock */
-#endif
    SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M,    /*!< Select PLL_48M as SPI source clock */
    SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,            /*!< Select XTAL as SPI source clock */
    SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,      /*!< Select RC_FAST as SPI source clock */
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -47,6 +47,10 @@ config SOC_RMT_SUPPORTED
    bool
    default y

+config SOC_GPSPI_SUPPORTED
+    bool
+    default y
+
 config SOC_I2C_SUPPORTED
    bool
    default y
@@ -551,6 +555,38 @@ config SOC_SPI_MAX_CS_NUM
    int
    default 6

+config SOC_SPI_MAXIMUM_BUFFER_SIZE
+    int
+    default 64
+
+config SOC_SPI_SUPPORT_DDRCLK
+    bool
+    default y
+
+config SOC_SPI_SLAVE_SUPPORT_SEG_TRANS
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CD_SIG
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_SLAVE_HD_VER2
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CLK_XTAL
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_CLK_RC_FAST
+    bool
+    default y
+
 config SOC_MEMSPI_IS_INDEPENDENT
    bool
    default y
--- a/components/soc/esp32h4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32h4/include/soc/clk_tree_defs.h
@@ -240,15 +240,15 @@ typedef enum {
 /**
 * @brief Array initializer for all supported clock sources of SPI
 */
-#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+#define SOC_SPI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F48M,SOC_MOD_CLK_RC_FAST}

 /**
 * @brief Type of SPI clock source.
 */
 typedef enum {
-    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,     /*!< Select PLL_48M as SPI source clock */
-    SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M,    /*!< Select PLL_48M as SPI source clock */
+    SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,     /*!< Select XTAL as SPI source clock */
    SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,            /*!< Select XTAL as SPI source clock */
+    SPI_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M,    /*!< Select PLL_48M as SPI source clock */
    SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,      /*!< Select RC_FAST as SPI source clock */
 } soc_periph_spi_clk_src_t;

--- a/components/soc/esp32h4/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32h4/include/soc/retention_periph_defs.h
@@ -46,14 +46,15 @@ typedef enum periph_retention_module {
    SLEEP_RETENTION_MODULE_TWAI0        = 22,
    SLEEP_RETENTION_MODULE_PARLIO0      = 23,
    SLEEP_RETENTION_MODULE_GPSPI2       = 24,
-    SLEEP_RETENTION_MODULE_LEDC         = 25,
-    SLEEP_RETENTION_MODULE_PCNT0        = 26,
-    SLEEP_RETENTION_MODULE_MCPWM0       = 27,
+    SLEEP_RETENTION_MODULE_GPSPI3       = 25,
+    SLEEP_RETENTION_MODULE_LEDC         = 26,
+    SLEEP_RETENTION_MODULE_PCNT0        = 27,
+    SLEEP_RETENTION_MODULE_MCPWM0       = 28,

    /* Modem module, which includes BLE and 802.15.4 */
-    SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
-    SLEEP_RETENTION_MODULE_BT_BB        = 29,
-    SLEEP_RETENTION_MODULE_802154_MAC   = 30,
+    SLEEP_RETENTION_MODULE_BLE_MAC      = 29,
+    SLEEP_RETENTION_MODULE_BT_BB        = 30,
+    SLEEP_RETENTION_MODULE_802154_MAC   = 31,

    SLEEP_RETENTION_MODULE_MAX          = SOC_PM_RETENTION_MODULE_NUM - 1
 } periph_retention_module_t;
@@ -83,6 +84,7 @@ typedef enum periph_retention_module {
    : ((m) == SLEEP_RETENTION_MODULE_TWAI0)        ? true \
    : ((m) == SLEEP_RETENTION_MODULE_PARLIO0)      ? true \
    : ((m) == SLEEP_RETENTION_MODULE_GPSPI2)       ? true \
+    : ((m) == SLEEP_RETENTION_MODULE_GPSPI3)       ? true \
    : ((m) == SLEEP_RETENTION_MODULE_LEDC)         ? true \
    : ((m) == SLEEP_RETENTION_MODULE_PCNT0)        ? true \
    : ((m) == SLEEP_RETENTION_MODULE_MCPWM0)       ? true \
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -57,7 +57,7 @@
 #define SOC_I2S_SUPPORTED               1
 #define SOC_RMT_SUPPORTED               1
 // #define SOC_SDM_SUPPORTED               1    // TODO: [ESP32H4] IDF-12348
-// #define SOC_GPSPI_SUPPORTED             1    // TODO: [ESP32H4] IDF-12362 IDF-12364 IDF-12366
+#define SOC_GPSPI_SUPPORTED             1
 // #define SOC_LEDC_SUPPORTED              1    // TODO: [ESP32H4] IDF-12343
 #define SOC_I2C_SUPPORTED               1
 #define SOC_SYSTIMER_SUPPORTED          1       // TODO: [ESP32H4] IDF-12375 IDF-12377
@@ -404,18 +404,16 @@
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM              3
 #define SOC_SPI_PERIPH_CS_NUM(i)        (((i)==0)? 2: (((i)==1)? 6: 3))
-#define SOC_SPI_MAX_CS_NUM          6
+#define SOC_SPI_MAX_CS_NUM              6

-// #define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
-
-// #define SOC_SPI_SUPPORT_DDRCLK              1
-// #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
-// #define SOC_SPI_SUPPORT_CD_SIG              1
-// #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
-// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
-// #define SOC_SPI_SUPPORT_CLK_XTAL            1
-// #define SOC_SPI_SUPPORT_CLK_PLL_F80M        1
-// #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
+#define SOC_SPI_SUPPORT_DDRCLK              1
+#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
+#define SOC_SPI_SUPPORT_CD_SIG              1
+#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
+#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+#define SOC_SPI_SUPPORT_CLK_XTAL            1
+#define SOC_SPI_SUPPORT_CLK_RC_FAST         1

 // Peripheral supports DIO, DOUT, QIO, or QOUT
 // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
--- a/components/soc/esp32h4/include/soc/spi_pins.h
+++ b/components/soc/esp32h4/include/soc/spi_pins.h
@@ -6,7 +6,6 @@

 #pragma once

-// TODO: [ESP32H4] IDF-12388
 #define MSPI_FUNC_NUM            0
 #define MSPI_IOMUX_PIN_NUM_CS0   7
 #define MSPI_IOMUX_PIN_NUM_CS1   6
--- a/components/soc/esp32h4/register/soc/pcr_reg.h
+++ b/components/soc/esp32h4/register/soc/pcr_reg.h
@@ -1550,9 +1550,8 @@ extern "C" {
 /** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
 *  Configures the clock source of SPI2.
 *  0 (default): XTAL_CLK
- *  1: PLL_F160M_CLK
+ *  1: PLL_F48M_CLK
 *  2: RC_FAST_CLK
- *  3: PLL_F120M_CLK
 */
 #define PCR_SPI2_CLKM_SEL    0x00000003U
 #define PCR_SPI2_CLKM_SEL_M  (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
@@ -2905,9 +2904,8 @@ extern "C" {
 /** PCR_SPI3_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
 *  Configures the clock source of SPI3.
 *  0 (default): XTAL_CLK
- *  1: PLL_F160M_CLK
+ *  1: PLL_F48M_CLK
 *  2: RC_FAST_CLK
- *  3: PLL_F120M_CLK
 */
 #define PCR_SPI3_CLKM_SEL    0x00000003U
 #define PCR_SPI3_CLKM_SEL_M  (PCR_SPI3_CLKM_SEL_V << PCR_SPI3_CLKM_SEL_S)
--- a/components/soc/esp32h4/register/soc/pcr_struct.h
+++ b/components/soc/esp32h4/register/soc/pcr_struct.h
@@ -1304,9 +1304,8 @@ typedef union {
        /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0;
         *  Configures the clock source of SPI2.
         *  0 (default): XTAL_CLK
-         *  1: PLL_F160M_CLK
+         *  1: PLL_F48M_CLK
         *  2: RC_FAST_CLK
-         *  3: PLL_F120M_CLK
         */
        uint32_t spi2_clkm_sel:2;
        /** spi2_clkm_en : R/W; bitpos: [22]; default: 1;
@@ -2452,9 +2451,8 @@ typedef union {
        /** spi3_clkm_sel : R/W; bitpos: [21:20]; default: 0;
         *  Configures the clock source of SPI3.
         *  0 (default): XTAL_CLK
-         *  1: PLL_F160M_CLK
+         *  1: PLL_F48M_CLK
         *  2: RC_FAST_CLK
-         *  3: PLL_F120M_CLK
         */
        uint32_t spi3_clkm_sel:2;
        /** spi3_clkm_en : R/W; bitpos: [22]; default: 0;
--- a/components/soc/esp32h4/register/soc/spi_reg.h
+++ b/components/soc/esp32h4/register/soc/spi_reg.h
@@ -11,7 +11,7 @@
 extern "C" {
 #endif

-#define DR_REG_SPI_BASE(i)                       (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3
+#define DR_REG_SPI_BASE(i)  (((i)>=2) ? (DR_REG_GPSPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3

 /** SPI_CMD_REG register
 *  Command control register
--- a/components/soc/esp32h4/spi_periph.c
+++ b/components/soc/esp32h4/spi_periph.c
@@ -0,0 +1,114 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include "soc/spi_periph.h"
+
+/*
+ Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
+    {
+        // MSPI has dedicated iomux pins
+    }, {
+        .spiclk_out = FSPICLK_OUT_IDX,
+        .spiclk_in = FSPICLK_IN_IDX,
+        .spid_out = FSPID_OUT_IDX,
+        .spiq_out = FSPIQ_OUT_IDX,
+        .spiwp_out = FSPIWP_OUT_IDX,
+        .spihd_out = FSPIHD_OUT_IDX,
+        .spid_in = FSPID_IN_IDX,
+        .spiq_in = FSPIQ_IN_IDX,
+        .spiwp_in = FSPIWP_IN_IDX,
+        .spihd_in = FSPIHD_IN_IDX,
+        .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX},
+        .spics_in = FSPICS0_IN_IDX,
+        .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
+        .irq = ETS_GPSPI2_INTR_SOURCE,
+        .irq_dma = -1,
+        .hw = &GPSPI2,
+        .func = SPI2_FUNC_NUM,
+    }, {
+        .spiclk_out = FSPI3CLK_OUT_IDX,
+        .spiclk_in = FSPI3CLK_IN_IDX,
+        .spid_out = FSPI3D_OUT_IDX,
+        .spiq_out = FSPI3Q_OUT_IDX,
+        .spiwp_out = FSPI3WP_OUT_IDX,
+        .spihd_out = FSPI3HD_OUT_IDX,
+        .spid_in = FSPI3D_IN_IDX,
+        .spiq_in = FSPI3Q_IN_IDX,
+        .spiwp_in = FSPI3WP_IN_IDX,
+        .spihd_in = FSPI3HD_IN_IDX,
+        .spics_out = {FSPI3CS0_OUT_IDX, FSPI3CS1_OUT_IDX, FSPI3CS2_OUT_IDX},
+        .spics_in = FSPI3CS0_IN_IDX,
+        //SPI3 doesn't have iomux pins
+        .spiclk_iomux_pin = -1,
+        .spid_iomux_pin = -1,
+        .spiq_iomux_pin = -1,
+        .spiwp_iomux_pin = -1,
+        .spihd_iomux_pin = -1,
+        .spics0_iomux_pin = -1,
+        .irq = ETS_GPSPI3_INTR_SOURCE,
+        .irq_dma = -1,
+        .hw = &GPSPI3,
+        .func = -1,
+    }
+};
+
+/**
+ * Backup registers in Light sleep: (total cnt 29)
+ *
+ * cmd
+ * addr
+ * ctrl
+ * clock
+ * user
+ * user1
+ * user2
+ * ms_dlen
+ * misc
+ * dma_conf
+ * dma_int_ena
+ * data_buf[0-15]   // slave driver only
+ * slave
+ * slave1
+ */
+#define SPI_RETENTION_REGS_CNT 29
+static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0};
+#define SPI_REG_RETENTION_ENTRIES(num) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
+                                               DR_REG_SPI_BASE(num), DR_REG_SPI_BASE(num), \
+                                               SPI_RETENTION_REGS_CNT, 0, 0, \
+                                               spi_regs_map[0], spi_regs_map[1], \
+                                               spi_regs_map[2], spi_regs_map[3]), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+    /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
+                                            SPI_DMA_INT_SET_REG(num), \
+                                            SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \
+                                            UINT32_MAX, 1, 0), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2);   // '2' for GPSPI2
+static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3);   // '3' for GPSPI3
+
+const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = {   // '-1' to except mspi
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI2,
+        .entry_array = spi2_regs_retention,
+        .array_size = ARRAY_SIZE(spi2_regs_retention),
+    }, {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI3,
+        .entry_array = spi3_regs_retention,
+        .array_size = ARRAY_SIZE(spi3_regs_retention),
+    }
+};
--- a/docs/docs_not_updated/esp32h4.txt
+++ b/docs/docs_not_updated/esp32h4.txt
@@ -144,7 +144,6 @@ api-reference/peripherals/jpeg.rst
 api-reference/peripherals/mcpwm.rst
 api-reference/peripherals/usb_host.rst
 api-reference/peripherals/camera_driver.rst
-api-reference/peripherals/spi_master.rst
 api-reference/peripherals/adc_oneshot.rst
 api-reference/peripherals/twai.rst
 api-reference/peripherals/etm.rst
@@ -154,7 +153,6 @@ api-reference/peripherals/adc_continuous.rst
 api-reference/peripherals/hmac.rst
 api-reference/peripherals/uart.rst
 api-reference/peripherals/sdspi_host.rst
-api-reference/peripherals/spi_slave_hd.rst
 api-reference/peripherals/vad.rst
 api-reference/peripherals/i2s.rst
 api-reference/peripherals/isp.rst
@@ -173,7 +171,6 @@ api-reference/peripherals/adc_calibration.rst
 api-reference/peripherals/lp_i2s.rst
 api-reference/peripherals/ecdsa.rst
 api-reference/peripherals/dac.rst
-api-reference/peripherals/spi_slave.rst
 api-reference/peripherals/spi_flash/index.rst
 api-reference/peripherals/spi_flash/spi_flash_concurrency.rst
 api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
@@ -188,7 +185,6 @@ api-reference/peripherals/lcd/spi_lcd.rst
 api-reference/peripherals/lcd/rgb_lcd.rst
 api-reference/peripherals/lcd/parl_lcd.rst
 api-reference/peripherals/pcnt.rst
-api-reference/peripherals/spi_features.rst
 api-reference/peripherals/ppa.rst
 api-reference/peripherals/ldo_regulator.rst
 api-reference/peripherals/ledc.rst
--- a/docs/en/api-reference/peripherals/spi_master.rst
+++ b/docs/en/api-reference/peripherals/spi_master.rst
@@ -481,12 +481,12 @@ GPIO Matrix and IO_MUX

 .. only:: not esp32

-    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8", esp32h21="12"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6", esp32h21="2"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7", esp32h21="3"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2", esp32h21="4"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3", esp32h21="1"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4", esp32h21="0"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8", esp32h21="12", esp32h4="20"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6", esp32h21="2",  esp32h4="16"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7", esp32h21="3",  esp32h4="17"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2", esp32h21="4",  esp32h4="15"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3", esp32h21="1",  esp32h4="19"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4", esp32h21="0",  esp32h4="18"}

    Most of the chip's peripheral signals have a direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.

@@ -532,10 +532,10 @@ The main parameter that determines the transfer speed for large transactions is
 Transaction Duration
 ^^^^^^^^^^^^^^^^^^^^

-{IDF_TARGET_MAX_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32"}
-{IDF_TARGET_MAX_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9",  esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17"}
-{IDF_TARGET_MAX_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29"}
-{IDF_TARGET_MAX_TRANS_TIME_POLL_CPU:default="N/A", esp32="8",  esp32s2="8",  esp32c3="9",  esp32s3="9",  esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14"}
+{IDF_TARGET_MAX_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32", esp32h21="60", esp32h4="70"}
+{IDF_TARGET_MAX_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9",  esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17", esp32h21="32", esp32h4="35"}
+{IDF_TARGET_MAX_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29", esp32h21="55", esp32h4="60"}
+{IDF_TARGET_MAX_TRANS_TIME_POLL_CPU:default="N/A", esp32="8",  esp32s2="8",  esp32c3="9",  esp32s3="9",  esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14", esp32h21="26", esp32h4="25"}

 Transaction duration includes setting up SPI peripheral registers, copying data to FIFOs or setting up DMA links, and the time for SPI transactions.

--- a/docs/zh_CN/api-reference/peripherals/spi_master.rst
+++ b/docs/zh_CN/api-reference/peripherals/spi_master.rst
@@ -481,12 +481,12 @@ GPIO 矩阵与 IO_MUX 管脚

 .. only:: not esp32

-    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8", esp32h21="12"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6", esp32h21="2"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7", esp32h21="3"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2", esp32h21="4"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3", esp32h21="1"}
-    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4", esp32h21="0"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CS:default="N/A",   esp32s2="10", esp32s3="10", esp32c2="10", esp32c3="10", esp32c6="16", esp32h2="1", esp32p4="7" , esp32c5="10", esp32c61="8", esp32h21="12", esp32h4="20"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_CLK:default="N/A",  esp32s2="12", esp32s3="12", esp32c2="6",  esp32c3="6",  esp32c6="6",  esp32h2="4", esp32p4="9" , esp32c5="6",  esp32c61="6", esp32h21="2",  esp32h4="16"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MOSI:default="N/A", esp32s2="11"  esp32s3="11", esp32c2="7"   esp32c3="7",  esp32c6="7",  esp32h2="5", esp32p4="8" , esp32c5="7",  esp32c61="7", esp32h21="3",  esp32h4="17"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_MISO:default="N/A", esp32s2="13"  esp32s3="13", esp32c2="2"   esp32c3="2",  esp32c6="2",  esp32h2="0", esp32p4="10", esp32c5="2",  esp32c61="2", esp32h21="4",  esp32h4="15"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_HD:default="N/A",   esp32s2="9"   esp32s3="9",  esp32c2="4"   esp32c3="4",  esp32c6="4",  esp32h2="3", esp32p4="6" , esp32c5="4",  esp32c61="3", esp32h21="1",  esp32h4="19"}
+    {IDF_TARGET_SPI2_IOMUX_PIN_WP:default="N/A",   esp32s2="14"  esp32s3="14", esp32c2="5"   esp32c3="5",  esp32c6="5",  esp32h2="2", esp32p4="11", esp32c5="5",  esp32c61="4", esp32h21="0",  esp32h4="18"}

    芯片的大多数外围信号都与之专用的 IO_MUX 管脚连接，但这些信号也可以通过较不直接的 GPIO 矩阵路由到任何其他可用的管脚。只要有一个信号是通过 GPIO 矩阵路由的，那么所有的信号都将通过它路由。

@@ -532,10 +532,10 @@ GPIO 矩阵与 IO_MUX 管脚
 传输事务持续时间
 ^^^^^^^^^^^^^^^^^^^^

-{IDF_TARGET_MAX_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32"}
-{IDF_TARGET_MAX_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9",  esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17"}
-{IDF_TARGET_MAX_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29"}
-{IDF_TARGET_MAX_TRANS_TIME_POLL_CPU:default="N/A", esp32="8",  esp32s2="8",  esp32c3="9",  esp32s3="9",  esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14"}
+{IDF_TARGET_MAX_TRANS_TIME_INTR_DMA:default="N/A", esp32="28", esp32s2="23", esp32c3="28", esp32s3="26", esp32c2="42", esp32c6="34", esp32h2="58", esp32p4="44", esp32c5="24", esp32c61="32", esp32h21="60", esp32h4="70"}
+{IDF_TARGET_MAX_TRANS_TIME_POLL_DMA:default="N/A", esp32="10", esp32s2="9",  esp32c3="10", esp32s3="11", esp32c2="17", esp32c6="17", esp32h2="28", esp32p4="27", esp32c5="15", esp32c61="17", esp32h21="32", esp32h4="35"}
+{IDF_TARGET_MAX_TRANS_TIME_INTR_CPU:default="N/A", esp32="25", esp32s2="22", esp32c3="27", esp32s3="24", esp32c2="40", esp32c6="32", esp32h2="54", esp32p4="26", esp32c5="22", esp32c61="29", esp32h21="55", esp32h4="60"}
+{IDF_TARGET_MAX_TRANS_TIME_POLL_CPU:default="N/A", esp32="8",  esp32s2="8",  esp32c3="9",  esp32s3="9",  esp32c2="15", esp32c6="15", esp32h2="24", esp32p4="12", esp32c5="12", esp32c61="14", esp32h21="26", esp32h4="25"}

 传输事务持续时间包括设置 SPI 外设寄存器，将数据复制到 FIFO 或设置 DMA 链接，以及 SPI 传输事务时间。

--- a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md
+++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

 # I2S TDM Example -- ES7210 4-Ch ADC Codec

--- a/examples/peripherals/lcd/spi_lcd_touch/README.md
+++ b/examples/peripherals/lcd/spi_lcd_touch/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 # SPI LCD and Touch Panel Example

--- a/examples/peripherals/lcd/tjpgd/README.md
+++ b/examples/peripherals/lcd/tjpgd/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 ## LCD tjpgd example

--- a/examples/peripherals/spi_master/hd_eeprom/README.md
+++ b/examples/peripherals/spi_master/hd_eeprom/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 ## SPI master half duplex EEPROM example

--- a/examples/peripherals/spi_master/lcd/README.md
+++ b/examples/peripherals/spi_master/lcd/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 # SPI Host Driver Example

--- a/examples/peripherals/spi_slave/README.md
+++ b/examples/peripherals/spi_slave/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 ## SPI slave example

--- a/examples/peripherals/spi_slave_hd/append_mode/master/README.md
+++ b/examples/peripherals/spi_slave_hd/append_mode/master/README.md
@@ -1,4 +1,4 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 See README.md in the parent directory
--- a/examples/peripherals/spi_slave_hd/append_mode/slave/README.md
+++ b/examples/peripherals/spi_slave_hd/append_mode/slave/README.md
@@ -1,4 +1,4 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 See README.md in the parent directory
--- a/examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md
+++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_master/README.md
@@ -1,4 +1,4 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 See README.md in the parent directory
--- a/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md
+++ b/examples/peripherals/spi_slave_hd/segment_mode/seg_slave/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
--- a/examples/storage/sd_card/sdspi/README.md
+++ b/examples/storage/sd_card/sdspi/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |

 # SD Card example (SDSPI)