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bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability. This commit helps to clear WEL when flash configuration is done. **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA. 2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips. Status register bitmap of ISSI chip and GD chip: | SR | ISSI | GD25LQ32C | | -- | ---- | --------- | | 0 | WIP | WIP | | 1 | WEL | WEL | | 2 | BP0 | BP0 | | 3 | BP1 | BP1 | | 4 | BP2 | BP2 | | 5 | BP3 | BP3 | | 6 | QE | BP4 | | 7 | SRWD | SRP0 | | 8 | | SRP1 | | 9 | | QE | | 10 | | SUS2 | | 11 | | LB1 | | 12 | | LB2 | | 13 | | LB3 | | 14 | | CMP | | 15 | | SUS1 | QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command. However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips. Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected. This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6). 3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared. This commit skips the clearing of status register if there is no protection bits active. Also move the execute_flash_command to be a bootloader API; move implementation of spi_flash_wrap_set to the bootloader
This commit is contained in:
Michael (XIAO Xufeng)
@@ -16,10 +16,26 @@
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#include <bootloader_flash.h>
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#include <esp_log.h>
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#include <esp_flash_encrypt.h>
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/spi_flash.h"
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#include "sdkconfig.h"
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#include "soc/soc_caps.h"
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#if CONFIG_IDF_TARGET_ESP32
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# include "soc/spi_struct.h"
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# include "soc/spi_reg.h"
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/* SPI flash controller */
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# define SPIFLASH SPI1
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#else
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# include "soc/spi_mem_struct.h"
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# include "soc/spi_mem_reg.h"
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/* SPI flash controller */
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# define SPIFLASH SPIMEM1
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/spi_flash.h" //For SPI_Encrypt_Write
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#endif
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#ifndef BOOTLOADER_BUILD
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/* Normal app version maps to esp_spi_flash.h operations...
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*/
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@@ -364,4 +380,90 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
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}
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return spi_to_esp_err(rc);
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}
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#endif
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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uint32_t bootloader_execute_flash_command(uint8_t command, uint32_t mosi_data, uint8_t mosi_len, uint8_t miso_len)
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{
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uint32_t old_ctrl_reg = SPIFLASH.ctrl.val;
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#if CONFIG_IDF_TARGET_ESP32
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SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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SPIFLASH.ctrl.val = SPI_MEM_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode
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#endif
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SPIFLASH.user.usr_dummy = 0;
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SPIFLASH.user.usr_addr = 0;
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SPIFLASH.user.usr_command = 1;
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SPIFLASH.user2.usr_command_bitlen = 7;
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SPIFLASH.user2.usr_command_value = command;
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SPIFLASH.user.usr_miso = miso_len > 0;
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#if CONFIG_IDF_TARGET_ESP32
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SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0;
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0;
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#endif
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SPIFLASH.user.usr_mosi = mosi_len > 0;
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#if CONFIG_IDF_TARGET_ESP32
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SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0;
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0;
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#endif
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SPIFLASH.data_buf[0] = mosi_data;
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if (g_rom_spiflash_dummy_len_plus[1]) {
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/* When flash pins are mapped via GPIO matrix, need a dummy cycle before reading via MISO */
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if (miso_len > 0) {
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SPIFLASH.user.usr_dummy = 1;
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SPIFLASH.user1.usr_dummy_cyclelen = g_rom_spiflash_dummy_len_plus[1] - 1;
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} else {
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SPIFLASH.user.usr_dummy = 0;
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SPIFLASH.user1.usr_dummy_cyclelen = 0;
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}
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}
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SPIFLASH.cmd.usr = 1;
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while (SPIFLASH.cmd.usr != 0) {
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}
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SPIFLASH.ctrl.val = old_ctrl_reg;
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return SPIFLASH.data_buf[0];
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}
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void bootloader_enable_wp(void)
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{
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bootloader_execute_flash_command(CMD_WRDI, 0, 0, 0); /* Exit OTP mode */
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}
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#if SOC_CACHE_SUPPORT_WRAP
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esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode)
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{
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uint32_t reg_bkp_ctrl = SPIFLASH.ctrl.val;
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uint32_t reg_bkp_usr = SPIFLASH.user.val;
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SPIFLASH.user.fwrite_dio = 0;
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SPIFLASH.user.fwrite_dual = 0;
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SPIFLASH.user.fwrite_qio = 1;
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SPIFLASH.user.fwrite_quad = 0;
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SPIFLASH.ctrl.fcmd_dual = 0;
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SPIFLASH.ctrl.fcmd_quad = 0;
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SPIFLASH.user.usr_dummy = 0;
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SPIFLASH.user.usr_addr = 1;
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SPIFLASH.user.usr_command = 1;
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SPIFLASH.user2.usr_command_bitlen = 7;
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SPIFLASH.user2.usr_command_value = CMD_WRAP;
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SPIFLASH.user1.usr_addr_bitlen = 23;
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SPIFLASH.addr = 0;
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SPIFLASH.user.usr_miso = 0;
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SPIFLASH.user.usr_mosi = 1;
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SPIFLASH.mosi_dlen.usr_mosi_bit_len = 7;
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SPIFLASH.data_buf[0] = (uint32_t) mode << 4;;
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SPIFLASH.cmd.usr = 1;
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while(SPIFLASH.cmd.usr != 0)
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{ }
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SPIFLASH.ctrl.val = reg_bkp_ctrl;
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SPIFLASH.user.val = reg_bkp_usr;
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return ESP_OK;
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}
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#endif //SOC_CACHE_SUPPORT_WRAP
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