Merge branch 'feature/iram_esp_system' into 'master'

feat(esp_system): Adds Kconfigs to place code in IRAM

Closes IDF-11426

See merge request espressif/esp-idf!38292

components/esp_system/Kconfig

@@ -9,6 +9,25 @@ menu "ESP System Settings"
 
     orsource "./port/soc/$IDF_TARGET/Kconfig.tracemem"
 
+    config ESP_SYSTEM_IN_IRAM
+        bool "Place system functions in IRAM" if SPI_FLASH_AUTO_SUSPEND
+        default y
+        help
+            The following system functions will be placed in IRAM if this option is enabled:
+            - system startup
+            - system time
+            - system error
+            - system restart
+            - system crosscore
+            - system debug
+            - system APB backup DMA lock
+            - system application tick hook
+            - Unified Behavior Sanitizer (UBSAN) hook
+            - Interrupt watchdog handler
+            - XTAL32K watchdog timer
+            - USB CDC functions for the esp_rom_printf (if ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF=y)
+            - IPC and IPC ISR
+
     choice ESP_SYSTEM_PANIC
         prompt "Panic handler behaviour"
         default ESP_SYSTEM_PANIC_PRINT_REBOOT
@@ -635,6 +654,11 @@ endmenu  # ESP System Settings
 
 menu "IPC (Inter-Processor Call)"
 
+    config ESP_IPC_ENABLE
+        bool
+        default y
+        depends on !ESP_SYSTEM_SINGLE_CORE_MODE || APPTRACE_GCOV_ENABLE
+
     config ESP_IPC_TASK_STACK_SIZE
         int "Inter-Processor Call (IPC) task stack size"
         range 512 65536 if !APPTRACE_ENABLE
@@ -651,7 +675,7 @@ menu "IPC (Inter-Processor Call)"
     config ESP_IPC_USES_CALLERS_PRIORITY
         bool "IPC runs at caller's priority"
         default y
-        depends on !FREERTOS_UNICORE
+        depends on ESP_IPC_ENABLE
         help
             If this option is not enabled then the IPC task will keep behavior same as prior to that of ESP-IDF v4.0,
             hence IPC task will run at (configMAX_PRIORITIES - 1) priority.

components/esp_system/crosscore_int.c

@@ -5,7 +5,7 @@
  */
 #include "sdkconfig.h"
 #include <stdint.h>
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "esp_err.h"
 #include "esp_cpu.h"
 #include "esp_intr_alloc.h"
@@ -34,12 +34,12 @@ static volatile uint32_t reason[CONFIG_FREERTOS_NUMBER_OF_CORES];
 ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
 the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
 */
-static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
+static inline void ESP_SYSTEM_IRAM_ATTR esp_crosscore_isr_handle_yield(void)
 {
     portYIELD_FROM_ISR();
 }
 
-static void IRAM_ATTR esp_crosscore_isr(void *arg)
+static void ESP_SYSTEM_IRAM_ATTR esp_crosscore_isr(void *arg)
 {
     uint32_t my_reason_val;
     //A pointer to the correct reason array item is passed to this ISR.
@@ -93,19 +93,23 @@ void esp_crosscore_int_init(void)
     reason[esp_cpu_get_core_id()] = 0;
     portEXIT_CRITICAL(&reason_spinlock);
     esp_err_t err __attribute__((unused)) = ESP_OK;
+    int flags = 0;
+#if CONFIG_ESP_SYSTEM_IN_IRAM
+    flags |= ESP_INTR_FLAG_IRAM;
+#endif
 #if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
     if (esp_cpu_get_core_id() == 0) {
-        err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
+        err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, flags, esp_crosscore_isr, (void*)&reason[0], NULL);
     } else {
-        err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
+        err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_1_SOURCE, flags, esp_crosscore_isr, (void*)&reason[1], NULL);
     }
 #else
-    err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
+    err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, flags, esp_crosscore_isr, (void*)&reason[0], NULL);
 #endif
     ESP_ERROR_CHECK(err);
 }
 
-static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
+static void ESP_SYSTEM_IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
 {
     assert(core_id < CONFIG_FREERTOS_NUMBER_OF_CORES);
     //Mark the reason we interrupt the other CPU
@@ -116,28 +120,28 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
     crosscore_int_ll_trigger_interrupt(core_id);
 }
 
-void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
+void ESP_SYSTEM_IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
 {
     esp_crosscore_int_send(core_id, REASON_YIELD);
 }
 
-void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
+void ESP_SYSTEM_IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
 {
     esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
 }
 
-void IRAM_ATTR esp_crosscore_int_send_gdb_call(int core_id)
+void ESP_SYSTEM_IRAM_ATTR esp_crosscore_int_send_gdb_call(int core_id)
 {
     esp_crosscore_int_send(core_id, REASON_GDB_CALL);
 }
 
-void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
+void ESP_SYSTEM_IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
 {
     esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
 }
 
 #if CONFIG_ESP_TASK_WDT_EN
-void IRAM_ATTR esp_crosscore_int_send_twdt_abort(int core_id)
+void ESP_SYSTEM_IRAM_ATTR esp_crosscore_int_send_twdt_abort(int core_id)
 {
     esp_crosscore_int_send(core_id, REASON_TWDT_ABORT);
 }

components/esp_system/esp_ipc.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,7 +12,7 @@
 #include "esp_err.h"
 #include "esp_ipc.h"
 #include "esp_private/esp_ipc_isr.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "esp_cpu.h"
 
 #include "freertos/FreeRTOS.h"
@@ -21,7 +21,7 @@
 
 #define IPC_MAX_PRIORITY (configMAX_PRIORITIES - 1)
 
-#if !defined(CONFIG_FREERTOS_UNICORE) || defined(CONFIG_APPTRACE_GCOV_ENABLE)
+#if CONFIG_ESP_IPC_ENABLE
 
 #if CONFIG_COMPILER_OPTIMIZATION_NONE
 #define IPC_STACK_SIZE (CONFIG_ESP_IPC_TASK_STACK_SIZE + 0x100)
@@ -49,7 +49,7 @@ static volatile esp_ipc_func_t s_no_block_func[portNUM_PROCESSORS] = { 0 };
 static volatile bool s_no_block_func_and_arg_are_ready[portNUM_PROCESSORS] = { 0 };
 static void * volatile s_no_block_func_arg[portNUM_PROCESSORS];
 
-static void IRAM_ATTR ipc_task(void* arg)
+static void ESP_SYSTEM_IRAM_ATTR ipc_task(void* arg)
 {
     const int cpuid = (int) arg;
 
@@ -198,4 +198,4 @@ esp_err_t esp_ipc_call_nonblocking(uint32_t cpu_id, esp_ipc_func_t func, void* a
     return ESP_FAIL;
 }
 
-#endif // !defined(CONFIG_FREERTOS_UNICORE) || defined(CONFIG_APPTRACE_GCOV_ENABLE)
+#endif // CONFIG_ESP_IPC_ENABLE

components/esp_system/fp_unwind.c

@@ -6,6 +6,7 @@
 
 #include "sdkconfig.h"
 #include <string.h>
+#include "esp_private/esp_system_attr.h"
 #include "esp_private/panic_internal.h"
 #include "esp_memory_utils.h"
 #include "riscv/libunwind-riscv.h"
@@ -52,7 +53,7 @@ static inline bool esp_fp_ptr_is_data(void* ptr)
  *
  * @returns Number of entries filled in the array.
  */
-uint32_t IRAM_ATTR esp_fp_get_callers(uint32_t frame, void** callers, void** stacks, uint32_t depth)
+uint32_t ESP_SYSTEM_IRAM_ATTR esp_fp_get_callers(uint32_t frame, void** callers, void** stacks, uint32_t depth)
 {
     uint32_t written = 0;
     uint32_t pc = 0;

components/esp_system/freertos_hooks.c

@@ -27,7 +27,7 @@ static portMUX_TYPE hooks_spinlock = portMUX_INITIALIZER_UNLOCKED;
 static esp_freertos_idle_cb_t idle_cb[CONFIG_FREERTOS_NUMBER_OF_CORES][MAX_HOOKS] = {0};
 static esp_freertos_tick_cb_t tick_cb[CONFIG_FREERTOS_NUMBER_OF_CORES][MAX_HOOKS] = {0};
 
-void IRAM_ATTR esp_vApplicationTickHook(void)
+void esp_vApplicationTickHook(void)
 {
     int n;
     int core = xPortGetCoreID();

components/esp_system/include/esp_private/esp_system_attr.h

@@ -0,0 +1,24 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_attr.h"
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if CONFIG_ESP_SYSTEM_IN_IRAM
+#define ESP_SYSTEM_IRAM_ATTR IRAM_ATTR
+#else
+#define ESP_SYSTEM_IRAM_ATTR
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/esp_system/int_wdt.c

@@ -17,7 +17,7 @@
 #include "esp_cpu.h"
 #include "esp_check.h"
 #include "esp_err.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "esp_log.h"
 #include "esp_intr_alloc.h"
 #include "esp_chip_info.h"
@@ -101,7 +101,7 @@ extern uint32_t _lx_intr_livelock_counter, _lx_intr_livelock_max;
 volatile bool int_wdt_cpu1_ticked = false;
 #endif
 
-static void IRAM_ATTR tick_hook(void)
+static void ESP_SYSTEM_IRAM_ATTR tick_hook(void)
 {
 #if CONFIG_ESP_INT_WDT_CHECK_CPU1
     if (esp_cpu_get_core_id() != 0) {

components/esp_system/linker.lf

@@ -12,9 +12,27 @@ entries:
             hw_stack_guard:esp_hw_stack_guard_get_fired_cpu (noflash)
             hw_stack_guard:esp_hw_stack_guard_get_pc (noflash)
 
+    # These functions are called when the cache is disabled
+    system_internal:esp_restart_noos (noflash)
+    system_internal:esp_system_reset_modules_on_exit (noflash)
+
+    if ESP_PANIC_HANDLER_IRAM = y || ESP_BROWNOUT_USE_INTR = y:
+        reset_reason:esp_reset_reason_set_hint (noflash)
+
+    # It may be called very frequently, so place it in IRAM to avoid performance degradation
+    freertos_hooks:esp_vApplicationTickHook (noflash)
+
+    if ESP_SYSTEM_IN_IRAM = y:
         esp_err (noflash)
         esp_system_chip:esp_system_abort (noflash)
+        panic:panic_abort (noflash)
+        if IDF_TARGET_ESP32 = y:
+            esp_system_chip:esp_restart_noos_dig (noflash)
+        system_time:esp_system_get_time (noflash)
+        system_time:esp_system_get_time_resolution (noflash)
         ubsan (noflash)
+        if COMPILER_STACK_CHECK = y:
+            stack_check:__stack_chk_fail (noflash)
 
         if ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF:
             usb_console:esp_usb_console_write_char (noflash)
@@ -36,6 +54,7 @@ entries:
 [mapping:vfs_cdcacm]
 archive: libvfs.a
 entries:
+    if ESP_SYSTEM_IN_IRAM = y:
         if ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF:
             vfs_cdcacm:cdcacm_tx_cb (noflash)
             vfs_cdcacm:cdcacm_rx_cb (noflash)

components/esp_system/panic.c

@@ -463,7 +463,7 @@ void esp_panic_handler(panic_info_t *info)
 #endif /* CONFIG_ESP_SYSTEM_PANIC_GDBSTUB */
 }
 
-void IRAM_ATTR __attribute__((noreturn, no_sanitize_undefined)) panic_abort(const char *details)
+void __attribute__((noreturn, no_sanitize_undefined)) panic_abort(const char *details)
 {
     g_panic_abort = true;
     g_panic_abort_details = (char *) details;
@@ -490,11 +490,11 @@ void IRAM_ATTR __attribute__((noreturn, no_sanitize_undefined)) panic_abort(cons
  * If these weren't provided, reset reason code would be linked into the app
  * even if the app never called esp_reset_reason().
  */
-void IRAM_ATTR __attribute__((weak)) esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void __attribute__((weak)) esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
 }
 
-esp_reset_reason_t IRAM_ATTR  __attribute__((weak)) esp_reset_reason_get_hint(void)
+esp_reset_reason_t __attribute__((weak)) esp_reset_reason_get_hint(void)
 {
     return ESP_RST_UNKNOWN;
 }

components/esp_system/port/arch/riscv/debug_helpers.c

@@ -11,7 +11,7 @@
 #include "freertos/task.h"
 #include "esp_private/freertos_debug.h"
 #include "esp_err.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "esp_private/esp_cpu_internal.h"
 #include <string.h>
 
@@ -36,7 +36,7 @@ extern void panic_print_registers(const void *frame, int core);
     * exit this handler as fast as possible, then we will simply print
     * the interruptee's registers.
     */
-esp_err_t IRAM_ATTR esp_backtrace_print(int depth)
+esp_err_t ESP_SYSTEM_IRAM_ATTR esp_backtrace_print(int depth)
 {
     (void)depth;
 

components/esp_system/port/arch/riscv/esp_ipc_isr_port.c

@@ -12,7 +12,7 @@
 #include "riscv/interrupt.h"
 #include "esp_rom_sys.h"
 #include "esp_cpu.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "sdkconfig.h"
 
 void esp_ipc_isr_port_init(const int cpuid)
@@ -36,7 +36,7 @@ void esp_ipc_isr_port_init(const int cpuid)
     esp_intr_enable_source(ETS_IPC_ISR_INUM);
 }
 
-IRAM_ATTR void esp_ipc_isr_port_int_trigger(const int cpuid)
+ESP_SYSTEM_IRAM_ATTR void esp_ipc_isr_port_int_trigger(const int cpuid)
 {
     if (cpuid == 0) {
         // it runs an interrupt on cpu0

components/esp_system/port/arch/riscv/esp_ipc_isr_routines.c

@@ -5,9 +5,9 @@
  */
 
 #include "stdint.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 
-void IRAM_ATTR esp_ipc_isr_waiting_for_finish_cmd(void* ipc_isr_finish_cmd)
+void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_waiting_for_finish_cmd(void* ipc_isr_finish_cmd)
 {
     while (*(volatile uint32_t *)ipc_isr_finish_cmd == 0) { };
 }

components/esp_system/port/arch/xtensa/debug_helpers.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,7 +9,7 @@
 #include <sys/param.h>
 #include "soc/soc_memory_layout.h"
 #include "esp_types.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "esp_err.h"
 #include "esp_check.h"
 #include "esp_ipc.h"
@@ -24,7 +24,7 @@
 
 const char *DEBUG_HELPER_TAG = "DBG HLPR";
 
-bool IRAM_ATTR esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame)
+bool ESP_SYSTEM_IRAM_ATTR esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame)
 {
     //Use frame(i-1)'s BS area located below frame(i)'s sp to get frame(i-1)'s sp and frame(i-2)'s pc
     void *base_save = (void *)frame->sp;     //Base save area consists of 4 words under SP
@@ -36,7 +36,7 @@ bool IRAM_ATTR esp_backtrace_get_next_frame(esp_backtrace_frame_t *frame)
     return (esp_stack_ptr_is_sane(frame->sp) && esp_ptr_executable((void*)esp_cpu_process_stack_pc(frame->pc)));
 }
 
-static void IRAM_ATTR print_entry(uint32_t pc, uint32_t sp, bool panic)
+static void ESP_SYSTEM_IRAM_ATTR print_entry(uint32_t pc, uint32_t sp, bool panic)
 {
     if (panic) {
         panic_print_str(" 0x");
@@ -48,7 +48,7 @@ static void IRAM_ATTR print_entry(uint32_t pc, uint32_t sp, bool panic)
     }
 }
 
-static void IRAM_ATTR print_str(const char* str, bool panic)
+static void ESP_SYSTEM_IRAM_ATTR print_str(const char* str, bool panic)
 {
     if (panic) {
         panic_print_str(str);
@@ -57,7 +57,7 @@ static void IRAM_ATTR print_str(const char* str, bool panic)
     }
 }
 
-esp_err_t IRAM_ATTR esp_backtrace_print_from_frame(int depth, const esp_backtrace_frame_t* frame, bool panic)
+esp_err_t ESP_SYSTEM_IRAM_ATTR esp_backtrace_print_from_frame(int depth, const esp_backtrace_frame_t* frame, bool panic)
 {
     //Check arguments
     if (depth <= 0) {
@@ -97,7 +97,7 @@ esp_err_t IRAM_ATTR esp_backtrace_print_from_frame(int depth, const esp_backtrac
     return ret;
 }
 
-esp_err_t IRAM_ATTR esp_backtrace_print(int depth)
+esp_err_t ESP_SYSTEM_IRAM_ATTR esp_backtrace_print(int depth)
 {
     //Initialize stk_frame with first frame of stack
     esp_backtrace_frame_t start = { 0 };
@@ -149,7 +149,7 @@ static void backtrace_other_cores_ipc_func(void *arg)
 }
 #endif // !CONFIG_FREERTOS_UNICORE
 
-esp_err_t IRAM_ATTR esp_backtrace_print_all_tasks(int depth)
+esp_err_t ESP_SYSTEM_IRAM_ATTR esp_backtrace_print_all_tasks(int depth)
 {
     esp_err_t ret = ESP_OK;
     TaskSnapshot_t *task_snapshots;

components/esp_system/port/arch/xtensa/esp_ipc_isr_port.c

@@ -12,7 +12,7 @@
 #endif
 #include "esp_rom_sys.h"
 #include "esp_intr_alloc.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "sdkconfig.h"
 
 void esp_ipc_isr_port_init(const int cpuid)
@@ -23,7 +23,7 @@ void esp_ipc_isr_port_init(const int cpuid)
     ESP_INTR_ENABLE(ETS_IPC_ISR_INUM);
 }
 
-IRAM_ATTR void esp_ipc_isr_port_int_trigger(const int cpuid)
+ESP_SYSTEM_IRAM_ATTR void esp_ipc_isr_port_int_trigger(const int cpuid)
 {
     if (cpuid == 0) {
         // it runs an interrupt on cpu0

components/esp_system/port/arch/xtensa/esp_ipc_isr_routines.S

@@ -8,13 +8,16 @@
 #include <xtensa/corebits.h>
 #include <xtensa/config/system.h>
 #include <xtensa/hal.h>
+#include "sdkconfig.h"
 
 /* esp_ipc_isr_waiting_for_finish_cmd(void* finish_cmd)
  *
  * It should be called by the CALLX0 command from the handler of High-priority interrupt.
  * Only these registers [a2, a3, a4] can be used here.
  */
+#if CONFIG_ESP_SYSTEM_IN_IRAM
     .section    .iram1, "ax"
+#endif
     .align      4
     .global     esp_ipc_isr_waiting_for_finish_cmd
     .type       esp_ipc_isr_waiting_for_finish_cmd, @function

components/esp_system/port/cpu_start.c

@@ -8,7 +8,7 @@
 #include <string.h>
 #include <stdbool.h>
 
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "esp_err.h"
 
 #include "esp_log.h"
@@ -194,7 +194,7 @@ void startup_resume_other_cores(void)
     s_resume_cores = true;
 }
 
-void IRAM_ATTR call_start_cpu1(void)
+void ESP_SYSTEM_IRAM_ATTR call_start_cpu1(void)
 {
 #ifdef __riscv
     // Configure the global pointer register
@@ -325,7 +325,7 @@ static void restore_app_mmu_from_pro_mmu(void)
 }
 #endif
 // This function is needed to make the multicore app runnable on a unicore bootloader (built with FREERTOS UNICORE).
-// It does some cache settings for other CPUs.
+// It does some cache settings for other CPUs, so it must be in IRAM.
 void IRAM_ATTR do_multicore_settings(void)
 {
     // We intentionally do not check the cache settings before changing them,

components/esp_system/port/esp_ipc_isr.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,7 +9,7 @@
 #include <string.h>
 #include <assert.h>
 #include "esp_err.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "freertos/portmacro.h"
@@ -63,14 +63,14 @@ void esp_ipc_isr_init(void)
 
 /* Public API functions */
 
-void IRAM_ATTR esp_ipc_isr_call(esp_ipc_isr_func_t func, void* arg)
+void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_call(esp_ipc_isr_func_t func, void* arg)
 {
     IPC_ISR_ENTER_CRITICAL();
     esp_ipc_isr_call_and_wait(func, arg, IPC_ISR_WAIT_FOR_START);
     IPC_ISR_EXIT_CRITICAL();
 }
 
-void IRAM_ATTR esp_ipc_isr_call_blocking(esp_ipc_isr_func_t func, void* arg)
+void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_call_blocking(esp_ipc_isr_func_t func, void* arg)
 {
     IPC_ISR_ENTER_CRITICAL();
     esp_ipc_isr_call_and_wait(func, arg, IPC_ISR_WAIT_FOR_END);
@@ -90,7 +90,7 @@ void esp_ipc_isr_waiting_for_finish_cmd(void* finish_cmd);
  * When cpu1 already in high-priority interrupt, cpu0 can access DPORT register.
  * Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
  */
-void IRAM_ATTR esp_ipc_isr_stall_other_cpu(void)
+void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_stall_other_cpu(void)
 {
 #if CONFIG_FREERTOS_SMP
     /*
@@ -123,7 +123,7 @@ void IRAM_ATTR esp_ipc_isr_stall_other_cpu(void)
     }
 }
 
-void IRAM_ATTR esp_ipc_isr_release_other_cpu(void)
+void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_release_other_cpu(void)
 {
     if (s_stall_state == STALL_STATE_RUNNING) {
         const uint32_t cpu_id = xPortGetCoreID();
@@ -150,20 +150,20 @@ void IRAM_ATTR esp_ipc_isr_release_other_cpu(void)
 #endif
 }
 
-void IRAM_ATTR esp_ipc_isr_stall_pause(void)
+void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_stall_pause(void)
 {
     IPC_ISR_ENTER_CRITICAL();
     s_stall_state = STALL_STATE_IDLE;
     IPC_ISR_EXIT_CRITICAL();
 }
 
-void IRAM_ATTR esp_ipc_isr_stall_abort(void)
+void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_stall_abort(void)
 {
     //Note: We don't enter a critical section here as we are calling this from a panic.
     s_stall_state = STALL_STATE_IDLE;
 }
 
-void IRAM_ATTR esp_ipc_isr_stall_resume(void)
+void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_stall_resume(void)
 {
     IPC_ISR_ENTER_CRITICAL();
     s_stall_state = STALL_STATE_RUNNING;
@@ -174,7 +174,7 @@ void IRAM_ATTR esp_ipc_isr_stall_resume(void)
 
 /* Private functions*/
 
-static void IRAM_ATTR esp_ipc_isr_call_and_wait(esp_ipc_isr_func_t func, void* arg, esp_ipc_isr_wait_t wait_for)
+static void ESP_SYSTEM_IRAM_ATTR esp_ipc_isr_call_and_wait(esp_ipc_isr_func_t func, void* arg, esp_ipc_isr_wait_t wait_for)
 {
     const uint32_t cpu_id = xPortGetCoreID();
 

components/esp_system/port/esp_system_chip.c

@@ -21,7 +21,7 @@
 
 // used only by ESP32 panic handler
 #ifdef CONFIG_IDF_TARGET_ESP32
-void IRAM_ATTR esp_restart_noos_dig(void)
+void esp_restart_noos_dig(void)
 {
     // In case any of the calls below results in re-enabling of interrupts
     // (for example, by entering a critical section), disable all the

components/esp_system/port/panic_handler.c

@@ -287,6 +287,7 @@ static void IRAM_ATTR panic_enable_cache(void)
 }
 #endif
 
+// This function must always be in IRAM as it is required to re-enable the flash cache.
 void IRAM_ATTR panicHandler(void *frame)
 {
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
@@ -299,6 +300,7 @@ void IRAM_ATTR panicHandler(void *frame)
     panic_handler(frame, true);
 }
 
+// This function must always be in IRAM as it is required to re-enable the flash cache.
 void IRAM_ATTR xt_unhandled_exception(void *frame)
 {
 #if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP

components/esp_system/port/soc/esp32/reset_reason.c

@@ -87,7 +87,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32/system_internal.c

@@ -28,7 +28,7 @@
 #include "esp32/rom/cache.h"
 #include "esp32/rom/rtc.h"
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -63,7 +63,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     esp_cpu_intr_disable(0xFFFFFFFF);

components/esp_system/port/soc/esp32c2/clk.c

@@ -281,7 +281,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
 }
 
 // Workaround for bootloader not calibrated well issue.
-// Placed in IRAM because disabling BBPLL may influence the cache
+// Placed in IRAM because disabling BBPLL may influence the cache.
 static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
 {
     rtc_cpu_freq_config_t old_config;

components/esp_system/port/soc/esp32c2/reset_reason.c

@@ -76,7 +76,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32c2/system_internal.c

@@ -27,7 +27,7 @@
 #include "esp32c2/rom/cache.h"
 #include "esp32c2/rom/rtc.h"
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -55,7 +55,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     rv_utils_intr_global_disable();

components/esp_system/port/soc/esp32c3/apb_backup_dma.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,14 +7,15 @@
 #include "soc/soc_caps.h"
 
 #if SOC_APB_BACKUP_DMA
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/portmacro.h"
 #include "esp32c3/rom/apb_backup_dma.h"
+#include "sdkconfig.h"
 
 static portMUX_TYPE s_apb_backup_dma_mutex = portMUX_INITIALIZER_UNLOCKED;
 
-static void IRAM_ATTR apb_backup_dma_lock(void)
+static void ESP_SYSTEM_IRAM_ATTR apb_backup_dma_lock(void)
 {
     if (xPortInIsrContext()) {
         portENTER_CRITICAL_ISR(&s_apb_backup_dma_mutex);
@@ -23,7 +24,7 @@ static void IRAM_ATTR apb_backup_dma_lock(void)
     }
 }
 
-static void IRAM_ATTR apb_backup_dma_unlock(void)
+static void ESP_SYSTEM_IRAM_ATTR apb_backup_dma_unlock(void)
 {
     if (xPortInIsrContext()) {
         portEXIT_CRITICAL_ISR(&s_apb_backup_dma_mutex);

components/esp_system/port/soc/esp32c3/reset_reason.c

@@ -93,7 +93,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32c3/system_internal.c

@@ -28,7 +28,7 @@
 #include "esp32c3/rom/cache.h"
 #include "esp32c3/rom/rtc.h"
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -64,7 +64,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     rv_utils_intr_global_disable();

components/esp_system/port/soc/esp32c5/reset_reason.c

@@ -102,7 +102,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32c5/system_internal.c

@@ -32,7 +32,7 @@
 #include "esp32c5/rom/rtc.h"
 #include "soc/pcr_reg.h"
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     esp_rom_output_tx_wait_idle(0);
@@ -88,7 +88,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     rv_utils_intr_global_disable();

components/esp_system/port/soc/esp32c6/clk.c

@@ -328,7 +328,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
 }
 
 // Workaround for bootloader not calibrated well issue.
-// Placed in IRAM because disabling BBPLL may influence the cache
+// Placed in IRAM because disabling BBPLL may influence the cache.
 static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
 {
     rtc_cpu_freq_config_t old_config;

components/esp_system/port/soc/esp32c6/reset_reason.c

@@ -99,7 +99,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32c6/system_internal.c

@@ -29,7 +29,7 @@
 #include "esp32c6/rom/rtc.h"
 #include "soc/pcr_reg.h"
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -81,7 +81,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     rv_utils_intr_global_disable();

components/esp_system/port/soc/esp32c61/reset_reason.c

@@ -102,7 +102,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32c61/system_internal.c

@@ -32,7 +32,7 @@
 #include "esp32c61/rom/rtc.h"
 #include "soc/pcr_reg.h"
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -88,7 +88,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     rv_utils_intr_global_disable();

components/esp_system/port/soc/esp32h2/clk.c

@@ -313,7 +313,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
 }
 
 // Workaround for bootloader not calibrated well issue.
-// Placed in IRAM because disabling BBPLL may influence the cache
+// Placed in IRAM because disabling BBPLL may influence the cache.
 static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
 {
     rtc_cpu_freq_config_t old_config;

components/esp_system/port/soc/esp32h2/reset_reason.c

@@ -99,7 +99,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32h2/system_internal.c

@@ -30,7 +30,7 @@
 #include "esp32h2/rom/rtc.h"
 #include "soc/pcr_reg.h"
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -79,7 +79,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     rv_utils_intr_global_disable();

components/esp_system/port/soc/esp32h21/reset_reason.c

@@ -98,7 +98,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32h21/system_internal.c

@@ -30,7 +30,7 @@
 
 // TODO: [ESP32H21] IDF-11900, IDF-11911
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -83,7 +83,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     rv_utils_intr_global_disable();

components/esp_system/port/soc/esp32h4/reset_reason.c

@@ -93,7 +93,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32h4/system_internal.c

@@ -24,7 +24,7 @@
 #include "esp32h4/rom/cache.h"
 // TODO: IDF-11911 need refactor
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -75,7 +75,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     rv_utils_intr_global_disable();

components/esp_system/port/soc/esp32p4/clk.c

@@ -78,6 +78,7 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src);
 
 static const char *TAG = "clk";
 
+// This function must be allocated in IRAM.
 void IRAM_ATTR esp_rtc_init(void)
 {
 #if SOC_PMU_SUPPORTED

components/esp_system/port/soc/esp32p4/reset_reason.c

@@ -104,7 +104,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32p4/system_internal.c

@@ -33,7 +33,7 @@
 #include "hal/dw_gdma_ll.h"
 #include "hal/dma2d_ll.h"
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -140,7 +140,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     rv_utils_intr_global_disable();

components/esp_system/port/soc/esp32s2/reset_reason.c

@@ -86,7 +86,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32s2/system_internal.c

@@ -30,7 +30,7 @@
 
 extern int _bss_end;
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -64,7 +64,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     esp_cpu_intr_disable(0xFFFFFFFF);

components/esp_system/port/soc/esp32s3/apb_backup_dma.c

@@ -1,18 +1,19 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/soc_caps.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/portmacro.h"
 #include "esp32s3/rom/apb_backup_dma.h"
+#include "sdkconfig.h"
 
 static portMUX_TYPE s_apb_backup_dma_mutex = portMUX_INITIALIZER_UNLOCKED;
 
-static void IRAM_ATTR apb_backup_dma_lock(void)
+static void ESP_SYSTEM_IRAM_ATTR apb_backup_dma_lock(void)
 {
     if (xPortInIsrContext()) {
         portENTER_CRITICAL_ISR(&s_apb_backup_dma_mutex);
@@ -21,7 +22,7 @@ static void IRAM_ATTR apb_backup_dma_lock(void)
     }
 }
 
-static void IRAM_ATTR apb_backup_dma_unlock(void)
+static void ESP_SYSTEM_IRAM_ATTR apb_backup_dma_unlock(void)
 {
     if (xPortInIsrContext()) {
         portEXIT_CRITICAL_ISR(&s_apb_backup_dma_mutex);

components/esp_system/port/soc/esp32s3/clk.c

@@ -340,7 +340,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
 }
 
 // Workaround for bootloader not calibrated well issue.
-// Placed in IRAM because disabling BBPLL may influence the cache
+// Placed in IRAM because disabling BBPLL may influence the cache.
 static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void)
 {
     rtc_cpu_freq_config_t old_config;

components/esp_system/port/soc/esp32s3/reset_reason.c

@@ -88,7 +88,7 @@ esp_reset_reason_t esp_reset_reason(void)
 #define RST_REASON_SHIFT 16
 
 /* in IRAM, can be called from panic handler */
-void IRAM_ATTR esp_reset_reason_set_hint(esp_reset_reason_t hint)
+void esp_reset_reason_set_hint(esp_reset_reason_t hint)
 {
     assert((hint & (~RST_REASON_MASK)) == 0);
     uint32_t val = hint | (hint << RST_REASON_SHIFT) | RST_REASON_BIT;

components/esp_system/port/soc/esp32s3/system_internal.c

@@ -31,7 +31,7 @@
 
 extern int _bss_end;
 
-void IRAM_ATTR esp_system_reset_modules_on_exit(void)
+void esp_system_reset_modules_on_exit(void)
 {
     // Flush any data left in UART FIFOs before reset the UART peripheral
     for (int i = 0; i < SOC_UART_HP_NUM; ++i) {
@@ -67,7 +67,7 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.
 */
-void IRAM_ATTR esp_restart_noos(void)
+void esp_restart_noos(void)
 {
     // Disable interrupts
     esp_cpu_intr_disable(0xFFFFFFFF);

components/esp_system/stack_check.c

@@ -19,11 +19,11 @@ void *__stack_chk_guard = NULL;
 static void __attribute__((constructor))
 __esp_stack_guard_setup(void)
 {
-    ESP_LOGD(TAG, "Intialize random stack guard");
+    ESP_LOGD(TAG, "Initialize random stack guard");
     __stack_chk_guard = (void *)esp_random();
 }
 
-IRAM_ATTR void __stack_chk_fail(void)
+void __stack_chk_fail(void)
 {
     esp_system_abort(DRAM_STR("Stack smashing protect failure!"));
 }

components/esp_system/startup.c

@@ -7,7 +7,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "esp_err.h"
 #include "esp_compiler.h"
 #include "esp_macros.h"
@@ -153,7 +153,7 @@ static void  esp_startup_start_app_other_cores_default(void)
 /* This function has to be in IRAM, as while it is running on CPU1, CPU0 may do some flash operations
  * (e.g. initialize the core dump), which means that cache will be disabled.
  */
-static void IRAM_ATTR start_cpu_other_cores_default(void)
+static void ESP_SYSTEM_IRAM_ATTR start_cpu_other_cores_default(void)
 {
     do_system_init_fn(ESP_SYSTEM_INIT_STAGE_SECONDARY);
 

components/esp_system/system_time.c

@@ -19,14 +19,14 @@
 
 // A component in the build should provide strong implementations that make use of
 // and actual hardware timer to provide timekeeping functions.
-int64_t IRAM_ATTR __attribute__((weak)) esp_system_get_time(void)
+int64_t __attribute__((weak)) esp_system_get_time(void)
 {
     int64_t t = 0;
     t = (esp_rtc_get_time_us() - g_startup_time);
     return t;
 }
 
-uint32_t IRAM_ATTR __attribute__((weak)) esp_system_get_time_resolution(void)
+uint32_t __attribute__((weak)) esp_system_get_time_resolution(void)
 {
     return 1000000000L / rtc_clk_slow_freq_get_hz();
 }

components/esp_system/xt_wdt.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,7 @@
 
 #include "esp_log.h"
 #include "esp_check.h"
-#include "esp_attr.h"
+#include "esp_private/esp_system_attr.h"
 #include "esp_intr_alloc.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
@@ -33,7 +33,7 @@ static void *s_callback_arg;
 
 static portMUX_TYPE s_xt_wdt_lock = portMUX_INITIALIZER_UNLOCKED;
 
-static IRAM_ATTR void rtc_xt_wdt_default_isr_handler(void *arg)
+static ESP_SYSTEM_IRAM_ATTR void rtc_xt_wdt_default_isr_handler(void *arg)
 {
     ESP_EARLY_LOGE(TAG, "XTAL32K watchdog timer got triggered");
 

tools/test_apps/configs/sdkconfig.flash_auto_suspend_iram_reduction

@@ -59,6 +59,10 @@ CONFIG_ESP_INTR_IN_IRAM=n
 CONFIG_LOG_IN_IRAM=n
 CONFIG_ESP_ROM_PRINT_IN_IRAM=n
 
+# esp_system related options
+CONFIG_ESP_PANIC_HANDLER_IRAM=n
+CONFIG_ESP_SYSTEM_IN_IRAM=n
+
 # Low power related options
 CONFIG_PM_SLEEP_FUNC_IN_IRAM=n
 CONFIG_PM_RTOS_IDLE_OPT=n