/* * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ // The long term plan is to have a single soc_caps.h for each peripheral. // During the refactoring and multichip support development process, we // seperate these information into periph_caps.h for each peripheral and // include them here. /* * These defines are parsed and imported as kconfig variables via the script * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` * * If this file is changed the script will automatically run the script * and generate the kconfig variables as part of the pre-commit hooks. * * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c6/include/soc/'` * * For more information see `tools/gen_soc_caps_kconfig/README.md` * */ #pragma once /*-------------------------- COMMON CAPS ---------------------------------------*/ // #define SOC_ADC_SUPPORTED 1 // TODO: IDF-5310 #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 #define SOC_PCNT_SUPPORTED 1 #define SOC_MCPWM_SUPPORTED 1 #define SOC_TWAI_SUPPORTED 1 #define SOC_ETM_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 #define SOC_IEEE802154_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 #define SOC_TEMP_SENSOR_SUPPORTED 1 // #define SOC_WIFI_SUPPORTED 1 // TODO: IDF-5679 #define SOC_SUPPORTS_SECURE_DL_MODE 1 //#define SOC_RISCV_COPROC_SUPPORTED 1 // TODO: IDF-5816 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_MEM_SUPPORTED 1 #define SOC_I2S_SUPPORTED 1 #define SOC_RMT_SUPPORTED 1 #define SOC_SDM_SUPPORTED 1 #define SOC_LEDC_SUPPORTED 1 #define SOC_I2C_SUPPORTED 1 #define SOC_SYSTIMER_SUPPORTED 1 #define SOC_SUPPORT_COEXISTENCE 1 // #define SOC_AES_SUPPORTED 1 // TODO: IDF-5356 // #define SOC_MPI_SUPPORTED 1 // #define SOC_SHA_SUPPORTED 1 // TODO: IDF-5353 // #define SOC_HMAC_SUPPORTED 1 // TODO: IDF-5355 // #define SOC_DIG_SIGN_SUPPORTED 1 // TODO: IDF-5360 #define SOC_ECC_SUPPORTED 1 #define SOC_FLASH_ENC_SUPPORTED 1 #define SOC_SECURE_BOOT_SUPPORTED 1 /*-------------------------- XTAL CAPS ---------------------------------------*/ #define SOC_XTAL_SUPPORT_40M 1 // TODO: IDF-5356 (Copy from esp32c3, need check) /*-------------------------- AES CAPS -----------------------------------------*/ #define SOC_AES_SUPPORT_DMA (1) /* Has a centralized DMA, which is shared with all peripherals */ #define SOC_AES_GDMA (1) #define SOC_AES_SUPPORT_AES_128 (1) #define SOC_AES_SUPPORT_AES_256 (1) // TODO: IDF-5310 (Copy from esp32c3, need check) /*-------------------------- ADC CAPS -------------------------------*/ /*!< SAR ADC Module*/ #define SOC_ADC_DIG_CTRL_SUPPORTED 1 #define SOC_ADC_ARBITER_SUPPORTED 1 #define SOC_ADC_FILTER_SUPPORTED 1 #define SOC_ADC_MONITOR_SUPPORTED 1 #define SOC_ADC_PERIPH_NUM (2) #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1) #define SOC_ADC_MAX_CHANNEL_NUM (5) #define SOC_ADC_ATTEN_NUM (4) /*!< Digital */ #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) #define SOC_ADC_PATT_LEN_MAX (8) /*!< One pattern table, each contains 8 items. Each item takes 1 byte */ #define SOC_ADC_DIGI_MAX_BITWIDTH (12) #define SOC_ADC_DIGI_FILTER_NUM (2) #define SOC_ADC_DIGI_MONITOR_NUM (2) /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */ #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 /*!< RTC */ #define SOC_ADC_RTC_MIN_BITWIDTH (12) #define SOC_ADC_RTC_MAX_BITWIDTH (12) /*!< Calibration */ #define SOC_ADC_CALIBRATION_V1_SUPPORTED (0) /*!< support HW offset calibration version 1*/ // ESP32C6-TODO: Copy from esp32c6, need check /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ #define SOC_APB_BACKUP_DMA (0) /*-------------------------- BROWNOUT CAPS -----------------------------------*/ #define SOC_BROWNOUT_RESET_SUPPORTED 1 /*-------------------------- CACHE CAPS --------------------------------------*/ #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data /*-------------------------- CPU CAPS ----------------------------------------*/ #define SOC_CPU_CORES_NUM (1U) #define SOC_CPU_INTR_NUM 32 #define SOC_CPU_HAS_FLEXIBLE_INTC 1 #define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller #define SOC_CPU_BREAKPOINTS_NUM 4 #define SOC_CPU_WATCHPOINTS_NUM 4 #define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes #define SOC_CPU_HAS_PMA 1 #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 // TODO: IDF-5339 (Copy from esp32c3, need check) /*-------------------------- MMU CAPS ----------------------------------------*/ #define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) // TODO: IDF-5360 (Copy from esp32c3, need check) /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ /** The maximum length of a Digital Signature in bits. */ #define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) /** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) /** Maximum wait time for DS parameter decryption key. If overdue, then key error. See TRM DS chapter for more details */ #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) /*-------------------------- GDMA CAPS -------------------------------------*/ #define SOC_GDMA_GROUPS (1U) // Number of GDMA groups #define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group #define SOC_GDMA_SUPPORT_ETM (1) // Support ETM submodule /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C6 has 1 GPIO peripheral #define SOC_GPIO_PORT 1U #define SOC_GPIO_PIN_COUNT 31 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 // GPIO peripheral has the ETM extension #define SOC_GPIO_SUPPORT_ETM 1 #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 // Target has the full LP IO subsystem // On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) // GPIO0~7 on ESP32C6 can support chip deep sleep wakeup #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_GPIO_VALID_GPIO_MASK ((1U<> 3) #define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) #define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) // TODO: IDF-5359 (Copy from esp32c3, need check) /*--------------------------- RSA CAPS ---------------------------------------*/ #define SOC_RSA_MAX_BIT_LEN (3072) // TODO: IDF-5353 (Copy from esp32c3, need check) /*--------------------------- SHA CAPS ---------------------------------------*/ /* Max amount of bytes in a single DMA operation is 4095, for SHA this means that the biggest safe amount of bytes is 31 blocks of 128 bytes = 3968 */ #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) #define SOC_SHA_SUPPORT_DMA (1) /* The SHA engine is able to resume hashing from a user */ #define SOC_SHA_SUPPORT_RESUME (1) /* Has a centralized DMA, which is shared with all peripherals */ #define SOC_SHA_GDMA (1) /* Supported HW algorithms */ #define SOC_SHA_SUPPORT_SHA1 (1) #define SOC_SHA_SUPPORT_SHA224 (1) #define SOC_SHA_SUPPORT_SHA256 (1) /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ #define SOC_SDM_GROUPS 1U #define SOC_SDM_CHANNELS_PER_GROUP 4 // TODO: IDF-5334 (Copy from esp32c3, need check) /*-------------------------- SPI CAPS ----------------------------------------*/ #define SOC_SPI_PERIPH_NUM 2 #define SOC_SPI_PERIPH_CS_NUM(i) 6 #define SOC_SPI_MAX_CS_NUM 6 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 #define SOC_SPI_SUPPORT_DDRCLK 1 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 #define SOC_SPI_SUPPORT_CD_SIG 1 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 // Peripheral supports DIO, DOUT, QIO, or QOUT // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) #define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_SPI_MAX_PRE_DIVIDER 16 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 // TODO: IDF-5323 (Copy from esp32c3, need check) /*-------------------------- SYSTIMER CAPS ----------------------------------*/ #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units #define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part #define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part #define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (2) #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) #define SOC_TIMER_GROUP_SUPPORT_PLL_F80M (1) #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) #define SOC_TIMER_SUPPORT_ETM (1) /*-------------------------- TWAI CAPS ---------------------------------------*/ #define SOC_TWAI_CONTROLLER_NUM 2 #define SOC_TWAI_CLK_SUPPORT_XTAL 1 #define SOC_TWAI_BRP_MIN 2 #define SOC_TWAI_BRP_MAX 32768 #define SOC_TWAI_SUPPORTS_RX_STATUS 1 // TODO: IDF-5357 (Copy from esp32c3, need check) /*-------------------------- Secure Boot CAPS----------------------------*/ #define SOC_SECURE_BOOT_V2_RSA 1 #define SOC_SECURE_BOOT_V2_ECC 1 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 // TODO: IDF-5358 (Copy from esp32c3, need check) /*-------------------------- Flash Encryption CAPS----------------------------*/ #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) #define SOC_FLASH_ENCRYPTION_XTS_AES 1 #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 /*-------------------------- MEMPROT CAPS ------------------------------------*/ // TODO: IDF-5338 (Copy from esp32c3, need check) /*-------------------------- UART CAPS ---------------------------------------*/ // ESP32-C6 has 2 UARTs #define SOC_UART_NUM (2) #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_DIV as the clock source */ #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ // #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: Test UART wakeup while supporting sleep // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) // TODO: IDF-5679 (Copy from esp32c3, need check) /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ #define SOC_COEX_HW_PTI (1) /*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) // TODO: IDF-5679 (Copy from esp32c3, need check) /*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) // TODO: IDF-5351 (Copy from esp32c3, need check) /*-------------------------- Power Management CAPS ----------------------------*/ #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) #define SOC_PM_SUPPORT_BT_WAKEUP (1) #define SOC_PM_SUPPORT_CPU_PD (1) #define SOC_PM_SUPPORT_WIFI_PD (1) #define SOC_PM_SUPPORT_BT_PD (1) /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) // TODO: IDF-5679 (Copy from esp32c3, need check) /*------------------------------------ WI-FI CAPS ------------------------------------*/ #define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */ #define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */ #define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */ #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ /*---------------------------------- Bluetooth CAPS ----------------------------------*/ #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */