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0075e2f316e627f9283c38ced996875ec07ff7a8
esp-idf/components/soc
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Mahavir Jain 0075e2f316 soc: fix trace memory region for single core mode
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2018-08-15 20:52:39 +05:30
..
esp32
soc: fix trace memory region for single core mode
2018-08-15 20:52:39 +05:30
include/soc
soc: Allow components to reserve fixed memory ranges that they need
2018-08-06 01:37:55 +00:00
src
soc: Allow components to reserve fixed memory ranges that they need
2018-08-06 01:37:55 +00:00
test
soc: add source code of rtc_clk, rtc_pm
2017-04-11 15:45:54 +08:00
component.mk
soc: Allow components to reserve fixed memory ranges that they need
2018-08-06 01:37:55 +00:00
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