mirror of
https://github.com/espressif/esp-idf.git
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1108 lines
50 KiB
C
1108 lines
50 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Clock gate Register */
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/** Type of clock_gate register
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* Clock Gating Configure Register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 0;
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* Clock enable bit of configuration registers for sigma delta modulation.
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gpio_ext_clock_gate_reg_t;
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/** Group: SDM Configure Registers */
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/** Type of sigmadelta_misc register
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* MISC Register
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*/
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typedef union {
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struct {
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/** sigmadelta_clk_en : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to enable the clock for sigma delta modulation.\\
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* 0: Not enable\\
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* 1: Enable\\%\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved.
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*/
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uint32_t sigmadelta_clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} gpio_ext_sigmadelta_misc_reg_t;
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/** Type of sigmadeltan register
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* Duty cycle configuration register for SDM channel 0
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*/
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typedef union {
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struct {
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/** sdn_in : R/W; bitpos: [7:0]; default: 0;
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* Configures the duty cycle of sigma delta modulation output. \\
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*/
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uint32_t sdn_in:8;
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/** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
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* Configures the divider value to divide IO MUX operating clock. \\
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*/
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uint32_t sdn_prescale:8;
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uint32_t reserved_16:16;
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};
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uint32_t val;
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} gpio_ext_sigmadeltan_reg_t;
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/** Group: Configure Registers */
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/** Type of pad_comp_config_0 register
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* Configuration register for zero-crossing detection
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*/
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typedef union {
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struct {
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/** xpd_comp_0 : R/W; bitpos: [0]; default: 0;
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* Configures whether to enable the function of analog PAD voltage comparator.\\
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* 0: Disable\\
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* 1: Enable\\
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*/
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uint32_t xpd_comp_0:1;
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/** mode_comp_0 : R/W; bitpos: [1]; default: 0;
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* Configures the reference voltage for analog PAD voltage comparater.. \\
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* 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
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* used as a regular GPIO\\
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* 1: Reference voltage is the voltage on the GPIO8 PAD\\
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*/
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uint32_t mode_comp_0:1;
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/** dref_comp_0 : R/W; bitpos: [4:2]; default: 0;
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* Configures the internal reference voltage for analog PAD voltage coparator. \\
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* 0: Internal reference voltage is 0 * VDDPST1\\
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* 1: Internal reference voltage is 0.1 * VDDPST1\\
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* …...\\
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* 6: Internal reference voltage is 0.6 * VDDPST1\\
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* 7: Internal reference voltage is 0.7 * VDDPST1\\
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*/
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uint32_t dref_comp_0:3;
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uint32_t reserved_5:27;
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};
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uint32_t val;
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} gpio_ext_pad_comp_config_0_reg_t;
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/** Type of pad_comp_filter_0 register
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* Configuration register for interrupt source mask period of zero-crossing detection
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*/
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typedef union {
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struct {
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/** zero_det_filter_cnt_0 : R/W; bitpos: [31:0]; default: 0;
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* Configures the period of masking new interrupt source foe analog PAD voltage
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* comparator.\\
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* Measurement unit: IO MUX operating clock cycle\\
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*/
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uint32_t zero_det_filter_cnt_0:32;
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};
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uint32_t val;
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} gpio_ext_pad_comp_filter_0_reg_t;
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/** Type of pin_ctrl register
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* Clock Output Configuration Register
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*/
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typedef union {
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struct {
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/** clk_out1 : R/W; bitpos: [4:0]; default: 0;
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* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
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* CLK_OUT_out1 can be found in peripheral output signals.
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*/
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uint32_t clk_out1:5;
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/** clk_out2 : R/W; bitpos: [9:5]; default: 0;
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* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
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* CLK_OUT_out2 can be found in peripheral output signals.
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*/
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uint32_t clk_out2:5;
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/** clk_out3 : R/W; bitpos: [14:10]; default: 0;
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* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
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* CLK_OUT_out3 can be found in peripheral output signals.
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*/
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uint32_t clk_out3:5;
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uint32_t reserved_15:17;
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};
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uint32_t val;
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} gpio_ext_pin_ctrl_reg_t;
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/** Group: Glitch filter Configure Registers */
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/** Type of glitch_filter_chn register
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* Glitch Filter Configure Register of Channeln
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*/
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typedef union {
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struct {
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/** filter_ch0_en : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to enable channel n of Glitch Filter.\\
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* 0: Not enable\\
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* 1: Enable\\
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*/
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uint32_t filter_ch0_en:1;
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/** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0;
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* Configures to select the input GPIO for Glitch Filter. \\
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* 0: Select GPIO0\\
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* 1: Select GPIO1\\
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* ......\\
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* 27: Select GPIO27\\
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* 28: Select GPIO28\\
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* 29 ~ 63: Reserved\\
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*/
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uint32_t filter_ch0_input_io_num:6;
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uint32_t reserved_7:1;
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/** filter_ch0_window_thres : R/W; bitpos: [13:8]; default: 0;
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* Configures the window threshold for Glitch Filter. The window threshold should be
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* less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.\\ %see DOC-4768\\
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* Measurement unit: IO MUX operating clock cycle\\
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*/
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uint32_t filter_ch0_window_thres:6;
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/** filter_ch0_window_width : R/W; bitpos: [19:14]; default: 0;
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* Configures the window width for Glitch Filter. The effective value of window width
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* is 0 ~ 63. \\
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* Measurement unit: IO MUX operating clock cycle\\
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*/
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uint32_t filter_ch0_window_width:6;
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uint32_t reserved_20:12;
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};
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uint32_t val;
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} gpio_ext_glitch_filter_chn_reg_t;
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/** Group: Etm Configure Registers */
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/** Type of etm_event_chn_cfg register
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* Etm Config register of Channeln
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*/
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typedef union {
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struct {
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/** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0;
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* Configures to select GPIO for ETM event channel.\\
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* 0: Select GPIO0\\
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* 1: Select GPIO1\\
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* ......\\
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* 27: Select GPIO27\\
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* 28: Select GPIO28\\
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* 29 ~ 63: Reserved\\
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*/
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uint32_t etm_ch0_event_sel:6;
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uint32_t reserved_6:1;
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/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
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* Configures whether or not to enable ETM event send.\\
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* 0: Not enable\\
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* 1: Enable\\
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*/
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uint32_t etm_ch0_event_en:1;
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uint32_t reserved_8:24;
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};
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uint32_t val;
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} gpio_ext_etm_event_chn_cfg_reg_t;
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/** Type of etm_task_p0_cfg register
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* GPIO selection register 0 for ETM
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*/
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typedef union {
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struct {
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/** etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0;
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* Configures to select an ETM task channel for GPIO$n.\\
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* 0: Select channel 0\\
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* 1: Select channel 1\\
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* ......\\
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* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
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* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
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* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
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* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
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* choose a etm task channel.
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*/
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uint32_t etm_task_gpio0_sel:3;
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uint32_t reserved_3:2;
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/** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0;
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* Configures whether or not to enable GPIO$n to response ETM task.\\
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* 0: Not enable\\
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* 1: Enable\\
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*/
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uint32_t etm_task_gpio0_en:1;
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/** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0;
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* Configures to select an ETM task channel for GPIO$n.\\
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* 0: Select channel 0\\
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* 1: Select channel 1\\
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* ......\\
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* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
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* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
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* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
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* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
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* choose a etm task channel.
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*/
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uint32_t etm_task_gpio1_sel:3;
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uint32_t reserved_9:2;
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/** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0;
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* Configures whether or not to enable GPIO$n to response ETM task.\\
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* 0: Not enable\\
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* 1: Enable\\
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*/
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uint32_t etm_task_gpio1_en:1;
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/** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0;
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* Configures to select an ETM task channel for GPIO$n.\\
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* 0: Select channel 0\\
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* 1: Select channel 1\\
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* ......\\
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* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
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* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
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* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
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* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
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* choose a etm task channel.
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*/
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uint32_t etm_task_gpio2_sel:3;
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uint32_t reserved_15:2;
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/** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0;
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* Configures whether or not to enable GPIO$n to response ETM task.\\
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* 0: Not enable\\
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* 1: Enable\\
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*/
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uint32_t etm_task_gpio2_en:1;
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/** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0;
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* Configures to select an ETM task channel for GPIO$n.\\
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* 0: Select channel 0\\
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* 1: Select channel 1\\
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* ......\\
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* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
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* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
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* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
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* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
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* choose a etm task channel.
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*/
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uint32_t etm_task_gpio3_sel:3;
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uint32_t reserved_21:2;
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/** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0;
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* Configures whether or not to enable GPIO$n to response ETM task.\\
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* 0: Not enable\\
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* 1: Enable\\
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*/
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uint32_t etm_task_gpio3_en:1;
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/** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0;
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* Configures to select an ETM task channel for GPIO$n.\\
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* 0: Select channel 0\\
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* 1: Select channel 1\\
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* ......\\
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* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
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* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
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* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
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* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
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* choose a etm task channel.
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*/
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uint32_t etm_task_gpio4_sel:3;
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uint32_t reserved_27:2;
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/** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0;
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* Configures whether or not to enable GPIO$n to response ETM task.\\
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* 0: Not enable\\
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* 1: Enable\\
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*/
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uint32_t etm_task_gpio4_en:1;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} gpio_ext_etm_task_p0_cfg_reg_t;
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/** Type of etm_task_p1_cfg register
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* GPIO selection register 1 for ETM
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*/
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typedef union {
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struct {
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/** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0;
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* Configures to select an ETM task channel for GPIO$n.\\
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* 0: Select channel 0\\
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* 1: Select channel 1\\
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* ......\\
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* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
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* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
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* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
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* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
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* choose a etm task channel.
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*/
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uint32_t etm_task_gpio5_sel:3;
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uint32_t reserved_3:2;
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/** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0;
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* Configures whether or not to enable GPIO$n to response ETM task.\\
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* 0: Not enable\\
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* 1: Enable\\
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*/
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uint32_t etm_task_gpio5_en:1;
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/** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0;
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* Configures to select an ETM task channel for GPIO$n.\\
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* 0: Select channel 0\\
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* 1: Select channel 1\\
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* ......\\
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* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
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* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
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* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
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* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
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* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
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* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
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* choose a etm task channel.
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*/
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uint32_t etm_task_gpio6_sel:3;
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uint32_t reserved_9:2;
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/** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0;
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* Configures whether or not to enable GPIO$n to response ETM task.\\
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* 0: Not enable\\
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* 1: Enable\\
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*/
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uint32_t etm_task_gpio6_en:1;
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/** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio7_sel:3;
|
|
uint32_t reserved_15:2;
|
|
/** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio7_en:1;
|
|
/** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio8_sel:3;
|
|
uint32_t reserved_21:2;
|
|
/** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio8_en:1;
|
|
/** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio9_sel:3;
|
|
uint32_t reserved_27:2;
|
|
/** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio9_en:1;
|
|
uint32_t reserved_30:2;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_etm_task_p1_cfg_reg_t;
|
|
|
|
/** Type of etm_task_p2_cfg register
|
|
* GPIO selection register 2 for ETM
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio10_sel:3;
|
|
uint32_t reserved_3:2;
|
|
/** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio10_en:1;
|
|
/** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio11_sel:3;
|
|
uint32_t reserved_9:2;
|
|
/** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio11_en:1;
|
|
/** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio12_sel:3;
|
|
uint32_t reserved_15:2;
|
|
/** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio12_en:1;
|
|
/** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio13_sel:3;
|
|
uint32_t reserved_21:2;
|
|
/** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio13_en:1;
|
|
/** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio14_sel:3;
|
|
uint32_t reserved_27:2;
|
|
/** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio14_en:1;
|
|
uint32_t reserved_30:2;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_etm_task_p2_cfg_reg_t;
|
|
|
|
/** Type of etm_task_p3_cfg register
|
|
* GPIO selection register 3 for ETM
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio15_sel:3;
|
|
uint32_t reserved_3:2;
|
|
/** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio15_en:1;
|
|
/** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio16_sel:3;
|
|
uint32_t reserved_9:2;
|
|
/** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio16_en:1;
|
|
/** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio17_sel:3;
|
|
uint32_t reserved_15:2;
|
|
/** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio17_en:1;
|
|
/** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio18_sel:3;
|
|
uint32_t reserved_21:2;
|
|
/** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio18_en:1;
|
|
/** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio19_sel:3;
|
|
uint32_t reserved_27:2;
|
|
/** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio19_en:1;
|
|
uint32_t reserved_30:2;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_etm_task_p3_cfg_reg_t;
|
|
|
|
/** Type of etm_task_p4_cfg register
|
|
* GPIO selection register 4 for ETM
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio20_sel:3;
|
|
uint32_t reserved_3:2;
|
|
/** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio20_en:1;
|
|
/** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio21_sel:3;
|
|
uint32_t reserved_9:2;
|
|
/** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio21_en:1;
|
|
/** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio22_sel:3;
|
|
uint32_t reserved_15:2;
|
|
/** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio22_en:1;
|
|
/** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio23_sel:3;
|
|
uint32_t reserved_21:2;
|
|
/** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio23_en:1;
|
|
/** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio24_sel:3;
|
|
uint32_t reserved_27:2;
|
|
/** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio24_en:1;
|
|
uint32_t reserved_30:2;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_etm_task_p4_cfg_reg_t;
|
|
|
|
/** Type of etm_task_p5_cfg register
|
|
* GPIO selection register 5 for ETM
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio25_sel:3;
|
|
uint32_t reserved_3:2;
|
|
/** etm_task_gpio25_en : R/W; bitpos: [5]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio25_en:1;
|
|
/** etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio26_sel:3;
|
|
uint32_t reserved_9:2;
|
|
/** etm_task_gpio26_en : R/W; bitpos: [11]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio26_en:1;
|
|
/** etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio27_sel:3;
|
|
uint32_t reserved_15:2;
|
|
/** etm_task_gpio27_en : R/W; bitpos: [17]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio27_en:1;
|
|
/** etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0;
|
|
* Configures to select an ETM task channel for GPIO$n.\\
|
|
* 0: Select channel 0\\
|
|
* 1: Select channel 1\\
|
|
* ......\\
|
|
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
|
|
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
|
|
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
|
|
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
|
|
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
|
|
* choose a etm task channel.
|
|
*/
|
|
uint32_t etm_task_gpio28_sel:3;
|
|
uint32_t reserved_21:2;
|
|
/** etm_task_gpio28_en : R/W; bitpos: [23]; default: 0;
|
|
* Configures whether or not to enable GPIO$n to response ETM task.\\
|
|
* 0: Not enable\\
|
|
* 1: Enable\\
|
|
*/
|
|
uint32_t etm_task_gpio28_en:1;
|
|
uint32_t reserved_24:8;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_etm_task_p5_cfg_reg_t;
|
|
|
|
|
|
/** Group: Interrupt Registers */
|
|
/** Type of int_raw register
|
|
* GPIO_EXT interrupt raw register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** comp_neg_0_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
|
* analog comparator pos edge interrupt raw
|
|
*/
|
|
uint32_t comp_neg_0_int_raw:1;
|
|
/** comp_pos_0_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
|
|
* analog comparator neg edge interrupt raw
|
|
*/
|
|
uint32_t comp_pos_0_int_raw:1;
|
|
/** comp_all_0_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
|
|
* analog comparator neg or pos edge interrupt raw
|
|
*/
|
|
uint32_t comp_all_0_int_raw:1;
|
|
uint32_t reserved_3:29;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_int_raw_reg_t;
|
|
|
|
/** Type of int_st register
|
|
* GPIO_EXT interrupt masked register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** comp_neg_0_int_st : RO; bitpos: [0]; default: 0;
|
|
* analog comparator pos edge interrupt status
|
|
*/
|
|
uint32_t comp_neg_0_int_st:1;
|
|
/** comp_pos_0_int_st : RO; bitpos: [1]; default: 0;
|
|
* analog comparator neg edge interrupt status
|
|
*/
|
|
uint32_t comp_pos_0_int_st:1;
|
|
/** comp_all_0_int_st : RO; bitpos: [2]; default: 0;
|
|
* analog comparator neg or pos edge interrupt status
|
|
*/
|
|
uint32_t comp_all_0_int_st:1;
|
|
uint32_t reserved_3:29;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_int_st_reg_t;
|
|
|
|
/** Type of int_ena register
|
|
* GPIO_EXT interrupt enable register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** comp_neg_0_int_ena : R/W; bitpos: [0]; default: 1;
|
|
* analog comparator pos edge interrupt enable
|
|
*/
|
|
uint32_t comp_neg_0_int_ena:1;
|
|
/** comp_pos_0_int_ena : R/W; bitpos: [1]; default: 1;
|
|
* analog comparator neg edge interrupt enable
|
|
*/
|
|
uint32_t comp_pos_0_int_ena:1;
|
|
/** comp_all_0_int_ena : R/W; bitpos: [2]; default: 1;
|
|
* analog comparator neg or pos edge interrupt enable
|
|
*/
|
|
uint32_t comp_all_0_int_ena:1;
|
|
uint32_t reserved_3:29;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_int_ena_reg_t;
|
|
|
|
/** Type of int_clr register
|
|
* GPIO_EXT interrupt clear register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** comp_neg_0_int_clr : WT; bitpos: [0]; default: 0;
|
|
* analog comparator pos edge interrupt clear
|
|
*/
|
|
uint32_t comp_neg_0_int_clr:1;
|
|
/** comp_pos_0_int_clr : WT; bitpos: [1]; default: 0;
|
|
* analog comparator neg edge interrupt clear
|
|
*/
|
|
uint32_t comp_pos_0_int_clr:1;
|
|
/** comp_all_0_int_clr : WT; bitpos: [2]; default: 0;
|
|
* analog comparator neg or pos edge interrupt clear
|
|
*/
|
|
uint32_t comp_all_0_int_clr:1;
|
|
uint32_t reserved_3:29;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_int_clr_reg_t;
|
|
|
|
|
|
/** Group: Version Register */
|
|
/** Type of version register
|
|
* Version Control Register
|
|
*/
|
|
typedef union {
|
|
struct {
|
|
/** date : R/W; bitpos: [27:0]; default: 36774208;
|
|
* Version control register.
|
|
*/
|
|
uint32_t date:28;
|
|
uint32_t reserved_28:4;
|
|
};
|
|
uint32_t val;
|
|
} gpio_ext_version_reg_t;
|
|
|
|
|
|
typedef struct {
|
|
volatile gpio_ext_clock_gate_reg_t clock_gate;
|
|
volatile gpio_ext_sigmadelta_misc_reg_t sigmadelta_misc;
|
|
volatile gpio_ext_sigmadeltan_reg_t sigmadeltan[4];
|
|
uint32_t reserved_018[16];
|
|
volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0;
|
|
volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0;
|
|
uint32_t reserved_060[30];
|
|
volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8];
|
|
uint32_t reserved_0f8[8];
|
|
volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
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uint32_t reserved_138[8];
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volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
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volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
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volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
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volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
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volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
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volatile gpio_ext_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
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uint32_t reserved_170[24];
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volatile gpio_ext_int_raw_reg_t int_raw;
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volatile gpio_ext_int_st_reg_t int_st;
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volatile gpio_ext_int_ena_reg_t int_ena;
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volatile gpio_ext_int_clr_reg_t int_clr;
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volatile gpio_ext_pin_ctrl_reg_t pin_ctrl;
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uint32_t reserved_1e4[6];
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volatile gpio_ext_version_reg_t version;
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} gpio_ext_dev_t;
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extern gpio_ext_dev_t GPIO_EXT;
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#ifndef __cplusplus
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_Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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