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https://github.com/espressif/esp-idf.git
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16677b0d3c
peripheral enable/disable usually should be managed by driver itself, so make it as espressif private APIs, not recommended for user to use it in application code. However, if user want to re-write the driver or ports to other platform, this is still possible by including the header in this way: "esp_private/peripheral_ctrl.h"
99 lines
3.8 KiB
C
99 lines
3.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "bootloader_random.h"
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#include "soc/rtc_periph.h"
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#include "soc/sens_periph.h"
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#include "soc/syscon_periph.h"
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#include "soc/dport_reg.h"
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#include "soc/i2s_periph.h"
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#include "esp_log.h"
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#include "soc/io_mux_reg.h"
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#include "soc/apb_saradc_reg.h"
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#include "regi2c_ctrl.h"
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#include "hal/adc_ll.h"
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#ifndef BOOTLOADER_BUILD
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#include "esp_private/periph_ctrl.h"
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#endif
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void bootloader_random_enable(void)
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{
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/* Ensure the Wifi clock for RNG modiule is enabled following a soft reset. This should always be the case already
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(this clock is never disabled while the CPU is running), this is a "belt and braces" type check.
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*/
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
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#else
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periph_module_enable(PERIPH_RNG_MODULE);
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#endif // BOOTLOADER_BUILD
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// Enable 8M clock source for RNG (this is actually enough to produce strong random results,
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// but enabling the SAR ADC as well adds some insurance.)
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
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// Enable SAR ADC to read a disconnected input for additional entropy
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SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN0_REG,DPORT_APB_SARADC_CLK_EN);
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REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
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SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
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CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
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SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 0x4);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 0x4);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
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REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR1_PATT_LEN, 0);
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WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG,0xafffffff); // set adc1 channel & bitwidth & atten
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REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR2_PATT_LEN, 0);
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WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG,0xafffffff); //set adc2 channel & bitwidth & atten
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SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG,SENS_SAR1_DIG_FORCE);
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REG_SET_FIELD(APB_SARADC_CTRL_REG,APB_SARADC_WORK_MODE, 1);
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CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_MEAS_NUM_LIMIT);
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REG_SET_FIELD(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3);
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SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_SEL);
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REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100);
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CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG,APB_SARADC_START_FORCE);
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SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_EN);
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}
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void bootloader_random_disable(void)
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{
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/* Restore internal I2C bus state */
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 0x1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 0x1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
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/* Restore SARADC to default mode */
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
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SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN0_REG, DPORT_APB_SARADC_CLK_EN);
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SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
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/* Note: the 8M CLK entropy source continues running even after this function is called,
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but as mentioned above it's better to enable Wi-Fi or BT or call bootloader_random_enable()
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in order to get a secondary entropy source.
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*/
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}
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