mirror of
https://github.com/espressif/esp-idf.git
synced 2025-11-04 00:51:42 +01:00
143 lines
4.5 KiB
C
143 lines
4.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stddef.h>
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#include <stdlib.h>
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#include "esp_err.h"
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#include "ulp_common.h"
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#include "esp_intr_alloc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ULP_RISCV_WAKEUP_SOURCE_TIMER,
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ULP_RISCV_WAKEUP_SOURCE_GPIO,
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} ulp_riscv_wakeup_source_t;
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/**
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* @brief ULP riscv init parameters
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*
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*/
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typedef struct {
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ulp_riscv_wakeup_source_t wakeup_source; /*!< ULP wakeup source */
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} ulp_riscv_cfg_t;
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#define ULP_RISCV_DEFAULT_CONFIG() \
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{ \
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.wakeup_source = ULP_RISCV_WAKEUP_SOURCE_TIMER, \
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}
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/* ULP RISC-V interrupt signals for the main CPU */
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#if (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3)
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#define ULP_RISCV_SW_INT (BIT(13)) // Corresponds to RTC_CNTL_COCPU_INT_ST_M interrupt status bit
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#define ULP_RISCV_TRAP_INT (BIT(17)) // Corresponds to RTC_CNTL_COCPU_TRAP_INT_ST_M interrupt status bit
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#else
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#error "ULP_RISCV_SW_INT and ULP_RISCV_TRAP_INT are undefined. Please check soc/rtc_cntl_reg.h for the correct bitmap on your target SoC."
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#endif /* (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3) */
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/**
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* @brief Register ULP signal ISR
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*
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* @note The ISR routine will only be active if the main CPU is not in deepsleep
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*
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* @param fn ISR callback function
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* @param arg ISR callback function arguments
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* @param mask Bit mask to enable the required ULP RISC-V interrupt signals
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* @return
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* - ESP_OK on success
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* - ESP_ERR_INVALID_ARG if callback function is NULL or if the interrupt bits are invalid
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* - ESP_ERR_NO_MEM if heap memory cannot be allocated for the interrupt
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* - other errors returned by esp_intr_alloc
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*/
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esp_err_t ulp_riscv_isr_register(intr_handler_t fn, void *arg, uint32_t mask);
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/**
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* @brief Deregister ULP signal ISR
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*
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* @param fn ISR callback function
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* @param arg ISR callback function arguments
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* @param mask Bit mask to enable the required ULP RISC-V interrupt signals
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* @return
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* - ESP_OK on success
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* - ESP_ERR_INVALID_ARG if callback function is NULL or if the interrupt bits are invalid
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* - ESP_ERR_INVALID_STATE if a handler matching both callback function and its arguments isn't registered
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*/
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esp_err_t ulp_riscv_isr_deregister(intr_handler_t fn, void *arg, uint32_t mask);
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/**
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* @brief Configure the ULP and run the program loaded into RTC memory
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*
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* @param cfg pointer to the config struct
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* @return ESP_OK on success
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*/
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esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg);
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/**
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* @brief Configure the ULP with default settings
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* and run the program loaded into RTC memory
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*
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* @return ESP_OK on success
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*/
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esp_err_t ulp_riscv_run(void);
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/**
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* @brief Load ULP-RISC-V program binary into RTC memory
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*
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* Different than ULP FSM, the binary program has no special format, it is the ELF
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* file generated by RISC-V toolchain converted to binary format using objcopy.
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*
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* Linker script in components/ulp/ld/ulp_riscv.ld produces ELF files which
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* correspond to this format. This linker script produces binaries with load_addr == 0.
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*
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* @param program_binary pointer to program binary
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* @param program_size_bytes size of the program binary
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* @return
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* - ESP_OK on success
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* - ESP_ERR_INVALID_SIZE if program_size_bytes is more than 8KiB
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*/
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esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes);
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/**
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* @brief Stop the ULP timer
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*
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* @note This will stop the ULP from waking up if halted, but will not abort any program
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* currently executing on the ULP.
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*/
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void ulp_riscv_timer_stop(void);
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/**
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* @brief Resumes the ULP timer
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*
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* @note This will resume an already configured timer, but does no other configuration
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*
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*/
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void ulp_riscv_timer_resume(void);
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/**
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* @brief Halts the program currently running on the ULP-RISC-V
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*
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* @note Program will restart at the next ULP timer trigger if timer is still running.
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* If you want to stop the ULP from waking up then call ulp_riscv_timer_stop() first.
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*/
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void ulp_riscv_halt(void);
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/**
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* @brief Resets the ULP-RISC-V core from the main CPU
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*
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* @note This will reset the ULP core from the main CPU. It is intended to be used when the
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* ULP is in a bad state and cannot run as intended due to a corrupt firmware or any other reason.
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* The main core can reset the ULP core with this API and then re-initilialize the ULP.
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*/
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void ulp_riscv_reset(void);
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#ifdef __cplusplus
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}
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#endif
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