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https://github.com/espressif/esp-idf.git
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115 lines
3.2 KiB
C
115 lines
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <sys/param.h>
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "hal/assert.h"
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#include "hal/cache_hal.h"
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#include "hal/cache_types.h"
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#include "hal/cache_ll.h"
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#include "soc/soc_caps.h"
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C2
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#include "esp32c2/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32H4
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#include "esp32h4/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32C6
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#include "esp32c6/rom/cache.h"
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#elif CONFIG_IDF_TARGET_ESP32H2
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#include "esp32h2/rom/cache.h"
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#endif
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/*------------------------------------------------------------------------------
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* Unified Cache Control
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* See cache_hal.h for more info about these HAL APIs
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* This file is in internal RAM.
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* Now this file doesn't compile on ESP32
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*----------------------------------------------------------------------------*/
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/**
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* To know if autoload is enabled or not.
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*
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* We should have a unified flag for this aim, then we don't need to call following 2 functions
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* to know the flag.
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*
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* Suggest ROM keeping this flag value to BIT(2). Then we can replace following lines to:
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* #define DATA_AUTOLOAD_FLAG BIT(2)
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* #define INST_AUTOLOAD_FLAG BIT(2)
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*/
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#define DATA_AUTOLOAD_FLAG Cache_Disable_DCache()
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#define INST_AUTOLOAD_FLAG Cache_Disable_ICache()
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/**
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* Necessary hal contexts, could be maintained by upper layer in the future
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*/
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typedef struct {
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uint32_t data_autoload_flag;
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uint32_t inst_autoload_flag;
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} cache_hal_context_t;
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static cache_hal_context_t ctx;
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void cache_hal_init(void)
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{
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#if SOC_SHARED_IDCACHE_SUPPORTED
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ctx.data_autoload_flag = INST_AUTOLOAD_FLAG;
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Cache_Enable_ICache(ctx.data_autoload_flag);
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#else
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ctx.data_autoload_flag = DATA_AUTOLOAD_FLAG;
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Cache_Enable_DCache(ctx.data_autoload_flag);
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ctx.inst_autoload_flag = INST_AUTOLOAD_FLAG;
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Cache_Enable_ICache(ctx.inst_autoload_flag);
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#endif
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cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_DBUS_MASK);
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cache_ll_l1_enable_bus(0, CACHE_LL_DEFAULT_IBUS_MASK);
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#if !CONFIG_FREERTOS_UNICORE
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cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_DBUS_MASK);
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cache_ll_l1_enable_bus(1, CACHE_LL_DEFAULT_IBUS_MASK);
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#endif
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}
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void cache_hal_disable(cache_type_t type)
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{
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#if SOC_SHARED_IDCACHE_SUPPORTED
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Cache_Disable_ICache();
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#else
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if (type == CACHE_TYPE_DATA) {
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Cache_Disable_DCache();
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} else if (type == CACHE_TYPE_INSTRUCTION) {
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Cache_Disable_ICache();
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} else {
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Cache_Disable_ICache();
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Cache_Disable_DCache();
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}
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#endif
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}
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void cache_hal_enable(cache_type_t type)
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{
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#if SOC_SHARED_IDCACHE_SUPPORTED
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Cache_Enable_ICache(ctx.inst_autoload_flag);
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#else
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if (type == CACHE_TYPE_DATA) {
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Cache_Enable_DCache(ctx.data_autoload_flag);
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} else if (type == CACHE_TYPE_INSTRUCTION) {
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Cache_Enable_ICache(ctx.inst_autoload_flag);
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} else {
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Cache_Enable_ICache(ctx.inst_autoload_flag);
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Cache_Enable_DCache(ctx.data_autoload_flag);
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}
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#endif
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}
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