mirror of
https://github.com/espressif/esp-idf.git
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106 lines
3.7 KiB
C
106 lines
3.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ROM_SPI_FLASH_H_
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#define _ROM_SPI_FLASH_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
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#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
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#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
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#define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1)
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#define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1)
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#define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
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#define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1)
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#define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1)
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#define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1)
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#define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1)
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#define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1)
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#define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1)
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#define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1)
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#define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1)
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#define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1)
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#define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1)
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#define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1)
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#define SPI0_R_QIO_DUMMY_CYCLELEN 5
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#define SPI0_R_QIO_ADDR_BITSLEN 23
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#define SPI0_R_FAST_DUMMY_CYCLELEN 7
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#define SPI0_R_DIO_DUMMY_CYCLELEN 3
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#define SPI0_R_FAST_ADDR_BITSLEN 23
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#define SPI0_R_SIO_ADDR_BITSLEN 23
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#define SPI1_R_QIO_DUMMY_CYCLELEN 5
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#define SPI1_R_QIO_ADDR_BITSLEN 23
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#define SPI1_R_FAST_DUMMY_CYCLELEN 7
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#define SPI1_R_DIO_DUMMY_CYCLELEN 3
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#define SPI1_R_DIO_ADDR_BITSLEN 23
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#define SPI1_R_FAST_ADDR_BITSLEN 23
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#define SPI1_R_SIO_ADDR_BITSLEN 23
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#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
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#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B
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//SPI address register
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#define ESP_ROM_SPIFLASH_BYTES_LEN 24
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#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
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#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
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#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
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//SPI status register
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#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
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#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
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#define ESP_ROM_SPIFLASH_BP0 BIT2
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#define ESP_ROM_SPIFLASH_BP1 BIT3
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#define ESP_ROM_SPIFLASH_BP2 BIT4
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#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
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#define ESP_ROM_SPIFLASH_QE BIT9
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#define FLASH_ID_GD25LQ32C 0xC86016
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typedef enum {
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SPI_FLASH_RESULT_OK,
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SPI_FLASH_RESULT_ERR,
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SPI_FLASH_RESULT_TIMEOUT
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} SpiFlashOpResult;
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typedef void (* spi_flash_func_t)(void);
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typedef SpiFlashOpResult (* spi_flash_op_t)(void);
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typedef SpiFlashOpResult (* spi_flash_erase_t)(uint32_t);
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typedef SpiFlashOpResult (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
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typedef SpiFlashOpResult (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
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typedef SpiFlashOpResult (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
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typedef SpiFlashOpResult (* spi_flash_wren_t)(void*);
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typedef struct {
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uint32_t read_sub_len;
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uint32_t write_sub_len;
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spi_flash_op_t unlock;
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spi_flash_erase_t erase_sector;
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spi_flash_erase_t erase_block;
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spi_flash_rd_t read;
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spi_flash_wr_t write;
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spi_flash_ewr_t encrypt_write;
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spi_flash_func_t check_sus;
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spi_flash_wren_t wren;
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spi_flash_op_t wait_idle;
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} spiflash_legacy_funcs_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_SPI_FLASH_H_ */
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