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173 lines
9.2 KiB
C
173 lines
9.2 KiB
C
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef BOOTLOADER_BUILD
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#include <stdlib.h>
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/soc_memory_layout.h"
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#include "esp_heap_caps.h"
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#include "sdkconfig.h"
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/* Memory layout for ESP32 SoC */
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/*
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Memory type descriptors. These describe the capabilities of a type of memory in the SoC. Each type of memory
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map consist of one or more regions in the address space.
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Each type contains an array of prioritised capabilities; types with later entries are only taken if earlier
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ones can't fulfill the memory request.
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The prioritised capabilities work roughly like this:
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- For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions,
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finally eat into the application memory.
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- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
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- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
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- Most other malloc caps only fit in one region anyway.
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*/
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const soc_memory_type_desc_t soc_memory_types[] = {
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//Type 0: Plain ole D-port RAM
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{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false},
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//Type 1: Plain ole D-port RAM which has an alias on the I-port
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//(This DRAM is also the region used by ROM during startup)
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{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true},
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//Type 2: IRAM
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{ "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
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//Type 3-8: PID 2-7 IRAM
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{ "PID2IRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false},
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{ "PID3IRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false},
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{ "PID4IRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false},
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{ "PID5IRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false},
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{ "PID6IRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false},
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{ "PID7IRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, 0, MALLOC_CAP_EXEC|MALLOC_CAP_32BIT }, false, false},
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//Type 9-14: PID 2-7 DRAM
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{ "PID2DRAM", { MALLOC_CAP_PID2|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID3DRAM", { MALLOC_CAP_PID3|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID4DRAM", { MALLOC_CAP_PID4|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID5DRAM", { MALLOC_CAP_PID5|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID6DRAM", { MALLOC_CAP_PID6|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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{ "PID7DRAM", { MALLOC_CAP_PID7|MALLOC_CAP_INTERNAL, MALLOC_CAP_8BIT, MALLOC_CAP_32BIT|MALLOC_CAP_DEFAULT }, false, false},
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//Type 15: SPI SRAM data
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{ "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
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};
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const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
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/*
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Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
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Because of requirements in the coalescing code which merges adjacent regions, this list should always be sorted
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from low to high start address.
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*/
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const soc_memory_region_t soc_memory_regions[] = {
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{ 0x3F800000, 0x400000, 15, 0}, //SPI SRAM, if available
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{ 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
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{ 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
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{ 0x3FFB8000, 0x8000, 0, 0}, //pool 14 <- if BT is enabled, used data memory for BT ROM functions.
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{ 0x3FFC0000, 0x2000, 0, 0}, //pool 10-13, mmu page 0
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{ 0x3FFC2000, 0x2000, 0, 0}, //pool 10-13, mmu page 1
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{ 0x3FFC4000, 0x2000, 0, 0}, //pool 10-13, mmu page 2
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{ 0x3FFC6000, 0x2000, 0, 0}, //pool 10-13, mmu page 3
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{ 0x3FFC8000, 0x2000, 0, 0}, //pool 10-13, mmu page 4
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{ 0x3FFCA000, 0x2000, 0, 0}, //pool 10-13, mmu page 5
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{ 0x3FFCC000, 0x2000, 0, 0}, //pool 10-13, mmu page 6
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{ 0x3FFCE000, 0x2000, 0, 0}, //pool 10-13, mmu page 7
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{ 0x3FFD0000, 0x2000, 0, 0}, //pool 10-13, mmu page 8
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{ 0x3FFD2000, 0x2000, 0, 0}, //pool 10-13, mmu page 9
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{ 0x3FFD4000, 0x2000, 0, 0}, //pool 10-13, mmu page 10
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{ 0x3FFD6000, 0x2000, 0, 0}, //pool 10-13, mmu page 11
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{ 0x3FFD8000, 0x2000, 0, 0}, //pool 10-13, mmu page 12
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{ 0x3FFDA000, 0x2000, 0, 0}, //pool 10-13, mmu page 13
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{ 0x3FFDC000, 0x2000, 0, 0}, //pool 10-13, mmu page 14
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{ 0x3FFDE000, 0x2000, 0, 0}, //pool 10-13, mmu page 15
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{ 0x3FFE0000, 0x4000, 1, 0x400BC000}, //pool 9 blk 1
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{ 0x3FFE4000, 0x4000, 1, 0x400B8000}, //pool 9 blk 0
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{ 0x3FFE8000, 0x8000, 1, 0x400B0000}, //pool 8 <- can be remapped to ROM, used for MAC dump
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{ 0x3FFF0000, 0x8000, 1, 0x400A8000}, //pool 7 <- can be used for MAC dump
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{ 0x3FFF8000, 0x4000, 1, 0x400A4000}, //pool 6 blk 1 <- can be used as trace memory
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{ 0x3FFFC000, 0x4000, 1, 0x400A0000}, //pool 6 blk 0 <- can be used as trace memory
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{ 0x40070000, 0x8000, 2, 0}, //pool 0
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{ 0x40078000, 0x8000, 2, 0}, //pool 1
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{ 0x40080000, 0x2000, 2, 0}, //pool 2-5, mmu page 0
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{ 0x40082000, 0x2000, 2, 0}, //pool 2-5, mmu page 1
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{ 0x40084000, 0x2000, 2, 0}, //pool 2-5, mmu page 2
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{ 0x40086000, 0x2000, 2, 0}, //pool 2-5, mmu page 3
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{ 0x40088000, 0x2000, 2, 0}, //pool 2-5, mmu page 4
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{ 0x4008A000, 0x2000, 2, 0}, //pool 2-5, mmu page 5
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{ 0x4008C000, 0x2000, 2, 0}, //pool 2-5, mmu page 6
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{ 0x4008E000, 0x2000, 2, 0}, //pool 2-5, mmu page 7
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{ 0x40090000, 0x2000, 2, 0}, //pool 2-5, mmu page 8
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{ 0x40092000, 0x2000, 2, 0}, //pool 2-5, mmu page 9
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{ 0x40094000, 0x2000, 2, 0}, //pool 2-5, mmu page 10
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{ 0x40096000, 0x2000, 2, 0}, //pool 2-5, mmu page 11
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{ 0x40098000, 0x2000, 2, 0}, //pool 2-5, mmu page 12
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{ 0x4009A000, 0x2000, 2, 0}, //pool 2-5, mmu page 13
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{ 0x4009C000, 0x2000, 2, 0}, //pool 2-5, mmu page 14
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{ 0x4009E000, 0x2000, 2, 0}, //pool 2-5, mmu page 15
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};
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const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_memory_region_t);
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/* Reserved memory regions
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These are removed from the soc_memory_regions array when heaps are created.
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*/
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const soc_reserved_region_t soc_reserved_regions[] = {
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{ 0x40070000, 0x40078000 }, //CPU0 cache region
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{ 0x40078000, 0x40080000 }, //CPU1 cache region
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/* Warning: The ROM stack is located in the 0x3ffe0000 area. We do not specifically disable that area here because
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after the scheduler has started, the ROM stack is not used anymore by anything. We handle it instead by not allowing
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any mallocs memory regions with the startup_stack flag set (these are the IRAM/DRAM region) until the
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scheduler has started.
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The 0x3ffe0000 region also contains static RAM for various ROM functions. The following lines
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reserve the regions for UART and ETSC, so these functions are usable. Libraries like xtos, which are
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not usable in FreeRTOS anyway, are commented out in the linker script so they cannot be used; we
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do not disable their memory regions here and they will be used as general purpose heap memory.
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Enabling the heap allocator for this region but disabling allocation here until FreeRTOS is started up
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is a somewhat risky action in theory, because on initializing the allocator, the multi_heap implementation
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will go and write metadata at the start and end of all regions. For the ESP32, these linked
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list entries happen to end up in a region that is not touched by the stack; they can be placed safely there.
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*/
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{ 0x3ffe0000, 0x3ffe0440 }, //Reserve ROM PRO data region
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{ 0x3ffe4000, 0x3ffe4350 }, //Reserve ROM APP data region
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#if CONFIG_BT_ENABLED
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{ 0x3ffb0000, 0x3ffc0000 }, //Reserve BT hardware shared memory & BT data region
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{ 0x3ffae000, 0x3ffaff10 }, //Reserve ROM data region, inc region needed for BT ROM routines
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#else
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{ 0x3ffae000, 0x3ffae6e0 }, //Reserve ROM data region
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#endif
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#if CONFIG_MEMMAP_TRACEMEM
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#if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
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{ 0x3fff8000, 0x40000000 }, //Reserve trace mem region
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#else
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{ 0x3fff8000, 0x3fffc000 }, //Reserve trace mem region
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#endif
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#endif
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{ 0x3f800000, 0x3fC00000 }, //SPI RAM gets added later if needed, in spiram.c; reserve it for now
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};
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const size_t soc_reserved_region_count = sizeof(soc_reserved_regions)/sizeof(soc_reserved_region_t);
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#endif
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