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301dacfb33
Configurable option to use IRAM as byte accessible memory (in single core mode) using load-store (non-word aligned and non-word size IRAM access specific) exception handlers. This allows to use IRAM for use-cases where certain performance penalty (upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration option has been provided to redirect mbedTLS specific in-out content length buffers to IRAM (in single core mode), allows to save 20KB per TLS connection.
19 lines
523 B
Makefile
19 lines
523 B
Makefile
#
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# Component Makefile
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#
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ifdef CONFIG_FREERTOS_DEBUG_OCDAWARE
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COMPONENT_ADD_LDFLAGS += -Wl,--undefined=uxTopUsedPriority
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endif
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COMPONENT_ADD_INCLUDEDIRS := include xtensa/include
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COMPONENT_PRIV_INCLUDEDIRS := include/freertos xtensa/include/freertos xtensa .
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COMPONENT_SRCDIRS += xtensa
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ifndef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
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COMPONENT_OBJEXCLUDE := xtensa/xtensa_loadstore_handler.o
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endif
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tasks.o event_groups.o timers.o queue.o: CFLAGS += -D_ESP_FREERTOS_INTERNAL
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COMPONENT_ADD_LDFRAGMENTS += linker.lf
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