Omar Chebib 5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer ...

G0 doesn't depend on any G1+ layer for RISC-V based targets

2022-06-14 15:00:53 +08:00

..

include/hal

G0: RISC-V targets have now an independent G0 layer

2022-06-14 15:00:53 +08:00

adc_hal.c

adc: support adc dma driver on all chips

2021-12-16 00:19:15 +00:00

brownout_hal.c

G0: RISC-V targets have now an independent G0 layer

2022-06-14 15:00:53 +08:00

efuse_hal.c

soc: Fix description of efuse fail bits

2022-05-31 11:21:24 +00:00

hmac_hal.c

hal: Add initial ESP32-C3 support

2020-11-30 15:23:15 +11:00

rtc_cntl_hal.c

light sleep: add cpu power down support for esp32s3

2021-08-27 11:11:06 +08:00