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89 lines
2.3 KiB
C
89 lines
2.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include <sys/param.h>
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#include "soc/soc_caps.h"
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#include "hal/assert.h"
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#include "hal/efuse_hal.h"
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#include "hal/efuse_ll.h"
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#include "hal/clk_tree_ll.h"
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#include "esp_attr.h"
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#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
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IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
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{
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return efuse_ll_get_chip_wafer_version_major();
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}
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IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
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{
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return efuse_ll_get_chip_wafer_version_minor();
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}
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/******************* eFuse control functions *************************/
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void efuse_hal_set_timing(uint32_t apb_freq_hz)
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{
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(void) apb_freq_hz;
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efuse_ll_set_pwr_off_num(0x190);
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int xtal = clk_ll_xtal_load_freq_mhz();
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HAL_ASSERT(xtal == 40 || xtal == 26);
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// for the XTAL = 40 MHz we use the default value = 200.
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// XTAL = 26 MHz the value = 130.
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efuse_ll_set_tpgm_inactive(xtal * 5);
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}
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void efuse_hal_read(void)
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{
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efuse_hal_set_timing(0);
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efuse_ll_set_conf_read_op_code();
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efuse_ll_set_read_cmd();
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while (efuse_ll_get_read_cmd() != 0) { }
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/*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
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while (efuse_ll_get_read_cmd() != 0) { }
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}
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void efuse_hal_clear_program_registers(void)
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{
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ets_efuse_clear_program_registers();
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}
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void efuse_hal_program(uint32_t block)
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{
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efuse_hal_set_timing(0);
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efuse_ll_set_conf_write_op_code();
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efuse_ll_set_pgm_cmd(block);
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while (efuse_ll_get_pgm_cmd() != 0) { }
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efuse_hal_clear_program_registers();
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efuse_hal_read();
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}
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void efuse_hal_rs_calculate(const void *data, void *rs_values)
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{
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ets_efuse_rs_calculate(data, rs_values);
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}
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/******************* eFuse control functions *************************/
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bool efuse_hal_is_coding_error_in_block(unsigned block)
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{
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if (block == 0) {
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return REG_READ(EFUSE_RD_REPEAT_ERR_REG) != 0;
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} else if (block <= 3) {
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// EFUSE_RD_RS_ERR_REG: (hi) ----, ----, ----, ----, ----, BLOCK3, BLOCK2, BLOCK1 (low)
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uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR_REG);
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return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block - 1) != 0;
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}
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return false;
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}
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