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119 lines
3.6 KiB
C
119 lines
3.6 KiB
C
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include "freertos/portmacro.h"
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#include "esp_freertos_hooks.h"
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#include "soc/soc_caps.h"
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#include "hal/cpu_hal.h"
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#include "esp_rom_sys.h"
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#if CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/clk.h"
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#endif
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typedef enum {
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PERF_TIMER_UNINIT = 0, // timer has not been initialized yet
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PERF_TIMER_IDLE, // timer has been initialized but is not tracking elapsed time
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PERF_TIMER_ACTIVE // timer is tracking elapsed time
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} ccomp_timer_state_t;
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typedef struct {
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uint32_t last_ccount; // last CCOUNT value, updated every os tick
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ccomp_timer_state_t state; // state of the timer
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int64_t ccount; // accumulated processors cycles during the time when timer is active
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} ccomp_timer_status_t;
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// Each core has its independent timer
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ccomp_timer_status_t s_status[SOC_CPU_CORES_NUM];
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static portMUX_TYPE s_lock = portMUX_INITIALIZER_UNLOCKED;
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static void IRAM_ATTR update_ccount(void)
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{
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if (s_status[cpu_hal_get_core_id()].state == PERF_TIMER_ACTIVE) {
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int64_t new_ccount = cpu_hal_get_cycle_count();
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if (new_ccount > s_status[cpu_hal_get_core_id()].last_ccount) {
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s_status[cpu_hal_get_core_id()].ccount += new_ccount - s_status[cpu_hal_get_core_id()].last_ccount;
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} else {
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// CCOUNT has wrapped around
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s_status[cpu_hal_get_core_id()].ccount += new_ccount + (UINT32_MAX - s_status[cpu_hal_get_core_id()].last_ccount);
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}
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s_status[cpu_hal_get_core_id()].last_ccount = new_ccount;
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}
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}
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esp_err_t ccomp_timer_impl_init(void)
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{
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s_status[cpu_hal_get_core_id()].state = PERF_TIMER_IDLE;
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return ESP_OK;
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}
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esp_err_t ccomp_timer_impl_deinit(void)
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{
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s_status[cpu_hal_get_core_id()].state = PERF_TIMER_UNINIT;
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return ESP_OK;
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}
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esp_err_t ccomp_timer_impl_start(void)
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{
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s_status[cpu_hal_get_core_id()].state = PERF_TIMER_ACTIVE;
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s_status[cpu_hal_get_core_id()].last_ccount = cpu_hal_get_cycle_count();
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// Update elapsed cycles every OS tick
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esp_register_freertos_tick_hook_for_cpu(update_ccount, cpu_hal_get_core_id());
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return ESP_OK;
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}
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esp_err_t IRAM_ATTR ccomp_timer_impl_stop(void)
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{
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esp_deregister_freertos_tick_hook_for_cpu(update_ccount, cpu_hal_get_core_id());
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update_ccount();
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s_status[cpu_hal_get_core_id()].state = PERF_TIMER_IDLE;
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return ESP_OK;
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}
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int64_t IRAM_ATTR ccomp_timer_impl_get_time(void)
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{
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update_ccount();
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int64_t cycles = s_status[cpu_hal_get_core_id()].ccount;
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return (cycles * 1000000) / esp_clk_cpu_freq();
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}
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esp_err_t ccomp_timer_impl_reset(void)
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{
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s_status[cpu_hal_get_core_id()].ccount = 0;
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s_status[cpu_hal_get_core_id()].last_ccount = 0;
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return ESP_OK;
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}
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bool ccomp_timer_impl_is_init(void)
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{
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return s_status[cpu_hal_get_core_id()].state != PERF_TIMER_UNINIT;
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}
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bool IRAM_ATTR ccomp_timer_impl_is_active(void)
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{
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return s_status[cpu_hal_get_core_id()].state == PERF_TIMER_ACTIVE;
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}
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void IRAM_ATTR ccomp_timer_impl_lock(void)
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{
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portENTER_CRITICAL(&s_lock);
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}
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void IRAM_ATTR ccomp_timer_impl_unlock(void)
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{
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portEXIT_CRITICAL(&s_lock);
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}
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