Marius Vikhammer 7b5bdcf077 ulp-riscv: always force COCPU clock on S3 ...

The coprocessor cpu trap signal doesnt have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU

2022-10-18 03:06:05 +00:00

..

cmake

tools: cmake: check tool supported version with idf_tools.py

2022-10-03 19:01:32 +04:00

ld

ulp: Added support for RTC I2C driver for ULP RISC-V on esp32s2 and esp32s3

2022-09-05 10:21:43 +02:00

test_apps

ulp: add all 'ignore' tests to pytest framework

2022-10-06 12:58:11 +02:00

ulp_common

ulp-fsm: Update ulp-fsm ADC example with S3 support

2022-09-07 16:48:06 +08:00

ulp_fsm

ulp: remove ESP32 ULP TSENS references

2022-07-05 17:37:13 +08:00

ulp_riscv

ulp-riscv: always force COCPU clock on S3

2022-10-18 03:06:05 +00:00

.build-test-rules.yml

ci: Modify build-test-rules.yml enable' to disable` to exclude preview targets

2022-09-01 12:38:00 +08:00

CMakeLists.txt

ulp-fsm: Update ulp-fsm ADC example with S3 support

2022-09-07 16:48:06 +08:00

component_ulp_common.cmake

ulp: use quotes when specifying files for embedding ulp binaries

2020-02-18 00:12:56 +00:00

esp32ulp_mapgen.py

ulp: esp32ulp_mapgen: remove the special case for RISC-V, cleanup

2022-08-30 02:34:28 +02:00

Kconfig

Add ULP-RISCV print and bitbanged UART tx API

2022-07-29 12:18:01 +08:00

project_include.cmake

ulp-riscv: add support for using ADC as well as an example show-casing it.

2022-07-11 09:31:22 +08:00

sdkconfig.rename.esp32

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00

sdkconfig.rename.esp32s2

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00