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78c67d2384
Add support of gpio for esp32s3(728). Adjust some pins and comments in test_gpio.c. Add support for gpio functions for gpio19 and gpio20. Update S3 programming guide Peripheral API: gpio and sigmadelta. Add unit test for input and output function of S3 USB pins(GPIO19 and GPIO20) and C3 USB pins(GPIO18 and GPIO19). Adjust input only test in test_spi_master.c.
119 lines
2.2 KiB
C
119 lines
2.2 KiB
C
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "soc/gpio_periph.h"
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const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
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IO_MUX_GPIO0_REG,
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IO_MUX_GPIO1_REG,
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IO_MUX_GPIO2_REG,
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IO_MUX_GPIO3_REG,
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IO_MUX_GPIO4_REG,
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IO_MUX_GPIO5_REG,
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IO_MUX_GPIO6_REG,
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IO_MUX_GPIO7_REG,
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IO_MUX_GPIO8_REG,
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IO_MUX_GPIO9_REG,
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IO_MUX_GPIO10_REG,
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IO_MUX_GPIO11_REG,
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IO_MUX_GPIO12_REG,
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IO_MUX_GPIO13_REG,
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IO_MUX_GPIO14_REG,
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IO_MUX_GPIO15_REG,
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IO_MUX_GPIO16_REG,
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IO_MUX_GPIO17_REG,
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IO_MUX_GPIO18_REG,
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IO_MUX_GPIO19_REG,
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IO_MUX_GPIO20_REG,
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IO_MUX_GPIO21_REG,
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0,
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0,
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0,
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0,
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IO_MUX_GPIO26_REG,
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IO_MUX_GPIO27_REG,
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IO_MUX_GPIO28_REG,
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IO_MUX_GPIO29_REG,
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IO_MUX_GPIO30_REG,
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IO_MUX_GPIO31_REG,
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IO_MUX_GPIO32_REG,
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IO_MUX_GPIO33_REG,
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IO_MUX_GPIO34_REG,
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IO_MUX_GPIO35_REG,
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IO_MUX_GPIO36_REG,
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IO_MUX_GPIO37_REG,
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IO_MUX_GPIO38_REG,
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IO_MUX_GPIO39_REG,
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IO_MUX_GPIO40_REG,
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IO_MUX_GPIO41_REG,
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IO_MUX_GPIO42_REG,
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IO_MUX_GPIO43_REG,
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IO_MUX_GPIO44_REG,
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IO_MUX_GPIO45_REG,
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IO_MUX_GPIO46_REG,
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IO_MUX_GPIO47_REG,
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IO_MUX_GPIO48_REG,
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};
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const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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BIT(1),
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BIT(2),
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BIT(3),
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BIT(4),
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BIT(5),
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BIT(6),
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BIT(7),
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BIT(8),
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BIT(9),
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BIT(10),
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BIT(11),
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BIT(12),
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BIT(13),
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BIT(14),
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BIT(15),
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BIT(16),
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BIT(17),
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BIT(18),
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BIT(19),
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BIT(20),
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BIT(21),
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BIT(22),
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BIT(23),
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BIT(24),
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BIT(25),
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BIT(26),
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};
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