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74 lines
2.0 KiB
C
74 lines
2.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/soc_caps.h"
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#define ESP_ROM_EFUSE_FLASH_DEFAULT_SPI (0)
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#define ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI (1)
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/**
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* @brief A CRC8 algorithm used for MAC addresses stored in eFuse
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*
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* @param data Pointer to the original data
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* @param len Data length in byte
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* @return uint8_t CRC value
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*/
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uint8_t esp_rom_efuse_mac_address_crc8(const uint8_t *data, uint32_t len);
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/**
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* @brief Get SPI Flash GPIO pin configurations from eFuse
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*
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* @return uint32_t
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* - 0: default SPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_SPI)
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* - 1: default HSPI pins (ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI)
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* - Others: Customized pin configuration mask. Pins are encoded as per the
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* EFUSE_SPICONFIG_RET_SPICLK, EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID,
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* EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
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*
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* @note WP pin (for quad I/O modes) is not saved in eFuse and not returned by this function.
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*/
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uint32_t esp_rom_efuse_get_flash_gpio_info(void);
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/**
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* @brief Get SPI Flash WP pin information from eFuse
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*
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* @return uint32_t
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* - 0x3F: invalid GPIO number
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* - 0~46: valid GPIO number
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*/
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uint32_t esp_rom_efuse_get_flash_wp_gpio(void);
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#if SOC_SPI_MEM_SUPPORT_OPI_MODE
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/**
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* @brief Read opi flash pads configuration from Efuse
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*
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* @return
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* - 0 for default SPI pins.
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* - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for:
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* DQS, D4, D5, D6, D7 accordingly.
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*/
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uint32_t esp_rom_efuse_get_opiconfig(void);
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#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
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/**
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* @brief Read eFuse to check whether secure boot has been enabled or not
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*
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* @return true if secure boot is enabled, otherwise false
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*/
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bool esp_rom_efuse_is_secure_boot_enabled(void);
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#ifdef __cplusplus
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}
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#endif
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