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https://github.com/espressif/esp-idf.git
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26a3cb93c7
1. move dport access header files to soc 2. reduce dport register write protection. Only protect read operation
100 lines
3.7 KiB
C
100 lines
3.7 KiB
C
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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The cache has an interrupt that can be raised as soon as an access to a cached
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region (flash, psram) is done without the cache being enabled. We use that here
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to panic the CPU, which from a debugging perspective is better than grabbing bad
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data from the bus.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include "freertos/FreeRTOS.h"
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#include "esp_err.h"
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#include "esp_intr.h"
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#include "esp_attr.h"
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#include "soc/dport_reg.h"
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#include "sdkconfig.h"
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void esp_cache_err_int_init()
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{
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uint32_t core_id = xPortGetCoreID();
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ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
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// We do not register a handler for the interrupt because it is interrupt
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// level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
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// a call to the panic handler for
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// this interrupt.
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intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
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// Enable invalid cache access interrupt when the cache is disabled.
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// When the interrupt happens, we can not determine the CPU where the
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// invalid cache access has occurred. We enable the interrupt to catch
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// invalid access on both CPUs, but the interrupt is connected to the
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// CPU which happens to call this function.
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// For this reason, panic handler backtrace will not be correct if the
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// interrupt is connected to PRO CPU and invalid access happens on the APP
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// CPU.
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if (core_id == PRO_CPU_NUM) {
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DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG,
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DPORT_CACHE_IA_INT_PRO_OPPOSITE |
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DPORT_CACHE_IA_INT_PRO_DRAM1 |
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DPORT_CACHE_IA_INT_PRO_DROM0 |
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DPORT_CACHE_IA_INT_PRO_IROM0 |
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DPORT_CACHE_IA_INT_PRO_IRAM0 |
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DPORT_CACHE_IA_INT_PRO_IRAM1);
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} else {
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DPORT_SET_PERI_REG_MASK(DPORT_CACHE_IA_INT_EN_REG,
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DPORT_CACHE_IA_INT_APP_OPPOSITE |
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DPORT_CACHE_IA_INT_APP_DRAM1 |
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DPORT_CACHE_IA_INT_APP_DROM0 |
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DPORT_CACHE_IA_INT_APP_IROM0 |
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DPORT_CACHE_IA_INT_APP_IRAM0 |
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DPORT_CACHE_IA_INT_APP_IRAM1);
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}
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ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
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}
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int IRAM_ATTR esp_cache_err_get_cpuid()
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{
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const uint32_t pro_mask =
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DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 |
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DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 |
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DPORT_PRO_CPU_DISABLED_CACHE_IA_IROM0 |
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DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM0 |
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DPORT_PRO_CPU_DISABLED_CACHE_IA_IRAM1 |
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DPORT_APP_CPU_DISABLED_CACHE_IA_OPPOSITE;
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if (DPORT_GET_PERI_REG_MASK(DPORT_PRO_DCACHE_DBUG3_REG, pro_mask)) {
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return PRO_CPU_NUM;
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}
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const uint32_t app_mask =
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DPORT_APP_CPU_DISABLED_CACHE_IA_DRAM1 |
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DPORT_APP_CPU_DISABLED_CACHE_IA_DROM0 |
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DPORT_APP_CPU_DISABLED_CACHE_IA_IROM0 |
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DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM0 |
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DPORT_APP_CPU_DISABLED_CACHE_IA_IRAM1 |
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DPORT_PRO_CPU_DISABLED_CACHE_IA_OPPOSITE;
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if (DPORT_GET_PERI_REG_MASK(DPORT_APP_DCACHE_DBUG3_REG, app_mask)) {
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return APP_CPU_NUM;
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}
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return -1;
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}
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