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167 lines
6.4 KiB
C
167 lines
6.4 KiB
C
// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/* Unit tests need to have access to reliable timestamps even if CPU and APB
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* clock frequencies change over time. This reference clock is built upon two
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* peripherals: one RMT channel and one PCNT channel, plus one GPIO to connect
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* these peripherals.
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*
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* RMT channel is configured to use REF_TICK as clock source, which is a 1 MHz
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* clock derived from APB_CLK using a set of dividers. The divider is changed
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* automatically by hardware depending on the current clock source of APB_CLK.
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* For example, if APB_CLK is derived from PLL, one divider is used, and when
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* APB_CLK is derived from XTAL, another divider is used. RMT channel clocked
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* by REF_TICK is configured to generate a continuous 0.5 MHz signal, which is
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* connected to a GPIO. PCNT takes the input signal from this GPIO and counts
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* the edges (which occur at 1MHz frequency). PCNT counter is only 16 bit wide,
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* so an interrupt is configured to trigger when the counter reaches 30000,
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* incrementing a 32-bit millisecond counter maintained by software.
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* Together these two counters may be used at any time to obtain the timestamp.
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*/
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#include "test_utils.h"
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#include "soc/rmt_periph.h"
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#include "soc/pcnt_periph.h"
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#include "soc/gpio_periph.h"
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#include "soc/dport_reg.h"
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#include "esp_intr_alloc.h"
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#include "freertos/FreeRTOS.h"
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#include "driver/periph_ctrl.h"
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/* Select which RMT and PCNT channels, and GPIO to use */
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#define REF_CLOCK_RMT_CHANNEL 7
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#define REF_CLOCK_PCNT_UNIT 0
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#define REF_CLOCK_GPIO 21
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#define REF_CLOCK_PRESCALER_MS 30
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static void IRAM_ATTR pcnt_isr(void* arg);
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static intr_handle_t s_intr_handle;
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static portMUX_TYPE s_lock = portMUX_INITIALIZER_UNLOCKED;
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static volatile uint32_t s_milliseconds;
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void ref_clock_init()
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{
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assert(s_intr_handle == NULL && "already initialized");
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// Route RMT output to GPIO matrix
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gpio_matrix_out(REF_CLOCK_GPIO, RMT_SIG_OUT0_IDX + REF_CLOCK_RMT_CHANNEL, false, false);
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// Initialize RMT
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periph_module_enable(PERIPH_RMT_MODULE);
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RMT.apb_conf.fifo_mask = 1;
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rmt_item32_t data = {
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.duration0 = 1,
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.level0 = 1,
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.duration1 = 0,
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.level1 = 0
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};
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RMTMEM.chan[REF_CLOCK_RMT_CHANNEL].data32[0] = data;
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RMTMEM.chan[REF_CLOCK_RMT_CHANNEL].data32[1].val = 0;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.clk_en = 1;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.tx_start = 0;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.mem_owner = 0;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.mem_rd_rst = 1;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.apb_mem_rst = 1;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.carrier_en = 0;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.div_cnt = 1;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.mem_size = 1;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.ref_always_on = 0;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.tx_conti_mode = 1;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.tx_start = 1;
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// Route signal to PCNT
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int pcnt_sig_idx = (REF_CLOCK_PCNT_UNIT < 5) ?
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PCNT_SIG_CH0_IN0_IDX + 4 * REF_CLOCK_PCNT_UNIT :
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PCNT_SIG_CH0_IN5_IDX + 4 * (REF_CLOCK_PCNT_UNIT - 5);
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gpio_matrix_in(REF_CLOCK_GPIO, pcnt_sig_idx, false);
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if (REF_CLOCK_GPIO != 20) {
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PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[REF_CLOCK_GPIO]);
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} else {
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PIN_INPUT_ENABLE(PERIPHS_IO_MUX_GPIO20_U);
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}
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// Initialize PCNT
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periph_module_enable(PERIPH_PCNT_MODULE);
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.ch0_hctrl_mode = 0;
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.ch0_lctrl_mode = 0;
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.ch0_pos_mode = 1;
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.ch0_neg_mode = 1;
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_l_lim_en = 0;
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_h_lim_en = 1;
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_zero_en = 0;
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_thres0_en = 0;
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_thres1_en = 0;
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PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf2.cnt_h_lim = REF_CLOCK_PRESCALER_MS * 1000;
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// Enable PCNT and wait for it to start counting
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PCNT.ctrl.val &= ~(BIT(REF_CLOCK_PCNT_UNIT * 2 + 1));
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PCNT.ctrl.val |= BIT(REF_CLOCK_PCNT_UNIT * 2);
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PCNT.ctrl.val &= ~BIT(REF_CLOCK_PCNT_UNIT * 2);
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ets_delay_us(10000);
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// Enable interrupt
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s_milliseconds = 0;
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_PCNT_INTR_SOURCE, ESP_INTR_FLAG_IRAM, pcnt_isr, NULL, &s_intr_handle));
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PCNT.int_clr.val = BIT(REF_CLOCK_PCNT_UNIT);
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PCNT.int_ena.val = BIT(REF_CLOCK_PCNT_UNIT);
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}
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static void IRAM_ATTR pcnt_isr(void* arg)
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{
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portENTER_CRITICAL_ISR(&s_lock);
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PCNT.int_clr.val = BIT(REF_CLOCK_PCNT_UNIT);
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s_milliseconds += REF_CLOCK_PRESCALER_MS;
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portEXIT_CRITICAL_ISR(&s_lock);
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}
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void ref_clock_deinit()
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{
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assert(s_intr_handle && "deinit called without init");
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// Disable interrupt
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PCNT.int_ena.val &= ~BIT(REF_CLOCK_PCNT_UNIT);
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esp_intr_free(s_intr_handle);
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s_intr_handle = NULL;
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// Disable RMT
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.tx_start = 0;
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RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.clk_en = 0;
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periph_module_disable(PERIPH_RMT_MODULE);
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// Disable PCNT
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PCNT.ctrl.val |= ~(BIT(REF_CLOCK_PCNT_UNIT * 2 + 1));
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periph_module_disable(PERIPH_PCNT_MODULE);
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}
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uint64_t ref_clock_get()
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{
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portENTER_CRITICAL(&s_lock);
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uint32_t microseconds = PCNT.cnt_unit[REF_CLOCK_PCNT_UNIT].cnt_val;
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uint32_t milliseconds = s_milliseconds;
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if (PCNT.int_st.val & BIT(REF_CLOCK_PCNT_UNIT)) {
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// refresh counter value, in case the overflow has happened after reading cnt_val
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microseconds = PCNT.cnt_unit[REF_CLOCK_PCNT_UNIT].cnt_val;
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milliseconds += REF_CLOCK_PRESCALER_MS;
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}
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portEXIT_CRITICAL(&s_lock);
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return 1000 * (uint64_t) milliseconds + (uint64_t) microseconds;
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}
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