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515 lines
16 KiB
C
515 lines
16 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include <sys/param.h> // For MIN/MAX
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#include "spi_flash_chip_generic.h"
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#include "spi_flash_defs.h"
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#include "esp_log.h"
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static const char TAG[] = "chip_generic";
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#define SPI_FLASH_GENERIC_CHIP_ERASE_TIMEOUT 4000
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#define SPI_FLASH_GENERIC_SECTOR_ERASE_TIMEOUT 500 //according to GD25Q127 + 100ms
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#define SPI_FLASH_GENERIC_BLOCK_ERASE_TIMEOUT 1300 //according to GD25Q127 + 100ms
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#define DEFAULT_IDLE_TIMEOUT 200
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#define DEFAULT_PAGE_PROGRAM_TIMEOUT 500
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esp_err_t spi_flash_chip_generic_probe(esp_flash_t *chip, uint32_t flash_id)
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{
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// This is the catch-all probe function, claim the chip always if nothing
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// else has claimed it yet.
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return ESP_OK;
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}
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esp_err_t spi_flash_chip_generic_reset(esp_flash_t *chip)
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{
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//this is written following the winbond spec..
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spi_flash_trans_t t;
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t = (spi_flash_trans_t) {
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.command = CMD_RST_EN,
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};
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esp_err_t err = chip->host->common_command(chip->host, &t);
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if (err != ESP_OK) {
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return err;
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}
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t = (spi_flash_trans_t) {
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.command = CMD_RST_DEV,
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};
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err = chip->host->common_command(chip->host, &t);
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if (err != ESP_OK) {
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return err;
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}
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err = chip->chip_drv->wait_idle(chip, DEFAULT_IDLE_TIMEOUT);
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return err;
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}
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esp_err_t spi_flash_chip_generic_detect_size(esp_flash_t *chip, uint32_t *size)
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{
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uint32_t id = chip->chip_id;
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*size = 0;
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/* Can't detect size unless the high byte of the product ID matches the same convention, which is usually 0x40 or
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* 0xC0 or similar. */
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if ((id & 0x0F00) != 0) {
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return ESP_ERR_FLASH_UNSUPPORTED_CHIP;
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}
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*size = 1 << (id & 0xFF);
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return ESP_OK;
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}
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esp_err_t spi_flash_chip_generic_erase_chip(esp_flash_t *chip)
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{
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esp_err_t err;
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err = chip->chip_drv->set_chip_write_protect(chip, false);
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if (err == ESP_OK) {
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err = chip->chip_drv->wait_idle(chip, DEFAULT_IDLE_TIMEOUT);
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}
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if (err == ESP_OK) {
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chip->host->erase_chip(chip->host);
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//to save time, flush cache here
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if (chip->host->flush_cache) {
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err = chip->host->flush_cache(chip->host, 0, chip->size);
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if (err != ESP_OK) {
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return err;
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}
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}
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err = chip->chip_drv->wait_idle(chip, SPI_FLASH_GENERIC_CHIP_ERASE_TIMEOUT);
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}
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return err;
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}
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esp_err_t spi_flash_chip_generic_erase_sector(esp_flash_t *chip, uint32_t start_address)
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{
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esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
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if (err == ESP_OK) {
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err = chip->chip_drv->wait_idle(chip, DEFAULT_IDLE_TIMEOUT);
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}
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if (err == ESP_OK) {
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chip->host->erase_sector(chip->host, start_address);
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//to save time, flush cache here
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if (chip->host->flush_cache) {
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err = chip->host->flush_cache(chip->host, start_address, chip->chip_drv->sector_size);
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if (err != ESP_OK) {
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return err;
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}
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}
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err = chip->chip_drv->wait_idle(chip, SPI_FLASH_GENERIC_SECTOR_ERASE_TIMEOUT);
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}
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return err;
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}
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esp_err_t spi_flash_chip_generic_erase_block(esp_flash_t *chip, uint32_t start_address)
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{
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esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false);
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if (err == ESP_OK) {
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err = chip->chip_drv->wait_idle(chip, DEFAULT_IDLE_TIMEOUT);
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}
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if (err == ESP_OK) {
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chip->host->erase_block(chip->host, start_address);
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//to save time, flush cache here
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if (chip->host->flush_cache) {
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err = chip->host->flush_cache(chip->host, start_address, chip->chip_drv->block_erase_size);
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if (err != ESP_OK) {
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return err;
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}
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}
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err = chip->chip_drv->wait_idle(chip, SPI_FLASH_GENERIC_BLOCK_ERASE_TIMEOUT);
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}
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return err;
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}
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esp_err_t spi_flash_chip_generic_read(esp_flash_t *chip, void *buffer, uint32_t address, uint32_t length)
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{
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esp_err_t err = ESP_OK;
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// Configure the host, and return
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err = spi_flash_chip_generic_config_host_io_mode(chip);
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if (err == ESP_ERR_NOT_SUPPORTED) {
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ESP_LOGE(TAG, "configure host io mode failed - unsupported");
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return err;
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}
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while (err == ESP_OK && length > 0) {
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uint32_t read_len = MIN(length, chip->host->max_read_bytes);
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err = chip->host->read(chip->host, buffer, address, read_len);
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buffer += read_len;
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length -= read_len;
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address += read_len;
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}
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return err;
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}
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esp_err_t spi_flash_chip_generic_page_program(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
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{
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esp_err_t err;
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err = chip->chip_drv->wait_idle(chip, DEFAULT_IDLE_TIMEOUT);
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if (err == ESP_OK) {
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// Perform the actual Page Program command
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chip->host->program_page(chip->host, buffer, address, length);
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err = chip->chip_drv->wait_idle(chip, DEFAULT_PAGE_PROGRAM_TIMEOUT);
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}
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return err;
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}
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esp_err_t spi_flash_chip_generic_write(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
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{
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esp_err_t err = ESP_OK;
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const uint32_t page_size = chip->chip_drv->page_size;
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while (err == ESP_OK && length > 0) {
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uint32_t page_len = MIN(chip->host->max_write_bytes, MIN(page_size, length));
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if ((address + page_len) / page_size != address / page_size) {
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// Most flash chips can't page write across a page boundary
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page_len = page_size - (address % page_size);
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}
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err = chip->chip_drv->set_chip_write_protect(chip, false);
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if (err == ESP_OK) {
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err = chip->chip_drv->program_page(chip, buffer, address, page_len);
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address += page_len;
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buffer = (void *)((intptr_t)buffer + page_len);
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length -= page_len;
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}
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}
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if (err == ESP_OK && chip->host->flush_cache) {
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err = chip->host->flush_cache(chip->host, address, length);
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}
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return err;
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}
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esp_err_t spi_flash_chip_generic_write_encrypted(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length)
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{
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return ESP_ERR_FLASH_UNSUPPORTED_HOST; // TODO
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}
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esp_err_t spi_flash_chip_generic_set_write_protect(esp_flash_t *chip, bool write_protect)
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{
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esp_err_t err = ESP_OK;
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err = chip->chip_drv->wait_idle(chip, DEFAULT_IDLE_TIMEOUT);
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if (err == ESP_OK) {
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chip->host->set_write_protect(chip->host, write_protect);
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}
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bool wp_read;
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err = chip->chip_drv->get_chip_write_protect(chip, &wp_read);
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if (err == ESP_OK && wp_read != write_protect) {
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// WREN flag has not been set!
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err = ESP_ERR_NOT_FOUND;
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}
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return err;
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}
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esp_err_t spi_flash_chip_generic_get_write_protect(esp_flash_t *chip, bool *out_write_protect)
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{
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esp_err_t err = ESP_OK;
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uint8_t status;
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assert(out_write_protect!=NULL);
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err = chip->host->read_status(chip->host, &status);
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if (err != ESP_OK) {
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return err;
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}
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*out_write_protect = ((status & SR_WREN) == 0);
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return err;
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}
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esp_err_t spi_flash_generic_wait_host_idle(esp_flash_t *chip, uint32_t *timeout_ms)
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{
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while (chip->host->host_idle(chip->host) && *timeout_ms > 0) {
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if (*timeout_ms > 1) {
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chip->os_func->delay_ms(chip->os_func_data, 1);
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}
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(*timeout_ms)--;
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}
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return (*timeout_ms > 0) ? ESP_OK : ESP_ERR_TIMEOUT;
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}
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esp_err_t spi_flash_chip_generic_wait_idle(esp_flash_t *chip, uint32_t timeout_ms)
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{
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timeout_ms++; // allow at least one pass before timeout, last one has no sleep cycle
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uint8_t status = 0;
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while (timeout_ms > 0) {
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esp_err_t err = spi_flash_generic_wait_host_idle(chip, &timeout_ms);
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if (err != ESP_OK) {
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return err;
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}
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err = chip->host->read_status(chip->host, &status);
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if (err != ESP_OK) {
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return err;
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}
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if ((status & SR_WIP) == 0) {
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break; // Write in progress is complete
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}
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if (timeout_ms > 1) {
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chip->os_func->delay_ms(chip->os_func_data, 1);
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}
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timeout_ms--;
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}
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return (timeout_ms > 0) ? ESP_OK : ESP_ERR_TIMEOUT;
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}
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esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip)
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{
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uint32_t dummy_cyclelen_base;
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uint32_t addr_bitlen;
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uint32_t read_command;
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switch (chip->read_mode) {
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case SPI_FLASH_QIO:
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//for QIO mode, the 4 bit right after the address are used for continuous mode, should be set to 0 to avoid that.
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addr_bitlen = 32;
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dummy_cyclelen_base = 4;
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read_command = CMD_FASTRD_QIO;
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break;
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case SPI_FLASH_QOUT:
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addr_bitlen = 24;
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dummy_cyclelen_base = 8;
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read_command = CMD_FASTRD_QUAD;
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break;
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case SPI_FLASH_DIO:
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//for DIO mode, the 4 bit right after the address are used for continuous mode, should be set to 0 to avoid that.
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addr_bitlen = 28;
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dummy_cyclelen_base = 2;
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read_command = CMD_FASTRD_DIO;
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break;
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case SPI_FLASH_DOUT:
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addr_bitlen = 24;
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dummy_cyclelen_base = 8;
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read_command = CMD_FASTRD_DUAL;
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break;
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case SPI_FLASH_FASTRD:
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addr_bitlen = 24;
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dummy_cyclelen_base = 8;
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read_command = CMD_FASTRD;
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break;
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case SPI_FLASH_SLOWRD:
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addr_bitlen = 24;
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dummy_cyclelen_base = 0;
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read_command = CMD_READ;
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break;
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default:
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return ESP_ERR_FLASH_NOT_INITIALISED;
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}
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return chip->host->configure_host_io_mode(chip->host, read_command, addr_bitlen, dummy_cyclelen_base,
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chip->read_mode);
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}
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esp_err_t spi_flash_chip_generic_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
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{
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// On "generic" chips, this involves checking
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// bit 1 (QE) of RDSR2 (35h) result
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// (it works this way on GigaDevice & Fudan Micro chips, probably others...)
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const uint8_t BIT_QE = 1 << 1;
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uint32_t sr;
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esp_err_t ret = spi_flash_common_read_status_8b_rdsr2(chip, &sr);
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if (ret == ESP_OK) {
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*out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
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}
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return ret;
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}
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esp_err_t spi_flash_chip_generic_set_io_mode(esp_flash_t *chip)
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{
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// On "generic" chips, this involves checking
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// bit 9 (QE) of RDSR (05h) result
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const uint32_t BIT_QE = 1 << 9;
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return spi_flash_common_set_io_mode(chip,
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spi_flash_common_write_status_16b_wrsr,
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spi_flash_common_read_status_16b_rdsr_rdsr2,
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BIT_QE);
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}
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static const char chip_name[] = "generic";
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const spi_flash_chip_t esp_flash_chip_generic = {
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.name = chip_name,
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.probe = spi_flash_chip_generic_probe,
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.reset = spi_flash_chip_generic_reset,
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.detect_size = spi_flash_chip_generic_detect_size,
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.erase_chip = spi_flash_chip_generic_erase_chip,
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.erase_sector = spi_flash_chip_generic_erase_sector,
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.erase_block = spi_flash_chip_generic_erase_block,
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.sector_size = 4 * 1024,
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.block_erase_size = 64 * 1024,
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// TODO: figure out if generic chip-wide protection bits exist across some manufacturers
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.get_chip_write_protect = spi_flash_chip_generic_get_write_protect,
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.set_chip_write_protect = spi_flash_chip_generic_set_write_protect,
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// Chip write protection regions do not appear to be standardised
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// at all, this is implemented in chip-specific drivers only.
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.num_protectable_regions = 0,
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.protectable_regions = NULL,
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.get_protected_regions = NULL,
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.set_protected_regions = NULL,
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.read = spi_flash_chip_generic_read,
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.write = spi_flash_chip_generic_write,
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.program_page = spi_flash_chip_generic_page_program,
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.page_size = 256,
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.write_encrypted = spi_flash_chip_generic_write_encrypted,
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.wait_idle = spi_flash_chip_generic_wait_idle,
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.set_io_mode = spi_flash_chip_generic_set_io_mode,
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.get_io_mode = spi_flash_chip_generic_get_io_mode,
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};
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/*******************************************************************************
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* Utility functions
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******************************************************************************/
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static esp_err_t spi_flash_common_read_qe_sr(esp_flash_t *chip, uint8_t qe_rdsr_command, uint8_t qe_sr_bitwidth, uint32_t *sr)
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{
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uint32_t sr_buf = 0;
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spi_flash_trans_t t = {
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.command = qe_rdsr_command,
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.miso_data = (uint8_t*) &sr_buf,
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.miso_len = qe_sr_bitwidth / 8,
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};
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esp_err_t ret = chip->host->common_command(chip->host, &t);
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*sr = sr_buf;
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return ret;
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}
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static esp_err_t spi_flash_common_write_qe_sr(esp_flash_t *chip, uint8_t qe_wrsr_command, uint8_t qe_sr_bitwidth, uint32_t qe)
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{
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spi_flash_trans_t t = {
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.command = qe_wrsr_command,
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.mosi_data = ((uint8_t*) &qe),
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.mosi_len = qe_sr_bitwidth / 8,
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.miso_len = 0,
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};
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return chip->host->common_command(chip->host, &t);
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}
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esp_err_t spi_flash_common_read_status_16b_rdsr_rdsr2(esp_flash_t* chip, uint32_t* out_sr)
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{
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uint32_t sr, sr2;
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esp_err_t ret = spi_flash_common_read_qe_sr(chip, CMD_RDSR2, 8, &sr2);
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if (ret == ESP_OK) {
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ret = spi_flash_common_read_qe_sr(chip, CMD_RDSR, 8, &sr);
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}
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if (ret == ESP_OK) {
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*out_sr = (sr & 0xff) | ((sr2 & 0xff) << 8);
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}
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return ret;
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}
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esp_err_t spi_flash_common_read_status_8b_rdsr2(esp_flash_t* chip, uint32_t* out_sr)
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{
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return spi_flash_common_read_qe_sr(chip, CMD_RDSR2, 8, out_sr);
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}
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esp_err_t spi_flash_common_read_status_8b_rdsr(esp_flash_t* chip, uint32_t* out_sr)
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{
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return spi_flash_common_read_qe_sr(chip, CMD_RDSR, 8, out_sr);
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}
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esp_err_t spi_flash_common_write_status_16b_wrsr(esp_flash_t* chip, uint32_t sr)
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{
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return spi_flash_common_write_qe_sr(chip, CMD_WRSR, 16, sr);
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}
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esp_err_t spi_flash_common_write_status_8b_wrsr(esp_flash_t* chip, uint32_t sr)
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{
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return spi_flash_common_write_qe_sr(chip, CMD_WRSR, 8, sr);
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}
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esp_err_t spi_flash_common_write_status_8b_wrsr2(esp_flash_t* chip, uint32_t sr)
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{
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return spi_flash_common_write_qe_sr(chip, CMD_WRSR2, 8, sr);
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}
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esp_err_t spi_flash_common_set_io_mode(esp_flash_t *chip, esp_flash_wrsr_func_t wrsr_func, esp_flash_rdsr_func_t rdsr_func, uint32_t qe_sr_bit)
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{
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esp_err_t ret = ESP_OK;
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const bool is_quad_mode = esp_flash_is_quad_mode(chip);
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bool update_config = false;
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const bool force_check = true; //in case some chips doesn't support erase QE
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bool need_check = is_quad_mode;
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if (force_check) {
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need_check = true;
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}
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uint32_t sr_update;
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if (need_check) {
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// Ensure quad modes are enabled, using the Quad Enable parameters supplied.
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uint32_t sr;
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ret = (*rdsr_func)(chip, &sr);
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if (ret != ESP_OK) {
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return ret;
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}
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ESP_EARLY_LOGD(TAG, "set_io_mode: status before 0x%x", sr);
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if (is_quad_mode) {
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sr_update = sr | qe_sr_bit;
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} else {
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sr_update = sr & (~qe_sr_bit);
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}
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ESP_EARLY_LOGV(TAG, "set_io_mode: status update 0x%x", sr_update);
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if (sr != sr_update) {
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update_config = true;
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}
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}
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if (update_config) {
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//some chips needs the write protect to be disabled before writing to Status Register
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chip->chip_drv->set_chip_write_protect(chip, false);
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ret = (*wrsr_func)(chip, sr_update);
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if (ret != ESP_OK) {
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return ret;
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}
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ret = chip->chip_drv->wait_idle(chip, DEFAULT_IDLE_TIMEOUT);
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if (ret != ESP_OK) {
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return ret;
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}
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/* Check the new QE bit has stayed set */
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uint32_t sr;
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ret = (*rdsr_func)(chip, &sr);
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if (ret != ESP_OK) {
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return ret;
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}
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ESP_EARLY_LOGD(TAG, "set_io_mode: status after 0x%x", sr);
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if (sr != sr_update) {
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ret = ESP_ERR_FLASH_NO_RESPONSE;
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}
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chip->chip_drv->set_chip_write_protect(chip, true);
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}
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return ret;
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}
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