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https://github.com/espressif/esp-idf.git
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6e9c59bfc3
1. Add reading psram EID. 2. Configure different clock mode for different EID. 3. add API to get psram size and voltage. 4. Remove unnecessary VSPI claim. For 32MBit@1.8V and 64MBit@3.3V psram, there should be 2 extra clock cycles after CS get high level. For 64MBit@1.8 psram, we can just use standard SPI protocol to drive the psram. We also need to increase the HOLD time for CS in this case. EID for psram: 32MBit 1.8v: 0x20 64MBit 1.8v: 0x26 64MBit 3.3v: 0x46
84 lines
2.5 KiB
C
84 lines
2.5 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _PSRAM_H
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#define _PSRAM_H
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#include "soc/spi_reg.h"
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#include "esp_err.h"
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#include "sdkconfig.h"
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typedef enum {
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PSRAM_CACHE_F80M_S40M = 0,
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PSRAM_CACHE_F40M_S40M,
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PSRAM_CACHE_F80M_S80M,
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PSRAM_CACHE_MAX,
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} psram_cache_mode_t;
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typedef enum {
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PSRAM_VOLT_3V3 = 0,
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PSRAM_VOLT_1V8 = 1,
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PSRAM_VOLT_MAX,
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} psram_volt_t;
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typedef enum {
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PSRAM_SIZE_32MBITS = 0,
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PSRAM_SIZE_64MBITS = 1,
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PSRAM_SIZE_MAX,
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} psram_size_t;
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/*
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See the TRM, chapter PID/MPU/MMU, header 'External RAM' for the definitions of these modes.
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Important is that NORMAL works with the app CPU cache disabled, but gives huge cache coherency
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issues when both app and pro CPU are enabled. LOWHIGH and EVENODD do not have these coherency
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issues but cannot be used when the app CPU cache is disabled.
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*/
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typedef enum {
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PSRAM_VADDR_MODE_NORMAL=0, ///< App and pro CPU use their own flash cache for external RAM access
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PSRAM_VADDR_MODE_LOWHIGH, ///< App and pro CPU share external RAM caches: pro CPU has low 2M, app CPU has high 2M
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PSRAM_VADDR_MODE_EVENODD, ///< App and pro CPU share external RAM caches: pro CPU does even 32yte ranges, app does odd ones.
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} psram_vaddr_mode_t;
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/**
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* @brief get psram voltage
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* @return
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* - PSRAM_VOLT_MAX if psram not enabled or not valid.
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* - PSRAM voltage
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*/
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psram_volt_t psram_get_volt();
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/**
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* @brief get psram size
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* @return
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* - PSRAM_SIZE_MAX if psram not enabled or not valid
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* - PSRAM size
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*/
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psram_size_t psram_get_size();
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/**
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* @brief psram cache enable function
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*
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* Esp-idf uses this to initialize cache for psram, mapping it into the main memory
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* address space.
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*
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* @param mode SPI mode to access psram in
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* @param vaddrmode Mode the psram cache works in.
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* @return ESP_OK on success, ESP_ERR_INVALID_STATE when VSPI peripheral is needed but cannot be claimed.
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*/
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esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode);
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#endif
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